commit 92905c647fce1869342022dcee6a60703876941b Author: John-Mark Gurney Date: Sun Mar 22 22:23:23 2020 -0700 add first test getting techmap working.. workings fine w/ yosys 0.9 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..dbdd6a2 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +p +synth.* diff --git a/NOTES.md b/NOTES.md new file mode 100644 index 0000000..3e47e2c --- /dev/null +++ b/NOTES.md @@ -0,0 +1,11 @@ +has half and full adder: +yosys/tests/liberty/normal.lib + +https://people.eecs.berkeley.edu/~alanmi/publications/other/liberty13_03.pdf + +use techmap to use the functions + +blueprint with max pack combiners around small poll (maybe do other ones for substation and medium poll?) + +has three other max spaced polls for reference, and a large one off to the side also for reference also has a few functions programed for reference. +0eNrFmFGPlDAQx7/LPBo427KAx9vp6aMmJuqpMRvYrXdNgJJSNm42/e627OZWWfDsROFpA+38++9vmZnCAYqy440StYbsAGIj6xayrwdoxX2dl+6e3jccMhCaVxBAnVfuKldCP1Rci024kVUh6lxLBSYAUW/5D8io+RYAr7XQgh8F+4v9uu6qgis74VGqrfKyDHnJN1pZuUaW3K7TyNbGyto5sHokgD1kYWJMcCHF/KTSP0hFT2zwQixkV/FRj9rNb4WyS/ej1pRlqZUs1wV/yHfCRtuQs+zaDm97qdYNfBeq1esL6juhdGfvnLfYzwiJY91yp/H3QV9ckGy4yo8e4ZmdIjvddB4r34AxY+hW3ujoCdxV/Du6lSe6Ewb36OrcPcdkuMtRw7Gv4YX9Jr5+ybJ+U1+/bFm/L9C5T2ZNfYpJ/c/D1H+OSP2XE6l/jSY3b9FkGHJ3Q3IhgtyrCXKUIKsm6ZPkf8KKMbA+DGHdvXuPwPVmChfF1eylSgpl3jX735QUrN8Icyqjo1Le5wG27NZjrF+6jN8Ec+od/6tSdP2OZq3fK0xJ+jgsSaiK9HqqIuFPDWxWdhGG3achu5u3twh4t1Pw/A8OZBxeMk/SMWy7jvzbNdYiskXO6JDhXmRmdBhhewFbpBewFe5Va0ai5+5aiPunelUYn3DaX+M+JPXfnrJfPlUFsOOq7SPSiNDrhNEoTYz5Ca/3hLU= diff --git a/cmds.txt b/cmds.txt new file mode 100644 index 0000000..ec5defa --- /dev/null +++ b/cmds.txt @@ -0,0 +1,3 @@ +ls * | ~/src/eradman-entr-c15b0be493fc/entr sh -c '~/github/yosys/yosys -s script.ys' + +python -c 'import sys; import pprint; import json; import zlib; pprint.pprint(json.loads(zlib.decompress(sys.stdin.read()[1:].decode("base64"))))' diff --git a/factorsynio.lib b/factorsynio.lib new file mode 100644 index 0000000..be41a72 --- /dev/null +++ b/factorsynio.lib @@ -0,0 +1,99 @@ +// test comment +/* test comment */ +library(demo) { + type (bus4) { + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + cell(BUF) { + area: 2; + pin(A) { direction: input; } + pin(Y) { direction: output; + function: "A"; } + } + cell(NOT) { + area: 2; + pin(A) { direction: input; } + pin(Y) { direction: output; + function: "A'"; } + } + cell(XOR) { + area: 100; + pin(A) { direction: input; } + pin(B) { direction: input; } + pin(Y) { direction: output; + function: "(A^B)"; } + } + // not used, see -g option of abc http://www.clifford.at/yosys/cmd_abc.html + cell(XORDUAL) { + area: 2; + pin(A) { direction: input; } + pin(B) { direction: input; } + pin(C) { direction: input; } + pin(D) { direction: input; } + pin(Y) { direction: output; + function: "(A^B)"; } + pin(Z) { direction: output; + function: "(C^D)"; } + } + cell(XOR2) { + area: 2; + bus(I1) { + bus_type : bus4; + direction : input; + } + bus(I2) { + bus_type : bus4; + direction : input; + } + bus(Y) { + bus_type : bus4; + direction : output; + pin (Y[0:3]) { + function: "(I1^I2)"; + } + } + } + cell(NAND) { + area: 2; + pin(A) { direction: input; } + pin(B) { direction: input; } + pin(Y) { direction: output; + function: "(A*B)'"; } + } + cell(NOR) { + area: 2; + pin(A) { direction: input; } + pin(B) { direction: input; } + pin(Y) { direction: output; + function: "(A+B)'"; } + } + cell(DFF) { + area: 2; + ff(IQ, IQN) { clocked_on: C; + next_state: D; } + pin(C) { direction: input; + clock: true; } + pin(D) { direction: input; } + pin(Q) { direction: output; + function: "IQ"; } + } + cell(DFFSR) { + area: 2; + ff("IQ", "IQN") { clocked_on: C; + next_state: D; + preset: S; + clear: R; } + pin(C) { direction: input; + clock: true; } + pin(D) { direction: input; } + pin(Q) { direction: output; + function: "IQ"; } + pin(S) { direction: input; } + pin(R) { direction: input; } + ; // empty statement + } +} diff --git a/factorsyniomap.v b/factorsyniomap.v new file mode 100644 index 0000000..8d98346 --- /dev/null +++ b/factorsyniomap.v @@ -0,0 +1,29 @@ +(* techmap_cellteype = "$mul" *) +module $mul(A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 4; +parameter B_WIDTH = 4; +parameter Y_WIDTH = 4; + +input [A_WIDTH-1:0] A; +input [B_WIDTH-1:0] B; +output [Y_WIDTH-1:0] Y; + + +foobar #( + .A_SIGNED(B_SIGNED), + .B_SIGNED(A_SIGNED), + .A_WIDTH(B_WIDTH), + .B_WIDTH(A_WIDTH), + .Y_WIDTH(Y_WIDTH) +) _TECHMAP_REPLACE_.baz ( + .A(B), + .B(A), + .Y(Y) +); + wire [1023:0] _TECHMAP_DO_00 = "log fklj;;"; + wire _TECHMAP_FAIL_ = 0; + +endmodule diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 0000000..e69de29 diff --git a/script.ys b/script.ys new file mode 100644 index 0000000..3e9146f --- /dev/null +++ b/script.ys @@ -0,0 +1,33 @@ +# read design +read_verilog testmod.v + +# from pdf docs, page 26 +proc +opt +memory +opt +#techmap +techmap -map factorsyniomap.v +opt +dfflibmap -liberty factorsynio.lib +abc -liberty factorsynio.lib + +opt + +##### from sample some where +# generic synthesis +#synth -top top #-noalumacc + +#techmap -map factorsyniomap.v + +# mapping to mycells.lib +#dfflibmap -liberty ../../git/factorsynio/factorsynio.lib +#abc -liberty ../../git/factorsynio/factorsynio.lib +#abc + +#clean + +# write synthesized design +write_verilog synth.v +write_ilang synth.ilang +write_json synth.json diff --git a/testmod.v b/testmod.v new file mode 100644 index 0000000..784d80a --- /dev/null +++ b/testmod.v @@ -0,0 +1,5 @@ +module top (output reg [3:0] out, input clk, input [3:0] a, input [3:0] b, input [3:0] c); + always @(posedge clk) begin + out <= (a * b) + c + (10 + 12); + end +endmodule