A set a scripts to take a design in Verilog and convert it to a factorio blueprint.
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has half and full adder: yosys/tests/liberty/normal.lib

https://people.eecs.berkeley.edu/~alanmi/publications/other/liberty13_03.pdf

use techmap to use the functions

blueprint with max pack combiners around small poll (maybe do other ones for substation and medium poll?)

has three other max spaced polls for reference, and a large one off to the side also for reference also has a few functions programed for reference. 0eNrFmFGPlDAQx7/LPBo427KAx9vp6aMmJuqpMRvYrXdNgJJSNm42/e627OZWWfDsROFpA+38++9vmZnCAYqy440StYbsAGIj6xayrwdoxX2dl+6e3jccMhCaVxBAnVfuKldCP1Rci024kVUh6lxLBSYAUW/5D8io+RYAr7XQgh8F+4v9uu6qgis74VGqrfKyDHnJN1pZuUaW3K7TyNbGyto5sHokgD1kYWJMcCHF/KTSP0hFT2zwQixkV/FRj9rNb4WyS/ej1pRlqZUs1wV/yHfCRtuQs+zaDm97qdYNfBeq1esL6juhdGfvnLfYzwiJY91yp/H3QV9ckGy4yo8e4ZmdIjvddB4r34AxY+hW3ujoCdxV/Du6lSe6Ewb36OrcPcdkuMtRw7Gv4YX9Jr5+ybJ+U1+/bFm/L9C5T2ZNfYpJ/c/D1H+OSP2XE6l/jSY3b9FkGHJ3Q3IhgtyrCXKUIKsm6ZPkf8KKMbA+DGHdvXuPwPVmChfF1eylSgpl3jX735QUrN8Icyqjo1Le5wG27NZjrF+6jN8Ec+od/6tSdP2OZq3fK0xJ+jgsSaiK9HqqIuFPDWxWdhGG3achu5u3twh4t1Pw/A8OZBxeMk/SMWy7jvzbNdYiskXO6JDhXmRmdBhhewFbpBewFe5Va0ai5+5aiPunelUYn3DaX+M+JPXfnrJfPlUFsOOq7SPSiNDrhNEoTYz5Ca/3hLU=