A set a scripts to take a design in Verilog and convert it to a factorio blueprint.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 

6 lines
169 B

  1. module top (output reg [3:0] out, input clk, input [3:0] a, input [3:0] b, input [3:0] c);
  2. always @(posedge clk) begin
  3. out <= (a * b) + c + (10 + 12);
  4. end
  5. endmodule