A set a scripts to take a design in Verilog and convert it to a factorio blueprint.
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John-Mark Gurney 92905c647f add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад
.gitignore add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад
NOTES.md add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад
cmds.txt add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад
factorsynio.lib add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад
factorsyniomap.v add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад
requirements.txt add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад
script.ys add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад
testmod.v add first test getting techmap working.. workings fine w/ yosys 0.9 7 месяцев назад