Implement a secure ICS protocol targeting LoRa Node151 microcontroller for controlling irrigation.
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  1. /*
  2. / _____) _ | |
  3. ( (____ _____ ____ _| |_ _____ ____| |__
  4. \____ \| ___ | (_ _) ___ |/ ___) _ \
  5. _____) ) ____| | | || |_| ____( (___| | | |
  6. (______/|_____)_|_|_| \__)_____)\____)_| |_|
  7. (C) 2014 Semtech
  8. Description: Actual implementation of a SX1276 radio, inherits Radio
  9. License: Revised BSD License, see LICENSE.TXT file include in the project
  10. Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  11. */
  12. #include "sx1276.h"
  13. const FskBandwidth_t SX1276::FskBandwidths[] =
  14. {
  15. { 2600 , 0x17 },
  16. { 3100 , 0x0F },
  17. { 3900 , 0x07 },
  18. { 5200 , 0x16 },
  19. { 6300 , 0x0E },
  20. { 7800 , 0x06 },
  21. { 10400 , 0x15 },
  22. { 12500 , 0x0D },
  23. { 15600 , 0x05 },
  24. { 20800 , 0x14 },
  25. { 25000 , 0x0C },
  26. { 31300 , 0x04 },
  27. { 41700 , 0x13 },
  28. { 50000 , 0x0B },
  29. { 62500 , 0x03 },
  30. { 83333 , 0x12 },
  31. { 100000, 0x0A },
  32. { 125000, 0x02 },
  33. { 166700, 0x11 },
  34. { 200000, 0x09 },
  35. { 250000, 0x01 },
  36. { 300000, 0x00 }, // Invalid Bandwidth
  37. };
  38. SX1276::SX1276( RadioEvents_t *events,
  39. PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
  40. PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
  41. : Radio( events ),
  42. spi( mosi, miso, sclk ),
  43. nss( nss ),
  44. reset( reset ),
  45. dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
  46. isRadioActive( false )
  47. {
  48. wait_ms( 10 );
  49. this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
  50. this->RadioEvents = events;
  51. this->dioIrq = new DioIrqHandler[6];
  52. this->dioIrq[0] = &SX1276::OnDio0Irq;
  53. this->dioIrq[1] = &SX1276::OnDio1Irq;
  54. this->dioIrq[2] = &SX1276::OnDio2Irq;
  55. this->dioIrq[3] = &SX1276::OnDio3Irq;
  56. this->dioIrq[4] = &SX1276::OnDio4Irq;
  57. this->dioIrq[5] = NULL;
  58. this->settings.State = RF_IDLE;
  59. }
  60. SX1276::~SX1276( )
  61. {
  62. delete this->rxtxBuffer;
  63. delete this->dioIrq;
  64. }
  65. void SX1276::Init( RadioEvents_t *events )
  66. {
  67. this->RadioEvents = events;
  68. }
  69. RadioState SX1276::GetStatus( void )
  70. {
  71. return this->settings.State;
  72. }
  73. void SX1276::SetChannel( uint32_t freq )
  74. {
  75. this->settings.Channel = freq;
  76. freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
  77. Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
  78. Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
  79. Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
  80. }
  81. bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
  82. {
  83. int16_t rssi = 0;
  84. SetModem( modem );
  85. SetChannel( freq );
  86. SetOpMode( RF_OPMODE_RECEIVER );
  87. wait_ms( 1 );
  88. rssi = GetRssi( modem );
  89. Sleep( );
  90. if( rssi > rssiThresh )
  91. {
  92. return false;
  93. }
  94. return true;
  95. }
  96. uint32_t SX1276::Random( void )
  97. {
  98. uint8_t i;
  99. uint32_t rnd = 0;
  100. /*
  101. * Radio setup for random number generation
  102. */
  103. // Set LoRa modem ON
  104. SetModem( MODEM_LORA );
  105. // Disable LoRa modem interrupts
  106. Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
  107. RFLR_IRQFLAGS_RXDONE |
  108. RFLR_IRQFLAGS_PAYLOADCRCERROR |
  109. RFLR_IRQFLAGS_VALIDHEADER |
  110. RFLR_IRQFLAGS_TXDONE |
  111. RFLR_IRQFLAGS_CADDONE |
  112. RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  113. RFLR_IRQFLAGS_CADDETECTED );
  114. // Set radio in continuous reception
  115. SetOpMode( RF_OPMODE_RECEIVER );
  116. for( i = 0; i < 32; i++ )
  117. {
  118. wait_ms( 1 );
  119. // Unfiltered RSSI value reading. Only takes the LSB value
  120. rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
  121. }
  122. Sleep( );
  123. return rnd;
  124. }
  125. /*!
  126. * Performs the Rx chain calibration for LF and HF bands
  127. * \remark Must be called just after the reset so all registers are at their
  128. * default values
  129. */
  130. void SX1276::RxChainCalibration( void )
  131. {
  132. uint8_t regPaConfigInitVal;
  133. uint32_t initialFreq;
  134. // Save context
  135. regPaConfigInitVal = this->Read( REG_PACONFIG );
  136. initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
  137. ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
  138. ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
  139. // Cut the PA just in case, RFO output, power = -1 dBm
  140. this->Write( REG_PACONFIG, 0x00 );
  141. // Launch Rx chain calibration for LF band
  142. Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
  143. while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
  144. {
  145. }
  146. // Sets a Frequency in HF band
  147. SetChannel( 868000000 );
  148. // Launch Rx chain calibration for HF band
  149. Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
  150. while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
  151. {
  152. }
  153. // Restore context
  154. this->Write( REG_PACONFIG, regPaConfigInitVal );
  155. SetChannel( initialFreq );
  156. }
  157. /*!
  158. * Returns the known FSK bandwidth registers value
  159. *
  160. * \param [IN] bandwidth Bandwidth value in Hz
  161. * \retval regValue Bandwidth register value.
  162. */
  163. uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
  164. {
  165. uint8_t i;
  166. for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
  167. {
  168. if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
  169. {
  170. return FskBandwidths[i].RegValue;
  171. }
  172. }
  173. // ERROR: Value not found
  174. while( 1 );
  175. }
  176. void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
  177. uint32_t datarate, uint8_t coderate,
  178. uint32_t bandwidthAfc, uint16_t preambleLen,
  179. uint16_t symbTimeout, bool fixLen,
  180. uint8_t payloadLen,
  181. bool crcOn, bool freqHopOn, uint8_t hopPeriod,
  182. bool iqInverted, bool rxContinuous )
  183. {
  184. SetModem( modem );
  185. switch( modem )
  186. {
  187. case MODEM_FSK:
  188. {
  189. this->settings.Fsk.Bandwidth = bandwidth;
  190. this->settings.Fsk.Datarate = datarate;
  191. this->settings.Fsk.BandwidthAfc = bandwidthAfc;
  192. this->settings.Fsk.FixLen = fixLen;
  193. this->settings.Fsk.PayloadLen = payloadLen;
  194. this->settings.Fsk.CrcOn = crcOn;
  195. this->settings.Fsk.IqInverted = iqInverted;
  196. this->settings.Fsk.RxContinuous = rxContinuous;
  197. this->settings.Fsk.PreambleLen = preambleLen;
  198. this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
  199. datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
  200. Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
  201. Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
  202. Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
  203. Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
  204. Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
  205. Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
  206. if( fixLen == 1 )
  207. {
  208. Write( REG_PAYLOADLENGTH, payloadLen );
  209. }
  210. else
  211. {
  212. Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
  213. }
  214. Write( REG_PACKETCONFIG1,
  215. ( Read( REG_PACKETCONFIG1 ) &
  216. RF_PACKETCONFIG1_CRC_MASK &
  217. RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
  218. ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
  219. ( crcOn << 4 ) );
  220. Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
  221. }
  222. break;
  223. case MODEM_LORA:
  224. {
  225. if( bandwidth > 2 )
  226. {
  227. // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
  228. while( 1 );
  229. }
  230. bandwidth += 7;
  231. this->settings.LoRa.Bandwidth = bandwidth;
  232. this->settings.LoRa.Datarate = datarate;
  233. this->settings.LoRa.Coderate = coderate;
  234. this->settings.LoRa.PreambleLen = preambleLen;
  235. this->settings.LoRa.FixLen = fixLen;
  236. this->settings.LoRa.PayloadLen = payloadLen;
  237. this->settings.LoRa.CrcOn = crcOn;
  238. this->settings.LoRa.FreqHopOn = freqHopOn;
  239. this->settings.LoRa.HopPeriod = hopPeriod;
  240. this->settings.LoRa.IqInverted = iqInverted;
  241. this->settings.LoRa.RxContinuous = rxContinuous;
  242. if( datarate > 12 )
  243. {
  244. datarate = 12;
  245. }
  246. else if( datarate < 6 )
  247. {
  248. datarate = 6;
  249. }
  250. if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
  251. ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
  252. {
  253. this->settings.LoRa.LowDatarateOptimize = 0x01;
  254. }
  255. else
  256. {
  257. this->settings.LoRa.LowDatarateOptimize = 0x00;
  258. }
  259. Write( REG_LR_MODEMCONFIG1,
  260. ( Read( REG_LR_MODEMCONFIG1 ) &
  261. RFLR_MODEMCONFIG1_BW_MASK &
  262. RFLR_MODEMCONFIG1_CODINGRATE_MASK &
  263. RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
  264. ( bandwidth << 4 ) | ( coderate << 1 ) |
  265. fixLen );
  266. Write( REG_LR_MODEMCONFIG2,
  267. ( Read( REG_LR_MODEMCONFIG2 ) &
  268. RFLR_MODEMCONFIG2_SF_MASK &
  269. RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
  270. RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
  271. ( datarate << 4 ) | ( crcOn << 2 ) |
  272. ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
  273. Write( REG_LR_MODEMCONFIG3,
  274. ( Read( REG_LR_MODEMCONFIG3 ) &
  275. RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
  276. ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
  277. Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
  278. Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
  279. Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
  280. if( fixLen == 1 )
  281. {
  282. Write( REG_LR_PAYLOADLENGTH, payloadLen );
  283. }
  284. if( this->settings.LoRa.FreqHopOn == true )
  285. {
  286. Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
  287. Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
  288. }
  289. if( ( bandwidth == 9 ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
  290. {
  291. // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
  292. Write( REG_LR_TEST36, 0x02 );
  293. Write( REG_LR_TEST3A, 0x64 );
  294. }
  295. else if( bandwidth == 9 )
  296. {
  297. // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
  298. Write( REG_LR_TEST36, 0x02 );
  299. Write( REG_LR_TEST3A, 0x7F );
  300. }
  301. else
  302. {
  303. // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
  304. Write( REG_LR_TEST36, 0x03 );
  305. }
  306. if( datarate == 6 )
  307. {
  308. Write( REG_LR_DETECTOPTIMIZE,
  309. ( Read( REG_LR_DETECTOPTIMIZE ) &
  310. RFLR_DETECTIONOPTIMIZE_MASK ) |
  311. RFLR_DETECTIONOPTIMIZE_SF6 );
  312. Write( REG_LR_DETECTIONTHRESHOLD,
  313. RFLR_DETECTIONTHRESH_SF6 );
  314. }
  315. else
  316. {
  317. Write( REG_LR_DETECTOPTIMIZE,
  318. ( Read( REG_LR_DETECTOPTIMIZE ) &
  319. RFLR_DETECTIONOPTIMIZE_MASK ) |
  320. RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
  321. Write( REG_LR_DETECTIONTHRESHOLD,
  322. RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
  323. }
  324. }
  325. break;
  326. }
  327. }
  328. void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
  329. uint32_t bandwidth, uint32_t datarate,
  330. uint8_t coderate, uint16_t preambleLen,
  331. bool fixLen, bool crcOn, bool freqHopOn,
  332. uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
  333. {
  334. SetModem( modem );
  335. SetRfTxPower( power );
  336. switch( modem )
  337. {
  338. case MODEM_FSK:
  339. {
  340. this->settings.Fsk.Power = power;
  341. this->settings.Fsk.Fdev = fdev;
  342. this->settings.Fsk.Bandwidth = bandwidth;
  343. this->settings.Fsk.Datarate = datarate;
  344. this->settings.Fsk.PreambleLen = preambleLen;
  345. this->settings.Fsk.FixLen = fixLen;
  346. this->settings.Fsk.CrcOn = crcOn;
  347. this->settings.Fsk.IqInverted = iqInverted;
  348. this->settings.Fsk.TxTimeout = timeout;
  349. fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
  350. Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
  351. Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
  352. datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
  353. Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
  354. Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
  355. Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
  356. Write( REG_PREAMBLELSB, preambleLen & 0xFF );
  357. Write( REG_PACKETCONFIG1,
  358. ( Read( REG_PACKETCONFIG1 ) &
  359. RF_PACKETCONFIG1_CRC_MASK &
  360. RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
  361. ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
  362. ( crcOn << 4 ) );
  363. Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
  364. }
  365. break;
  366. case MODEM_LORA:
  367. {
  368. this->settings.LoRa.Power = power;
  369. if( bandwidth > 2 )
  370. {
  371. // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
  372. while( 1 );
  373. }
  374. bandwidth += 7;
  375. this->settings.LoRa.Bandwidth = bandwidth;
  376. this->settings.LoRa.Datarate = datarate;
  377. this->settings.LoRa.Coderate = coderate;
  378. this->settings.LoRa.PreambleLen = preambleLen;
  379. this->settings.LoRa.FixLen = fixLen;
  380. this->settings.LoRa.FreqHopOn = freqHopOn;
  381. this->settings.LoRa.HopPeriod = hopPeriod;
  382. this->settings.LoRa.CrcOn = crcOn;
  383. this->settings.LoRa.IqInverted = iqInverted;
  384. this->settings.LoRa.TxTimeout = timeout;
  385. if( datarate > 12 )
  386. {
  387. datarate = 12;
  388. }
  389. else if( datarate < 6 )
  390. {
  391. datarate = 6;
  392. }
  393. if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
  394. ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
  395. {
  396. this->settings.LoRa.LowDatarateOptimize = 0x01;
  397. }
  398. else
  399. {
  400. this->settings.LoRa.LowDatarateOptimize = 0x00;
  401. }
  402. if( this->settings.LoRa.FreqHopOn == true )
  403. {
  404. Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
  405. Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
  406. }
  407. Write( REG_LR_MODEMCONFIG1,
  408. ( Read( REG_LR_MODEMCONFIG1 ) &
  409. RFLR_MODEMCONFIG1_BW_MASK &
  410. RFLR_MODEMCONFIG1_CODINGRATE_MASK &
  411. RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
  412. ( bandwidth << 4 ) | ( coderate << 1 ) |
  413. fixLen );
  414. Write( REG_LR_MODEMCONFIG2,
  415. ( Read( REG_LR_MODEMCONFIG2 ) &
  416. RFLR_MODEMCONFIG2_SF_MASK &
  417. RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
  418. ( datarate << 4 ) | ( crcOn << 2 ) );
  419. Write( REG_LR_MODEMCONFIG3,
  420. ( Read( REG_LR_MODEMCONFIG3 ) &
  421. RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
  422. ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
  423. Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
  424. Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
  425. if( datarate == 6 )
  426. {
  427. Write( REG_LR_DETECTOPTIMIZE,
  428. ( Read( REG_LR_DETECTOPTIMIZE ) &
  429. RFLR_DETECTIONOPTIMIZE_MASK ) |
  430. RFLR_DETECTIONOPTIMIZE_SF6 );
  431. Write( REG_LR_DETECTIONTHRESHOLD,
  432. RFLR_DETECTIONTHRESH_SF6 );
  433. }
  434. else
  435. {
  436. Write( REG_LR_DETECTOPTIMIZE,
  437. ( Read( REG_LR_DETECTOPTIMIZE ) &
  438. RFLR_DETECTIONOPTIMIZE_MASK ) |
  439. RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
  440. Write( REG_LR_DETECTIONTHRESHOLD,
  441. RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
  442. }
  443. }
  444. break;
  445. }
  446. }
  447. uint32_t SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
  448. {
  449. uint32_t airTime = 0;
  450. switch( modem )
  451. {
  452. case MODEM_FSK:
  453. {
  454. airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
  455. ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
  456. ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
  457. ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
  458. pktLen +
  459. ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
  460. this->settings.Fsk.Datarate ) * 1e3 );
  461. }
  462. break;
  463. case MODEM_LORA:
  464. {
  465. double bw = 0.0;
  466. // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
  467. switch( this->settings.LoRa.Bandwidth )
  468. {
  469. //case 0: // 7.8 kHz
  470. // bw = 78e2;
  471. // break;
  472. //case 1: // 10.4 kHz
  473. // bw = 104e2;
  474. // break;
  475. //case 2: // 15.6 kHz
  476. // bw = 156e2;
  477. // break;
  478. //case 3: // 20.8 kHz
  479. // bw = 208e2;
  480. // break;
  481. //case 4: // 31.2 kHz
  482. // bw = 312e2;
  483. // break;
  484. //case 5: // 41.4 kHz
  485. // bw = 414e2;
  486. // break;
  487. //case 6: // 62.5 kHz
  488. // bw = 625e2;
  489. // break;
  490. case 7: // 125 kHz
  491. bw = 125e3;
  492. break;
  493. case 8: // 250 kHz
  494. bw = 250e3;
  495. break;
  496. case 9: // 500 kHz
  497. bw = 500e3;
  498. break;
  499. }
  500. // Symbol rate : time for one symbol (secs)
  501. double rs = bw / ( 1 << this->settings.LoRa.Datarate );
  502. double ts = 1 / rs;
  503. // time of preamble
  504. double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
  505. // Symbol length of payload and time
  506. double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
  507. 28 + 16 * this->settings.LoRa.CrcOn -
  508. ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
  509. ( double )( 4 * ( this->settings.LoRa.Datarate -
  510. ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
  511. ( this->settings.LoRa.Coderate + 4 );
  512. double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
  513. double tPayload = nPayload * ts;
  514. // Time on air
  515. double tOnAir = tPreamble + tPayload;
  516. // return ms secs
  517. airTime = floor( tOnAir * 1e3 + 0.999 );
  518. }
  519. break;
  520. }
  521. return airTime;
  522. }
  523. void SX1276::Send( uint8_t *buffer, uint8_t size )
  524. {
  525. uint32_t txTimeout = 0;
  526. switch( this->settings.Modem )
  527. {
  528. case MODEM_FSK:
  529. {
  530. this->settings.FskPacketHandler.NbBytes = 0;
  531. this->settings.FskPacketHandler.Size = size;
  532. if( this->settings.Fsk.FixLen == false )
  533. {
  534. WriteFifo( ( uint8_t* )&size, 1 );
  535. }
  536. else
  537. {
  538. Write( REG_PAYLOADLENGTH, size );
  539. }
  540. if( ( size > 0 ) && ( size <= 64 ) )
  541. {
  542. this->settings.FskPacketHandler.ChunkSize = size;
  543. }
  544. else
  545. {
  546. memcpy( rxtxBuffer, buffer, size );
  547. this->settings.FskPacketHandler.ChunkSize = 32;
  548. }
  549. // Write payload buffer
  550. WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
  551. this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
  552. txTimeout = this->settings.Fsk.TxTimeout;
  553. }
  554. break;
  555. case MODEM_LORA:
  556. {
  557. if( this->settings.LoRa.IqInverted == true )
  558. {
  559. Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
  560. Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
  561. }
  562. else
  563. {
  564. Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
  565. Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
  566. }
  567. this->settings.LoRaPacketHandler.Size = size;
  568. // Initializes the payload size
  569. Write( REG_LR_PAYLOADLENGTH, size );
  570. // Full buffer used for Tx
  571. Write( REG_LR_FIFOTXBASEADDR, 0 );
  572. Write( REG_LR_FIFOADDRPTR, 0 );
  573. // FIFO operations can not take place in Sleep mode
  574. if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
  575. {
  576. Standby( );
  577. wait_ms( 1 );
  578. }
  579. // Write payload buffer
  580. WriteFifo( buffer, size );
  581. txTimeout = this->settings.LoRa.TxTimeout;
  582. }
  583. break;
  584. }
  585. Tx( txTimeout );
  586. }
  587. void SX1276::Sleep( void )
  588. {
  589. txTimeoutTimer.detach( );
  590. rxTimeoutTimer.detach( );
  591. SetOpMode( RF_OPMODE_SLEEP );
  592. this->settings.State = RF_IDLE;
  593. }
  594. void SX1276::Standby( void )
  595. {
  596. txTimeoutTimer.detach( );
  597. rxTimeoutTimer.detach( );
  598. SetOpMode( RF_OPMODE_STANDBY );
  599. this->settings.State = RF_IDLE;
  600. }
  601. void SX1276::Rx( uint32_t timeout )
  602. {
  603. bool rxContinuous = false;
  604. switch( this->settings.Modem )
  605. {
  606. case MODEM_FSK:
  607. {
  608. rxContinuous = this->settings.Fsk.RxContinuous;
  609. // DIO0=PayloadReady
  610. // DIO1=FifoLevel
  611. // DIO2=SyncAddr
  612. // DIO3=FifoEmpty
  613. // DIO4=Preamble
  614. // DIO5=ModeReady
  615. Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
  616. RF_DIOMAPPING1_DIO1_MASK &
  617. RF_DIOMAPPING1_DIO2_MASK ) |
  618. RF_DIOMAPPING1_DIO0_00 |
  619. RF_DIOMAPPING1_DIO1_00 |
  620. RF_DIOMAPPING1_DIO2_11 );
  621. Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
  622. RF_DIOMAPPING2_MAP_MASK ) |
  623. RF_DIOMAPPING2_DIO4_11 |
  624. RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
  625. this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
  626. Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
  627. this->settings.FskPacketHandler.PreambleDetected = false;
  628. this->settings.FskPacketHandler.SyncWordDetected = false;
  629. this->settings.FskPacketHandler.NbBytes = 0;
  630. this->settings.FskPacketHandler.Size = 0;
  631. }
  632. break;
  633. case MODEM_LORA:
  634. {
  635. if( this->settings.LoRa.IqInverted == true )
  636. {
  637. Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
  638. Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
  639. }
  640. else
  641. {
  642. Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
  643. Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
  644. }
  645. // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
  646. if( this->settings.LoRa.Bandwidth < 9 )
  647. {
  648. Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
  649. Write( REG_LR_TEST30, 0x00 );
  650. switch( this->settings.LoRa.Bandwidth )
  651. {
  652. case 0: // 7.8 kHz
  653. Write( REG_LR_TEST2F, 0x48 );
  654. SetChannel(this->settings.Channel + 7.81e3 );
  655. break;
  656. case 1: // 10.4 kHz
  657. Write( REG_LR_TEST2F, 0x44 );
  658. SetChannel(this->settings.Channel + 10.42e3 );
  659. break;
  660. case 2: // 15.6 kHz
  661. Write( REG_LR_TEST2F, 0x44 );
  662. SetChannel(this->settings.Channel + 15.62e3 );
  663. break;
  664. case 3: // 20.8 kHz
  665. Write( REG_LR_TEST2F, 0x44 );
  666. SetChannel(this->settings.Channel + 20.83e3 );
  667. break;
  668. case 4: // 31.2 kHz
  669. Write( REG_LR_TEST2F, 0x44 );
  670. SetChannel(this->settings.Channel + 31.25e3 );
  671. break;
  672. case 5: // 41.4 kHz
  673. Write( REG_LR_TEST2F, 0x44 );
  674. SetChannel(this->settings.Channel + 41.67e3 );
  675. break;
  676. case 6: // 62.5 kHz
  677. Write( REG_LR_TEST2F, 0x40 );
  678. break;
  679. case 7: // 125 kHz
  680. Write( REG_LR_TEST2F, 0x40 );
  681. break;
  682. case 8: // 250 kHz
  683. Write( REG_LR_TEST2F, 0x40 );
  684. break;
  685. }
  686. }
  687. else
  688. {
  689. Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
  690. }
  691. rxContinuous = this->settings.LoRa.RxContinuous;
  692. if( this->settings.LoRa.FreqHopOn == true )
  693. {
  694. Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
  695. //RFLR_IRQFLAGS_RXDONE |
  696. //RFLR_IRQFLAGS_PAYLOADCRCERROR |
  697. RFLR_IRQFLAGS_VALIDHEADER |
  698. RFLR_IRQFLAGS_TXDONE |
  699. RFLR_IRQFLAGS_CADDONE |
  700. //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  701. RFLR_IRQFLAGS_CADDETECTED );
  702. // DIO0=RxDone, DIO2=FhssChangeChannel
  703. Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
  704. }
  705. else
  706. {
  707. Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
  708. //RFLR_IRQFLAGS_RXDONE |
  709. //RFLR_IRQFLAGS_PAYLOADCRCERROR |
  710. RFLR_IRQFLAGS_VALIDHEADER |
  711. RFLR_IRQFLAGS_TXDONE |
  712. RFLR_IRQFLAGS_CADDONE |
  713. RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  714. RFLR_IRQFLAGS_CADDETECTED );
  715. // DIO0=RxDone
  716. Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
  717. }
  718. Write( REG_LR_FIFORXBASEADDR, 0 );
  719. Write( REG_LR_FIFOADDRPTR, 0 );
  720. }
  721. break;
  722. }
  723. memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
  724. this->settings.State = RF_RX_RUNNING;
  725. if( timeout != 0 )
  726. {
  727. rxTimeoutTimer.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ), timeout * 1e3 );
  728. }
  729. if( this->settings.Modem == MODEM_FSK )
  730. {
  731. SetOpMode( RF_OPMODE_RECEIVER );
  732. if( rxContinuous == false )
  733. {
  734. rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ),
  735. this->settings.Fsk.RxSingleTimeout * 1e3 );
  736. }
  737. }
  738. else
  739. {
  740. if( rxContinuous == true )
  741. {
  742. SetOpMode( RFLR_OPMODE_RECEIVER );
  743. }
  744. else
  745. {
  746. SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
  747. }
  748. }
  749. }
  750. void SX1276::Tx( uint32_t timeout )
  751. {
  752. switch( this->settings.Modem )
  753. {
  754. case MODEM_FSK:
  755. {
  756. // DIO0=PacketSent
  757. // DIO1=FifoEmpty
  758. // DIO2=FifoFull
  759. // DIO3=FifoEmpty
  760. // DIO4=LowBat
  761. // DIO5=ModeReady
  762. Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
  763. RF_DIOMAPPING1_DIO1_MASK &
  764. RF_DIOMAPPING1_DIO2_MASK ) |
  765. RF_DIOMAPPING1_DIO1_01 );
  766. Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
  767. RF_DIOMAPPING2_MAP_MASK ) );
  768. this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
  769. }
  770. break;
  771. case MODEM_LORA:
  772. {
  773. if( this->settings.LoRa.FreqHopOn == true )
  774. {
  775. Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
  776. RFLR_IRQFLAGS_RXDONE |
  777. RFLR_IRQFLAGS_PAYLOADCRCERROR |
  778. RFLR_IRQFLAGS_VALIDHEADER |
  779. //RFLR_IRQFLAGS_TXDONE |
  780. RFLR_IRQFLAGS_CADDONE |
  781. //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  782. RFLR_IRQFLAGS_CADDETECTED );
  783. // DIO0=TxDone, DIO2=FhssChangeChannel
  784. Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
  785. }
  786. else
  787. {
  788. Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
  789. RFLR_IRQFLAGS_RXDONE |
  790. RFLR_IRQFLAGS_PAYLOADCRCERROR |
  791. RFLR_IRQFLAGS_VALIDHEADER |
  792. //RFLR_IRQFLAGS_TXDONE |
  793. RFLR_IRQFLAGS_CADDONE |
  794. RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  795. RFLR_IRQFLAGS_CADDETECTED );
  796. // DIO0=TxDone
  797. Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
  798. }
  799. }
  800. break;
  801. }
  802. this->settings.State = RF_TX_RUNNING;
  803. txTimeoutTimer.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ), timeout * 1e3 );
  804. SetOpMode( RF_OPMODE_TRANSMITTER );
  805. }
  806. void SX1276::StartCad( void )
  807. {
  808. switch( this->settings.Modem )
  809. {
  810. case MODEM_FSK:
  811. {
  812. }
  813. break;
  814. case MODEM_LORA:
  815. {
  816. Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
  817. RFLR_IRQFLAGS_RXDONE |
  818. RFLR_IRQFLAGS_PAYLOADCRCERROR |
  819. RFLR_IRQFLAGS_VALIDHEADER |
  820. RFLR_IRQFLAGS_TXDONE |
  821. //RFLR_IRQFLAGS_CADDONE |
  822. RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
  823. //RFLR_IRQFLAGS_CADDETECTED
  824. );
  825. // DIO3=CADDone
  826. Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
  827. this->settings.State = RF_CAD;
  828. SetOpMode( RFLR_OPMODE_CAD );
  829. }
  830. break;
  831. default:
  832. break;
  833. }
  834. }
  835. void SX1276::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
  836. {
  837. uint32_t timeout = ( uint32_t )( time * 1e6 );
  838. SetChannel( freq );
  839. SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
  840. Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
  841. // Disable radio interrupts
  842. Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
  843. Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
  844. this->settings.State = RF_TX_RUNNING;
  845. txTimeoutTimer.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ), timeout );
  846. SetOpMode( RF_OPMODE_TRANSMITTER );
  847. }
  848. int16_t SX1276::GetRssi( RadioModems_t modem )
  849. {
  850. int16_t rssi = 0;
  851. switch( modem )
  852. {
  853. case MODEM_FSK:
  854. rssi = -( Read( REG_RSSIVALUE ) >> 1 );
  855. break;
  856. case MODEM_LORA:
  857. if( this->settings.Channel > RF_MID_BAND_THRESH )
  858. {
  859. rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
  860. }
  861. else
  862. {
  863. rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
  864. }
  865. break;
  866. default:
  867. rssi = -1;
  868. break;
  869. }
  870. return rssi;
  871. }
  872. void SX1276::SetOpMode( uint8_t opMode )
  873. {
  874. if( opMode == RF_OPMODE_SLEEP )
  875. {
  876. SetAntSwLowPower( true );
  877. }
  878. else
  879. {
  880. SetAntSwLowPower( false );
  881. SetAntSw( opMode );
  882. }
  883. Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
  884. }
  885. void SX1276::SetModem( RadioModems_t modem )
  886. {
  887. if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
  888. {
  889. this->settings.Modem = MODEM_LORA;
  890. }
  891. else
  892. {
  893. this->settings.Modem = MODEM_FSK;
  894. }
  895. if( this->settings.Modem == modem )
  896. {
  897. return;
  898. }
  899. this->settings.Modem = modem;
  900. switch( this->settings.Modem )
  901. {
  902. default:
  903. case MODEM_FSK:
  904. Sleep( );
  905. Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
  906. Write( REG_DIOMAPPING1, 0x00 );
  907. Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
  908. break;
  909. case MODEM_LORA:
  910. Sleep( );
  911. Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
  912. Write( REG_DIOMAPPING1, 0x00 );
  913. Write( REG_DIOMAPPING2, 0x00 );
  914. break;
  915. }
  916. }
  917. void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
  918. {
  919. this->SetModem( modem );
  920. switch( modem )
  921. {
  922. case MODEM_FSK:
  923. if( this->settings.Fsk.FixLen == false )
  924. {
  925. this->Write( REG_PAYLOADLENGTH, max );
  926. }
  927. break;
  928. case MODEM_LORA:
  929. this->Write( REG_LR_PAYLOADMAXLENGTH, max );
  930. break;
  931. }
  932. }
  933. void SX1276::SetPublicNetwork( bool enable )
  934. {
  935. SetModem( MODEM_LORA );
  936. this->settings.LoRa.PublicNetwork = enable;
  937. if( enable == true )
  938. {
  939. // Change LoRa modem SyncWord
  940. Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
  941. }
  942. else
  943. {
  944. // Change LoRa modem SyncWord
  945. Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
  946. }
  947. }
  948. void SX1276::OnTimeoutIrq( void )
  949. {
  950. switch( this->settings.State )
  951. {
  952. case RF_RX_RUNNING:
  953. if( this->settings.Modem == MODEM_FSK )
  954. {
  955. this->settings.FskPacketHandler.PreambleDetected = false;
  956. this->settings.FskPacketHandler.SyncWordDetected = false;
  957. this->settings.FskPacketHandler.NbBytes = 0;
  958. this->settings.FskPacketHandler.Size = 0;
  959. // Clear Irqs
  960. Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
  961. RF_IRQFLAGS1_PREAMBLEDETECT |
  962. RF_IRQFLAGS1_SYNCADDRESSMATCH );
  963. Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
  964. if( this->settings.Fsk.RxContinuous == true )
  965. {
  966. // Continuous mode restart Rx chain
  967. Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
  968. rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ),
  969. this->settings.Fsk.RxSingleTimeout * 1e3 );
  970. }
  971. else
  972. {
  973. this->settings.State = RF_IDLE;
  974. rxTimeoutSyncWord.detach( );
  975. }
  976. }
  977. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
  978. {
  979. this->RadioEvents->RxTimeout( );
  980. }
  981. break;
  982. case RF_TX_RUNNING:
  983. // Tx timeout shouldn't happen.
  984. // But it has been observed that when it happens it is a result of a corrupted SPI transfer
  985. // it depends on the platform design.
  986. //
  987. // The workaround is to put the radio in a known state. Thus, we re-initialize it.
  988. // BEGIN WORKAROUND
  989. // Reset the radio
  990. Reset( );
  991. // Calibrate Rx chain
  992. RxChainCalibration( );
  993. // Initialize radio default values
  994. SetOpMode( RF_OPMODE_SLEEP );
  995. RadioRegistersInit( );
  996. SetModem( MODEM_FSK );
  997. // Restore previous network type setting.
  998. SetPublicNetwork( this->settings.LoRa.PublicNetwork );
  999. // END WORKAROUND
  1000. this->settings.State = RF_IDLE;
  1001. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
  1002. {
  1003. this->RadioEvents->TxTimeout( );
  1004. }
  1005. break;
  1006. default:
  1007. break;
  1008. }
  1009. }
  1010. void SX1276::OnDio0Irq( void )
  1011. {
  1012. volatile uint8_t irqFlags = 0;
  1013. switch( this->settings.State )
  1014. {
  1015. case RF_RX_RUNNING:
  1016. //TimerStop( &RxTimeoutTimer );
  1017. // RxDone interrupt
  1018. switch( this->settings.Modem )
  1019. {
  1020. case MODEM_FSK:
  1021. if( this->settings.Fsk.CrcOn == true )
  1022. {
  1023. irqFlags = Read( REG_IRQFLAGS2 );
  1024. if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
  1025. {
  1026. // Clear Irqs
  1027. Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
  1028. RF_IRQFLAGS1_PREAMBLEDETECT |
  1029. RF_IRQFLAGS1_SYNCADDRESSMATCH );
  1030. Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
  1031. rxTimeoutTimer.detach( );
  1032. if( this->settings.Fsk.RxContinuous == false )
  1033. {
  1034. rxTimeoutSyncWord.detach( );
  1035. this->settings.State = RF_IDLE;
  1036. }
  1037. else
  1038. {
  1039. // Continuous mode restart Rx chain
  1040. Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
  1041. rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ),
  1042. this->settings.Fsk.RxSingleTimeout * 1e3 );
  1043. }
  1044. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
  1045. {
  1046. this->RadioEvents->RxError( );
  1047. }
  1048. this->settings.FskPacketHandler.PreambleDetected = false;
  1049. this->settings.FskPacketHandler.SyncWordDetected = false;
  1050. this->settings.FskPacketHandler.NbBytes = 0;
  1051. this->settings.FskPacketHandler.Size = 0;
  1052. break;
  1053. }
  1054. }
  1055. // Read received packet size
  1056. if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
  1057. {
  1058. if( this->settings.Fsk.FixLen == false )
  1059. {
  1060. ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
  1061. }
  1062. else
  1063. {
  1064. this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
  1065. }
  1066. ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1067. this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1068. }
  1069. else
  1070. {
  1071. ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1072. this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1073. }
  1074. rxTimeoutTimer.detach( );
  1075. if( this->settings.Fsk.RxContinuous == false )
  1076. {
  1077. this->settings.State = RF_IDLE;
  1078. rxTimeoutSyncWord.detach( );
  1079. }
  1080. else
  1081. {
  1082. // Continuous mode restart Rx chain
  1083. Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
  1084. rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ),
  1085. this->settings.Fsk.RxSingleTimeout * 1e3 );
  1086. }
  1087. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
  1088. {
  1089. this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
  1090. }
  1091. this->settings.FskPacketHandler.PreambleDetected = false;
  1092. this->settings.FskPacketHandler.SyncWordDetected = false;
  1093. this->settings.FskPacketHandler.NbBytes = 0;
  1094. this->settings.FskPacketHandler.Size = 0;
  1095. break;
  1096. case MODEM_LORA:
  1097. {
  1098. int8_t snr = 0;
  1099. // Clear Irq
  1100. Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
  1101. irqFlags = Read( REG_LR_IRQFLAGS );
  1102. if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
  1103. {
  1104. // Clear Irq
  1105. Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
  1106. if( this->settings.LoRa.RxContinuous == false )
  1107. {
  1108. this->settings.State = RF_IDLE;
  1109. }
  1110. rxTimeoutTimer.detach( );
  1111. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
  1112. {
  1113. this->RadioEvents->RxError( );
  1114. }
  1115. break;
  1116. }
  1117. this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
  1118. if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
  1119. {
  1120. // Invert and divide by 4
  1121. snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
  1122. snr = -snr;
  1123. }
  1124. else
  1125. {
  1126. // Divide by 4
  1127. snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
  1128. }
  1129. int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
  1130. if( snr < 0 )
  1131. {
  1132. if( this->settings.Channel > RF_MID_BAND_THRESH )
  1133. {
  1134. this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
  1135. snr;
  1136. }
  1137. else
  1138. {
  1139. this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
  1140. snr;
  1141. }
  1142. }
  1143. else
  1144. {
  1145. if( this->settings.Channel > RF_MID_BAND_THRESH )
  1146. {
  1147. this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
  1148. }
  1149. else
  1150. {
  1151. this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
  1152. }
  1153. }
  1154. this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
  1155. ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
  1156. if( this->settings.LoRa.RxContinuous == false )
  1157. {
  1158. this->settings.State = RF_IDLE;
  1159. }
  1160. rxTimeoutTimer.detach( );
  1161. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
  1162. {
  1163. this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
  1164. }
  1165. }
  1166. break;
  1167. default:
  1168. break;
  1169. }
  1170. break;
  1171. case RF_TX_RUNNING:
  1172. txTimeoutTimer.detach( );
  1173. // TxDone interrupt
  1174. switch( this->settings.Modem )
  1175. {
  1176. case MODEM_LORA:
  1177. // Clear Irq
  1178. Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
  1179. // Intentional fall through
  1180. case MODEM_FSK:
  1181. default:
  1182. this->settings.State = RF_IDLE;
  1183. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
  1184. {
  1185. this->RadioEvents->TxDone( );
  1186. }
  1187. break;
  1188. }
  1189. break;
  1190. default:
  1191. break;
  1192. }
  1193. }
  1194. void SX1276::OnDio1Irq( void )
  1195. {
  1196. switch( this->settings.State )
  1197. {
  1198. case RF_RX_RUNNING:
  1199. switch( this->settings.Modem )
  1200. {
  1201. case MODEM_FSK:
  1202. // FifoLevel interrupt
  1203. // Read received packet size
  1204. if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
  1205. {
  1206. if( this->settings.Fsk.FixLen == false )
  1207. {
  1208. ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
  1209. }
  1210. else
  1211. {
  1212. this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
  1213. }
  1214. }
  1215. if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
  1216. {
  1217. ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
  1218. this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
  1219. }
  1220. else
  1221. {
  1222. ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1223. this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1224. }
  1225. break;
  1226. case MODEM_LORA:
  1227. // Sync time out
  1228. rxTimeoutTimer.detach( );
  1229. // Clear Irq
  1230. Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
  1231. this->settings.State = RF_IDLE;
  1232. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
  1233. {
  1234. this->RadioEvents->RxTimeout( );
  1235. }
  1236. break;
  1237. default:
  1238. break;
  1239. }
  1240. break;
  1241. case RF_TX_RUNNING:
  1242. switch( this->settings.Modem )
  1243. {
  1244. case MODEM_FSK:
  1245. // FifoEmpty interrupt
  1246. if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
  1247. {
  1248. WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
  1249. this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
  1250. }
  1251. else
  1252. {
  1253. // Write the last chunk of data
  1254. WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1255. this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
  1256. }
  1257. break;
  1258. case MODEM_LORA:
  1259. break;
  1260. default:
  1261. break;
  1262. }
  1263. break;
  1264. default:
  1265. break;
  1266. }
  1267. }
  1268. void SX1276::OnDio2Irq( void )
  1269. {
  1270. switch( this->settings.State )
  1271. {
  1272. case RF_RX_RUNNING:
  1273. switch( this->settings.Modem )
  1274. {
  1275. case MODEM_FSK:
  1276. // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
  1277. if( this->dioIrq[4] == NULL )
  1278. {
  1279. this->settings.FskPacketHandler.PreambleDetected = true;
  1280. }
  1281. if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
  1282. {
  1283. rxTimeoutSyncWord.detach( );
  1284. this->settings.FskPacketHandler.SyncWordDetected = true;
  1285. this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
  1286. this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
  1287. ( uint16_t )Read( REG_AFCLSB ) ) *
  1288. ( double )FREQ_STEP;
  1289. this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
  1290. }
  1291. break;
  1292. case MODEM_LORA:
  1293. if( this->settings.LoRa.FreqHopOn == true )
  1294. {
  1295. // Clear Irq
  1296. Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
  1297. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
  1298. {
  1299. this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
  1300. }
  1301. }
  1302. break;
  1303. default:
  1304. break;
  1305. }
  1306. break;
  1307. case RF_TX_RUNNING:
  1308. switch( this->settings.Modem )
  1309. {
  1310. case MODEM_FSK:
  1311. break;
  1312. case MODEM_LORA:
  1313. if( this->settings.LoRa.FreqHopOn == true )
  1314. {
  1315. // Clear Irq
  1316. Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
  1317. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
  1318. {
  1319. this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
  1320. }
  1321. }
  1322. break;
  1323. default:
  1324. break;
  1325. }
  1326. break;
  1327. default:
  1328. break;
  1329. }
  1330. }
  1331. void SX1276::OnDio3Irq( void )
  1332. {
  1333. switch( this->settings.Modem )
  1334. {
  1335. case MODEM_FSK:
  1336. break;
  1337. case MODEM_LORA:
  1338. if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
  1339. {
  1340. // Clear Irq
  1341. Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
  1342. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
  1343. {
  1344. this->RadioEvents->CadDone( true );
  1345. }
  1346. }
  1347. else
  1348. {
  1349. // Clear Irq
  1350. Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
  1351. if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
  1352. {
  1353. this->RadioEvents->CadDone( false );
  1354. }
  1355. }
  1356. break;
  1357. default:
  1358. break;
  1359. }
  1360. }
  1361. void SX1276::OnDio4Irq( void )
  1362. {
  1363. switch( this->settings.Modem )
  1364. {
  1365. case MODEM_FSK:
  1366. {
  1367. if( this->settings.FskPacketHandler.PreambleDetected == false )
  1368. {
  1369. this->settings.FskPacketHandler.PreambleDetected = true;
  1370. }
  1371. }
  1372. break;
  1373. case MODEM_LORA:
  1374. break;
  1375. default:
  1376. break;
  1377. }
  1378. }
  1379. void SX1276::OnDio5Irq( void )
  1380. {
  1381. switch( this->settings.Modem )
  1382. {
  1383. case MODEM_FSK:
  1384. break;
  1385. case MODEM_LORA:
  1386. break;
  1387. default:
  1388. break;
  1389. }
  1390. }