Implement a secure ICS protocol targeting LoRa Node151 microcontroller for controlling irrigation.
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  1. /**
  2. ******************************************************************************
  3. * @file stm32l0xx_hal_dac_ex.c
  4. * @author MCD Application Team
  5. * @brief Extended DAC HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of DAC extension peripheral:
  8. * + Extended features functions
  9. *
  10. *
  11. @verbatim
  12. ==============================================================================
  13. ##### How to use this driver #####
  14. ==============================================================================
  15. [..]
  16. (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
  17. Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
  18. HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
  19. (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
  20. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
  21. @endverbatim
  22. ******************************************************************************
  23. * @attention
  24. *
  25. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  26. *
  27. * Redistribution and use in source and binary forms, with or without modification,
  28. * are permitted provided that the following conditions are met:
  29. * 1. Redistributions of source code must retain the above copyright notice,
  30. * this list of conditions and the following disclaimer.
  31. * 2. Redistributions in binary form must reproduce the above copyright notice,
  32. * this list of conditions and the following disclaimer in the documentation
  33. * and/or other materials provided with the distribution.
  34. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  35. * may be used to endorse or promote products derived from this software
  36. * without specific prior written permission.
  37. *
  38. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  39. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  40. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  41. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  42. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  43. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  44. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  45. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  46. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48. *
  49. ******************************************************************************
  50. */
  51. #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
  52. /* Includes ------------------------------------------------------------------*/
  53. #include "stm32l0xx_hal.h"
  54. #ifdef HAL_DAC_MODULE_ENABLED
  55. /** @addtogroup STM32L0xx_HAL_Driver
  56. * @{
  57. */
  58. /** @addtogroup DACEx DACEx
  59. * @brief DAC driver modules
  60. * @{
  61. */
  62. /** @addtogroup DACEx_Private
  63. * @{
  64. */
  65. /* Private typedef -----------------------------------------------------------*/
  66. /* Private define ------------------------------------------------------------*/
  67. /* Private macro -------------------------------------------------------------*/
  68. /* Private variables ---------------------------------------------------------*/
  69. /* Private function prototypes -----------------------------------------------*/
  70. /* Private functions ---------------------------------------------------------*/
  71. #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
  72. static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
  73. static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
  74. static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
  75. #endif
  76. static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
  77. static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
  78. static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
  79. /**
  80. * @}
  81. */
  82. /** @addtogroup DACEx_Exported_Functions
  83. * @{
  84. */
  85. /** @addtogroup DACEx_Exported_Functions_Group1
  86. * @brief Extended features functions
  87. *
  88. * @{
  89. */
  90. #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
  91. /**
  92. * @brief Returns the last data output value of the selected DAC channel.
  93. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  94. * the configuration information for the specified DAC.
  95. * @retval The selected DAC channel data output value.
  96. */
  97. uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
  98. {
  99. uint32_t tmp = 0U;
  100. tmp |= hdac->Instance->DOR1;
  101. tmp |= hdac->Instance->DOR2 << 16U;
  102. /* Returns the DAC channel data output register value */
  103. return tmp;
  104. }
  105. #endif
  106. /**
  107. * @brief Enables or disables the selected DAC channel wave generation.
  108. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  109. * the configuration information for the specified DAC.
  110. * @param Channel: The selected DAC channel.
  111. * This parameter can be one of the following values:
  112. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  113. * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
  114. * @param Amplitude: Select max triangle amplitude.
  115. * This parameter can be one of the following values:
  116. * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  117. * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  118. * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  119. * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  120. * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  121. * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  122. * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  123. * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  124. * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  125. * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  126. * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  127. * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
  128. * @retval HAL status
  129. */
  130. HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
  131. {
  132. /* Check the parameters */
  133. assert_param(IS_DAC_CHANNEL(Channel));
  134. assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
  135. /* Process locked */
  136. __HAL_LOCK(hdac);
  137. /* Change DAC state */
  138. hdac->State = HAL_DAC_STATE_BUSY;
  139. /* Enable the triangle wave generation for the selected DAC channel */
  140. MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
  141. /* Change DAC state */
  142. hdac->State = HAL_DAC_STATE_READY;
  143. /* Process unlocked */
  144. __HAL_UNLOCK(hdac);
  145. /* Return function status */
  146. return HAL_OK;
  147. }
  148. /**
  149. * @brief Enables or disables the selected DAC channel wave generation.
  150. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  151. * the configuration information for the specified DAC.
  152. * @param Channel: The selected DAC channel.
  153. * This parameter can be one of the following values:
  154. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  155. * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
  156. * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
  157. * This parameter can be one of the following values:
  158. * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  159. * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  160. * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  161. * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  162. * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  163. * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  164. * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  165. * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  166. * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  167. * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  168. * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  169. * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
  170. * @retval HAL status
  171. */
  172. HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
  173. {
  174. /* Check the parameters */
  175. assert_param(IS_DAC_CHANNEL(Channel));
  176. assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
  177. /* Process locked */
  178. __HAL_LOCK(hdac);
  179. /* Change DAC state */
  180. hdac->State = HAL_DAC_STATE_BUSY;
  181. /* Enable the noise wave generation for the selected DAC channel */
  182. MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
  183. /* Change DAC state */
  184. hdac->State = HAL_DAC_STATE_READY;
  185. /* Process unlocked */
  186. __HAL_UNLOCK(hdac);
  187. /* Return function status */
  188. return HAL_OK;
  189. }
  190. #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
  191. /**
  192. * @brief Set the specified data holding register value for dual DAC channel.
  193. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  194. * the configuration information for the specified DAC.
  195. * @param Alignment: Specifies the data alignment for dual channel DAC.
  196. * This parameter can be one of the following values:
  197. * DAC_ALIGN_8B_R: 8bit right data alignment selected
  198. * DAC_ALIGN_12B_L: 12bit left data alignment selected
  199. * DAC_ALIGN_12B_R: 12bit right data alignment selected
  200. * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
  201. * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
  202. * @note In dual mode, a unique register access is required to write in both
  203. * DAC channels at the same time.
  204. * @retval HAL status
  205. */
  206. HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
  207. {
  208. uint32_t data = 0U, tmp = 0U;
  209. /* Check the parameters */
  210. assert_param(IS_DAC_ALIGN(Alignment));
  211. assert_param(IS_DAC_DATA(Data1));
  212. assert_param(IS_DAC_DATA(Data2));
  213. /* Calculate and set dual DAC data holding register value */
  214. if (Alignment == DAC_ALIGN_8B_R)
  215. {
  216. data = ((uint32_t)Data2 << 8U) | Data1;
  217. }
  218. else
  219. {
  220. data = ((uint32_t)Data2 << 16U) | Data1;
  221. }
  222. tmp = (uint32_t)hdac->Instance;
  223. tmp += DAC_DHR12RD_ALIGNEMENT(Alignment);
  224. /* Set the dual DAC selected data holding register */
  225. *(__IO uint32_t *)tmp = data;
  226. /* Return function status */
  227. return HAL_OK;
  228. }
  229. /**
  230. * @brief Conversion complete callback in non blocking mode for Channel2
  231. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  232. * the configuration information for the specified DAC.
  233. * @retval None
  234. */
  235. __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
  236. {
  237. /* Prevent unused argument(s) compilation warning */
  238. UNUSED(hdac);
  239. /* NOTE : This function Should not be modified, when the callback is needed,
  240. the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
  241. */
  242. }
  243. /**
  244. * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
  245. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  246. * the configuration information for the specified DAC.
  247. * @retval None
  248. */
  249. __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
  250. {
  251. /* Prevent unused argument(s) compilation warning */
  252. UNUSED(hdac);
  253. /* NOTE : This function Should not be modified, when the callback is needed,
  254. the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
  255. */
  256. }
  257. /**
  258. * @brief Error DAC callback for Channel2.
  259. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  260. * the configuration information for the specified DAC.
  261. * @retval None
  262. */
  263. __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
  264. {
  265. /* Prevent unused argument(s) compilation warning */
  266. UNUSED(hdac);
  267. /* NOTE : This function Should not be modified, when the callback is needed,
  268. the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
  269. */
  270. }
  271. /**
  272. * @brief DMA underrun DAC callback for channel2.
  273. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  274. * the configuration information for the specified DAC.
  275. * @retval None
  276. */
  277. __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
  278. {
  279. /* Prevent unused argument(s) compilation warning */
  280. UNUSED(hdac);
  281. /* NOTE : This function Should not be modified, when the callback is needed,
  282. the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
  283. */
  284. }
  285. /**
  286. * @brief Enables DAC and starts conversion of channel.
  287. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  288. * the configuration information for the specified DAC.
  289. * @param Channel: The selected DAC channel.
  290. * This parameter can be one of the following values:
  291. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  292. * @arg DAC_CHANNEL_2: DAC Channel2 selected
  293. * @retval HAL status
  294. */
  295. HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
  296. {
  297. uint32_t tmp1 = 0U, tmp2 = 0U;
  298. /* Check the parameters */
  299. assert_param(IS_DAC_CHANNEL(Channel));
  300. /* Process locked */
  301. __HAL_LOCK(hdac);
  302. /* Change DAC state */
  303. hdac->State = HAL_DAC_STATE_BUSY;
  304. /* Enable the Peripharal */
  305. __HAL_DAC_ENABLE(hdac, Channel);
  306. if(Channel == DAC_CHANNEL_1)
  307. {
  308. tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
  309. tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
  310. /* Check if software trigger enabled */
  311. if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
  312. {
  313. /* Enable the selected DAC software conversion */
  314. SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
  315. }
  316. }
  317. else
  318. {
  319. tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
  320. tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
  321. /* Check if software trigger enabled */
  322. if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
  323. {
  324. /* Enable the selected DAC software conversion*/
  325. SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
  326. }
  327. }
  328. /* Change DAC state */
  329. hdac->State = HAL_DAC_STATE_READY;
  330. /* Process unlocked */
  331. __HAL_UNLOCK(hdac);
  332. /* Return function status */
  333. return HAL_OK;
  334. }
  335. /**
  336. * @brief Enables DAC and starts conversion of channel using DMA.
  337. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  338. * the configuration information for the specified DAC.
  339. * @param Channel: The selected DAC channel.
  340. * This parameter can be one of the following values:
  341. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  342. * @arg DAC_CHANNEL_2: DAC Channel2 selected
  343. * @param pData: The destination peripheral Buffer address.
  344. * @param Length: The length of data to be transferred from memory to DAC peripheral
  345. * @param Alignment: Specifies the data alignment for DAC channel.
  346. * This parameter can be one of the following values:
  347. * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
  348. * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
  349. * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
  350. * @retval HAL status
  351. */
  352. HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
  353. {
  354. uint32_t tmpreg = 0U;
  355. /* Check the parameters */
  356. assert_param(IS_DAC_CHANNEL(Channel));
  357. assert_param(IS_DAC_ALIGN(Alignment));
  358. /* Process locked */
  359. __HAL_LOCK(hdac);
  360. /* Change DAC state */
  361. hdac->State = HAL_DAC_STATE_BUSY;
  362. if(Channel == DAC_CHANNEL_1)
  363. {
  364. /* Set the DMA transfer complete callback for channel1 */
  365. hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
  366. /* Set the DMA half transfer complete callback for channel1 */
  367. hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
  368. /* Set the DMA error callback for channel1 */
  369. hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
  370. /* Enable the selected DAC channel1 DMA request */
  371. SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
  372. /* Case of use of channel 1 */
  373. switch(Alignment)
  374. {
  375. case DAC_ALIGN_12B_R:
  376. /* Get DHR12R1 address */
  377. tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
  378. break;
  379. case DAC_ALIGN_12B_L:
  380. /* Get DHR12L1 address */
  381. tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
  382. break;
  383. case DAC_ALIGN_8B_R:
  384. /* Get DHR8R1 address */
  385. tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
  386. break;
  387. default:
  388. break;
  389. }
  390. UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
  391. }
  392. else
  393. {
  394. /* Set the DMA transfer complete callback for channel2 */
  395. hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
  396. /* Set the DMA half transfer complete callback for channel2 */
  397. hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
  398. /* Set the DMA error callback for channel2 */
  399. hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
  400. /* Enable the selected DAC channel2 DMA request */
  401. SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
  402. /* Case of use of channel 2 */
  403. switch(Alignment)
  404. {
  405. case DAC_ALIGN_12B_R:
  406. /* Get DHR12R2 address */
  407. tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
  408. break;
  409. case DAC_ALIGN_12B_L:
  410. /* Get DHR12L2 address */
  411. tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
  412. break;
  413. case DAC_ALIGN_8B_R:
  414. /* Get DHR8R2 address */
  415. tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
  416. break;
  417. default:
  418. break;
  419. }
  420. }
  421. /* Enable the DMA Stream */
  422. if(Channel == DAC_CHANNEL_1)
  423. {
  424. /* Enable the DAC DMA underrun interrupt */
  425. __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
  426. /* Enable the DMA Stream */
  427. HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
  428. }
  429. else
  430. {
  431. /* Enable the DAC DMA underrun interrupt */
  432. __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
  433. /* Enable the DMA Stream */
  434. HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
  435. }
  436. /* Enable the Peripharal */
  437. __HAL_DAC_ENABLE(hdac, Channel);
  438. /* Process Unlocked */
  439. __HAL_UNLOCK(hdac);
  440. /* Return function status */
  441. return HAL_OK;
  442. }
  443. /**
  444. * @brief Disables DAC and stop conversion of channel.
  445. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  446. * the configuration information for the specified DAC.
  447. * @param Channel: The selected DAC channel.
  448. * This parameter can be one of the following values:
  449. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  450. * @arg DAC_CHANNEL_2: DAC Channel2 selected
  451. * @retval HAL status
  452. */
  453. HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
  454. {
  455. HAL_StatusTypeDef status = HAL_OK;
  456. /* Check the parameters */
  457. assert_param(IS_DAC_CHANNEL(Channel));
  458. /* Disable the selected DAC channel DMA request */
  459. CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
  460. /* Disable the Peripharal */
  461. __HAL_DAC_DISABLE(hdac, Channel);
  462. /* Disable the DMA Channel */
  463. /* Channel1 is used */
  464. if(Channel == DAC_CHANNEL_1)
  465. {
  466. status = HAL_DMA_Abort(hdac->DMA_Handle1);
  467. }
  468. else /* Channel2 is used for */
  469. {
  470. status = HAL_DMA_Abort(hdac->DMA_Handle2);
  471. }
  472. /* Check if DMA Channel effectively disabled */
  473. if(status != HAL_OK)
  474. {
  475. /* Update DAC state machine to error */
  476. hdac->State = HAL_DAC_STATE_ERROR;
  477. }
  478. else
  479. {
  480. /* Change DAC state */
  481. hdac->State = HAL_DAC_STATE_READY;
  482. }
  483. /* Return function status */
  484. return status;
  485. }
  486. /**
  487. * @brief Returns the last data output value of the selected DAC channel.
  488. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  489. * the configuration information for the specified DAC.
  490. * @param Channel: The selected DAC channel.
  491. * This parameter can be one of the following values:
  492. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  493. * @arg DAC_CHANNEL_2: DAC Channel2 selected
  494. * @retval The selected DAC channel data output value.
  495. */
  496. uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
  497. {
  498. /* Check the parameters */
  499. assert_param(IS_DAC_CHANNEL(Channel));
  500. /* Returns the DAC channel data output register value */
  501. if(Channel == DAC_CHANNEL_1)
  502. {
  503. return hdac->Instance->DOR1;
  504. }
  505. else
  506. {
  507. return hdac->Instance->DOR2;
  508. }
  509. }
  510. /**
  511. * @brief Handles DAC interrupt request
  512. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  513. * the configuration information for the specified DAC.
  514. * @retval None
  515. */
  516. void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
  517. {
  518. /* Check underrun flag of DAC channel 1 */
  519. if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
  520. {
  521. /* Change DAC state to error state */
  522. hdac->State = HAL_DAC_STATE_ERROR;
  523. /* Set DAC error code to chanel1 DMA underrun error */
  524. hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
  525. /* Clear the underrun flag */
  526. __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
  527. /* Disable the selected DAC channel1 DMA request */
  528. CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
  529. /* Error callback */
  530. HAL_DAC_DMAUnderrunCallbackCh1(hdac);
  531. }
  532. /* Check underrun flag of DAC channel 2 */
  533. if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
  534. {
  535. /* Change DAC state to error state */
  536. hdac->State = HAL_DAC_STATE_ERROR;
  537. /* Set DAC error code to channel2 DMA underrun error */
  538. hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
  539. /* Clear the underrun flag */
  540. __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
  541. /* Disable the selected DAC channel1 DMA request */
  542. CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
  543. /* Error callback */
  544. HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
  545. }
  546. }
  547. /**
  548. * @brief Set the specified data holding register value for DAC channel.
  549. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  550. * the configuration information for the specified DAC.
  551. * @param Channel: The selected DAC channel.
  552. * This parameter can be one of the following values:
  553. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  554. * @arg DAC_CHANNEL_2: DAC Channel2 selected
  555. * @param Alignment: Specifies the data alignment.
  556. * This parameter can be one of the following values:
  557. * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
  558. * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
  559. * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
  560. * @param Data: Data to be loaded in the selected data holding register.
  561. * @retval HAL status
  562. */
  563. HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
  564. {
  565. __IO uint32_t tmp = 0U;
  566. /* Check the parameters */
  567. assert_param(IS_DAC_CHANNEL(Channel));
  568. assert_param(IS_DAC_ALIGN(Alignment));
  569. assert_param(IS_DAC_DATA(Data));
  570. tmp = (uint32_t)hdac->Instance;
  571. if(Channel == DAC_CHANNEL_1)
  572. {
  573. tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
  574. }
  575. else
  576. {
  577. tmp += DAC_DHR12R2_ALIGNEMENT(Alignment);
  578. }
  579. /* Set the DAC channel selected data holding register */
  580. *(__IO uint32_t *) tmp = Data;
  581. /* Return function status */
  582. return HAL_OK;
  583. }
  584. #else /* All products with only one channel */
  585. /**
  586. * @brief Enables DAC and starts conversion of channel.
  587. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  588. * the configuration information for the specified DAC.
  589. * @param Channel: The selected DAC channel.
  590. * This parameter can be one of the following values:
  591. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  592. * @retval HAL status
  593. */
  594. HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
  595. {
  596. uint32_t tmp1 = 0U, tmp2 = 0U;
  597. /* Check the parameters */
  598. assert_param(IS_DAC_CHANNEL(Channel));
  599. /* Process locked */
  600. __HAL_LOCK(hdac);
  601. /* Change DAC state */
  602. hdac->State = HAL_DAC_STATE_BUSY;
  603. /* Enable the Peripharal */
  604. __HAL_DAC_ENABLE(hdac, Channel);
  605. tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
  606. tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
  607. /* Check if software trigger enabled */
  608. if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
  609. {
  610. /* Enable the selected DAC software conversion */
  611. SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
  612. }
  613. /* Change DAC state */
  614. hdac->State = HAL_DAC_STATE_READY;
  615. /* Process unlocked */
  616. __HAL_UNLOCK(hdac);
  617. /* Return function status */
  618. return HAL_OK;
  619. }
  620. /**
  621. * @brief Enables DAC and starts conversion of channel using DMA.
  622. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  623. * the configuration information for the specified DAC.
  624. * @param Channel: The selected DAC channel.
  625. * This parameter can be one of the following values:
  626. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  627. * @param pData: The destination peripheral Buffer address.
  628. * @param Length: The length of data to be transferred from memory to DAC peripheral
  629. * @param Alignment: Specifies the data alignment for DAC channel.
  630. * This parameter can be one of the following values:
  631. * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
  632. * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
  633. * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
  634. * @retval HAL status
  635. */
  636. HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
  637. {
  638. uint32_t tmpreg = 0U;
  639. /* Check the parameters */
  640. assert_param(IS_DAC_CHANNEL(Channel));
  641. assert_param(IS_DAC_ALIGN(Alignment));
  642. /* Process locked */
  643. __HAL_LOCK(hdac);
  644. /* Change DAC state */
  645. hdac->State = HAL_DAC_STATE_BUSY;
  646. /* Set the DMA transfer complete callback for channel1 */
  647. hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
  648. /* Set the DMA half transfer complete callback for channel1 */
  649. hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
  650. /* Set the DMA error callback for channel1 */
  651. hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
  652. /* Enable the selected DAC channel1 DMA request */
  653. SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
  654. /* Case of use of channel 1 */
  655. switch(Alignment)
  656. {
  657. case DAC_ALIGN_12B_R:
  658. /* Get DHR12R1 address */
  659. tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
  660. break;
  661. case DAC_ALIGN_12B_L:
  662. /* Get DHR12L1 address */
  663. tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
  664. break;
  665. case DAC_ALIGN_8B_R:
  666. /* Get DHR8R1 address */
  667. tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
  668. break;
  669. default:
  670. break;
  671. }
  672. UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
  673. /* Enable the DMA Stream */
  674. /* Enable the DAC DMA underrun interrupt */
  675. __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
  676. /* Enable the DMA Stream */
  677. HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
  678. /* Enable the Peripharal */
  679. __HAL_DAC_ENABLE(hdac, Channel);
  680. /* Process Unlocked */
  681. __HAL_UNLOCK(hdac);
  682. /* Return function status */
  683. return HAL_OK;
  684. }
  685. /**
  686. * @brief Disables DAC and stop conversion of channel.
  687. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  688. * the configuration information for the specified DAC.
  689. * @param Channel: The selected DAC channel.
  690. * This parameter can be one of the following values:
  691. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  692. * @retval HAL status
  693. */
  694. HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
  695. {
  696. HAL_StatusTypeDef status = HAL_OK;
  697. /* Check the parameters */
  698. assert_param(IS_DAC_CHANNEL(Channel));
  699. /* Disable the selected DAC channel DMA request */
  700. CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
  701. /* Disable the Peripharal */
  702. __HAL_DAC_DISABLE(hdac, Channel);
  703. /* Disable the DMA Channel */
  704. status = HAL_DMA_Abort(hdac->DMA_Handle1);
  705. /* Check if DMA Channel effectively disabled */
  706. if(status != HAL_OK)
  707. {
  708. /* Update DAC state machine to error */
  709. hdac->State = HAL_DAC_STATE_ERROR;
  710. }
  711. else
  712. {
  713. /* Change DAC state */
  714. hdac->State = HAL_DAC_STATE_READY;
  715. }
  716. /* Return function status */
  717. return status;
  718. }
  719. /**
  720. * @brief Returns the last data output value of the selected DAC channel.
  721. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  722. * the configuration information for the specified DAC.
  723. * @param Channel: The selected DAC channel.
  724. * This parameter can be one of the following values:
  725. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  726. * @retval The selected DAC channel data output value.
  727. */
  728. uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
  729. {
  730. /* Check the parameters */
  731. assert_param(IS_DAC_CHANNEL(Channel));
  732. /* Returns the DAC channel data output register value */
  733. return hdac->Instance->DOR1;
  734. }
  735. /**
  736. * @brief Handles DAC interrupt request
  737. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  738. * the configuration information for the specified DAC.
  739. * @retval None
  740. */
  741. void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
  742. {
  743. /* Check underrun flag of DAC channel 1 */
  744. if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
  745. {
  746. /* Change DAC state to error state */
  747. hdac->State = HAL_DAC_STATE_ERROR;
  748. /* Set DAC error code to chanel1 DMA underrun error */
  749. hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
  750. /* Clear the underrun flag */
  751. __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
  752. /* Disable the selected DAC channel1 DMA request */
  753. CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
  754. /* Error callback */
  755. HAL_DAC_DMAUnderrunCallbackCh1(hdac);
  756. }
  757. }
  758. /**
  759. * @brief Set the specified data holding register value for DAC channel.
  760. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
  761. * the configuration information for the specified DAC.
  762. * @param Channel: The selected DAC channel.
  763. * This parameter can be one of the following values:
  764. * @arg DAC_CHANNEL_1: DAC Channel1 selected
  765. * @param Alignment: Specifies the data alignment.
  766. * This parameter can be one of the following values:
  767. * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
  768. * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
  769. * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
  770. * @param Data: Data to be loaded in the selected data holding register.
  771. * @retval HAL status
  772. */
  773. HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
  774. {
  775. __IO uint32_t tmp = 0U;
  776. /* Check the parameters */
  777. assert_param(IS_DAC_CHANNEL(Channel));
  778. assert_param(IS_DAC_ALIGN(Alignment));
  779. assert_param(IS_DAC_DATA(Data));
  780. tmp = (uint32_t)hdac->Instance;
  781. tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
  782. /* Set the DAC channel selected data holding register */
  783. *(__IO uint32_t *) tmp = Data;
  784. /* Return function status */
  785. return HAL_OK;
  786. }
  787. #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
  788. /**
  789. * @}
  790. */
  791. /**
  792. * @}
  793. */
  794. /** @addtogroup DACEx_Private
  795. * @{
  796. */
  797. #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
  798. /**
  799. * @brief DMA conversion complete callback.
  800. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  801. * the configuration information for the specified DMA module.
  802. * @retval None
  803. */
  804. static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
  805. {
  806. DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  807. HAL_DACEx_ConvCpltCallbackCh2(hdac);
  808. hdac->State= HAL_DAC_STATE_READY;
  809. }
  810. /**
  811. * @brief DMA half transfer complete callback.
  812. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  813. * the configuration information for the specified DMA module.
  814. * @retval None
  815. */
  816. static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
  817. {
  818. DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  819. /* Conversion complete callback */
  820. HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
  821. }
  822. /**
  823. * @brief DMA error callback
  824. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  825. * the configuration information for the specified DMA module.
  826. * @retval None
  827. */
  828. static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
  829. {
  830. DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  831. /* Set DAC error code to DMA error */
  832. hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
  833. HAL_DACEx_ErrorCallbackCh2(hdac);
  834. hdac->State= HAL_DAC_STATE_READY;
  835. }
  836. #endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
  837. /**
  838. * @brief DMA conversion complete callback.
  839. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  840. * the configuration information for the specified DMA module.
  841. * @retval None
  842. */
  843. static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
  844. {
  845. DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  846. HAL_DAC_ConvCpltCallbackCh1(hdac);
  847. hdac->State= HAL_DAC_STATE_READY;
  848. }
  849. /**
  850. * @brief DMA half transfer complete callback.
  851. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  852. * the configuration information for the specified DMA module.
  853. * @retval None
  854. */
  855. static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
  856. {
  857. DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  858. /* Conversion complete callback */
  859. HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
  860. }
  861. /**
  862. * @brief DMA error callback
  863. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  864. * the configuration information for the specified DMA module.
  865. * @retval None
  866. */
  867. static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
  868. {
  869. DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  870. /* Set DAC error code to DMA error */
  871. hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
  872. HAL_DAC_ErrorCallbackCh1(hdac);
  873. hdac->State= HAL_DAC_STATE_READY;
  874. }
  875. /**
  876. * @}
  877. */
  878. /**
  879. * @}
  880. */
  881. /**
  882. * @}
  883. */
  884. #endif /* HAL_DAC_MODULE_ENABLED */
  885. #endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
  886. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/