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Implement a secure ICS protocol targeting LoRa Node151 microcontroller for controlling irrigation.
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lora-irrigation/SX1276Lib/registers/sx1276Regs-LoRa.h

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  1. /*

  2.  / _____)             _              | |

  3. ( (____  _____ ____ _| |_ _____  ____| |__

  4.  \____ \| ___ |    (_   _) ___ |/ ___)  _ \

  5.  _____) ) ____| | | || |_| ____( (___| | | |

  6. (______/|_____)_|_|_| \__)_____)\____)_| |_|

  7.     (C) 2014 Semtech

  8. 

  9. Description: SX1276 LoRa modem registers and bits definitions

  10. 

  11. License: Revised BSD License, see LICENSE.TXT file include in the project

  12. 

  13. Maintainer: Miguel Luis and Gregory Cristian

  14. */

  15. #ifndef __SX1276_REGS_LORA_H__

  16. #define __SX1276_REGS_LORA_H__

  17. 

  18. /*!

  19.  * ============================================================================

  20.  * SX1276 Internal registers Address

  21.  * ============================================================================

  22.  */

  23. #define REG_LR_FIFO                                 0x00 

  24. // Common settings

  25. #define REG_LR_OPMODE                               0x01 

  26. #define REG_LR_FRFMSB                               0x06 

  27. #define REG_LR_FRFMID                               0x07

  28. #define REG_LR_FRFLSB                               0x08 

  29. // Tx settings

  30. #define REG_LR_PACONFIG                             0x09 

  31. #define REG_LR_PARAMP                               0x0A 

  32. #define REG_LR_OCP                                  0x0B 

  33. // Rx settings

  34. #define REG_LR_LNA                                  0x0C 

  35. // LoRa registers

  36. #define REG_LR_FIFOADDRPTR                          0x0D 

  37. #define REG_LR_FIFOTXBASEADDR                       0x0E 

  38. #define REG_LR_FIFORXBASEADDR                       0x0F 

  39. #define REG_LR_FIFORXCURRENTADDR                    0x10 

  40. #define REG_LR_IRQFLAGSMASK                         0x11 

  41. #define REG_LR_IRQFLAGS                             0x12 

  42. #define REG_LR_RXNBBYTES                            0x13 

  43. #define REG_LR_RXHEADERCNTVALUEMSB                  0x14 

  44. #define REG_LR_RXHEADERCNTVALUELSB                  0x15 

  45. #define REG_LR_RXPACKETCNTVALUEMSB                  0x16 

  46. #define REG_LR_RXPACKETCNTVALUELSB                  0x17 

  47. #define REG_LR_MODEMSTAT                            0x18 

  48. #define REG_LR_PKTSNRVALUE                          0x19 

  49. #define REG_LR_PKTRSSIVALUE                         0x1A 

  50. #define REG_LR_RSSIVALUE                            0x1B 

  51. #define REG_LR_HOPCHANNEL                           0x1C 

  52. #define REG_LR_MODEMCONFIG1                         0x1D 

  53. #define REG_LR_MODEMCONFIG2                         0x1E 

  54. #define REG_LR_SYMBTIMEOUTLSB                       0x1F 

  55. #define REG_LR_PREAMBLEMSB                          0x20 

  56. #define REG_LR_PREAMBLELSB                          0x21 

  57. #define REG_LR_PAYLOADLENGTH                        0x22 

  58. #define REG_LR_PAYLOADMAXLENGTH                     0x23 

  59. #define REG_LR_HOPPERIOD                            0x24 

  60. #define REG_LR_FIFORXBYTEADDR                       0x25

  61. #define REG_LR_MODEMCONFIG3                         0x26

  62. #define REG_LR_FEIMSB                               0x28

  63. #define REG_LR_FEIMID                               0x29

  64. #define REG_LR_FEILSB                               0x2A

  65. #define REG_LR_RSSIWIDEBAND                         0x2C

  66. #define REG_LR_TEST2F                               0x2F

  67. #define REG_LR_TEST30                               0x30

  68. #define REG_LR_DETECTOPTIMIZE                       0x31

  69. #define REG_LR_INVERTIQ                             0x33

  70. #define REG_LR_TEST36                               0x36

  71. #define REG_LR_DETECTIONTHRESHOLD                   0x37

  72. #define REG_LR_SYNCWORD                             0x39

  73. #define REG_LR_TEST3A                               0x3A

  74. #define REG_LR_INVERTIQ2                            0x3B

  75. 

  76. // end of documented register in datasheet

  77. // I/O settings

  78. #define REG_LR_DIOMAPPING1                          0x40

  79. #define REG_LR_DIOMAPPING2                          0x41

  80. // Version

  81. #define REG_LR_VERSION                              0x42

  82. // Additional settings

  83. #define REG_LR_PLLHOP                               0x44

  84. #define REG_LR_TCXO                                 0x4B

  85. #define REG_LR_PADAC                                0x4D

  86. #define REG_LR_FORMERTEMP                           0x5B

  87. #define REG_LR_BITRATEFRAC                          0x5D

  88. #define REG_LR_AGCREF                               0x61

  89. #define REG_LR_AGCTHRESH1                           0x62

  90. #define REG_LR_AGCTHRESH2                           0x63

  91. #define REG_LR_AGCTHRESH3                           0x64

  92. #define REG_LR_PLL                                  0x70

  93. 

  94. /*!

  95.  * ============================================================================

  96.  * SX1276 LoRa bits control definition

  97.  * ============================================================================

  98.  */

  99. 

  100. /*!

  101.  * RegFifo

  102.  */

  103. 

  104. /*!

  105.  * RegOpMode

  106.  */

  107. #define RFLR_OPMODE_LONGRANGEMODE_MASK              0x7F 

  108. #define RFLR_OPMODE_LONGRANGEMODE_OFF               0x00 // Default

  109. #define RFLR_OPMODE_LONGRANGEMODE_ON                0x80 

  110. 

  111. #define RFLR_OPMODE_ACCESSSHAREDREG_MASK            0xBF 

  112. #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE          0x40 

  113. #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE         0x00 // Default

  114. 

  115. #define RFLR_OPMODE_FREQMODE_ACCESS_MASK            0xF7

  116. #define RFLR_OPMODE_FREQMODE_ACCESS_LF              0x08 // Default

  117. #define RFLR_OPMODE_FREQMODE_ACCESS_HF              0x00 

  118. 

  119. #define RFLR_OPMODE_MASK                            0xF8 

  120. #define RFLR_OPMODE_SLEEP                           0x00 

  121. #define RFLR_OPMODE_STANDBY                         0x01 // Default

  122. #define RFLR_OPMODE_SYNTHESIZER_TX                  0x02 

  123. #define RFLR_OPMODE_TRANSMITTER                     0x03 

  124. #define RFLR_OPMODE_SYNTHESIZER_RX                  0x04 

  125. #define RFLR_OPMODE_RECEIVER                        0x05 

  126. // LoRa specific modes

  127. #define RFLR_OPMODE_RECEIVER_SINGLE                 0x06 

  128. #define RFLR_OPMODE_CAD                             0x07 

  129. 

  130. /*!

  131.  * RegFrf (MHz)

  132.  */

  133. #define RFLR_FRFMSB_434_MHZ                         0x6C // Default

  134. #define RFLR_FRFMID_434_MHZ                         0x80 // Default

  135. #define RFLR_FRFLSB_434_MHZ                         0x00 // Default

  136. 

  137. /*!

  138.  * RegPaConfig

  139.  */

  140. #define RFLR_PACONFIG_PASELECT_MASK                 0x7F 

  141. #define RFLR_PACONFIG_PASELECT_PABOOST              0x80 

  142. #define RFLR_PACONFIG_PASELECT_RFO                  0x00 // Default

  143. 

  144. #define RFLR_PACONFIG_MAX_POWER_MASK                0x8F

  145. 

  146. #define RFLR_PACONFIG_OUTPUTPOWER_MASK              0xF0 

  147.  

  148. /*!

  149.  * RegPaRamp

  150.  */

  151. #define RFLR_PARAMP_TXBANDFORCE_MASK                0xEF 

  152. #define RFLR_PARAMP_TXBANDFORCE_BAND_SEL            0x10 

  153. #define RFLR_PARAMP_TXBANDFORCE_AUTO                0x00 // Default

  154. 

  155. #define RFLR_PARAMP_MASK                            0xF0 

  156. #define RFLR_PARAMP_3400_US                         0x00 

  157. #define RFLR_PARAMP_2000_US                         0x01 

  158. #define RFLR_PARAMP_1000_US                         0x02

  159. #define RFLR_PARAMP_0500_US                         0x03 

  160. #define RFLR_PARAMP_0250_US                         0x04 

  161. #define RFLR_PARAMP_0125_US                         0x05 

  162. #define RFLR_PARAMP_0100_US                         0x06 

  163. #define RFLR_PARAMP_0062_US                         0x07 

  164. #define RFLR_PARAMP_0050_US                         0x08 

  165. #define RFLR_PARAMP_0040_US                         0x09 // Default

  166. #define RFLR_PARAMP_0031_US                         0x0A 

  167. #define RFLR_PARAMP_0025_US                         0x0B 

  168. #define RFLR_PARAMP_0020_US                         0x0C 

  169. #define RFLR_PARAMP_0015_US                         0x0D 

  170. #define RFLR_PARAMP_0012_US                         0x0E 

  171. #define RFLR_PARAMP_0010_US                         0x0F 

  172. 

  173. /*!

  174.  * RegOcp

  175.  */

  176. #define RFLR_OCP_MASK                               0xDF 

  177. #define RFLR_OCP_ON                                 0x20 // Default

  178. #define RFLR_OCP_OFF                                0x00   

  179. 

  180. #define RFLR_OCP_TRIM_MASK                          0xE0

  181. #define RFLR_OCP_TRIM_045_MA                        0x00

  182. #define RFLR_OCP_TRIM_050_MA                        0x01   

  183. #define RFLR_OCP_TRIM_055_MA                        0x02 

  184. #define RFLR_OCP_TRIM_060_MA                        0x03 

  185. #define RFLR_OCP_TRIM_065_MA                        0x04 

  186. #define RFLR_OCP_TRIM_070_MA                        0x05 

  187. #define RFLR_OCP_TRIM_075_MA                        0x06 

  188. #define RFLR_OCP_TRIM_080_MA                        0x07  

  189. #define RFLR_OCP_TRIM_085_MA                        0x08

  190. #define RFLR_OCP_TRIM_090_MA                        0x09 

  191. #define RFLR_OCP_TRIM_095_MA                        0x0A 

  192. #define RFLR_OCP_TRIM_100_MA                        0x0B  // Default

  193. #define RFLR_OCP_TRIM_105_MA                        0x0C 

  194. #define RFLR_OCP_TRIM_110_MA                        0x0D 

  195. #define RFLR_OCP_TRIM_115_MA                        0x0E 

  196. #define RFLR_OCP_TRIM_120_MA                        0x0F 

  197. #define RFLR_OCP_TRIM_130_MA                        0x10

  198. #define RFLR_OCP_TRIM_140_MA                        0x11   

  199. #define RFLR_OCP_TRIM_150_MA                        0x12 

  200. #define RFLR_OCP_TRIM_160_MA                        0x13 

  201. #define RFLR_OCP_TRIM_170_MA                        0x14 

  202. #define RFLR_OCP_TRIM_180_MA                        0x15 

  203. #define RFLR_OCP_TRIM_190_MA                        0x16 

  204. #define RFLR_OCP_TRIM_200_MA                        0x17  

  205. #define RFLR_OCP_TRIM_210_MA                        0x18

  206. #define RFLR_OCP_TRIM_220_MA                        0x19 

  207. #define RFLR_OCP_TRIM_230_MA                        0x1A 

  208. #define RFLR_OCP_TRIM_240_MA                        0x1B

  209. 

  210. /*!

  211.  * RegLna

  212.  */

  213. #define RFLR_LNA_GAIN_MASK                          0x1F 

  214. #define RFLR_LNA_GAIN_G1                            0x20 // Default

  215. #define RFLR_LNA_GAIN_G2                            0x40 

  216. #define RFLR_LNA_GAIN_G3                            0x60 

  217. #define RFLR_LNA_GAIN_G4                            0x80 

  218. #define RFLR_LNA_GAIN_G5                            0xA0 

  219. #define RFLR_LNA_GAIN_G6                            0xC0 

  220. 

  221. #define RFLR_LNA_BOOST_LF_MASK                      0xE7 

  222. #define RFLR_LNA_BOOST_LF_DEFAULT                   0x00 // Default

  223. 

  224. #define RFLR_LNA_BOOST_HF_MASK                      0xFC 

  225. #define RFLR_LNA_BOOST_HF_OFF                       0x00 // Default

  226. #define RFLR_LNA_BOOST_HF_ON                        0x03 

  227. 

  228. /*!

  229.  * RegFifoAddrPtr

  230.  */

  231. #define RFLR_FIFOADDRPTR                            0x00 // Default

  232. 

  233. /*!

  234.  * RegFifoTxBaseAddr

  235.  */

  236. #define RFLR_FIFOTXBASEADDR                         0x80 // Default

  237. 

  238. /*!

  239.  * RegFifoTxBaseAddr

  240.  */

  241. #define RFLR_FIFORXBASEADDR                         0x00 // Default

  242. 

  243. /*!

  244.  * RegFifoRxCurrentAddr (Read Only)

  245.  */

  246. 

  247. /*!

  248.  * RegIrqFlagsMask

  249.  */

  250. #define RFLR_IRQFLAGS_RXTIMEOUT_MASK                0x80 

  251. #define RFLR_IRQFLAGS_RXDONE_MASK                   0x40 

  252. #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK          0x20 

  253. #define RFLR_IRQFLAGS_VALIDHEADER_MASK              0x10 

  254. #define RFLR_IRQFLAGS_TXDONE_MASK                   0x08 

  255. #define RFLR_IRQFLAGS_CADDONE_MASK                  0x04 

  256. #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK       0x02 

  257. #define RFLR_IRQFLAGS_CADDETECTED_MASK              0x01 

  258. 

  259. /*!

  260.  * RegIrqFlags

  261.  */

  262. #define RFLR_IRQFLAGS_RXTIMEOUT                     0x80 

  263. #define RFLR_IRQFLAGS_RXDONE                        0x40 

  264. #define RFLR_IRQFLAGS_PAYLOADCRCERROR               0x20 

  265. #define RFLR_IRQFLAGS_VALIDHEADER                   0x10 

  266. #define RFLR_IRQFLAGS_TXDONE                        0x08 

  267. #define RFLR_IRQFLAGS_CADDONE                       0x04 

  268. #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL            0x02 

  269. #define RFLR_IRQFLAGS_CADDETECTED                   0x01 

  270. 

  271. /*!

  272.  * RegFifoRxNbBytes (Read Only)

  273.  */

  274. 

  275. /*!

  276.  * RegRxHeaderCntValueMsb (Read Only)

  277.  */

  278. 

  279. /*!

  280.  * RegRxHeaderCntValueLsb (Read Only)

  281.  */

  282. 

  283. /*!

  284.  * RegRxPacketCntValueMsb (Read Only)

  285.  */

  286. 

  287. /*!

  288.  * RegRxPacketCntValueLsb (Read Only)

  289.  */

  290. 

  291. /*!

  292.  * RegModemStat (Read Only)

  293.  */

  294. #define RFLR_MODEMSTAT_RX_CR_MASK                   0x1F 

  295. #define RFLR_MODEMSTAT_MODEM_STATUS_MASK            0xE0 

  296.  

  297. /*!

  298.  * RegPktSnrValue (Read Only)

  299.  */

  300. 

  301. /*!

  302.  * RegPktRssiValue (Read Only)

  303.  */

  304. 

  305. /*!

  306.  * RegRssiValue (Read Only)

  307.  */

  308. 

  309. /*!

  310.  * RegHopChannel (Read Only)

  311.  */

  312. #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK       0x7F 

  313. #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL               0x80 

  314. #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED            0x00 // Default

  315.                                                     

  316. #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK           0xBF

  317. #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON             0x40

  318. #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF            0x00 // Default

  319. 

  320. #define RFLR_HOPCHANNEL_CHANNEL_MASK                0x3F 

  321. 

  322. /*!

  323.  * RegModemConfig1

  324.  */

  325. #define RFLR_MODEMCONFIG1_BW_MASK                   0x0F 

  326. #define RFLR_MODEMCONFIG1_BW_7_81_KHZ               0x00 

  327. #define RFLR_MODEMCONFIG1_BW_10_41_KHZ              0x10 

  328. #define RFLR_MODEMCONFIG1_BW_15_62_KHZ              0x20 

  329. #define RFLR_MODEMCONFIG1_BW_20_83_KHZ              0x30 

  330. #define RFLR_MODEMCONFIG1_BW_31_25_KHZ              0x40 

  331. #define RFLR_MODEMCONFIG1_BW_41_66_KHZ              0x50 

  332. #define RFLR_MODEMCONFIG1_BW_62_50_KHZ              0x60 

  333. #define RFLR_MODEMCONFIG1_BW_125_KHZ                0x70 // Default

  334. #define RFLR_MODEMCONFIG1_BW_250_KHZ                0x80 

  335. #define RFLR_MODEMCONFIG1_BW_500_KHZ                0x90 

  336.                                                     

  337. #define RFLR_MODEMCONFIG1_CODINGRATE_MASK           0xF1 

  338. #define RFLR_MODEMCONFIG1_CODINGRATE_4_5            0x02

  339. #define RFLR_MODEMCONFIG1_CODINGRATE_4_6            0x04 // Default

  340. #define RFLR_MODEMCONFIG1_CODINGRATE_4_7            0x06 

  341. #define RFLR_MODEMCONFIG1_CODINGRATE_4_8            0x08 

  342.                                                     

  343. #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK       0xFE 

  344. #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON         0x01 

  345. #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF        0x00 // Default

  346. 

  347. /*!

  348.  * RegModemConfig2

  349.  */

  350. #define RFLR_MODEMCONFIG2_SF_MASK                   0x0F 

  351. #define RFLR_MODEMCONFIG2_SF_6                      0x60 

  352. #define RFLR_MODEMCONFIG2_SF_7                      0x70 // Default

  353. #define RFLR_MODEMCONFIG2_SF_8                      0x80 

  354. #define RFLR_MODEMCONFIG2_SF_9                      0x90 

  355. #define RFLR_MODEMCONFIG2_SF_10                     0xA0 

  356. #define RFLR_MODEMCONFIG2_SF_11                     0xB0 

  357. #define RFLR_MODEMCONFIG2_SF_12                     0xC0 

  358. 

  359. #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK     0xF7 

  360. #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON       0x08 

  361. #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF      0x00 

  362. 

  363. #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK         0xFB 

  364. #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON           0x04 

  365. #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF          0x00 // Default

  366.  

  367. #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK       0xFC 

  368. #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB            0x00 // Default

  369. 

  370. /*!

  371.  * RegSymbTimeoutLsb

  372.  */

  373. #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT             0x64 // Default

  374. 

  375. /*!

  376.  * RegPreambleLengthMsb

  377.  */

  378. #define RFLR_PREAMBLELENGTHMSB                      0x00 // Default

  379. 

  380. /*!

  381.  * RegPreambleLengthLsb

  382.  */

  383. #define RFLR_PREAMBLELENGTHLSB                      0x08 // Default

  384. 

  385. /*!

  386.  * RegPayloadLength

  387.  */

  388. #define RFLR_PAYLOADLENGTH                          0x0E // Default

  389. 

  390. /*!

  391.  * RegPayloadMaxLength

  392.  */

  393. #define RFLR_PAYLOADMAXLENGTH                       0xFF // Default

  394. 

  395. /*!

  396.  * RegHopPeriod

  397.  */

  398. #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD            0x00 // Default

  399. 

  400. /*!

  401.  * RegFifoRxByteAddr (Read Only)

  402.  */

  403. 

  404. /*!

  405.  * RegModemConfig3

  406.  */

  407. #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK  0xF7 

  408. #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON    0x08 

  409. #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF   0x00 // Default

  410. 

  411. #define RFLR_MODEMCONFIG3_AGCAUTO_MASK              0xFB 

  412. #define RFLR_MODEMCONFIG3_AGCAUTO_ON                0x04 // Default 

  413. #define RFLR_MODEMCONFIG3_AGCAUTO_OFF               0x00 

  414. 

  415. /*!

  416.  * RegFeiMsb (Read Only)

  417.  */

  418. 

  419. /*!

  420.  * RegFeiMid (Read Only)

  421.  */

  422. 

  423. /*!

  424.  * RegFeiLsb (Read Only)

  425.  */

  426. 

  427. /*!

  428.  * RegRssiWideband (Read Only)

  429.  */

  430. 

  431. /*!

  432.  * RegDetectOptimize

  433.  */

  434. #define RFLR_DETECTIONOPTIMIZE_MASK                 0xF8

  435. #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12          0x03 // Default

  436. #define RFLR_DETECTIONOPTIMIZE_SF6                  0x05

  437. 

  438. /*!

  439.  * RegInvertIQ

  440.  */

  441. #define RFLR_INVERTIQ_RX_MASK                       0xBF

  442. #define RFLR_INVERTIQ_RX_OFF                        0x00

  443. #define RFLR_INVERTIQ_RX_ON                         0x40

  444. #define RFLR_INVERTIQ_TX_MASK                       0xFE

  445. #define RFLR_INVERTIQ_TX_OFF                        0x01

  446. #define RFLR_INVERTIQ_TX_ON                         0x00

  447. 

  448. /*!

  449.  * RegDetectionThreshold

  450.  */

  451. #define RFLR_DETECTIONTHRESH_SF7_TO_SF12            0x0A // Default

  452. #define RFLR_DETECTIONTHRESH_SF6                    0x0C

  453. 

  454. /*!

  455.  * RegInvertIQ2

  456.  */

  457. #define RFLR_INVERTIQ2_ON                           0x19

  458. #define RFLR_INVERTIQ2_OFF                          0x1D

  459. 

  460. /*!

  461.  * RegDioMapping1

  462.  */

  463. #define RFLR_DIOMAPPING1_DIO0_MASK                  0x3F

  464. #define RFLR_DIOMAPPING1_DIO0_00                    0x00  // Default

  465. #define RFLR_DIOMAPPING1_DIO0_01                    0x40

  466. #define RFLR_DIOMAPPING1_DIO0_10                    0x80

  467. #define RFLR_DIOMAPPING1_DIO0_11                    0xC0

  468. 

  469. #define RFLR_DIOMAPPING1_DIO1_MASK                  0xCF

  470. #define RFLR_DIOMAPPING1_DIO1_00                    0x00  // Default

  471. #define RFLR_DIOMAPPING1_DIO1_01                    0x10

  472. #define RFLR_DIOMAPPING1_DIO1_10                    0x20

  473. #define RFLR_DIOMAPPING1_DIO1_11                    0x30

  474. 

  475. #define RFLR_DIOMAPPING1_DIO2_MASK                  0xF3

  476. #define RFLR_DIOMAPPING1_DIO2_00                    0x00  // Default

  477. #define RFLR_DIOMAPPING1_DIO2_01                    0x04

  478. #define RFLR_DIOMAPPING1_DIO2_10                    0x08

  479. #define RFLR_DIOMAPPING1_DIO2_11                    0x0C

  480. 

  481. #define RFLR_DIOMAPPING1_DIO3_MASK                  0xFC

  482. #define RFLR_DIOMAPPING1_DIO3_00                    0x00  // Default

  483. #define RFLR_DIOMAPPING1_DIO3_01                    0x01

  484. #define RFLR_DIOMAPPING1_DIO3_10                    0x02

  485. #define RFLR_DIOMAPPING1_DIO3_11                    0x03

  486. 

  487. /*!

  488.  * RegDioMapping2

  489.  */

  490. #define RFLR_DIOMAPPING2_DIO4_MASK                  0x3F

  491. #define RFLR_DIOMAPPING2_DIO4_00                    0x00  // Default

  492. #define RFLR_DIOMAPPING2_DIO4_01                    0x40

  493. #define RFLR_DIOMAPPING2_DIO4_10                    0x80

  494. #define RFLR_DIOMAPPING2_DIO4_11                    0xC0

  495. 

  496. #define RFLR_DIOMAPPING2_DIO5_MASK                  0xCF

  497. #define RFLR_DIOMAPPING2_DIO5_00                    0x00  // Default

  498. #define RFLR_DIOMAPPING2_DIO5_01                    0x10

  499. #define RFLR_DIOMAPPING2_DIO5_10                    0x20

  500. #define RFLR_DIOMAPPING2_DIO5_11                    0x30

  501. 

  502. #define RFLR_DIOMAPPING2_MAP_MASK                   0xFE

  503. #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT         0x01

  504. #define RFLR_DIOMAPPING2_MAP_RSSI                   0x00  // Default

  505. 

  506. /*!

  507.  * RegVersion (Read Only)

  508.  */

  509. 

  510. /*!

  511.  * RegPllHop

  512.  */

  513. #define RFLR_PLLHOP_FASTHOP_MASK                    0x7F

  514. #define RFLR_PLLHOP_FASTHOP_ON                      0x80

  515. #define RFLR_PLLHOP_FASTHOP_OFF                     0x00 // Default

  516. 

  517. /*!

  518.  * RegTcxo

  519.  */

  520. #define RFLR_TCXO_TCXOINPUT_MASK                    0xEF

  521. #define RFLR_TCXO_TCXOINPUT_ON                      0x10

  522. #define RFLR_TCXO_TCXOINPUT_OFF                     0x00  // Default

  523. 

  524. /*!

  525.  * RegPaDac

  526.  */

  527. #define RFLR_PADAC_20DBM_MASK                       0xF8

  528. #define RFLR_PADAC_20DBM_ON                         0x07

  529. #define RFLR_PADAC_20DBM_OFF                        0x04  // Default

  530. 

  531. /*!

  532.  * RegFormerTemp

  533.  */

  534. 

  535. /*!

  536.  * RegBitrateFrac

  537.  */

  538. #define RF_BITRATEFRAC_MASK                         0xF0

  539. 

  540. /*!

  541.  * RegAgcRef

  542.  */

  543. 

  544. /*!

  545.  * RegAgcThresh1

  546.  */

  547. 

  548. /*!

  549.  * RegAgcThresh2

  550.  */

  551. 

  552. /*!

  553.  * RegAgcThresh3

  554.  */

  555. 

  556. /*!

  557.  * RegPll

  558.  */

  559. #define RF_PLL_BANDWIDTH_MASK                       0x3F

  560. #define RF_PLL_BANDWIDTH_75                         0x00

  561. #define RF_PLL_BANDWIDTH_150                        0x40

  562. #define RF_PLL_BANDWIDTH_225                        0x80

  563. #define RF_PLL_BANDWIDTH_300                        0xC0  // Default

  564. 

  565. #endif // __SX1276_REGS_LORA_H__