Import STM32Cube_FW_L4_V1.8.0 on 21-Apr-2017

CMSIS/STM32L4xx/Include/stm32l4xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32l4xx.h
   * @author  MCD Application Team
-  * @version V1.0.3
-  * @date    29-January-2016
+  * @version V1.3.1
+  * @date    21-April-2017
   * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
   *
   *          The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -75,12 +75,25 @@
    application
   */
 
-#if !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx)
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+    !defined (STM32L496xx) && !defined (STM32L4A6xx)
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */
+  /* #define STM32L432xx */   /*!< STM32L432xx Devices */
+  /* #define STM32L433xx */   /*!< STM32L433xx Devices */
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */
+  /* #define STM32L451xx */   /*!< STM32L451xx Devices */
+  /* #define STM32L452xx */   /*!< STM32L452xx Devices */
+  /* #define STM32L462xx */   /*!< STM32L462xx Devices */
   /* #define STM32L471xx */   /*!< STM32L471xx Devices */
   /* #define STM32L475xx */   /*!< STM32L475xx Devices */
   /* #define STM32L476xx */   /*!< STM32L476xx Devices */
   /* #define STM32L485xx */   /*!< STM32L485xx Devices */
   /* #define STM32L486xx */   /*!< STM32L486xx Devices */
+  /* #define STM32L496xx */   /*!< STM32L496xx Devices */
+  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */
 #endif
 
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -96,11 +109,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.0.3
+  * @brief CMSIS Device version number V1.3.1
   */
 #define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L4_CMSIS_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32L4_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
 #define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
@@ -115,7 +128,23 @@
   * @{
   */
 
-#if defined(STM32L471xx)
+#if defined(STM32L431xx)
+  #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+  #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+  #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+  #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+  #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+  #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+  #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+  #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
   #include "stm32l471xx.h"
 #elif defined(STM32L475xx)
   #include "stm32l475xx.h"
@@ -125,6 +154,10 @@
   #include "stm32l485xx.h"
 #elif defined(STM32L486xx)
   #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+  #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+  #include "stm32l4a6xx.h"
 #else
  #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
 #endif

CMSIS/STM32L4xx/Include/system_stm32l4xx.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    system_stm32l4xx.h
   * @author  MCD Application Team
-  * @version V1.0.3
-  * @date    29-January-2016
+  * @version V1.3.1
+  * @date    21-April-2017
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h

@@ -0,0 +1,75 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   STM32 assert template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32_assert.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(char *file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h

@@ -2,14 +2,14 @@
   ******************************************************************************
   * @file    stm32l4xx_hal.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   This file contains all the functions prototypes for the HAL
   *          module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -66,8 +66,15 @@
   */
 #define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000)
 #define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
 #define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
+
 #define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
 
 /**
@@ -88,7 +95,7 @@
   * @}
   */
 
-/** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection
+/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
   * @{
   */
 #define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
@@ -107,6 +114,7 @@
 #define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
 #define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
 #define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
+#if defined(SYSCFG_SWPR_PAGE31)
 #define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
 #define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
 #define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
@@ -123,10 +131,53 @@
 #define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
 #define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
 #define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
+#endif /* SYSCFG_SWPR_PAGE31 */
+
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_SWPR2_PAGE63)
+/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
+  * @{
+  */
+#define SYSCFG_SRAM2WRP_PAGE32         SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
+#define SYSCFG_SRAM2WRP_PAGE33         SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
+#define SYSCFG_SRAM2WRP_PAGE34         SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
+#define SYSCFG_SRAM2WRP_PAGE35         SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
+#define SYSCFG_SRAM2WRP_PAGE36         SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
+#define SYSCFG_SRAM2WRP_PAGE37         SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
+#define SYSCFG_SRAM2WRP_PAGE38         SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
+#define SYSCFG_SRAM2WRP_PAGE39         SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
+#define SYSCFG_SRAM2WRP_PAGE40         SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
+#define SYSCFG_SRAM2WRP_PAGE41         SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
+#define SYSCFG_SRAM2WRP_PAGE42         SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
+#define SYSCFG_SRAM2WRP_PAGE43         SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
+#define SYSCFG_SRAM2WRP_PAGE44         SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
+#define SYSCFG_SRAM2WRP_PAGE45         SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
+#define SYSCFG_SRAM2WRP_PAGE46         SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
+#define SYSCFG_SRAM2WRP_PAGE47         SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
+#define SYSCFG_SRAM2WRP_PAGE48         SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
+#define SYSCFG_SRAM2WRP_PAGE49         SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
+#define SYSCFG_SRAM2WRP_PAGE50         SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
+#define SYSCFG_SRAM2WRP_PAGE51         SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
+#define SYSCFG_SRAM2WRP_PAGE52         SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
+#define SYSCFG_SRAM2WRP_PAGE53         SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
+#define SYSCFG_SRAM2WRP_PAGE54         SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
+#define SYSCFG_SRAM2WRP_PAGE55         SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
+#define SYSCFG_SRAM2WRP_PAGE56         SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
+#define SYSCFG_SRAM2WRP_PAGE57         SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
+#define SYSCFG_SRAM2WRP_PAGE58         SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
+#define SYSCFG_SRAM2WRP_PAGE59         SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
+#define SYSCFG_SRAM2WRP_PAGE60         SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
+#define SYSCFG_SRAM2WRP_PAGE61         SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
+#define SYSCFG_SRAM2WRP_PAGE62         SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
+#define SYSCFG_SRAM2WRP_PAGE63         SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
 
 /**
   * @}
   */
+#endif /* SYSCFG_SWPR2_PAGE63 */
 
 #if defined(VREFBUF)
 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
@@ -166,7 +217,7 @@
   */
 
 /** @brief  Fast-mode Plus driving capability on a specific GPIO
-  */  
+  */
 #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
 #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
@@ -252,11 +303,21 @@
 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
 #endif
 
+#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#endif
+
 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
 #define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
 #define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
 #endif
 
+#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_FREEZE_CAN2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
+#endif
+
 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
 #define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
 #define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
@@ -312,10 +373,16 @@
   */
 #define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
 
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+
 /** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
   */
 #define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
 
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
 /** @brief  QUADSPI mapped at 0x00000000.
   */
 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
@@ -326,20 +393,32 @@
   *         of the following values:
   *           @arg @ref SYSCFG_BOOT_MAINFLASH
   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
+  @if STM32L486xx
   *           @arg @ref SYSCFG_BOOT_FMC
+  @endif
   *           @arg @ref SYSCFG_BOOT_SRAM
   *           @arg @ref SYSCFG_BOOT_QUADSPI
   */
 #define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
 
-/** @brief  SRAM2 page write protection enable macro
-  * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP
-  * @note   write protection can only be disabled by a system reset
+/** @brief  SRAM2 page 0 to 31 write protection enable macro
+  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
+  * @note   Write protection can only be disabled by a system reset
   */
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
+#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
                                                          SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
                                                         }while(0)
 
+#if defined(SYSCFG_SWPR2_PAGE63)
+/** @brief  SRAM2 page 32 to 63 write protection enable macro
+  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
+  * @note   Write protection can only be disabled by a system reset
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
+                                                                SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
+                                                            }while(0)
+#endif /* SYSCFG_SWPR2_PAGE63 */
+
 /** @brief  SRAM2 page write protection unlock prior to erase
   * @note   Writing a wrong key reactivates the write protection
   */
@@ -401,9 +480,9 @@
 #define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
 
 /** @brief  Fast-mode Plus driving capability enable/disable macros
-  * @param __FASTMODEPLUS__: This parameter can be a value of : 
+  * @param __FASTMODEPLUS__: This parameter can be a value of :
   *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
-  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
   *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
   *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
   */
@@ -503,6 +582,9 @@ void HAL_ResumeTick(void);
 uint32_t HAL_GetHalVersion(void);
 uint32_t HAL_GetREVID(void);
 uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
 
 /**
   * @}

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_can.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of CAN HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -155,7 +155,7 @@ typedef struct
                                        This parameter can be set to ENABLE or DISABLE */
 
   uint32_t BankNumber;            /*!< Select the start slave bank filter.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ 
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
 
 }CAN_FilterConfTypeDef;
 
@@ -204,7 +204,7 @@ typedef struct
   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
                              This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
 
-  uint32_t Data[8];     /*!< Contains the data to be received.
+  uint8_t Data[8];      /*!< Contains the data to be received.
                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
 
   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
@@ -595,7 +595,7 @@ typedef struct
   * @retval None
   */
 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
 
 /**
   * @brief  Cancel a transmit request.
@@ -611,29 +611,29 @@ typedef struct
 /**
   * @brief  Enable or disable the DBG Freeze for CAN.
   * @param  __HANDLE__: specifies the CAN Handle.
-  * @param  __NEWSTATE__: new state of the CAN peripheral. 
+  * @param  __NEWSTATE__: new state of the CAN peripheral.
   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
-  *         during debug. Reception FIFO can still be accessed/controlled normally) 
+  *         during debug. Reception FIFO can still be accessed/controlled normally)
   *         or DISABLE (CAN is working during debug).
   * @retval None
   */
 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
 
 /**
  * @}
- */  
- 
-/* Exported functions --------------------------------------------------------*/  
+ */
+
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup CAN_Exported_Functions CAN Exported Functions
   * @{
   */
-  
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  * @{
  */
-/* addtogroup and de-initialization functions *****************************/ 
+/* addtogroup and de-initialization functions *****************************/
 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
@@ -641,10 +641,10 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
 /**
  * @}
- */ 
- 
+ */
+
 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    I/O operation functions 
+ *  @brief    I/O operation functions
  * @{
  */
 /* IO operation functions *****************************************************/
@@ -660,10 +660,10 @@ void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
 /**
  * @}
- */ 
- 
+ */
+
 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions 
+ *  @brief   CAN Peripheral State functions
  * @{
  */
 /* Peripheral State and Error functions ***************************************/
@@ -671,11 +671,11 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
 /**
  * @}
- */ 
+ */
 
 /**
  * @}
- */ 
+ */
 
 /* Private types -------------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h

@@ -0,0 +1,790 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_comp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of COMP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_COMP_H
+#define __STM32L4xx_HAL_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Types COMP Exported Types
+  * @{
+  */
+
+/**
+  * @brief  COMP Init structure definition
+  */
+typedef struct
+{
+
+  uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
+                                    (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
+                                    Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
+                                    This parameter can be a value of @ref COMP_WindowMode */
+
+  uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
+                                    Note: For the characteritics of comparator power modes
+                                          (propagation delay and power consumption), refer to device datasheet.
+                                    This parameter can be a value of @ref COMP_PowerMode */
+
+  uint32_t NonInvertingInput;  /*!< Set comparator input plus (non-inverting input).
+                                    This parameter can be a value of @ref COMP_InputPlus */
+
+  uint32_t InvertingInput;     /*!< Set comparator input minus (inverting input).
+                                    This parameter can be a value of @ref COMP_InputMinus */
+
+  uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
+                                    This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t OutputPol;          /*!< Set comparator output polarity.
+                                    This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t BlankingSrce;       /*!< Set comparator blanking source.
+                                    This parameter can be a value of @ref COMP_BlankingSrce */
+
+  uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
+                                    This parameter can be a value of @ref COMP_EXTI_TriggerMode */
+
+}COMP_InitTypeDef;
+
+/**
+  * @brief  HAL COMP state machine: HAL COMP states definition
+  */
+#define COMP_STATE_BITFIELD_LOCK  ((uint32_t)0x10)
+typedef enum
+{
+  HAL_COMP_STATE_RESET             = 0x00,                                              /*!< COMP not yet initialized                             */
+  HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
+  HAL_COMP_STATE_READY             = 0x01,                                              /*!< COMP initialized and ready for use                   */
+  HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
+  HAL_COMP_STATE_BUSY              = 0x02,                                              /*!< COMP is running                                      */
+  HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
+}HAL_COMP_StateTypeDef;
+
+/**
+  * @brief  COMP Handle Structure definition
+  */
+typedef struct
+{
+  COMP_TypeDef       *Instance;       /*!< Register base address    */
+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
+  HAL_LockTypeDef    Lock;            /*!< Locking object           */
+  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
+} COMP_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_WindowMode COMP Window Mode
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
+#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_PowerMode COMP power mode
+  * @{
+  */
+/* Note: For the characteritics of comparator power modes                     */
+/*       (propagation delay and power consumption),                           */
+/*       refer to device datasheet.                                           */
+#define COMP_POWERMODE_HIGHSPEED       ((uint32_t)0x00000000) /*!< High Speed */
+#define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_PWRMODE_0)   /*!< Medium Speed */
+#define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CSR_PWRMODE)     /*!< Ultra-low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
+  * @{
+  */
+#define COMP_INPUT_PLUS_IO1            ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
+#define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL_0)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
+#if defined(COMP_CSR_INPSEL_1)
+#define COMP_INPUT_PLUS_IO3            (COMP_CSR_INPSEL_1)    /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputMinus COMP input minus (inverting input)
+  * @{
+  */
+#define COMP_INPUT_MINUS_1_4VREFINT    (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
+#define COMP_INPUT_MINUS_1_2VREFINT    (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
+#define COMP_INPUT_MINUS_3_4VREFINT    (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
+#define COMP_INPUT_MINUS_VREFINT       (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
+#define COMP_INPUT_MINUS_DAC1_CH1      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define COMP_INPUT_MINUS_DAC1_CH2      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#endif
+#define COMP_INPUT_MINUS_IO1           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
+#define COMP_INPUT_MINUS_IO2           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
+#if defined(COMP_CSR_INMESEL_1)
+#define COMP_INPUT_MINUS_IO3           (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
+#define COMP_INPUT_MINUS_IO4           (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
+#define COMP_INPUT_MINUS_IO5           (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Hysteresis COMP hysteresis
+  * @{
+  */
+#define COMP_HYSTERESIS_NONE           ((uint32_t)0x00000000) /*!< No hysteresis */
+#define COMP_HYSTERESIS_LOW            (COMP_CSR_HYST_0)      /*!< Hysteresis level low */
+#define COMP_HYSTERESIS_MEDIUM         (COMP_CSR_HYST_1)      /*!< Hysteresis level medium */
+#define COMP_HYSTERESIS_HIGH           (COMP_CSR_HYST)        /*!< Hysteresis level high */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputPolarity COMP output Polarity
+  * @{
+  */
+#define COMP_OUTPUTPOL_NONINVERTED     ((uint32_t)0x00000000) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
+#define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_BlankingSrce  COMP blanking source
+  * @{
+  */
+/* Note: Some blanking sources are not available depending on timer           */
+/*       availability or devices specificities                                */
+/*       (STM32L43xx, STM32L44xx, STM32L45xx, STM32L46xx)                     */
+#define COMP_BLANKINGSRC_NONE                    ((uint32_t)0x00000000) /*!< No blanking source */
+/* Blanking sources for COMP instance: COMP1 */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP1          (COMP_CSR_BLANKING_0)  /*!< Blanking source for COMP1: TIM1 OC5 selected as blanking source for comparator */
+#define COMP_BLANKINGSRC_TIM2_OC3_COMP1          (COMP_CSR_BLANKING_1)  /*!< Blanking source for COMP1: TIM2 OC3 selected as blanking source for comparator */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define COMP_BLANKINGSRC_TIM3_OC3_COMP1          (COMP_CSR_BLANKING_2)  /*!< Blanking source for COMP1: TIM3 OC3 selected as blanking source for comparator */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+
+/* Blanking sources for COMP instance: COMP2 */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define COMP_BLANKINGSRC_TIM3_OC4_COMP2          (COMP_CSR_BLANKING_0)  /*!< Blanking source for COMP2: TIM3 OC4 selected as blanking source for comparator */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP2          (COMP_CSR_BLANKING_1)  /*!< Blanking source for COMP2: TIM8 OC5 selected as blanking source for comparator */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+#define COMP_BLANKINGSRC_TIM15_OC1_COMP2         (COMP_CSR_BLANKING_2)  /*!< Blanking source for COMP2: TIM15 OC1 selected as blanking source for comparator */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel COMP Output Level
+  * @{
+  */
+/* Note: Comparator output level values are fixed to "0" and "1",             */
+/* corresponding COMP register bit is managed by HAL function to match        */
+/* with these values (independently of bit position in register).             */
+
+/* When output polarity is not inverted, comparator output is low when
+   the input plus is at a lower voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_LOW              ((uint32_t)0x00000000)
+/* When output polarity is not inverted, comparator output is high when
+   the input plus is at a higher voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_HIGH             ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
+  * @{
+  */
+#define COMP_TRIGGERMODE_NONE                 ((uint32_t)0x00000000)                                    /*!< Comparator output triggering no External Interrupt Line */
+#define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
+#define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
+#define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
+#define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+  * @{
+  */
+
+/** @defgroup COMP_Handle_Management  COMP Handle Management
+  * @{
+  */
+
+/** @brief  Reset COMP handle state.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+
+/**
+  * @brief  Enable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+  * @brief  Disable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+  * @brief  Lock the specified comparator configuration.
+  * @note   Using this macro induce HAL COMP handle state machine being no
+  *         more in line with COMP instance state.
+  *         To keep HAL COMP handle state machine updated, it is recommended
+  *         to use function "HAL_COMP_Lock')".
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
+
+/**
+  * @brief  Check whether the specified comparator is locked.
+  * @param  __HANDLE__  COMP handle
+  * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
+  */
+#define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exti_Management  COMP external interrupt line management
+  * @{
+  */
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Generate a software interrupt on the COMP1 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Check whether the COMP1 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Clear the COMP1 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Generate a software interrupt on the COMP2 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Check whether the COMP2 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Clear the COMP2 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+  * @{
+  */
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_LINE_COMP1           (EXTI_IMR1_IM21)  /*!< EXTI line 21 connected to COMP1 output */
+#define COMP_EXTI_LINE_COMP2           (EXTI_IMR1_IM22)  /*!< EXTI line 22 connected to COMP2 output */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_IT                        ((uint32_t) 0x01)  /*!< EXTI line event with interruption */
+#define COMP_EXTI_EVENT                     ((uint32_t) 0x02)  /*!< EXTI line event only (without interruption) */
+#define COMP_EXTI_RISING                    ((uint32_t) 0x10)  /*!< EXTI line event on rising edge */
+#define COMP_EXTI_FALLING                   ((uint32_t) 0x20)  /*!< EXTI line event on falling edge */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+  * @{
+  */
+
+/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
+  * @{
+  */
+/**
+  * @brief  Get the specified EXTI line for a comparator instance.
+  * @param  __INSTANCE__  specifies the COMP instance.
+  * @retval value of @ref COMP_ExtiLine
+  */
+#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ?                 \
+                                             COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
+  * @{
+  */
+#define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
+                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
+
+#define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
+                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
+                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
+
+#if defined(COMP_CSR_INPSEL_1)
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
+#else
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
+#endif
+
+/* Note: On this STM32 family, comparator input minus parameters are          */
+/*       the same on all COMP instances.                                      */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#if defined(COMP_CSR_INMESEL_1) && defined(DAC_CHANNEL2_SUPPORT)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
+#elif defined(COMP_CSR_INMESEL_1)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
+#elif defined(DAC_CHANNEL2_SUPPORT)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
+#else
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
+#endif
+
+#define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
+
+#define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
+                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
+
+#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
+
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)  \
+   ((((__INSTANCE__) == COMP1) &&                                     \
+    (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)))        \
+    ||                                                                \
+    (((__INSTANCE__) == COMP2) &&                                     \
+     (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)           ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
+
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+
+#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
+
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)  \
+   ((((__INSTANCE__) == COMP1) &&                                     \
+    (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)))        \
+    ||                                                                \
+    (((__INSTANCE__) == COMP2) &&                                     \
+     (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)           ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
+
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)  || \
+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
+
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)  \
+   ((((__INSTANCE__) == COMP1) &&                                     \
+    (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)))        \
+    ||                                                                \
+    (((__INSTANCE__) == COMP2) &&                                     \
+     (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)           ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) ||      \
+      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+       /* STM32L496xx || STM32L4A6xx */
+
+#define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
+
+#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
+                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMP_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup COMP_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup COMP_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+/* Callback in interrupt mode */
+void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  **************************************************/
+/** @addtogroup COMP_Exported_Functions_Group4
+  * @{
+  */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h

@@ -0,0 +1,408 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32l4xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CONF_H
+#define __STM32L4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_FIREWALL_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LCD_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SWPMI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE   ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+  #define LSI_VALUE  ((uint32_t)32000U)      /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                       /*!< Value of the Internal Low Speed oscillator in Hz
+                                              The real value may vary depending on the variations
+                                              in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)  /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/**
+  * @brief External clock source for SAI2 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
+  #define EXTERNAL_SAI2_CLOCK_VALUE    ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              0U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT               1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32l4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32l4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32l4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32l4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+  #include "stm32l4xx_hal_firewall.h"
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32l4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32l4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32l4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32l4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+  #include "stm32l4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+  #include "stm32l4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+  #include "stm32l4xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32l4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+  #include "stm32l4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+  #include "stm32l4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+  #include "stm32l4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32l4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+  #include "stm32l4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+  #include "stm32l4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+  #include "stm32l4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+  #include "stm32l4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+  #include "stm32l4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+  #include "stm32l4xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+  #include "stm32l4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32l4xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+  #include "stm32l4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+  #include "stm32l4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+  #include "stm32l4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+  #include "stm32l4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+  #include "stm32l4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32l4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+  #include "stm32l4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(char *file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -65,26 +65,26 @@
   */
 typedef struct
 {
-  uint8_t                Enable;                /*!< Specifies the status of the region. 
+  uint8_t                Enable;                /*!< Specifies the status of the region.
                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+  uint8_t                Number;                /*!< Specifies the number of the region to protect.
                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
 }MPU_Region_InitTypeDef;
 /**
@@ -230,7 +230,7 @@ typedef struct
   * @}
   */
 
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
   * @{
   */
 #define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
@@ -277,7 +277,7 @@ typedef struct
   * @{
   */
 
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
   * @brief    Initialization and Configuration functions
   * @{
   */
@@ -298,15 +298,15 @@ __STATIC_INLINE void HAL_MPU_Disable(void)
 {
   /* Disable fault exceptions */
   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
+
   /* Disable the MPU */
   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
 }
 
 /**
   * @brief  Enable the MPU.
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged accessto the default memory 
+  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
+  *          NMI, FAULTMASK and privileged accessto the default memory
   *          This parameter can be one of the following values:
   *            @arg MPU_HFNMI_PRIVDEF_NONE
   *            @arg MPU_HARDFAULT_NMI
@@ -318,7 +318,7 @@ __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
 {
   /* Enable the MPU */
   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
+
   /* Enable fault exceptions */
   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 }
@@ -327,7 +327,7 @@ __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
   * @}
   */
 
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
   * @brief   Cortex control functions
   * @{
   */
@@ -353,7 +353,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/ 
+/* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h

@@ -0,0 +1,368 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_crc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CRC_H
+#define __STM32L4xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Types CRC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  CRC HAL State Structure definition
+  */
+typedef enum
+{
+  HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
+}HAL_CRC_StateTypeDef;
+
+
+
+/**
+  * @brief CRC Init Structure definition
+  */
+typedef struct
+{
+  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+                                            In that case, there is no need to set GeneratingPolynomial field.
+                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+
+  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.
+                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
+
+  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
+                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
+                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
+                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */
+
+  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+                                           Value can be either one of
+                                           @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
+
+  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+                                           is set to DEFAULT_INIT_VALUE_ENABLE.   */
+
+  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+                                           Can be either one of the following values
+                                           @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
+                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+
+  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+                                            Can be either
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
+}CRC_InitTypeDef;
+
+
+
+/**
+  * @brief  CRC Handle Structure definition
+  */
+typedef struct
+{
+  CRC_TypeDef                 *Instance;   /*!< Register base address        */
+
+  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
+
+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
+
+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
+
+  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+                                            Can be either
+                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)
+
+                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
+                                           must occur if InputBufferFormat is not one of the three values listed above  */
+}CRC_HandleTypeDef;
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
+  * @{
+  */
+#define DEFAULT_CRC32_POLY      0x04C11DB7  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define DEFAULT_CRC_INITVALUE   0xFFFFFFFF  /*!< Initial CRC default value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
+  * @{
+  */
+#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00)  /*!< Enable default generating polynomial 0x04C11DB7  */
+#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01)  /*!< Disable default generating polynomial 0x04C11DB7 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
+  * @{
+  */
+#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00) /*!< Enable initial CRC default value  */
+#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01) /*!< Disable initial CRC default value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
+  * @{
+  */
+#define CRC_POLYLENGTH_32B                  ((uint32_t)0x00000000)        /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial  */
+#define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)   /*!< Resort to a 7-bit long generating polynomial  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+  * @{
+  */
+#define HAL_CRC_LENGTH_32B     32          /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B     16          /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B       8          /*!< 8-bit long CRC  */
+#define HAL_CRC_LENGTH_7B       7          /*!< 7-bit long CRC  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+  * @{
+  */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED             ((uint32_t)0x00000000)  /*!< Undefined input data format    */
+#define CRC_INPUTDATA_FORMAT_BYTES                 ((uint32_t)0x00000001)  /*!< Input data in byte format      */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS             ((uint32_t)0x00000002)  /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS                 ((uint32_t)0x00000003)  /*!< Input data in word format      */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRC handle state.
+  * @param  __HANDLE__: CRC handle.
+  * @retval None
+  */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+  * @brief  Reset CRC Data Register.
+  * @param  __HANDLE__: CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+  * @brief  Set CRC INIT non-default value
+  * @param  __HANDLE__: CRC handle
+  * @param  __INIT__: 32-bit initial value
+  * @retval None
+  */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+/**
+  * @brief Store a 8-bit data in the Independent Data(ID) register.
+  * @param __HANDLE__: CRC handle
+  * @param __VALUE__: 8-bit value to be stored in the ID register
+  * @retval None
+  */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+  * @brief Return the 8-bit data stored in the Independent Data(ID) register.
+  * @param __HANDLE__: CRC handle
+  * @retval 8-bit value of the ID register
+  */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  CRC_Private_Macros   CRC Private Macros
+  * @{
+  */
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+
+#define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+#define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
+                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
+                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
+                                       ((LENGTH) == CRC_POLYLENGTH_7B))
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+  * @}
+  */
+
+/* Include CRC HAL Extended module */
+#include "stm32l4xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h

@@ -0,0 +1,173 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_crc_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CRC_EX_H
+#define __STM32L4xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+  * @{
+  */
+#define CRC_INPUTDATA_INVERSION_NONE              ((uint32_t)0x00000000)      /*!< No input data inversion            */
+#define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion     */
+#define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)   /*!< Word-wise input data inversion     */
+/**
+  * @}
+  */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+  * @{
+  */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE         ((uint32_t)0x00000000)     /*!< No output data inversion       */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Set CRC output reversal
+  * @param  __HANDLE__: CRC handle
+  * @retval None
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+  * @brief  Unset CRC output reversal
+  * @param  __HANDLE__: CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+/**
+  * @brief  Set CRC non-default polynomial
+  * @param  __HANDLE__: CRC handle
+  * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
+  * @retval None
+  */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  CRCEx_Private_Macros   CRCEx Private Macros
+  * @{
+  */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h

@@ -0,0 +1,698 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cryp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRYP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CRYP_H
+#define __STM32L4xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+  * @{
+  */
+
+/**
+  * @brief  CRYP Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t DataType;       /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                             This parameter can be a value of @ref CRYP_Data_Type */
+
+  uint32_t KeySize;        /*!< 128 or 256-bit key length.
+                             This parameter can be a value of @ref CRYP_Key_Size */
+
+  uint32_t OperatingMode;  /*!< AES operating mode.
+                             This parameter can be a value of @ref CRYP_AES_OperatingMode */
+
+  uint32_t ChainingMode;   /*!< AES chaining mode.
+                             This parameter can be a value of @ref CRYP_AES_ChainingMode */
+
+  uint32_t KeyWriteFlag;   /*!< Allows to bypass or not key write-up before decryption.
+                             This parameter can be a value of @ref CRYP_Key_Write */
+
+  uint32_t GCMCMACPhase;   /*!< Indicates the processing phase of the Galois Counter Mode (GCM),
+                             Galois Message Authentication Code (GMAC), Cipher Message
+                             Authentication Code (CMAC) (when applicable) or Counter with Cipher
+                             Mode (CCM) (when applicable).
+                             This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */
+
+  uint8_t* pKey;           /*!< Encryption/Decryption Key */
+
+  uint8_t* pInitVect;      /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC (when applicable)
+                                and CCM (when applicable) modes */
+
+  uint8_t* Header;         /*!< Header used in GCM/GMAC, CMAC (when applicable) and CCM (when applicable) modes */
+
+  uint64_t HeaderSize;     /*!< Header size in bytes */
+
+}CRYP_InitTypeDef;
+
+/**
+  * @brief HAL CRYP State structures definition
+  */
+typedef enum
+{
+  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
+  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
+  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
+  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
+  HAL_CRYP_STATE_ERROR             = 0x04,  /*!< CRYP error state                      */
+  HAL_CRYP_STATE_SUSPENDED         = 0x05   /*!< CRYP suspended                        */
+}HAL_CRYP_STATETypeDef;
+
+/**
+  * @brief HAL CRYP phase structures definition
+  */
+typedef enum
+{
+  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization.             */
+  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase                   */
+  HAL_CRYP_PHASE_START             = 0x03,    /*!< CRYP peripheral has been initialized but
+                                                 GCM/GMAC(/CMAC)(/CCM) initialization phase has not started */
+  HAL_CRYP_PHASE_INIT_OVER         = 0x04,    /*!< GCM/GMAC(/CMAC)(/CCM) init phase has been carried out    */
+  HAL_CRYP_PHASE_HEADER_OVER       = 0x05,    /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been carried out  */
+  HAL_CRYP_PHASE_PAYLOAD_OVER      = 0x06,    /*!< GCM(/CCM) payload phase has been carried out             */
+  HAL_CRYP_PHASE_FINAL_OVER        = 0x07,    /*!< GCM/GMAC(/CMAC)(/CCM) final phase has been carried out   */
+  HAL_CRYP_PHASE_HEADER_SUSPENDED  = 0x08,    /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been suspended    */
+  HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09,    /*!< GCM(/CCM) payload phase has been suspended               */
+  HAL_CRYP_PHASE_NOT_USED          = 0x0a     /*!< Phase is irrelevant to the current chaining mode         */
+}HAL_PhaseTypeDef;
+
+/**
+  * @brief HAL CRYP mode suspend definitions
+  */
+typedef enum
+{
+  HAL_CRYP_SUSPEND_NONE            = 0x00,    /*!< CRYP peripheral suspension not requested */
+  HAL_CRYP_SUSPEND                 = 0x01     /*!< CRYP peripheral suspension requested     */
+}HAL_SuspendTypeDef;
+
+
+/**
+  * @brief  HAL CRYP Error Codes definition
+  */
+#define HAL_CRYP_ERROR_NONE      ((uint32_t)0x00000000)  /*!< No error        */
+#define HAL_CRYP_WRITE_ERROR     ((uint32_t)0x00000001)  /*!< Write error     */
+#define HAL_CRYP_READ_ERROR      ((uint32_t)0x00000002)  /*!< Read error      */
+#define HAL_CRYP_DMA_ERROR       ((uint32_t)0x00000004)  /*!< DMA error       */
+#define HAL_CRYP_BUSY_ERROR      ((uint32_t)0x00000008)  /*!< Busy flag error */
+
+/**
+  * @brief  CRYP handle Structure definition
+  */
+typedef struct
+{
+      AES_TypeDef              *Instance;        /*!< Register base address        */
+
+      CRYP_InitTypeDef         Init;             /*!< CRYP initialization parameters */
+
+      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
+
+      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
+
+      uint32_t                 CrypInCount;      /*!< Input data size in bytes or, after suspension, the remaining
+                                                       number of bytes to process */
+
+      uint32_t                 CrypOutCount;     /*!< Output data size in bytes */
+
+      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC (when applicable)
+                                                      or CCM (when applicable) modes.
+                                                      Indicates the last phase carried out to ease
+                                                      phase transitions  */
+
+      DMA_HandleTypeDef        *hdmain;          /*!< CRYP peripheral Input DMA handle parameters */
+
+      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP peripheral Output DMA handle parameters */
+
+      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
+
+   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
+
+    __IO uint32_t              ErrorCode;        /*!< CRYP peripheral error code */
+
+     HAL_SuspendTypeDef        SuspendRequest;   /*!< CRYP peripheral suspension request flag */
+}CRYP_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Key_Size  Key size selection
+  * @{
+  */
+#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)  /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE          /*!< 256-bit long key */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Data_Type  AES Data Type selection
+  * @{
+  */
+#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)  /*!< 32-bit data type (no swapping)        */
+#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
+#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
+#define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
+/**
+  * @}
+  */
+
+ /** @defgroup CRYP_AES_State  AES Enable state
+  * @{
+  */
+#define CRYP_AES_DISABLE                 ((uint32_t)0x00000000)   /*!< Disable AES */
+#define CRYP_AES_ENABLE                   AES_CR_EN               /*!< Enable AES  */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_AES_OperatingMode AES operating mode
+  * @{
+  */
+#define CRYP_ALGOMODE_ENCRYPT                   ((uint32_t)0x00000000)  /*!< Encryption mode                                              */
+#define CRYP_ALGOMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode                                          */
+#define CRYP_ALGOMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption                                                   */
+#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption                                */
+#define CRYP_ALGOMODE_TAG_GENERATION            ((uint32_t)0x00000000)  /*!< GMAC or CMAC (when applicable) authentication tag generation */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_AES_ChainingMode AES chaining mode
+  * @{
+  */
+#define CRYP_CHAINMODE_AES_ECB            ((uint32_t)0x00000000)            /*!< Electronic codebook chaining algorithm                   */
+#define CRYP_CHAINMODE_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
+#define CRYP_CHAINMODE_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
+#define CRYP_CHAINMODE_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
+#if defined(AES_CR_NPBLB)
+#define CRYP_CHAINMODE_AES_CCM            AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode                                 */
+#else
+#define CRYP_CHAINMODE_AES_CMAC           AES_CR_CHMOD_2                    /*!< Cipher message authentication code                       */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Key_Write AES decryption key write-up flag
+  * @{
+  */
+#define CRYP_KEY_WRITE_ENABLE            ((uint32_t)0x00000000)  /*!< Enable decryption key writing  */
+#define CRYP_KEY_WRITE_DISABLE           ((uint32_t)0x00000001)  /*!< Disable decryption key writing */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_DMAIN DMA Input phase management enable state
+  * @{
+  */
+#define CRYP_DMAIN_DISABLE             ((uint32_t)0x00000000)    /*!< Disable DMA Input phase management */
+#define CRYP_DMAIN_ENABLE              AES_CR_DMAINEN            /*!< Enable DMA Input phase management  */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_DMAOUT DMA Output phase management enable state
+  * @{
+  */
+#define CRYP_DMAOUT_DISABLE             ((uint32_t)0x00000000)   /*!< Disable DMA Output phase management */
+#define CRYP_DMAOUT_ENABLE              AES_CR_DMAOUTEN          /*!< Enable DMA Output phase management  */
+/**
+  * @}
+  */
+
+
+/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CCM/CMAC (when applicable) processing phase selection
+  * @{
+  */
+#define CRYP_GCM_INIT_PHASE             ((uint32_t)0x00000000)  /*!< GCM/GMAC (or CCM) init phase   */
+#define CRYP_GCMCMAC_HEADER_PHASE       AES_CR_GCMPH_0          /*!< GCM/GMAC/CCM/CMAC header phase */
+#define CRYP_GCM_PAYLOAD_PHASE          AES_CR_GCMPH_1          /*!< GCM/CCM payload phase          */
+#define CRYP_GCMCMAC_FINAL_PHASE        AES_CR_GCMPH            /*!< GCM/GMAC/CCM/CMAC final phase  */
+/* Definitions duplication for code readibility's sake:
+   supported or not supported chain modes are not specified for each phase */
+#define CRYP_INIT_PHASE                 ((uint32_t)0x00000000)  /*!< Init phase    */
+#define CRYP_HEADER_PHASE               AES_CR_GCMPH_0          /*!< Header phase  */
+#define CRYP_PAYLOAD_PHASE              AES_CR_GCMPH_1          /*!< Payload phase */
+#define CRYP_FINAL_PHASE                AES_CR_GCMPH            /*!< Final phase   */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Flags   AES status flags
+  * @{
+  */
+
+#define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
+#define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
+#define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
+#define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Clear_Flags   AES clearing flags
+  * @{
+  */
+
+#define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
+#define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear                */
+/**
+  * @}
+  */
+
+/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
+  * @{
+  */
+#define CRYP_IT_CCFIE                         AES_CR_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_ERRIE                         AES_CR_ERRIE /*!< Error interrupt enable                */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Interrupts_Flags   AES Interrupts flags
+  * @{
+  */
+#define CRYP_IT_WRERR   AES_SR_WRERR  /*!< Write Error           */
+#define CRYP_IT_RDERR   AES_SR_RDERR  /*!< Read Error            */
+#define CRYP_IT_CCF     AES_SR_CCF    /*!< Computation completed */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRYP handle state.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+  * @brief  Enable the CRYP AES peripheral.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  AES_CR_EN)
+
+/**
+  * @brief  Disable the CRYP AES peripheral.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~AES_CR_EN)
+
+/**
+  * @brief  Set the algorithm operating mode.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __OPERATING_MODE__: specifies the operating mode
+  *          This parameter can be one of the following values:
+  *            @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
+  *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
+  *            @arg @ref CRYP_ALGOMODE_DECRYPT decryption
+  *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
+  * @retval None
+  */
+#define __HAL_CRYP_SET_OPERATINGMODE(__HANDLE__, __OPERATING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_MODE, (__OPERATING_MODE__))
+
+
+/**
+  * @brief  Set the algorithm chaining mode.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __CHAINING_MODE__: specifies the chaining mode
+  *          This parameter can be one of the following values:
+  *            @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
+  *            @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
+  *            @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
+  *            @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
+  *            @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
+  * @retval None
+  */
+#define __HAL_CRYP_SET_CHAININGMODE(__HANDLE__, __CHAINING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
+
+
+
+/** @brief  Check whether the specified CRYP status flag is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
+  *            @arg @ref CRYP_IT_WRERR Write Error
+  *            @arg @ref CRYP_IT_RDERR Read Error
+  *            @arg @ref CRYP_IT_CCF Computation Complete
+  * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Clear the CRYP pending status flag.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
+
+
+
+/** @brief  Check whether the specified CRYP interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param __INTERRUPT__: CRYP interrupt source to check
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+  * @retval State of interruption (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+
+/** @brief  Check whether the specified CRYP interrupt is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: specifies the interrupt to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_IT_WRERR Write Error
+  *            @arg @ref CRYP_IT_RDERR Read Error
+  *            @arg @ref CRYP_IT_CCF  Computation Complete
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+
+
+/** @brief  Clear the CRYP pending interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: specifies the IT to clear.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/**
+  * @brief  Enable the CRYP interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+
+/**
+  * @brief  Disable the CRYP interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+  * @retval None
+  */
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  CRYP_Private_Macros   CRYP Private Macros
+  * @{
+  */
+
+/**
+  * @brief Verify the key size length.
+  * @param __KEYSIZE__: Ciphering/deciphering algorithm key size.
+  * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
+  */
+#define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
+                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
+
+/**
+  * @brief Verify the input data type.
+  * @param __DATATYPE__: Ciphering/deciphering algorithm input data type.
+  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+  */
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+/**
+  * @brief Verify the CRYP AES IP running mode.
+  * @param __MODE__: CRYP AES IP running mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
+                               ((__MODE__) == CRYP_AES_ENABLE))
+
+/**
+  * @brief Verify the selected CRYP algorithm.
+  * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
+  * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
+  */
+#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT)        || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION)  || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT)        || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
+                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))
+
+/**
+  * @brief Verify the selected CRYP chaining algorithm.
+  * @param __CHAINMODE__: Selected CRYP chaining algorithm.
+  * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
+  */
+#if defined(AES_CR_NPBLB)
+#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM))
+#else
+#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
+                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
+#endif
+
+/**
+  * @brief Verify the deciphering key write option.
+  * @param __WRITE__: deciphering key write option.
+  * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
+  */
+#define IS_CRYP_WRITE(__WRITE__)   (((__WRITE__) == CRYP_KEY_WRITE_ENABLE)      || \
+                                    ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
+
+/**
+  * @brief Verify the CRYP input data DMA mode.
+  * @param __MODE__: CRYP input data DMA mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
+                                 ((__MODE__) == CRYP_DMAIN_ENABLE))
+
+/**
+  * @brief Verify the CRYP output data DMA mode.
+  * @param __MODE__: CRYP output data DMA mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
+                                  ((__MODE__) == CRYP_DMAOUT_ENABLE))
+
+/**
+  * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
+  * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
+  * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
+  */
+#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_INIT_PHASE)    || \
+                                          ((__PHASE__) == CRYP_HEADER_PHASE)  || \
+                                          ((__PHASE__) == CRYP_PAYLOAD_PHASE) || \
+                                          ((__PHASE__) == CRYP_FINAL_PHASE))
+
+/**
+  * @}
+  */
+
+/* Include CRYP HAL Extended module */
+#include "stm32l4xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
+  * @{
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* MSP initialization/de-initialization functions  ****************************/
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions
+  * @{
+  */
+
+/* AES encryption/decryption processing functions  ****************************/
+
+/* AES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
+  * @{
+  */
+/* CallBack functions  ********************************************************/
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
+  * @{
+  */
+
+/* AES interrupt handling function  *******************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions
+  * @{
+  */
+
+/* Peripheral State functions  ************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+uint32_t              HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h

@@ -0,0 +1,148 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cryp_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRYPEx HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CRYP_EX_H
+#define __STM32L4xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYPEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRYPEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* CallBack functions  ********************************************************/
+void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2
+  * @{
+  */
+
+/* AES encryption/decryption processing functions  ****************************/
+HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
+HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
+
+/* AES encryption/decryption/authentication processing functions  *************/
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* AES suspension/resumption functions  ***************************************/
+void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
+void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
+void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
+  * @{
+  */
+HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -46,7 +46,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l4xx_hal_def.h"
-   
+
 /** @addtogroup STM32L4xx_HAL_Driver
   * @{
   */
@@ -61,9 +61,9 @@
   * @{
   */
 
-/** 
-  * @brief  HAL State structures definition  
-  */ 
+/**
+  * @brief  HAL State structures definition
+  */
 typedef enum
 {
   HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
@@ -71,74 +71,74 @@ typedef enum
   HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
   HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
   HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
- 
+
 }HAL_DAC_StateTypeDef;
- 
-/** 
-  * @brief  DAC handle Structure definition  
-  */ 
+
+/**
+  * @brief  DAC handle Structure definition
+  */
 typedef struct
 {
   DAC_TypeDef                 *Instance;     /*!< Register base address             */
-  
+
   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
 
   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-  
+
   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-  
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */ 
-  
+
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
+
   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
-  
+
 }DAC_HandleTypeDef;
 
-/** 
-  * @brief   DAC Configuration sample and hold Channel structure definition  
-  */ 
+/**
+  * @brief   DAC Configuration sample and hold Channel structure definition
+  */
 typedef struct
 {
   uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */  
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
 
   uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */    
-  
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
   uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */  
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
 }
 DAC_SampleAndHoldConfTypeDef;
 
-/** 
-  * @brief   DAC Configuration regular Channel structure definition  
-  */ 
+/**
+  * @brief   DAC Configuration regular Channel structure definition
+  */
 typedef struct
 {
   uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
                                               This parameter can be a value of @ref DAC_SampleAndHold */
-  
+
   uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
                                               This parameter can be a value of @ref DAC_trigger_selection */
-  
+
   uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
                                                This parameter can be a value of @ref DAC_output_buffer */
 
   uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
                                               This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
-  
-  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode 
-                                              This parameter must be a value of @ref DAC_UserTrimming 
+
+  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
+                                              This parameter must be a value of @ref DAC_UserTrimming
                                               DAC_UserTrimming is either factory or user trimming */
-                                        
-  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value 
-                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 
+
+  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
+                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
                                                This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
 
-  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */ 
-      
+  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
+
 }DAC_ChannelConfTypeDef;
 
 /**
@@ -167,7 +167,27 @@ typedef struct
   * @{
   */
 
-#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register 
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register
+                                                                       has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+#endif     /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register
+                                                                       has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+#endif     /* STM32L451xx STM32L452xx STM32L462xx                         */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register
                                                                        has been loaded, and not by external trigger */
 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
@@ -177,10 +197,13 @@ typedef struct
 #define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+#endif     /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/
+
+
 
 /**
   * @}
-  */   
+  */
 
 /** @defgroup DAC_output_buffer DAC output buffer
   * @{
@@ -191,12 +214,16 @@ typedef struct
 /**
   * @}
   */
-    
+
 /** @defgroup DAC_Channel_selection DAC Channel selection
   * @{
   */
 #define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
 #define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
 
 /**
   * @}
@@ -215,9 +242,9 @@ typedef struct
 
 /** @defgroup DAC_flags_definition DAC flags definition
   * @{
-  */ 
+  */
 #define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
 
 /**
   * @}
@@ -225,14 +252,14 @@ typedef struct
 
 /** @defgroup DAC_IT_definition  DAC IT definition
   * @{
-  */ 
+  */
 #define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
 
 /**
   * @}
   */
-  
+
 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
   * @{
   */
@@ -249,10 +276,10 @@ typedef struct
 
 #define DAC_TRIMMING_FACTORY        ((uint32_t)0x00000000)           /*!< Factory trimming */
 #define DAC_TRIMMING_USER           ((uint32_t)0x00000001)           /*!< User trimming */
-   
+
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup DAC_SampleAndHold DAC power mode
   * @{
@@ -295,7 +322,7 @@ typedef struct
   */
 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
- 
+
 /** @brief Set DHR12R1 alignment.
   * @param  __ALIGNMENT__: specifies the DAC alignment
   * @retval None
@@ -366,7 +393,7 @@ typedef struct
 
 /**
   * @}
-  */ 
+  */
 
 /* Private macro -------------------------------------------------------------*/
 
@@ -376,8 +403,16 @@ typedef struct
 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
 
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
                                 ((CHANNEL) == DAC_CHANNEL_2))
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#if defined (STM32L451xx)  || defined (STM32L452xx)  || defined (STM32L462xx)
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
+#endif /* STM32L451xx STM32L452xx STM32L462xx */
 
 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
                              ((ALIGN) == DAC_ALIGN_12B_L) || \
@@ -390,11 +425,11 @@ typedef struct
 /**
   * @}
   */
-  
+
 /* Include DAC HAL Extended module */
-#include "stm32l4xx_hal_dac_ex.h"   
+#include "stm32l4xx_hal_dac_ex.h"
 
-/* Exported functions --------------------------------------------------------*/  
+/* Exported functions --------------------------------------------------------*/
 
 /** @addtogroup DAC_Exported_Functions
   * @{
@@ -402,8 +437,8 @@ typedef struct
 
 /** @addtogroup DAC_Exported_Functions_Group1
   * @{
-  */  
-/* Initialization and de-initialization functions *****************************/ 
+  */
+/* Initialization and de-initialization functions *****************************/
 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
@@ -415,7 +450,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
 
 /** @addtogroup DAC_Exported_Functions_Group2
  * @{
- */    
+ */
 /* IO operation functions *****************************************************/
 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
@@ -436,7 +471,7 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
 
 /** @addtogroup DAC_Exported_Functions_Group3
   * @{
-  */ 
+  */
 /* Peripheral Control functions ***********************************************/
 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
 
@@ -447,7 +482,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
 
 /** @addtogroup DAC_Exported_Functions_Group4
   * @{
-  */     
+  */
 /* Peripheral State and Error functions ***************************************/
 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
@@ -463,15 +498,15 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
 /**
   * @}
   */
-  
+
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
-#endif 
-  
+#endif
+
 
 #endif /*__STM32L4xx_HAL_DAC_H */
 

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_dac_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of DAC HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -45,7 +45,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l4xx_hal_def.h"
-           
+
 /** @addtogroup STM32L4xx_HAL_Driver
   * @{
   */
@@ -55,18 +55,18 @@
   */
 
 /* Exported types ------------------------------------------------------------*/
-   
-/** 
-  * @brief  HAL State structures definition  
-  */ 
+
+/**
+  * @brief  HAL State structures definition
+  */
 
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
   * @{
-  */ 
-    
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
+  */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
   * @{
   */
 #define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
@@ -96,7 +96,7 @@
 
 /**
   * @}
-  */       
+  */
 
 /**
   * @}
@@ -110,7 +110,24 @@
 /** @defgroup DACEx_Private_Macros DACEx Private Macros
   * @{
   */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif     /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
 
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif     /* STM32L451xx STM32L452xx STM32L462xx                         */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
@@ -119,7 +136,8 @@
                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))      
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif     /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
 
 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
 
@@ -170,7 +188,7 @@
   * @}
   */
 
-/* Exported functions --------------------------------------------------------*/  
+/* Exported functions --------------------------------------------------------*/
 /* Extended features functions ***********************************************/
 
 /** @addtogroup DACEx_Exported_Functions
@@ -179,17 +197,25 @@
 
 /** @addtogroup DACEx_Exported_Functions_Group2
  * @{
- */    
+ */
 /* IO operation functions *****************************************************/
-  
+
 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
 
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
 
 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
@@ -200,12 +226,17 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe
 
 /** @addtogroup DACEx_Exported_Functions_Group3
   * @{
-  */ 
+  */
 /* Peripheral Control functions ***********************************************/
 
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
 uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
-   
+
 /**
   * @}
   */
@@ -214,6 +245,9 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
   * @}
   */
 
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+
 /** @addtogroup DACEx_Private_Functions
   * @{
   */
@@ -227,7 +261,8 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
 /**
  * @}
  */
-
+#endif  /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx                         */
+        /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
 /**
   * @}
   */
@@ -238,7 +273,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
 
 #ifdef __cplusplus
 }
-#endif   
+#endif
 
 #endif /*__STM32L4xx_HAL_DAC_EX_H */
 

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h

@@ -0,0 +1,656 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dcmi.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DCMI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DCMI_H
+#define __STM32L4xx_HAL_DCMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DCMI DCMI
+  * @brief DCMI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Types DCMI Exported Types
+  * @{
+  */
+/**
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
+  */
+typedef struct
+{
+  uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+  uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
+  uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
+  uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
+}DCMI_CodesInitTypeDef;
+
+
+/**
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
+  */
+typedef struct
+{
+  uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+  uint8_t LineStartUnmask;  /*!< Specifies the line start delimiter unmask.  */
+  uint8_t LineEndUnmask;    /*!< Specifies the line end delimiter unmask.    */
+  uint8_t FrameEndUnmask;   /*!< Specifies the frame end delimiter unmask.   */
+}DCMI_SyncUnmaskTypeDef;
+
+
+/**
+  * @brief   DCMI Init structure definition
+  */
+typedef struct
+{
+  uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+                                             This parameter can be a value of @ref DCMI_Synchronization_Mode. */
+
+  uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
+                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity.       */
+
+  uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
+                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity.       */
+
+  uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
+                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity.       */
+
+  uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+                                             This parameter can be a value of @ref DCMI_Capture_Rate.         */
+
+  uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode.   */
+
+  DCMI_CodesInitTypeDef SynchroCode;    /*!< Specifies the frame start delimiter codes.                       */
+
+  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.
+                                             This parameter can be a value of @ref DCMI_JPEG_Mode.            */
+
+  uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface.
+                                            This parameter can be a value of @ref DCMI_Byte_Select_Mode.      */
+
+  uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd.
+                                            This parameter can be a value of @ref DCMI_Byte_Select_Start.     */
+
+  uint32_t LineSelectMode;              /*!< Specifies the data line to be captured by the interface.
+                                            This parameter can be a value of @ref DCMI_Line_Select_Mode.      */
+
+  uint32_t LineSelectStart;             /*!< Specifies if the data line to be captured by the interface is even or odd.
+                                            This parameter can be a value of @ref DCMI_Line_Select_Start.     */
+
+}DCMI_InitTypeDef;
+
+
+/**
+  * @brief  HAL DCMI State structures definition
+  */
+typedef enum
+{
+  HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */
+  HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
+  HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
+  HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
+  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
+  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */
+}HAL_DCMI_StateTypeDef;
+
+
+/**
+  * @brief  DCMI handle Structure definition
+  */
+typedef struct
+{
+  DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
+
+  DCMI_InitTypeDef              Init;                /*!< DCMI init parameters         */
+
+  HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */
+
+  __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */
+
+  __IO uint32_t                 XferCount;           /*!< DMA transfers counter        */
+
+  __IO uint32_t                 XferSize;            /*!< DMA transfer size            */
+
+  uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */
+
+  DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to DMA handler       */
+
+  DMA_HandleTypeDef             *DMAM2M_Handle;      /*!< Pointer to DMA handler for memory to memory copy
+                                                        (case picture size >  maximum DMA transfer length) */
+
+  __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
+
+  uint32_t                      pCircularBuffer;     /*!< Pointer to intermediate copy buffer
+                                                        (case picture size >  maximum DMA transfer length) */
+
+  uint32_t                      HalfCopyLength;      /*!< Intermediate copies length
+                                                        (case picture size >  maximum DMA transfer length) */
+
+}DCMI_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Error_Code DCMI Error Code
+  * @{
+  */
+#define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
+#define HAL_DCMI_ERROR_OVR       ((uint32_t)0x00000001)    /*!< Overrun error         */
+#define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002)    /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
+#define HAL_DCMI_ERROR_DMA       ((uint32_t)0x00000040)    /*!< DMA error             */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
+  * @{
+  */
+#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000)  /*!< The received data are transferred continuously
+                                                                    into the destination memory through the DMA             */
+#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of
+                                                                    frame and then transfers a single frame through the DMA */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
+  * @{
+  */
+#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000)   /*!< Hardware synchronization data capture (frame/line start/stop)
+                                                                   is synchronized with the HSYNC/VSYNC signals                  */
+#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with
+                                                                   synchronization codes embedded in the data flow               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_PIXCK_Polarity DCMI Pixel Clock Polarity
+  * @{
+  */
+#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000)      /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
+  * @{
+  */
+#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Vertical synchronization active Low  */
+#define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
+  * @{
+  */
+#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Horizontal synchronization active Low  */
+#define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_JPEG_Mode DCMI JPEG Mode
+  * @{
+  */
+#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000)    /*!< JPEG mode disabled  */
+#define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< JPEG mode enabled   */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
+  * @{
+  */
+#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000)      /*!< All frames are captured        */
+#define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
+#define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
+  * @{
+  */
+#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000)                       /*!< Interface captures 8-bit data on every pixel clock  */
+#define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
+  * @{
+  */
+#define DCMI_BSM_ALL                 ((uint32_t)0x00000000) /*!< Interface captures all received data */
+#define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
+#define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
+#define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
+  * @{
+  */
+#define DCMI_OEBS_ODD               ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */
+#define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
+  * @{
+  */
+#define DCMI_LSM_ALL                 ((uint32_t)0x00000000) /*!< Interface captures all received lines */
+#define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
+  * @{
+  */
+#define DCMI_OELS_ODD               ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */
+#define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DCMI_interrupt_sources  DCMI Interrupt Sources
+  * @{
+  */
+#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */
+#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */
+#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */
+#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */
+#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Flags DCMI Flags
+  * @{
+  */
+
+/**
+  * @brief   DCMI SR register
+  */
+#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */
+#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
+#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */
+/**
+  * @brief   DCMI RIS register
+  */
+#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Capture complete interrupt flag      */
+#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag               */
+#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag */
+#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                 */
+#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                  */
+/**
+  * @brief   DCMI MIS register
+  */
+#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Capture complete masked interrupt status      */
+#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status               */
+#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status */
+#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                 */
+#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
+  * @{
+  */
+
+/** @brief Reset DCMI handle state
+  * @param  __HANDLE__: specifies the DCMI handle.
+  * @retval None
+  */
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+
+/**
+  * @brief  Enable the DCMI.
+  * @param  __HANDLE__: DCMI handle
+  * @retval None
+  */
+#define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
+
+/**
+  * @brief  Disable the DCMI.
+  * @param  __HANDLE__: DCMI handle
+  * @retval None
+  */
+#define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DCMI pending flag.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __FLAG__: Get the specified flag.
+  *         This parameter can be one of the following values (no combination allowed)
+  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
+  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
+  *            @arg DCMI_FLAG_FNE: FIFO empty flag
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
+  *            @arg DCMI_FLAG_OVRRI: Overrun flag
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag
+  *            @arg DCMI_FLAG_LINERI: Line flag
+  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
+  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
+  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
+  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
+  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
+  * @retval The state of FLAG.
+  */
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
+((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
+ (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DCMI pending flag.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
+  *            @arg DCMI_FLAG_OVRRI: Overrun flag
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag
+  *            @arg DCMI_FLAG_LINERI: Line flag
+  * @retval None
+  */
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DCMI interrupts.
+  * @param  __HANDLE__:    DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt
+  *            @arg DCMI_IT_OVR: Overrun interrupt
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt
+  *            @arg DCMI_IT_LINE: Line interrupt
+  * @retval None
+  */
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DCMI interrupts.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt
+  *            @arg DCMI_IT_OVR: Overrun interrupt
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt
+  *            @arg DCMI_IT_LINE: Line interrupt
+  * @retval None
+  */
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether or not the specified DCMI interrupt has occurred and that the interruption is enabled at the same time.
+  * @note   A bit in MIS register is set if the corresponding enable bit in
+  *         DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt flag and source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVR: Overrun interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval The state of INTERRUPT.
+  */
+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MIS & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DCMI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
+void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+/**
+  * @}
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
+void              HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+/**
+  * @}
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
+/**
+  * @}
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
+uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DCMI_Private_Constants DCMI Private Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Registers_Indices DCMI Registers Indices
+  * @{
+  */
+#define DCMI_MIS_INDEX        ((uint32_t)0x1000)         /*!< DCMI MIS register index */
+#define DCMI_SR_INDEX         ((uint32_t)0x2000)         /*!< DCMI SR register index */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
+  * @{
+  */
+#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFF)  /*!< Window coordinate */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Window_Height DCMI Window Height
+  * @{
+  */
+#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFF)  /*!< Window Height */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Macros DCMI Private Macros
+  * @{
+  */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+                                   ((MODE) == DCMI_MODE_SNAPSHOT))
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
+                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
+                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \
+                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \
+                                    ((DATA) == DCMI_EXTEND_DATA_14B))
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+
+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
+                                       ((MODE) == DCMI_BSM_OTHER) || \
+                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \
+                                       ((MODE) == DCMI_BSM_ALTERNATE_2))
+
+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
+                                            ((POLARITY) == DCMI_OEBS_EVEN))
+
+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
+                                       ((MODE) == DCMI_LSM_ALTERNATE_2))
+
+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
+                                            ((POLARITY) == DCMI_OELS_EVEN))
+
+#define IS_DCMI_INTERRUPTS(INTERRUPTS) ((INTERRUPTS) <= DCMI_IER_INT_IE)
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h

@@ -2,14 +2,14 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_def.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   This file contains HAL common defines, enumeration, macros and
   *          structures definitions.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -73,7 +73,7 @@ typedef enum
 
 /* Exported macros -----------------------------------------------------------*/
 
-#define HAL_MAX_DELAY      0xFFFFFFFF
+#define HAL_MAX_DELAY      0xFFFFFFFFU
 
 #define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
 #define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
@@ -85,14 +85,14 @@ typedef enum
                         } while(0)
 
 #define UNUSED(x) ((void)(x))
-                         
+
 /** @brief Reset the Handle's State field.
   * @param __HANDLE__: specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose: 
+  * @note  This macro can be used for the following purpose:
   *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
   *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            Otherwise, "State" field may have any random value and the first time the function
   *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
   *            (i.e. HAL_PPP_MspInit() will not be executed).
   *          - When there is a need to reconfigure the low level hardware: instead of calling
@@ -188,14 +188,14 @@ typedef enum
 
 #endif
 
-/** 
+/**
   * @brief  __NOINLINE definition
-  */ 
+  */
 #if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
-/* ARM & GNUCompiler 
-   ---------------- 
+/* ARM & GNUCompiler
+   ----------------
 */
-#define __NOINLINE __attribute__ ( (noinline) )  
+#define __NOINLINE __attribute__ ( (noinline) )
 
 #elif defined ( __ICCARM__ )
 /* ICCARM Compiler

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h

@@ -0,0 +1,755 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dfsdm.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DFSDM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DFSDM_H
+#define __STM32L4xx_HAL_DFSDM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DFSDM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL DFSDM Channel states definition
+  */
+typedef enum
+{
+  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
+  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
+  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */
+}HAL_DFSDM_Channel_StateTypeDef;
+
+/**
+  * @brief  DFSDM channel output clock structure definition
+  */
+typedef struct
+{
+  FunctionalState Activation; /*!< Output clock enable/disable */
+  uint32_t        Selection;  /*!< Output clock is system clock or audio clock.
+                                   This parameter can be a value of @ref DFSDM_Channel_OuputClock */
+  uint32_t        Divider;    /*!< Output clock divider.
+                                   This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
+}DFSDM_Channel_OutputClockTypeDef;
+
+/**
+  * @brief  DFSDM channel input structure definition
+  */
+typedef struct
+{
+  uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
+                             ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,
+                             STM32L496xx, STM32L4A6xx products.
+                             This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
+  uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
+                             This parameter can be a value of @ref DFSDM_Channel_DataPacking */
+  uint32_t Pins;        /*!< Input pins are taken from same or following channel.
+                             This parameter can be a value of @ref DFSDM_Channel_InputPins */
+}DFSDM_Channel_InputTypeDef;
+
+/**
+  * @brief  DFSDM channel serial interface structure definition
+  */
+typedef struct
+{
+  uint32_t Type;     /*!< SPI or Manchester modes.
+                          This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
+  uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
+                          This parameter can be a value of @ref DFSDM_Channel_SpiClock */
+}DFSDM_Channel_SerialInterfaceTypeDef;
+
+/**
+  * @brief  DFSDM channel analog watchdog structure definition
+  */
+typedef struct
+{
+  uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.
+                              This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
+  uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
+                              This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+}DFSDM_Channel_AwdTypeDef;
+
+/**
+  * @brief  DFSDM channel init structure definition
+  */
+typedef struct
+{
+  DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */
+  DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */
+  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
+  DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */
+  int32_t                              Offset;          /*!< DFSDM channel offset.
+                                                             This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
+                                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+}DFSDM_Channel_InitTypeDef;
+
+/**
+  * @brief  DFSDM channel handle structure definition
+  */
+typedef struct
+{
+  DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
+  DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
+  HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
+}DFSDM_Channel_HandleTypeDef;
+
+/**
+  * @brief  HAL DFSDM Filter states definition
+  */
+typedef enum
+{
+  HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */
+  HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */
+  HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */
+  HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */
+  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
+  HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */
+}HAL_DFSDM_Filter_StateTypeDef;
+
+/**
+  * @brief  DFSDM filter regular conversion parameters structure definition
+  */
+typedef struct
+{
+  uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.
+                                 This parameter can be a value of @ref DFSDM_Filter_Trigger */
+  FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
+  FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
+}DFSDM_Filter_RegularParamTypeDef;
+
+/**
+  * @brief  DFSDM filter injected conversion parameters structure definition
+  */
+typedef struct
+{
+  uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.
+                                       This parameter can be a value of @ref DFSDM_Filter_Trigger */
+  FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */
+  FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */
+  uint32_t        ExtTrigger;     /*!< External trigger.
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
+  uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
+}DFSDM_Filter_InjectedParamTypeDef;
+
+/**
+  * @brief  DFSDM filter parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SincOrder;       /*!< Sinc filter order.
+                                 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
+  uint32_t Oversampling;    /*!< Filter oversampling ratio.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+  uint32_t IntOversampling; /*!< Integrator oversampling ratio.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
+}DFSDM_Filter_FilterParamTypeDef;
+
+/**
+  * @brief  DFSDM filter init structure definition
+  */
+typedef struct
+{
+  DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
+  DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
+  DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
+}DFSDM_Filter_InitTypeDef;
+
+/**
+  * @brief  DFSDM filter handle structure definition
+  */
+typedef struct
+{
+  DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
+  DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
+  DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */
+  DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */
+  uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */
+  uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */
+  uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */
+  uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
+  FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */
+  uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */
+  uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
+  HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
+  uint32_t                      ErrorCode;           /*!< DFSDM filter error code */
+}DFSDM_Filter_HandleTypeDef;
+
+/**
+  * @brief  DFSDM filter analog watchdog parameters structure definition
+  */
+typedef struct
+{
+  uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.
+                                 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
+  uint32_t Channel;         /*!< Analog watchdog channel selection.
+                                 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
+  int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */
+  uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */
+}DFSDM_Filter_AwdParamTypeDef;
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
+  * @{
+  */
+
+/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
+  * @{
+  */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
+  * @{
+  */
+#define DFSDM_CHANNEL_EXTERNAL_INPUTS    ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+#define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
+  * @{
+  */
+#define DFSDM_CHANNEL_STANDARD_MODE         ((uint32_t)0x00000000U) /*!< Standard data packing mode */
+#define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
+#define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
+  * @{
+  */
+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS      ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
+  * @{
+  */
+#define DFSDM_CHANNEL_SPI_RISING         ((uint32_t)0x00000000U) /*!< SPI with rising edge */
+#define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */
+#define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */
+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
+  * @{
+  */
+#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              ((uint32_t)0x00000000U)  /*!< External SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
+  * @{
+  */
+#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
+#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
+#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
+#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
+  * @{
+  */
+#define DFSDM_FILTER_SW_TRIGGER   ((uint32_t)0x00000000U) /*!< Software trigger */
+#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
+#define DFSDM_FILTER_EXT_TRIGGER  ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
+  * @{
+  */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  ((uint32_t)0x00000000U)                           /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */
+#else
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  ((uint32_t)0x00000000U)                           /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 0, 1 and 2 */
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
+  * @{
+  */
+#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
+#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
+#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
+  * @{
+  */
+#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)               /*!< FastSinc filter type */
+#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */
+#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */
+#define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
+#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */
+#define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
+  * @{
+  */
+#define DFSDM_FILTER_AWD_FILTER_DATA  ((uint32_t)0x00000000U) /*!< From digital filter */
+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
+  * @{
+  */
+#define DFSDM_FILTER_ERROR_NONE             ((uint32_t)0x00000000U) /*!< No error */
+#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
+#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
+#define DFSDM_FILTER_ERROR_DMA              ((uint32_t)0x00000003U) /*!< DMA error occurs */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_BreakSignals DFSDM break signals
+  * @{
+  */
+#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
+#define DFSDM_BREAK_SIGNAL_0  ((uint32_t)0x00000001U) /*!< Break signal 0 */
+#define DFSDM_BREAK_SIGNAL_1  ((uint32_t)0x00000002U) /*!< Break signal 1 */
+#define DFSDM_BREAK_SIGNAL_2  ((uint32_t)0x00000004U) /*!< Break signal 2 */
+#define DFSDM_BREAK_SIGNAL_3  ((uint32_t)0x00000008U) /*!< Break signal 3 */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
+  * @{
+  */
+/* DFSDM Channels ------------------------------------------------------------*/
+/* The DFSDM channels are defined as follows:
+   - in 16-bit LSB the channel mask is set
+   - in 16-bit MSB the channel number is set
+   e.g. for channel 5 definition:
+        - the channel mask is 0x00000020 (bit 5 is set)
+        - the channel number 5 is 0x00050000
+        --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define DFSDM_CHANNEL_0                              ((uint32_t)0x00000001U)
+#define DFSDM_CHANNEL_1                              ((uint32_t)0x00010002U)
+#define DFSDM_CHANNEL_2                              ((uint32_t)0x00020004U)
+#define DFSDM_CHANNEL_3                              ((uint32_t)0x00030008U)
+#else /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define DFSDM_CHANNEL_0                              ((uint32_t)0x00000001U)
+#define DFSDM_CHANNEL_1                              ((uint32_t)0x00010002U)
+#define DFSDM_CHANNEL_2                              ((uint32_t)0x00020004U)
+#define DFSDM_CHANNEL_3                              ((uint32_t)0x00030008U)
+#define DFSDM_CHANNEL_4                              ((uint32_t)0x00040010U)
+#define DFSDM_CHANNEL_5                              ((uint32_t)0x00050020U)
+#define DFSDM_CHANNEL_6                              ((uint32_t)0x00060040U)
+#define DFSDM_CHANNEL_7                              ((uint32_t)0x00070080U)
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
+  * @{
+  */
+#define DFSDM_CONTINUOUS_CONV_OFF            ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
+#define DFSDM_CONTINUOUS_CONV_ON             ((uint32_t)0x00000001U) /*!< Conversion are continuous */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
+  * @{
+  */
+#define DFSDM_AWD_HIGH_THRESHOLD            ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
+#define DFSDM_AWD_LOW_THRESHOLD             ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
+ * @{
+ */
+
+/** @brief  Reset DFSDM channel handle state.
+  * @param  __HANDLE__: DFSDM channel handle.
+  * @retval None
+  */
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
+
+/** @brief  Reset DFSDM filter handle state.
+  * @param  __HANDLE__: DFSDM filter handle.
+  * @retval None
+  */
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
+  * @{
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
+  * @{
+  */
+/* Channel initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
+  * @{
+  */
+/* Channel operation functions ************************************************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+
+void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
+  * @{
+  */
+/* Channel state function *****************************************************/
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
+  * @{
+  */
+/* Filter initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
+  * @{
+  */
+/* Filter control functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel,
+                                                   uint32_t                    ContinuousMode);
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
+  * @{
+  */
+/* Filter operation functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                              DFSDM_Filter_AwdParamTypeDef* awdParam);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+
+void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
+void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
+  * @{
+  */
+/* Filter state functions *****************************************************/
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
+* @{
+*/
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
+                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
+#else
+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */
+#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
+                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
+                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
+#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
+                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
+#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
+#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
+#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
+#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1 <= (RATIO)) && ((RATIO) <= 32))
+#define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1F)
+#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFF)
+#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
+#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
+#else
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
+#define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
+#define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1 <= (RATIO)) && ((RATIO) <= 1024))
+#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1 <= (RATIO)) && ((RATIO) <= 256))
+#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
+                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
+#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_3))
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU))
+#else /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_7))
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+#define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
+                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_DFSDM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -55,6 +55,7 @@
   */
 
 /* Exported types ------------------------------------------------------------*/
+
 /** @defgroup DMA_Exported_Types DMA Exported Types
   * @{
   */
@@ -92,27 +93,15 @@ typedef struct
                                            This parameter can be a value of @ref DMA_Priority_level */
 } DMA_InitTypeDef;
 
-/**
-  * @brief DMA Configuration enumeration values definition
-  */
-typedef enum
-{
-  DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
-  DMA_PRIORITY        = 1       /*!< Control related priority level Parameter in DMA_InitTypeDef  */
-
-} DMA_ControlTypeDef;
-
 /**
   * @brief  HAL DMA State structures definition
   */
 typedef enum
 {
   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled    */
-  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use  */
-  HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success               */
+  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use      */
   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing                 */
-  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                      */
-  HAL_DMA_STATE_ERROR             = 0x04   /*!< DMA error state                        */
+  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                     */
 }HAL_DMA_StateTypeDef;
 
 /**
@@ -124,20 +113,34 @@ typedef enum
   HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
 }HAL_DMA_LevelCompleteTypeDef;
 
+
+/**
+  * @brief  HAL DMA Callback ID structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01,    /*!< Half transfer     */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x02,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x03,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */
+
+}HAL_DMA_CallbackIDTypeDef;
+
 /**
   * @brief  DMA handle Structure definition
   */
 typedef struct __DMA_HandleTypeDef
 {
-  DMA_Channel_TypeDef    *Instance;                                                /*!< Register base address                  */
-                                                                                
-  DMA_InitTypeDef       Init;                                                      /*!< DMA communication parameters           */
-                                                                                
-  HAL_LockTypeDef       Lock;                                                      /*!< DMA locking object                     */
-                                                                                
-  __IO HAL_DMA_StateTypeDef  State;                                                /*!< DMA transfer state                     */
-                                                                                
-  void                  *Parent;                                                   /*!< Parent object state                    */
+  DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
+
+  DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
+
+  HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
+
+  __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
+
+  void                  *Parent;                                                     /*!< Parent object state                  */
 
   void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */
 
@@ -145,9 +148,14 @@ typedef struct __DMA_HandleTypeDef
 
   void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */
 
-  __IO uint32_t          ErrorCode;                                                /*!< DMA Error code                         */
-}DMA_HandleTypeDef;
+  void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer abort callback          */
+
+  __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
+
+  DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
 
+  uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */
+}DMA_HandleTypeDef;
 /**
   * @}
   */
@@ -161,9 +169,11 @@ typedef struct __DMA_HandleTypeDef
 /** @defgroup DMA_Error_Code DMA Error Code
   * @{
   */
-#define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
-#define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
-#define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
+#define HAL_DMA_ERROR_NONE          ((uint32_t)0x00000000)    /*!< No error                              */
+#define HAL_DMA_ERROR_TE            ((uint32_t)0x00000001)    /*!< Transfer error                        */
+#define HAL_DMA_ERROR_NO_XFER       ((uint32_t)0x00000004)    /*!< no ongoing transfer                   */
+#define HAL_DMA_ERROR_TIMEOUT       ((uint32_t)0x00000020)    /*!< Timeout error                         */
+#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)    /*!< Not supported mode                    */
 /**
   * @}
   */
@@ -415,11 +425,11 @@ typedef struct __DMA_HandleTypeDef
   * @param  __HANDLE__: DMA handle
   * @param  __FLAG__: Get the specified flag.
   *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
-  *            @arg DMA_ISR_GIFx: Global interrupt flag
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be from 1 to 7 to select the DMA Channel x flag.
   * @retval The state of FLAG (SET or RESET).
   */
 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
@@ -430,15 +440,15 @@ typedef struct __DMA_HandleTypeDef
   * @param  __HANDLE__: DMA handle
   * @param  __FLAG__: specifies the flag to clear.
   *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
-  *            @arg DMA_ISR_GIFx: Global interrupt flag
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be from 1 to 7 to select the DMA Channel x flag.
   * @retval None
   */
 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
- (DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))
+ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
 
 /**
   * @brief  Enable the specified DMA Channel interrupts.
@@ -476,6 +486,13 @@ typedef struct __DMA_HandleTypeDef
   */
 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
 
+/**
+  * @brief  Return the number of remaining data units in the current DMA Channel transfer.
+  * @param  __HANDLE__: DMA handle
+  * @retval The number of remaining data units in the current DMA Channel transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
 /**
   * @}
   */
@@ -503,8 +520,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
 /**
   * @}
   */
@@ -567,7 +588,7 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 
 /**
   * @}
-  */ 
+  */
 
 /* Private functions ---------------------------------------------------------*/
 

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h

@@ -0,0 +1,619 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dma2d.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of DMA2D HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DMA2D_H
+#define __STM32L4xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA2D DMA2D
+  * @brief DMA2D HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
+  * @{
+  */
+#define MAX_DMA2D_LAYER  2U
+
+/**
+  * @brief DMA2D color Structure definition
+  */
+typedef struct
+{
+  uint32_t Blue;               /*!< Configures the blue value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Green;              /*!< Configures the green value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Red;                /*!< Configures the red value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+} DMA2D_ColorTypeDef;
+
+/**
+  * @brief DMA2D CLUT Structure definition
+  */
+typedef struct
+{
+  uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
+
+  uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
+                                         This parameter can be one value of @ref DMA2D_CLUT_CM. */
+
+  uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+} DMA2D_CLUTCfgTypeDef;
+
+/**
+  * @brief DMA2D Init structure definition
+  */
+typedef struct
+{
+  uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
+                                                This parameter can be one value of @ref DMA2D_Mode. */
+
+  uint32_t             ColorMode;          /*!< Configures the color format of the output image.
+                                                This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
+
+  uint32_t             OutputOffset;       /*!< Specifies the Offset value.
+                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
+
+  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
+                                               for the output pixel format converter.
+                                               This parameter can be one value of @ref DMA2D_RB_Swap. */
+} DMA2D_InitTypeDef;
+
+
+/**
+  * @brief DMA2D Layer structure definition
+  */
+typedef struct
+{
+  uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
+                                               This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+  uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.
+                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
+
+  uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Mode. */
+
+  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
+                                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
+                                               @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
+                                               Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
+                                               - InputAlpha[24:31] is the alpha value ALPHA[0:7]
+                                               - InputAlpha[16:23] is the red value RED[0:7]
+                                               - InputAlpha[8:15] is the green value GREEN[0:7]
+                                               - InputAlpha[0:7] is the blue value BLUE[0:7]. */
+
+  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
+
+  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
+                                               This parameter can be one value of @ref DMA2D_RB_Swap. */
+
+} DMA2D_LayerCfgTypeDef;
+
+/**
+  * @brief  HAL DMA2D State structures definition
+  */
+typedef enum
+{
+  HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
+  HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
+  HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
+}HAL_DMA2D_StateTypeDef;
+
+/**
+  * @brief  DMA2D handle Structure definition
+  */
+typedef struct __DMA2D_HandleTypeDef
+{
+  DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */
+
+  DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */
+
+  void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */
+
+  void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */
+
+  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters                    */
+
+  HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */
+
+  __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */
+
+  __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */
+} DMA2D_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_Error_Code DMA2D Error Code
+  * @{
+  */
+#define HAL_DMA2D_ERROR_NONE        ((uint32_t)0x00000000U)  /*!< No error             */
+#define HAL_DMA2D_ERROR_TE          ((uint32_t)0x00000001U)  /*!< Transfer error       */
+#define HAL_DMA2D_ERROR_CE          ((uint32_t)0x00000002U)  /*!< Configuration error  */
+#define HAL_DMA2D_ERROR_CAE         ((uint32_t)0x00000004U)  /*!< CLUT access error    */
+#define HAL_DMA2D_ERROR_TIMEOUT     ((uint32_t)0x00000020U)  /*!< Timeout error        */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Mode DMA2D Mode
+  * @{
+  */
+#define DMA2D_M2M                   ((uint32_t)0x00000000U)  /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC               DMA2D_CR_MODE_0          /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1          /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
+  * @{
+  */
+#define DMA2D_OUTPUT_ARGB8888       ((uint32_t)0x00000000U)               /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
+#define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
+#define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
+  * @{
+  */
+#define DMA2D_INPUT_ARGB8888        ((uint32_t)0x00000000U)  /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888          ((uint32_t)0x00000001U)  /*!< RGB888 color mode   */
+#define DMA2D_INPUT_RGB565          ((uint32_t)0x00000002U)  /*!< RGB565 color mode   */
+#define DMA2D_INPUT_ARGB1555        ((uint32_t)0x00000003U)  /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444        ((uint32_t)0x00000004U)  /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8              ((uint32_t)0x00000005U)  /*!< L8 color mode       */
+#define DMA2D_INPUT_AL44            ((uint32_t)0x00000006U)  /*!< AL44 color mode     */
+#define DMA2D_INPUT_AL88            ((uint32_t)0x00000007U)  /*!< AL88 color mode     */
+#define DMA2D_INPUT_L4              ((uint32_t)0x00000008U)  /*!< L4 color mode       */
+#define DMA2D_INPUT_A8              ((uint32_t)0x00000009U)  /*!< A8 color mode       */
+#define DMA2D_INPUT_A4              ((uint32_t)0x0000000AU)  /*!< A4 color mode       */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
+  * @{
+  */
+#define DMA2D_NO_MODIF_ALPHA        ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA         ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA         ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value
+                                                                with original alpha channel value                              */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
+  * @{
+  */
+#define DMA2D_REGULAR_ALPHA         ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
+#define DMA2D_INVERTED_ALPHA        ((uint32_t)0x00000001U)  /*!< Invert the alpha channel value */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
+  * @{
+  */
+#define DMA2D_RB_REGULAR            ((uint32_t)0x00000000U)  /*!< Select regular mode (RGB or ARGB) */
+#define DMA2D_RB_SWAP               ((uint32_t)0x00000001U)  /*!< Select swap mode (BGR or ABGR) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
+  * @{
+  */
+#define DMA2D_CCM_ARGB8888          ((uint32_t)0x00000000U)  /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888            ((uint32_t)0x00000001U)  /*!< RGB888 DMA2D CLUT color mode   */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts
+  * @{
+  */
+#define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
+#define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Flags DMA2D Flags
+  * @{
+  */
+#define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+  * @{
+  */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
+  * @{
+  */
+
+/** @brief Reset DMA2D handle state
+  * @param  __HANDLE__: specifies the DMA2D handle.
+  * @retval None
+  */
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+
+/**
+  * @brief  Enable the DMA2D.
+  * @param  __HANDLE__: DMA2D handle
+  * @retval None.
+  */
+#define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DMA2D pending flags.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __FLAG__: flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag
+  * @retval The state of FLAG.
+  */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+  * @brief  Clear the DMA2D pending flags.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag
+  * @retval None
+  */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DMA2D interrupts.
+  * @param  __HANDLE__: DMA2D handle
+  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA2D interrupts.
+  * @param  __HANDLE__: DMA2D handle
+  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval The state of INTERRUPT source.
+  */
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
+void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
+uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
+  * @{
+  */
+#define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Color_Value DMA2D Color Value
+  * @{
+  */
+#define DMA2D_COLOR_VALUE                 ((uint32_t)0x000000FFU)  /*!< Color value mask */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
+  * @{
+  */
+#define DMA2D_MAX_LAYER         2         /*!< DMA2D maximum number of layers */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Offset DMA2D Offset
+  * @{
+  */
+#define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< Line Offset */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Size DMA2D Size
+  * @{
+  */
+#define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D number of pixels per line */
+#define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D number of lines           */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
+  * @{
+  */
+#define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8)  /*!< DMA2D CLUT size */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
+  * @{
+  */
+#define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= DMA2D_MAX_LAYER)
+#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
+                                               ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
+#define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
+#define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
+                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
+                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_A4))
+#define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
+                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+
+#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
+                                                 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
+
+#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
+                                   ((RB_Swap) == DMA2D_RB_SWAP))
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
+#define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+                                               ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+                                               ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+#define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+                                               ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
+                                               ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L496xx || STM32L4A6xx || */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_DMA2D_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_firewall.h

@@ -0,0 +1,372 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_firewall.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of FIREWALL HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_FIREWALL_H
+#define __STM32L4xx_HAL_FIREWALL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FIREWALL  FIREWALL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FIREWALL_Exported_Types FIREWALL Exported Types
+  * @{
+  */
+
+/**
+  * @brief FIREWALL Initialization Structure definition
+  */
+typedef struct
+{
+  uint32_t CodeSegmentStartAddress;        /*!< Protected code segment start address. This value is 24-bit long, the 8 LSB bits are
+                                                reserved and forced to 0 in order to allow a 256-byte granularity. */
+
+  uint32_t CodeSegmentLength;              /*!< Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are
+                                                reserved and forced to 0 for the length to be a multiple of 256 bytes. */
+
+  uint32_t NonVDataSegmentStartAddress;    /*!< Protected non-volatile data segment start address. This value is 24-bit long, the 8 LSB
+                                                bits are reserved and forced to 0 in order to allow a 256-byte granularity. */
+
+  uint32_t NonVDataSegmentLength;          /*!< Protected non-volatile data segment length in bytes. This value is 22-bit long, the 8 LSB
+                                                bits are reserved and forced to 0 for the length to be a multiple of 256 bytes. */
+
+  uint32_t VDataSegmentStartAddress;       /*!< Protected volatile data segment start address. This value is 17-bit long, the 6 LSB bits
+                                                are reserved and forced to 0 in order to allow a 64-byte granularity. */
+
+  uint32_t VDataSegmentLength;             /*!< Protected volatile data segment length in bytes. This value is 17-bit long, the 6 LSB
+                                                bits are reserved and forced to 0 for the length to be a multiple of 64 bytes. */
+
+  uint32_t VolatileDataExecution;          /*!< Set VDE bit specifying whether or not the volatile data segment can be executed.
+                                                 When VDS = 1 (set by parameter VolatileDataShared), VDE bit has no meaning.
+                                                This parameter can be a value of @ref FIREWALL_VolatileData_Executable */
+
+  uint32_t VolatileDataShared;             /*!< Set VDS bit in specifying whether or not the volatile data segment can be shared with a
+                                                non-protected application code.
+                                                This parameter can be a value of @ref FIREWALL_VolatileData_Shared */
+
+}FIREWALL_InitTypeDef;
+
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FIREWALL_Exported_Constants FIREWALL Exported Constants
+  * @{
+  */
+
+/** @defgroup FIREWALL_VolatileData_Executable   FIREWALL volatile data segment execution status
+  * @{
+  */
+#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE                 ((uint32_t)0x0000)
+#define FIREWALL_VOLATILEDATA_EXECUTABLE                     ((uint32_t)FW_CR_VDE)
+/**
+  * @}
+  */
+
+/** @defgroup FIREWALL_VolatileData_Shared  FIREWALL volatile data segment share status
+  * @{
+  */
+#define FIREWALL_VOLATILEDATA_NOT_SHARED                ((uint32_t)0x0000)
+#define FIREWALL_VOLATILEDATA_SHARED                    ((uint32_t)FW_CR_VDS)
+/**
+  * @}
+  */
+
+/** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status
+  * @{
+  */
+#define FIREWALL_PRE_ARM_RESET                 ((uint32_t)0x0000)
+#define FIREWALL_PRE_ARM_SET                   ((uint32_t)FW_CR_FPA)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup FIREWALL_Private_Macros   FIREWALL Private Macros
+  * @{
+  */
+#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
+#define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
+
+#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
+#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
+
+#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= SRAM1_BASE) && ((ADDRESS) < (SRAM1_BASE + SRAM1_SIZE_MAX)))
+#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM1_BASE + SRAM1_SIZE_MAX))
+
+
+#define IS_FIREWALL_VOLATILEDATA_SHARE(SHARE) (((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \
+                                               ((SHARE) == FIREWALL_VOLATILEDATA_SHARED))
+
+#define IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE) (((EXECUTE) == FIREWALL_VOLATILEDATA_NOT_EXECUTABLE) || \
+                                                   ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE))
+/**
+  * @}
+  */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FIREWALL_Exported_Macros FIREWALL Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether the FIREWALL is enabled or not.
+  * @retval FIREWALL enabling status (TRUE or FALSE).
+  */
+#define  __HAL_FIREWALL_IS_ENABLED()  HAL_IS_BIT_CLR(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS)
+
+
+/** @brief Enable FIREWALL pre arm.
+  * @note When FPA bit is set, any code executed outside the protected segment
+  *       closes the Firewall, otherwise it generates a system reset.
+  * @note This macro provides the same service as HAL_FIREWALL_EnablePreArmFlag() API
+  *       but can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  */
+#define __HAL_FIREWALL_PREARM_ENABLE()                                         \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_FPA) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+
+
+/** @brief Disable FIREWALL pre arm.
+  * @note When FPA bit is set, any code executed outside the protected segment
+  *       closes the Firewall, otherwise, it generates a system reset.
+  * @note This macro provides the same service as HAL_FIREWALL_DisablePreArmFlag() API
+  *       but can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  */
+#define __HAL_FIREWALL_PREARM_DISABLE()                                        \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Enable volatile data sharing in setting VDS bit.
+  * @note When VDS bit is set, the volatile data segment is shared with non-protected
+  *       application code. It can be accessed whatever the Firewall state (opened or closed).
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  */
+#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE()                            \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_VDS) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Disable volatile data sharing in resetting VDS bit.
+  * @note When VDS bit is reset, the volatile data segment is not shared and cannot be
+  *       hit by a non protected executable code when the Firewall is closed. If it is
+  *       accessed in such a condition, a system reset is generated by the Firewall.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  */
+#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE()                           \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Enable volatile data execution in setting VDE bit.
+  * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be
+  *       executed whatever the VDE bit value.
+  * @note When VDE bit is set (with VDS = 0), the volatile data segment is executable. When
+  *       the Firewall call is closed, a "call gate" entry procedure is required to open
+  *       first the Firewall.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  */
+#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE()                         \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_VDE) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Disable volatile data execution in resetting VDE bit.
+  * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be
+  *       executed whatever the VDE bit value.
+  * @note When VDE bit is reset (with VDS = 0), the volatile data segment cannot  be executed.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  */
+#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE()                           \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+
+/** @brief Check whether or not the volatile data segment is shared.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  * @retval VDS bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)
+
+/** @brief Check whether or not the volatile data segment is declared executable.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  * @retval VDE bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)
+
+/** @brief Check whether or not the Firewall pre arm bit is set.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.
+  * @retval FPA bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup FIREWALL_Exported_Functions FIREWALL Exported Functions
+  * @{
+  */
+
+/** @addtogroup FIREWALL_Exported_Functions_Group1 Initialization Functions
+  * @brief    Initialization and Configuration Functions
+  * @{
+  */
+
+/* Initialization functions  ********************************/
+HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init);
+void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config);
+void HAL_FIREWALL_EnableFirewall(void);
+void HAL_FIREWALL_EnablePreArmFlag(void);
+void HAL_FIREWALL_DisablePreArmFlag(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_FIREWALL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V1.3.0 
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of FLASH HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -52,7 +52,7 @@
 
 /** @addtogroup FLASH
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup FLASH_Exported_Types FLASH Exported Types
@@ -63,17 +63,17 @@
   * @brief  FLASH Erase structure definition
   */
 typedef struct
-{ 
+{
   uint32_t TypeErase;   /*!< Mass erase or page erase.
                              This parameter can be a value of @ref FLASH_Type_Erase */
   uint32_t Banks;       /*!< Select bank to erase.
-                             This parameter must be a value of @ref FLASH_Banks 
-                             (FLASH_BANK_BOTH should be used only for mass erase) */        
+                             This parameter must be a value of @ref FLASH_Banks
+                             (FLASH_BANK_BOTH should be used only for mass erase) */
   uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled
-                             This parameter must be a value between 0 and (max number of pages in the bank - 1) 
+                             This parameter must be a value between 0 and (max number of pages in the bank - 1)
                              (eg : 255 for 1MB dual bank) */
   uint32_t NbPages;     /*!< Number of pages to be erased.
-                             This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/           
+                             This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
 } FLASH_EraseInitTypeDef;
 
 /**
@@ -98,16 +98,16 @@ typedef struct
   uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).
                                 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
                                 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
-                                @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 
-                                @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 
-                                @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 
-                                @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 
+                                @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
+                                @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
+                                @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,
+                                @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,
                                 @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
   uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
-                                This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 
+                                This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
                                 and @ref FLASH_OB_PCROP_RDP */
   uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
-                                This parameter must be a value between begin and end of bank 
+                                This parameter must be a value between begin and end of bank
                                 => Be careful of the bank swapping for the address */
   uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
                                 This parameter must be a value between PCROP Start address and end of bank */
@@ -116,7 +116,7 @@ typedef struct
 /**
   * @brief  FLASH Procedure structure definition
   */
-typedef enum 
+typedef enum
 {
   FLASH_PROC_NONE = 0,
   FLASH_PROC_PAGE_ERASE,
@@ -125,8 +125,19 @@ typedef enum
   FLASH_PROC_PROGRAM_LAST
 } FLASH_ProcedureTypeDef;
 
-/** 
-  * @brief  FLASH handle Structure definition  
+/**
+  * @brief  FLASH Cache structure definition
+  */
+typedef enum
+{
+  FLASH_CACHE_DISABLED = 0,
+  FLASH_CACHE_ICACHE_ENABLED,
+  FLASH_CACHE_DCACHE_ENABLED,
+  FLASH_CACHE_ICACHE_DCACHE_ENABLED
+} FLASH_CacheTypeDef;
+
+/**
+  * @brief  FLASH handle Structure definition
   */
 typedef struct
 {
@@ -137,6 +148,7 @@ typedef struct
   __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */
   __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */
   __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
+  __IO FLASH_CacheTypeDef     CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
 }FLASH_ProcessTypeDef;
 
 /**
@@ -150,7 +162,7 @@ typedef struct
 
 /** @defgroup FLASH_Error FLASH Error
   * @{
-  */ 
+  */
 #define HAL_FLASH_ERROR_NONE      ((uint32_t)0x00000000)
 #define HAL_FLASH_ERROR_OP        ((uint32_t)0x00000001)
 #define HAL_FLASH_ERROR_PROG      ((uint32_t)0x00000002)
@@ -163,13 +175,17 @@ typedef struct
 #define HAL_FLASH_ERROR_RD        ((uint32_t)0x00000100)
 #define HAL_FLASH_ERROR_OPTV      ((uint32_t)0x00000200)
 #define HAL_FLASH_ERROR_ECCD      ((uint32_t)0x00000400)
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define HAL_FLASH_ERROR_PEMPTY    ((uint32_t)0x00000800)
+#endif
 /**
   * @}
   */
 
 /** @defgroup FLASH_Type_Erase FLASH Erase Type
   * @{
-  */ 
+  */
 #define FLASH_TYPEERASE_PAGES     ((uint32_t)0x00)  /*!<Pages erase only*/
 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)  /*!<Flash mass erase activation*/
 /**
@@ -180,8 +196,13 @@ typedef struct
   * @{
   */
 #define FLASH_BANK_1              ((uint32_t)0x01)                          /*!< Bank 1   */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define FLASH_BANK_2              ((uint32_t)0x02)                          /*!< Bank 2   */
 #define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */
+#else
+#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1))                /*!< Bank 1   */
+#endif
 /**
   * @}
   */
@@ -212,11 +233,14 @@ typedef struct
 
 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
   * @{
-  */ 
+  */
 #define OB_WRPAREA_BANK1_AREAA    ((uint32_t)0x00)  /*!< Flash Bank 1 Area A */
 #define OB_WRPAREA_BANK1_AREAB    ((uint32_t)0x01)  /*!< Flash Bank 1 Area B */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define OB_WRPAREA_BANK2_AREAA    ((uint32_t)0x02)  /*!< Flash Bank 2 Area A */
 #define OB_WRPAREA_BANK2_AREAB    ((uint32_t)0x04)  /*!< Flash Bank 2 Area B */
+#endif
 /**
   * @}
   */
@@ -226,11 +250,11 @@ typedef struct
   */
 #define OB_RDP_LEVEL_0            ((uint32_t)0xAA)
 #define OB_RDP_LEVEL_1            ((uint32_t)0xBB)
-#define OB_RDP_LEVEL_2            ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 
+#define OB_RDP_LEVEL_2            ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2
                                                         it's no more possible to go back to level 1 or 0 */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
   * @{
@@ -242,15 +266,24 @@ typedef struct
 #define OB_USER_IWDG_STOP         ((uint32_t)0x0010)                   /*!< Independent watchdog counter freeze in stop mode */
 #define OB_USER_IWDG_STDBY        ((uint32_t)0x0020)                   /*!< Independent watchdog counter freeze in standby mode */
 #define OB_USER_WWDG_SW           ((uint32_t)0x0040)                   /*!< Window watchdog selection */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define OB_USER_BFB2              ((uint32_t)0x0080)                   /*!< Dual-bank boot */
 #define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
+#endif
 #define OB_USER_nBOOT1            ((uint32_t)0x0200)                   /*!< Boot configuration */
 #define OB_USER_SRAM2_PE          ((uint32_t)0x0400)                   /*!< SRAM2 parity check enable */
 #define OB_USER_SRAM2_RST         ((uint32_t)0x0800)                   /*!< SRAM2 Erase when system reset */
 #define OB_USER_nRST_SHDW         ((uint32_t)0x1000)                   /*!< Reset generated when entering the shutdown mode */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define OB_USER_nSWBOOT0          ((uint32_t)0x2000)                   /*!< Software BOOT0 */
+#define OB_USER_nBOOT0            ((uint32_t)0x4000)                   /*!< nBOOT0 option bit */
+#endif
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
   * @{
@@ -262,16 +295,16 @@ typedef struct
 #define OB_BOR_LEVEL_4            ((uint32_t)FLASH_OPTR_BOR_LEV_4)     /*!< Reset level threshold is around 2.8V */
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 
+/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
   * @{
   */
 #define OB_STOP_RST               ((uint32_t)0x0000)                   /*!< Reset generated when entering the stop mode */
 #define OB_STOP_NORST             ((uint32_t)FLASH_OPTR_nRST_STOP)     /*!< No reset generated when entering the stop mode */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
   * @{
@@ -280,7 +313,7 @@ typedef struct
 #define OB_STANDBY_NORST          ((uint32_t)FLASH_OPTR_nRST_STDBY)    /*!< No reset generated when entering the standby mode */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
   * @{
@@ -289,7 +322,7 @@ typedef struct
 #define OB_SHUTDOWN_NORST         ((uint32_t)FLASH_OPTR_nRST_SHDW)     /*!< No reset generated when entering the shutdown mode */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
   * @{
@@ -298,7 +331,7 @@ typedef struct
 #define OB_IWDG_SW                ((uint32_t)FLASH_OPTR_IWDG_SW)       /*!< Software independent watchdog */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
   * @{
@@ -307,7 +340,7 @@ typedef struct
 #define OB_IWDG_STOP_RUN          ((uint32_t)FLASH_OPTR_IWDG_STOP)     /*!< Independent watchdog counter is running in Stop mode */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
   * @{
@@ -316,7 +349,7 @@ typedef struct
 #define OB_IWDG_STDBY_RUN         ((uint32_t)FLASH_OPTR_IWDG_STDBY)    /*!< Independent watchdog counter is running in Standby mode */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
   * @{
@@ -325,8 +358,10 @@ typedef struct
 #define OB_WWDG_SW                ((uint32_t)FLASH_OPTR_WWDG_SW)       /*!< Software window watchdog */
 /**
   * @}
-  */ 
+  */
 
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
   * @{
   */
@@ -334,8 +369,7 @@ typedef struct
 #define OB_BFB2_ENABLE            ((uint32_t)FLASH_OPTR_BFB2)          /*!< Dual-bank boot enable */
 /**
   * @}
-  */ 
-
+  */
 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
   * @{
   */
@@ -343,7 +377,8 @@ typedef struct
 #define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DUALBANK)      /*!< 256 KB/512 KB Dual-bank Flash */
 /**
   * @}
-  */ 
+  */
+#endif
 
 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
   * @{
@@ -352,7 +387,7 @@ typedef struct
 #define OB_BOOT1_SYSTEM           ((uint32_t)FLASH_OPTR_nBOOT1)        /*!< System memory is selected as boot space (if BOOT0=1) */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
   * @{
@@ -361,7 +396,7 @@ typedef struct
 #define OB_SRAM2_PARITY_DISABLE   ((uint32_t)FLASH_OPTR_SRAM2_PE)      /*!< SRAM2 parity check disable */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
   * @{
@@ -370,22 +405,44 @@ typedef struct
 #define OB_SRAM2_RST_NOT_ERASE    ((uint32_t)FLASH_OPTR_SRAM2_RST)     /*!< SRAM2 is not erased when a system reset occurs */
 /**
   * @}
-  */ 
+  */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+/** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
+  * @{
+  */
+#define OB_BOOT0_FROM_OB          ((uint32_t)0x0000000)                /*!< BOOT0 taken from the option bit nBOOT0 */
+#define OB_BOOT0_FROM_PIN         ((uint32_t)FLASH_OPTR_nSWBOOT0)      /*!< BOOT0 taken from PH3/BOOT0 pin */
+/**
+  * @}
+  */
+
+/** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
+  * @{
+  */
+#define OB_BOOT0_RESET            ((uint32_t)0x0000000)                /*!< nBOOT0 = 0 */
+#define OB_BOOT0_SET              ((uint32_t)FLASH_OPTR_nBOOT0)        /*!< nBOOT0 = 1 */
+/**
+  * @}
+  */
+#endif
 
 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
   * @{
   */
-#define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000)               /*!< PCROP area is not erased when the RDP level 
+#define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000)               /*!< PCROP area is not erased when the RDP level
                                                                             is decreased from Level 1 to Level 0 */
-#define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 
+#define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is
                                                                             decreased from Level 1 to Level 0 (full mass erase) */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_Latency FLASH Latency
   * @{
-  */ 
+  */
 #define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS                /*!< FLASH Zero wait state */
 #define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS                /*!< FLASH One wait state */
 #define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS                /*!< FLASH Two wait states */
@@ -393,21 +450,21 @@ typedef struct
 #define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS                /*!< FLASH Four wait states */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_Keys FLASH Keys
   * @{
-  */ 
+  */
 #define FLASH_KEY1                ((uint32_t)0x45670123U)               /*!< Flash key1 */
-#define FLASH_KEY2                ((uint32_t)0xCDEF89ABU)               /*!< Flash key2: used with FLASH_KEY1 
+#define FLASH_KEY2                ((uint32_t)0xCDEF89ABU)               /*!< Flash key2: used with FLASH_KEY1
                                                                             to unlock the FLASH registers access */
 
 #define FLASH_PDKEY1              ((uint32_t)0x04152637U)               /*!< Flash power down key1 */
-#define FLASH_PDKEY2              ((uint32_t)0xFAFBFCFDU)               /*!< Flash power down key2: used with FLASH_PDKEY1 
+#define FLASH_PDKEY2              ((uint32_t)0xFAFBFCFDU)               /*!< Flash power down key2: used with FLASH_PDKEY1
                                                                             to unlock the RUN_PD bit in FLASH_ACR */
 
 #define FLASH_OPTKEY1             ((uint32_t)0x08192A3BU)               /*!< Flash option byte key1 */
-#define FLASH_OPTKEY2             ((uint32_t)0x4C5D6E7FU)               /*!< Flash option byte key2: used with FLASH_OPTKEY1 
+#define FLASH_OPTKEY2             ((uint32_t)0x4C5D6E7FU)               /*!< Flash option byte key2: used with FLASH_OPTKEY1
                                                                             to allow option bytes operations */
 /**
   * @}
@@ -415,7 +472,7 @@ typedef struct
 
 /** @defgroup FLASH_Flags FLASH Flags Definition
   * @{
-  */ 
+  */
 #define FLASH_FLAG_EOP            FLASH_SR_EOP                         /*!< FLASH End of operation flag */
 #define FLASH_FLAG_OPERR          FLASH_SR_OPERR                       /*!< FLASH Operation error flag */
 #define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR                     /*!< FLASH Programming error flag */
@@ -428,6 +485,10 @@ typedef struct
 #define FLASH_FLAG_RDERR          FLASH_SR_RDERR                       /*!< FLASH PCROP read error flag */
 #define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR                     /*!< FLASH Option validity error flag  */
 #define FLASH_FLAG_BSY            FLASH_SR_BSY                         /*!< FLASH Busy flag */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define FLASH_FLAG_PEMPTY         FLASH_SR_PEMPTY                      /*!< FLASH Program empty */
+#endif
 #define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC                      /*!< FLASH ECC correction */
 #define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD                      /*!< FLASH ECC detection */
 
@@ -437,19 +498,19 @@ typedef struct
                                    FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
   * @brief FLASH Interrupt definition
   * @{
-  */ 
+  */
 #define FLASH_IT_EOP              FLASH_CR_EOPIE                       /*!< End of FLASH Operation Interrupt source */
 #define FLASH_IT_OPERR            FLASH_CR_ERRIE                       /*!< Error Interrupt source */
 #define FLASH_IT_RDERR            FLASH_CR_RDERRIE                     /*!< PCROP Read Error Interrupt source*/
 #define FLASH_IT_ECCC             (FLASH_ECCR_ECCIE >> 24)             /*!< ECC Correction Interrupt source */
 /**
   * @}
-  */  
+  */
 
 /**
   * @}
@@ -457,39 +518,39 @@ typedef struct
 
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- *  @brief macros to control FLASH features 
+ *  @brief macros to control FLASH features
  *  @{
  */
 
 /**
   * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__: FLASH Latency                   
+  * @param  __LATENCY__: FLASH Latency
   *         This parameter can be one of the following values :
   *     @arg FLASH_LATENCY_0: FLASH Zero wait state
-  *     @arg FLASH_LATENCY_1: FLASH One wait state    
+  *     @arg FLASH_LATENCY_1: FLASH One wait state
   *     @arg FLASH_LATENCY_2: FLASH Two wait states
   *     @arg FLASH_LATENCY_3: FLASH Three wait states
   *     @arg FLASH_LATENCY_4: FLASH Four wait states
   * @retval None
-  */ 
+  */
 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
 
 /**
   * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency                   
+  * @retval FLASH Latency
   *         This parameter can be one of the following values :
   *     @arg FLASH_LATENCY_0: FLASH Zero wait state
-  *     @arg FLASH_LATENCY_1: FLASH One wait state    
+  *     @arg FLASH_LATENCY_1: FLASH One wait state
   *     @arg FLASH_LATENCY_2: FLASH Two wait states
   *     @arg FLASH_LATENCY_3: FLASH Three wait states
   *     @arg FLASH_LATENCY_4: FLASH Four wait states
-  */ 
+  */
 #define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
 
 /**
   * @brief  Enable the FLASH prefetch buffer.
   * @retval None
-  */ 
+  */
 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
 
 /**
@@ -501,30 +562,30 @@ typedef struct
 /**
   * @brief  Enable the FLASH instruction cache.
   * @retval none
-  */ 
+  */
 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
 
 /**
   * @brief  Disable the FLASH instruction cache.
   * @retval none
-  */ 
+  */
 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
 
 /**
   * @brief  Enable the FLASH data cache.
   * @retval none
-  */ 
+  */
 #define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
 
 /**
   * @brief  Disable the FLASH data cache.
   * @retval none
-  */ 
+  */
 #define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
 
 /**
   * @brief  Reset the FLASH instruction Cache.
-  * @note   This function must be used only when the Instruction Cache is disabled.  
+  * @note   This function must be used only when the Instruction Cache is disabled.
   * @retval None
   */
 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
@@ -533,7 +594,7 @@ typedef struct
 
 /**
   * @brief  Reset the FLASH data Cache.
-  * @note   This function must be used only when the data Cache is disabled.  
+  * @note   This function must be used only when the data Cache is disabled.
   * @retval None
   */
 #define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
@@ -563,48 +624,48 @@ typedef struct
 /**
   * @brief  Enable the FLASH power down during Low-Power sleep mode
   * @retval none
-  */ 
+  */
 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
 
 /**
   * @brief  Disable the FLASH power down during Low-Power sleep mode
   * @retval none
-  */ 
+  */
 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
 
 /**
   * @}
-  */  
+  */
 
 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
  *  @brief macros to handle FLASH interrupts
  * @{
- */ 
+ */
 
 /**
   * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__: FLASH interrupt 
+  * @param  __INTERRUPT__: FLASH interrupt
   *         This parameter can be any combination of the following values:
   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_OPERR: Error Interrupt    
+  *     @arg FLASH_IT_OPERR: Error Interrupt
   *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
   *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
   * @retval none
-  */  
+  */
 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
                                                      if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
                                                    } while(0)
 
 /**
   * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__: FLASH interrupt 
+  * @param  __INTERRUPT__: FLASH interrupt
   *         This parameter can be any combination of the following values:
   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_OPERR: Error Interrupt    
+  *     @arg FLASH_IT_OPERR: Error Interrupt
   *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
   *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
   * @retval none
-  */  
+  */
 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
                                                      if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
                                                    } while(0)
@@ -616,7 +677,7 @@ typedef struct
   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
   *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
   *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
-  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
   *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
   *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
   *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
@@ -624,7 +685,8 @@ typedef struct
   *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
   *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
   *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
-  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 
+  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+  *     @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
   *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
   *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
   * @retval The new state of FLASH_FLAG (SET or RESET).
@@ -640,7 +702,7 @@ typedef struct
   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
   *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
   *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
-  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
   *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
   *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
   *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
@@ -658,13 +720,13 @@ typedef struct
                                                    } while(0)
 /**
   * @}
-  */  
+  */
 
 /* Include FLASH HAL Extended module */
 #include "stm32l4xx_hal_flash_ex.h"
 #include "stm32l4xx_hal_flash_ramfunc.h"
 
-/* Exported functions --------------------------------------------------------*/ 
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup FLASH_Exported_Functions
   * @{
   */
@@ -677,7 +739,7 @@ HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uin
 HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
 /* FLASH IRQ handler method */
 void               HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */ 
+/* Callbacks in non blocking modes */
 void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
 void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
 /**
@@ -716,11 +778,21 @@ uint32_t HAL_FLASH_GetError(void);
   * @{
   */
 #define FLASH_SIZE_DATA_REGISTER           ((uint32_t)0x1FFF75E0)
-    
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define FLASH_SIZE                         ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \
+                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
+#else
 #define FLASH_SIZE                         ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
                                             (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
+#endif
 
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define FLASH_BANK_SIZE                    (FLASH_SIZE >> 1)
+#else
+#define FLASH_BANK_SIZE                    (FLASH_SIZE)
+#endif
 
 #define FLASH_PAGE_SIZE                    ((uint32_t)0x800)
 
@@ -728,50 +800,77 @@ uint32_t HAL_FLASH_GetError(void);
 /**
   * @}
   */
- 
+
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup FLASH_Private_Macros FLASH Private Macros
  *  @{
  */
 
 #define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \
-                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
+                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))
 
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
                                             ((BANK) == FLASH_BANK_2)  || \
                                             ((BANK) == FLASH_BANK_BOTH))
 
 #define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
                                             ((BANK) == FLASH_BANK_2))
+#else
+#define IS_FLASH_BANK(BANK)                ((BANK) == FLASH_BANK_1)
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      ((BANK) == FLASH_BANK_1)
+#endif
 
 #define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
                                             ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
-                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))  
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
 
 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE)        && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
                                             ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
                                             ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
-                                            ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))) 
+                                            ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \
+                                            ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))))
 
 #define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
 
 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
 
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
 #define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
                                             ((PAGE) < 256)))))
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
+                                            ((PAGE) < 256))))
+#else
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80)  ? ((PAGE) < 64) : \
+                                            ((PAGE) < 128))))
+#endif
 
 #define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
 
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
                                             ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
+#else
+#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
+#endif
 
 #define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0)   ||\
                                             ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
                                             ((LEVEL) == OB_RDP_LEVEL_2)*/)
 
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
 #define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
+#else
+#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0))
+#endif
 
 #define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
                                             ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
@@ -791,9 +890,12 @@ uint32_t HAL_FLASH_GetError(void);
 
 #define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
 
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
 
 #define IS_OB_USER_DUALBANK(VALUE)         (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
+#endif
 
 #define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
 
@@ -801,6 +903,14 @@ uint32_t HAL_FLASH_GetError(void);
 
 #define IS_OB_USER_SRAM2_RST(VALUE)        (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
 
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
+    defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_OB_USER_SWBOOT0(VALUE)          (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
+
+#define IS_OB_USER_BOOT0(VALUE)            (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))
+#endif
+
 #define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
 
 #define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || \
@@ -810,15 +920,15 @@ uint32_t HAL_FLASH_GetError(void);
                                             ((LATENCY) == FLASH_LATENCY_4))
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0 
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of FLASH HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -52,7 +52,7 @@
 
 /** @addtogroup FLASHEx
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 
@@ -60,7 +60,7 @@
 
 /* Exported macro ------------------------------------------------------------*/
 
-/* Exported functions --------------------------------------------------------*/ 
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup FLASHEx_Exported_Functions
   * @{
   */
@@ -75,19 +75,19 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_flash_ramfunc.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of FLASH RAMFUNC driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L4xx_FLASH_RAMFUNC_H
@@ -52,42 +52,42 @@
 
 /** @addtogroup FLASH_RAMFUNC
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /* Exported macro ------------------------------------------------------------*/
-/** 
+/**
   * @brief  __RAM_FUNC definition
-  */ 
+  */
 #if defined ( __CC_ARM   )
 /* ARM Compiler
    ------------
-   RAM functions are defined using the toolchain options. 
+   RAM functions are defined using the toolchain options.
    Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
    area of a module to a memory space in physical RAM.
    Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog. 
+   dialog.
 */
-#define __RAM_FUNC HAL_StatusTypeDef 
+#define __RAM_FUNC HAL_StatusTypeDef
 
 #elif defined ( __ICCARM__ )
 /* ICCARM Compiler
    ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
 */
 #define __RAM_FUNC __ramfunc HAL_StatusTypeDef
 
 #elif defined   (  __GNUC__  )
 /* GNU Compiler
    ------------
-  RAM functions are defined using a specific toolchain attribute 
+  RAM functions are defined using a specific toolchain attribute
    "__attribute__((section(".RamFunc")))".
 */
 #define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
 
 #endif
-                                      
+
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup FLASH_RAMFUNC_Exported_Functions
@@ -102,15 +102,15 @@ __RAM_FUNC  HAL_FLASHEx_EnableRunPowerDown(void);
 __RAM_FUNC  HAL_FLASHEx_DisableRunPowerDown(void);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -76,7 +76,7 @@ typedef struct
   uint32_t Speed;      /*!< Specifies the speed for the selected pins.
                            This parameter can be a value of @ref GPIO_speed */
 
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins 
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
                             This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
 }GPIO_InitTypeDef;
 
@@ -180,7 +180,7 @@ typedef enum
 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
   * @{
   */
-  
+
 /**
   * @brief  Check whether the specified EXTI line flag is set or not.
   * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
@@ -231,7 +231,8 @@ typedef enum
   */
 #define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
 
-#define IS_GPIO_PIN(__PIN__)        (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
+#define IS_GPIO_PIN(__PIN__)        ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
+                                     (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
 
 #define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
                                      ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
@@ -262,16 +263,16 @@ typedef enum
 /* Include GPIO HAL Extended module */
 #include "stm32l4xx_hal_gpio_ex.h"
 
-/* Exported functions --------------------------------------------------------*/ 
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
   * @{
   */
 
-/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
+/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
  *  @brief    Initialization and Configuration functions
  * @{
  */
-     
+
 /* Initialization and de-initialization functions *****************************/
 void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
 void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
@@ -280,10 +281,10 @@ void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
   * @}
   */
 
-/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions 
+/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
  * @{
  */
-   
+
 /* IO operation functions *****************************************************/
 GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
 void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
@@ -302,12 +303,12 @@ void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */  
-  
+  */
+
 #ifdef __cplusplus
 }
 #endif

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of GPIO HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -65,8 +65,245 @@
   * @{
   */
 
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
+/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#if defined(STM32L433xx) || defined(STM32L443xx)
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                          */
+#endif /* STM32L433xx || STM32L443xx */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART1 Alternate Function mapping */
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
+
+/**
+  * @brief   AF 10 selection
+  */
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
+#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */
+
+#if defined(STM32L433xx) || defined(STM32L443xx)
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
+#endif /* STM32L433xx || STM32L443xx */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+/*--------------STM32L451xx/STM32L452xx/STM32L462xx---------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_I2C4          ((uint8_t)0x02)  /* I2C4 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF3_CAN1          ((uint8_t)0x03)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping  */
+
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
+
+/**
+  * @brief   AF 10 selection
+  */
+#if defined(STM32L452xx) || defined(STM32L462xx)
+#define GPIO_AF10_USB_FS       ((uint8_t)0x0A)  /* USB_FS Alternate Function mapping */
+#endif /* STM32L452xx || STM32L462xx */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_CAN1         ((uint8_t)0x0A)  /* CAN1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 11 selection
+  */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+
 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx----*/
+/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/
 /**
   * @brief   AF 0 selection
   */
@@ -121,7 +358,7 @@
   * @brief   AF 6 selection
   */
 #define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
-#define GPIO_AF6_DFSDM         ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
 
 /**
   * @brief   AF 7 selection
@@ -148,56 +385,196 @@
   * @brief   AF 10 selection
   */
 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-#define GPIO_AF10_OTG_FS       ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-#define GPIO_AF10_QUADSPI      ((uint8_t)0xA)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */
 
 #if defined(STM32L476xx) || defined(STM32L486xx)
 /**
   * @brief   AF 11 selection
   */
-#define GPIO_AF11_LCD           ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
 #endif /* STM32L476xx || STM32L486xx */
 
 /**
   * @brief   AF 12 selection
   */
-#define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping     */
-#define GPIO_AF12_SWPMI1        ((uint8_t)0xC)  /* SWPMI1 Alternate Function mapping  */
-#define GPIO_AF12_COMP1         ((uint8_t)0xC)  /* COMP1 Alternate Function mapping   */
-#define GPIO_AF12_COMP2         ((uint8_t)0xC)  /* COMP2 Alternate Function mapping   */
-#define GPIO_AF12_SDMMC1        ((uint8_t)0xC)  /* SDMMC1 Alternate Function mapping  */
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
 
 /**
   * @brief   AF 13 selection
   */
-#define GPIO_AF13_SAI1          ((uint8_t)0x0D)   /* SAI1 Alternate Function mapping */
-#define GPIO_AF13_SAI2          ((uint8_t)0x0D)   /* SAI2 Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP2    ((uint8_t)0x0D)   /* TIM8/COMP2 Break in Alternate Function mapping  */
-#define GPIO_AF13_TIM8_COMP1    ((uint8_t)0x0D)   /* TIM8/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */
+#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */
+#define GPIO_AF13_TIM8_COMP2   ((uint8_t)0x0D)  /* TIM8/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */
 
 /**
   * @brief   AF 14 selection
   */
-#define GPIO_AF14_TIM2          ((uint8_t)0x0E)   /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15         ((uint8_t)0x0E)   /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16         ((uint8_t)0x0E)   /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_TIM17         ((uint8_t)0x0E)   /* TIM17 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2        ((uint8_t)0x0E)   /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM8_COMP1    ((uint8_t)0x0E)   /* TIM8/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM8_COMP1   ((uint8_t)0x0E)  /* TIM8/COMP1 Break in Alternate Function mapping  */
 
 /**
   * @brief   AF 15 selection
   */
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
 
 #define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
 
 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
 
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/*--------------------------------STM32L496xx/STM32L4A6xx---------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */
+#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_I2C4          ((uint8_t)0x02)  /* I2C4 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF3_CAN2          ((uint8_t)0x03)  /* CAN2 Alternate Function mapping    */
+#define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping */
+#define GPIO_AF3_QUADSPI       ((uint8_t)0x03)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF3_SPI2          ((uint8_t)0x03)  /* SPI2 Alternate Function mapping */
+#define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF4_DCMI          ((uint8_t)0x04)  /* DCMI Alternate Function mapping   */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_DCMI          ((uint8_t)0x05)  /* DCMI Alternate Function mapping   */
+#define GPIO_AF5_I2C4          ((uint8_t)0x05)  /* I2C4 Alternate Function mapping */
+#define GPIO_AF5_QUADSPI       ((uint8_t)0x05)  /* QUADSPI Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF6_I2C3          ((uint8_t)0x06)  /* I2C3 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+#define GPIO_AF8_CAN2          ((uint8_t)0x08)  /* CAN2 Alternate Function mapping    */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_OTG_FS       ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_CAN2         ((uint8_t)0x0A)  /* CAN2 Alternate Function mapping */
+#define GPIO_AF10_DCMI         ((uint8_t)0x0A)  /* DCMI Alternate Function mapping */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_LCD          ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SWPMI1       ((uint8_t)0x0C)  /* SWPMI1 Alternate Function mapping  */
+#define GPIO_AF12_COMP1        ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2        ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+#define GPIO_AF12_TIM1_COMP2   ((uint8_t)0x0C)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF12_TIM1_COMP1   ((uint8_t)0x0C)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+#define GPIO_AF12_TIM8_COMP2   ((uint8_t)0x0C)  /* TIM8/COMP2 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping */
+#define GPIO_AF13_SAI2         ((uint8_t)0x0D)  /* SAI2 Alternate Function mapping */
+#define GPIO_AF13_TIM8_COMP2   ((uint8_t)0x0D)  /* TIM8/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF13_TIM8_COMP1   ((uint8_t)0x0D)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16        ((uint8_t)0x0E)  /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17        ((uint8_t)0x0E)  /* TIM17 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2       ((uint8_t)0x0E)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM8_COMP1   ((uint8_t)0x0E)  /* TIM8/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+#endif /* STM32L496xx || STM32L4A6xx */
+
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
@@ -211,6 +588,36 @@
 /** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
 * @{
   */
+#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOE))? 4U : 7U)
+
+#endif /* STM32L431xx || STM32L433xx || STM32L443xx */
+
+#if defined(STM32L432xx) || defined(STM32L442xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U : 7U)
+
+#endif /* STM32L432xx || STM32L442xx */
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOE))? 4U : 7U)
+
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
                                       ((__GPIOx__) == (GPIOB))? 1U :\
                                       ((__GPIOx__) == (GPIOC))? 2U :\
@@ -219,6 +626,22 @@
                                       ((__GPIOx__) == (GPIOF))? 5U :\
                                       ((__GPIOx__) == (GPIOG))? 6U : 7U)
 
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOE))? 4U :\
+                                      ((__GPIOx__) == (GPIOF))? 5U :\
+                                      ((__GPIOx__) == (GPIOG))? 6U :\
+                                      ((__GPIOx__) == (GPIOH))? 7U : 8U)
+
+#endif /* STM32L496xx || STM32L4A6xx */
+
+
 /**
   * @}
   */
@@ -227,7 +650,7 @@
   * @}
   */
 
-/* Exported functions --------------------------------------------------------*/ 
+/* Exported functions --------------------------------------------------------*/
 /**
   * @}
   */

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h

@@ -0,0 +1,582 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hash.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of HASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_HASH_H
+#define __STM32L4xx_HAL_HASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HASH_Exported_Types HASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HASH Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
+                              This parameter can be a value of @ref HASH_Data_Type. */
+
+  uint32_t KeySize;     /*!< The key size is used only in HMAC operation. */
+
+  uint8_t* pKey;        /*!< The key is used only in HMAC operation. */
+
+} HASH_InitTypeDef;
+
+/**
+  * @brief HAL State structures definition
+  */
+typedef enum
+{
+  HAL_HASH_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized            */
+  HAL_HASH_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
+  HAL_HASH_STATE_BUSY              = 0x02,    /*!< Processing (hashing) is ongoing          */
+  HAL_HASH_STATE_TIMEOUT           = 0x06,    /*!< Timeout state                            */
+  HAL_HASH_STATE_ERROR             = 0x07,    /*!< Error state                              */
+  HAL_HASH_STATE_SUSPENDED         = 0x08     /*!< Suspended state                          */
+}HAL_HASH_StateTypeDef;
+
+/**
+  * @brief HAL phase structures definition
+  */
+typedef enum
+{
+  HAL_HASH_PHASE_READY             = 0x01,    /*!< HASH peripheral is ready to start                    */
+  HAL_HASH_PHASE_PROCESS           = 0x02,    /*!< HASH peripheral is in HASH processing phase          */
+  HAL_HASH_PHASE_HMAC_STEP_1       = 0x03,    /*!< HASH peripheral is in HMAC step 1 processing phase
+                                              (step 1 consists in entering the inner hash function key) */
+  HAL_HASH_PHASE_HMAC_STEP_2       = 0x04,    /*!< HASH peripheral is in HMAC step 2 processing phase
+                                              (step 2 consists in entering the message text) */
+  HAL_HASH_PHASE_HMAC_STEP_3       = 0x05     /*!< HASH peripheral is in HMAC step 3 processing phase
+                                              (step 3 consists in entering the outer hash function key) */
+}HAL_HASH_PhaseTypeDef;
+
+/**
+  * @brief HAL HASH mode suspend definitions
+  */
+typedef enum
+{
+  HAL_HASH_SUSPEND_NONE            = 0x00,    /*!< HASH peripheral suspension not requested */
+  HAL_HASH_SUSPEND                 = 0x01     /*!< HASH peripheral suspension is requested  */
+}HAL_HASH_SuspendTypeDef;
+
+
+/**
+  * @brief  HASH Handle Structure definition
+  */
+typedef struct
+{
+  HASH_InitTypeDef           Init;             /*!< HASH required parameters */
+
+  uint8_t                    *pHashInBuffPtr;  /*!< Pointer to input buffer */
+
+  uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
+
+  uint8_t                    *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
+
+  uint8_t                    *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
+
+  uint32_t                   HashBuffSize;     /*!< Size of buffer to be processed */
+
+  __IO uint32_t              HashInCount;      /*!< Counter of inputted data */
+
+  __IO uint32_t              HashITCounter;    /*!< Counter of issued interrupts */
+
+  __IO uint32_t              HashKeyCount;     /*!< Counter for Key inputted data (HMAC only) */
+
+  HAL_StatusTypeDef          Status;           /*!< HASH peripheral status   */
+
+  HAL_HASH_PhaseTypeDef      Phase;            /*!< HASH peripheral phase   */
+
+  DMA_HandleTypeDef          *hdmain;          /*!< HASH In DMA Handle parameters */
+
+  HAL_LockTypeDef            Lock;             /*!< Locking object */
+
+  __IO HAL_HASH_StateTypeDef State;            /*!< HASH peripheral state */
+
+  HAL_HASH_SuspendTypeDef    SuspendRequest;   /*!< HASH peripheral suspension request flag */
+
+  FlagStatus                 DigestCalculationDisable;  /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
+
+  __IO uint32_t              NbWordsAlreadyPushed;      /*!< Numbers of words already pushed in FIFO before inputting new block */
+
+} HASH_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants  HASH Exported Constants
+  * @{
+  */
+
+/** @defgroup HASH_Algo_Selection   HASH algorithm selection
+  * @{
+  */
+#define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x0000) /*!< HASH function is SHA1   */
+#define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1     /*!< HASH function is SHA224 */
+#define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO       /*!< HASH function is SHA256 */
+#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Algorithm_Mode   HASH algorithm mode
+  * @{
+  */
+#define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000) /*!< Algorithm is HASH */
+#define HASH_ALGOMODE_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Data_Type      HASH input data type
+  * @{
+  */
+#define HASH_DATATYPE_32B          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
+#define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
+#define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
+#define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode   HMAC key length type
+  * @{
+  */
+#define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY           /*!< HMAC Key size is > 64 bytes  */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_flags_definition  HASH flags definitions
+  * @{
+  */
+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                             */
+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing              */
+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                       */
+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data     */
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_interrupts_definition   HASH interrupts definitions
+  * @{
+  */
+#define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_alias HASH API alias
+  * @{
+  */
+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
+/**
+  * @}
+  */
+
+
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HASH_Exported_Macros HASH Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether or not the specified HASH flag is set.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.
+  *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
+  *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
+  *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_HASH_GET_FLAG(__FLAG__)  (((__FLAG__) > 8U)  ?                    \
+                                       ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+                                       ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+
+
+/** @brief  Clear the specified HASH flag.
+  * @param  __FLAG__: specifies the flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
+
+
+/** @brief  Enable the specified HASH interrupt.
+  * @param  __INTERRUPT__: specifies the HASH interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_ENABLE_IT(__INTERRUPT__)   SET_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief  Disable the specified HASH interrupt.
+  * @param  __INTERRUPT__: specifies the HASH interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Reset HASH handle state.
+  * @param  __HANDLE__: HASH handle.
+  * @retval None
+  */
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+
+/** @brief Reset HASH handle status.
+  * @param  __HANDLE__: HASH handle.
+  * @retval None
+  */
+#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
+
+/**
+  * @brief  Enable the multi-buffer DMA transfer mode.
+  * @note   This bit is set when hashing large files when multiple DMA transfers are needed.
+  * @retval None
+  */
+#define __HAL_HASH_SET_MDMAT()          SET_BIT(HASH->CR, HASH_CR_MDMAT)
+
+/**
+  * @brief  Disable the multi-buffer DMA transfer mode.
+  * @retval None
+  */
+#define __HAL_HASH_RESET_MDMAT()        CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
+
+
+
+/**
+  * @brief Start the digest computation.
+  * @retval None
+  */
+#define __HAL_HASH_START_DIGEST()       SET_BIT(HASH->STR, HASH_STR_DCAL)
+
+/**
+  * @brief Set the number of valid bits in the last word written in data register DIN.
+  * @param  __SIZE__: size in bytes of last data written in Data register.
+  * @retval None
+*/
+#define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))
+
+/**
+  * @brief Reset the HASH core.
+  * @retval None
+  */
+#define __HAL_HASH_INIT()       SET_BIT(HASH->CR, HASH_CR_INIT)
+
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros   HASH Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Return digest length in bytes.
+  * @retval Digest length
+  */
+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20 : \
+                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28 : \
+                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32 : 16 ) ) )
+
+/**
+  * @brief  Return number of words already pushed in the FIFO.
+  * @retval Number of words already pushed in the FIFO
+  */
+#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)
+
+/**
+  * @brief Ensure that HASH input data type is valid.
+  * @param __DATATYPE__: HASH input data type.
+  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+  */
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+                                        ((__DATATYPE__) == HASH_DATATYPE_1B))
+
+
+
+/**
+  * @brief Ensure that input data buffer size is valid for multi-buffer HASH
+  *        processing in polling mode.
+  * @note  This check is valid only for multi-buffer HASH processing in polling mode.
+  * @param __SIZE__: input data buffer size.
+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+  */
+#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__)  (((__SIZE__) % 4) == 0)
+
+/**
+  * @brief Ensure that input data buffer size is valid for multi-buffer HASH
+  *        processing in DMA mode.
+  * @note  This check is valid only for multi-buffer HASH processing in DMA mode.
+  * @param __SIZE__: input data buffer size.
+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+  */
+#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__)  ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))
+
+/**
+  * @brief Ensure that input data buffer size is valid for multi-buffer HMAC
+  *        processing in DMA mode.
+  * @note  This check is valid only for multi-buffer HMAC processing in DMA mode.
+  * @param __HANDLE__: HASH handle.
+  * @param __SIZE__: input data buffer size.
+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+  */
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__)  ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))
+
+/**
+  * @brief Ensure that handle phase is set to HASH processing.
+  * @param __HANDLE__: HASH handle.
+  * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
+  */
+#define IS_HASH_PROCESSING(__HANDLE__)  ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
+
+/**
+  * @brief Ensure that handle phase is set to HMAC processing.
+  * @param __HANDLE__: HASH handle.
+  * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
+  */
+#define IS_HMAC_PROCESSING(__HANDLE__)  (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
+                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
+                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+
+/**
+  * @}
+  */
+
+
+/* Include HASH HAL Extended module */
+#include "stm32l4xx_hal_hash_ex.h"
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASH_Exported_Functions HASH Exported Functions
+  * @{
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization methods  **********************************/
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+  * @{
+  */
+
+
+/* HASH processing using polling  *********************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
+  * @{
+  */
+
+/* HASH processing using IT  **************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
+  * @{
+  */
+
+/* HASH processing using DMA  *************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
+  * @{
+  */
+
+/* HASH-MAC processing using polling  *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+  * @{
+  */
+
+/* HASH-HMAC processing using DMA  ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
+  * @{
+  */
+
+
+/* Peripheral State methods  **************************************************/
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+
+/** @addtogroup HASH_Private_Functions HASH Private Functions
+  * @{
+  */
+
+/* Private functions */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (STM32L4A6xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_HASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h

@@ -0,0 +1,182 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hash_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of HASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_HASH_EX_H
+#define __STM32L4xx_HAL_HASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
+  * @{
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
+  * @{
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (STM32L4A6xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_HASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h

@@ -0,0 +1,263 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_hcd.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of HCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_HCD_H
+#define __STM32L4xx_HAL_HCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_usb.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Types HCD Exported Types
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+  * @{
+  */
+typedef enum
+{
+  HAL_HCD_STATE_RESET    = 0x00,
+  HAL_HCD_STATE_READY    = 0x01,
+  HAL_HCD_STATE_ERROR    = 0x02,
+  HAL_HCD_STATE_BUSY     = 0x03,
+  HAL_HCD_STATE_TIMEOUT  = 0x04
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
+typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
+  * @{
+  */
+typedef struct
+{
+  HCD_TypeDef               *Instance;  /*!< Register base address    */
+  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
+  HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
+  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
+  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
+  void                      *pData;     /*!< Pointer Stack Handler    */
+
+} HCD_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+  * @{
+  */
+
+/** @defgroup HCD_Speed HCD Speed
+  * @{
+  */
+#define HCD_SPEED_HIGH               0
+#define HCD_SPEED_LOW                2
+#define HCD_SPEED_FULL               3
+/**
+  * @}
+  */
+
+/** @defgroup HCD_PHY_Module HCD PHY Module
+  * @{
+  */
+#define HCD_PHY_EMBEDDED             1
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_HCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps);
+
+HAL_StatusTypeDef       HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
+                                  uint8_t ch_num);
+
+void            HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void            HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                                 uint8_t pipe,
+                                                 uint8_t direction ,
+                                                 uint8_t ep_type,
+                                                 uint8_t token,
+                                                 uint8_t* pbuff,
+                                                 uint16_t length,
+                                                 uint8_t do_ping);
+
+ /* Non-Blocking mode: Interrupt */
+void             HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+                                                            uint8_t chnum,
+                                                            HCD_URBStateTypeDef urb_state);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+ * @{
+ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_HCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -44,7 +44,7 @@
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"  
+#include "stm32l4xx_hal_def.h"
 
 /** @addtogroup STM32L4xx_HAL_Driver
   * @{
@@ -52,7 +52,7 @@
 
 /** @addtogroup I2C
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup I2C_Exported_Types I2C Exported Types
@@ -60,61 +60,84 @@
   */
 
 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
-  * @brief  I2C Configuration Structure definition  
+  * @brief  I2C Configuration Structure definition
   * @{
   */
 typedef struct
 {
   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
-                                  This parameter calculated by referring to I2C initialization 
+                                  This parameter calculated by referring to I2C initialization
                                          section in Reference manual */
 
   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
                                   This parameter can be a 7-bit or 10-bit address. */
 
   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_addressing_mode */
+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
 
   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
 
   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
                                   This parameter can be a 7-bit address. */
 
   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
-                                  This parameter can be a value of @ref I2C_own_address2_masks */
+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
 
   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
 
   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref I2C_nostretch_mode */
+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
 
 }I2C_InitTypeDef;
 
-/** 
+/**
   * @}
   */
 
 /** @defgroup HAL_state_structure_definition HAL state structure definition
   * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     IP initilisation status\n
+  *             0  : Reset (IP not initialized)\n
+  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (IP in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (IP busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
   * @{
-  */ 
-
+  */
 typedef enum
 {
-  HAL_I2C_STATE_RESET             = 0x00,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21,   /*!< Data Transmission process is ongoing      */ 
-  HAL_I2C_STATE_BUSY_RX           = 0x22,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_LISTEN            = 0x28,   /*!< Address Listen Mode is ongoing            */
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                        */
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2A,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                        */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0    /*!< Error                                     */ 
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
 
 }HAL_I2C_StateTypeDef;
 
@@ -124,82 +147,87 @@ typedef enum
 
 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
   * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
   * @{
   */
 typedef enum
 {
-  HAL_I2C_MODE_NONE               = 0x00,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40    /*!< I2C communication is in Memory Mode       */
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
 
 }HAL_I2C_ModeTypeDef;
 
-/** 
+/**
   * @}
   */
 
 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
-  * @brief  I2C Error Code definition  
-  * @{
-  */
-#define HAL_I2C_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
-#define HAL_I2C_ERROR_BERR      ((uint32_t)0x00000001)    /*!< BERR error            */
-#define HAL_I2C_ERROR_ARLO      ((uint32_t)0x00000002)    /*!< ARLO error            */
-#define HAL_I2C_ERROR_AF        ((uint32_t)0x00000004)    /*!< ACKF error            */
-#define HAL_I2C_ERROR_OVR       ((uint32_t)0x00000008)    /*!< OVR error             */
-#define HAL_I2C_ERROR_DMA       ((uint32_t)0x00000010)    /*!< DMA transfer error    */
-#define HAL_I2C_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
-#define HAL_I2C_ERROR_SIZE      ((uint32_t)0x00000040)    /*!< Size Management error */
-/** 
-  * @}
-  */
-
-/** @defgroup I2C_XferOptions_definition  I2C XferOptions definition
+  * @brief  I2C Error Code definition
   * @{
   */
-#define I2C_NO_OPTION_FRAME             ((uint32_t)0xFFFF0000)
-#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
-#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
 /**
   * @}
   */
 
 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
-  * @brief  I2C handle Structure definition  
+  * @brief  I2C handle Structure definition
   * @{
   */
-typedef struct
+typedef struct __I2C_HandleTypeDef
 {
-  I2C_TypeDef                *Instance;        /*!< I2C registers base address       */
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
 
-  I2C_InitTypeDef            Init;             /*!< I2C communication parameters     */
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
 
-  uint8_t                    *pBuffPtr;        /*!< Pointer to I2C transfer buffer   */
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
 
-  uint16_t                   XferSize;         /*!< I2C transfer size                */
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
 
-  __IO uint16_t              XferCount;        /*!< I2C transfer counter             */
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
 
-  __IO uint32_t              XferOptions;      /*!< I2C transfer options             */
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
 
-  __IO uint32_t              PreviousState;    /*!< I2C communication Previous state */
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
 
-  DMA_HandleTypeDef          *hdmatx;          /*!< I2C Tx DMA handle parameters     */
+  HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
 
-  DMA_HandleTypeDef          *hdmarx;          /*!< I2C Rx DMA handle parameters     */
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
 
-  HAL_LockTypeDef            Lock;             /*!< I2C locking object               */
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
 
-  __IO HAL_I2C_StateTypeDef  State;            /*!< I2C communication state          */
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
 
-  __IO HAL_I2C_ModeTypeDef   Mode;             /*!< I2C communication mode           */
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
 
-  __IO uint32_t              ErrorCode;        /*!< I2C Error code                   */
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
 
-  __IO uint32_t              AddrEventCount;   /*!< I2C Address Event counter        */
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
 }I2C_HandleTypeDef;
 /**
   * @}
@@ -207,96 +235,108 @@ typedef struct
 
 /**
   * @}
-  */  
+  */
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup I2C_Exported_Constants I2C Exported Constants
   * @{
   */
 
-/** @defgroup I2C_addressing_mode I2C addressing mode
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
   * @{
   */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001)
-#define I2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002)
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
 /**
   * @}
   */
 
-/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
   * @{
   */
-#define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000)
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
 /**
   * @}
   */
 
-/** @defgroup I2C_own_address2_masks I2C own address2 masks
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
   * @{
   */
-#define I2C_OA2_NOMASK                  ((uint8_t)0x00)
-#define I2C_OA2_MASK01                  ((uint8_t)0x01)
-#define I2C_OA2_MASK02                  ((uint8_t)0x02)
-#define I2C_OA2_MASK03                  ((uint8_t)0x03)
-#define I2C_OA2_MASK04                  ((uint8_t)0x04)
-#define I2C_OA2_MASK05                  ((uint8_t)0x05)
-#define I2C_OA2_MASK06                  ((uint8_t)0x06)
-#define I2C_OA2_MASK07                  ((uint8_t)0x07)
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
 /**
   * @}
   */
 
-/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
   * @{
   */
-#define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
 /**
   * @}
   */
 
-/** @defgroup I2C_nostretch_mode I2C nostretch mode
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
   * @{
   */
-#define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
 /**
   * @}
   */
 
-/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
   * @{
   */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000002)
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
 /**
   * @}
   */
-  
-/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
   * @{
   */
-#define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000000)
-#define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000001)
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
 /**
   * @}
   */
 
-/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
   * @{
   */
 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
-#define  I2C_SOFTEND_MODE               ((uint32_t)0x00000000)
+#define  I2C_SOFTEND_MODE               (0x00000000U)
 /**
   * @}
   */
 
-/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
   * @{
   */
-#define  I2C_NO_STARTSTOP               ((uint32_t)0x00000000)
+#define  I2C_NO_STARTSTOP               (0x00000000U)
 #define  I2C_GENERATE_STOP              I2C_CR2_STOP
 #define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
 #define  I2C_GENERATE_START_WRITE       I2C_CR2_START
@@ -323,7 +363,7 @@ typedef struct
 
 /** @defgroup I2C_Flag_definition I2C Flag definition
   * @{
-  */ 
+  */
 #define I2C_FLAG_TXE                    I2C_ISR_TXE
 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
@@ -349,7 +389,7 @@ typedef struct
   */
 
 /* Exported macros -----------------------------------------------------------*/
-  
+
 /** @defgroup I2C_Exported_Macros I2C Exported Macros
   * @{
   */
@@ -387,11 +427,11 @@ typedef struct
   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
   *            @arg @ref I2C_IT_RXI   RX interrupt enable
   *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *   
+  *
   * @retval None
   */
 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
- 
+
 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
   * @param  __HANDLE__ specifies the I2C Handle.
   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
@@ -404,7 +444,7 @@ typedef struct
   *            @arg @ref I2C_IT_RXI   RX interrupt enable
   *            @arg @ref I2C_IT_TXI   TX interrupt enable
   *
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
@@ -429,9 +469,9 @@ typedef struct
   *            @arg @ref I2C_FLAG_BUSY    Bus busy
   *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
   *
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  * @retval The new state of __FLAG__ (SET or RESET).
   */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
 
 /** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
   * @param  __HANDLE__ specifies the I2C Handle.
@@ -443,16 +483,16 @@ typedef struct
   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
   *            @arg @ref I2C_FLAG_BERR    Bus error
   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun            
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag 
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
   *
   * @retval None
   */
 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
                                                                                  : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
- 
+
 /** @brief  Enable the specified I2C peripheral.
   * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
@@ -465,6 +505,11 @@ typedef struct
   */
 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
 /**
   * @}
   */
@@ -544,9 +589,10 @@ void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
 /**
   * @}
-  */ 
+  */
 
 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
   * @{
@@ -558,11 +604,11 @@ uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup I2C_Private_Constants I2C Private Constants
@@ -571,7 +617,7 @@ uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 
 /**
   * @}
-  */ 
+  */
 
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup I2C_Private_Macro I2C Private Macros
@@ -612,31 +658,30 @@ uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
                                          ((REQUEST) == I2C_NO_STARTSTOP))
 
 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
                                                    ((REQUEST) == I2C_NEXT_FRAME)           || \
                                                    ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
                                                    ((REQUEST) == I2C_LAST_FRAME))
 
 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
 
-#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)
-#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
+#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_ISR_REG(__HANDLE__)               ((__HANDLE__)->Instance->ISR)
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         (((__ISR__) & (__FLAG__)) == (__FLAG__))
 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
 
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= (uint32_t)0x000003FF)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FF)
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
 
-#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
 
 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
 /**
   * @}
-  */ 
+  */
 
 /* Private Functions ---------------------------------------------------------*/
 /** @defgroup I2C_Private_Functions I2C Private Functions
@@ -645,15 +690,15 @@ uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 /* Private functions are defined in stm32l4xx_hal_i2c.c file */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_i2c_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of I2C HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -52,7 +52,7 @@
 
 /** @addtogroup I2CEx
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
@@ -64,29 +64,44 @@
 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
   * @{
   */
-#define I2C_ANALOGFILTER_ENABLE         ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
 #define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
 /**
   * @}
   */
 
-/** @defgroup I2CEx_FastModePlus I2CEx FastModePlus
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
   * @{
   */
-#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
-#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
-#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
-#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
-#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
-#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
-#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#else
+#define I2C_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */
+#define I2C_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */
+#endif
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(SYSCFG_CFGR1_I2C2_FMP)
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */
+#endif
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#if defined(SYSCFG_CFGR1_I2C4_FMP)
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_CFGR1_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */
+#endif
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
+  */
 
 /* Exported macro ------------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
@@ -109,7 +124,7 @@ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
 
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
   * @{
   */
 
@@ -118,27 +133,29 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
   * @{
   */
 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                           ((FILTER) == I2C_ANALOGFILTER_DISABLE))
 
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
-
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6)    || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7)   || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8)   || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9)   || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
-                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
+                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
 /**
   * @}
-  */ 
+  */
 
 /* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
   * @{
   */
 /* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h

@@ -0,0 +1,849 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_irda.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of IRDA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_IRDA_H
+#define __STM32L4xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IRDA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+  * @{
+  */
+
+/**
+  * @brief IRDA Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref IRDA_Word_Length */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref IRDA_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref IRDA_Transfer_Mode */
+
+  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
+                                           to achieve low-power frequency.
+                                           @note Prescaler value 0 is forbidden */
+
+  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
+                                           This parameter can be a value of @ref IRDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+  * @brief HAL IRDA State structures definition
+  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains IRDA state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_IRDA_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_IRDA_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_IRDA_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_IRDA_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_ERROR             = 0xE0U    /*!< Error
+                                                   Value is allowed for gState only */
+}HAL_IRDA_StateTypeDef;
+
+/**
+  * @brief  HAL IRDA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_IRDA_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_IRDA_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_IRDA_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_IRDA_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_IRDA_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_IRDA_ERROR_DMA       = 0x10,     /*!< DMA transfer error  */
+  HAL_IRDA_ERROR_BUSY      = 0x20     /*!< Busy Error          */
+}HAL_IRDA_ErrorTypeDef;
+
+/**
+  * @brief IRDA clock sources definition
+  */
+typedef enum
+{
+  IRDA_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
+  IRDA_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
+  IRDA_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
+  IRDA_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
+  IRDA_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
+  IRDA_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
+}IRDA_ClockSourceTypeDef;
+
+/**
+  * @brief  IRDA handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef            *Instance;        /*!< IRDA registers base address        */
+
+  IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
+
+  uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;      /* !<IRDA Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
+
+  uint16_t                 Mask;             /*!< IRDA RX RDR register mask          */
+
+  DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef          Lock;             /*!< Locking object                     */
+
+  __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
+                                                  and also related to Tx operations.
+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  uint32_t                 ErrorCode;        /*!< IRDA Error code                    */
+
+}IRDA_HandleTypeDef;
+
+/**
+  * @brief  IRDA Configuration enumeration values definition
+  */
+typedef enum
+{
+  IRDA_BAUDRATE        = 0x00,     /*!< IRDA Baud rate          */
+  IRDA_PARITY          = 0x01,     /*!< IRDA frame parity       */
+  IRDA_WORDLENGTH      = 0x02,     /*!< IRDA frame length       */
+  IRDA_MODE            = 0x03,     /*!< IRDA communication mode */
+  IRDA_PRESCALER       = 0x04,     /*!< IRDA prescaling         */
+  IRDA_POWERMODE       = 0x05      /*!< IRDA power mode         */
+}IRDA_ControlTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
+  * @{
+  */
+
+/** @defgroup IRDA_Word_Length IRDA Word Length
+  * @{
+  */
+#define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long frame */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Parity IRDA Parity
+  * @{
+  */
+#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)                      /*!< No parity   */
+#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
+#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+  * @{
+  */
+#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
+#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
+#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+  * @{
+  */
+#define IRDA_POWERMODE_NORMAL               ((uint32_t)0x00000000)       /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_LOWPOWER             ((uint32_t)USART_CR3_IRLP)   /*!< IRDA low power mode    */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_State IRDA State
+  * @{
+  */
+#define IRDA_STATE_DISABLE                  ((uint32_t)0x00000000)     /*!< IRDA disabled  */
+#define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)   /*!< IRDA enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Mode  IRDA Mode
+  * @{
+  */
+#define IRDA_MODE_DISABLE                   ((uint32_t)0x00000000)      /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE                    ((uint32_t)USART_CR3_IREN)  /*!< Associated UART enabled in IRDA mode  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_One_Bit  IRDA One Bit Sampling
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)       /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
+  * @{
+  */
+#define IRDA_DMA_TX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)   /*!< IRDA DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_DMA_Rx  IRDA DMA Rx
+  * @{
+  */
+#define IRDA_DMA_RX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)   /*!< IRDA DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+  * @{
+  */
+#define IRDA_AUTOBAUD_REQUEST            ((uint16_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
+#define IRDA_RXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
+#define IRDA_TXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Flags IRDA Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define IRDA_FLAG_REACK                     ((uint32_t)0x00400000)    /*!< IRDA Receive enable acknowledge flag  */
+#define IRDA_FLAG_TEACK                     ((uint32_t)0x00200000)    /*!< IRDA Transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY                      ((uint32_t)0x00010000)    /*!< IRDA Busy flag                        */
+#define IRDA_FLAG_ABRF                      ((uint32_t)0x00008000)    /*!< IRDA Auto baud rate flag              */
+#define IRDA_FLAG_ABRE                      ((uint32_t)0x00004000)    /*!< IRDA Auto baud rate error             */
+#define IRDA_FLAG_TXE                       ((uint32_t)0x00000080)    /*!< IRDA Transmit data register empty     */
+#define IRDA_FLAG_TC                        ((uint32_t)0x00000040)    /*!< IRDA Transmission complete            */
+#define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020)    /*!< IRDA Read data register not empty     */
+#define IRDA_FLAG_ORE                       ((uint32_t)0x00000008)    /*!< IRDA Overrun error                    */
+#define IRDA_FLAG_NE                        ((uint32_t)0x00000004)    /*!< IRDA Noise error                      */
+#define IRDA_FLAG_FE                        ((uint32_t)0x00000002)    /*!< IRDA Framing error                    */
+#define IRDA_FLAG_PE                        ((uint32_t)0x00000001)    /*!< IRDA Parity error                     */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define IRDA_IT_PE                          ((uint16_t)0x0028)     /*!< IRDA Parity error interruption                 */
+#define IRDA_IT_TXE                         ((uint16_t)0x0727)     /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC                          ((uint16_t)0x0626)     /*!< IRDA Transmission complete interruption        */
+#define IRDA_IT_RXNE                        ((uint16_t)0x0525)     /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE                        ((uint16_t)0x0424)     /*!< IRDA Idle interruption                         */
+#define IRDA_IT_ERR                         ((uint16_t)0x0060)       /*!< IRDA Error interruption        */
+#define IRDA_IT_ORE                         ((uint16_t)0x0300)      /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE                          ((uint16_t)0x0200)      /*!< IRDA Noise error interruption   */
+#define IRDA_IT_FE                          ((uint16_t)0x0100)      /*!< IRDA Frame error interruption   */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_IT_CLEAR_Flags   IRDA Interruption Clear Flags
+  * @{
+  */
+#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
+#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
+#define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
+#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
+#define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
+#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Interruption_Mask    IRDA interruptions flags mask
+  * @{
+  */
+#define IRDA_IT_MASK  ((uint16_t)0x001F)                             /*!< IRDA Interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+ * @}
+ */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset IRDA handle state.
+  * @param  __HANDLE__: IRDA handle.
+  * @retval None
+  */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
+                                                     } while(0)
+
+/** @brief  Flush the IRDA DR register.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
+    do{                                                                    \
+         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+      } while(0)
+
+/** @brief  Clear the specified IRDA pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref IRDA_CLEAR_PEF
+  *            @arg @ref IRDA_CLEAR_FEF
+  *            @arg @ref IRDA_CLEAR_NEF
+  *            @arg @ref IRDA_CLEAR_OREF
+  *            @arg @ref IRDA_CLEAR_TCF
+  *            @arg @ref IRDA_CLEAR_IDLEF
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the IRDA PE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief  Clear the IRDA FE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief  Clear the IRDA NE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief  Clear the IRDA ORE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief  Clear the IRDA IDLE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified IRDA flag is set or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref IRDA_FLAG_BUSY  Busy flag
+  *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
+  *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
+  *            @arg @ref IRDA_FLAG_NE    Noise Error flag
+  *            @arg @ref IRDA_FLAG_FE    Framing Error flag
+  *            @arg @ref IRDA_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Enable the specified IRDA interrupt.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief  Disable the specified IRDA interrupt.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+
+/** @brief  Check whether the specified IRDA interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT__: specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
+  *            @arg @ref IRDA_IT_NE Noise Error interrupt
+  *            @arg @ref IRDA_IT_FE Framing Error interrupt
+  *            @arg @ref IRDA_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
+
+/** @brief  Check whether the specified IRDA interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT__: specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
+  *            @arg @ref IRDA_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
+                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
+
+
+/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
+  *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+
+/** @brief  Set a specific IRDA request flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __REQ__: specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the IRDA one bit sample method.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the IRDA one bit sample method.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable UART/USART associated to IRDA Handle.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable UART/USART associated to IRDA Handle.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros   IRDA Private Macros
+  * @{
+  */
+
+/** @brief  Compute the mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+  if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x01FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x003F ;                                 \
+     }                                                                \
+  }                                                                   \
+} while(0)
+
+/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
+  * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+  * @retval True or False
+  */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
+
+/** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
+  * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.
+  * @retval True or False
+  */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
+
+/**
+  * @brief Ensure that IRDA frame length is valid.
+  * @param __LENGTH__: IRDA frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that IRDA frame parity is valid.
+  * @param __PARITY__: IRDA frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
+                                    ((__PARITY__) == IRDA_PARITY_ODD))
+
+/**
+  * @brief Ensure that IRDA communication mode is valid.
+  * @param __MODE__: IRDA communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+  * @brief Ensure that IRDA power mode is valid.
+  * @param __MODE__: IRDA power mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/**
+  * @brief Ensure that IRDA state is valid.
+  * @param __STATE__: IRDA state mode.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+                                  ((__STATE__) == IRDA_STATE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA associated UART/USART mode is valid.
+  * @param __MODE__: IRDA associated UART/USART mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
+                                 ((__MODE__) == IRDA_MODE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA sampling rate is valid.
+  * @param __ONEBIT__: IRDA sampling rate.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA DMA TX mode is valid.
+  * @param __DMATX__: IRDA DMA TX mode.
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that IRDA DMA RX mode is valid.
+  * @param __DMARX__: IRDA DMA RX mode.
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that IRDA request is valid.
+  * @param __PARAM__: IRDA request.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/* Include IRDA HAL Extended module */
+#include "stm32l4xx_hal_irda_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+  * @{
+  */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+
+/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h

@@ -0,0 +1,405 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_irda_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of IRDA HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_IRDA_EX_H
+#define __STM32L4xx_HAL_IRDA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IRDAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the IRDA clock source.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval IRDA clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
+       {                                                      \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART5_SOURCE())                   \
+       {                                                      \
+        case RCC_UART5CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L432xx) || defined (STM32L442xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
+       {                                                      \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#endif
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_IRDA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h

@@ -0,0 +1,257 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of IWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_IWDG_H
+#define __STM32L4xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IWDG IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+  * @{
+  */
+
+/**
+  * @brief  IWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
+                            This parameter can be a value of @ref IWDG_Prescaler */
+
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+  * @brief  IWDG Handle Structure definition
+  */
+typedef struct
+{
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
+  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
+
+}IWDG_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+  * @{
+  */
+#define IWDG_PRESCALER_4                0x00000000u                   /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)   /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)   /*!< IWDG prescaler set to 256 */
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Window_option IWDG Window option
+  * @{
+  */
+#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the IWDG peripheral.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+  * @brief  Reload IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+  * @{
+  */
+/* Initialization/Start functions  ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+  * @{
+  */
+
+/**
+  * @brief  IWDG Key Register BitMask
+  */
+#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+  * @brief  Check IWDG prescaler value.
+  * @param  __PRESCALER__  IWDG prescaler value
+  * @retval None
+  */
+#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+  * @brief  Check IWDG reload value.
+  * @param  __RELOAD__  IWDG reload value
+  * @retval None
+  */
+#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+  * @brief  Check IWDG window value.
+  * @param  __WINDOW__  IWDG window value
+  * @retval None
+  */
+#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lcd.h

@@ -0,0 +1,789 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_lcd.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of LCD Controller HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_LCD_H
+#define __STM32L4xx_HAL_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup LCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LCD_Exported_Types LCD Exported Types
+  * @{
+  */
+
+/**
+  * @brief LCD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t Prescaler;       /*!< Configures the LCD Prescaler.
+                                 This parameter can be one value of @ref LCD_Prescaler */
+  uint32_t Divider;         /*!< Configures the LCD Divider.
+                                 This parameter can be one value of @ref LCD_Divider */
+  uint32_t Duty;            /*!< Configures the LCD Duty.
+                                 This parameter can be one value of @ref LCD_Duty */
+  uint32_t Bias;            /*!< Configures the LCD Bias.
+                                 This parameter can be one value of @ref LCD_Bias */
+  uint32_t VoltageSource;   /*!< Selects the LCD Voltage source.
+                                 This parameter can be one value of @ref LCD_Voltage_Source */
+  uint32_t Contrast;        /*!< Configures the LCD Contrast.
+                                 This parameter can be one value of @ref LCD_Contrast */
+  uint32_t DeadTime;        /*!< Configures the LCD Dead Time.
+                                 This parameter can be one value of @ref LCD_DeadTime */
+  uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
+                                 This parameter can be one value of @ref LCD_PulseOnDuration */
+  uint32_t HighDrive;       /*!< Enable or disable the low resistance divider.
+                                 This parameter can be one value of @ref LCD_HighDrive */
+  uint32_t BlinkMode;       /*!< Configures the LCD Blink Mode.
+                                 This parameter can be one value of @ref LCD_BlinkMode */
+  uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
+                                 This parameter can be one value of @ref LCD_BlinkFrequency */
+  uint32_t MuxSegment;      /*!< Enable or disable mux segment.
+                                 This parameter can be one value of @ref LCD_MuxSegment */
+} LCD_InitTypeDef;
+
+/**
+  * @brief HAL LCD State structures definition
+  */
+typedef enum
+{
+  HAL_LCD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
+  HAL_LCD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
+  HAL_LCD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
+  HAL_LCD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
+  HAL_LCD_STATE_ERROR             = 0x04     /*!< Error */
+} HAL_LCD_StateTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct
+{
+  LCD_TypeDef                   *Instance;  /* LCD registers base address */
+
+  LCD_InitTypeDef               Init;       /* LCD communication parameters */
+
+  HAL_LockTypeDef               Lock;       /* Locking object */
+
+  __IO HAL_LCD_StateTypeDef     State;      /* LCD communication state */
+
+  __IO uint32_t                 ErrorCode;  /* LCD Error code */
+
+}LCD_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LCD_Exported_Constants LCD Exported Constants
+  * @{
+  */
+
+/** @defgroup  LCD_ErrorCode LCD Error Code
+  * @{
+  */
+#define HAL_LCD_ERROR_NONE       ((uint32_t)0x00)    /*!< No error */
+#define HAL_LCD_ERROR_FCRSF      ((uint32_t)0x01)    /*!< Synchro flag timeout error */
+#define HAL_LCD_ERROR_UDR        ((uint32_t)0x02)    /*!< Update display request flag timeout error */
+#define HAL_LCD_ERROR_UDD        ((uint32_t)0x04)    /*!< Update display done flag timeout error */
+#define HAL_LCD_ERROR_ENS        ((uint32_t)0x08)    /*!< LCD enabled status flag timeout error */
+#define HAL_LCD_ERROR_RDY        ((uint32_t)0x10)    /*!< LCD Booster ready timeout error */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Prescaler LCD Prescaler
+  * @{
+  */
+#define LCD_PRESCALER_1        ((uint32_t)0x00000000)  /*!< CLKPS = LCDCLK        */
+#define LCD_PRESCALER_2        ((uint32_t)0x00400000)  /*!< CLKPS = LCDCLK/2      */
+#define LCD_PRESCALER_4        ((uint32_t)0x00800000)  /*!< CLKPS = LCDCLK/4      */
+#define LCD_PRESCALER_8        ((uint32_t)0x00C00000)  /*!< CLKPS = LCDCLK/8      */
+#define LCD_PRESCALER_16       ((uint32_t)0x01000000)  /*!< CLKPS = LCDCLK/16     */
+#define LCD_PRESCALER_32       ((uint32_t)0x01400000)  /*!< CLKPS = LCDCLK/32     */
+#define LCD_PRESCALER_64       ((uint32_t)0x01800000)  /*!< CLKPS = LCDCLK/64     */
+#define LCD_PRESCALER_128      ((uint32_t)0x01C00000)  /*!< CLKPS = LCDCLK/128    */
+#define LCD_PRESCALER_256      ((uint32_t)0x02000000)  /*!< CLKPS = LCDCLK/256    */
+#define LCD_PRESCALER_512      ((uint32_t)0x02400000)  /*!< CLKPS = LCDCLK/512    */
+#define LCD_PRESCALER_1024     ((uint32_t)0x02800000)  /*!< CLKPS = LCDCLK/1024   */
+#define LCD_PRESCALER_2048     ((uint32_t)0x02C00000)  /*!< CLKPS = LCDCLK/2048   */
+#define LCD_PRESCALER_4096     ((uint32_t)0x03000000)  /*!< CLKPS = LCDCLK/4096   */
+#define LCD_PRESCALER_8192     ((uint32_t)0x03400000)  /*!< CLKPS = LCDCLK/8192   */
+#define LCD_PRESCALER_16384    ((uint32_t)0x03800000)  /*!< CLKPS = LCDCLK/16384  */
+#define LCD_PRESCALER_32768    ((uint32_t)0x03C00000)  /*!< CLKPS = LCDCLK/32768  */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Divider LCD Divider
+  * @{
+  */
+#define LCD_DIVIDER_16    ((uint32_t)0x00000000)  /*!< LCD frequency = CLKPS/16 */
+#define LCD_DIVIDER_17    ((uint32_t)0x00040000)  /*!< LCD frequency = CLKPS/17 */
+#define LCD_DIVIDER_18    ((uint32_t)0x00080000)  /*!< LCD frequency = CLKPS/18 */
+#define LCD_DIVIDER_19    ((uint32_t)0x000C0000)  /*!< LCD frequency = CLKPS/19 */
+#define LCD_DIVIDER_20    ((uint32_t)0x00100000)  /*!< LCD frequency = CLKPS/20 */
+#define LCD_DIVIDER_21    ((uint32_t)0x00140000)  /*!< LCD frequency = CLKPS/21 */
+#define LCD_DIVIDER_22    ((uint32_t)0x00180000)  /*!< LCD frequency = CLKPS/22 */
+#define LCD_DIVIDER_23    ((uint32_t)0x001C0000)  /*!< LCD frequency = CLKPS/23 */
+#define LCD_DIVIDER_24    ((uint32_t)0x00200000)  /*!< LCD frequency = CLKPS/24 */
+#define LCD_DIVIDER_25    ((uint32_t)0x00240000)  /*!< LCD frequency = CLKPS/25 */
+#define LCD_DIVIDER_26    ((uint32_t)0x00280000)  /*!< LCD frequency = CLKPS/26 */
+#define LCD_DIVIDER_27    ((uint32_t)0x002C0000)  /*!< LCD frequency = CLKPS/27 */
+#define LCD_DIVIDER_28    ((uint32_t)0x00300000)  /*!< LCD frequency = CLKPS/28 */
+#define LCD_DIVIDER_29    ((uint32_t)0x00340000)  /*!< LCD frequency = CLKPS/29 */
+#define LCD_DIVIDER_30    ((uint32_t)0x00380000)  /*!< LCD frequency = CLKPS/30 */
+#define LCD_DIVIDER_31    ((uint32_t)0x003C0000)  /*!< LCD frequency = CLKPS/31 */
+/**
+  * @}
+  */
+
+
+/** @defgroup LCD_Duty LCD Duty
+  * @{
+  */
+#define LCD_DUTY_STATIC                 ((uint32_t)0x00000000)            /*!< Static duty */
+#define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
+#define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
+#define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
+#define LCD_DUTY_1_8                    (LCD_CR_DUTY_2)                   /*!< 1/8 duty    */
+/**
+  * @}
+  */
+
+
+/** @defgroup LCD_Bias LCD Bias
+  * @{
+  */
+#define LCD_BIAS_1_4                    ((uint32_t)0x00000000)  /*!< 1/4 Bias */
+#define LCD_BIAS_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
+#define LCD_BIAS_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Voltage_Source LCD Voltage Source
+  * @{
+  */
+#define LCD_VOLTAGESOURCE_INTERNAL      ((uint32_t)0x00000000)  /*!< Internal voltage source for the LCD */
+#define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL             /*!< External voltage source for the LCD */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Interrupts LCD Interrupts
+  * @{
+  */
+#define LCD_IT_SOF                      LCD_FCR_SOFIE
+#define LCD_IT_UDD                      LCD_FCR_UDDIE
+/**
+  * @}
+  */
+
+/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
+  * @{
+  */
+#define LCD_PULSEONDURATION_0           ((uint32_t)0x00000000)          /*!< Pulse ON duration = 0 pulse   */
+#define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
+#define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
+#define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
+#define LCD_PULSEONDURATION_4           (LCD_FCR_PON_2)                 /*!< Pulse ON duration = 4/CK_PS  */
+#define LCD_PULSEONDURATION_5           (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS  */
+#define LCD_PULSEONDURATION_6           (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS  */
+#define LCD_PULSEONDURATION_7           (LCD_FCR_PON)                   /*!< Pulse ON duration = 7/CK_PS  */
+/**
+  * @}
+  */
+
+
+/** @defgroup LCD_DeadTime LCD Dead Time
+  * @{
+  */
+#define LCD_DEADTIME_0                  ((uint32_t)0x00000000)            /*!< No dead Time  */
+#define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
+#define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
+#define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
+#define LCD_DEADTIME_4                  (LCD_FCR_DEAD_2)                  /*!< Four Phase between different couple of Frame  */
+#define LCD_DEADTIME_5                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame  */
+#define LCD_DEADTIME_6                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame   */
+#define LCD_DEADTIME_7                  (LCD_FCR_DEAD)                    /*!< Seven Phase between different couple of Frame */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_BlinkMode LCD Blink Mode
+  * @{
+  */
+#define LCD_BLINKMODE_OFF               ((uint32_t)0x00000000)  /*!< Blink disabled            */
+#define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
+#define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to
+                                                                    8 pixels according to the programmed duty)  */
+#define LCD_BLINKMODE_ALLSEG_ALLCOM     (LCD_FCR_BLINK)         /*!< Blink enabled on all SEG and all COM (all pixels)  */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_BlinkFrequency LCD Blink Frequency
+  * @{
+  */
+#define LCD_BLINKFREQUENCY_DIV8         ((uint32_t)0x00000000)                /*!< The Blink frequency = fLCD/8    */
+#define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
+#define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
+#define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
+#define LCD_BLINKFREQUENCY_DIV128       (LCD_FCR_BLINKF_2)                    /*!< The Blink frequency = fLCD/128  */
+#define LCD_BLINKFREQUENCY_DIV256       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)  /*!< The Blink frequency = fLCD/256  */
+#define LCD_BLINKFREQUENCY_DIV512       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)  /*!< The Blink frequency = fLCD/512  */
+#define LCD_BLINKFREQUENCY_DIV1024      (LCD_FCR_BLINKF)                      /*!< The Blink frequency = fLCD/1024 */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Contrast LCD Contrast
+  * @{
+  */
+#define LCD_CONTRASTLEVEL_0               ((uint32_t)0x00000000)        /*!< Maximum Voltage = 2.60V    */
+#define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
+#define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
+#define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
+#define LCD_CONTRASTLEVEL_4               (LCD_FCR_CC_2)                /*!< Maximum Voltage = 3.12V    */
+#define LCD_CONTRASTLEVEL_5               (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.26V    */
+#define LCD_CONTRASTLEVEL_6               (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.40V    */
+#define LCD_CONTRASTLEVEL_7               (LCD_FCR_CC)                  /*!< Maximum Voltage = 3.55V    */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_RAMRegister LCD RAMRegister
+  * @{
+  */
+#define LCD_RAM_REGISTER0               ((uint32_t)0x00000000) /*!< LCD RAM Register 0  */
+#define LCD_RAM_REGISTER1               ((uint32_t)0x00000001) /*!< LCD RAM Register 1  */
+#define LCD_RAM_REGISTER2               ((uint32_t)0x00000002) /*!< LCD RAM Register 2  */
+#define LCD_RAM_REGISTER3               ((uint32_t)0x00000003) /*!< LCD RAM Register 3  */
+#define LCD_RAM_REGISTER4               ((uint32_t)0x00000004) /*!< LCD RAM Register 4  */
+#define LCD_RAM_REGISTER5               ((uint32_t)0x00000005) /*!< LCD RAM Register 5  */
+#define LCD_RAM_REGISTER6               ((uint32_t)0x00000006) /*!< LCD RAM Register 6  */
+#define LCD_RAM_REGISTER7               ((uint32_t)0x00000007) /*!< LCD RAM Register 7  */
+#define LCD_RAM_REGISTER8               ((uint32_t)0x00000008) /*!< LCD RAM Register 8  */
+#define LCD_RAM_REGISTER9               ((uint32_t)0x00000009) /*!< LCD RAM Register 9  */
+#define LCD_RAM_REGISTER10              ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
+#define LCD_RAM_REGISTER11              ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
+#define LCD_RAM_REGISTER12              ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
+#define LCD_RAM_REGISTER13              ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
+#define LCD_RAM_REGISTER14              ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
+#define LCD_RAM_REGISTER15              ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_HighDrive LCD High Drive
+  * @{
+  */
+
+#define LCD_HIGHDRIVE_DISABLE             ((uint32_t)0x00000000)        /*!< High drive disabled */
+#define LCD_HIGHDRIVE_ENABLE              (LCD_FCR_HD)                  /*!< High drive enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_MuxSegment LCD Mux Segment
+  * @{
+  */
+
+#define LCD_MUXSEGMENT_DISABLE            ((uint32_t)0x00000000)        /*!< SEG pin multiplexing disabled */
+#define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Flag_Definition LCD Flags Definition
+  * @{
+  */
+#define LCD_FLAG_ENS                    LCD_SR_ENS   /*!< LCD enabled status */
+#define LCD_FLAG_SOF                    LCD_SR_SOF   /*!< Start of frame flag */
+#define LCD_FLAG_UDR                    LCD_SR_UDR   /*!< Update display request */
+#define LCD_FLAG_UDD                    LCD_SR_UDD   /*!< Update display done */
+#define LCD_FLAG_RDY                    LCD_SR_RDY   /*!< Ready flag */
+#define LCD_FLAG_FCRSF                  LCD_SR_FCRSR /*!< LCD Frame Control Register Synchronization flag */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup LCD_Exported_Macros LCD Exported Macros
+  * @{
+  */
+
+/** @brief Reset LCD handle state.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
+
+/** @brief  Enable the LCD peripheral.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
+
+/** @brief  Disable the LCD peripheral.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
+
+/** @brief  Enable the low resistance divider.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @note   Displays with high internal resistance may need a longer drive time to
+  *         achieve satisfactory contrast. This function is useful in this case if
+  *         some additional power consumption can be tolerated.
+  * @note   When this mode is enabled, the PulseOn Duration (PON) have to be
+  *         programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
+  * @retval None
+  */
+#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)                       \
+                  do {                                                \
+                    SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
+                    LCD_WaitForSynchro(__HANDLE__);                   \
+                  } while(0)
+
+/** @brief  Disable the low resistance divider.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)                        \
+                  do {                                                  \
+                    CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
+                    LCD_WaitForSynchro(__HANDLE__);                     \
+                  } while(0)
+
+/** @brief  Enable the voltage output buffer for higher driving capability.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
+
+/** @brief  Disable the voltage output buffer for higher driving capability.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
+
+/**
+  * @brief  Configure the LCD pulse on duration.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __DURATION__: specifies the LCD pulse on duration in terms of
+  *         CK_PS (prescaled LCD clock period) pulses.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_PULSEONDURATION_0: 0 pulse
+  *     @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
+  *     @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
+  *     @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
+  *     @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
+  *     @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
+  *     @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
+  *     @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
+  * @retval None
+  */
+#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)                        \
+                  do {                                                                    \
+                    MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
+                    LCD_WaitForSynchro(__HANDLE__);                                       \
+                  } while(0)
+
+/**
+  * @brief  Configure the LCD dead time.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __DEADTIME__: specifies the LCD dead time.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_DEADTIME_0: No dead Time
+  *     @arg LCD_DEADTIME_1: One Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
+  * @retval None
+  */
+#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)                                \
+                  do {                                                                     \
+                    MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
+                    LCD_WaitForSynchro(__HANDLE__);                                        \
+                  } while(0)
+
+/**
+  * @brief  Configure the LCD contrast.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __CONTRAST__: specifies the LCD Contrast.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
+  *     @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
+  *     @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
+  *     @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
+  *     @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
+  *     @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
+  *     @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
+  *     @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
+  * @retval None
+  */
+#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)                           \
+              do {                                                                    \
+                MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
+                LCD_WaitForSynchro(__HANDLE__);                                       \
+              } while(0)
+
+/**
+  * @brief  Configure the LCD Blink mode and Blink frequency.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __BLINKMODE__: specifies the LCD blink mode.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_BLINKMODE_OFF:           Blink disabled
+  *     @arg LCD_BLINKMODE_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
+  *     @arg LCD_BLINKMODE_SEG0_ALLCOM:   Blink enabled on SEG[0], all COM (up to 8
+  *                                       pixels according to the programmed duty)
+  *     @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM
+  *                                       (all pixels)
+  * @param  __BLINKFREQUENCY__: specifies the LCD blink frequency.
+  *     @arg LCD_BLINKFREQUENCY_DIV8:    The Blink frequency = fLcd/8
+  *     @arg LCD_BLINKFREQUENCY_DIV16:   The Blink frequency = fLcd/16
+  *     @arg LCD_BLINKFREQUENCY_DIV32:   The Blink frequency = fLcd/32
+  *     @arg LCD_BLINKFREQUENCY_DIV64:   The Blink frequency = fLcd/64
+  *     @arg LCD_BLINKFREQUENCY_DIV128:  The Blink frequency = fLcd/128
+  *     @arg LCD_BLINKFREQUENCY_DIV256:  The Blink frequency = fLcd/256
+  *     @arg LCD_BLINKFREQUENCY_DIV512:  The Blink frequency = fLcd/512
+  *     @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
+  * @retval None
+  */
+#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)         \
+              do {                                                                    \
+                MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
+                LCD_WaitForSynchro(__HANDLE__);                                       \
+              } while(0)
+
+/** @brief  Enable the specified LCD interrupt.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __INTERRUPT__: specifies the LCD interrupt source to be enabled.
+  *          This parameter can be one of the following values:
+  *     @arg LCD_IT_SOF: Start of Frame Interrupt
+  *     @arg LCD_IT_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)                      \
+                  do {                                                      \
+                    SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));  \
+                    LCD_WaitForSynchro(__HANDLE__);                         \
+                  } while(0)
+
+/** @brief  Disable the specified LCD interrupt.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __INTERRUPT__: specifies the LCD interrupt source to be disabled.
+  *          This parameter can be one of the following values:
+  *     @arg LCD_IT_SOF: Start of Frame Interrupt
+  *     @arg LCD_IT_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)                      \
+                  do {                                                       \
+                    CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
+                    LCD_WaitForSynchro(__HANDLE__);                          \
+                  } while(0)
+
+/** @brief  Check whether the specified LCD interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __IT__: specifies the LCD interrupt source to check.
+  *        This parameter can be one of the following values:
+  *        @arg LCD_IT_SOF: Start of Frame Interrupt
+  *        @arg LCD_IT_UDD: Update Display Done Interrupt.
+  * @note If the device is in STOP mode (PCLK not provided) UDD will not
+  *          generate an interrupt even if UDDIE = 1.
+  *          If the display is not enabled the UDD interrupt will never occur.
+  * @retval The state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
+
+/** @brief  Check whether the specified LCD flag is set or not.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *        @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
+  * @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR
+  *             goes from 0 to 1. On deactivation it reflects the real status of
+  *             LCD so it becomes 0 at the end of the last displayed frame.
+  *        @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
+  *             the beginning of a new frame, at the same time as the display data is
+  *             updated.
+  *        @arg LCD_FLAG_UDR: Update Display Request flag.
+  *        @arg LCD_FLAG_UDD: Update Display Done flag.
+  *        @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
+  *             of the step-up converter.
+  *        @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
+  *             This flag is set by hardware each time the LCD_FCR register is updated
+  *             in the LCDCLK domain.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified LCD pending flag.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *        This parameter can be any combination of the following values:
+  *        @arg LCD_FLAG_SOF: Start of Frame Interrupt
+  *        @arg LCD_FLAG_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__)  WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/** @addtogroup LCD_Exported_Functions
+  * @{
+  */
+
+/* Initialization/de-initialization methods  **********************************/
+/** @addtogroup LCD_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef    HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
+HAL_StatusTypeDef    HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
+void                 HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
+void                 HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
+/**
+  * @}
+  */
+
+/* IO operation methods *******************************************************/
+/** @addtogroup LCD_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef    HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
+HAL_StatusTypeDef    HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
+HAL_StatusTypeDef    HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
+/**
+  * @}
+  */
+
+/* Peripheral State methods  **************************************************/
+/** @addtogroup LCD_Exported_Functions_Group3
+  * @{
+  */
+HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
+uint32_t             HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LCD_Private_Macros LCD Private Macros
+  * @{
+  */
+
+#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_2)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_4)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_8)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_16)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_32)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_64)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_128)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_256)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_512)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_16384) || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_32768))
+
+#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_17) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_18) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_19) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_20) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_21) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_22) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_23) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_24) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_25) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_26) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_27) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_28) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_29) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_30) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_31))
+
+#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC)  || \
+                               ((__DUTY__) == LCD_DUTY_1_2)     || \
+                               ((__DUTY__) == LCD_DUTY_1_3)     || \
+                               ((__DUTY__) == LCD_DUTY_1_4)     || \
+                               ((__DUTY__) == LCD_DUTY_1_8))
+
+#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
+                               ((__BIAS__) == LCD_BIAS_1_2) || \
+                               ((__BIAS__) == LCD_BIAS_1_3))
+
+#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
+                                       ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
+
+
+#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_1) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_2) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_3) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_4) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_5) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_6) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_7))
+
+#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
+                                    ((__TIME__) == LCD_DEADTIME_1) || \
+                                    ((__TIME__) == LCD_DEADTIME_2) || \
+                                    ((__TIME__) == LCD_DEADTIME_3) || \
+                                    ((__TIME__) == LCD_DEADTIME_4) || \
+                                    ((__TIME__) == LCD_DEADTIME_5) || \
+                                    ((__TIME__) == LCD_DEADTIME_6) || \
+                                    ((__TIME__) == LCD_DEADTIME_7))
+
+#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF)            || \
+                                     ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
+                                     ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
+                                     ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
+
+#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
+
+#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
+
+#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER10) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER11) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER12) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER13) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER14) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER15))
+
+#define IS_LCD_HIGH_DRIVE(__VALUE__) (((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \
+                                      ((__VALUE__) == LCD_HIGHDRIVE_ENABLE))
+
+#define IS_LCD_MUX_SEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
+                                       ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup LCD_Private_Functions
+  * @{
+  */
+
+HAL_StatusTypeDef     LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_LCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h

@@ -0,0 +1,704 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_lptim.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of LPTIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_LPTIM_H
+#define __STM32L4xx_HAL_LPTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup LPTIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  LPTIM Clock configuration definition
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Selects the clock source.
+                           This parameter can be a value of @ref LPTIM_Clock_Source   */
+
+  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
+                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */
+
+}LPTIM_ClockConfigTypeDef;
+
+/**
+  * @brief  LPTIM Clock configuration definition
+  */
+typedef struct
+{
+  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
+                           if the ULPTIM input is selected.
+                           Note: This parameter is used only when Ultra low power clock source is used.
+                           Note: If the polarity is configured on 'both edges', an auxiliary clock
+                           (one of the Low power oscillator) must be active.
+                           This parameter can be a value of @ref LPTIM_Clock_Polarity */
+
+  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
+                           Note: This parameter is used only when Ultra low power clock source is used.
+                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
+
+}LPTIM_ULPClockConfigTypeDef;
+
+/**
+  * @brief  LPTIM Trigger configuration definition
+  */
+typedef struct
+{
+  uint32_t Source;        /*!< Selects the Trigger source.
+                          This parameter can be a value of @ref LPTIM_Trigger_Source */
+
+  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
+                          Note: This parameter is used only when an external trigger is used.
+                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
+
+  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
+                          Note: This parameter is used only when an external trigger is used.
+                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
+}LPTIM_TriggerConfigTypeDef;
+
+/**
+  * @brief  LPTIM Initialization Structure definition
+  */
+typedef struct
+{
+  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
+
+  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
+
+  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
+
+  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
+                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */
+
+  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autoreload and the compare
+                                                    values is done immediately or after the end of current period.
+                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */
+
+  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
+                                                    or each external event.
+                                                    This parameter can be a value of @ref LPTIM_Counter_Source */
+
+  uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).
+                                                    This parameter can be a value of @ref LPTIM_Input1_Source */
+
+  uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).
+                                                    Note: This parameter is used only for encoder feature so is used only
+                                                    for LPTIM1 instance.
+                                                    This parameter can be a value of @ref LPTIM_Input2_Source */
+
+}LPTIM_InitTypeDef;
+
+/**
+  * @brief  HAL LPTIM State structure definition
+  */
+typedef enum __HAL_LPTIM_StateTypeDef
+{
+  HAL_LPTIM_STATE_RESET            = 0x00,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_LPTIM_STATE_READY            = 0x01,    /*!< Peripheral Initialized and ready for use    */
+  HAL_LPTIM_STATE_BUSY             = 0x02,    /*!< An internal process is ongoing              */
+  HAL_LPTIM_STATE_TIMEOUT          = 0x03,    /*!< Timeout state                               */
+  HAL_LPTIM_STATE_ERROR            = 0x04     /*!< Internal Process is ongoing                */
+}HAL_LPTIM_StateTypeDef;
+
+/**
+  * @brief  LPTIM handle Structure definition
+  */
+typedef struct
+{
+      LPTIM_TypeDef              *Instance;         /*!< Register base address     */
+
+      LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */
+
+      HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */
+
+      HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */
+
+   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
+
+}LPTIM_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
+  * @{
+  */
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00)
+#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
+  * @{
+  */
+#define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000)
+#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
+#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
+#define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
+#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
+#define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
+  * @{
+  */
+
+#define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000)
+#define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
+  * @{
+  */
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
+  * @{
+  */
+#define LPTIM_CLOCKPOLARITY_RISING              ((uint32_t)0x00000000)
+#define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
+  * @{
+  */
+#define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFF)
+#define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000)
+#define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
+#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
+#define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
+#define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_6                      ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
+  * @{
+  */
+#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
+#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
+#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
+  * @{
+  */
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
+  * @{
+  */
+
+#define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000)
+#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
+  * @{
+  */
+
+#define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000)
+#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
+  * @{
+  */
+
+#define LPTIM_INPUT1SOURCE_GPIO         ((uint32_t)0x00000000) /*!< For LPTIM1 and LPTIM2 */
+#define LPTIM_INPUT1SOURCE_COMP1        LPTIM_OR_OR_0          /*!< For LPTIM1 and LPTIM2 */
+#define LPTIM_INPUT1SOURCE_COMP2        LPTIM_OR_OR_1          /*!< For LPTIM2 */
+#define LPTIM_INPUT1SOURCE_COMP1_COMP2  LPTIM_OR_OR            /*!< For LPTIM2 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
+  * @{
+  */
+
+#define LPTIM_INPUT2SOURCE_GPIO         ((uint32_t)0x00000000) /*!< For LPTIM1 */
+#define LPTIM_INPUT2SOURCE_COMP2        LPTIM_OR_OR_1          /*!< For LPTIM1 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
+  * @{
+  */
+
+#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
+#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
+#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
+#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
+#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
+#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
+#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
+  * @{
+  */
+
+#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
+#define LPTIM_IT_UP                              LPTIM_IER_UPIE
+#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
+#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
+#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
+#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
+#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
+  * @{
+  */
+
+/** @brief Reset LPTIM handle state.
+  * @param  __HANDLE__: LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
+
+/**
+  * @brief  Enable the LPTIM peripheral.
+  * @param  __HANDLE__: LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))
+
+/**
+  * @brief  Disable the LPTIM peripheral.
+  * @param  __HANDLE__: LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))
+
+/**
+  * @brief  Start the LPTIM peripheral in Continuous or in single mode.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
+
+
+/**
+  * @brief  Write the passed parameter in the Autoreload register.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __VALUE__: Autoreload value
+  * @retval None
+  */
+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
+
+/**
+  * @brief  Write the passed parameter in the Compare register.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __VALUE__: Compare value
+  * @retval None
+  */
+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
+
+/**
+  * @brief  Check whether the specified LPTIM flag is set or not.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __FLAG__: LPTIM flag to check
+  *            This parameter can be a value of:
+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
+  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
+  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
+  * @retval The state of the specified flag (SET or RESET).
+  */
+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the specified LPTIM flag.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __FLAG__: LPTIM flag to clear.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
+  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
+  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
+  * @retval None
+  */
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
+
+/**
+  * @brief  Enable the specified LPTIM interrupt.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __INTERRUPT__: LPTIM interrupt to set.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval None
+  */
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
+
+ /**
+  * @brief  Disable the specified LPTIM interrupt.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __INTERRUPT__: LPTIM interrupt to set.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval None
+  */
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
+
+    /**
+  * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __INTERRUPT__: LPTIM interrupt to check.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval Interrupt status.
+  */
+
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* MSP functions  *************************************************************/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* Start/Stop operation functions  *********************************************/
+/* ################################# PWM Mode ################################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# One Pulse Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Set once Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################### Encoder Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# Time out  Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Counter Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* Reading operation functions ************************************************/
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+
+/* LPTIM IRQ functions  *******************************************************/
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
+
+/* CallBack functions  ********************************************************/
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+
+/* Peripheral State functions  ************************************************/
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Types LPTIM Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
+  * @{
+  */
+
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+
+
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
+
+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
+                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
+
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
+
+#define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))
+
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
+                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
+                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
+
+#define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFF)
+
+#define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFF)
+
+#define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFF)
+
+#define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFF)
+
+#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)  \
+    ((((__INSTANCE__) == LPTIM1) &&                       \
+     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
+     ||                                                   \
+     (((__INSTANCE__) == LPTIM2) &&                       \
+     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
+
+#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
+     (((__INSTANCE__) == LPTIM1) &&                       \
+     (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
+      ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_LPTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h

@@ -0,0 +1,307 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_nand.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of NAND HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_NAND_H
+#define __STM32L4xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_fmc.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup NAND
+  * @{
+  */
+
+/** @addtogroup NAND_Private_Constants
+  * @{
+  */
+
+#define NAND_DEVICE                FMC_BANK3
+#define NAND_WRITE_TIMEOUT         ((uint32_t)1000)
+
+#define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
+#define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)
+#define NAND_CMD_READID            ((uint8_t)0x90)
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
+#define NAND_BUSY                  ((uint32_t)0x00000000)
+#define NAND_ERROR                 ((uint32_t)0x00000001)
+#define NAND_READY                 ((uint32_t)0x00000040)
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Private_Macros
+  * @{
+  */
+
+/**
+  * @brief  NAND memory address computation.
+  * @param  __ADDRESS__: NAND memory address.
+  * @param  __HANDLE__: NAND handle.
+  * @retval NAND Raw address value
+  */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
+                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
+
+/**
+  * @brief  NAND memory address cycling.
+  * @param  __ADDRESS__: NAND memory address.
+  * @retval NAND address cycling value.
+  */
+#define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL NAND State structures definition
+  */
+typedef enum
+{
+  HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
+  HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
+  HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
+  HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
+}HAL_NAND_StateTypeDef;
+
+/**
+  * @brief  NAND Memory electronic signature Structure definition
+  */
+typedef struct
+{
+  /*<! NAND memory electronic signature maker and device IDs */
+
+  uint8_t Maker_Id;
+
+  uint8_t Device_Id;
+
+  uint8_t Third_Id;
+
+  uint8_t Fourth_Id;
+}NAND_IDTypeDef;
+
+/**
+  * @brief  NAND Memory address Structure definition
+  */
+typedef struct
+{
+  uint16_t Page;   /*!< NAND memory Page address  */
+
+  uint16_t Zone;   /*!< NAND memory Zone address  */
+
+  uint16_t Block;  /*!< NAND memory Block address */
+
+}NAND_AddressTypeDef;
+
+/**
+  * @brief  NAND Memory info Structure definition
+  */
+typedef struct
+{
+  uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
+
+  uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
+
+  uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
+
+  uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
+
+  uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
+}NAND_InfoTypeDef;
+
+/**
+  * @brief  NAND handle Structure definition
+  */
+typedef struct
+{
+  FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
+
+  FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
+
+  HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
+
+  __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
+
+  NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
+}NAND_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
+ * @{
+ */
+
+/** @brief Reset NAND handle state.
+  * @param  __HANDLE__: specifies the NAND handle.
+  * @retval None
+  */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+  * @{
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef   HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef   HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+void                HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void                HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void                HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void                HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+  * @{
+  */
+
+/* IO operation functions  ****************************************************/
+HAL_StatusTypeDef   HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef   HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef   HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef   HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef   HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef   HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef   HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t            HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t            HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* NAND Control functions  ****************************************************/
+HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h

@@ -0,0 +1,303 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_nor.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of NOR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_NOR_H
+#define __STM32L4xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_fmc.h"
+
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup NOR
+  * @{
+  */
+
+/** @addtogroup NOR_Private_Constants
+  * @{
+  */
+
+/* NOR device IDs addresses */
+#define MC_ADDRESS               ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS             ((uint16_t)0x10)
+#define CFI2_ADDRESS             ((uint16_t)0x11)
+#define CFI3_ADDRESS             ((uint16_t)0x12)
+#define CFI4_ADDRESS             ((uint16_t)0x13)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B            ((uint8_t)0x0)
+#define NOR_MEMORY_16B           ((uint8_t)0x1)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1       FMC_BANK1_1
+#define NOR_MEMORY_ADRESS2       FMC_BANK1_2
+#define NOR_MEMORY_ADRESS3       FMC_BANK1_3
+#define NOR_MEMORY_ADRESS4       FMC_BANK1_4
+
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Private_Macros
+  * @{
+  */
+
+/**
+  * @brief  NOR memory address shifting.
+  * @param  __NOR_ADDRESS: NOR base address
+  * @param  __NOR_MEMORY_WIDTH_: NOR memory width
+  * @param  __ADDRESS__: NOR memory address
+  * @retval NOR shifted address value
+  */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
+            ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
+              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
+              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
+/**
+  * @brief  NOR memory write data to specified address.
+  * @param  __ADDRESS__: NOR memory address
+  * @param  __DATA__: Data to write
+  * @retval None
+  */
+#define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL SRAM State structures definition
+  */
+typedef enum
+{
+  HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
+  HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
+  HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
+  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
+  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
+}HAL_NOR_StateTypeDef;
+
+/**
+  * @brief  FMC NOR Status typedef
+  */
+typedef enum
+{
+  HAL_NOR_STATUS_SUCCESS = 0,
+  HAL_NOR_STATUS_ONGOING,
+  HAL_NOR_STATUS_ERROR,
+  HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef;
+
+/**
+  * @brief  FMC NOR ID typedef
+  */
+typedef struct
+{
+  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
+
+  uint16_t Device_Code1;
+
+  uint16_t Device_Code2;
+
+  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
+                                    These codes can be accessed by performing read operations with specific
+                                    control signals and addresses set.They can also be accessed by issuing
+                                    an Auto Select command.                                                   */
+}NOR_IDTypeDef;
+
+/**
+  * @brief  FMC NOR CFI typedef
+  */
+typedef struct
+{
+  uint16_t CFI_1;
+
+  uint16_t CFI_2;
+
+  uint16_t CFI_3;
+
+  uint16_t CFI_4;  /*!< Defines the information stored in the memory's Common flash interface
+                        which contains a description of various electrical and timing parameters,
+                        density information and functions supported by the memory.                   */
+}NOR_CFITypeDef;
+
+/**
+  * @brief  NOR handle Structure definition
+  */
+typedef struct
+{
+  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
+
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
+
+  FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
+
+  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
+
+  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
+
+}NOR_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+  * @{
+  */
+
+/** @brief Reset NOR handle state.
+  * @param  __HANDLE__: NOR handle
+  * @retval None
+  */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+  * @{
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
+  * @{
+  */
+
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* NOR Control functions  *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h

@@ -0,0 +1,425 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_opamp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of OPAMP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_OPAMP_H
+#define __STM32L4xx_HAL_OPAMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup OPAMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
+  * @{
+  */
+
+/**
+  * @brief  OPAMP Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t PowerSupplyRange;            /*!< Specifies the power supply range: above or under 2.4V.
+                                             This parameter must be a value of @ref OPAMP_PowerSupplyRange
+                                             Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */
+
+  uint32_t PowerMode;                   /*!< Specifies the power mode Normal or Low-Power.
+                                             This parameter must be a value of @ref OPAMP_PowerMode */
+
+  uint32_t Mode;                        /*!< Specifies the OPAMP mode
+                                             This parameter must be a value of @ref OPAMP_Mode
+                                             mode is either Standalone, - Follower or PGA */
+
+  uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone & PGA modes
+                                               - In Standalone mode:   i.e. when mode is OPAMP_STANDALONE_MODE
+                                                 & PGA mode:           i.e. when mode is OPAMP_PGA_MODE
+                                                 This parameter must be a value of @ref OPAMP_InvertingInput
+                                               - In Follower mode    i.e. when mode is OPAMP_FOLLOWER_MODE
+                                                 This parameter is Not Applicable */
+
+  uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp:
+                                             This parameter must be a value of @ref OPAMP_NonInvertingInput */
+
+  uint32_t PgaGain;                     /*!< Specifies the gain in PGA mode
+                                             i.e. when mode is OPAMP_PGA_MODE.
+                                             This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */
+
+  uint32_t UserTrimming;                /*!< Specifies the trimming mode
+                                             This parameter must be a value of @ref OPAMP_UserTrimming
+                                             UserTrimming is either factory or user trimming.*/
+
+  uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS)
+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31
+                                             16 is typical default value */
+
+  uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS)
+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31
+                                             16 is typical default value */
+
+  uint32_t TrimmingValuePLowPower;      /*!< Specifies the offset trimming value (PMOS)
+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31
+                                             16 is typical default value */
+
+  uint32_t TrimmingValueNLowPower;      /*!< Specifies the offset trimming value (NMOS)
+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31
+                                             16 is typical default value */
+
+}OPAMP_InitTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+
+typedef enum
+{
+  HAL_OPAMP_STATE_RESET               = 0x00000000, /*!< OPAMP is not yet Initialized          */
+
+  HAL_OPAMP_STATE_READY               = 0x00000001, /*!< OPAMP is initialized and ready for use */
+  HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
+
+  HAL_OPAMP_STATE_BUSY                = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
+  HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005  /*!< OPAMP is locked
+                                                         only system reset allows reconfiguring the opamp. */
+
+}HAL_OPAMP_StateTypeDef;
+
+/**
+  * @brief OPAMP Handle Structure definition
+  */
+typedef struct
+{
+  OPAMP_TypeDef       *Instance;                    /*!< OPAMP instance's registers base address   */
+  OPAMP_InitTypeDef   Init;                         /*!< OPAMP required parameters */
+  HAL_StatusTypeDef Status;                         /*!< OPAMP peripheral status   */
+  HAL_LockTypeDef   Lock;                           /*!< Locking object          */
+  __IO HAL_OPAMP_StateTypeDef  State;               /*!< OPAMP communication state */
+
+} OPAMP_HandleTypeDef;
+
+/**
+  * @brief HAl_OPAMP_TrimmingValueTypeDef definition
+  */
+
+typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
+  * @{
+  */
+
+/** @defgroup OPAMP_Mode OPAMP Mode
+  * @{
+  */
+#define OPAMP_STANDALONE_MODE            ((uint32_t)0x00000000) /*!< standalone mode */
+#define OPAMP_PGA_MODE                   OPAMP_CSR_OPAMODE_1    /*!< PGA mode */
+#define OPAMP_FOLLOWER_MODE              OPAMP_CSR_OPAMODE      /*!< follower mode */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_IO0        ((uint32_t)0x00000000)  /*!< OPAMP non-inverting input connected to dedicated IO pin */
+#define OPAMP_NONINVERTINGINPUT_DAC_CH      OPAMP_CSR_VPSEL        /*!< OPAMP non-inverting input connected internally to DAC channel */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
+  * @{
+  */
+
+#define OPAMP_INVERTINGINPUT_IO0              ((uint32_t)0x00000000)  /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */
+#define OPAMP_INVERTINGINPUT_IO1              OPAMP_CSR_VMSEL_0       /*!< OPAMP inverting input connected to alternative IO pin available on some device packages */
+#define OPAMP_INVERTINGINPUT_CONNECT_NO       OPAMP_CSR_VMSEL_1       /*!< OPAMP inverting input not connected externally (PGA mode only) */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
+  * @{
+  */
+
+#define OPAMP_PGA_GAIN_2                ((uint32_t)0x00000000)                        /*!< PGA gain =  2 */
+#define OPAMP_PGA_GAIN_4                OPAMP_CSR_PGGAIN_0                            /*!< PGA gain =  4 */
+#define OPAMP_PGA_GAIN_8                OPAMP_CSR_PGGAIN_1                            /*!< PGA gain =  8 */
+#define OPAMP_PGA_GAIN_16              (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)      /*!< PGA gain = 16 */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_PowerMode OPAMP PowerMode
+  * @{
+  */
+#define OPAMP_POWERMODE_NORMAL        ((uint32_t)0x00000000)
+#define OPAMP_POWERMODE_LOWPOWER      OPAMP_CSR_OPALPM
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange
+  * @{
+  */
+#define OPAMP_POWERSUPPLY_LOW          ((uint32_t)0x00000000)  /*!< Power supply range low (VDDA lower than 2.4V) */
+#define OPAMP_POWERSUPPLY_HIGH         OPAMP1_CSR_OPARANGE     /*!< Power supply range high (VDDA higher than 2.4V) */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
+  * @{
+  */
+#define OPAMP_TRIMMING_FACTORY        ((uint32_t)0x00000000)                          /*!< Factory trimming */
+#define OPAMP_TRIMMING_USER           OPAMP_CSR_USERTRIM                              /*!< User trimming */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
+  * @{
+  */
+#define OPAMP_FACTORYTRIMMING_DUMMY    ((uint32_t)0xFFFFFFFF)                           /*!< Dummy value if trimming value could not be retrieved */
+
+#define OPAMP_FACTORYTRIMMING_N        ((uint32_t)0x00000000)                          /*!< Offset trimming N */
+#define OPAMP_FACTORYTRIMMING_P        ((uint32_t)0x00000001)                          /*!< Offset trimming P */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
+  * @brief   OPAMP Private constants and defines
+  * @{
+  */
+
+/* NONINVERTING bit position in OTR & LPOTR */
+#define OPAMP_INPUT_NONINVERTING              ((uint32_t) 8) /*!< Non inverting input */
+
+/* Offset trimming time: during calibration, minimum time needed between two  */
+/* steps to have 1 mV accuracy.                                               */
+/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=1ms.*/
+/* Unit: ms.                                                                  */
+#define OPAMP_TRIMMING_DELAY               ((uint32_t) 1)
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
+  * @{
+  */
+
+/** @brief Reset OPAMP handle state.
+  * @param  __HANDLE__: OPAMP handle.
+  * @retval None
+  */
+#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup OPAMP_Private_Macros OPAMP Private Macros
+  * @{
+  */
+
+#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
+                                               ((INPUT) == OPAMP_PGA_MODE) || \
+                                               ((INPUT) == OPAMP_FOLLOWER_MODE))
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+
+#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+                                                    ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
+#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx)  || defined (STM32L442xx)  || defined (STM32L443xx) || defined (STM32L451xx)  || defined (STM32L452xx)  || defined (STM32L462xx)
+#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) ((INPUT) == OPAMP_INVERTINGINPUT_IO0)
+#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */
+
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
+                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+                                             ((INPUT) == OPAMP_INVERTINGINPUT_IO1)|| \
+                                             ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
+#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
+
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx)  || defined (STM32L442xx)  || defined (STM32L443xx) || defined (STM32L451xx)  || defined (STM32L452xx)  || defined (STM32L462xx)
+#define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+                                             ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
+#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */
+
+#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
+                                 ((GAIN) == OPAMP_PGA_GAIN_4) || \
+                                 ((GAIN) == OPAMP_PGA_GAIN_8) || \
+                                 ((GAIN) == OPAMP_PGA_GAIN_16))
+
+#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
+                                      ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) )
+
+#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \
+                                            ((RANGE) == OPAMP_POWERSUPPLY_HIGH)  )
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
+                                     ((TRIMMING) == OPAMP_TRIMMING_USER))
+
+
+#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
+
+#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
+                                             ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
+
+/**
+  * @}
+  */
+
+/* Include OPAMP HAL Extended module */
+#include "stm32l4xx_hal_opamp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup OPAMP_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
+/**
+  * @}
+  */
+
+/** @addtogroup OPAMP_Exported_Functions_Group2
+  * @{
+  */
+
+/* I/O operation functions  *****************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
+
+/**
+  * @}
+  */
+
+/** @addtogroup OPAMP_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
+HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
+
+/**
+  * @}
+  */
+
+/** @addtogroup OPAMP_Exported_Functions_Group4
+  * @{
+  */
+
+/* Peripheral State functions  **************************************************/
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_OPAMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h

@@ -0,0 +1,107 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_opamp_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of OPAMP HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_OPAMP_EX_H
+#define __STM32L4xx_HAL_OPAMP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup OPAMPEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
+  * @{
+  */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+
+/* I/O operation functions  *****************************************************/
+/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
+
+/**
+  * @}
+  */
+#endif
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup OPAMPEx_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_OPAMP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_pcd.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L4xx_HAL_PCD_H
@@ -43,28 +43,31 @@
  extern "C" {
 #endif
 
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l4xx_ll_usb.h"
-   
+
 /** @addtogroup STM32L4xx_HAL_Driver
   * @{
   */
 
 /** @addtogroup PCD
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup PCD_Exported_Types PCD Exported Types
   * @{
   */
 
-   /** 
-  * @brief  PCD State structure definition  
-  */  
-typedef enum 
+   /**
+  * @brief  PCD State structure definition
+  */
+typedef enum
 {
   HAL_PCD_STATE_RESET   = 0x00,
   HAL_PCD_STATE_READY   = 0x01,
@@ -74,7 +77,7 @@ typedef enum
 } PCD_StateTypeDef;
 
 /* Device LPM suspend state */
-typedef enum  
+typedef enum
 {
   LPM_L0 = 0x00, /* on */
   LPM_L1 = 0x01, /* LPM L1 sleep */
@@ -82,39 +85,73 @@ typedef enum
   LPM_L3 = 0x03, /* off */
 }PCD_LPM_StateTypeDef;
 
+#if defined (USB)
+/**
+  * @brief  PCD double buffered endpoint direction
+  */
+typedef enum
+{
+  PCD_EP_DBUF_OUT,
+  PCD_EP_DBUF_IN,
+  PCD_EP_DBUF_ERR,
+}PCD_EP_DBUF_DIR;
+
+/**
+  * @brief  PCD endpoint buffer number
+  */
+typedef enum
+{
+  PCD_EP_NOBUF,
+  PCD_EP_BUF0,
+  PCD_EP_BUF1
+}PCD_EP_BUF_NUM;
+#endif /* USB */
+
+#if defined (USB_OTG_FS)
 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;                          
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+typedef USB_TypeDef        PCD_TypeDef;
+typedef USB_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_EPTypeDef      PCD_EPTypeDef;
+#endif /* USB */
 
-/** 
-  * @brief  PCD Handle Structure definition  
-  */ 
+/**
+  * @brief  PCD Handle Structure definition
+  */
 typedef struct
 {
-  PCD_TypeDef             *Instance;   /*!< Register base address              */ 
+  PCD_TypeDef             *Instance;   /*!< Register base address              */
   PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
+  __IO uint8_t            USB_Address; /*!< USB Address: not used by USB OTG FS */
   PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */ 
+  PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */
   HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
   __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
   uint32_t                Setup[12];   /*!< Setup packet buffer                */
   PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
   uint32_t                BESL;
-  
-  
-  uint32_t lpm_active;                  /*!< Enable or disable the Link Power Management .                                  
+
+
+  uint32_t lpm_active;                  /*!< Enable or disable the Link Power Management .
                                         This parameter can be set to ENABLE or DISABLE                      */
 
-  uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.                                  
+  uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.
                                         This parameter can be set to ENABLE or DISABLE                      */
-  void                    *pData;      /*!< Pointer to upper stack Handler     */    
-  
+  void                    *pData;      /*!< Pointer to upper stack Handler     */
+
 } PCD_HandleTypeDef;
 
 /**
   * @}
   */
-  
+
+/* Include PCD HAL Extended module */
+#include "stm32l4xx_hal_pcd_ex.h"
+
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup PCD_Exported_Constants PCD Exported Constants
   * @{
@@ -127,7 +164,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 /** @defgroup PCD_PHY_Module PCD PHY Module
   * @{
   */
@@ -148,16 +185,17 @@ typedef struct
 
 /**
   * @}
-  */ 
-  
+  */
+
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup PCD_Exported_Macros PCD Exported Macros
  *  @brief macros to handle interrupts and specific clock configurations
  * @{
  */
+#if defined (USB_OTG_FS)
 #define __HAL_PCD_ENABLE(__HANDLE__)                       USB_EnableGlobalInt ((__HANDLE__)->Instance)
 #define __HAL_PCD_DISABLE(__HANDLE__)                      USB_DisableGlobalInt ((__HANDLE__)->Instance)
-   
+
 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
@@ -167,16 +205,9 @@ typedef struct
                                                           ~(USB_OTG_PCGCCTL_STOPCLK)
 
 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-                                                      
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
-                                                         
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08) 
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0C) 
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10) 
 
-#define USB_OTG_FS_WAKEUP_EXTI_LINE                       ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the USB FS EXTI Line */
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
 
-                                                      
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
@@ -197,17 +228,48 @@ typedef struct
                                                                    EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                                    EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
                                                                    EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                                  } while(0)                                                                   
-                                                         
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)                                                          
+                                                                  } while(0)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)
+
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+#define __HAL_PCD_ENABLE(__HANDLE__)                                  USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                                 USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_GET_FLAG()                              EXTI->PR1 & (USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG()                            EXTI->PR1 = USB_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()                    do {\
+                                                                        EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
+                                                                        EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\
+                                                                      } while(0)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()                   do {\
+                                                                        EXTI->FTSR1 |= (USB_WAKEUP_EXTI_LINE);\
+                                                                        EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
+                                                                      } while(0)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()            do {\
+                                                                        EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
+                                                                        EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
+                                                                        EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\
+                                                                        EXTI->FTSR1 |= USB_WAKEUP_EXTI_LINE;\
+                                                                      } while(0)
+
+#define __HAL_USB_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_WAKEUP_EXTI_LINE)
+
+#endif /* USB */
 
 /**
   * @}
   */
 
-/* Include PCD HAL Extended module */
-#include "stm32l4xx_hal_pcd_ex.h"
-
 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
   * @{
   */
@@ -281,26 +343,526 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
 
 /**
   * @}
-  */ 
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+  * @{
+  */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+  * @{
+  */
+#if defined (USB_OTG_FS)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            ((uint32_t)0x08)
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           ((uint32_t)0x0C)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    ((uint32_t)0x10)
+
+#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the USB EXTI Line */
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+#define  USB_WAKEUP_EXTI_LINE                                         ((uint32_t)0x00020000)  /*!< External interrupt line 17Connected to the USB EXTI Line */
+#endif /* USB */
+
+/**
+  * @}
+  */
+
+#if defined (USB)
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
+  * @{
+  */
+#define PCD_EP0MPS_64                                                 DEP0CTL_MPS_64
+#define PCD_EP0MPS_32                                                 DEP0CTL_MPS_32
+#define PCD_EP0MPS_16                                                 DEP0CTL_MPS_16
+#define PCD_EP0MPS_08                                                 DEP0CTL_MPS_8
+/**
+  * @}
+  */
+
+/** @defgroup PCD_ENDP PCD ENDP
+  * @{
+  */
+#define PCD_ENDP0                                                     ((uint8_t)0)
+#define PCD_ENDP1                                                     ((uint8_t)1)
+#define PCD_ENDP2                                                     ((uint8_t)2)
+#define PCD_ENDP3                                                     ((uint8_t)3)
+#define PCD_ENDP4                                                     ((uint8_t)4)
+#define PCD_ENDP5                                                     ((uint8_t)5)
+#define PCD_ENDP6                                                     ((uint8_t)6)
+#define PCD_ENDP7                                                     ((uint8_t)7)
+/**
+  * @}
+  */
+
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
+  * @{
+  */
+#define PCD_SNG_BUF                                                   0
+#define PCD_DBL_BUF                                                   1
+/**
+  * @}
+  */
+#endif /* USB */
+/**
+  * @}
+  */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
+/** @addtogroup PCD_Private_Macros PCD Private Macros
  * @{
  */
+#if defined (USB)
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum)            (*(&(USBx)->EP0R + (bEpNum) * 2))
+
+/* ENDPOINT transfer */
+#define USB_EP0StartXfer                          USB_EPStartXfer
 
+/**
+  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wType: Endpoint Type.
+  * @retval None
+  */
+#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+                                  ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
+
+/**
+  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval Endpoint Type
+  */
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+
+/**
+  * @brief free buffer used from the application realizing it to the line
+          toggles bit SW_BUF in the double buffered endpoint register
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  bDir: Direction
+  * @retval None
+  */
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
+{\
+  if ((bDir) == PCD_EP_DBUF_OUT)\
+  { /* OUT double buffered endpoint */\
+    PCD_TX_DTOG((USBx), (bEpNum));\
+  }\
+  else if ((bDir) == PCD_EP_DBUF_IN)\
+  { /* IN double buffered endpoint */\
+    PCD_RX_DTOG((USBx), (bEpNum));\
+  }\
+}
+
+/**
+  * @brief gets direction of the double buffered endpoint
+  * @param   USBx: USB peripheral instance register address.
+  * @param   bEpNum: Endpoint Number.
+  * @retval EP_DBUF_OUT, EP_DBUF_IN,
+  *         EP_DBUF_ERR if the endpoint counter not yet programmed.
+  */
+#define PCD_GET_DB_DIR(USBx, bEpNum)\
+{\
+  if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
+    return(PCD_EP_DBUF_OUT);\
+  else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
+    return(PCD_EP_DBUF_IN);\
+  else\
+    return(PCD_EP_DBUF_ERR);\
+}
+
+/**
+  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wState: new state
+  * @retval None
+  */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
+   \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
+   /* toggle first bit ? */     \
+   if((USB_EPTX_DTOG1 & (wState))!= 0)\
+   {                                                                            \
+     _wRegVal ^= USB_EPTX_DTOG1;        \
+   }                                                                            \
+   /* toggle second bit ?  */         \
+   if((USB_EPTX_DTOG2 & (wState))!= 0)      \
+   {                                                                            \
+     _wRegVal ^= USB_EPTX_DTOG2;        \
+   }                                                                            \
+   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
+  } /* PCD_SET_EP_TX_STATUS */
+
+/**
+  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wState: new state
+  * @retval None
+  */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
+    register uint16_t _wRegVal;   \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
+    /* toggle first bit ? */  \
+    if((USB_EPRX_DTOG1 & (wState))!= 0) \
+    {                                                                             \
+      _wRegVal ^= USB_EPRX_DTOG1;  \
+    }                                                                             \
+    /* toggle second bit ? */  \
+    if((USB_EPRX_DTOG2 & (wState))!= 0) \
+    {                                                                             \
+      _wRegVal ^= USB_EPRX_DTOG2;  \
+    }                                                                             \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+  } /* PCD_SET_EP_RX_STATUS */
+
+/**
+  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wStaterx: new state.
+  * @param  wStatetx: new state.
+  * @retval None
+  */
+#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
+    register uint32_t _wRegVal;   \
+    \
+    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
+    /* toggle first bit ? */  \
+    if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
+    {                                                                                    \
+      _wRegVal ^= USB_EPRX_DTOG1;  \
+    }                                                                                    \
+    /* toggle second bit ? */  \
+    if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
+    {                                                                                    \
+      _wRegVal ^= USB_EPRX_DTOG2;  \
+    }                                                                                    \
+    /* toggle first bit ? */     \
+    if((USB_EPTX_DTOG1 & (wStatetx))!= 0)      \
+    {                                                                                    \
+      _wRegVal ^= USB_EPTX_DTOG1;        \
+    }                                                                                    \
+    /* toggle second bit ?  */         \
+    if((USB_EPTX_DTOG2 & (wStatetx))!= 0)      \
+    {                                                                                    \
+      _wRegVal ^= USB_EPTX_DTOG2;        \
+    }                                                                                    \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
+  } /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
+  *         /STAT_RX[1:0])
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval status
+  */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+
+/**
+  * @brief  sets directly the VALID tx/rx-status into the endpoint register
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+
+/**
+  * @brief  checks stall condition in an endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval TRUE = endpoint in stall condition.
+  */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
+                                   == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
+                                   == USB_EP_RX_STALL)
+
+/**
+  * @brief  set & clear EP_KIND bit.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+                                (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
+
+/**
+  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
+
+/**
+  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+#define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+
+/**
+  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
+                                         {                                                              \
+                                           PCD_RX_DTOG((USBx), (bEpNum));                               \
+                                         }
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
+                                         {                                                              \
+                                            PCD_TX_DTOG((USBx), (bEpNum));                              \
+                                         }
+
+/**
+  * @brief  Sets address in an endpoint register.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  bAddr: Address.
+  * @retval None
+  */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
+    USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
+
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
+
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+     ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+  ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+  ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+  ((uint32_t)(USBx) + 0x400)))
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+    uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
+    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+  }
+
+/**
+  * @brief  sets address of the tx/rx buffer.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wAddr: address to be set (must be word aligned).
+  * @retval None
+  */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+
+/**
+  * @brief  Gets address of the tx/rx buffer.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval address of the buffer.
+  */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+  * @brief  Sets counter of rx buffer with no. of blocks.
+  * @param  dwReg: Register
+  * @param  wCount: Counter.
+  * @param  wNBlocks: no. of Blocks.
+  * @retval None
+  */
+#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
+    (wNBlocks) = (wCount) >> 5;\
+    if(((wCount) & 0x1f) == 0)\
+    {                                                  \
+      (wNBlocks)--;\
+    }                                                  \
+    *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
+  }/* PCD_CALC_BLK32 */
+
+#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
+    (wNBlocks) = (wCount) >> 1;\
+    if(((wCount) & 0x1) != 0)\
+    {                                                  \
+      (wNBlocks)++;\
+    }                                                  \
+    *pdwReg = (uint16_t)((wNBlocks) << 10);\
+  }/* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount)  {\
+    uint16_t wNBlocks;\
+    if((wCount) > 62)                                \
+    {                                                \
+      PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);     \
+    }                                                \
+    else                                             \
+    {                                                \
+      PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);      \
+    }                                                \
+  }/* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
+    uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
+    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+  }
+
+/**
+  * @brief  sets counter for the tx/rx buffer.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wCount: Counter value.
+  * @retval None
+  */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
+
+
+/**
+  * @brief  gets counter of the tx buffer.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval Counter value
+  */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
+
+/**
+  * @brief  Sets buffer 0/1 address in a double buffer endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wBuf0Addr: buffer 0 address.
+  * @retval Counter value
+  */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
+
+/**
+  * @brief  Sets addresses in a double buffer endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wBuf0Addr: buffer 0 address.
+  * @param  wBuf1Addr = buffer 1 address.
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
+    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
+    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
+  } /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @param  bDir: endpoint dir  EP_DBUF_OUT = OUT
+  *         EP_DBUF_IN  = IN
+  * @param  wCount: Counter value
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
+    if((bDir) == PCD_EP_DBUF_OUT)\
+      /* OUT endpoint */ \
+    {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
+    else if((bDir) == PCD_EP_DBUF_IN)\
+      /* IN endpoint */ \
+      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
+  } /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
+    if((bDir) == PCD_EP_DBUF_OUT)\
+    {/* OUT endpoint */                                       \
+      PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));           \
+    }                                                         \
+    else if((bDir) == PCD_EP_DBUF_IN)\
+    {/* IN endpoint */                                        \
+      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+    }                                                         \
+  } /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
+    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+  } /* PCD_SET_EP_DBUF_CNT  */
+
+/**
+  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
+  * @param  USBx: USB peripheral instance register address.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+
+#endif /* USB */
+
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx)
+
+/** @defgroup PCD_Instance_definition PCD Instance definition
+  * @{
+  */
+#define IS_PCD_ALL_INSTANCE                                        IS_USB_ALL_INSTANCE
 /**
   * @}
   */
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx */
 
 /**
   * @}
-  */ 
+  */
+
+/**
+  * @}
+  */
 
 /**
   * @}
   */
 
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx || */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
 
 #ifdef __cplusplus
 }

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_pcd_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L4xx_HAL_PCD_EX_H
@@ -43,11 +43,14 @@
  extern "C" {
 #endif
 
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l4xx_hal_def.h"
-   
+
 /** @addtogroup STM32L4xx_HAL_Driver
   * @{
   */
@@ -56,21 +59,21 @@
   * @{
   */
 /* Exported types ------------------------------------------------------------*/
-typedef enum  
+typedef enum
 {
   PCD_LPM_L0_ACTIVE = 0x00, /* on */
   PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
 }PCD_LPM_MsgTypeDef;
 
-typedef enum  
+typedef enum
 {
-  PCD_BCD_ERROR                     = 0xFF, 
+  PCD_BCD_ERROR                     = 0xFF,
   PCD_BCD_CONTACT_DETECTION         = 0xFE,
   PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
   PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
   PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
   PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
-  
+
 }PCD_BCD_MsgTypeDef;
 
 /* Exported constants --------------------------------------------------------*/
@@ -82,8 +85,18 @@ typedef enum
 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
   * @{
   */
+
+#if defined(USB_OTG_FS)
 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+                                       uint16_t ep_addr,
+                                       uint16_t ep_kind,
+                                       uint32_t pmaadress);
+#endif /* USB */
 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
@@ -94,21 +107,24 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
 
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L452xx || STM32L462xx || */
+       /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
 
 #ifdef __cplusplus
 }

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_pwr.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of PWR HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -54,7 +54,7 @@
   * @{
   */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 
 /** @defgroup PWR_Exported_Types PWR Exported Types
   * @{
@@ -108,12 +108,12 @@ typedef struct
 #define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
 #define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
 #define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */                               
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
 /**
   * @}
   */
-  
-  
+
+
 
 
 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
@@ -142,7 +142,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 
 /** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
   * @{
@@ -154,7 +154,7 @@ typedef struct
 
 /** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
   * @{
-  */  
+  */
 #define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */
 /**
   * @}
@@ -181,28 +181,30 @@ typedef struct
   *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
   *                  was received from the WKUP pin 4.
   *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
-  *                  was received from the WKUP pin 5.          
+  *                  was received from the WKUP pin 5.
   *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
   *                  entered StandBy mode.
   *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
   *                 the internal wakeup line.
-  *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the 
+  *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
   *                 low-power regulator is ready.
-  *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the 
-  *                 regulator is ready in main mode or is in low-power mode. 
-  *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready 
+  *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
+  *                 regulator is ready in main mode or is in low-power mode.
+  *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
   *                 in the selected voltage range or is still changing to the required voltage level.
   *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
   *                  below or above the selected PVD threshold.
   *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
   *                  is below or above PVM1 threshold (applicable when USB feature is supported).
+  @if STM32L486xx
   *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
-  *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device). 
+  *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
+  @endif
   *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
-  *                  is below or above PVM3 threshold. 
+  *                  is below or above PVM3 threshold.
   *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
-  *                  is below or above PVM4 threshold.                           
-  *    
+  *                  is below or above PVM4 threshold.
+  *
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
@@ -225,7 +227,7 @@ typedef struct
   *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
   *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
   *                  entered Standby mode.
-  * @retval None   
+  * @retval None
   */
 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
                                          (PWR->SCR  = (__FLAG__)) :\
@@ -321,7 +323,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 
 /* Private macros --------------------------------------------------------*/
 /** @addtogroup  PWR_Private_Macros   PWR Private Macros
@@ -332,25 +334,25 @@ typedef struct
                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-                                 
+
 #define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\
                                 ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
                                 ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
                                 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
                                 ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
                                 ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
-                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) 
-                                
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
+
 #define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                           ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-                                          
+
 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
 
 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
-                                      
+
 /**
   * @}
-  */  
+  */
 
 /* Include PWR HAL Extended module */
 #include "stm32l4xx_hal_pwr_ex.h"
@@ -360,11 +362,11 @@ typedef struct
 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
   * @{
   */
-  
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
-  
+
 /* Initialization and de-initialization functions *******************************/
 void HAL_PWR_DeInit(void);
 void HAL_PWR_EnableBkUpAccess(void);
@@ -374,7 +376,7 @@ void HAL_PWR_DisableBkUpAccess(void);
   * @}
   */
 
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
   * @{
   */
 
@@ -404,10 +406,10 @@ void HAL_PWR_PVDCallback(void);
 /**
   * @}
   */
-  
+
 /**
   * @}
-  */  
+  */
 
 /**
   * @}
@@ -416,7 +418,7 @@ void HAL_PWR_PVDCallback(void);
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
 #endif

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_pwr_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of PWR HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -67,11 +67,13 @@
   */
 typedef struct
 {
-  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold. 
-                           This parameter can be a value of @ref PWREx_PVM_Type. 
-                           @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 
-                           @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 
-                           @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 
+  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.
+                           This parameter can be a value of @ref PWREx_PVM_Type.
+                           @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
+@if STM32L486xx
+                           @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
+@endif
+                           @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
                            @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
 
   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
@@ -80,7 +82,7 @@ typedef struct
 
 /**
   * @}
-  */ 
+  */
 
 /* Exported constants --------------------------------------------------------*/
 
@@ -94,12 +96,12 @@ typedef struct
 #define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polariry */
 /**
   * @}
-  */  
+  */
 
 
 /** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
   * @{
-  */                                                      
+  */
 #define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
 #define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
 #define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
@@ -122,16 +124,18 @@ typedef struct
 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
   * @{
   */
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#if defined(PWR_CR2_PVME1)
 #define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
 #define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
+#endif /* PWR_CR2_PVME2 */
 #define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
 #define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */
 /**
   * @}
-  */  
-  
+  */
+
 /** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
   * @{
   */
@@ -145,8 +149,8 @@ typedef struct
 /**
   * @}
   */
-  
-  
+
+
 
 /** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
   * @{
@@ -157,7 +161,7 @@ typedef struct
   * @}
   */
 
-  
+
 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
   * @{
   */
@@ -166,7 +170,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
   * @{
   */
@@ -174,8 +178,8 @@ typedef struct
 #define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
   * @{
   */
@@ -197,49 +201,64 @@ typedef struct
 #define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup PWREx_GPIO GPIO port
   * @{
   */
 #define PWR_GPIO_A   0x00000000      /*!< GPIO port A */
 #define PWR_GPIO_B   0x00000001      /*!< GPIO port B */
 #define PWR_GPIO_C   0x00000002      /*!< GPIO port C */
+#if defined(GPIOD_BASE)
 #define PWR_GPIO_D   0x00000003      /*!< GPIO port D */
+#endif
+#if defined(GPIOE_BASE)
 #define PWR_GPIO_E   0x00000004      /*!< GPIO port E */
+#endif
+#if defined(GPIOF_BASE)
 #define PWR_GPIO_F   0x00000005      /*!< GPIO port F */
+#endif
+#if defined(GPIOG_BASE)
 #define PWR_GPIO_G   0x00000006      /*!< GPIO port G */
+#endif
 #define PWR_GPIO_H   0x00000007      /*!< GPIO port H */
+#if defined(GPIOI_BASE)
+#define PWR_GPIO_I   0x00000008      /*!< GPIO port I */
+#endif
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
   * @{
-  */    
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+  */
+#if defined(PWR_CR2_PVME1)
 #define PWR_EXTI_LINE_PVM1  ((uint32_t)0x00000008)  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
 #define PWR_EXTI_LINE_PVM2  ((uint32_t)0x00000010)  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */
+#endif /* PWR_CR2_PVME2 */
 #define PWR_EXTI_LINE_PVM3  ((uint32_t)0x00000020)  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */
-#define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */ 
+#define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
   * @{
-  */    
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+  */
+#if defined(PWR_CR2_PVME1)
 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)  /*!< Event line 35 Connected to the PVM1 EXTI Line */
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)  /*!< Event line 36 Connected to the PVM2 EXTI Line */
+#endif /* PWR_CR2_PVME2 */
 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)  /*!< Event line 37 Connected to the PVM3 EXTI Line */
-#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */ 
+#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup PWREx_Flag  PWR Status Flags
   *        Elements values convention: 0000 0000 0XXY YYYYb
   *           - Y YYYY  : Flag position in the XX register (5 bits)
@@ -247,9 +266,9 @@ typedef struct
   *                 - 01: SR1 register
   *                 - 10: SR2 register
   *        The only exception is PWR_FLAG_WU, encompassing all
-  *        wake-up flags and set to PWR_SR1_WUF.    
-  * @{   
-  */  
+  *        wake-up flags and set to PWR_SR1_WUF.
+  * @{
+  */
 #define PWR_FLAG_WUF1                       ((uint32_t)0x0020)   /*!< Wakeup event on wakeup pin 1 */
 #define PWR_FLAG_WUF2                       ((uint32_t)0x0021)   /*!< Wakeup event on wakeup pin 2 */
 #define PWR_FLAG_WUF3                       ((uint32_t)0x0022)   /*!< Wakeup event on wakeup pin 3 */
@@ -263,26 +282,28 @@ typedef struct
 #define PWR_FLAG_REGLPF                     ((uint32_t)0x0049)   /*!< Low-power regulator flag */
 #define PWR_FLAG_VOSF                       ((uint32_t)0x004A)   /*!< Voltage scaling flag */
 #define PWR_FLAG_PVDO                       ((uint32_t)0x004B)   /*!< Power Voltage Detector output flag */
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#if defined(PWR_CR2_PVME1)
 #define PWR_FLAG_PVMO1                      ((uint32_t)0x004C)   /*!< Power Voltage Monitoring 1 output flag */
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
 #define PWR_FLAG_PVMO2                      ((uint32_t)0x004D)   /*!< Power Voltage Monitoring 2 output flag */
+#endif /* PWR_CR2_PVME2 */
 #define PWR_FLAG_PVMO3                      ((uint32_t)0x004E)   /*!< Power Voltage Monitoring 3 output flag */
 #define PWR_FLAG_PVMO4                      ((uint32_t)0x004F)   /*!< Power Voltage Monitoring 4 output flag */
 /**
   * @}
-  */        
+  */
 
 /**
   * @}
-  */  
+  */
 
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
  * @{
  */
 
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#if defined(PWR_CR2_PVME1)
 /**
   * @brief Enable the PVM1 Extended Interrupt Line.
   * @retval None
@@ -371,9 +392,10 @@ typedef struct
   */
 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
 
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#endif /* PWR_CR2_PVME1 */
 
 
+#if defined(PWR_CR2_PVME2)
 /**
   * @brief Enable the PVM2 Extended Interrupt Line.
   * @retval None
@@ -433,7 +455,7 @@ typedef struct
     __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
     __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
   } while(0)
-  
+
 /**
   * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
   * @retval None
@@ -462,6 +484,7 @@ typedef struct
   */
 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
 
+#endif /* PWR_CR2_PVME2 */
 
 
 /**
@@ -523,7 +546,7 @@ typedef struct
     __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
     __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
   } while(0)
-  
+
 /**
   * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
   * @retval None
@@ -614,7 +637,7 @@ typedef struct
     __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
     __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
   } while(0)
-  
+
 /**
   * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
   * @retval None
@@ -650,14 +673,14 @@ typedef struct
   *         a tradeoff between performance and power consumption.
   *          This parameter can be one of the following values:
   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
-  *                                                typical output voltage at 1.2 V,  
+  *                                                typical output voltage at 1.2 V,
   *                                                system frequency up to 80 MHz.
   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
-  *                                                typical output voltage at 1.0 V,                
-  *                                                system frequency up to 26 MHz.  
+  *                                                typical output voltage at 1.0 V,
+  *                                                system frequency up to 26 MHz.
   * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
   *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
-  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.   
+  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
   * @retval None
   */
 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
@@ -671,7 +694,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 /* Private macros --------------------------------------------------------*/
 /** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
   * @{
@@ -692,8 +715,9 @@ typedef struct
                                 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
                                 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
                                 ((PIN) == PWR_WAKEUP_PIN5_LOW))
-                                
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
                                ((TYPE) == PWR_PVM_2) ||\
                                ((TYPE) == PWR_PVM_3) ||\
@@ -704,26 +728,49 @@ typedef struct
                                ((TYPE) == PWR_PVM_4))
 #endif
 
+#if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
+                               ((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+#endif
+
 #define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
                                 ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
                                 ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
                                 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
                                 ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
-                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))  
-                                
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
+
 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                              ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
-                                             
+
 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
-                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))  
-                                                  
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+
 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
-                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 
-                                           
+                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
+
 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
-                                           
-                             
+
+
+#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_D) ||\
+                           ((GPIO) == PWR_GPIO_E) ||\
+                           ((GPIO) == PWR_GPIO_H))
+#elif defined (STM32L432xx) || defined (STM32L442xx)
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_H))
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
                            ((GPIO) == PWR_GPIO_B) ||\
                            ((GPIO) == PWR_GPIO_C) ||\
@@ -732,18 +779,29 @@ typedef struct
                            ((GPIO) == PWR_GPIO_F) ||\
                            ((GPIO) == PWR_GPIO_G) ||\
                            ((GPIO) == PWR_GPIO_H))
+#elif defined (STM32L496xx) || defined (STM32L4A6xx)
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_D) ||\
+                           ((GPIO) == PWR_GPIO_E) ||\
+                           ((GPIO) == PWR_GPIO_F) ||\
+                           ((GPIO) == PWR_GPIO_G) ||\
+                           ((GPIO) == PWR_GPIO_H) ||\
+                           ((GPIO) == PWR_GPIO_I))
+#endif
 
 
 /**
   * @}
-  */  
-  
+  */
+
 
 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
   * @{
   */
-  
-/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
   * @{
   */
 
@@ -753,12 +811,14 @@ uint32_t HAL_PWREx_GetVoltageRange(void);
 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
 void HAL_PWREx_DisableBatteryCharging(void);
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#if defined(PWR_CR2_USV)
 void HAL_PWREx_EnableVddUSB(void);
 void HAL_PWREx_DisableVddUSB(void);
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#endif /* PWR_CR2_USV */
+#if defined(PWR_CR2_IOSV)
 void HAL_PWREx_EnableVddIO2(void);
 void HAL_PWREx_DisableVddIO2(void);
+#endif /* PWR_CR2_IOSV */
 void HAL_PWREx_EnableInternalWakeUpLine(void);
 void HAL_PWREx_DisableInternalWakeUpLine(void);
 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
@@ -769,12 +829,14 @@ void HAL_PWREx_EnablePullUpPullDownConfig(void);
 void HAL_PWREx_DisablePullUpPullDownConfig(void);
 void HAL_PWREx_EnableSRAM2ContentRetention(void);
 void HAL_PWREx_DisableSRAM2ContentRetention(void);
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#if defined(PWR_CR2_PVME1)
 void HAL_PWREx_EnablePVM1(void);
 void HAL_PWREx_DisablePVM1(void);
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
 void HAL_PWREx_EnablePVM2(void);
 void HAL_PWREx_DisablePVM2(void);
+#endif /* PWR_CR2_PVME2 */
 void HAL_PWREx_EnablePVM3(void);
 void HAL_PWREx_DisablePVM3(void);
 void HAL_PWREx_EnablePVM4(void);
@@ -791,14 +853,15 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
 void HAL_PWREx_EnterSHUTDOWNMode(void);
 
 void HAL_PWREx_PVD_PVM_IRQHandler(void);
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#if defined(PWR_CR2_PVME1)
 void HAL_PWREx_PVM1Callback(void);
-#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#endif /* PWR_CR2_PVME1 */
+#if defined(PWR_CR2_PVME2)
 void HAL_PWREx_PVM2Callback(void);
+#endif /* PWR_CR2_PVME2 */
 void HAL_PWREx_PVM3Callback(void);
 void HAL_PWREx_PVM4Callback(void);
 
-
 /**
   * @}
   */

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_qspi.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of QSPI HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
-  ******************************************************************************  
+  ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
@@ -52,74 +52,83 @@
 
 /** @addtogroup QSPI
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup QSPI_Exported_Types QSPI Exported Types
   * @{
   */
 
-/** 
-  * @brief  QSPI Init structure definition  
+/**
+  * @brief  QSPI Init structure definition
   */
 typedef struct
 {
   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
-                                  This parameter can be a number between 0 and 255 */ 
+                                  This parameter can be a number between 0 and 255 */
   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
                                   This parameter can be a value between 1 and 16 */
-  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 
+  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
                                   This parameter can be a value of @ref QSPI_SampleShifting */
-  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 
-                                  required to address the flash memory. The flash capacity can be up to 4GB 
-                                  (addressed using 32 bits) in indirect mode, but the addressable space in 
+  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+                                  required to address the flash memory. The flash capacity can be up to 4GB
+                                  (addressed using 32 bits) in indirect mode, but the addressable space in
                                   memory-mapped mode is limited to 256MB
                                   This parameter can be a number between 0 and 31 */
-  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 
+  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
                                   of clock cycles which the chip select must remain high between commands.
-                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */   
+                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */
   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
                                   This parameter can be a value of @ref QSPI_ClockMode */
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+  uint32_t FlashID;            /* Specifies the Flash which will be used,
+                                  This parameter can be a value of @ref QSPI_Flash_Select */
+  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
+                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */
+#endif
 }QSPI_InitTypeDef;
 
-/** 
-  * @brief HAL QSPI State structures definition  
-  */ 
+/**
+  * @brief HAL QSPI State structures definition
+  */
 typedef enum
 {
   HAL_QSPI_STATE_RESET             = 0x00,    /*!< Peripheral not initialized                            */
   HAL_QSPI_STATE_READY             = 0x01,    /*!< Peripheral initialized and ready for use              */
-  HAL_QSPI_STATE_BUSY              = 0x02,    /*!< Peripheral in indirect mode and busy                  */ 
-  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12,    /*!< Peripheral in indirect mode with transmission ongoing */ 
+  HAL_QSPI_STATE_BUSY              = 0x02,    /*!< Peripheral in indirect mode and busy                  */
+  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12,    /*!< Peripheral in indirect mode with transmission ongoing */
   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22,    /*!< Peripheral in indirect mode with reception ongoing    */
   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42,    /*!< Peripheral in auto polling mode ongoing               */
   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82,    /*!< Peripheral in memory mapped mode ongoing              */
+  HAL_QSPI_STATE_ABORT             = 0x08,    /*!< Peripheral with abort request ongoing                 */
   HAL_QSPI_STATE_ERROR             = 0x04     /*!< Peripheral in error                                   */
 }HAL_QSPI_StateTypeDef;
 
-/** 
-  * @brief  QSPI Handle Structure definition  
-  */  
+/**
+  * @brief  QSPI Handle Structure definition
+  */
 typedef struct
 {
   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
-  __IO uint16_t              TxXferSize;       /* QSPI Tx Transfer size              */
-  __IO uint16_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
+  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
+  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
-  __IO uint16_t              RxXferSize;       /* QSPI Rx Transfer size              */
-  __IO uint16_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
+  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
+  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
   DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
-  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */ 
+  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
 }QSPI_HandleTypeDef;
 
-/** 
-  * @brief  QSPI Command structure definition  
+/**
+  * @brief  QSPI Command structure definition
   */
 typedef struct
 {
@@ -143,26 +152,26 @@ typedef struct
                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
                                   This parameter can be a value of @ref QSPI_DataMode */
-  uint32_t NbData;             /* Specifies the number of data to transfer. 
-                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 
+  uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
+                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
                                   until end of memory)*/
   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
                                   This parameter can be a value of @ref QSPI_DdrMode */
-  uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of 
+  uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of
                                   system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
                                   This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
   uint32_t SIOOMode;           /* Specifies the send instruction only once mode
                                   This parameter can be a value of @ref QSPI_SIOOMode */
 }QSPI_CommandTypeDef;
 
-/** 
-  * @brief  QSPI Auto Polling mode configuration structure definition  
+/**
+  * @brief  QSPI Auto Polling mode configuration structure definition
   */
 typedef struct
 {
   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
                                   This parameter can be any value between 0 and 0xFFFFFFFF */
-  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received. 
+  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
                                   This parameter can be any value between 0 and 0xFFFFFFFF */
   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
                                   This parameter can be any value between 0 and 0xFFFF */
@@ -173,15 +182,15 @@ typedef struct
   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
                                   This parameter can be a value of @ref QSPI_AutomaticStop */
 }QSPI_AutoPollingTypeDef;
-                           
-/** 
-  * @brief  QSPI Memory Mapped mode configuration structure definition  
+
+/**
+  * @brief  QSPI Memory Mapped mode configuration structure definition
   */
 typedef struct
 {
   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
                                   This parameter can be any value between 0 and 0xFFFF */
-  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select. 
+  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
 }QSPI_MemoryMappedTypeDef;
 
@@ -196,14 +205,15 @@ typedef struct
 
 /** @defgroup QSPI_ErrorCode QSPI Error Code
   * @{
-  */ 
-#define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000) /*!< No error           */
-#define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001) /*!< Timeout error      */
-#define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002) /*!< Transfer error     */
-#define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004) /*!< DMA transfer error */
+  */
+#define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000) /*!< No error                 */
+#define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001) /*!< Timeout error            */
+#define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002) /*!< Transfer error           */
+#define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004) /*!< DMA transfer error       */
+#define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008) /*!< Invalid parameters error */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
   * @{
@@ -212,7 +222,7 @@ typedef struct
 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
   * @{
@@ -238,6 +248,28 @@ typedef struct
   * @}
   */
 
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+/** @defgroup QSPI_Flash_Select QSPI Flash Select
+  * @{
+  */
+#define QSPI_FLASH_ID_1                ((uint32_t)0x00000000)      /*!<FLASH 1 selected*/
+#define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
+/**
+  * @}
+  */
+
+  /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+  * @{
+  */
+#define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
+#define QSPI_DUALFLASH_DISABLE         ((uint32_t)0x00000000)     /*!<Dual-flash mode disabled*/
+/**
+  * @}
+  */
+#endif
+
 /** @defgroup QSPI_AddressSize QSPI Address Size
   * @{
   */
@@ -247,7 +279,7 @@ typedef struct
 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
 /**
   * @}
-  */  
+  */
 
 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
   * @{
@@ -280,7 +312,7 @@ typedef struct
 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
 /**
   * @}
-  */  
+  */
 
 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
 * @{
@@ -291,7 +323,7 @@ typedef struct
 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
 /**
   * @}
-  */  
+  */
 
 /** @defgroup QSPI_DataMode QSPI Data Mode
   * @{
@@ -302,7 +334,7 @@ typedef struct
 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
 /**
   * @}
-  */  
+  */
 
 /** @defgroup QSPI_DdrMode QSPI DDR Mode
   * @{
@@ -317,6 +349,11 @@ typedef struct
   * @{
   */
 #define QSPI_DDR_HHC_ANALOG_DELAY      ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
+#endif
 /**
   * @}
   */
@@ -337,7 +374,7 @@ typedef struct
 #define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
 /**
   * @}
-  */  
+  */
 
 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
   * @{
@@ -346,7 +383,7 @@ typedef struct
 #define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
 /**
   * @}
-  */  
+  */
 
 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
   * @{
@@ -355,7 +392,7 @@ typedef struct
 #define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
 /**
   * @}
-  */  
+  */
 
 /** @defgroup QSPI_Flags QSPI Flags
   * @{
@@ -372,7 +409,7 @@ typedef struct
 
 /** @defgroup QSPI_Interrupts QSPI Interrupts
   * @{
-  */  
+  */
 #define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
 #define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
 #define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
@@ -385,11 +422,11 @@ typedef struct
 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
   * @brief QSPI Timeout definition
   * @{
-  */ 
+  */
 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
 /**
   * @}
-  */  
+  */
 
 /**
   * @}
@@ -408,7 +445,7 @@ typedef struct
 /** @brief  Enable the QSPI peripheral.
   * @param  __HANDLE__: specifies the QSPI Handle.
   * @retval None
-  */ 
+  */
 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
 
 /** @brief  Disable the QSPI peripheral.
@@ -455,7 +492,7 @@ typedef struct
   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
   */
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Check whether the selected QSPI flag is set or not.
@@ -487,7 +524,7 @@ typedef struct
   * @}
   */
 
-/* Exported functions --------------------------------------------------------*/  
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup QSPI_Exported_Functions
   * @{
   */
@@ -520,6 +557,7 @@ HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_Comm
 
 /* Callback functions in non-blocking modes ***********************************/
 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
 
 /* QSPI indirect mode */
@@ -536,14 +574,17 @@ void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
 
 /* Peripheral Control and State functions  ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState  (QSPI_HandleTypeDef *hqspi);
-uint32_t              HAL_QSPI_GetError  (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef     HAL_QSPI_Abort     (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
+uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
+uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
 /**
   * @}
   */
-/* End of exported functions -------------------------------------------------*/  
+/* End of exported functions -------------------------------------------------*/
 
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup QSPI_Private_Macros QSPI Private Macros
@@ -570,7 +611,17 @@ void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Ti
 #define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))
 
-#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFF) 
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define IS_QSPI_FLASH_ID(FLASH)            (((FLASH) == QSPI_FLASH_ID_1) || \
+                                            ((FLASH) == QSPI_FLASH_ID_2))
+
+#define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+                                            ((MODE) == QSPI_DUALFLASH_DISABLE))
+#endif
+
+#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFF)
 
 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
@@ -582,7 +633,7 @@ void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Ti
                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
 
-#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31) 
+#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31)
 
 #define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
@@ -607,38 +658,45 @@ void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Ti
 #define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
 
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
+    defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+#else
 #define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
+#endif
 
 #define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
 
-#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 
+#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
 
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1) && ((SIZE) <= 4)) 
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1) && ((SIZE) <= 4))
 
 #define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
-                                            ((MODE) == QSPI_MATCH_MODE_OR)) 
+                                            ((MODE) == QSPI_MATCH_MODE_OR))
 
 #define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
-                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 
+                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
 
 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
-                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 
+                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
 
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFF) 
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFF)
 /**
 * @}
-*/ 
+*/
 /* End of private macros -----------------------------------------------------*/
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
-  
+  */
+
 #ifdef __cplusplus
 }
 #endif

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_rng.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of RNG HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L4xx_HAL_RNG_H
@@ -52,42 +52,42 @@
 
 /** @addtogroup RNG
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup RNG_Exported_Types RNG Exported Types
   * @{
   */
 
-/** 
-  * @brief  RNG HAL State Structure definition  
-  */ 
+/**
+  * @brief  RNG HAL State Structure definition
+  */
 typedef enum
 {
   HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
   HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
-  HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */ 
+  HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */
   HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
   HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
-    
+
 }HAL_RNG_StateTypeDef;
 
-/** 
-  * @brief  RNG Handle Structure definition  
-  */ 
+/**
+  * @brief  RNG Handle Structure definition
+  */
 typedef struct
 {
-  RNG_TypeDef                 *Instance;  /*!< Register base address   */ 
-  
+  RNG_TypeDef                 *Instance;  /*!< Register base address   */
+
   HAL_LockTypeDef             Lock;       /*!< RNG locking object      */
-  
+
   __IO HAL_RNG_StateTypeDef   State;      /*!< RNG communication state */
-  
+
   uint32_t               RandomNumber;    /*!< Last Generated RNG Data */
-  
+
 }RNG_HandleTypeDef;
 
-/** 
+/**
   * @}
   */
 
@@ -108,7 +108,7 @@ typedef struct
 
 /** @defgroup RNG_Flag_definition  RNG Flags Definition
   * @{
-  */ 
+  */
 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
@@ -118,8 +118,8 @@ typedef struct
 
 /**
   * @}
-  */ 
-  
+  */
+
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup RNG_Exported_Macros RNG Exported Macros
   * @{
@@ -150,9 +150,9 @@ typedef struct
   * @param  __HANDLE__: RNG Handle
   * @param  __FLAG__: RNG flag
   *          This parameter can be one of the following values:
-  *            @arg RNG_FLAG_DRDY:  Data ready                
+  *            @arg RNG_FLAG_DRDY:  Data ready
   *            @arg RNG_FLAG_CECS:  Clock error current status
-  *            @arg RNG_FLAG_SECS:  Seed error current status 
+  *            @arg RNG_FLAG_SECS:  Seed error current status
   * @retval The new state of __FLAG__ (SET or RESET).
   */
 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
@@ -161,7 +161,7 @@ typedef struct
 /**
   * @brief  Clear the selected RNG flag status.
   * @param  __HANDLE__: RNG handle
-  * @param  __FLAG__: RNG flag to clear  
+  * @param  __FLAG__: RNG flag to clear
   * @note   WARNING: This is a dummy macro for HAL code alignment,
   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
   * @retval None
@@ -176,7 +176,7 @@ typedef struct
   * @retval None
   */
 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
-    
+
 /**
   * @brief  Disable the RNG interrupt.
   * @param  __HANDLE__: RNG Handle
@@ -189,28 +189,28 @@ typedef struct
   * @param  __HANDLE__: RNG Handle
   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
   *         This parameter can be one of the following values:
-  *            @arg RNG_IT_DRDY: Data ready interrupt              
+  *            @arg RNG_IT_DRDY: Data ready interrupt
   *            @arg RNG_IT_CEI: Clock error interrupt
   *            @arg RNG_IT_SEI: Seed error interrupt
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Clear the RNG interrupt status flags.
   * @param  __HANDLE__: RNG Handle
   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
-  *          This parameter can be one of the following values:            
+  *          This parameter can be one of the following values:
   *            @arg RNG_IT_CEI: Clock error interrupt
   *            @arg RNG_IT_SEI: Seed error interrupt
-  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          
+  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
   * @retval None
   */
 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
 
 /**
   * @}
-  */ 
+  */
 
 
 /* Exported functions --------------------------------------------------------*/
@@ -221,14 +221,14 @@ typedef struct
 /* Initialization and de-initialization functions  ******************************/
 /** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
-  */  
+  */
 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
 HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
 /**
   * @}
-  */ 
+  */
 
 /* Peripheral Control functions  ************************************************/
 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
@@ -246,7 +246,7 @@ void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
 /**
   * @}
-  */ 
+  */
 
 /* Peripheral State functions  **************************************************/
 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
@@ -256,7 +256,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
 /**
   * @}
   */
-  
+
 /**
   * @}
   */
@@ -270,11 +270,11 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_rtc.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of RTC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -58,8 +58,8 @@
 /** @defgroup RTC_Exported_Types RTC Exported Types
   * @{
   */
-/** 
-  * @brief  HAL State structures definition  
+/**
+  * @brief  HAL State structures definition
   */
 typedef enum
 {
@@ -71,7 +71,7 @@ typedef enum
 
 }HAL_RTCStateTypeDef;
 
-/** 
+/**
   * @brief  RTC Configuration Structure definition
   */
 typedef struct
@@ -81,7 +81,7 @@ typedef struct
 
   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-                               
+
   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
 
@@ -91,15 +91,15 @@ typedef struct
   uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
                                  This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
 
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
+  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
 
   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
 }RTC_InitTypeDef;
 
-/** 
-  * @brief  RTC Time structure definition  
+/**
+  * @brief  RTC Time structure definition
   */
 typedef struct
 {
@@ -115,26 +115,26 @@ typedef struct
 
   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
-  
+
   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
                                  This parameter corresponds to a time unit range between [0-1] Second
                                  with [1 Sec / SecondFraction +1] granularity */
- 
+
   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
                                  This parameter corresponds to a time unit range between [0-1] Second
                                  with [1 Sec / SecondFraction +1] granularity.
                                  This field will be used only by HAL_RTC_GetTime function */
-  
+
   uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
 
-  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
+  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
                                  in CR register to store the operation.
                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
 }RTC_TimeTypeDef;
 
-/** 
+/**
   * @brief  RTC Date structure definition
   */
 typedef struct
@@ -153,7 +153,7 @@ typedef struct
 
 }RTC_DateTypeDef;
 
-/** 
+/**
   * @brief  RTC Alarm structure definition
   */
 typedef struct
@@ -162,7 +162,7 @@ typedef struct
 
   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-  
+
   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
 
@@ -177,7 +177,7 @@ typedef struct
                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
 }RTC_AlarmTypeDef;
 
-/** 
+/**
   * @brief  Time Handle Structure definition
   */
 typedef struct
@@ -578,31 +578,31 @@ typedef struct
 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None
   */
 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
 
 /**
-  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None
   */
 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
   * @retval None
   */
 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
 
 /**
-  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
   * @retval None
   */
 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None
   */
 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
@@ -611,7 +611,7 @@ typedef struct
                                                            } while(0)
 
 /**
-  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None
   */
 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
@@ -711,7 +711,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/ 
+/* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup RTC_Private_Constants RTC Private Constants
@@ -719,12 +719,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
   */
 /* Masks Definition */
 #define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
-#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)  
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)
 #define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
 
 #define RTC_TIMEOUT_VALUE  1000
-  
+
 #define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the RTC Alarm event */
 
 /**
@@ -738,7 +738,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 
 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
   * @{
-  */ 
+  */
 
 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
                                         ((FORMAT) == RTC_HOURFORMAT_24))

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_rtc_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of RTC HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L4xx_HAL_RTC_EX_H
@@ -155,7 +155,7 @@ typedef struct
 
 /** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions
   * @{
-  */ 
+  */
 #define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
 #define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
 /**
@@ -317,9 +317,9 @@ typedef struct
   */
 #define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
                                                                     period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration 
+#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
                                                                     period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration 
+#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
                                                                     period is 8s, else 2exp18 RTCCLK seconds */
 /**
   * @}
@@ -437,8 +437,9 @@ typedef struct
   *            @arg RTC_FLAG_WUTF
   * @retval None
   */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
 
+#if defined(RTC_TAMPER1_SUPPORT)
 /**
   * @brief  Enable the RTC Tamper1 input detection.
   * @param  __HANDLE__: specifies the RTC handle.
@@ -452,6 +453,7 @@ typedef struct
   * @retval None
   */
 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
+#endif /* RTC_TAMPER1_SUPPORT */
 
 /**
   * @brief  Enable the RTC Tamper2 input detection.
@@ -467,6 +469,7 @@ typedef struct
   */
 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
 
+#if defined(RTC_TAMPER3_SUPPORT)
 /**
   * @brief  Enable the RTC Tamper3 input detection.
   * @param  __HANDLE__: specifies the RTC handle.
@@ -480,6 +483,7 @@ typedef struct
   * @retval None
   */
 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
+#endif /* RTC_TAMPER3_SUPPORT */
 
 /**
   * @brief  Enable the RTC Tamper interrupt.
@@ -491,13 +495,13 @@ typedef struct
   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
   * @retval None
-  */   
+  */
 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the RTC Tamper interrupt.
   * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. 
+  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
   *         This parameter can be any combination of the following values:
   *            @arg  RTC_IT_TAMP: All tampers interrupts
   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
@@ -517,9 +521,13 @@ typedef struct
   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
   * @retval None
   */
+#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
                                                                       ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
                                                                       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
+#else
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET)
+#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
 
 /**
   * @brief  Check whether the specified RTC Tamper interrupt is enabled or not.
@@ -585,7 +593,7 @@ typedef struct
 /**
   * @brief  Disable the RTC TimeStamp interrupt.
   * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. 
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -731,7 +739,7 @@ typedef struct
 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. 
+  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
@@ -816,7 +824,7 @@ typedef struct
 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. 
+  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
   * @retval None
   */
 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
@@ -959,7 +967,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
 /** @addtogroup RTCEx_Exported_Functions_Group4
   * @{
   */
-void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); 
+void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
 /**
   * @}
@@ -969,7 +977,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/ 
+/* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
@@ -989,7 +997,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
 
 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
   * @{
-  */ 
+  */
 
 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
                                ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
@@ -1010,7 +1018,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
 #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
                                         ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
                                         ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) 
+                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
 
 #define IS_RTC_TAMPER_ERASE_MODE(MODE)             (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
                                                     ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h

@@ -0,0 +1,849 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sai.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SAI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SAI_H
+#define __STM32L4xx_HAL_SAI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SAI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Types SAI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */
+  HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */
+  HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */
+  HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
+  HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */
+}HAL_SAI_StateTypeDef;
+
+/**
+  * @brief  SAI Callback prototype
+  */
+typedef void (*SAIcallback)(void);
+
+/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
+  * @brief  SAI Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
+                                     This parameter can be a value of @ref SAI_Block_Mode */
+
+  uint32_t Synchro;             /*!< Specifies SAI Block synchronization
+                                     This parameter can be a value of @ref SAI_Block_Synchronization */
+
+  uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
+                                     for BlockA and BlockB
+                                     This parameter can be a value of @ref SAI_Block_SyncExt
+                                     @note: If both audio blocks of same SAI are used, this parameter has
+                                            to be set to the same value for each audio block */
+
+  uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
+                                     This parameter can be a value of @ref SAI_Block_Output_Drive
+                                     @note this value has to be set before enabling the audio block
+                                     but after the audio block configuration. */
+
+  uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
+                                     This parameter can be a value of @ref SAI_Block_NoDivider
+                                     @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+                                              should be aligned to a number equal to a power of 2, from 8 to 256.
+                                              If bit NODIV in the SAI_xCR1 register is set, the frame length can
+                                              take any of the values without constraint since the input clock of
+                                              the audio block should be equal to the bit clock.
+                                              There is no MCLK_x clock which can be output. */
+
+  uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
+                                     This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
+                                     This parameter can be a value of @ref SAI_Audio_Frequency */
+
+  uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for
+                                     AudioFrequency the user choice
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
+
+  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
+                                     This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
+
+  uint32_t CompandingMode;      /*!< Specifies the companding mode type.
+                                     This parameter can be a value of @ref SAI_Block_Companding_Mode */
+
+  uint32_t TriState;            /*!< Specifies the companding mode type.
+                                     This parameter can be a value of @ref SAI_TRIState_Management */
+
+  /* This part of the structure is automatically filled if your are using the high level initialisation
+     function HAL_SAI_InitProtocol */
+
+  uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
+                                 This parameter can be a value of @ref SAI_Block_Protocol */
+
+  uint32_t DataSize;        /*!< Specifies the SAI Block data size.
+                                 This parameter can be a value of @ref SAI_Block_Data_Size */
+
+  uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+
+  uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
+                                 This parameter can be a value of @ref SAI_Block_Clock_Strobing */
+}SAI_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
+  * @brief  SAI Frame Init structure definition
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+                                    This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+                                    @note: If master clock MCLK_x pin is declared as an output, the frame length
+                                           should be aligned to a number equal to power of 2 in order to keep
+                                           in an audio frame, an integer number of MCLK pulses by bit Clock. */
+
+  uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
+                                    This Parameter specifies the length in number of bit clock (SCK + 1)
+                                    of the active level of FS signal in audio frame.
+                                    This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+  uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
+                                    This parameter can be a value of @ref SAI_Block_FS_Definition */
+
+  uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
+                                    This parameter can be a value of @ref SAI_Block_FS_Polarity */
+
+  uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
+                                    This parameter can be a value of @ref SAI_Block_FS_Offset */
+
+}SAI_FrameInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
+  * @brief   SAI Block Slot Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+  uint32_t SlotSize;        /*!< Specifies the Slot Size.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Size */
+
+  uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+  uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Active */
+}SAI_SlotInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
+  * @brief  SAI handle Structure definition
+  * @{
+  */
+typedef struct __SAI_HandleTypeDef
+{
+  SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */
+
+  SAI_InitTypeDef           Init;         /*!< SAI communication parameters */
+
+  SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */
+
+  SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */
+
+  uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */
+
+  uint16_t                  XferSize;     /*!< SAI transfer size */
+
+  uint16_t                  XferCount;    /*!< SAI transfer counter */
+
+  DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */
+
+  DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */
+
+  SAIcallback               mutecallback; /*!< SAI mute callback */
+
+  void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
+
+  HAL_LockTypeDef           Lock;         /*!< SAI locking object */
+
+  __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */
+
+  __IO uint32_t             ErrorCode;    /*!< SAI Error code */
+}SAI_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Constants SAI Exported Constants
+  * @{
+  */
+
+/** @defgroup SAI_Error_Code SAI Error Code
+  * @{
+  */
+#define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000U)  /*!< No error */
+#define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001U)  /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002U)  /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004U)  /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008U)  /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error */
+#define HAL_SAI_ERROR_DMA     ((uint32_t)0x00000080U)  /*!< DMA error */
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
+  * @{
+  */
+#define SAI_SYNCEXT_DISABLE          0
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Protocol SAI Supported protocol
+  * @{
+  */
+#define SAI_I2S_STANDARD      0
+#define SAI_I2S_MSBJUSTIFIED  1
+#define SAI_I2S_LSBJUSTIFIED  2
+#define SAI_PCM_LONG          3
+#define SAI_PCM_SHORT         4
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size
+  * @{
+  */
+#define SAI_PROTOCOL_DATASIZE_16BIT         0
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
+#define SAI_PROTOCOL_DATASIZE_24BIT         2
+#define SAI_PROTOCOL_DATASIZE_32BIT         3
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
+  * @{
+  */
+#define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000U)
+#define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000U)
+#define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000U)
+#define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100U)
+#define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000U)
+#define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050U)
+#define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000U)
+#define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025U)
+#define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000U)
+#define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0U)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mode SAI Block Mode
+  * @{
+  */
+#define SAI_MODEMASTER_TX         ((uint32_t)0x00000000U)
+#define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)
+#define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)
+#define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Protocol SAI Block Protocol
+  * @{
+  */
+#define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000U)
+#define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)
+#define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Data_Size SAI Block Data Size
+  * @{
+  */
+#define SAI_DATASIZE_8     ((uint32_t)SAI_xCR1_DS_1)
+#define SAI_DATASIZE_10    ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_16    ((uint32_t)SAI_xCR1_DS_2)
+#define SAI_DATASIZE_20    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_24    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
+#define SAI_DATASIZE_32    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
+  * @{
+  */
+#define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)
+#define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
+  * @{
+  */
+#define SAI_CLOCKSTROBING_FALLINGEDGE     0
+#define SAI_CLOCKSTROBING_RISINGEDGE      1
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
+  * @{
+  */
+#define SAI_ASYNCHRONOUS                  0 /*!< Asynchronous */
+#define SAI_SYNCHRONOUS                   1 /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1          2 /*!< Synchronous with other SAI, SAI1 */
+#define SAI_SYNCHRONOUS_EXT_SAI2          3 /*!< Synchronous with other SAI, SAI2 */
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000U)
+#define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
+  * @{
+  */
+#define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000U)
+#define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)
+/**
+  * @}
+  */
+
+
+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
+  * @{
+  */
+#define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000U)
+#define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
+  * @{
+  */
+#define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)
+#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
+  * @{
+  */
+#define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000U)
+#define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
+/**
+  * @}
+  */
+
+
+  /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
+  * @{
+  */
+#define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000U)
+#define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
+#define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
+  * @{
+  */
+#define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000U)
+#define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001U)
+#define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002U)
+#define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004U)
+#define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008U)
+#define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010U)
+#define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020U)
+#define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040U)
+#define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080U)
+#define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100U)
+#define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200U)
+#define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400U)
+#define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800U)
+#define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000U)
+#define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000U)
+#define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000U)
+#define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000U)
+#define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFFU)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
+  * @{
+  */
+#define SAI_STEREOMODE               ((uint32_t)0x00000000U)
+#define SAI_MONOMODE                 ((uint32_t)SAI_xCR1_MONO)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_TRIState_Management SAI TRIState Management
+  * @{
+  */
+#define SAI_OUTPUT_NOTRELEASED    ((uint32_t)0x00000000U)
+#define SAI_OUTPUT_RELEASED       ((uint32_t)SAI_xCR2_TRIS)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
+  * @{
+  */
+#define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)
+#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))
+#define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
+  * @{
+  */
+#define SAI_NOCOMPANDING                 ((uint32_t)0x00000000U)
+#define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))
+#define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
+#define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
+#define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
+  * @{
+  */
+#define SAI_ZERO_VALUE                     ((uint32_t)0x00000000U)
+#define SAI_LAST_SENT_VALUE                ((uint32_t)SAI_xCR2_MUTEVAL)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
+  * @{
+  */
+#define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
+#define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
+#define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
+#define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
+#define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
+#define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
+#define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
+  * @{
+  */
+#define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
+#define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
+#define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
+#define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
+#define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
+#define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
+#define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
+  * @{
+  */
+#define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000U)
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000U)
+#define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000U)
+#define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000U)
+#define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000U)
+#define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Macros SAI Exported Macros
+ *  @brief macros to handle interrupts and specific configurations
+ * @{
+ */
+
+/** @brief Reset SAI handle state.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @retval None
+  */
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+
+/** @brief  Enable or disable the specified SAI interrupts.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval None
+  */
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SAI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __INTERRUPT__: specifies the SAI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SAI flag is set or not.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+  *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
+  *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+  *            @arg SAI_FLAG_FREQ: FIFO request flag.
+  *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
+  *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+  *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified SAI pending flag.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
+  *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
+  *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
+  *            @arg SAI_FLAG_FREQ: Clear FIFO request
+  *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
+  *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+  *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+  *
+  * @retval None
+  */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
+
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
+
+ /**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SAI_Exported_Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+
+/** @addtogroup SAI_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+
+/** @addtogroup SAI_Exported_Functions_Group2
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* Abort function */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
+
+/* Mute management */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/** @addtogroup SAI_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SAI_Private_Macros
+  * @{
+  */
+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
+                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
+                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
+
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
+                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
+                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
+                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
+                                               ((PROTOCOL) == SAI_PCM_SHORT))
+
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
+
+#define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \
+                                  ((MODE) == SAI_MODEMASTER_RX) || \
+                                  ((MODE) == SAI_MODESLAVE_TX)  || \
+                                  ((MODE) == SAI_MODESLAVE_RX))
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
+                                         ((DATASIZE) == SAI_DATASIZE_10) || \
+                                         ((DATASIZE) == SAI_DATASIZE_16) || \
+                                         ((DATASIZE) == SAI_DATASIZE_20) || \
+                                         ((DATASIZE) == SAI_DATASIZE_24) || \
+                                         ((DATASIZE) == SAI_DATASIZE_32))
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+                                     ((BIT) == SAI_FIRSTBIT_LSB))
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
+                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
+                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
+
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
+                                           ((VALUE) == SAI_LAST_SENT_VALUE))
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
+                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+                                                 ((STATE) == SAI_OUTPUT_RELEASED))
+
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+                                       ((MODE) == SAI_STEREOMODE))
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
+
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
+                                      ((SIZE) == SAI_SLOTSIZE_32B))
+
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
+
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Functions SAI Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SAI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h

@@ -0,0 +1,395 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_smartcard_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SMARTCARD HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SMARTCARD_EX_H
+#define __STM32L4xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARDEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
+  * @{
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
+#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)    /*!< No advanced feature initialization                  */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)    /*!< TX pin active level inversion                       */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)    /*!< RX pin active level inversion                       */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)    /*!< Binary data inversion                               */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)    /*!< TX/RX pins swap                                     */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)    /*!< RX overrun disable                                  */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)    /*!< DMA disable on Reception Error                      */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)    /*!< Most significant bit sent/received first            */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION            ((uint32_t)0x00000100)    /*!< TX completion indication before of after guard time */
+#endif /* USART_TCBGT_SUPPORT */
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT      /*!< SMARTCARD transmission complete before guard time completion */
+#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_FLAG_REACK          USART_ISR_REACK      /*!< SMARTCARD receive enable acknowledge flag  */
+#define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK      /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY       /*!< SMARTCARD busy flag                        */
+#define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF       /*!< SMARTCARD end of block flag                */
+#define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF       /*!< SMARTCARD receiver timeout flag            */
+#define SMARTCARD_FLAG_TXE            USART_ISR_TXE        /*!< SMARTCARD transmit data register empty     */
+#define SMARTCARD_FLAG_TC             USART_ISR_TC         /*!< SMARTCARD transmission complete            */
+#define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE       /*!< SMARTCARD read data register not empty     */
+#define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE       /*!< SMARTCARD idle line detection              */
+#define SMARTCARD_FLAG_ORE            USART_ISR_ORE        /*!< SMARTCARD overrun error                    */
+#define SMARTCARD_FLAG_NE             USART_ISR_NE         /*!< SMARTCARD noise error                      */
+#define SMARTCARD_FLAG_FE             USART_ISR_FE         /*!< SMARTCARD frame error                      */
+#define SMARTCARD_FLAG_PE             USART_ISR_PE         /*!< SMARTCARD parity error                     */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5 bits)
+  *           - XX  : Interrupt source register (2 bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5 bits)
+  * @{
+  */
+#define SMARTCARD_IT_PE                     ((uint16_t)0x0028)        /*!< SMARTCARD parity error interruption                 */
+#define SMARTCARD_IT_TXE                    ((uint16_t)0x0727)        /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC                     ((uint16_t)0x0626)        /*!< SMARTCARD transmission complete interruption        */
+#define SMARTCARD_IT_RXNE                   ((uint16_t)0x0525)        /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE                   ((uint16_t)0x0424)        /*!< SMARTCARD idle line detection interruption          */
+
+#define SMARTCARD_IT_ERR                    ((uint16_t)0x0060)        /*!< SMARTCARD error interruption         */
+#define SMARTCARD_IT_ORE                    ((uint16_t)0x0300)        /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE                     ((uint16_t)0x0200)        /*!< SMARTCARD noise error interruption   */
+#define SMARTCARD_IT_FE                     ((uint16_t)0x0100)        /*!< SMARTCARD frame error interruption   */
+
+#define SMARTCARD_IT_EOB                    ((uint16_t)0x0C3B)        /*!< SMARTCARD end of block interruption     */
+#define SMARTCARD_IT_RTO                    ((uint16_t)0x0B3A)        /*!< SMARTCARD receiver timeout interruption */
+
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_IT_TCBGT                  ((uint16_t)0x1978)        /*!< SMARTCARD transmission complete before guard time completion interruption */
+#endif /* USART_TCBGT_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+  * @{
+  */
+#define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
+#define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
+#define SMARTCARD_CLEAR_NEF                 USART_ICR_NCF     /*!< SMARTCARD noise detected clear flag        */
+#define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
+#define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
+#define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
+#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
+#define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macros -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+  * @{
+  */
+
+/** @brief  Report the SMARTCARD clock source.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L432xx) || defined (STM32L442xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#else
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART3)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+       {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#endif /* STM32L432xx || STM32L442xx */
+
+/** @brief  Set the Transmission Completion flag
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
+  *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
+  *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
+  * @retval None
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
+  do {                                                                                                       \
+    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
+    {                                                                                                        \
+     (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
+    }                                                                                                        \
+    else                                                                                                     \
+    {                                                                                                        \
+      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
+    }                                                                                                        \
+  } while(0)
+#else
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)         \
+  do {                                                                \
+    (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+  } while(0)
+#endif
+
+/** @brief  Return the transmission completion flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
+  *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
+  *        reported.
+  * @retval Transmission completion flag
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
+  (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
+#else
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)    (SMARTCARD_FLAG_TC)
+#endif
+
+/**
+  * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+  * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag.
+  * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
+  */
+#if defined(USART_TCBGT_SUPPORT)
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
+                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))
+#else
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
+#endif
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Peripheral Control functions ***********************************************/
+void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SMARTCARD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h

@@ -0,0 +1,701 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_smbus.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SMBUS HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SMBUS_H
+#define __STM32L4xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMBUS
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+  * @{
+  */
+
+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
+  * @brief  SMBUS Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
+                                     This parameter calculated by referring to SMBUS initialization
+                                            section in Reference manual */
+  uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
+                                     This parameter can be a value of @ref SMBUS_Analog_Filter */
+
+  uint32_t OwnAddress1;            /*!< Specifies the first device own address.
+                                     This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+                                     This parameter can be a value of @ref SMBUS_addressing_mode */
+
+  uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
+                                     This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+  uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
+                                     This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+                                     This parameter can be a value of @ref SMBUS_own_address2_masks. */
+
+  uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
+                                     This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+
+  uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
+                                     This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+  uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
+                                     This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+  uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
+                                     This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+  uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
+                                                                        (Enable bits and different timeout values)
+                                     This parameter calculated by referring to SMBUS initialization
+                                         section in Reference manual */
+} SMBUS_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_definition HAL state definition
+  * @brief  HAL State definition
+  * @{
+  */
+#define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
+#define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
+#define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
+#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
+#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
+#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
+  * @brief  SMBUS Error Code definition
+  * @{
+  */
+#define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
+#define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
+#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
+#define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
+#define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
+#define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
+#define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
+#define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
+  * @brief  SMBUS handle Structure definition
+  * @{
+  */
+typedef struct
+{
+  I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
+
+  SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
+
+  uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
+
+  uint16_t                     XferSize;        /*!< SMBUS transfer size                */
+
+  __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
+
+  __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
+
+  __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
+
+  HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
+
+  __IO uint32_t                State;           /*!< SMBUS communication state          */
+
+  __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
+
+}SMBUS_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+  * @{
+  */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+  * @{
+  */
+#define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
+#define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+  * @{
+  */
+#define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
+#define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+  * @{
+  */
+
+#define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
+#define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
+  * @{
+  */
+
+#define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
+#define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
+#define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
+#define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
+#define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
+#define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
+#define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
+#define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+  * @{
+  */
+#define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
+#define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_nostretch_mode  SMBUS nostretch mode
+  * @{
+  */
+#define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
+#define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+  * @{
+  */
+#define SMBUS_PEC_DISABLE                       (0x00000000U)
+#define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+  * @{
+  */
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+  * @{
+  */
+
+#define  SMBUS_SOFTEND_MODE                     (0x00000000U)
+#define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
+#define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
+#define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
+  * @{
+  */
+
+#define  SMBUS_NO_STARTSTOP                     (0x00000000U)
+#define  SMBUS_GENERATE_STOP                    I2C_CR2_STOP
+#define  SMBUS_GENERATE_START_READ              (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  SMBUS_GENERATE_START_WRITE             I2C_CR2_START
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+  * @{
+  */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
+#define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
+#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
+#define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
+#define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+#define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
+#define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+  * @brief SMBUS Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
+#define SMBUS_IT_TCI                            I2C_CR1_TCIE
+#define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI                            I2C_CR1_RXIE
+#define SMBUS_IT_TXI                            I2C_CR1_TXIE
+#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+  * @brief Flag definition
+  *        Elements values convention: 0xXXXXYYYY
+  *           - XXXXXXXX  : Flag mask
+  * @{
+  */
+
+#define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
+#define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
+#define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
+#define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
+#define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
+#define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
+#define  SMBUS_FLAG_TC                          I2C_ISR_TC
+#define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
+#define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
+#define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
+#define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
+#define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
+#define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
+#define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
+#define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
+#define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SMBUS handle state.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+
+/** @brief  Enable the specified SMBUS interrupts.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified SMBUS interrupts.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SMBUS flag is set or not.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
+  *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
+  *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
+  *            @arg @ref SMBUS_FLAG_BERR    Bus error
+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
+  *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
+  *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define SMBUS_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+/** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
+  *            @arg @ref SMBUS_FLAG_BERR    Bus error
+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Enable the specified SMBUS peripheral.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Disable the specified SMBUS peripheral.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
+  * @{
+  */
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
+                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK07))
+
+#define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
+                                                          ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
+                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
+                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+
+#define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
+                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \
+                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \
+                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \
+                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+
+
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
+                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
+                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
+                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == SMBUS_FIRST_FRAME)                        || \
+                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
+                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
+                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
+                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
+                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
+                                                          IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
+                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
+#define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+
+#define SMBUS_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
+  * @{
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @{
+ */
+
+/* Peripheral State and Errors functions  **************************************************/
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32l4xx_hal_smbus.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_SMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h

@@ -1,14 +1,14 @@
- /**
+/**
   ******************************************************************************
   * @file    stm32l4xx_hal_spi.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -40,7 +40,7 @@
 #define __STM32L4xx_HAL_SPI_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -92,14 +92,14 @@ typedef struct
   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
 
-  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not .
+  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
                                      This parameter can be a value of @ref SPI_TI_mode */
 
   uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
                                      This parameter can be a value of @ref SPI_CRC_Calculation */
 
   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
 
   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
                                      CRC Length is only used with Data8 and Data16, not other data size
@@ -114,64 +114,64 @@ typedef struct
 } SPI_InitTypeDef;
 
 /**
-  * @brief  HAL State structures definition
+  * @brief  HAL SPI State structure definition
   */
 typedef enum
 {
-  HAL_SPI_STATE_RESET      = 0x00,    /*!< Peripheral not Initialized                         */
-  HAL_SPI_STATE_READY      = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_SPI_STATE_BUSY       = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_SPI_STATE_BUSY_TX    = 0x03,    /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x04,    /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x05,    /*!< Data Transmission and Reception process is ongoing*/
-  HAL_SPI_STATE_ERROR      = 0x06     /*!< SPI error state                                   */
-}HAL_SPI_StateTypeDef;
+  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
+  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
+  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
+  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
+  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
+  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
+} HAL_SPI_StateTypeDef;
 
 /**
   * @brief  SPI handle Structure definition
   */
 typedef struct __SPI_HandleTypeDef
 {
-  SPI_TypeDef             *Instance;      /* SPI registers base address     */
+  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
 
-  SPI_InitTypeDef         Init;           /* SPI communication parameters   */
+  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
 
-  uint8_t                 *pTxBuffPtr;    /* Pointer to SPI Tx transfer Buffer */
+  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
 
-  uint16_t                TxXferSize;     /* SPI Tx Transfer size */
+  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
 
-  uint16_t                TxXferCount;    /* SPI Tx Transfer Counter */
+  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
 
-  uint8_t                 *pRxBuffPtr;    /* Pointer to SPI Rx transfer Buffer */
+  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
 
-  uint16_t                RxXferSize;     /* SPI Rx Transfer size */
+  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
 
-  uint16_t                RxXferCount;    /* SPI Rx Transfer Counter */
+  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
 
-  uint32_t                CRCSize;        /* SPI CRC size used for the transfer */
+  uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
 
-  void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler   */
+  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
 
-  void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler   */
+  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
 
-  DMA_HandleTypeDef       *hdmatx;        /* SPI Tx DMA Handle parameters   */
+  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
 
-  DMA_HandleTypeDef       *hdmarx;        /* SPI Rx DMA Handle parameters   */
+  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
 
-  HAL_LockTypeDef         Lock;           /* Locking object                 */
+  HAL_LockTypeDef            Lock;           /*!< Locking object                           */
 
-  HAL_SPI_StateTypeDef    State;          /* SPI communication state        */
+  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
 
-  uint32_t                ErrorCode;      /* SPI Error code                 */
+  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
 
-}SPI_HandleTypeDef;
+} SPI_HandleTypeDef;
 
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-
 /** @defgroup SPI_Exported_Constants SPI Exported Constants
   * @{
   */
@@ -179,23 +179,22 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_Error_Code SPI Error Code
   * @{
   */
-#define HAL_SPI_ERROR_NONE   (uint32_t)0x00000000  /*!< No error                          */
-#define HAL_SPI_ERROR_MODF   (uint32_t)0x00000001  /*!< MODF error                        */
-#define HAL_SPI_ERROR_CRC    (uint32_t)0x00000002  /*!< CRC error                         */
-#define HAL_SPI_ERROR_OVR    (uint32_t)0x00000004  /*!< OVR error                         */
-#define HAL_SPI_ERROR_FRE    (uint32_t)0x00000008  /*!< FRE error                         */
-#define HAL_SPI_ERROR_DMA    (uint32_t)0x00000010  /*!< DMA transfer error                */
-#define HAL_SPI_ERROR_FLAG   (uint32_t)0x00000020  /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040  /*!< Unknown error                     */
+#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
+#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
+#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
+#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
+#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
+#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
+#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
 /**
   * @}
   */
 
-
 /** @defgroup SPI_Mode SPI Mode
   * @{
   */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
+#define SPI_MODE_SLAVE                  (0x00000000U)
 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 /**
   * @}
@@ -204,7 +203,7 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_Direction SPI Direction Mode
   * @{
   */
-#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES            (0x00000000U)
 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
 /**
@@ -214,19 +213,19 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_Data_Size SPI Data Size
   * @{
   */
-#define SPI_DATASIZE_4BIT               ((uint32_t)0x0300)
-#define SPI_DATASIZE_5BIT               ((uint32_t)0x0400)
-#define SPI_DATASIZE_6BIT               ((uint32_t)0x0500)
-#define SPI_DATASIZE_7BIT               ((uint32_t)0x0600)
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x0700)
-#define SPI_DATASIZE_9BIT               ((uint32_t)0x0800)
-#define SPI_DATASIZE_10BIT              ((uint32_t)0x0900)
-#define SPI_DATASIZE_11BIT              ((uint32_t)0x0A00)
-#define SPI_DATASIZE_12BIT              ((uint32_t)0x0B00)
-#define SPI_DATASIZE_13BIT              ((uint32_t)0x0C00)
-#define SPI_DATASIZE_14BIT              ((uint32_t)0x0D00)
-#define SPI_DATASIZE_15BIT              ((uint32_t)0x0E00)
-#define SPI_DATASIZE_16BIT              ((uint32_t)0x0F00)
+#define SPI_DATASIZE_4BIT               (0x00000300U)
+#define SPI_DATASIZE_5BIT               (0x00000400U)
+#define SPI_DATASIZE_6BIT               (0x00000500U)
+#define SPI_DATASIZE_7BIT               (0x00000600U)
+#define SPI_DATASIZE_8BIT               (0x00000700U)
+#define SPI_DATASIZE_9BIT               (0x00000800U)
+#define SPI_DATASIZE_10BIT              (0x00000900U)
+#define SPI_DATASIZE_11BIT              (0x00000A00U)
+#define SPI_DATASIZE_12BIT              (0x00000B00U)
+#define SPI_DATASIZE_13BIT              (0x00000C00U)
+#define SPI_DATASIZE_14BIT              (0x00000D00U)
+#define SPI_DATASIZE_15BIT              (0x00000E00U)
+#define SPI_DATASIZE_16BIT              (0x00000F00U)
 /**
   * @}
   */
@@ -234,7 +233,7 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
   * @{
   */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
+#define SPI_POLARITY_LOW                (0x00000000U)
 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 /**
   * @}
@@ -243,18 +242,18 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_Clock_Phase SPI Clock Phase
   * @{
   */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
+#define SPI_PHASE_1EDGE                 (0x00000000U)
 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 /**
   * @}
   */
 
-/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
   * @{
   */
 #define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
-#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
+#define SPI_NSS_HARD_INPUT              (0x00000000U)
+#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
 /**
   * @}
   */
@@ -263,7 +262,7 @@ typedef struct __SPI_HandleTypeDef
   * @{
   */
 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000)
+#define SPI_NSS_PULSE_DISABLE           (0x00000000U)
 /**
   * @}
   */
@@ -271,31 +270,31 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
   * @{
   */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
-#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
-#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
-#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
-#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
-#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
-#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
-#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
+#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
+#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
 /**
   * @}
   */
 
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
   * @{
   */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_MSB                (0x00000000U)
 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 /**
   * @}
   */
 
-/** @defgroup SPI_TI_mode SPI TI mode
+/** @defgroup SPI_TI_mode SPI TI Mode
   * @{
   */
-#define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000)
+#define SPI_TIMODE_DISABLE              (0x00000000U)
 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
 /**
   * @}
@@ -304,7 +303,7 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
   * @{
   */
-#define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
 /**
   * @}
@@ -317,9 +316,9 @@ typedef struct __SPI_HandleTypeDef
   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
   */
-#define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000)
-#define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001)
-#define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002)
+#define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
+#define SPI_CRC_LENGTH_8BIT             (0x00000001U)
+#define SPI_CRC_LENGTH_16BIT            (0x00000002U)
 /**
   * @}
   */
@@ -334,16 +333,13 @@ typedef struct __SPI_HandleTypeDef
   *          level is greater or equal to 1/4(8 bits). */
 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000)
+#define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)
 
 /**
   * @}
   */
 
-/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
-  * @brief SPI Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
   * @{
   */
 #define SPI_IT_TXE                      SPI_CR2_TXEIE
@@ -353,23 +349,18 @@ typedef struct __SPI_HandleTypeDef
   * @}
   */
 
-
-/** @defgroup SPI_Flag_definition SPI Flag definition
-  * @brief Flag definition
-  *        Elements values convention: 0xXXXXYYYY
-  *           - XXXX  : Flag register Index
-  *           - YYYY  : Flag mask
+/** @defgroup SPI_Flags_definition SPI Flags Definition
   * @{
   */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
+#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
+#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
+#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
+#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level */
-#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level */
+#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
+#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
 /**
   * @}
   */
@@ -377,10 +368,10 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
   * @{
   */
-#define SPI_FTLVL_EMPTY           ((uint32_t)0x0000)
-#define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x0800)
-#define SPI_FTLVL_HALF_FULL       ((uint32_t)0x1000)
-#define SPI_FTLVL_FULL            ((uint32_t)0x1800)
+#define SPI_FTLVL_EMPTY                 (0x00000000U)
+#define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
+#define SPI_FTLVL_HALF_FULL             (0x00001000U)
+#define SPI_FTLVL_FULL                  (0x00001800U)
 
 /**
   * @}
@@ -389,10 +380,10 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
   * @{
   */
-#define SPI_FRLVL_EMPTY           ((uint32_t)0x0000)
-#define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x0200)
-#define SPI_FRLVL_HALF_FULL       ((uint32_t)0x0400)
-#define SPI_FRLVL_FULL            ((uint32_t)0x0600)
+#define SPI_FRLVL_EMPTY                 (0x00000000U)
+#define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
+#define SPI_FRLVL_HALF_FULL             (0x00000400U)
+#define SPI_FRLVL_FULL                  (0x00000600U)
 /**
   * @}
   */
@@ -401,29 +392,41 @@ typedef struct __SPI_HandleTypeDef
   * @}
   */
 
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup SPI_Exported_Macros SPI Exported Macros
   * @{
   */
 
 /** @brief  Reset SPI handle state.
-  * @param  __HANDLE__: SPI handle.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
 
-/** @brief  Enable or disable the specified SPI interrupts.
+/** @brief  Enable the specified SPI interrupts.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *        This parameter can be one of the following values:
+  * @param  __INTERRUPT__: specifies the interrupt source to enable.
+  *         This parameter can be one of the following values:
   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
   *            @arg SPI_IT_ERR: Error interrupt enable
   * @retval None
   */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief  Disable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to disable.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
 
 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
   * @param  __HANDLE__: specifies the SPI Handle.
@@ -441,7 +444,7 @@ typedef struct __SPI_HandleTypeDef
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
   *            @arg SPI_FLAG_CRCERR: CRC error flag
@@ -465,64 +468,61 @@ typedef struct __SPI_HandleTypeDef
 /** @brief  Clear the SPI MODF pending flag.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  *
   * @retval None
   */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)        \
-   do{                                              \
-     __IO uint32_t tmpreg;                          \
-     tmpreg = (__HANDLE__)->Instance->SR;           \
-     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
-     UNUSED(tmpreg);                                \
-   } while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
+  do{                                                    \
+    __IO uint32_t tmpreg_modf = 0x00U;                   \
+    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
+    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+    UNUSED(tmpreg_modf);                                 \
+  } while(0U)
 
 /** @brief  Clear the SPI OVR pending flag.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  *
   * @retval None
   */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)         \
-   do{                                              \
-     __IO uint32_t tmpreg;                          \
-     tmpreg = (__HANDLE__)->Instance->DR;           \
-     tmpreg = (__HANDLE__)->Instance->SR;           \
-     UNUSED(tmpreg);                                \
-   } while(0)
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
+  do{                                              \
+    __IO uint32_t tmpreg_ovr = 0x00U;              \
+    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
+    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
+    UNUSED(tmpreg_ovr);                            \
+  } while(0U)
 
 /** @brief  Clear the SPI FRE pending flag.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  *
   * @retval None
   */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)         \
-   do{                                              \
-     __IO uint32_t tmpreg;                          \
-     tmpreg = (__HANDLE__)->Instance->SR;           \
-     UNUSED(tmpreg);                                \
-   } while(0)
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
+  do{                                              \
+  __IO uint32_t tmpreg_fre = 0x00U;                \
+  tmpreg_fre = (__HANDLE__)->Instance->SR;         \
+  UNUSED(tmpreg_fre);                              \
+  }while(0U)
 
 /** @brief  Enable the SPI peripheral.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
+#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 
 /** @brief  Disable the SPI peripheral.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 
 /**
   * @}
   */
 
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros   SPI Private Macros
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
   * @{
   */
 
@@ -531,34 +531,34 @@ typedef struct __SPI_HandleTypeDef
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
 
 /** @brief  Set the SPI receive-only mode.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
 
 /** @brief  Reset the CRC calculation of the SPI.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
-                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
 
 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
                            ((MODE) == SPI_MODE_MASTER))
 
-#define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES) || \
-                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
-                                  ((MODE) == SPI_DIRECTION_1LINE))
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
+                                ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+                                ((MODE) == SPI_DIRECTION_1LINE))
 
 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
 
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
-                                                 ((MODE) == SPI_DIRECTION_1LINE))
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+                                                ((MODE) == SPI_DIRECTION_1LINE))
 
 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
@@ -580,19 +580,19 @@ typedef struct __SPI_HandleTypeDef
 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
                            ((CPHA) == SPI_PHASE_2EDGE))
 
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
                          ((NSS) == SPI_NSS_HARD_INPUT) || \
                          ((NSS) == SPI_NSS_HARD_OUTPUT))
 
 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
                            ((NSSP) == SPI_NSS_PULSE_DISABLE))
 
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
 
@@ -609,7 +609,7 @@ typedef struct __SPI_HandleTypeDef
                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT))
 
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
 
 
 /**
@@ -624,34 +624,40 @@ typedef struct __SPI_HandleTypeDef
   * @{
   */
 
-/* Initialization and de-initialization functions  ****************************/
 /** @addtogroup SPI_Exported_Functions_Group1
   * @{
   */
+/* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
 
-/* IO operation functions *****************************************************/
 /** @addtogroup SPI_Exported_Functions_Group2
   * @{
   */
+/* I/O operation functions  ***************************************************/
 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+                                          uint32_t Timeout);
 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+                                             uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+                                              uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
 
 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
@@ -661,14 +667,15 @@ void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
 
-/* Peripheral State and Error functions ***************************************/
 /** @addtogroup SPI_Exported_Functions_Group3
   * @{
   */
+/* Peripheral State and Error functions ***************************************/
 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 /**

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h

@@ -1,14 +1,14 @@
- /**
+/**
   ******************************************************************************
   * @file    stm32l4xx_hal_spi_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of SPI HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -40,7 +40,7 @@
 #define __STM32L4xx_HAL_SPI_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -56,7 +56,7 @@
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup SPIEx_Exported_Functions
   * @{

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h

@@ -0,0 +1,202 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sram.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SRAM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SRAM_H
+#define __STM32L4xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_fmc.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SRAM
+  * @{
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+  * @{
+  */
+/**
+  * @brief  HAL SRAM State structures definition
+  */
+typedef enum
+{
+  HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
+  HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
+  HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
+  HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
+  HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
+
+}HAL_SRAM_StateTypeDef;
+
+/**
+  * @brief  SRAM handle Structure definition
+  */
+typedef struct
+{
+  FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
+
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
+
+  FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
+
+  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
+
+  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
+
+  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
+
+}SRAM_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
+
+/** @brief Reset SRAM handle state.
+  * @param  __HANDLE__: SRAM handle
+  * @retval None
+  */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
+  * @{
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @{
+ */
+
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
+ * @{
+ */
+
+/* SRAM Control functions  ****************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* SRAM Peripheral State functions ********************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx ||                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h

@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_swpmi.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of SWPMI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SWPMI_H
+#define __STM32L4xx_HAL_SWPMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
+    defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SWPMI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SWPMI_Exported_Types SWPMI Exported Types
+  * @{
+  */
+
+/**
+  * @brief SWPMI Init Structure definition
+  */
+typedef struct
+{
+  uint32_t VoltageClass;             /*!< Specifies the SWP Voltage Class.
+                                          This parameter can be a value of @ref SWPMI_Voltage_Class */
+
+  uint32_t BitRate;                  /*!< Specifies the SWPMI Bitrate.
+                                          This parameter must be a number between 0 and 63.
+                                          The Bitrate is computed using the following formula:
+                                          SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
+                                          */
+
+  uint32_t TxBufferingMode;          /*!< Specifies the transmission buffering mode.
+                                          This parameter can be a value of @ref SWPMI_Tx_Buffering_Mode */
+
+  uint32_t RxBufferingMode;          /*!< Specifies the reception buffering mode.
+                                          This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
+
+}SWPMI_InitTypeDef;
+
+
+/**
+  * @brief HAL SWPMI State structures definition
+  */
+typedef enum
+{
+  HAL_SWPMI_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                             */
+  HAL_SWPMI_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SWPMI_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
+  HAL_SWPMI_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
+  HAL_SWPMI_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
+  HAL_SWPMI_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_SWPMI_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
+  HAL_SWPMI_STATE_ERROR             = 0x04     /*!< Error                                              */
+}HAL_SWPMI_StateTypeDef;
+
+/**
+  * @brief  SWPMI handle Structure definition
+  */
+typedef struct
+{
+  SWPMI_TypeDef                  *Instance;     /* SWPMI registers base address         */
+
+  SWPMI_InitTypeDef              Init;          /* SWMPI communication parameters       */
+
+  uint32_t                       *pTxBuffPtr;   /* Pointer to SWPMI Tx transfer Buffer  */
+
+  uint32_t                       TxXferSize;    /* SWPMI Tx Transfer size               */
+
+  uint32_t                       TxXferCount;   /* SWPMI Tx Transfer Counter            */
+
+  uint32_t                       *pRxBuffPtr;   /* Pointer to SWPMI Rx transfer Buffer  */
+
+  uint32_t                       RxXferSize;    /* SWPMI Rx Transfer size               */
+
+  uint32_t                       RxXferCount;   /* SWPMI Rx Transfer Counter            */
+
+  DMA_HandleTypeDef              *hdmatx;       /* SWPMI Tx DMA Handle parameters       */
+
+  DMA_HandleTypeDef              *hdmarx;       /* SWPMI Rx DMA Handle parameters       */
+
+  HAL_LockTypeDef                Lock;          /* SWPMI object                         */
+
+  __IO HAL_SWPMI_StateTypeDef    State;         /* SWPMI communication state            */
+
+  __IO uint32_t                  ErrorCode;     /* SWPMI Error code                     */
+
+}SWPMI_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SWPMI_Exported_Constants SWPMI Exported Constants
+  * @{
+  */
+
+/**
+  * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap
+  * @{
+  */
+#define HAL_SWPMI_ERROR_NONE                 ((uint32_t)0x00000000) /*!< No error             */
+#define HAL_SWPMI_ERROR_CRC                  ((uint32_t)0x00000004) /*!< frame error          */
+#define HAL_SWPMI_ERROR_OVR                  ((uint32_t)0x00000008) /*!< Overrun error        */
+#define HAL_SWPMI_ERROR_UDR                  ((uint32_t)0x0000000C) /*!< Underrun error       */
+#define HAL_SWPMI_ERROR_DMA                  ((uint32_t)0x00000010) /*!< DMA transfer error   */
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Voltage_Class SWPMI Voltage Class
+  * @{
+  */
+#define SWPMI_VOLTAGE_CLASS_C                ((uint32_t)0x00000000)
+#define SWPMI_VOLTAGE_CLASS_B                SWPMI_OR_CLASS
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Tx_Buffering_Mode SWPMI Tx Buffering Mode
+  * @{
+  */
+#define SWPMI_TX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
+#define SWPMI_TX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
+#define SWPMI_TX_MULTI_SOFTWAREBUFFER        SWPMI_CR_TXMODE
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Rx_Buffering_Mode SWPMI Rx Buffering Mode
+  * @{
+  */
+#define SWPMI_RX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
+#define SWPMI_RX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
+#define SWPMI_RX_MULTI_SOFTWAREBUFFER        SWPMI_CR_RXMODE
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Flags SWPMI Status Flags
+  *        Elements values convention: 0xXXXXXXXX
+  *           - 0xXXXXXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define SWPMI_FLAG_RXBFF                 SWPMI_ISR_RXBFF
+#define SWPMI_FLAG_TXBEF                 SWPMI_ISR_TXBEF
+#define SWPMI_FLAG_RXBERF                SWPMI_ISR_RXBERF
+#define SWPMI_FLAG_RXOVRF                SWPMI_ISR_RXOVRF
+#define SWPMI_FLAG_TXUNRF                SWPMI_ISR_TXUNRF
+#define SWPMI_FLAG_RXNE                  SWPMI_ISR_RXNE
+#define SWPMI_FLAG_TXE                   SWPMI_ISR_TXE
+#define SWPMI_FLAG_TCF                   SWPMI_ISR_TCF
+#define SWPMI_FLAG_SRF                   SWPMI_ISR_SRF
+#define SWPMI_FLAG_SUSP                  SWPMI_ISR_SUSP
+#define SWPMI_FLAG_DEACTF                SWPMI_ISR_DEACTF
+/**
+  * @}
+  */
+
+/** @defgroup SWPMI_Interrupt_definition SWPMI Interrupts Definition
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the IER register
+  * @{
+  */
+#define SWPMI_IT_SRIE                    SWPMI_IER_SRIE
+#define SWPMI_IT_TCIE                    SWPMI_IER_TCIE
+#define SWPMI_IT_TIE                     SWPMI_IER_TIE
+#define SWPMI_IT_RIE                     SWPMI_IER_RIE
+#define SWPMI_IT_TXUNRIE                 SWPMI_IER_TXUNRIE
+#define SWPMI_IT_RXOVRIE                 SWPMI_IER_RXOVRIE
+#define SWPMI_IT_RXBERIE                 SWPMI_IER_RXBERIE
+#define SWPMI_IT_TXBEIE                  SWPMI_IER_TXBEIE
+#define SWPMI_IT_RXBFIE                  SWPMI_IER_RXBFIE
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SWPMI_Exported_Macros SWPMI Exported Macros
+  * @{
+  */
+
+/** @brief Reset SWPMI handle state.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @retval None
+  */
+#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
+
+/**
+  * @brief  Enable the SWPMI peripheral.
+  * @param  __HANDLE__: SWPMI handle
+  * @retval None
+  */
+#define __HAL_SWPMI_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
+
+/**
+  * @brief  Disable the SWPMI peripheral.
+  * @param  __HANDLE__: SWPMI handle
+  * @retval None
+  */
+#define __HAL_SWPMI_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
+
+/** @brief  Check whether the specified SWPMI flag is set or not.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
+  *            @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
+  *            @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
+  *            @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
+  *            @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
+  *            @arg SWPMI_FLAG_RXNE : Receive data register not empty.
+  *            @arg SWPMI_FLAG_TXE : Transmit data register empty.
+  *            @arg SWPMI_FLAG_TCF : Transfer complete flag.
+  *            @arg SWPMI_FLAG_SRF : Slave resume flag.
+  *            @arg SWPMI_FLAG_SUSP : SUSPEND flag.
+  *            @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified SWPMI ISR flag.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
+  *            @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
+  *            @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
+  *            @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
+  *            @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
+  *            @arg SWPMI_FLAG_TCF : Transfer complete flag.
+  *            @arg SWPMI_FLAG_SRF : Slave resume flag.
+  * @retval None
+  */
+#define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
+
+/** @brief  Enable the specified SWPMI interrupt.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __INTERRUPT__: specifies the SWPMI interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
+  *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
+  *            @arg SWPMI_IT_TIE :  Transmit interrupt.
+  *            @arg SWPMI_IT_RIE :  Receive interrupt.
+  *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
+  *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
+  *            @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
+  *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
+  *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
+  * @retval None
+  */
+#define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
+
+/** @brief  Disable the specified SWPMI interrupt.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __INTERRUPT__: specifies the SWPMI interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
+  *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
+  *            @arg SWPMI_IT_TIE :  Transmit interrupt.
+  *            @arg SWPMI_IT_RIE :  Receive interrupt.
+  *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
+  *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
+  *            @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
+  *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
+  *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
+  * @retval None
+  */
+#define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
+
+/** @brief  Check whether the specified SWPMI interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __IT__: specifies the SWPMI interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
+  *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
+  *            @arg SWPMI_IT_TIE :  Transmit interrupt.
+  *            @arg SWPMI_IT_RIE :  Receive interrupt.
+  *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
+  *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
+  *            @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
+  *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
+  *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__)  (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
+
+/** @brief  Check whether the specified SWPMI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SWPMI Handle.
+  * @param  __IT__: specifies the SWPMI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
+  *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
+  *            @arg SWPMI_IT_TIE :  Transmit interrupt.
+  *            @arg SWPMI_IT_RIE :  Receive interrupt.
+  *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
+  *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
+  *            @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
+  *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
+  *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi);
+HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi);
+HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi);
+HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
+void              HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi);
+
+/* Peripheral Control and State functions  ************************************/
+HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi);
+uint32_t               HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SWPMI_Private_Types SWPMI Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SWPMI_Private_Variables SWPMI Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SWPMI_Private_Constants SWPMI Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SWPMI_Private_Macros SWPMI Private Macros
+  * @{
+  */
+
+
+#define IS_SWPMI_VOLTAGE_CLASS(__CLASS__)    (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
+                                              ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))
+
+#define IS_SWPMI_BITRATE_VALUE(__VALUE__)    (((__VALUE__) <= 63))
+
+
+#define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
+                                              ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))
+
+
+#define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
+                                              ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SWPMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_tim.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of TIM HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -593,9 +593,9 @@ typedef struct
   * @}
   */
 
-/** @defgroup TIM_Commutation_Source  TIM Commutation Source 
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
   * @{
-  */  
+  */
 #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
 #define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
 /**
@@ -1051,6 +1051,14 @@ typedef struct
                             } \
                         } while(0)
 
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
 /** @brief  Enable the specified TIM interrupt.
   * @param  __HANDLE__: specifies the TIM Handle.
   * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
@@ -1129,8 +1137,8 @@ typedef struct
   *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_BREAK: Break interrupt flag   
-  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag                     
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
@@ -1153,8 +1161,8 @@ typedef struct
   *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_BREAK: Break interrupt flag   
-  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag                     
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
@@ -1362,7 +1370,7 @@ mode.
 /**
   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
   * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is set, only counter 
+  * @note  When the USR bit of the TIMx_CR1 register is set, only counter
   *        overflow/underflow generates an update interrupt or DMA request (if
   *        enabled)
   * @retval None
@@ -1373,8 +1381,8 @@ mode.
 /**
   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
   * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is reset, any of the 
-  *        following events generate an update interrupt or DMA request (if 
+  * @note  When the USR bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
   *        enabled):
   *           _ Counter overflow underflow
   *           _ Setting the UG bit
@@ -1383,7 +1391,7 @@ mode.
   */
 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
       ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-        
+
 /**
   * @brief  Set the TIM Capture x input polarity on runtime.
   * @param  __HANDLE__: TIM handle.
@@ -1393,7 +1401,7 @@ mode.
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__: Polarity for TIx source   
+  * @param  __POLARITY__: Polarity for TIx source
   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
@@ -1404,7 +1412,7 @@ mode.
           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
         }while(0)
-          
+
 /**
   * @}
   */
@@ -1422,7 +1430,7 @@ mode.
   * @}
   */
 /* End of private constants --------------------------------------------------*/
-  
+
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup TIM_Private_Macros TIM Private Macros
   * @{
@@ -1945,10 +1953,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
 */
 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
 
@@ -1958,7 +1963,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
 /**
 * @}
-*/ 
+*/
 /* End of private functions --------------------------------------------------*/
 
 /**

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_tim_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of TIM HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L4xx_HAL_TIM_EX_H
@@ -52,35 +52,35 @@
 
 /** @addtogroup TIMEx
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
   * @{
   */
 
-/** 
-  * @brief  TIM Hall sensor Configuration Structure definition  
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
   */
 
 typedef struct
 {
-                                  
+
   uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
                                      This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-                                                                   
+
   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-                                  
+
   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
 
-  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
 } TIM_HallSensor_InitTypeDef;
 
-/** 
-  * @brief  TIM Break/Break2 input configuration   
+/**
+  * @brief  TIM Break/Break2 input configuration
   */
 typedef struct {
   uint32_t Source;         /*!< Specifies the source of the timer break input.
@@ -89,13 +89,13 @@ typedef struct {
                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
   uint32_t Polarity;       /*!< Specifies the break input source polarity.
                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
-                                Not relevant when analog watchdog output of the DFSDM used as break input source */
+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */
 } TIMEx_BreakInputConfigTypeDef;
 
 /**
   * @}
   */
-/* End of exported types -----------------------------------------------------*/ 
+/* End of exported types -----------------------------------------------------*/
 
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
@@ -109,16 +109,31 @@ typedef struct {
 #define TIM_TIM1_ETR_ADC1_AWD1      (TIM1_OR1_ETR_ADC1_RMP_0)                             /* !< TIM1_ETR is connected to ADC1 AWD1 */
 #define TIM_TIM1_ETR_ADC1_AWD2      (TIM1_OR1_ETR_ADC1_RMP_1)                             /* !< TIM1_ETR is connected to ADC1 AWD2 */
 #define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0)   /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define TIM_TIM1_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
 #define TIM_TIM1_ETR_ADC3_AWD1      (TIM1_OR1_ETR_ADC3_RMP_0)                             /* !< TIM1_ETR is connected to ADC3 AWD1 */
 #define TIM_TIM1_ETR_ADC3_AWD2      (TIM1_OR1_ETR_ADC3_RMP_1)                             /* !< TIM1_ETR is connected to ADC3 AWD2 */
 #define TIM_TIM1_ETR_ADC3_AWD3      (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0)   /* !< TIM1_ETR is connected to ADC3 AWD3 */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
 #define TIM_TIM1_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM1 TI1 is connected to GPIO */
 #define TIM_TIM1_TI1_COMP1          (TIM1_OR1_TI1_RMP)                                    /* !< TIM1 TI1 is connected to COMP1 */
 #define TIM_TIM1_ETR_COMP1          (TIM1_OR2_ETRSEL_0)                                   /* !< TIM1_ETR is connected to COMP1 output */
 #define TIM_TIM1_ETR_COMP2          (TIM1_OR2_ETRSEL_1)                                   /* !< TIM1_ETR is connected to COMP2 output */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define TIM_TIM2_ITR1_TIM8_TRGO     ((uint32_t)(0x00000000))                              /* !< TIM2_ITR1 is connected to TIM8_TRGO */
 #define TIM_TIM2_ITR1_OTG_FS_SOF    (TIM2_OR1_ITR1_RMP)                                   /* !< TIM2_ITR1 is connected to OTG_FS SOF */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define TIM_TIM2_ITR1_NONE          ((uint32_t)(0x00000000))                              /* !< No internal trigger on TIM2_ITR1 */
+#define TIM_TIM2_ITR1_USB_SOF       (TIM2_OR1_ITR1_RMP)                                   /* !< TIM2_ITR1 is connected to USB SOF */
+#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */
+       /* STM32L451xx || STM32L452xx || STM32L462xx */
 #define TIM_TIM2_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2_ETR is connected to GPIO */
 #define TIM_TIM2_ETR_LSE            (TIM2_OR1_ETR1_RMP)                                   /* !< TIM2_ETR is connected to LSE */
 #define TIM_TIM2_ETR_COMP1          (TIM2_OR2_ETRSEL_0)                                   /* !< TIM2_ETR is connected to COMP1 output */
@@ -127,12 +142,22 @@ typedef struct {
 #define TIM_TIM2_TI4_COMP1          (TIM2_OR1_TI4_RMP_0)                                  /* !< TIM2 TI4 is connected to COMP1 output */
 #define TIM_TIM2_TI4_COMP2          (TIM2_OR1_TI4_RMP_1)                                  /* !< TIM2 TI4 is connected to COMP2 output */
 #define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0)              /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
+
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define TIM_TIM3_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3 TI1 is connected to GPIO */
 #define TIM_TIM3_TI1_COMP1          (TIM3_OR1_TI1_RMP_0)                                  /* !< TIM3 TI1 is connected to COMP1 output */
 #define TIM_TIM3_TI1_COMP2          (TIM3_OR1_TI1_RMP_1)                                  /* !< TIM3 TI1 is connected to COMP2 output */
 #define TIM_TIM3_TI1_COMP1_COMP2    (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0)             /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
 #define TIM_TIM3_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3_ETR is connected to GPIO */
 #define TIM_TIM3_ETR_COMP1          (TIM3_OR2_ETRSEL_0)                                   /* !< TIM3_ETR is connected to COMP1 output */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define TIM_TIM8_ETR_ADC2_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
 #define TIM_TIM8_ETR_ADC2_AWD1      (TIM8_OR1_ETR_ADC2_RMP_0)                             /* !< TIM8_ETR is connected to ADC2 AWD1 */
 #define TIM_TIM8_ETR_ADC2_AWD2      (TIM8_OR1_ETR_ADC2_RMP_1)                             /* !< TIM8_ETR is connected to ADC2 AWD2 */
@@ -141,27 +166,55 @@ typedef struct {
 #define TIM_TIM8_ETR_ADC3_AWD1      (TIM8_OR1_ETR_ADC3_RMP_0)                             /* !< TIM8_ETR is connected to ADC3 AWD1 */
 #define TIM_TIM8_ETR_ADC3_AWD2      (TIM8_OR1_ETR_ADC3_RMP_1)                             /* !< TIM8_ETR is connected to ADC3 AWD2 */
 #define TIM_TIM8_ETR_ADC3_AWD3      (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0)   /* !< TIM8_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM8_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM8 TI1 is connected to GPIO */
-#define TIM_TIM8_TI1_COMP2          (TIM8_OR1_TI1_RMP)                                    /* !< TIM8 TI1 is connected to COMP1 */
 #define TIM_TIM8_ETR_COMP1          (TIM8_OR2_ETRSEL_0)                                   /* !< TIM8_ETR is connected to COMP1 output */
 #define TIM_TIM8_ETR_COMP2          (TIM8_OR2_ETRSEL_1)                                   /* !< TIM8_ETR is connected to COMP2 output */
+#define TIM_TIM8_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM8 TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP2          (TIM8_OR1_TI1_RMP)                                    /* !< TIM8 TI1 is connected to COMP1 */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
 #define TIM_TIM15_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM15 TI1 is connected to GPIO */
 #define TIM_TIM15_TI1_LSE           (TIM15_OR1_TI1_RMP)                                   /* !< TIM15 TI1 is connected to LSE */
 #define TIM_TIM15_ENCODERMODE_NONE  ((uint32_t)(0x00000000))                              /* !< No redirection */
 #define TIM_TIM15_ENCODERMODE_TIM2  (TIM15_OR1_ENCODER_MODE_0)                            /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define TIM_TIM15_ENCODERMODE_TIM3  (TIM15_OR1_ENCODER_MODE_1)                            /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define TIM_TIM15_ENCODERMODE_TIM4  (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
 #define TIM_TIM16_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM16 TI1 is connected to GPIO */
 #define TIM_TIM16_TI1_LSI           (TIM16_OR1_TI1_RMP_0)                                 /* !< TIM16 TI1 is connected to LSI */
 #define TIM_TIM16_TI1_LSE           (TIM16_OR1_TI1_RMP_1)                                 /* !< TIM16 TI1 is connected to LSE */
 #define TIM_TIM16_TI1_RTC           (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
+#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
+    defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_TIM16_TI1_MSI           (TIM16_OR1_TI1_RMP_2)                                 /* !< TIM16 TI1 is connected to MSI */
+#define TIM_TIM16_TI1_HSE_32        (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to HSE div 32 */
+#define TIM_TIM16_TI1_MCO           (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1)           /* !< TIM16 TI1 is connected to MCO */
+#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */
+       /* STM32L451xx || STM32L452xx || STM32L462xx || */
+       /* STM32L496xx || STM32L4A6xx */
+
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define TIM_TIM17_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM17 TI1 is connected to GPIO */
 #define TIM_TIM17_TI1_MSI           (TIM17_OR1_TI1_RMP_0)                                 /* !< TIM17 TI1 is connected to MSI */
 #define TIM_TIM17_TI1_HSE_32        (TIM17_OR1_TI1_RMP_1)                                 /* !< TIM17 TI1 is connected to HSE div 32 */
 #define TIM_TIM17_TI1_MCO           (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0)           /* !< TIM17 TI1 is connected to MCO */
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup TIMEx_Break_Input TIM  Extended Break input
   * @{
@@ -170,7 +223,7 @@ typedef struct {
 #define TIM_BREAKINPUT_BRK2    ((uint32_t)(0x00000002)) /* !< Timer break2 input */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source
   * @{
@@ -178,10 +231,16 @@ typedef struct {
 #define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin  */
 #define TIM_BREAKINPUTSOURCE_COMP1    ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
 #define TIM_BREAKINPUTSOURCE_COMP2    ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_DFSDM    ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM peripheral is connected to the break input */
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
+#define TIM_BREAKINPUTSOURCE_DFSDM1   ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */
+       /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
+       /* STM32L496xx || STM32L4A6xx */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
   * @{
@@ -190,7 +249,7 @@ typedef struct {
 #define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM  Extended Break input polarity
   * @{
@@ -199,36 +258,44 @@ typedef struct {
 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
 /**
   * @}
-  */ 
-   
+  */
+
 /**
   * @}
-  */ 
+  */
 /* End of exported constants -------------------------------------------------*/
 
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
   * @{
-  */  
+  */
 
 /**
   * @}
-  */ 
+  */
 /* End of exported macro -----------------------------------------------------*/
 
 /* Private macro -------------------------------------------------------------*/
 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
   * @{
-  */  
+  */
 #define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))
 
 #define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
                                             ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
 
+#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
+    defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
+    defined (STM32L496xx) || defined (STM32L4A6xx)
 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
-                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
+#else
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
 
 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
                                                    ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
@@ -237,7 +304,7 @@ typedef struct {
                                                          ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
 /**
   * @}
-  */ 
+  */
 /* End of private macro ------------------------------------------------------*/
 
 /* Exported functions --------------------------------------------------------*/
@@ -245,7 +312,7 @@ typedef struct {
   * @{
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
  *  @brief    Timer Hall Sensor functions
  * @{
  */
@@ -342,7 +409,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
   * @brief    Extended Callbacks functions
   * @{
   */
@@ -353,7 +420,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
   * @brief    Extended Peripheral State functions
   * @{
   */
@@ -365,7 +432,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
 
 /**
   * @}
-  */ 
+  */
 /* End of exported functions -------------------------------------------------*/
 
 /* Private functions----------------------------------------------------------*/
@@ -375,17 +442,17 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
 /**
 * @}
-*/ 
+*/
 /* End of private functions --------------------------------------------------*/
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
 #endif

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h

@@ -0,0 +1,726 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_tsc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of TSC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_TSC_H
+#define __STM32L4xx_HAL_TSC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TSC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TSC_Exported_Types TSC Exported Types
+  * @{
+  */
+
+/**
+  * @brief TSC state structure definition
+  */
+typedef enum
+{
+  HAL_TSC_STATE_RESET  = 0x00, /*!< TSC registers have their reset value */
+  HAL_TSC_STATE_READY  = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
+  HAL_TSC_STATE_BUSY   = 0x02, /*!< TSC initialization or acquisition is on-going */
+  HAL_TSC_STATE_ERROR  = 0x03  /*!< Acquisition is completed with max count error */
+} HAL_TSC_StateTypeDef;
+
+/**
+  * @brief TSC group status structure definition
+  */
+typedef enum
+{
+  TSC_GROUP_ONGOING   = 0x00, /*!< Acquisition on group is on-going or not started */
+  TSC_GROUP_COMPLETED = 0x01  /*!< Acquisition on group is completed with success (no max count error) */
+} TSC_GroupStatusTypeDef;
+
+/**
+  * @brief TSC init structure definition
+  */
+typedef struct
+{
+  uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length
+                                         This parameter can be a value of @ref TSC_CTPulseHL_Config  */
+  uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length
+                                         This parameter can be a value of @ref TSC_CTPulseLL_Config  */
+  uint32_t SpreadSpectrum;          /*!< Spread spectrum activation
+                                         This parameter can be a value of @ref TSC_CTPulseLL_Config  */
+  uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
+                                         This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
+  uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
+                                         This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
+  uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
+                                         This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
+  uint32_t MaxCountValue;           /*!< Max count value
+                                         This parameter can be a value of @ref TSC_MaxCount_Value  */
+  uint32_t IODefaultMode;           /*!< IO default mode
+                                         This parameter can be a value of @ref TSC_IO_Default_Mode  */
+  uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity
+                                         This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
+  uint32_t AcquisitionMode;         /*!< Acquisition mode
+                                         This parameter can be a value of @ref TSC_Acquisition_Mode  */
+  uint32_t MaxCountInterrupt;       /*!< Max count interrupt activation
+                                         This parameter can be set to ENABLE or DISABLE. */
+  uint32_t ChannelIOs;              /*!< Channel IOs mask */
+  uint32_t ShieldIOs;               /*!< Shield IOs mask */
+  uint32_t SamplingIOs;             /*!< Sampling IOs mask */
+} TSC_InitTypeDef;
+
+/**
+  * @brief TSC IOs configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ChannelIOs;  /*!< Channel IOs mask */
+  uint32_t ShieldIOs;   /*!< Shield IOs mask */
+  uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_IOConfigTypeDef;
+
+/**
+  * @brief  TSC handle Structure definition
+  */
+typedef struct
+{
+  TSC_TypeDef               *Instance; /*!< Register base address */
+  TSC_InitTypeDef           Init;      /*!< Initialization parameters */
+  __IO HAL_TSC_StateTypeDef State;     /*!< Peripheral state */
+  HAL_LockTypeDef           Lock;      /*!< Lock feature */
+} TSC_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TSC_Exported_Constants TSC Exported Constants
+  * @{
+  */
+
+/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
+  * @{
+  */
+#define TSC_CTPH_1CYCLE   ((uint32_t)((uint32_t) 0 << 28))
+#define TSC_CTPH_2CYCLES  ((uint32_t)((uint32_t) 1 << 28))
+#define TSC_CTPH_3CYCLES  ((uint32_t)((uint32_t) 2 << 28))
+#define TSC_CTPH_4CYCLES  ((uint32_t)((uint32_t) 3 << 28))
+#define TSC_CTPH_5CYCLES  ((uint32_t)((uint32_t) 4 << 28))
+#define TSC_CTPH_6CYCLES  ((uint32_t)((uint32_t) 5 << 28))
+#define TSC_CTPH_7CYCLES  ((uint32_t)((uint32_t) 6 << 28))
+#define TSC_CTPH_8CYCLES  ((uint32_t)((uint32_t) 7 << 28))
+#define TSC_CTPH_9CYCLES  ((uint32_t)((uint32_t) 8 << 28))
+#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
+#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
+#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
+#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
+#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
+#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
+#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
+/**
+  * @}
+  */
+
+/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
+  * @{
+  */
+#define TSC_CTPL_1CYCLE   ((uint32_t)((uint32_t) 0 << 24))
+#define TSC_CTPL_2CYCLES  ((uint32_t)((uint32_t) 1 << 24))
+#define TSC_CTPL_3CYCLES  ((uint32_t)((uint32_t) 2 << 24))
+#define TSC_CTPL_4CYCLES  ((uint32_t)((uint32_t) 3 << 24))
+#define TSC_CTPL_5CYCLES  ((uint32_t)((uint32_t) 4 << 24))
+#define TSC_CTPL_6CYCLES  ((uint32_t)((uint32_t) 5 << 24))
+#define TSC_CTPL_7CYCLES  ((uint32_t)((uint32_t) 6 << 24))
+#define TSC_CTPL_8CYCLES  ((uint32_t)((uint32_t) 7 << 24))
+#define TSC_CTPL_9CYCLES  ((uint32_t)((uint32_t) 8 << 24))
+#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
+#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
+#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
+#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
+#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
+#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
+#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
+/**
+  * @}
+  */
+
+/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
+  * @{
+  */
+#define TSC_SS_PRESC_DIV1 ((uint32_t)0)
+#define TSC_SS_PRESC_DIV2  (TSC_CR_SSPSC)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
+  * @{
+  */
+#define TSC_PG_PRESC_DIV1   ((uint32_t)(0 << 12))
+#define TSC_PG_PRESC_DIV2   ((uint32_t)(1 << 12))
+#define TSC_PG_PRESC_DIV4   ((uint32_t)(2 << 12))
+#define TSC_PG_PRESC_DIV8   ((uint32_t)(3 << 12))
+#define TSC_PG_PRESC_DIV16  ((uint32_t)(4 << 12))
+#define TSC_PG_PRESC_DIV32  ((uint32_t)(5 << 12))
+#define TSC_PG_PRESC_DIV64  ((uint32_t)(6 << 12))
+#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
+/**
+  * @}
+  */
+
+/** @defgroup TSC_MaxCount_Value Max Count Value
+  * @{
+  */
+#define TSC_MCV_255   ((uint32_t)(0 << 5))
+#define TSC_MCV_511   ((uint32_t)(1 << 5))
+#define TSC_MCV_1023  ((uint32_t)(2 << 5))
+#define TSC_MCV_2047  ((uint32_t)(3 << 5))
+#define TSC_MCV_4095  ((uint32_t)(4 << 5))
+#define TSC_MCV_8191  ((uint32_t)(5 << 5))
+#define TSC_MCV_16383 ((uint32_t)(6 << 5))
+/**
+  * @}
+  */
+
+/** @defgroup TSC_IO_Default_Mode IO Default Mode
+  * @{
+  */
+#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
+#define TSC_IODEF_IN_FLOAT   (TSC_CR_IODEF)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
+  * @{
+  */
+#define TSC_SYNC_POLARITY_FALLING  ((uint32_t)0)
+#define TSC_SYNC_POLARITY_RISING   (TSC_CR_SYNCPOL)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_Acquisition_Mode Acquisition Mode
+  * @{
+  */
+#define TSC_ACQ_MODE_NORMAL  ((uint32_t)0)
+#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_IO_Mode IO Mode
+  * @{
+  */
+#define TSC_IOMODE_UNUSED   ((uint32_t)0)
+#define TSC_IOMODE_CHANNEL  ((uint32_t)1)
+#define TSC_IOMODE_SHIELD   ((uint32_t)2)
+#define TSC_IOMODE_SAMPLING ((uint32_t)3)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_interrupts_definition Interrupts definition
+  * @{
+  */
+#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
+#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_flags_definition Flags definition
+  * @{
+  */
+#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
+#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
+/**
+  * @}
+  */
+
+/** @defgroup TSC_Group_definition Group definition
+  * @{
+  */
+#define TSC_NB_OF_GROUPS (8)
+
+#define TSC_GROUP1 ((uint32_t)0x00000001)
+#define TSC_GROUP2 ((uint32_t)0x00000002)
+#define TSC_GROUP3 ((uint32_t)0x00000004)
+#define TSC_GROUP4 ((uint32_t)0x00000008)
+#define TSC_GROUP5 ((uint32_t)0x00000010)
+#define TSC_GROUP6 ((uint32_t)0x00000020)
+#define TSC_GROUP7 ((uint32_t)0x00000040)
+#define TSC_GROUP8 ((uint32_t)0x00000080)
+#define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
+
+#define TSC_GROUP1_IDX ((uint32_t)0)
+#define TSC_GROUP2_IDX ((uint32_t)1)
+#define TSC_GROUP3_IDX ((uint32_t)2)
+#define TSC_GROUP4_IDX ((uint32_t)3)
+#define TSC_GROUP5_IDX ((uint32_t)4)
+#define TSC_GROUP6_IDX ((uint32_t)5)
+#define TSC_GROUP7_IDX ((uint32_t)6)
+#define TSC_GROUP8_IDX ((uint32_t)7)
+
+#define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
+#define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
+#define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
+#define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
+#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
+
+#define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
+#define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
+#define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
+#define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
+#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
+
+#define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
+#define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
+#define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
+#define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
+#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
+
+#define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
+#define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
+#define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
+#define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
+#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
+
+#define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
+#define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
+#define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
+#define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
+#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
+
+#define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
+#define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
+#define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
+#define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
+#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
+
+#define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
+#define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
+#define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
+#define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
+#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
+
+#define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
+#define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
+#define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
+#define TSC_GROUP8_IO4 ((uint32_t)0x80000000)
+#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
+
+#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+  * @{
+  */
+
+/** @brief Reset TSC handle state.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+
+/**
+  * @brief Enable the TSC peripheral.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
+
+/**
+  * @brief Disable the TSC peripheral.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
+
+/**
+  * @brief Start acquisition.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
+
+/**
+  * @brief Stop acquisition.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
+
+/**
+  * @brief Set IO default mode to output push-pull low.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
+
+/**
+  * @brief Set IO default mode to input floating.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
+
+/**
+  * @brief Set synchronization polarity to falling edge.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
+
+/**
+  * @brief Set synchronization polarity to rising edge and high level.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
+
+/**
+  * @brief Enable TSC interrupt.
+  * @param  __HANDLE__: TSC handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief Disable TSC interrupt.
+  * @param  __HANDLE__: TSC handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
+
+/** @brief Check whether the specified TSC interrupt source is enabled or not.
+  * @param  __HANDLE__: TSC Handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief Check whether the specified TSC flag is set or not.
+  * @param  __HANDLE__: TSC handle
+  * @param  __FLAG__: TSC flag
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+  * @brief Clear the TSC's pending flag.
+  * @param  __HANDLE__: TSC handle
+  * @param  __FLAG__: TSC flag
+  * @retval None
+  */
+#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief Enable schmitt trigger hysteresis on a group of IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable schmitt trigger hysteresis on a group of IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Open analog switch on a group of IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Close analog switch on a group of IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Enable a group of IOs in channel mode.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable a group of channel IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Enable a group of IOs in sampling mode.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable a group of sampling IOs.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Enable acquisition groups.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_MASK__: Groups mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
+
+/**
+  * @brief Disable acquisition groups.
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_MASK__: Groups mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
+
+/** @brief Gets acquisition group status.
+  * @param  __HANDLE__: TSC Handle
+  * @param  __GX_INDEX__: Group index
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
+((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup TSC_Private_Macros TSC Private Macros
+  * @{
+  */
+
+#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
+                          ((VAL) == TSC_CTPH_2CYCLES) || \
+                          ((VAL) == TSC_CTPH_3CYCLES) || \
+                          ((VAL) == TSC_CTPH_4CYCLES) || \
+                          ((VAL) == TSC_CTPH_5CYCLES) || \
+                          ((VAL) == TSC_CTPH_6CYCLES) || \
+                          ((VAL) == TSC_CTPH_7CYCLES) || \
+                          ((VAL) == TSC_CTPH_8CYCLES) || \
+                          ((VAL) == TSC_CTPH_9CYCLES) || \
+                          ((VAL) == TSC_CTPH_10CYCLES) || \
+                          ((VAL) == TSC_CTPH_11CYCLES) || \
+                          ((VAL) == TSC_CTPH_12CYCLES) || \
+                          ((VAL) == TSC_CTPH_13CYCLES) || \
+                          ((VAL) == TSC_CTPH_14CYCLES) || \
+                          ((VAL) == TSC_CTPH_15CYCLES) || \
+                          ((VAL) == TSC_CTPH_16CYCLES))
+
+#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
+                          ((VAL) == TSC_CTPL_2CYCLES) || \
+                          ((VAL) == TSC_CTPL_3CYCLES) || \
+                          ((VAL) == TSC_CTPL_4CYCLES) || \
+                          ((VAL) == TSC_CTPL_5CYCLES) || \
+                          ((VAL) == TSC_CTPL_6CYCLES) || \
+                          ((VAL) == TSC_CTPL_7CYCLES) || \
+                          ((VAL) == TSC_CTPL_8CYCLES) || \
+                          ((VAL) == TSC_CTPL_9CYCLES) || \
+                          ((VAL) == TSC_CTPL_10CYCLES) || \
+                          ((VAL) == TSC_CTPL_11CYCLES) || \
+                          ((VAL) == TSC_CTPL_12CYCLES) || \
+                          ((VAL) == TSC_CTPL_13CYCLES) || \
+                          ((VAL) == TSC_CTPL_14CYCLES) || \
+                          ((VAL) == TSC_CTPL_15CYCLES) || \
+                          ((VAL) == TSC_CTPL_16CYCLES))
+
+#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
+
+#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
+
+#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
+                              ((VAL) == TSC_PG_PRESC_DIV2) || \
+                              ((VAL) == TSC_PG_PRESC_DIV4) || \
+                              ((VAL) == TSC_PG_PRESC_DIV8) || \
+                              ((VAL) == TSC_PG_PRESC_DIV16) || \
+                              ((VAL) == TSC_PG_PRESC_DIV32) || \
+                              ((VAL) == TSC_PG_PRESC_DIV64) || \
+                              ((VAL) == TSC_PG_PRESC_DIV128))
+
+#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
+                         ((VAL) == TSC_MCV_511) || \
+                         ((VAL) == TSC_MCV_1023) || \
+                         ((VAL) == TSC_MCV_2047) || \
+                         ((VAL) == TSC_MCV_4095) || \
+                         ((VAL) == TSC_MCV_8191) || \
+                         ((VAL) == TSC_MCV_16383))
+
+#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
+
+#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
+
+#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
+
+#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
+                            ((VAL) == TSC_IOMODE_CHANNEL) || \
+                            ((VAL) == TSC_IOMODE_SHIELD) || \
+                            ((VAL) == TSC_IOMODE_SAMPLING))
+
+#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TSC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
+void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* TSC IRQHandler and Callbacks used in Interrupt mode */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_TSC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_uart.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of UART HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -69,9 +69,9 @@ typedef struct
                                            - If oversampling is 16 or in LIN mode,
                                               Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
                                            - If oversampling is 8,
-                                           - -  Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
-                                           - -  Baud Rate Register[3] =  0
-                                           - -  Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
+                                              Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+                                              Baud Rate Register[3] =  0
+                                              Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
 
   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
                                            This parameter can be a value of @ref UARTEx_Word_Length. */
@@ -144,17 +144,62 @@ typedef struct
 
 /**
   * @brief HAL UART State structures definition
+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
   */
 typedef enum
 {
-  HAL_UART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized                      */
-  HAL_UART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_UART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_UART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
-  HAL_UART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_UART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
-  HAL_UART_STATE_ERROR             = 0x04     /*!< Error                                              */
+  HAL_UART_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_UART_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_ERROR             = 0xE0U    /*!< Error
+                                                   Value is allowed for gState only */
 }HAL_UART_StateTypeDef;
 
 /**
@@ -167,7 +212,8 @@ typedef enum
   HAL_UART_ERROR_NE        = 0x02,    /*!< Noise error         */
   HAL_UART_ERROR_FE        = 0x04,    /*!< frame error         */
   HAL_UART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
-  HAL_UART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
+  HAL_UART_ERROR_DMA       = 0x10,    /*!< DMA transfer error  */
+  HAL_UART_ERROR_BUSY      = 0x20     /*!< Busy Error          */
 }HAL_UART_ErrorTypeDef;
 
 /**
@@ -175,10 +221,10 @@ typedef enum
   */
 typedef enum
 {
-  UART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source  */
-  UART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source  */
-  UART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source    */
-  UART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source */
+  UART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
+  UART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
+  UART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
+  UART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
   UART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
   UART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
 }UART_ClockSourceTypeDef;
@@ -198,13 +244,13 @@ typedef struct
 
   uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */
 
-  uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
+  __IO uint16_t            TxXferCount;      /*!< UART Tx Transfer Counter           */
 
   uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
 
   uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */
 
-  uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
+  __IO uint16_t            RxXferCount;      /*!< UART Rx Transfer Counter           */
 
   uint16_t                 Mask;             /*!< UART Rx RDR register mask          */
 
@@ -214,7 +260,12 @@ typedef struct
 
   HAL_LockTypeDef           Lock;            /*!< Locking object                     */
 
-  __IO HAL_UART_StateTypeDef    State;       /*!< UART communication state           */
+  __IO HAL_UART_StateTypeDef    gState;      /*!< UART state information related to global Handle management
+                                                  and also related to Tx operations.
+                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.
+                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */
 
   __IO uint32_t             ErrorCode;       /*!< UART Error code                    */
 
@@ -264,14 +315,14 @@ typedef struct
 /** @defgroup UART_Mode UART Transfer Mode
   * @{
   */
-#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)                    /*!< RX mode        */ 
-#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)                    /*!< TX mode        */ 
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))    /*!< RX and TX mode */ 
+#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)                    /*!< RX mode        */
+#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)                    /*!< TX mode        */
+#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))    /*!< RX and TX mode */
 /**
   * @}
   */
 
- /** @defgroup UART_State  UART State
+/** @defgroup UART_State  UART State
   * @{
   */
 #define UART_STATE_DISABLE                  ((uint32_t)0x00000000)          /*!< UART disabled  */
@@ -301,9 +352,9 @@ typedef struct
 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
   * @{
   */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x0000)                /*!< Auto Baud rate detection on start bit            */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x00000000)            /*!< Auto Baud rate detection on start bit            */
 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)   /*!< Auto Baud rate detection on falling edge         */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)   /*!< Auto Baud rate detection on 0x7F frame detection */    
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)   /*!< Auto Baud rate detection on 0x7F frame detection */
 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)     /*!< Auto Baud rate detection on 0x55 frame detection */
 /**
   * @}
@@ -348,7 +399,7 @@ typedef struct
 /** @defgroup UART_DMA_Rx   UART DMA Rx
   * @{
   */
-#define UART_DMA_RX_DISABLE                 ((uint32_t)0x0000)                      /*!< UART DMA RX disabled */
+#define UART_DMA_RX_DISABLE                 ((uint32_t)0x00000000)                  /*!< UART DMA RX disabled */
 #define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)              /*!< UART DMA RX enabled  */
 /**
   * @}
@@ -357,7 +408,7 @@ typedef struct
 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
   * @{
   */
-#define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x0000)                      /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x00000000)                  /*!< UART half-duplex disabled */
 #define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)             /*!< UART half-duplex enabled  */
 /**
   * @}
@@ -412,8 +463,8 @@ typedef struct
 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
   * @{
   */
-#define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000)              /*!< RX pin active level inversion disable */ 
-#define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)         /*!< RX pin active level inversion enable  */ 
+#define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000)              /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)         /*!< RX pin active level inversion enable  */
 /**
   * @}
   */
@@ -439,8 +490,8 @@ typedef struct
 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
   * @{
   */
-#define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000)              /*!< RX overrun enable  */ 
-#define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */ 
+#define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000)              /*!< RX overrun enable  */
+#define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
 /**
   * @}
   */
@@ -448,8 +499,8 @@ typedef struct
 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
   * @{
   */
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000)           /*!< RX Auto Baud rate detection enable  */ 
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)      /*!< RX Auto Baud rate detection disable */ 
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000)           /*!< RX Auto Baud rate detection enable  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)      /*!< RX Auto Baud rate detection disable */
 /**
   * @}
   */
@@ -562,7 +613,7 @@ typedef struct
 #define UART_FLAG_CMF                       ((uint32_t)0x00020000)              /*!< UART character match flag                 */
 #define UART_FLAG_BUSY                      ((uint32_t)0x00010000)              /*!< UART busy flag                            */
 #define UART_FLAG_ABRF                      ((uint32_t)0x00008000)              /*!< UART auto Baud rate flag                  */
-#define UART_FLAG_ABRE                      ((uint32_t)0x00004000)              /*!< UART uto Baud rate error                  */
+#define UART_FLAG_ABRE                      ((uint32_t)0x00004000)              /*!< UART auto Baud rate error                 */
 #define UART_FLAG_EOBF                      ((uint32_t)0x00001000)              /*!< UART end of block flag                    */
 #define UART_FLAG_RTOF                      ((uint32_t)0x00000800)              /*!< UART receiver timeout flag                */
 #define UART_FLAG_CTS                       ((uint32_t)0x00000400)              /*!< UART clear to send flag                   */
@@ -590,29 +641,19 @@ typedef struct
   *           - ZZZZZ  : Flag position in the ISR register(5bits)
   * @{
   */
-#define UART_IT_PE                          ((uint32_t)0x0028)                  /*!< UART parity error interruption                 */    
-#define UART_IT_TXE                         ((uint32_t)0x0727)                  /*!< UART transmit data register empty interruption */    
-#define UART_IT_TC                          ((uint32_t)0x0626)                  /*!< UART transmission complete interruption        */    
-#define UART_IT_RXNE                        ((uint32_t)0x0525)                  /*!< UART read data register not empty interruption */    
-#define UART_IT_IDLE                        ((uint32_t)0x0424)                  /*!< UART idle interruption                         */                                                               
-#define UART_IT_LBD                         ((uint32_t)0x0846)                  /*!< UART LIN break detection interruption          */                
-#define UART_IT_CTS                         ((uint32_t)0x096A)                  /*!< UART CTS interruption                          */                
-#define UART_IT_CM                          ((uint32_t)0x112E)                  /*!< UART character match interruption              */                
-#define UART_IT_WUF                         ((uint32_t)0x1476)                  /*!< UART wake-up from stop mode interruption       */                
-                                                                                                     
-/*        Elements values convention: 000000000XXYYYYYb                                         
-              - YYYYY  : Interrupt source position in the XX register (5bits)                   
-              - XX  : Interrupt source register (2bits)
-                    - 01: CR1 register
-                    - 10: CR2 register
-                    - 11: CR3 register */
-#define UART_IT_ERR                         ((uint32_t)0x0060)                  /*!< UART error interruption         */   
-                                                                                  
-/*       Elements values convention: 0000ZZZZ00000000b                            
-             - ZZZZ  : Flag position in the ISR register(4bits) */                
-#define UART_IT_ORE                         ((uint32_t)0x0300)                  /*!< UART overrun error interruption */ 
-#define UART_IT_NE                          ((uint32_t)0x0200)                  /*!< UART noise error interruption   */ 
-#define UART_IT_FE                          ((uint32_t)0x0100)                  /*!< UART frame error interruption   */ 
+#define UART_IT_PE                          ((uint32_t)0x0028)                  /*!< UART parity error interruption                 */
+#define UART_IT_TXE                         ((uint32_t)0x0727)                  /*!< UART transmit data register empty interruption */
+#define UART_IT_TC                          ((uint32_t)0x0626)                  /*!< UART transmission complete interruption        */
+#define UART_IT_RXNE                        ((uint32_t)0x0525)                  /*!< UART read data register not empty interruption */
+#define UART_IT_IDLE                        ((uint32_t)0x0424)                  /*!< UART idle interruption                         */
+#define UART_IT_LBD                         ((uint32_t)0x0846)                  /*!< UART LIN break detection interruption          */
+#define UART_IT_CTS                         ((uint32_t)0x096A)                  /*!< UART CTS interruption                          */
+#define UART_IT_CM                          ((uint32_t)0x112E)                  /*!< UART character match interruption              */
+#define UART_IT_WUF                         ((uint32_t)0x1476)                  /*!< UART wake-up from stop mode interruption       */
+#define UART_IT_ERR                         ((uint32_t)0x0060)                  /*!< UART error interruption         */
+#define UART_IT_ORE                         ((uint32_t)0x0300)                  /*!< UART overrun error interruption */
+#define UART_IT_NE                          ((uint32_t)0x0200)                  /*!< UART noise error interruption   */
+#define UART_IT_FE                          ((uint32_t)0x0100)                  /*!< UART frame error interruption   */
 /**
   * @}
   */
@@ -646,15 +687,17 @@ typedef struct
   * @{
   */
 
-/** @brief Reset UART handle state.
+/** @brief  Reset UART handle states.
   * @param  __HANDLE__: UART handle.
   * @retval None
   */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
-
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0)
 /** @brief  Flush the UART Data registers.
   * @param  __HANDLE__: specifies the UART Handle.
-  * @retval None  
+  * @retval None
   */
 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
   do{                \
@@ -666,18 +709,18 @@ typedef struct
   * @param  __HANDLE__: specifies the UART Handle.
   * @param  __FLAG__: specifies the flag to check.
   *          This parameter can be any combination of the following values:
-  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag           
-  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag          
-  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag         
-  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag          
-  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag     
-  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag  
-  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag    
-  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag          
-  *            @arg @ref UART_CLEAR_RTOF     Receiver Time Out Clear Flag      
-  *            @arg @ref UART_CLEAR_EOBF     End Of Block Clear Flag           
-  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag        
-  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag 
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Time Out Clear Flag
+  *            @arg @ref UART_CLEAR_EOBF     End Of Block Clear Flag
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
   * @retval None
   */
 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -795,8 +838,8 @@ typedef struct
   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
   *            @arg @ref UART_IT_ORE  Overrun Error interrupt
-  *            @arg @ref UART_IT_NE   Noise Error interrupt   
-  *            @arg @ref UART_IT_FE   Framing Error interrupt   
+  *            @arg @ref UART_IT_NE   Noise Error interrupt
+  *            @arg @ref UART_IT_FE   Framing Error interrupt
   *            @arg @ref UART_IT_PE   Parity Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
@@ -807,7 +850,7 @@ typedef struct
   * @param  __IT__: specifies the UART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
-  *            @arg @ref UART_IT_CM   Character match interrupt  
+  *            @arg @ref UART_IT_CM   Character match interrupt
   *            @arg @ref UART_IT_CTS  CTS change interrupt
   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
@@ -834,6 +877,8 @@ typedef struct
   *            @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
   *            @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
   *            @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
+  *            @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
   *            @arg @ref UART_CLEAR_CMF Character Match Clear Flag
   *            @arg @ref UART_CLEAR_WUF  Wake Up from stop mode Clear Flag
   * @retval None
@@ -854,15 +899,15 @@ typedef struct
 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
 
 /** @brief  Enable the UART one bit sample method.
-  * @param  __HANDLE__: specifies the UART Handle.  
+  * @param  __HANDLE__: specifies the UART Handle.
   * @retval None
-  */     
+  */
 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Disable the UART one bit sample method.
-  * @param  __HANDLE__: specifies the UART Handle.  
+  * @param  __HANDLE__: specifies the UART Handle.
   * @retval None
-  */      
+  */
 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART.
@@ -878,14 +923,14 @@ typedef struct
 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
 
 /** @brief  Enable CTS flow control.
-  * @note   This macro allows to enable CTS hardware flow control for a given UART instance, 
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
   * @param  __HANDLE__: specifies the UART Handle.
   * @retval None
   */
@@ -896,14 +941,14 @@ typedef struct
   } while(0)
 
 /** @brief  Disable CTS flow control.
-  * @note   This macro allows to disable CTS hardware flow control for a given UART instance, 
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
   * @param  __HANDLE__: specifies the UART Handle.
   * @retval None
   */
@@ -914,14 +959,14 @@ typedef struct
   } while(0)
 
 /** @brief  Enable RTS flow control.
-  * @note   This macro allows to enable RTS hardware flow control for a given UART instance, 
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
   * @param  __HANDLE__: specifies the UART Handle.
   * @retval None
   */
@@ -932,14 +977,14 @@ typedef struct
   } while(0)
 
 /** @brief  Disable RTS flow control.
-  * @note   This macro allows to disable RTS hardware flow control for a given UART instance, 
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). 
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
   * @param  __HANDLE__: specifies the UART Handle.
   * @retval None
   */
@@ -962,21 +1007,21 @@ typedef struct
   * @param  __BAUD__: Baud rate set by the user.
   * @retval Division result
   */
-#define UART_DIV_LPUART(__PCLK__, __BAUD__)                (((uint64_t)(__PCLK__)*256)/((__BAUD__)))
+#define UART_DIV_LPUART(__PCLK__, __BAUD__)      ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__))
 
 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
   * @param  __PCLK__: UART clock.
   * @param  __BAUD__: Baud rate set by the user.
   * @retval Division result
   */
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)             (((__PCLK__)*2)/((__BAUD__)))
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__))
 
 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
   * @param  __PCLK__: UART clock.
   * @param  __BAUD__: Baud rate set by the user.
   * @retval Division result
   */
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)             (((__PCLK__))/((__BAUD__)))
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__))
 
 /** @brief  Check whether or not UART instance is Low Power UART.
   * @param  __HANDLE__: specifies the UART Handle.
@@ -1006,8 +1051,8 @@ typedef struct
 
 /**
   * @brief Ensure that UART frame number of stop bits is valid.
-  * @param __STOPBITS__: UART frame number of stop bits. 
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)  UART_STOPBITS_1_5
+  * @param __STOPBITS__: UART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
   */
 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
                                         ((__STOPBITS__) == UART_STOPBITS_1)   || \
@@ -1016,26 +1061,26 @@ typedef struct
 
 /**
   * @brief Ensure that LPUART frame number of stop bits is valid.
-  * @param __STOPBITS__: LPUART frame number of stop bits. 
+  * @param __STOPBITS__: LPUART frame number of stop bits.
   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
-  */ 
+  */
 #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
                                           ((__STOPBITS__) == UART_STOPBITS_2))
 
 /**
   * @brief Ensure that UART frame parity is valid.
-  * @param __PARITY__: UART frame parity. 
+  * @param __PARITY__: UART frame parity.
   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
-  */ 
+  */
 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
                                     ((__PARITY__) == UART_PARITY_EVEN) || \
                                     ((__PARITY__) == UART_PARITY_ODD))
 
 /**
   * @brief Ensure that UART hardware flow control is valid.
-  * @param __CONTROL__: UART hardware flow control. 
+  * @param __CONTROL__: UART hardware flow control.
   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
-  */ 
+  */
 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
                                    (((__CONTROL__) == UART_HWCONTROL_NONE) || \
                                     ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
@@ -1044,30 +1089,30 @@ typedef struct
 
 /**
   * @brief Ensure that UART communication mode is valid.
-  * @param __MODE__: UART communication mode. 
+  * @param __MODE__: UART communication mode.
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */ 
+  */
 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
 
 /**
   * @brief Ensure that UART state is valid.
-  * @param __STATE__: UART state. 
+  * @param __STATE__: UART state.
   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
-  */ 
+  */
 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
                                   ((__STATE__) == UART_STATE_ENABLE))
 
 /**
   * @brief Ensure that UART oversampling is valid.
-  * @param __SAMPLING__: UART oversampling. 
+  * @param __SAMPLING__: UART oversampling.
   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
-  */ 
+  */
 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
                                             ((__SAMPLING__) == UART_OVERSAMPLING_8))
 
 /**
   * @brief Ensure that UART frame sampling is valid.
-  * @param __ONEBIT__: UART frame sampling. 
+  * @param __ONEBIT__: UART frame sampling.
   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
   */
 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
@@ -1075,7 +1120,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART auto Baud rate detection mode is valid.
-  * @param __MODE__: UART auto Baud rate detection mode. 
+  * @param __MODE__: UART auto Baud rate detection mode.
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */
 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
@@ -1085,7 +1130,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART receiver timeout setting is valid.
-  * @param __TIMEOUT__: UART receiver timeout setting. 
+  * @param __TIMEOUT__: UART receiver timeout setting.
   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
   */
 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
@@ -1093,7 +1138,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART LIN state is valid.
-  * @param __LIN__: UART LIN state. 
+  * @param __LIN__: UART LIN state.
   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
   */
 #define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
@@ -1101,7 +1146,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART LIN break detection length is valid.
-  * @param __LENGTH__: UART LIN break detection length. 
+  * @param __LENGTH__: UART LIN break detection length.
   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
   */
 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
@@ -1109,7 +1154,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART DMA TX state is valid.
-  * @param __DMATX__: UART DMA TX state. 
+  * @param __DMATX__: UART DMA TX state.
   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
   */
 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
@@ -1117,7 +1162,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART DMA RX state is valid.
-  * @param __DMARX__: UART DMA RX state. 
+  * @param __DMARX__: UART DMA RX state.
   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
   */
 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
@@ -1125,7 +1170,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART half-duplex state is valid.
-  * @param __HDSEL__: UART half-duplex state. 
+  * @param __HDSEL__: UART half-duplex state.
   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
   */
 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
@@ -1133,7 +1178,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART wake-up method is valid.
-  * @param __WAKEUP__: UART wake-up method . 
+  * @param __WAKEUP__: UART wake-up method .
   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
   */
 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
@@ -1141,7 +1186,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART request parameter is valid.
-  * @param __PARAM__: UART request parameter. 
+  * @param __PARAM__: UART request parameter.
   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
   */
 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
@@ -1152,7 +1197,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART advanced features initialization is valid.
-  * @param __INIT__: UART advanced features initialization. 
+  * @param __INIT__: UART advanced features initialization.
   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
   */
 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
@@ -1167,7 +1212,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART frame TX inversion setting is valid.
-  * @param __TXINV__: UART frame TX inversion setting. 
+  * @param __TXINV__: UART frame TX inversion setting.
   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
   */
 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
@@ -1175,7 +1220,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART frame RX inversion setting is valid.
-  * @param __RXINV__: UART frame RX inversion setting. 
+  * @param __RXINV__: UART frame RX inversion setting.
   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
   */
 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
@@ -1183,7 +1228,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART frame data inversion setting is valid.
-  * @param __DATAINV__: UART frame data inversion setting. 
+  * @param __DATAINV__: UART frame data inversion setting.
   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
   */
 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
@@ -1191,7 +1236,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
-  * @param __SWAP__: UART frame RX/TX pins swap setting. 
+  * @param __SWAP__: UART frame RX/TX pins swap setting.
   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
   */
 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
@@ -1199,7 +1244,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART frame overrun setting is valid.
-  * @param __OVERRUN__: UART frame overrun setting. 
+  * @param __OVERRUN__: UART frame overrun setting.
   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
   */
 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
@@ -1207,7 +1252,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART auto Baud rate state is valid.
-  * @param __AUTOBAUDRATE__: UART auto Baud rate state. 
+  * @param __AUTOBAUDRATE__: UART auto Baud rate state.
   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
   */
 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
@@ -1215,7 +1260,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
-  * @param __DMA__: UART DMA enabling or disabling on error setting. 
+  * @param __DMA__: UART DMA enabling or disabling on error setting.
   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
   */
 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
@@ -1223,7 +1268,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART frame MSB first setting is valid.
-  * @param __MSBFIRST__: UART frame MSB first setting. 
+  * @param __MSBFIRST__: UART frame MSB first setting.
   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
   */
 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
@@ -1231,7 +1276,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART stop mode state is valid.
-  * @param __STOPMODE__: UART stop mode state. 
+  * @param __STOPMODE__: UART stop mode state.
   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
   */
 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
@@ -1239,7 +1284,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART mute mode state is valid.
-  * @param __MUTE__: UART mute mode state. 
+  * @param __MUTE__: UART mute mode state.
   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
   */
 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
@@ -1247,7 +1292,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART wake-up selection is valid.
-  * @param __WAKE__: UART wake-up selection. 
+  * @param __WAKE__: UART wake-up selection.
   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
   */
 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
@@ -1256,7 +1301,7 @@ typedef struct
 
 /**
   * @brief Ensure that UART driver enable polarity is valid.
-  * @param __POLARITY__: UART driver enable polarity. 
+  * @param __POLARITY__: UART driver enable polarity.
   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
   */
 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
@@ -1305,12 +1350,23 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
 
 /**
   * @}
@@ -1355,7 +1411,7 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
 
 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
 
 /**

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l4xx_hal_uart_ex.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    29-January-2016
+  * @version V1.7.1
+  * @date    21-April-2017
   * @brief   Header file of UART HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -155,6 +155,7 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
   * @param  __CLOCKSOURCE__: output variable.
   * @retval UART clocking source, written in __CLOCKSOURCE__.
   */
+#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
   do {                                                        \
     if((__HANDLE__)->Instance == USART1)                      \
@@ -284,6 +285,271 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
        }                                                      \
     }                                                         \
   } while(0)
+#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L432xx) || defined (STM32L442xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
+       {                                                      \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#endif
 
 /** @brief  Report the UART mask to apply to retrieve the received data
   *         according to the word length and to the parity bits activation.
@@ -334,7 +600,7 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
 
 /**
   * @brief Ensure that UART frame length is valid.
-  * @param __LENGTH__: UART frame length. 
+  * @param __LENGTH__: UART frame length.
   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
   */
 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
@@ -343,7 +609,7 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
 
 /**
   * @brief Ensure that UART wake-up address length is valid.
-  * @param __ADDRESS__: UART wake-up address length. 
+  * @param __ADDRESS__: UART wake-up address length.
   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
   */
 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h

@@ -0,0 +1,718 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_usart.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of USART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_USART_H
+#define __STM32L4xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+  * @{
+  */
+
+/**
+  * @brief USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USARTEx_Word_Length. */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits. */
+
+  uint32_t Parity;                   /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode. */
+
+  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_Clock_Polarity. */
+
+  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_Clock_Phase. */
+
+  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_Last_Bit. */
+}USART_InitTypeDef;
+
+/**
+  * @brief HAL USART State structures definition
+  */
+typedef enum
+{
+  HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized                  */
+  HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use       */
+  HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                 */
+  HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing           */
+  HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing              */
+  HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
+  HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                  */
+  HAL_USART_STATE_ERROR             = 0x04     /*!< Error                                          */
+}HAL_USART_StateTypeDef;
+
+/**
+  * @brief  HAL USART Error Code structure definition
+  */
+typedef enum
+{
+  HAL_USART_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_USART_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_USART_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_USART_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_USART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_USART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
+}HAL_USART_ErrorTypeDef;
+
+/**
+  * @brief  USART clock sources definitions
+  */
+typedef enum
+{
+  USART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
+  USART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
+  USART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
+  USART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
+  USART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
+  USART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
+}USART_ClockSourceTypeDef;
+
+
+/**
+  * @brief  USART handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef                 *Instance;        /*!< USART registers base address        */
+
+  USART_InitTypeDef             Init;             /*!< USART communication parameters      */
+
+  uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */
+
+  uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */
+
+  __IO uint16_t                 TxXferCount;      /*!< USART Tx Transfer Counter           */
+
+  uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */
+
+  uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */
+
+  __IO uint16_t                 RxXferCount;      /*!< USART Rx Transfer Counter           */
+
+  uint16_t                      Mask;             /*!< USART Rx RDR register mask          */
+
+  DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef               Lock;             /*!< Locking object                      */
+
+  __IO HAL_USART_StateTypeDef   State;            /*!< USART communication state           */
+
+  __IO uint32_t                 ErrorCode;        /*!< USART Error code                    */
+
+}USART_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_Stop_Bits  USART Number of Stop Bits
+  * @{
+  */
+#define USART_STOPBITS_0_5                   USART_CR2_STOP_0                      /*!< USART frame with 0.5 stop bit  */
+#define USART_STOPBITS_1                     ((uint32_t)0x00000000)                /*!< USART frame with 1 stop bit    */
+#define USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
+#define USART_STOPBITS_2                     USART_CR2_STOP_1                      /*!< USART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Parity    USART Parity
+  * @{
+  */
+#define USART_PARITY_NONE                   ((uint32_t)0x00000000)                      /*!< No parity   */
+#define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
+#define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Mode   USART Mode
+  * @{
+  */
+#define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
+#define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
+#define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Over_Sampling USART Over Sampling
+  * @{
+  */
+#define USART_OVERSAMPLING_16               ((uint32_t)0x00000000)          /*!< Oversampling by 16 */
+#define USART_OVERSAMPLING_8                ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock  USART Clock
+  * @{
+  */
+#define USART_CLOCK_DISABLE                 ((uint32_t)0x00000000)        /*!< USART clock disable */
+#define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)   /*!< USART clock enable  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Polarity  USART Clock Polarity
+  * @{
+  */
+#define USART_POLARITY_LOW                  ((uint32_t)0x00000000)       /*!< USART Clock signal is steady Low */
+#define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)   /*!< USART Clock signal is steady High  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Phase   USART Clock Phase
+  * @{
+  */
+#define USART_PHASE_1EDGE                   ((uint32_t)0x00000000)       /*!< USART frame phase on first clock transition  */
+#define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)   /*!< USART frame phase on second clock transition */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit  USART Last Bit
+  * @{
+  */
+#define USART_LASTBIT_DISABLE               ((uint32_t)0x00000000)       /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)   /*!< USART frame last data bit clock pulse output to SCLK pin     */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Request_Parameters  USART Request Parameters
+  * @{
+  */
+#define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
+#define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Flags      USART Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define USART_FLAG_REACK                     ((uint32_t)0x00400000)    /*!< USART receive enable acknowledge flag  */
+#define USART_FLAG_TEACK                     ((uint32_t)0x00200000)    /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY                      ((uint32_t)0x00010000)    /*!< USART busy flag                        */
+#define USART_FLAG_CTS                       ((uint32_t)0x00000400)    /*!< USART clear to send flag               */
+#define USART_FLAG_CTSIF                     ((uint32_t)0x00000200)    /*!< USART clear to send interrupt flag     */
+#define USART_FLAG_LBDF                      ((uint32_t)0x00000100)    /*!< USART LIN break detection flag         */
+#define USART_FLAG_TXE                       ((uint32_t)0x00000080)    /*!< USART transmit data register empty     */
+#define USART_FLAG_TC                        ((uint32_t)0x00000040)    /*!< USART transmission complete            */
+#define USART_FLAG_RXNE                      ((uint32_t)0x00000020)    /*!< USART read data register not empty     */
+#define USART_FLAG_IDLE                      ((uint32_t)0x00000010)    /*!< USART idle flag                        */
+#define USART_FLAG_ORE                       ((uint32_t)0x00000008)    /*!< USART overrun error                    */
+#define USART_FLAG_NE                        ((uint32_t)0x00000004)    /*!< USART noise error                      */
+#define USART_FLAG_FE                        ((uint32_t)0x00000002)    /*!< USART frame error                      */
+#define USART_FLAG_PE                        ((uint32_t)0x00000001)    /*!< USART parity error                     */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+
+#define USART_IT_PE                          ((uint16_t)0x0028)     /*!< USART parity error interruption                 */
+#define USART_IT_TXE                         ((uint16_t)0x0727)     /*!< USART transmit data register empty interruption */
+#define USART_IT_TC                          ((uint16_t)0x0626)     /*!< USART transmission complete interruption        */
+#define USART_IT_RXNE                        ((uint16_t)0x0525)     /*!< USART read data register not empty interruption */
+#define USART_IT_IDLE                        ((uint16_t)0x0424)     /*!< USART idle interruption                         */
+#define USART_IT_ERR                         ((uint16_t)0x0060)     /*!< USART error interruption                        */
+#define USART_IT_ORE                         ((uint16_t)0x0300)     /*!< USART overrun error interruption                */
+#define USART_IT_NE                          ((uint16_t)0x0200)     /*!< USART noise error interruption                  */
+#define USART_IT_FE                          ((uint16_t)0x0100)     /*!< USART frame error interruption                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
+  * @{
+  */
+#define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
+#define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
+#define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
+#define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
+#define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
+#define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
+  * @{
+  */
+#define USART_IT_MASK                             ((uint16_t)0x001F)     /*!< USART interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @brief Reset USART handle state.
+  * @param  __HANDLE__: USART handle.
+  * @retval None
+  */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief  Check whether the specified USART flag is set or not.
+  * @param  __HANDLE__: specifies the USART Handle
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref USART_FLAG_BUSY  Busy flag
+  *            @arg @ref USART_FLAG_CTS   CTS Change flag
+  *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref USART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref USART_FLAG_ORE   OverRun Error flag
+  *            @arg @ref USART_FLAG_NE    Noise Error flag
+  *            @arg @ref USART_FLAG_FE    Framing Error flag
+  *            @arg @ref USART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified USART pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref USART_CLEAR_PEF
+  *            @arg @ref USART_CLEAR_FEF
+  *            @arg @ref USART_CLEAR_NEF
+  *            @arg @ref USART_CLEAR_OREF
+  *            @arg @ref USART_CLEAR_IDLEF
+  *            @arg @ref USART_CLEAR_TCF
+  *            @arg @ref USART_CLEAR_CTSF
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the USART PE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief  Clear the USART FE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief  Clear the USART NE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief  Clear the USART ORE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief  Clear the USART IDLE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+/** @brief  Enable the specified USART interrupt.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC   Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_PE   Parity Error interrupt
+  *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & 0xFF) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((((__INTERRUPT__) & 0xFF) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief  Disable the specified USART interrupt.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC   Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_PE   Parity Error interrupt
+  *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & 0xFF) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((((__INTERRUPT__) & 0xFF) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+
+/** @brief  Check whether the specified USART interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT__: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC  Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_ORE OverRun Error interrupt
+  *            @arg @ref USART_IT_NE Noise Error interrupt
+  *            @arg @ref USART_IT_FE Framing Error interrupt
+  *            @arg @ref USART_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief  Check whether the specified USART interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT__: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC  Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_ORE OverRun Error interrupt
+  *            @arg @ref USART_IT_NE Noise Error interrupt
+  *            @arg @ref USART_IT_FE Framing Error interrupt
+  *            @arg @ref USART_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
+                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
+                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))
+
+
+/** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+  *            @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+  *            @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+  *            @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
+  *            @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+  *            @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+  *            @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific USART request flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __REQ__: specifies the request flag to set.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (__REQ__))
+
+/** @brief  Enable the USART one bit sample method.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the USART one bit sample method.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable USART.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable USART.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros   USART Private Macros
+  * @{
+  */
+
+/** @brief  Check USART Baud rate.
+  * @param  __BAUDRATE__: Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8).
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
+
+/**
+  * @brief Ensure that USART frame number of stop bits is valid.
+  * @param __STOPBITS__: USART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
+                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
+                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
+                                         ((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+  * @brief Ensure that USART frame parity is valid.
+  * @param __PARITY__: USART frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
+                                     ((__PARITY__) == USART_PARITY_EVEN) || \
+                                     ((__PARITY__) == USART_PARITY_ODD))
+
+/**
+  * @brief Ensure that USART communication mode is valid.
+  * @param __MODE__: USART communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))
+
+/**
+  * @brief Ensure that USART oversampling is valid.
+  * @param __SAMPLING__: USART oversampling.
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that USART clock state is valid.
+  * @param __CLOCK__: USART clock state.
+  * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+  */
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+                                   ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+  * @brief Ensure that USART frame polarity is valid.
+  * @param __CPOL__: USART frame polarity.
+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+  */
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+  * @brief Ensure that USART frame phase is valid.
+  * @param __CPHA__: USART frame phase.
+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+  */
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
+
+/**
+  * @brief Ensure that USART frame last bit clock pulse setting is valid.
+  * @param __LASTBIT__: USART frame last bit clock pulse setting.
+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+  */
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
+                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))
+
+/**
+  * @brief Ensure that USART request parameter is valid.
+  * @param __PARAM__: USART request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @}
+  */
+
+/* Include USART HAL Extended module */
+#include "stm32l4xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+
+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h

@@ -0,0 +1,280 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_usart_ex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of USART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_USART_EX_H
+#define __STM32L4xx_HAL_USART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup USARTEx_Word_Length USARTEx Word Length
+  * @{
+  */
+#define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the USART clock source.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval the USART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L432xx) || defined (STM32L442xx)
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#else
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART3)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+       {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#endif /* STM32L432xx || STM32L442xx */
+
+/** @brief  Compute the USART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define USART_MASK_COMPUTATION(__HANDLE__)                            \
+  do {                                                                \
+  if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x01FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x003F ;                                 \
+     }                                                                \
+  }                                                                   \
+} while(0)
+
+
+/**
+  * @brief Ensure that USART frame length is valid.
+  * @param __LENGTH__: USART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
+                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
+                                          ((__LENGTH__) == USART_WORDLENGTH_9B))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_USART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h

@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of WWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_WWDG_H
+#define __STM32L4xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+  * @{
+  */
+
+/**
+  * @brief  WWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
+                               This parameter can be a value of @ref WWDG_Prescaler */
+
+  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
+                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
+                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+                               This parameter can be a value of @ref WWDG_EWI_Mode */
+
+}WWDG_InitTypeDef;
+
+/**
+  * @brief  WWDG handle Structure definition
+  */
+typedef struct
+{
+  WWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
+  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
+
+}WWDG_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+  * @{
+  */
+#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+  * @brief WWDG Flag definition
+  * @{
+  */
+#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+  * @{
+  */
+#define WWDG_PRESCALER_1                    0x00000000u       /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8                    WWDG_CFR_WDGTB    /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+  * @{
+  */
+#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
+#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+  * @{
+  */
+#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_8))
+
+#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
+                                             ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+  * @}
+  */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the WWDG peripheral.
+  * @param  __HANDLE__  WWDG handle
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+
+/**
+  * @brief  Enable the WWDG early wakeup interrupt.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt to enable.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early wakeup interrupt
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the selected WWDG interrupt has occurred or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the it to check.
+  *        This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief  Clear the WWDG interrupt pending bits.
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified WWDG flag is set or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the WWDG's pending flags.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval None
+  */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief  Check whether the specified WWDG interrupt source is enabled or not.
+  * @param  __HANDLE__  WWDG Handle.
+  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
+  * @retval state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup WWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/**
+  * @}
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h

@@ -0,0 +1,896 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_comp.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of COMP LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_COMP_H
+#define __STM32L4xx_LL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @defgroup COMP_LL COMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Constants COMP Private Constants
+  * @{
+  */
+
+/* COMP registers bits positions */
+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of COMP instance.
+  */
+typedef struct
+{
+  uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
+                                             This parameter can be a value of @ref COMP_LL_EC_POWERMODE
+
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
+
+  uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
+
+  uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
+
+  uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
+
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
+
+  uint32_t OutputPolarity;              /*!< Set comparator output polarity.
+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
+
+  uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
+
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
+  * @{
+  */
+#define LL_COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)      /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
+  * @{
+  */
+#define LL_COMP_POWERMODE_HIGHSPEED     ((uint32_t)0x00000000U)                   /*!< COMP power mode to high speed */
+#define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CSR_PWRMODE_0)                      /*!< COMP power mode to medium speed */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+  * @{
+  */
+#define LL_COMP_INPUT_PLUS_IO1          ((uint32_t)0x00000000U)                 /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
+#define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_INPSEL_0)                     /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
+#if defined(COMP_CSR_INPSEL_1)
+#define LL_COMP_INPUT_PLUS_IO3          (COMP_CSR_INPSEL_1)                     /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+  * @{
+  */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT  (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt  */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt  */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT  (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt  */
+#define LL_COMP_INPUT_MINUS_VREFINT     (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_COMP_INPUT_MINUS_DAC1_CH2    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
+#endif
+#define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
+#if defined(COMP_CSR_INMESEL_1)
+#define LL_COMP_INPUT_MINUS_IO3         (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO4         (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO5         (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_LEGACY Comparator inputs legacy literals name
+  * @{
+  */
+#define LL_COMP_WINDOWMODE_ENABLE         LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define LL_COMP_INVERTINGINPUT_1_4VREFINT LL_COMP_INPUT_MINUS_1_4VREFINT
+#define LL_COMP_INVERTINGINPUT_1_2VREFINT LL_COMP_INPUT_MINUS_1_2VREFINT
+#define LL_COMP_INVERTINGINPUT_3_4VREFINT LL_COMP_INPUT_MINUS_3_4VREFINT
+#define LL_COMP_INVERTINGINPUT_VREFINT    LL_COMP_INPUT_MINUS_VREFINT
+#define LL_COMP_INVERTINGINPUT_DAC1       LL_COMP_INPUT_MINUS_DAC1_CH1
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_COMP_INVERTINGINPUT_DAC2       LL_COMP_INPUT_MINUS_DAC1_CH2
+#endif
+#define LL_COMP_INVERTINGINPUT_IO1        LL_COMP_INPUT_MINUS_IO1
+#define LL_COMP_INVERTINGINPUT_IO2        LL_COMP_INPUT_MINUS_IO2
+#if defined(COMP_CSR_INMESEL_1)
+#define LL_COMP_INVERTINGINPUT_IO3        LL_COMP_INPUT_MINUS_IO3
+#define LL_COMP_INVERTINGINPUT_IO4        LL_COMP_INPUT_MINUS_IO4
+#define LL_COMP_INVERTINGINPUT_IO5        LL_COMP_INPUT_MINUS_IO5
+#endif
+
+#define LL_COMP_NONINVERTINGINPUT_IO1     LL_COMP_INPUT_PLUS_IO1
+#define LL_COMP_NONINVERTINGINPUT_IO2     LL_COMP_INPUT_PLUS_IO2
+#if defined(COMP_CSR_INPSEL_1)
+#define LL_COMP_NONINVERTINGINPUT_IO3     LL_COMP_INPUT_PLUS_IO3
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
+  * @{
+  */
+#define LL_COMP_HYSTERESIS_NONE         ((uint32_t)0x00000000U)             /*!< No hysteresis */
+#define LL_COMP_HYSTERESIS_LOW          (                  COMP_CSR_HYST_0) /*!< Hysteresis level low */
+#define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CSR_HYST_1                  ) /*!< Hysteresis level medium */
+#define LL_COMP_HYSTERESIS_HIGH         (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+  * @{
+  */
+#define LL_COMP_OUTPUTPOL_NONINVERTED   ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_POLARITY)     /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
+  * @{
+  */
+#define LL_COMP_BLANKINGSRC_NONE            ((uint32_t)0x00000000U) /*!<Comparator output without blanking */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1) */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP2) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE_LEGACY Comparator output blanking source legacy literals name
+  * @{
+  */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5    (LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)
+#define LL_COMP_BLANKINGSRC_TIM2_OC3    (LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)
+#define LL_COMP_BLANKINGSRC_TIM3_OC3    (LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)
+
+#define LL_COMP_BLANKINGSRC_TIM3_OC4    (LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)
+#define LL_COMP_BLANKINGSRC_TIM8_OC5    (LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)
+#define LL_COMP_BLANKINGSRC_TIM15_OC1   (LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
+  * @{
+  */
+#define LL_COMP_OUTPUT_LEVEL_LOW        ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH       ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
+  * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Delay for comparator startup time.                                         */
+/* Note: Delay required to reach propagation delay specification.             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_COMP_DELAY_STARTUP_US          ((uint32_t) 80U)  /*!< Delay for COMP startup time */
+
+/* Delay for comparator voltage scaler stabilization time.                    */
+/* Note: Voltage scaler is used when selecting comparator input               */
+/*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART_SCALER").                                                */
+/* Unit: us                                                                   */
+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)  /*!< Delay for COMP voltage scaler stabilization time */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
+  * @{
+  */
+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
+  * @{
+  */
+
+/**
+  * @brief  Write a value in COMP register
+  * @param  __INSTANCE__ comparator instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in COMP register
+  * @param  __INSTANCE__ comparator instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to select the COMP common instance
+  *         to which is belonging the selected COMP instance.
+  * @note   COMP common register instance can be used to
+  *         set parameters common to several COMP instances.
+  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
+  * @param  __COMPx__ COMP instance
+  * @retval COMP common instance or value "0" if there is no COMP common instance.
+  */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
+  (COMP12_COMMON)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+  * @{
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
+  * @{
+  */
+
+/**
+  * @brief  Set window mode of a pair of comparators instances
+  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+  * @rmtoll CSR      WINMODE        LL_COMP_SetCommonWindowMode
+  * @param  COMPxy_COMMON Comparator common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+  * @param  WindowMode This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
+  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
+{
+  /* Note: On this STM32 serie, window mode can be set only                   */
+  /*       from COMP instance: COMP2.                                         */
+  MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode);
+}
+
+/**
+  * @brief  Get window mode of a pair of comparators instances
+  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+  * @rmtoll CSR      WINMODE        LL_COMP_GetCommonWindowMode
+  * @param  COMPxy_COMMON Comparator common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
+  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
+  * @{
+  */
+
+/**
+  * @brief  Set comparator instance operating mode to adjust power and speed.
+  * @rmtoll CSR      PWRMODE        LL_COMP_SetPowerMode
+  * @param  COMPx Comparator instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode);
+}
+
+/**
+  * @brief  Get comparator instance operating mode to adjust power and speed.
+  * @rmtoll CSR      PWRMODE        LL_COMP_GetPowerMode
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+  * @{
+  */
+
+/**
+  * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   On this STM32 serie, scaler bridge is configurable:
+  *         to optimize power consumption, this function enables the
+  *         voltage scaler bridge only when required
+  *         (when selecting comparator input based on VrefInt: VrefInt or
+  *         subdivision of VrefInt).
+  *         - For scaler bridge power consumption values,
+  *           refer to device datasheet, parameter "IDDA(SCALER)".
+  *         - Voltage scaler requires a delay for voltage stabilization.
+  *           Refer to device datasheet, parameter "tSTART_SCALER".
+  *         - Scaler bridge is common for all comparator instances,
+  *           therefore if at least one of the comparator instance
+  *           is requiring the scaler bridge, it remains enabled.
+  * @rmtoll CSR      INMSEL         LL_COMP_ConfigInputs\n
+  *         CSR      INPSEL         LL_COMP_ConfigInputs\n
+  *         CSR      BRGEN          LL_COMP_ConfigInputs\n
+  *         CSR      SCALEN         LL_COMP_ConfigInputs
+  * @param  COMPx Comparator instance
+  * @param  InputMinus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
+  *
+  *         (*) Parameter not available on all devices.
+  * @param  InputPlus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
+  *
+  *         (*) Parameter not available on all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+#if defined(COMP_CSR_INMESEL_1)
+  MODIFY_REG(COMPx->CSR,
+             COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
+             InputMinus | InputPlus);
+#else
+  MODIFY_REG(COMPx->CSR,
+             COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
+             InputMinus | InputPlus);
+#endif
+}
+
+/**
+  * @brief  Set comparator input plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INPSEL         LL_COMP_SetInputPlus
+  * @param  COMPx Comparator instance
+  * @param  InputPlus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
+  *
+  *         (*) Parameter not available on all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
+}
+
+/**
+  * @brief  Get comparator input plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INPSEL         LL_COMP_GetInputPlus
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
+  *
+  *         (*) Parameter not available on all devices.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
+}
+
+/**
+  * @brief  Set comparator input minus (inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   On this STM32 serie, scaler bridge is configurable:
+  *         to optimize power consumption, this function enables the
+  *         voltage scaler bridge only when required
+  *         (when selecting comparator input based on VrefInt: VrefInt or
+  *         subdivision of VrefInt).
+  *         - For scaler bridge power consumption values,
+  *           refer to device datasheet, parameter "IDDA(SCALER)".
+  *         - Voltage scaler requires a delay for voltage stabilization.
+  *           Refer to device datasheet, parameter "tSTART_SCALER".
+  *         - Scaler bridge is common for all comparator instances,
+  *           therefore if at least one of the comparator instance
+  *           is requiring the scaler bridge, it remains enabled.
+  * @rmtoll CSR      INMSEL         LL_COMP_SetInputMinus\n
+  *         CSR      BRGEN          LL_COMP_SetInputMinus\n
+  *         CSR      SCALEN         LL_COMP_SetInputMinus
+  * @param  COMPx Comparator instance
+  * @param  InputMinus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
+  *
+  *         (*) Parameter not available on all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+#if defined(COMP_CSR_INMESEL_1)
+  MODIFY_REG(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
+#else
+  MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
+#endif
+}
+
+/**
+  * @brief  Get comparator input minus (inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INMSEL         LL_COMP_GetInputMinus\n
+  *         CSR      BRGEN          LL_COMP_GetInputMinus\n
+  *         CSR      SCALEN         LL_COMP_GetInputMinus
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
+  *
+  *         (*) Parameter not available on all devices.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+{
+#if defined(COMP_CSR_INMESEL_1)
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
+#else
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
+#endif
+}
+
+/**
+  * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
+  * @rmtoll CSR      HYST           LL_COMP_SetInputHysteresis
+  * @param  COMPx Comparator instance
+  * @param  InputHysteresis This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_HYSTERESIS_NONE
+  *         @arg @ref LL_COMP_HYSTERESIS_LOW
+  *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+  *         @arg @ref LL_COMP_HYSTERESIS_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
+}
+
+/**
+  * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
+  * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_HYSTERESIS_NONE
+  *         @arg @ref LL_COMP_HYSTERESIS_LOW
+  *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+  *         @arg @ref LL_COMP_HYSTERESIS_HIGH
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+  * @{
+  */
+
+/**
+  * @brief  Set comparator instance output polarity.
+  * @rmtoll CSR      POLARITY       LL_COMP_SetOutputPolarity
+  * @param  COMPx Comparator instance
+  * @param  OutputPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
+}
+
+/**
+  * @brief  Get comparator instance output polarity.
+  * @rmtoll CSR      POLARITY       LL_COMP_GetOutputPolarity
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
+}
+
+/**
+  * @brief  Set comparator instance blanking source.
+  * @note   Blanking source may be specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   Availability of parameters of blanking source from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CSR      BLANKING       LL_COMP_SetOutputBlankingSource
+  * @param  COMPx Comparator instance
+  * @param  BlankingSource This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_BLANKINGSRC_NONE
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (1)(3)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (1)(3)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3)
+  *
+  *         (1) Parameter availability depending on timer availability
+  *             on the selected device.
+  *         (2) On STM32L4, parameter available only on comparator instance: COMP1.
+  *         (3) On STM32L4, parameter available only on comparator instance: COMP2.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
+}
+
+/**
+  * @brief  Get comparator instance blanking source.
+  * @note   Availability of parameters of blanking source from timer
+  *         depends on timers availability on the selected device.
+  * @note   Blanking source may be specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      BLANKING       LL_COMP_GetOutputBlankingSource
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_BLANKINGSRC_NONE
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (1)(2)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (1)(3)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (1)(3)
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3)
+  *
+  *         (1) Parameter availability depending on timer availability
+  *             on the selected device.
+  *         (2) On STM32L4, parameter available only on comparator instance: COMP1.
+  *         (3) On STM32L4, parameter available only on comparator instance: COMP2.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_Legacy_Functions Configuration of COMP, legacy functions name
+  * @{
+  */
+/* Old functions name kept for legacy purpose, to be replaced by the          */
+/* current functions name.                                                    */
+__STATIC_INLINE void LL_COMP_SetInputNonInverting(COMP_TypeDef *COMPx, uint32_t InputNonInverting)
+{
+  LL_COMP_SetInputPlus(COMPx, InputNonInverting);
+}
+__STATIC_INLINE uint32_t LL_COMP_GetInputNonInverting(COMP_TypeDef *COMPx)
+{
+  return LL_COMP_GetInputPlus(COMPx);
+}
+
+__STATIC_INLINE void LL_COMP_SetInputInverting(COMP_TypeDef *COMPx, uint32_t InputInverting)
+{
+  LL_COMP_SetInputMinus(COMPx, InputInverting);
+}
+__STATIC_INLINE uint32_t LL_COMP_GetInputInverting(COMP_TypeDef *COMPx)
+{
+  return LL_COMP_GetInputMinus(COMPx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+  * @{
+  */
+
+/**
+  * @brief  Enable comparator instance.
+  * @note   After enable from off state, comparator requires a delay
+  *         to reach reach propagation delay specification.
+  *         Refer to device datasheet, parameter "tSTART".
+  * @rmtoll CSR      EN             LL_COMP_Enable
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CSR, COMP_CSR_EN);
+}
+
+/**
+  * @brief  Disable comparator instance.
+  * @rmtoll CSR      EN             LL_COMP_Disable
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+  CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
+}
+
+/**
+  * @brief  Get comparator enable state
+  *         (0: COMP is disabled, 1: COMP is enabled)
+  * @rmtoll CSR      EN             LL_COMP_IsEnabled
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+{
+  return (READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN));
+}
+
+/**
+  * @brief  Lock comparator instance.
+  * @note   Once locked, comparator configuration can be accessed in read-only.
+  * @note   The only way to unlock the comparator is a device hardware reset.
+  * @rmtoll CSR      LOCK           LL_COMP_Lock
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
+}
+
+/**
+  * @brief  Get comparator lock state
+  *         (0: COMP is unlocked, 1: COMP is locked).
+  * @note   Once locked, comparator configuration can be accessed in read-only.
+  * @note   The only way to unlock the comparator is a device hardware reset.
+  * @rmtoll CSR      LOCK           LL_COMP_IsLocked
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+{
+  return (READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK));
+}
+
+/**
+  * @brief  Read comparator instance output level.
+  * @note   The comparator output level depends on the selected polarity
+  *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
+  *         If the comparator polarity is not inverted:
+  *          - Comparator output is low when the input plus
+  *            is at a lower voltage than the input minus
+  *          - Comparator output is high when the input plus
+  *            is at a higher voltage than the input minus
+  *         If the comparator polarity is inverted:
+  *          - Comparator output is high when the input plus
+  *            is at a lower voltage than the input minus
+  *          - Comparator output is low when the input plus
+  *            is at a higher voltage than the input minus
+  * @rmtoll CSR      VALUE          LL_COMP_ReadOutputLevel
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
+                    >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* COMP1 || COMP2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h

@@ -0,0 +1,657 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_CORTEX_H
+#define __STM32L4xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+  {
+    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+  else
+  {
+    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Constant number
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
+  * @retval Value should be equal to 0xF for Cortex-M4 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC24 for Cortex-M4
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h

@@ -0,0 +1,479 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_crc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_CRC_H
+#define __STM32L4xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
+  * @{
+  */
+#define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
+  * @{
+  */
+#define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
+#define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
+#define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
+#define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
+  * @{
+  */
+#define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
+#define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
+  * @brief    Normal representation of this polynomial value is
+  *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
+  * @{
+  */
+#define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Reset the CRC calculation unit.
+  * @note   If Programmable Initial CRC value feature
+  *         is available, also set the Data Register to the value stored in the
+  *         CRC_INIT register, otherwise, reset Data Register to its default value.
+  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
+  * @param  CRCx CRC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+  SET_BIT(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+  * @brief  Configure size of the polynomial.
+  * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
+  * @param  CRCx CRC Instance
+  * @param  PolySize This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_POLYLENGTH_32B
+  *         @arg @ref LL_CRC_POLYLENGTH_16B
+  *         @arg @ref LL_CRC_POLYLENGTH_8B
+  *         @arg @ref LL_CRC_POLYLENGTH_7B
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
+}
+
+/**
+  * @brief  Return size of the polynomial.
+  * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_POLYLENGTH_32B
+  *         @arg @ref LL_CRC_POLYLENGTH_16B
+  *         @arg @ref LL_CRC_POLYLENGTH_8B
+  *         @arg @ref LL_CRC_POLYLENGTH_7B
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the input data
+  * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @param  ReverseMode This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
+}
+
+/**
+  * @brief  Return type of reversal for input data bit order
+  * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the Output data
+  * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @param  ReverseMode This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the Output data
+  * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
+}
+
+/**
+  * @brief  Initialize the Programmable initial CRC value.
+  * @note   If the CRC size is less than 32 bits, the least significant bits
+  *         are used to write the correct value
+  * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
+  * @rmtoll INIT         INIT          LL_CRC_SetInitialData
+  * @param  CRCx CRC Instance
+  * @param  InitCrc Value to be programmed in Programmable initial CRC value register
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
+{
+  WRITE_REG(CRCx->INIT, InitCrc);
+}
+
+/**
+  * @brief  Return current Initial CRC value.
+  * @note   If the CRC size is less than 32 bits, the least significant bits
+  *         are used to read the correct value
+  * @rmtoll INIT         INIT          LL_CRC_GetInitialData
+  * @param  CRCx CRC Instance
+  * @retval Value programmed in Programmable initial CRC value register
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->INIT));
+}
+
+/**
+  * @brief  Initialize the Programmable polynomial value
+  *         (coefficients of the polynomial to be used for CRC calculation).
+  * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
+  * @note   Please check Reference Manual and existing Errata Sheets,
+  *         regarding possible limitations for Polynomial values usage.
+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
+  * @param  CRCx CRC Instance
+  * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
+{
+  WRITE_REG(CRCx->POL, PolynomCoef);
+}
+
+/**
+  * @brief  Return current Programmable polynomial value
+  * @note   Please check Reference Manual and existing Errata Sheets,
+  *         regarding possible limitations for Polynomial values usage.
+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
+  * @param  CRCx CRC Instance
+  * @retval Value programmed in Programmable Polynomial value register
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->POL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Write given 32-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData32
+  * @param  CRCx CRC Instance
+  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+  * @brief  Write given 16-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData16
+  * @param  CRCx CRC Instance
+  * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
+{
+  *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
+}
+
+/**
+  * @brief  Write given 8-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData8
+  * @param  CRCx CRC Instance
+  * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
+{
+  *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
+}
+
+/**
+  * @brief  Return current CRC calculation result. 32 bits value is returned.
+  * @rmtoll DR           DR            LL_CRC_ReadData32
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+  */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+  * @brief  Return current CRC calculation result. 16 bits value is returned.
+  * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData16
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
+  */
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+{
+  return (uint16_t)READ_REG(CRCx->DR);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 8 bits value is returned.
+  * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData8
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
+  */
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+{
+  return (uint8_t)READ_REG(CRCx->DR);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 7 bits value is returned.
+  * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData7
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
+  */
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+{
+  return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
+}
+
+/**
+  * @brief  Return data stored in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one byte.
+  * @rmtoll IDR          IDR           LL_CRC_Read_IDR
+  * @param  CRCx CRC Instance
+  * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
+  */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+  * @brief  Store data in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one byte.
+  * @rmtoll IDR          IDR           LL_CRC_Write_IDR
+  * @param  CRCx CRC Instance
+  * @param  InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
+}
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h

@@ -0,0 +1,801 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_crs.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of CRS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_CRS_H
+#define __STM32L4xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+  * @{
+  */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
+  * @{
+  */
+#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
+  * @{
+  */
+#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+  * @{
+  */
+#define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+  * @{
+  */
+#define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+  * @{
+  */
+#define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+  * @{
+  */
+#define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+  * @{
+  */
+/**
+  * @brief Reset value of the RELOAD field
+  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+  */
+#define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)
+
+/**
+  * @brief Reset value of Frequency error limit.
+  */
+#define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)
+
+/**
+  * @brief Reset value of the HSI48 Calibration field
+  * @note The default value is 32, which corresponds to the middle of the trimming interval.
+  *       The trimming step is around 67 kHz between two consecutive TRIM steps.
+  *       A higher TRIM value corresponds to a higher output frequency
+  */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x20U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+  * @{
+  */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+  * @{
+  */
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between
+  *         the target frequency and the frequency of the synchronization source after
+  *         prescaling. It is then decreased by one in order to reach the expected
+  *         synchronization on the zero value. The formula is the following:
+  *              RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval Reload value (in Hz)
+  */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+  * @{
+  */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable Frequency error counter
+  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Disable Frequency error counter
+  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Check if Frequency error counter is enabled or not
+  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
+}
+
+/**
+  * @brief  Enable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Disable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Check if Automatic trimming is enabled or not
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
+}
+
+/**
+  * @brief  Set HSI48 oscillator smooth trimming
+  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
+  * @param  Value a number between Min_Data = 0 and Max_Data = 63
+  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI48 oscillator smooth trimming
+  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
+  * @retval a number between Min_Data = 0 and Max_Data = 63
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Set counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
+  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
+  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+  * @brief  Get counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
+  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Set frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
+  * @param  Value a number between Min_Data = 0 and Max_Data = 255
+  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Get frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
+  * @retval A number between Min_Data = 0 and Max_Data = 255
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Set division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+  * @brief  Get division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+  * @brief  Set SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+  * @brief  Get SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+  * @brief  Set input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+  * @brief  Get input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+  * @brief  Configure CRS for the synchronization
+  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
+  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
+  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
+  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
+  * @param  Settings This parameter can be a combination of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
+  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+  MODIFY_REG(CRS->CFGR,
+             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
+             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate software SYNC event
+  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Get the frequency error direction latched in the time of the last
+  * SYNC event
+  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
+  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
+  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if SYNC event OK signal occurred or not
+  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
+}
+
+/**
+  * @brief  Check if SYNC warning signal occurred or not
+  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error signal occurred or not
+  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
+}
+
+/**
+  * @brief  Check if Expected SYNC signal occurred or not
+  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
+}
+
+/**
+  * @brief  Check if SYNC error signal occurred or not
+  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
+}
+
+/**
+  * @brief  Check if SYNC missed error signal occurred or not
+  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
+}
+
+/**
+  * @brief  Check if Trimming overflow or underflow occurred or not
+  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
+}
+
+/**
+  * @brief  Clear the SYNC event OK flag
+  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+  * @brief  Clear the  SYNC warning flag
+  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
+  * the ERR flag
+  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+  * @brief  Clear Expected SYNC flag
+  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Disable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Check if SYNC event OK interrupt is enabled or not
+  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
+}
+
+/**
+  * @brief  Enable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Disable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Check if SYNC warning interrupt is enabled or not
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
+}
+
+/**
+  * @brief  Enable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Disable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
+  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
+}
+
+/**
+  * @brief  Enable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Disable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Check if Expected SYNC interrupt is enabled or not
+  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_CRS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h

@@ -0,0 +1,979 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_fmc.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of FMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_FMC_H
+#define __STM32L4xx_LL_FMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+#if defined(FMC_BANK1)
+
+/** @addtogroup FMC_LL
+  * @{
+  */
+
+/** @addtogroup FMC_LL_Private_Macros
+  * @{
+  */
+
+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
+                                        ((__BANK__) == FMC_NORSRAM_BANK2) || \
+                                        ((__BANK__) == FMC_NORSRAM_BANK3) || \
+                                        ((__BANK__) == FMC_NORSRAM_BANK4))
+
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+                              ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+                                    ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+                                    ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_WRITE_BURST(__BURST__)          (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+                                                ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+
+#define IS_FMC_PAGESIZE(__SIZE__)              (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
+                                                ((__SIZE__) == FMC_PAGE_SIZE_128) || \
+                                                ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+                                                ((__SIZE__) == FMC_PAGE_SIZE_512) || \
+                                                ((__SIZE__) == FMC_PAGE_SIZE_1024))
+
+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__)     (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+                                                ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#if defined(FMC_BCR1_WFDIS)
+#define IS_FMC_WRITE_FIFO(__FIFO__)            (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
+                                                ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
+
+#endif /* FMC_BCR1_WFDIS */
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+                                       ((__MODE__) == FMC_ACCESS_MODE_B) || \
+                                       ((__MODE__) == FMC_ACCESS_MODE_C) || \
+                                       ((__MODE__) == FMC_ACCESS_MODE_D))
+
+#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
+
+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
+                                      ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
+
+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
+                                         ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
+
+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
+                                 ((__STATE__) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+                                   ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+/** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time
+  * @{
+  */
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time
+  * @{
+  */
+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Setup_Time FMC_Setup_Time
+  * @{
+  */
+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time
+  * @{
+  */
+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time
+  * @{
+  */
+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time
+  * @{
+  */
+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
+  * @{
+  */
+
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
+  * @{
+  */
+
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
+  * @{
+  */
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+/**
+  * @}
+  */
+
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+                                      ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                             ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+                                                ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+                                                ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+                                          ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+                                         ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                     ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
+
+/** @defgroup FMC_Data_Latency FMC Data Latency
+  * @{
+  */
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
+  * @{
+  */
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
+  * @{
+  */
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
+  * @{
+  */
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
+  * @{
+  */
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types
+  * @{
+  */
+
+#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef               FMC_Bank3_TypeDef
+
+#define FMC_NORSRAM_DEVICE                    FMC_Bank1_R
+#define FMC_NORSRAM_EXTENDED_DEVICE           FMC_Bank1E_R
+#define FMC_NAND_DEVICE                       FMC_Bank3_R
+
+/**
+  * @brief  FMC_NORSRAM Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                     */
+
+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
+                                              multiplexed on the data bus or not.
+                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */
+
+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
+                                              the corresponding memory device.
+                                              This parameter can be a value of @ref FMC_Memory_Type                      */
+
+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */
+
+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
+                                              valid only with synchronous burst Flash memories.
+                                              This parameter can be a value of @ref FMC_Burst_Access_Mode                */
+
+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
+                                              the Flash memory in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */
+
+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
+                                              clock cycle before the wait state or during the wait state,
+                                              valid only when accessing memories in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Timing                      */
+
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC.
+                                              This parameter can be a value of @ref FMC_Write_Operation                  */
+
+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
+                                              signal, valid for Flash memory access in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal                      */
+
+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
+                                              This parameter can be a value of @ref FMC_Extended_Mode                    */
+
+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
+                                              valid only with asynchronous Flash memories.
+                                              This parameter can be a value of @ref FMC_AsynchronousWait                 */
+
+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
+                                              This parameter can be a value of @ref FMC_Write_Burst                      */
+
+  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care
+                                              through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Continous_Clock                  */
+
+  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.
+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care
+                                              through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Write_FIFO.
+                                              @note This Parameter is not available for STM32L47x/L48x devices.         */
+
+  uint32_t PageSize;                     /*!< Specifies the memory page size.
+                                              This parameter can be a value of @ref FMC_Page_Size                        */
+}FMC_NORSRAM_InitTypeDef;
+
+/**
+  * @brief  FMC_NORSRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address setup time.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
+
+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address hold time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
+
+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the data setup time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+                                              NOR Flash memories.                                                        */
+
+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the bus turnaround.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is only used for multiplexed NOR Flash memories.      */
+
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+                                              accesses.                                                                  */
+
+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
+                                              to the memory before getting the first data.
+                                              The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+                                                with synchronous burst mode enable                                       */
+
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
+                                              This parameter can be a value of @ref FMC_Access_Mode                      */
+
+}FMC_NORSRAM_TimingTypeDef;
+
+/**
+  * @brief  FMC_NAND Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
+                                        This parameter can be a value of @ref FMC_NAND_Bank                    */
+
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
+                                        This parameter can be any value of @ref FMC_Wait_feature               */
+
+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
+                                        This parameter can be any value of @ref FMC_NAND_Data_Width            */
+
+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
+                                        This parameter can be any value of @ref FMC_ECC                        */
+
+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
+                                        This parameter can be any value of @ref FMC_ECC_Page_Size              */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_NAND_InitTypeDef;
+
+/**
+  * @brief  FMC_NAND Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
+                                      the command assertion for NAND-Flash read or write access
+                                      to common/Attribute or I/O memory space (depending on
+                                      the memory space timing to be configured).
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
+
+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
+                                      command for NAND-Flash read or write access to
+                                      common/Attribute or I/O memory space (depending on the
+                                      memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
+                                      (and data for write access) after the command de-assertion
+                                      for NAND-Flash read or write access to common/Attribute
+                                      or I/O memory space (depending on the memory space timing
+                                      to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
+                                      data bus is kept in HiZ after the start of a NAND-Flash
+                                      write access to common/Attribute or I/O memory space (depending
+                                      on the memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+}FMC_NAND_PCC_TimingTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
+  * @{
+  */
+#define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
+#define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
+#define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
+#define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
+  * @{
+  */
+
+#define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FMC_BCRx_MUXEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Memory_Type FMC Memory Type
+  * @{
+  */
+
+#define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FMC_BCRx_MTYP_0)
+#define FMC_MEMORY_TYPE_NOR                     ((uint32_t)FMC_BCRx_MTYP_1)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width
+  * @{
+  */
+
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FMC_BCRx_MWID_0)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FMC_BCRx_MWID_1)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
+  * @{
+  */
+
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FMC_BCRx_FACCEN)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
+  * @{
+  */
+
+#define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FMC_BCRx_BURSTEN)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
+  * @{
+  */
+
+#define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FMC_BCRx_WAITPOL)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+  * @{
+  */
+
+#define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)FMC_BCRx_WAITCFG)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
+  * @{
+  */
+
+#define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)FMC_BCRx_WREN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+  * @{
+  */
+
+#define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FMC_BCRx_WAITEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+  * @{
+  */
+
+#define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)FMC_BCRx_EXTMOD)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
+  * @{
+  */
+
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FMC_BCRx_ASYNCWAIT)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Page_Size FMC Page Size
+  * @{
+  */
+#define FMC_PAGE_SIZE_NONE                      ((uint32_t)0x00000000)
+#define FMC_PAGE_SIZE_128                       ((uint32_t)FMC_BCRx_CPSIZE_0)
+#define FMC_PAGE_SIZE_256                       ((uint32_t)FMC_BCRx_CPSIZE_1)
+#define FMC_PAGE_SIZE_512                       ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
+#define FMC_PAGE_SIZE_1024                      ((uint32_t)FMC_BCRx_CPSIZE_2)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
+  * @{
+  */
+
+#define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE                  ((uint32_t)FMC_BCRx_CBURSTRW)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Continous_Clock FMC Continous Clock
+  * @{
+  */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)FMC_BCR1_CCLKEN)
+/**
+  * @}
+  */
+
+#if defined(FMC_BCR1_WFDIS)
+/** @defgroup FMC_Write_FIFO FMC Write FIFO
+  * @{
+  */
+#define FMC_WRITE_FIFO_DISABLE                  ((uint32_t)FMC_BCR1_WFDIS)
+#define FMC_WRITE_FIFO_ENABLE                   ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+#endif /* FMC_BCR1_WFDIS */
+/** @defgroup FMC_Access_Mode FMC Access Mode
+  * @{
+  */
+
+#define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
+#define FMC_ACCESS_MODE_B                        ((uint32_t)FMC_BTRx_ACCMOD_0)
+#define FMC_ACCESS_MODE_C                        ((uint32_t)FMC_BTRx_ACCMOD_1)
+#define FMC_ACCESS_MODE_D                        ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller
+  * @{
+  */
+
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
+  * @{
+  */
+#define FMC_NAND_BANK3                          ((uint32_t)0x00000100)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_feature FMC Wait feature
+  * @{
+  */
+#define FMC_NAND_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
+#define FMC_NAND_WAIT_FEATURE_ENABLE            ((uint32_t)FMC_PCR_PWAITEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
+  * @{
+  */
+#define FMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)FMC_PCR_PTYP)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
+  * @{
+  */
+#define FMC_NAND_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
+#define FMC_NAND_MEM_BUS_WIDTH_16               ((uint32_t)FMC_PCR_PWID_0)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC FMC NAND ECC
+  * @{
+  */
+#define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE                     ((uint32_t)FMC_PCR_ECCEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
+  * @{
+  */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)FMC_PCR_ECCPS_0)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)FMC_PCR_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)FMC_PCR_ECCPS_2)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Interrupt_definition FMC Interrupt definition
+  * @brief FMC Interrupt definition
+  * @{
+  */
+#define FMC_IT_RISING_EDGE                ((uint32_t)FMC_SR_IREN)
+#define FMC_IT_LEVEL                      ((uint32_t)FMC_SR_ILEN)
+#define FMC_IT_FALLING_EDGE               ((uint32_t)FMC_SR_IFEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Flag_definition FMC Flag definition
+  * @brief FMC Flag definition
+  * @{
+  */
+#define FMC_FLAG_RISING_EDGE                    ((uint32_t)FMC_SR_IRS)
+#define FMC_FLAG_LEVEL                          ((uint32_t)FMC_SR_ILS)
+#define FMC_FLAG_FALLING_EDGE                   ((uint32_t)FMC_SR_IFS)
+#define FMC_FLAG_FEMPT                          ((uint32_t)FMC_SR_FEMPT)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
+  * @{
+  */
+
+/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
+ *  @brief macros to handle NOR device enable/disable and read/write operations
+ *  @{
+ */
+
+/**
+  * @brief  Enable the NORSRAM device access.
+  * @param  __INSTANCE__ FMC_NORSRAM Instance
+  * @param  __BANK__ FMC_NORSRAM Bank
+  * @retval none
+  */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+
+/**
+  * @brief  Disable the NORSRAM device access.
+  * @param  __INSTANCE__ FMC_NORSRAM Instance
+  * @param  __BANK__ FMC_NORSRAM Bank
+  * @retval none
+  */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Macros FMC NAND Macros
+ *  @brief macros to handle NAND device enable/disable
+ *  @{
+ */
+
+/**
+  * @brief  Enable the NAND device access.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__ FMC_NAND Bank
+  * @retval None
+  */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
+
+/**
+  * @brief  Disable the NAND device access.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__ FMC_NAND Bank
+  * @retval None
+  */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Interrupt FMC Interrupt
+ *  @brief macros to handle FMC interrupts
+ * @{
+ */
+
+/**
+  * @brief  Enable the NAND device interrupt.
+  * @param  __INSTANCE__  FMC_NAND Instance
+  * @param  __BANK__      FMC_NAND Bank
+  * @param  __INTERRUPT__ FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
+  * @retval None
+  */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the NAND device interrupt.
+  * @param  __INSTANCE__  FMC_NAND Instance
+  * @param  __BANK__      FMC_NAND Bank
+  * @param  __INTERRUPT__ FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
+  * @retval None
+  */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__))
+
+/**
+  * @brief  Get flag status of the NAND device.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __FLAG__ FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT FIFO empty flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the NAND device.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __FLAG__ FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT FIFO empty flag.
+  * @retval None
+  */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__))
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup FMC_LL_Exported_Functions
+ *  @{
+ */
+
+/** @addtogroup FMC_NORSRAM
+ *  @{
+ */
+
+/** @addtogroup FMC_NORSRAM_Group1
+ *  @{
+ */
+
+/* FMC_NORSRAM Controller functions ******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/**
+  * @}
+  */
+
+/** @addtogroup FMC_NORSRAM_Group2
+ *  @{
+ */
+
+/* FMC_NORSRAM Control functions */
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FMC_NAND
+ *  @{
+ */
+
+/* FMC_NAND Controller functions **********************************************/
+/* Initialization/de-initialization functions */
+/** @addtogroup FMC_NAND_Exported_Functions_Group1
+ *  @{
+ */
+
+HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/**
+  * @}
+  */
+
+/* FMC_NAND Control functions */
+/** @addtogroup FMC_NAND_Exported_Functions_Group2
+ *  @{
+ */
+
+HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* FMC_BANK1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_FMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h

@@ -0,0 +1,363 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.7.1
+  * @date    21-April-2017
+  * @brief   Header file of IWDG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_IWDG_H
+#define __STM32L4xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+  * @{
+  */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+  * @{
+  */
+
+#define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
+#define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
+  * @{
+  */
+#define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
+#define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
+  * @{
+  */
+#define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
+#define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
+#define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
+#define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
+#define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
+#define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in IWDG register
+  * @param  __INSTANCE__ IWDG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in IWDG register
+  * @param  __INSTANCE__ IWDG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+  * @{
+  */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Start the Independent Watchdog
+  * @note   Except if the hardware watchdog option is selected
+  * @rmtoll KR           KEY           LL_IWDG_Enable
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+  * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+  * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+  * @brief  Select the prescaler of the IWDG
+  * @rmtoll PR           PR            LL_IWDG_SetPrescaler
+  * @param  IWDGx IWDG Instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_IWDG_PRESCALER_4
+  *         @arg @ref LL_IWDG_PRESCALER_8
+  *         @arg @ref LL_IWDG_PRESCALER_16
+  *         @arg @ref LL_IWDG_PRESCALER_32
+  *         @arg @ref LL_IWDG_PRESCALER_64
+  *         @arg @ref LL_IWDG_PRESCALER_128
+  *         @arg @ref LL_IWDG_PRESCALER_256
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+  WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+  * @brief  Get the selected prescaler of the IWDG
+  * @rmtoll PR           PR            LL_IWDG_GetPrescaler
+  * @param  IWDGx IWDG Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_IWDG_PRESCALER_4
+  *         @arg @ref LL_IWDG_PRESCALER_8
+  *         @arg @ref LL_IWDG_PRESCALER_16
+  *         @arg @ref LL_IWDG_PRESCALER_32
+  *         @arg @ref LL_IWDG_PRESCALER_64
+  *         @arg @ref LL_IWDG_PRESCALER_128
+  *         @arg @ref LL_IWDG_PRESCALER_256
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->PR));
+}
+
+/**
+  * @brief  Specify the IWDG down-counter reload value
+  * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+  WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+  * @brief  Get the specified IWDG down-counter reload value
+  * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->RLR));
+}
+
+/**
+  * @brief  Specify high limit of the window value to be compared to the down-counter.
+  * @rmtoll WINR         WIN           LL_IWDG_SetWindow
+  * @param  IWDGx IWDG Instance
+  * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
+{
+  WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
+}
+
+/**
+  * @brief  Get the high limit of the window value specified.
+  * @rmtoll WINR         WIN           LL_IWDG_GetWindow
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->WINR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if flag Prescaler Value Update is set or not
+  * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+}
+
+/**
+  * @brief  Check if flag Reload Value Update is set or not
+  * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+}
+
+/**
+  * @brief  Check if flag Window Value Update is set or not
+  * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
+}
+
+/**
+  * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
+  * @rmtoll SR           PVU           LL_IWDG_IsReady\n
+  *         SR           WVU           LL_IWDG_IsReady\n
+  *         SR           RVU           LL_IWDG_IsReady
+  * @param  IWDGx IWDG Instance
+  * @retval State of bits (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* IWDG) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/