diff --git a/CMSIS/STM32WBxx/Include/stm32wb30xx.h b/CMSIS/STM32WBxx/Include/stm32wb30xx.h index 1518495..7b4849b 100644 --- a/CMSIS/STM32WBxx/Include/stm32wb30xx.h +++ b/CMSIS/STM32WBxx/Include/stm32wb30xx.h @@ -110,7 +110,6 @@ typedef enum I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ SPI1_IRQn = 34, /*!< SPI1 Interrupt */ USART1_IRQn = 36, /*!< USART1 Interrupt */ - TSC_IRQn = 39, /*!< TSC Interrupt */ EXTI15_10_IRQn = 40, /*!< EXTI Lines1[15:10 ]Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarms (A and B) Interrupt */ PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn = 43, /*!< PWR switching on the fly interrupt @@ -354,7 +353,6 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ } LPTIM_TypeDef; /** @@ -541,15 +539,6 @@ typedef struct } SYSCFG_TypeDef; -/** - * @brief VREFBUF - */ -typedef struct -{ - __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ - __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ -} VREFBUF_TypeDef; - /** * @brief TIM */ @@ -770,8 +759,8 @@ typedef struct #define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */ -#define SRAM2A_BASE (SRAM_BASE + 0x00008000UL)/*!< SRAM2A(32 KB) base address */ -#define SRAM2B_BASE (SRAM_BASE + 0x00010000UL)/*!< SRAM2B(32 KB) base address */ +#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ +#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */ /* Memory Size */ #define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U) @@ -781,8 +770,8 @@ typedef struct /* End addresses */ #define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 - 0x20007FFF) */ -#define SRAM2A_END_ADDR (0x2000FFFFUL) /*!< SRAM2a (backup) : 32KB (0x20008000 - 0x2000FFFF) */ -#define SRAM2B_END_ADDR (0x20017FFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20010000 - 0x20017FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ #define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ @@ -809,7 +798,6 @@ typedef struct /*!< APB2 peripherals */ #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) @@ -856,7 +844,6 @@ typedef struct #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) - /*!< AHB Shared peripherals */ #define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL) #define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL) @@ -899,7 +886,6 @@ typedef struct /* Peripherals available on APB2 bus */ #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) @@ -984,6 +970,9 @@ typedef struct /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ + +#define ADC_SUPPORT_5_MSPS /* ADC sampling rate 5 Msamples/sec */ + /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ @@ -2495,7 +2484,7 @@ typedef struct /******************************************************************************/ /******************** Bits definition for DMAMUX_CxCR register **************/ #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) -#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */ #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ @@ -2503,8 +2492,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ -#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ @@ -2558,27 +2545,6 @@ typedef struct #define DMAMUX_CSR_SOF6_Pos (6U) #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ -#define DMAMUX_CSR_SOF7_Pos (7U) -#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ -#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */ -#define DMAMUX_CSR_SOF8_Pos (8U) -#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ -#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */ -#define DMAMUX_CSR_SOF9_Pos (9U) -#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ -#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */ -#define DMAMUX_CSR_SOF10_Pos (10U) -#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ -#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */ -#define DMAMUX_CSR_SOF11_Pos (11U) -#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ -#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */ -#define DMAMUX_CSR_SOF12_Pos (12U) -#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ -#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */ -#define DMAMUX_CSR_SOF13_Pos (13U) -#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ -#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */ /******************** Bits definition for DMAMUX_CFR register **************/ #define DMAMUX_CFR_CSOF0_Pos (0U) @@ -2602,27 +2568,6 @@ typedef struct #define DMAMUX_CFR_CSOF6_Pos (6U) #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ -#define DMAMUX_CFR_CSOF7_Pos (7U) -#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ -#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */ -#define DMAMUX_CFR_CSOF8_Pos (8U) -#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ -#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */ -#define DMAMUX_CFR_CSOF9_Pos (9U) -#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ -#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */ -#define DMAMUX_CFR_CSOF10_Pos (10U) -#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */ -#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */ -#define DMAMUX_CFR_CSOF11_Pos (11U) -#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */ -#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */ -#define DMAMUX_CFR_CSOF12_Pos (12U) -#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */ -#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */ -#define DMAMUX_CFR_CSOF13_Pos (13U) -#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */ -#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */ /******************** Bits definition for DMAMUX_RGxCR register ************/ #define DMAMUX_RGxCR_SIG_ID_Pos (0U) @@ -2751,15 +2696,6 @@ typedef struct #define EXTI_RTSR1_RT19_Pos (19U) #define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR1_RT20_Pos (20U) -#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ -#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR1_RT21_Pos (21U) -#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ -#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR1_RT31_Pos (31U) -#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */ -#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */ /****************** Bit definition for EXTI_FTSR1 register ******************/ #define EXTI_FTSR1_FT_Pos (0U) @@ -3279,6 +3215,7 @@ typedef struct #define EXTI_C2IMR1_IM30_Pos (30U) #define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */ #define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */ + /******************** Bits definition for EXTI_C2EMR1 register **************/ #define EXTI_C2EMR1_Pos (0U) #define EXTI_C2EMR1_Msk (0x003EFFFFUL << EXTI_C2EMR1_Pos) /*!< 0xFFFFFFFF */ @@ -3904,7 +3841,7 @@ typedef struct /****************** Bits definition for FLASH_SRRVR register ************/ #define FLASH_SRRVR_SBRV_Pos (0U) #define FLASH_SRRVR_SBRV_Msk (0x3FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0003FFFF */ -#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */ +#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* CPU2 boot reset vector memory offset */ #define FLASH_SRRVR_SBRSA_Pos (18U) #define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */ @@ -3921,7 +3858,7 @@ typedef struct #define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */ #define FLASH_SRRVR_C2OPT_Pos (31U) #define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */ -#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */ +#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* CPU2 boot reset vector memory selection */ /****************** Bits definition for FLASH_C2ACR register ************/ #define FLASH_C2ACR_PRFTEN_Pos (8U) @@ -5877,6 +5814,8 @@ typedef struct /* */ /******************************************************************************/ +#define PWR_SUPPORT_STOP2 + /******************** Bit definition for PWR_CR1 register ********************/ #define PWR_CR1_LPMS_Pos (0U) #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ @@ -5931,10 +5870,6 @@ typedef struct #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable external WKUP Pin 4 [line 3] */ -#define PWR_CR3_EBORHSMPSFB_Pos (8U) -#define PWR_CR3_EBORHSMPSFB_Msk (0x1UL << PWR_CR3_EBORHSMPSFB_Pos) /*!< 0x00000100 */ -#define PWR_CR3_EBORHSMPSFB PWR_CR3_EBORHSMPSFB_Msk /*!< BORH interrupt for CPU1 (mention of SMPS is not applicable to this device) */ - #define PWR_CR3_RRS_Pos (9U) #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000200 */ #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention in STANDBY mode */ @@ -6358,6 +6293,8 @@ typedef struct /* * @brief Specific device feature definitions */ +#define RCC_HSI48_SUPPORT +#define RCC_802_SUPPORT /******************** Bit definition for RCC_CR register *****************/ #define RCC_CR_MSION_Pos (0U) @@ -6409,9 +6346,6 @@ typedef struct #define RCC_CR_HSERDY_Pos (17U) #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ -#define RCC_CR_HSEBYP_Pos (18U) -#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ -#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */ #define RCC_CR_CSSON_Pos (19U) #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ @@ -6775,19 +6709,19 @@ typedef struct /******************** Bit definition for RCC_APB2RSTR register **************/ #define RCC_APB2RSTR_TIM1RST_Pos (11U) -#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk #define RCC_APB2RSTR_SPI1RST_Pos (12U) -#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk #define RCC_APB2RSTR_TIM16RST_Pos (17U) -#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk #define RCC_APB2RSTR_TIM17RST_Pos (18U) -#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /******************** Bit definition for RCC_APB3RSTR register **************/ @@ -6870,19 +6804,19 @@ typedef struct /******************** Bit definition for RCC_APB2ENR register **************/ #define RCC_APB2ENR_TIM1EN_Pos (11U) -#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk #define RCC_APB2ENR_SPI1EN_Pos (12U) -#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk #define RCC_APB2ENR_USART1EN_Pos (14U) #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk #define RCC_APB2ENR_TIM16EN_Pos (17U) -#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk #define RCC_APB2ENR_TIM17EN_Pos (18U) -#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /******************** Bit definition for RCC_AHB1SMENR register ****************/ @@ -6960,19 +6894,19 @@ typedef struct /******************** Bit definition for RCC_APB2SMENR register **************/ #define RCC_APB2SMENR_TIM1SMEN_Pos (11U) -#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) -#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk #define RCC_APB2SMENR_USART1SMEN_Pos (14U) #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk #define RCC_APB2SMENR_TIM16SMEN_Pos (17U) -#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk #define RCC_APB2SMENR_TIM17SMEN_Pos (18U) -#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk /******************** Bit definition for RCC_CCIPR register ******************/ @@ -7282,19 +7216,19 @@ typedef struct /******************** Bit definition for RCC_C2APB2ENR register **************/ #define RCC_C2APB2ENR_TIM1EN_Pos (11U) -#define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ #define RCC_C2APB2ENR_TIM1EN RCC_C2APB2ENR_TIM1EN_Msk #define RCC_C2APB2ENR_SPI1EN_Pos (12U) -#define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_C2APB2ENR_SPI1EN RCC_C2APB2ENR_SPI1EN_Msk #define RCC_C2APB2ENR_USART1EN_Pos (14U) #define RCC_C2APB2ENR_USART1EN_Msk (0x1UL << RCC_C2APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_C2APB2ENR_USART1EN RCC_C2APB2ENR_USART1EN_Msk #define RCC_C2APB2ENR_TIM16EN_Pos (17U) -#define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ #define RCC_C2APB2ENR_TIM16EN RCC_C2APB2ENR_TIM16EN_Msk #define RCC_C2APB2ENR_TIM17EN_Pos (18U) -#define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ #define RCC_C2APB2ENR_TIM17EN RCC_C2APB2ENR_TIM17EN_Msk /******************** Bit definition for RCC_C2APB3ENR register **************/ @@ -7377,19 +7311,19 @@ typedef struct /******************** Bit definition for RCC_C2APB2SMENR register **************/ #define RCC_C2APB2SMENR_TIM1SMEN_Pos (11U) -#define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ #define RCC_C2APB2SMENR_TIM1SMEN RCC_C2APB2SMENR_TIM1SMEN_Msk #define RCC_C2APB2SMENR_SPI1SMEN_Pos (12U) -#define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ #define RCC_C2APB2SMENR_SPI1SMEN RCC_C2APB2SMENR_SPI1SMEN_Msk #define RCC_C2APB2SMENR_USART1SMEN_Pos (14U) #define RCC_C2APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ #define RCC_C2APB2SMENR_USART1SMEN RCC_C2APB2SMENR_USART1SMEN_Msk #define RCC_C2APB2SMENR_TIM16SMEN_Pos (17U) -#define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ #define RCC_C2APB2SMENR_TIM16SMEN RCC_C2APB2SMENR_TIM16SMEN_Msk #define RCC_C2APB2SMENR_TIM17SMEN_Pos (18U) -#define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ +#define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ #define RCC_C2APB2SMENR_TIM17SMEN RCC_C2APB2SMENR_TIM17SMEN_Msk /******************** Bit definition for RCC_C2APB3SMENR register **************/ @@ -8876,9 +8810,6 @@ typedef struct #define SYSCFG_C2IMR2_PVDIM_Pos (20U) #define SYSCFG_C2IMR2_PVDIM_Msk (0x1UL << SYSCFG_C2IMR2_PVDIM_Pos) /*!< 0x00100000 */ #define SYSCFG_C2IMR2_PVDIM SYSCFG_C2IMR2_PVDIM_Msk /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */ -#define SYSCFG_C2IMR2_TSCIM_Pos (21U) -#define SYSCFG_C2IMR2_TSCIM_Msk (0x1UL << SYSCFG_C2IMR2_TSCIM_Pos) /*!< 0x00200000 */ -#define SYSCFG_C2IMR2_TSCIM SYSCFG_C2IMR2_TSCIM_Msk /*!< Enabling of interrupt from Touch Sensing Controller to CPU2 */ /***************** Bit definition for SYSCFG_SIPCR register (SYSCFG secure IP control register) *****************************************************************************/ #define SYSCFG_SIPCR_SAES2_Pos (1U) @@ -9586,17 +9517,9 @@ typedef struct #define TIM1_OR_TI1_RMP TIM1_OR_TI1_RMP_Msk /*!< Input Capture 1 remap*/ /******************* Bit definition for TIM2_OR register *******************/ -#define TIM2_OR_TI4_RMP_Pos (2U) -#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x0000000C */ -#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!< TI4 RMA[1:0]Input capture 4 remap*/ -#define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000004 */ -#define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */ #define TIM2_OR_ETR_RMP_Pos (1U) #define TIM2_OR_ETR_RMP_Msk (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */ #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!< External trigger remap*/ -#define TIM2_OR_ITR1_RMP_Pos (0U) -#define TIM2_OR_ITR1_RMP_Msk (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */ -#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!< Internal trigger remap*/ /******************* Bit definition for TIM16_OR register ******************/ #define TIM16_OR_TI1_RMP_Pos (0U) @@ -9660,9 +9583,10 @@ typedef struct /******************************************************************************/ /* */ -/* Low Power Timer (LPTTIM) */ +/* Low Power Timer (LPTIM) */ /* */ /******************************************************************************/ + /****************** Bit definition for LPTIM_ISR register *******************/ #define LPTIM_ISR_CMPM_Pos (0U) #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ @@ -9826,12 +9750,6 @@ typedef struct #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ -/****************** Bit definition for LPTIM_OR register *******************/ -#define LPTIM_OR_OR_Pos (0U) -#define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos) /*!< 0x00000003 */ -#define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */ -#define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */ -#define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */ /******************************************************************************/ /* */ @@ -10601,30 +10519,6 @@ typedef struct #define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ #define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ -/******************************************************************************/ -/* */ -/* VREFBUF */ -/* */ -/******************************************************************************/ -/******************* Bit definition for VREFBUF_CSR register ****************/ -#define VREFBUF_CSR_ENVR_Pos (0U) -#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ -#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2020 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - /** * @} */ @@ -315,6 +314,11 @@ #if defined(STM32G0) #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM #endif #if defined(STM32H7) @@ -579,7 +583,8 @@ #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS @@ -642,6 +647,10 @@ #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ #if defined(STM32H7) @@ -1449,7 +1458,7 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End @@ -1471,7 +1480,7 @@ #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT -#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1530,18 +1539,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -3371,7 +3380,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined STM32WL +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h index 2d5d9a2..99e171a 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h @@ -136,6 +136,7 @@ typedef enum #define SYSCFG_SRAM2WRP_PAGE33 LL_SYSCFG_SRAM2WRP_PAGE33 /*!< SRAM2B Write protection page 33 */ #define SYSCFG_SRAM2WRP_PAGE34 LL_SYSCFG_SRAM2WRP_PAGE34 /*!< SRAM2B Write protection page 34 */ #define SYSCFG_SRAM2WRP_PAGE35 LL_SYSCFG_SRAM2WRP_PAGE35 /*!< SRAM2B Write protection page 35 */ +#if defined(LL_SYSCFG_SRAM2WRP_PAGE36) #define SYSCFG_SRAM2WRP_PAGE36 LL_SYSCFG_SRAM2WRP_PAGE36 /*!< SRAM2B Write protection page 36 */ #define SYSCFG_SRAM2WRP_PAGE37 LL_SYSCFG_SRAM2WRP_PAGE37 /*!< SRAM2B Write protection page 37 */ #define SYSCFG_SRAM2WRP_PAGE38 LL_SYSCFG_SRAM2WRP_PAGE38 /*!< SRAM2B Write protection page 38 */ @@ -164,6 +165,7 @@ typedef enum #define SYSCFG_SRAM2WRP_PAGE61 LL_SYSCFG_SRAM2WRP_PAGE61 /*!< SRAM2B Write protection page 61 */ #define SYSCFG_SRAM2WRP_PAGE62 LL_SYSCFG_SRAM2WRP_PAGE62 /*!< SRAM2B Write protection page 62 */ #define SYSCFG_SRAM2WRP_PAGE63 LL_SYSCFG_SRAM2WRP_PAGE63 /*!< SRAM2B Write protection page 63 */ +#endif /* LL_SYSCFG_SRAM2WRP_PAGE36 */ /** * @} @@ -422,7 +424,7 @@ typedef enum * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 * @note Write protection can only be disabled by a system reset */ -#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ +#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP2_PAGE((__SRAM2WRP__)));\ LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\ }while(0) @@ -520,6 +522,7 @@ typedef enum (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) +#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) #if defined(VREFBUF) #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ @@ -657,8 +660,10 @@ void HAL_SYSCFG_DisableVREFBUF(void); void HAL_SYSCFG_EnableIOBooster(void); void HAL_SYSCFG_DisableIOBooster(void); +#if defined(SYSCFG_CFGR1_ANASWVDD) void HAL_SYSCFG_EnableIOVdd(void); void HAL_SYSCFG_DisableIOVdd(void); +#endif void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess); void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess); diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h index b962634..7f575b2 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h @@ -44,6 +44,9 @@ extern "C" { * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief ADC group regular oversampling structure definition */ @@ -67,6 +70,7 @@ typedef struct This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ } ADC_OversamplingTypeDef; +#endif /** * @brief Structure definition of ADC instance and ADC group regular. @@ -131,6 +135,13 @@ typedef struct use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ +#if defined(ADC_SUPPORT_2_5_MSPS) + FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). + This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). + This parameter can be set to ENABLE or DISABLE. + Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ + +#endif FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ @@ -147,9 +158,13 @@ typedef struct Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group regular number of discontinuous conversions" not available on ADC peripheral of this STM32WB device */ +#else uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ +#endif uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. @@ -176,12 +191,47 @@ typedef struct overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ +#if defined (ADC_SUPPORT_2_5_MSPS) + uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + + uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ +#endif + +#if !defined (ADC_SUPPORT_2_5_MSPS) FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ + Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ +#endif + +#if defined (ADC_SUPPORT_2_5_MSPS) + uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. + This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. + Note: ADC trigger frequency mode must be set to low frequency when + a duration is exceeded before ADC conversion start trigger event + (between ADC enable and ADC conversion start trigger event + or between two ADC conversion start trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". + Note: When ADC trigger frequency mode is set to low frequency, + some rearm cycles are inserted before performing ADC conversion + start, inducing a delay of 2 ADC clock cycles. */ +#endif } ADC_InitTypeDef; @@ -253,7 +303,7 @@ typedef struct { uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') - For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) + For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel). Note: Analog Watchdog 2 and 3 are not available on devices: STM32WB10xx, STM32WB15xx. This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. @@ -367,7 +417,11 @@ typedef struct HAL_LockTypeDef Lock; /*!< ADC locking object */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ +#if defined (ADC_SUPPORT_2_5_MSPS) + uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */ +#else ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ +#endif #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ @@ -474,7 +528,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -482,8 +536,33 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_Scan_mode ADC sequencer scan mode * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Note: On STM32WB10xx, STM32WB15xx devices, ADC group regular sequencer */ +/* both modes "fully configurable" or "not fully configurable" are */ +/* available. */ +/* Scan mode values must be compatible with other STM32 devices having */ +/* a configurable sequencer. */ +/* Scan direction setting values are defined by taking in account */ +/* already defined values for other STM32 devices: */ +/* ADC_SCAN_DISABLE (0x00000000UL) */ +/* ADC_SCAN_ENABLE (0x00000001UL) */ +/* Sequencer fully configurable with only rank 1 enabled is considered */ +/* as default setting equivalent to scan enable. */ +/* In case of migration from another STM32 device, the user will be */ +/* warned of change of setting choices with assert check. */ +#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */ +#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */ + +#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ + +#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */ +#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */ + +#else #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} */ @@ -493,6 +572,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /* ADC group regular trigger sources for all ADC instances */ #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#else #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ @@ -501,6 +588,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#endif /** * @} */ @@ -537,6 +625,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ +#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */ + +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +#else #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ @@ -553,10 +654,36 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ +#endif /** * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME ADC instance - Sampling time common to a group of channels + * @{ + */ +#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ +#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE Channel - Sampling time (ADC instance scope for sampling time common 1 or 2, not channel wise) + * @{ + */ +#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ +#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ +#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ +#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ +#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ +/** + * @} + */ +#else /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ @@ -571,6 +698,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @} */ +#endif /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number * @{ @@ -607,8 +735,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */ +#else #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ +#endif /** * @} */ @@ -627,6 +759,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */ +#else /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio * @{ */ @@ -657,6 +792,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @} */ +#endif /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ @@ -676,6 +812,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode + * @{ + */ +#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +/** + * @} + */ +#endif + /** @defgroup ADC_Event_type ADC Event type * @{ @@ -685,7 +832,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ +#if !defined (ADC_SUPPORT_2_5_MSPS) #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ +#endif /** * @} */ @@ -699,12 +848,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC end of calibration interrupt source */ +#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ +#else #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ +#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ +#endif #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ -#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ @@ -720,13 +874,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC end of calibration flag */ +#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */ +#else #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ +#endif #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ -#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ - /** * @} */ @@ -781,7 +939,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (8UL))) +#else #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) +#endif /** @@ -863,6 +1025,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @param __REGTRIG__ programmed ADC regular conversions external trigger. * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START) ) +#else #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ @@ -872,6 +1043,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) +#endif /** * @brief Verify the ADC regular conversions check for converted data availability. @@ -889,11 +1061,26 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ + ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) +#endif + /** * @brief Verify the ADC conversions sampling time. * @param __TIME__ ADC conversions sampling time. * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \ + ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_7CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_19CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_39CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_79CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_160CYCLES_5) ) +#else #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ @@ -902,28 +1089,45 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) +#endif + +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ + ((RANK) == ADC_RANK_NONE) ) +#endif /** * @brief Verify the ADC regular channel setting. - * @param __CHANNEL__ programmed ADC regular channel. - * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) - */ -#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) + * @param RANK programmed ADC regular channel. + * @retval SET (RANK is valid) or RESET (RANK is invalid) + */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ + ((RANK) == ADC_REGULAR_RANK_2 ) || \ + ((RANK) == ADC_REGULAR_RANK_3 ) || \ + ((RANK) == ADC_REGULAR_RANK_4 ) || \ + ((RANK) == ADC_REGULAR_RANK_5 ) || \ + ((RANK) == ADC_REGULAR_RANK_6 ) || \ + ((RANK) == ADC_REGULAR_RANK_7 ) || \ + ((RANK) == ADC_REGULAR_RANK_8 ) ) +#else +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ + ((RANK) == ADC_REGULAR_RANK_2 ) || \ + ((RANK) == ADC_REGULAR_RANK_3 ) || \ + ((RANK) == ADC_REGULAR_RANK_4 ) || \ + ((RANK) == ADC_REGULAR_RANK_5 ) || \ + ((RANK) == ADC_REGULAR_RANK_6 ) || \ + ((RANK) == ADC_REGULAR_RANK_7 ) || \ + ((RANK) == ADC_REGULAR_RANK_8 ) || \ + ((RANK) == ADC_REGULAR_RANK_9 ) || \ + ((RANK) == ADC_REGULAR_RANK_10) || \ + ((RANK) == ADC_REGULAR_RANK_11) || \ + ((RANK) == ADC_REGULAR_RANK_12) || \ + ((RANK) == ADC_REGULAR_RANK_13) || \ + ((RANK) == ADC_REGULAR_RANK_14) || \ + ((RANK) == ADC_REGULAR_RANK_15) || \ + ((RANK) == ADC_REGULAR_RANK_16) ) +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} @@ -950,6 +1154,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */ +#endif + /** * @} */ @@ -994,10 +1202,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_OVR ADC overrun interrupt source * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1015,10 +1225,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_OVR ADC overrun interrupt source * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1033,12 +1245,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source * @arg @ref ADC_IT_OVR ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source (1) + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source (1) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source (1) * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ @@ -1054,12 +1268,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag (1) + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag (1) + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag (1) * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval State of flag (TRUE or FALSE). */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ @@ -1075,12 +1291,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag (1) + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag (1) + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag (1) * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval None */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc_ex.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc_ex.h index 2bf99de..59864e5 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc_ex.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc_ex.h @@ -41,6 +41,9 @@ extern "C" { * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief ADC Injected Conversion Oversampling structure definition */ @@ -170,6 +173,7 @@ typedef struct Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ } ADC_InjectionConfTypeDef; +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} @@ -181,6 +185,9 @@ typedef struct * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source * @{ */ @@ -206,12 +213,15 @@ typedef struct /** * @} */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ +#if !defined (ADC_SUPPORT_2_5_MSPS) #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ +#endif /** * @} */ @@ -228,6 +238,9 @@ typedef struct * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ @@ -238,13 +251,18 @@ typedef struct /** * @} */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups * @{ */ #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} */ @@ -315,6 +333,9 @@ typedef struct */ #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Set the selected injected Channel rank. * @param __CHANNELNB__ Channel number. @@ -336,6 +357,7 @@ typedef struct * @retval None */ #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Configure ADC discontinuous conversion mode for regular group @@ -365,6 +387,47 @@ typedef struct */ #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) +#if defined (ADC_SUPPORT_2_5_MSPS) +/** + * @brief Enable ADC overrun mode. + * @param _OVERRUN_MODE_ Overrun mode. + * @retval Overun bit setting to be programmed into CFGR register + */ +/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ +/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ +/* as the default case to be compliant with other STM32 devices. */ +#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \ + ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ + )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ + ) + +/** + * @brief Enable the ADC auto off mode. + * @param _AUTOOFF_ Auto off bit enable or disable. + * @retval None + */ +#define ADC_CFGR_AUTOOFF(_AUTOOFF_) \ + ((_AUTOOFF_) << 15UL) + +/** + * @brief Set ADC scan mode with differentiation of sequencer setting + * fixed or configurable + * @param _SCAN_MODE_ Scan conversion mode. + * @retval None + */ +/* Note: Scan mode set using this macro (instead of parameter direct set) */ +/* due to different modes on other STM32 devices: */ +/* if scan mode is disabled, sequencer is set to fully configurable */ +/* with setting of only rank 1 enabled afterwards. */ +#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ + ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ + )? \ + ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ + : \ + (ADC_CFGR1_CHSELRMOD) \ + ) + +#endif /** * @brief Configure the ADC DMA continuous request. * @param __DMACONTREQ_MODE__ DMA continuous request mode. @@ -400,8 +463,13 @@ typedef struct * @param __THRESHOLD__ Value to be shifted * @retval None */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ + ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL)) +#else #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) +#endif /** * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. @@ -414,22 +482,38 @@ typedef struct * @param __THRESHOLD__ Value to be shifted * @retval None */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ + ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) != (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)) ? \ + ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ + ((__THRESHOLD__) << 2UL) \ + ) +#else #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ ((__THRESHOLD__) << 2UL) \ ) +#endif /** * @brief Clear Common Control Register. * @param __HANDLE__ ADC handle. * @retval None */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ + ADC_CCR_PRESC | \ + ADC_CCR_VBATEN | \ + ADC_CCR_TSEN | \ + ADC_CCR_VREFEN ) +#else #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ ADC_CCR_PRESC | \ ADC_CCR_VBATEN | \ ADC_CCR_TSEN | \ ADC_CCR_VREFEN ) +#endif /** @@ -453,12 +537,16 @@ typedef struct */ #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Verify the length of scheduled injected conversions group. * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Calibration factor size verification (7 bits maximum). @@ -525,8 +613,12 @@ typedef struct * @param __SING_DIFF__ programmed channel setting. * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) ((__SING_DIFF__) == ADC_SINGLE_ENDED) +#else #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) +#endif /** * @brief Verify the ADC offset management setting. @@ -539,6 +631,9 @@ typedef struct ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Verify the ADC injected channel setting. * @param __CHANNEL__ programmed ADC injected channel. @@ -572,21 +667,31 @@ typedef struct ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Verify the ADC analog watchdog setting. * @param __WATCHDOG__ programmed ADC analog watchdog setting. * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) +#else #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) +#endif /** * @brief Verify the ADC analog watchdog mode setting. * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) ) +#else #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ @@ -594,6 +699,12 @@ typedef struct ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) +#endif /* ADC_SUPPORT_2_5_MSPS */ + +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ + ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) +#endif /** * @brief Verify the ADC conversion (regular or injected or both). @@ -609,13 +720,24 @@ typedef struct * @param __EVENT__ ADC event. * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ + ((__EVENT__) == ADC_AWD1_EVENT) || \ + ((__EVENT__) == ADC_AWD2_EVENT) || \ + ((__EVENT__) == ADC_AWD3_EVENT) || \ + ((__EVENT__) == ADC_OVR_EVENT) ) +#else #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ ((__EVENT__) == ADC_AWD_EVENT) || \ ((__EVENT__) == ADC_AWD2_EVENT) || \ ((__EVENT__) == ADC_AWD3_EVENT) || \ ((__EVENT__) == ADC_OVR_EVENT) || \ ((__EVENT__) == ADC_JQOVF_EVENT) ) +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Verify the ADC oversampling ratio. * @param __RATIO__ programmed ADC oversampling ratio. @@ -629,6 +751,7 @@ typedef struct ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) +#endif /** * @brief Verify the ADC oversampling shift. @@ -653,6 +776,8 @@ typedef struct #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) +#if defined (ADC_SUPPORT_2_5_MSPS) +#else /** * @brief Verify the ADC oversampling regular conversion resumed or continued mode. * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. @@ -660,6 +785,7 @@ typedef struct */ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) +#endif /** * @brief Verify the DFSDM mode configuration. @@ -702,6 +828,9 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); @@ -710,21 +839,34 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *h /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); +#endif /* ADC_SUPPORT_2_5_MSPS */ void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /* ADC group regular conversions stop */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} */ @@ -733,11 +875,23 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected); +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); +#endif /* ADC_SUPPORT_2_5_MSPS */ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */ +#else HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); +#endif /** * @} diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_comp.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_comp.h index b7908ee..e09a474 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_comp.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_comp.h @@ -49,10 +49,12 @@ extern "C" { typedef struct { +#if defined(COMP2) uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP and COMP). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of @ref COMP_WindowMode */ +#endif /* COMP2 */ uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed. Note: For the characteristics of comparator power modes @@ -152,6 +154,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @} */ +#if defined(COMP2) /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ @@ -160,6 +163,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** * @} */ +#endif /** @defgroup COMP_PowerMode COMP power mode * @{ @@ -177,11 +181,9 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_InputPlus COMP input plus (non-inverting input) * @{ */ -#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ #define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ -#if defined(COMP_CSR_INPSEL_1) #define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ -#endif /** * @} */ @@ -194,7 +196,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */ #define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */ #define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ -#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */ +#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ #define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */ #define COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */ #define COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */ @@ -422,6 +424,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1) +#if defined(COMP2) /** * @brief Enable the COMP2 EXTI line rising edge trigger. * @retval None @@ -506,6 +509,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2) +#endif /* COMP2 */ /** * @} */ @@ -525,7 +529,9 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @{ */ #define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_20) /*!< EXTI line 20 connected to COMP1 output */ +#if defined(COMP2) #define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP2 output */ +#endif /* COMP2 */ /** * @} */ @@ -558,30 +564,42 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ +#if defined(COMP2) #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ : COMP_EXTI_LINE_COMP2) +#else +#define COMP_GET_EXTI_LINE(__INSTANCE__) COMP_EXTI_LINE_COMP1 +#endif /* COMP2 */ /** * @} */ -/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters +/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters * @{ */ +#if defined(COMP2) #define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) ) +#endif #define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \ ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) ) +#if defined(COMP_INPUT_PLUS_IO1) #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)) +#else +#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)) +#endif -/* Note: On this STM32 serie, comparator input minus parameters are */ +/* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ +#if defined(COMP_INPUT_MINUS_IO2) #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ @@ -591,6 +609,16 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5)) +#else +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5)) +#endif #define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \ ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h index ec5c1d4..4dabd50 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h @@ -64,9 +64,10 @@ typedef struct uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data. */ - uint32_t HeaderSize; /*!< The size of header buffer in word */ + uint32_t HeaderSize; /*!< The size of header buffer */ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ - uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization Vector only once and to skip configuration for consecutive processings. This parameter can be a value of @ref CRYP_Configuration_Skip */ @@ -108,7 +109,7 @@ typedef struct __CRYP_HandleTypeDef typedef struct #endif { - AES_TypeDef *Instance; /*!< AES Register base address */ + AES_TypeDef *Instance; /*!< AES Register base address */ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ @@ -119,13 +120,13 @@ typedef struct uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ + __IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */ - __IO uint16_t CrypInCount; /*!< Counter of input data */ + __IO uint16_t CrypInCount; /*!< Counter of input data in words */ - __IO uint16_t CrypOutCount; /*!< Counter of output data */ + __IO uint16_t CrypOutCount; /*!< Counter of output data in words */ - uint16_t Size; /*!< length of input data in words */ + uint16_t Size; /*!< Length of input data */ uint32_t Phase; /*!< CRYP peripheral phase */ @@ -261,6 +262,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point #define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ #define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */ +/** + * @} + */ + +/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit + * @{ + */ + +#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */ +#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */ + /** * @} */ @@ -568,10 +580,11 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \ - (((((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || ((ALGO) == CRYP_AES_CTR)) && \ + (((((ALGO) == CRYP_AES_CTR)) && \ ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ - (((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) + (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ + ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) /** * @} diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h index add713e..b8d94c3 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h @@ -190,26 +190,34 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ +#if defined(SPI2) #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ #define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ +#endif /* SPI2 */ #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ +#if defined(I2C3) #define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ #define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ +#endif /* I2C3 */ #define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ #define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ +#if defined(LPUART1) #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */ #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */ +#endif /* LPUART1 */ #if defined (SAI1) #define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A /*!< DMAMUX SAI1 A request */ #define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B /*!< DMAMUX SAI1 B request */ #endif /* SAI1 */ +#if defined(QUADSPI) #define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI /*!< DMAMUX QUADSPI request */ +#endif /* QUADSPI */ #define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ #define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ @@ -231,8 +239,10 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ #define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ +#if defined(AES1) #define DMA_REQUEST_AES1_IN LL_DMAMUX_REQ_AES1_IN /*!< DMAMUX AES1 IN request */ #define DMA_REQUEST_AES1_OUT LL_DMAMUX_REQ_AES1_OUT /*!< DMAMUX AES1 OUT request */ +#endif /* AES1 */ #define DMA_REQUEST_AES2_IN LL_DMAMUX_REQ_AES2_IN /*!< DMAMUX AES2 IN request */ #define DMA_REQUEST_AES2_OUT LL_DMAMUX_REQ_AES2_OUT /*!< DMAMUX AES2 OUT request */ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h index e1eccc6..a9acfc7 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h @@ -105,11 +105,14 @@ typedef struct #define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u) #define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u) #define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u) -#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx #define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u) -#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u) #else #define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u) +#endif +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u) +#else #define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u) #endif #define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) @@ -119,7 +122,7 @@ typedef struct #define EXTI_LINE_23 (EXTI_RESERVED | EXTI_REG1 | 0x17u) #endif #define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) -#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx #define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) #else #define EXTI_LINE_25 (EXTI_RESERVED | EXTI_REG1 | 0x19u) @@ -133,7 +136,7 @@ typedef struct #endif #define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) #define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) -#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx #define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) #else #define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu) @@ -156,7 +159,11 @@ typedef struct #endif #define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu) #define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx) || defined (STM32WB35xx) || defined (STM32WB30xx) #define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu) +#else +#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_REG2 | 0x0Eu) +#endif #define EXTI_LINE_47 (EXTI_RESERVED | EXTI_REG2 | 0x0Fu) #define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u) /** @@ -266,21 +273,21 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) -#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) -#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) #if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h index 0dd6798..ba6be23 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h @@ -75,6 +75,7 @@ typedef struct uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of the values of @ref FLASH_OB_USER_AGC_TRIM, @ref FLASH_OB_USER_BOR_LEVEL + @ref FLASH_OB_USER_RESET_CONFIG(*), @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, @@ -280,6 +281,9 @@ typedef struct #define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ #define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ #define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ +#if defined(FLASH_OPTR_IRHEN) +#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */ +#endif #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ @@ -289,12 +293,24 @@ typedef struct #define OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST /*!< SRAM2 erase when system reset */ #define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ +#if defined(FLASH_OPTR_nRST_MODE) +#define OB_USER_NRST_MODE FLASH_OPTR_nRST_MODE /*!< Reset pin configuration */ +#endif #define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM /*!< Automatic Gain Control Trimming */ +#if defined(FLASH_OPTR_IRHEN) && defined(FLASH_OPTR_nRST_MODE) +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ + OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ + OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ + OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \ + OB_USER_nBOOT0 | OB_USER_AGC_TRIM | OB_USER_NRST_MODE | \ + OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ +#else #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \ OB_USER_nBOOT0 | OB_USER_AGC_TRIM) /*!< all option bits */ +#endif /** * @} @@ -435,6 +451,29 @@ typedef struct * @} */ +#if defined(FLASH_OPTR_nRST_MODE) +/** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit + * @{ + */ +#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_nRST_MODE_0 /*!< Reset pin is in Reset input mode only */ +#define OB_RESET_MODE_GPIO FLASH_OPTR_nRST_MODE_1 /*!< Reset pin is in GPIO normal mode only */ +#define OB_RESET_MODE_INPUT_OUTPUT (FLASH_OPTR_nRST_MODE_0 | FLASH_OPTR_nRST_MODE_1) /*!< Reset pin is in Reset input and output mode */ +/** + * @} + */ +#endif + +#if defined(FLASH_OPTR_IRHEN) +/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit + * @{ + */ +#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */ +#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */ +/** + * @} + */ +#endif + /** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE * @{ */ @@ -857,7 +896,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) -#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__))) +#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)(FLASH_PAGE_SIZE - 1U)) == (__VALUE__))) #define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) #define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) #define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE)) diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h index ad6d00f..339c968 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h @@ -53,181 +53,10 @@ * */ -#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx) - - /* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | - *_____________________________________________________________________________________________ - * |SYS_AF |TIM |TIM |SPI/SAI/TI|I2C | I2C | RF | USART | - *_____________________________________________________________________________________________ - * PA0 | |TIM2_CH1 | | | | |RF_DTB2 | | - * PA1 | |TIM2_CH2 | | |I2C1_SMBA |SPI1_SCK |RF_DTB3 | | - * PA2 | |TIM2_CH3 | | | | |RF_DTB4 | | - * PA3 | |TIM2_CH4 | |SAI1_CK1 | | |RF_DTB5 | | - * PA4 | | | | | |SPI1_NSS |RF_DTB6 | | - * PA5 | |TIM2_CH1 |TIM2_ETR | | |SPI1_SCK |RF_DTB7 | | - * PA6 | |TIM1_BKIN | | | |SPI1_MISO |RF_DTB8 | | - * PA7 | |TIM1_CH1N | | |I2C3_SCL |SPI1_MOSI |RF_DTB9 | | - * PA8 |MCO |TIM1_CH1 | |SAI1_CK2 | | |RF_DTB12 |USART1_CK | - * PA9 | |TIM2_CH2 | |SAI1_DI2 |I2C1_SCL |SPI2_SCK |RF_DTB13 |USART1_TX | - * PA10| |TIM2_CH3 | |SAI1_DI1 |I2C1_SDA | |RF_DTB14 |USART1_RX | - * PA11| |TIM2_CH4 |TIM1_BKIN2| | |SPI1_MISO |RF_DTB15 |USART1_CTS| - * PA12| |TIM2_ETR | | | |SPI1_MOSI |RF_MISO |USART1_RTS| - * PA13|JTMS_SWDIO| | | | | | | | - * PA14|JTCK_SWCLK|LPTIM1_OUT| | |I2C1_SMBA | | | | - * PA15|JTDI |TIM2_CH1 |TIM2_ETR | | |SPI1_NSS | | | - *______________________________________________________________________________________________ - * PB0 | | | | | | | | | - * PB1 | | | | | | | | | - * PB2 |RTC_OUT |LPTIM1_OUT| | |I2C3_SMBA |SPI1_NSS |RF_DTB10 | | - * PB3 |JTDO |TIM2_CH2 | | | |SPI1_SCK | |USART1_RTS| - * PB4 |NJTRST | | | |I2C3_SDA |SPI1_MISO | |USART1_CTS| - * PB5 | |LPTIM1_IN1| | |I2C1_SMBA |SPI1_MOSI |RF_MOSI |USART1_CK | - * PB6 | |LPTIM1_ETR| | |I2C1_SCL | |RF_SCK |USART1_TX | - * PB7 | |LPTIM1_IN2| |TIM1_BKIN |I2C1_SDA | |RF_DTB11 |USART1_RX | - * PB8 | |TIM1_CH2N | |SAI1_CK1 |I2C1_SCL | |RF_DTB16 | | - * PB9 | |TIM1_CH3N | |SAI1_DI2 |I2C1_SDA |SPI2_NSS | | | - * PB10| |TIM2_CH3 | | |I2C3_SCL |SPI2_SCK |RF_DTB18 | | - * PB11| |TIM2_CH4 | | |I2C3_SDA | |RF_DTB17 | | - * PB12| |TIM1_BKIN | |TIM1_BKIN |I2C3_SMBA |SPI2_NSS | | | - * PB13| |TIM1_CH1N | | |I2C3_SCL |SPI2_SCK | | | - * PB14| |TIM1_CH2N | | |I2C3_SDA |SPI2_MISO | | | - * PB15|RTC_REFIN |TIM1_CH3N | | | |SPI2_MOSI | | | - *______________________________________________________________________________________________ - * PC0 | |LPTIM1_IN1| | |I2C3_SCL | | | | - * PC1 | |LPTIM1_OUT| |SPI2_MOSI |I2C3_SDA | | | | - * PC2 | |LPTIM1_IN2| | | |SPI2_MISO | | | - * PC3 | |LPTIM1_ETR| |SAI1_DI1 | |SPI2_MOSI | | | - * PC4 | | | | | | | | | - * PC5 | | | |SAI1_DI3 | | | | | - * PC6 | | | | | | | | | - * PC7 | | | | | | | | | - * PC8 | | | | | | | | | - * PC9 | | | |TIM1_BKIN | | | | | - * PC10|TRACED1 | | | | | | | | - * PC11| | | | | | | | | - * PC12|TRACED3 | | | | | | | | - * PC13| | | | | | | | | - * PC14| | | | | | |RF_DTB0 | | - * PC15| | | | | | |RF_DTB1 | | - *______________________________________________________________________________________________ - * PD0 | | | | | |SPI2_NSS | | | - * PD1 | | | | | |SPI2_SCK | | | - * PD2 |TRACED2 | | | | | | | | - * PD3 | | | |SPI2_SCK | |SPI2_MISO | | | - * PD4 | | | | | |SPI2_MOSI | | | - * PD5 | | | | | | | | | - * PD6 | | | |SAI1_DI1 | | | | | - * PD7 | | | | | | | | | - * PD8 | | |TIM1_BKIN2| | | | | | - * PD9 |TRACED0 | | | | | | | | - * PD10|TRIG_IO | | | | | | | | - * PD11| | | | | | | | | - * PD12| | | | | | | | | - * PD13| | | | | | | | | - * PD14| |TIM1_CH1 | | | | | | | - * PD15| |TIM1_CH2 | | | | | | | - *______________________________________________________________________________________________ - * PE0 | |TIM1_ETR | | | | | | | - * PE1 | | | | | | | | | - * PE2 |TRACED2 | | |SAI1_CK1 | | | | | - * PE3 | | | | | | | | | - * PE4 | | | | | | | | | - *______________________________________________________________________________________________ - * PH0 | | | | | | | | | - * PH1 | | | | | | | | | - * PE2 | | | | | | | | | - * PH3 | | | | | | |RF_NSS | | - *______________________________________________________________________________________________*/ - - - /* | AF8 | AF9 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 | - *_____________________________________________________________________________________________ - * |LPUART1 |TSC |USB/QUADSP|LCD |COMP/TIM |SAI |TIM |EVENTOUT | - *_____________________________________________________________________________________________ - * PA0 | | | | |COMP1_OUT |SAI1_E_CLK|TIM2_ETR |EVENTOUT | - * PA1 | | | |LCD_SEG0 | | | |EVENTOUT | - * PA2 |LPUART1_TX| |QSPI_NCS |LCD_SEG1 |COMP2_OUT | | |EVENTOUT | - * PA3 |LPUART1_RX| |QSPI_CLK |LCD_SEG2 | |SAI1_CLK_A| |EVENTOUT | - * PA4 | | | | | |SAI1_FS_B |LPTIM2_OUT|EVENTOUT | - * PA5 | | | | | | |LPTIM2_ETR|EVENTOUT | - * PA6 |LPUART1_CT| |QSPI_IO3 |LCD_SEG3 |TIM1_BKIN | |TIM16_CH1 |EVENTOUT | - * PA7 | | |QSPI_IO2 |LCD_SEG4 |COMP2_OUT | |TIM17_CH1 |EVENTOUT | - * PA8 | | | |LCD_COM0 | |SAI1_SCK_A|LPTIM2_OUT|EVENTOUT | - * PA9 | | | |LCD_COM1 | |SAI1_FS_A | |EVENTOUT | - * PA10| | |USB_CRS_SY|LCD_COM2 | |SAI1_SD_A |TIM17_BKIN|EVENTOUT | - * PA11| | |USB_DM | |TIM1_BKIN2| | |EVENTOUT | - * PA12| | |USB_DP | | | | |EVENTOUT | - * PA13|IR_OUT | |USB_NOE | | |SAI1_SD_B | |EVENTOUT | - * PA14| | | | | |SAI1_FS_B | |EVENTOUT | - * PA15| |TSC_G3_IO1| |LCD_SEG17 | | | |EVENTOUT | - *______________________________________________________________________________________________ - * PB0 | | | |LCD_SEG5 |COMP1_OUT | | |EVENTOUT | - * PB1 |LPUART1_RT| | |LCD_SEG6 | | |LPTIM2_IN1|EVENTOUT | - * PB2 | | | |LCD_VLCD | |SAI1_E_CLK| |EVENTOUT | - * PB3 | | | |LCD_SEG7 | |SAI1_SCK_B| |EVENTOUT | - * PB4 | |TSC_G2_IO1| |LCD_SEG8 | |SAI1_CLK_B|TIM17_BKIN|EVENTOUT | - * PB5 | |TSC_G2_IO2| |LCD_SEG9 |COMP2_OUT |SAI1_SD_B |TIM16_BKIN|EVENTOUT | - * PB6 | |TSC_G2_IO3| | | |SAI1_FS_B |TIM16_CH1N|EVENTOUT | - * PB7 | |TSC_G2_IO4| |LCD_SEG21 | | |TIM17_CH1N|EVENTOUT | - * PB8 | | |QSPI_IO1 |LCD_SEG16 | |SAI1_CLK_A|TIM16_CH1 |EVENTOUT | - * PB9 |IR_OUT |TSC_G7_IO4|QSPI_IO0 |LCD_COM3 | |SAI1_FS_A |TIM17_CH1 |EVENTOUT | - * PB10|LPUART1_RX|TSC_SYNC |QSPI_CLK |LCD_SEG10 |COMP1_OUT |SAI1_SCK_A| |EVENTOUT | - * PB11|LPUART1_TX| |QSPI_NCS |LCD_SEG11 |COMP2_OUT | | |EVENTOUT | - * PB12|LPUART1_RT|TSC_G1_IO1| |LCD_SEG12 | |SAI1_FS_A | |EVENTOUT | - * PB13|LPUART1_CT|TSC_G1_IO2| |LCD_SEG13 | |SAI1_SCK_A| |EVENTOUT | - * PB14| |TSC_G1_IO3| |LCD_SEG14 | |SAI1_CLK_A| |EVENTOUT | - * PB15| |TSC_G1_IO4| |LCD_SEG15 | |SAI1_SD_A | |EVENTOUT | - *______________________________________________________________________________________________ - * PC0 |LPUART1_RX| | |LCD_SEG18 | | |LPTIM2_IN1|EVENTOUT | - * PC1 |LPUART1_TX| | |LCD_SEG19 | | | |EVENTOUT | - * PC2 | | | |LCD_SEG20 | | | |EVENTOUT | - * PC3 | | | |LCD_VLCD | |SAI1_SD_A |LPTIM2_ETR|EVENTOUT | - * PC4 | | | |LCD_SEG22 | | | |EVENTOUT | - * PC5 | | | |LCD_SEG23 | | | |EVENTOUT | - * PC6 | |TSC_G4_IO1| |LCD_SEG24 | | | |EVENTOUT | - * PC7 | |TSC_G4_IO2| |LCD_SEG25 | | | |EVENTOUT | - * PC8 | |TSC_G4_IO3| |LCD_SEG26 | | | |EVENTOUT | - * PC9 | |TSC_G4_IO4|USB_NOE |LCD_SEG27 | |SAI1_SCK_B| |EVENTOUT | - * PC10| |TSC_G3_IO2| |LCD_Cx_SEx| | | |EVENTOUT | - * PC11| |TSC_G3_IO3| |LCD_Cx_SEx| | | |EVENTOUT | - * PC12| |TSC_G3_IO4| |LCD_Cx_SEx| | | |EVENTOUT | - * PC13| | | | | | | |EVENTOUT | - * PC14| | | | | | | |EVENTOUT | - * PC15| | | | | | | |EVENTOUT | - *______________________________________________________________________________________________ - * PD0 | | | | | | | |EVENTOUT | - * PD1 | | | | | | | |EVENTOUT | - * PD2 | |TSC_SYNC | |LCD_Cx_SEx| | | |EVENTOUT | - * PD3 | | |QSPI_NCS | | | | |EVENTOUT | - * PD4 | |TSC_G5_IO1|QSPI_IO0 | | | | |EVENTOUT | - * PD5 | |TSC_G5_IO2|QSPI_IO1 | | |SAI1_CLK_B| |EVENTOUT | - * PD6 | |TSC_G5_IO3|QSPI_IO2 | | |SAI1_SD_A | |EVENTOUT | - * PD7 | |TSC_G5_IO4|QSPI_IO3 |LCD_SEG39 | | | |EVENTOUT | - * PD8 | | | |LCD_SEG28 | | | |EVENTOUT | - * PD9 | | | |LCD_SEG29 | | | |EVENTOUT | - * PD10| |TSC_G6_IO1| |LCD_SEG30 | | | |EVENTOUT | - * PD11| |TSC_G6_IO2| |LCD_SEG31 | | |LPTIM2_ETR|EVENTOUT | - * PD12| |TSC_G6_IO3| |LCD_SEG32 | | |LPTIM2_IN1|EVENTOUT | - * PD13| |TSC_G6_IO4| |LCD_SEG33 | | |LPTIM2_OUT|EVENTOUT | - * PD14| | | |LCD_SEG34 | | | |EVENTOUT | - * PD15| | | |LCD_SEG35 | | | |EVENTOUT | - *______________________________________________________________________________________________ - * PE0 | |TSC_G7_IO3| |LCD_SEG36 | | |TIM16_CH1 |EVENTOUT | - * PE1 | |TSC_G7_IO2| |LCD_SEG37 | | |TIM17_CH1 |EVENTOUT | - * PE2 | |TSC_G7_IO1| |LCD_SEG38 | |SAI1_CLK_A| |EVENTOUT | - * PE3 | | | | | | | |EVENTOUT | - * PE4 | | | | | | | |EVENTOUT | - *______________________________________________________________________________________________ - * PH0 | | | | | | | |EVENTOUT | - * PH1 | | | | | | | |EVENTOUT | - * PE2 | | | | | | | |EVENTOUT | - * PH3 | | | | | | | |EVENTOUT | - *______________________________________________________________________________________________*/ - +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) /** * @brief AF 0 selection */ - #define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ #define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */ #define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */ @@ -255,9 +84,9 @@ /** * @brief AF 2 selection */ - #define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ + /** * @brief AF 3 selection */ @@ -362,6 +191,108 @@ #endif +#if defined (STM32WB50xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */ +#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */ +#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */ +#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */ +#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */ +#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */ +#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */ + + /** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */ +#define GPIO_AF6_LSCO ((uint8_t)0x06) /*!< LSCO Alternate Function mapping */ +#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */ +#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */ +#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */ +#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */ +#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0c) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0e) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0e) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0e) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0e) /*!< LPTIM2 Alternate Function mapping */ + +/** +* @brief AF 15 selection +*/ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x09) && ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D)) + +#endif + + #if defined (STM32WB35xx) /** * @brief AF 0 selection @@ -395,8 +326,7 @@ /** * @brief AF 3 selection */ -#define GPIO_AF3_SPI1 ((uint8_t)0x03) /*!< SPI1 Alternate Function mapping */ -#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1_CK1 Alternate Function mapping */ #define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */ /** @@ -404,18 +334,17 @@ */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ -#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */ +#define GPIO_AF6_LSCO ((uint8_t)0x06) /*!< LSCO Alternate Function mapping */ #define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */ #define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */ #define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */ @@ -451,11 +380,6 @@ #define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ #define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ - #define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ - /** * @brief AF 10 selection */ @@ -469,6 +393,11 @@ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ #define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */ +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0d) /*!< SAI1 Alternate Function mapping */ + /** * @brief AF 14 selection */ @@ -525,7 +454,6 @@ * @brief AF 4 selection */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ -#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */ /** * @brief AF 5 selection @@ -536,6 +464,7 @@ * @brief AF 6 selection */ #define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */ +#define GPIO_AF6_LSCO ((uint8_t)0x06) /*!< LSCO Alternate Function mapping */ #define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */ #define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */ #define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */ @@ -570,11 +499,6 @@ */ #define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ - /** * @brief AF 12 selection */ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c_ex.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c_ex.h index 1ae6f86..9cdef10 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c_ex.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c_ex.h @@ -38,7 +38,6 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ @@ -75,24 +74,51 @@ extern "C" { */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions * @{ */ - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions + * @{ + */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions + * @{ + */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + + +/** + * @} + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants @@ -118,9 +144,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)) - - - /** * @} */ @@ -142,14 +165,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h deleted file mode 100644 index b1fcb0a..0000000 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h +++ /dev/null @@ -1,546 +0,0 @@ -/** - ****************************************************************************** - * @file stm32wbxx_hal_i2s.h - * @author MCD Application Team - * @brief Header file of I2S HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32WBxx_HAL_I2S_H -#define STM32WBxx_HAL_I2S_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32wbxx_hal_def.h" - -#if defined(SPI_I2S_SUPPORT) -/** @addtogroup STM32WBxx_HAL_Driver - * @{ - */ - -/** @addtogroup I2S - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2S_Exported_Types I2S Exported Types - * @{ - */ - -/** - * @brief I2S Init structure definition - */ -typedef struct -{ - uint32_t Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint32_t Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -} I2S_InitTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ - HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ -} HAL_I2S_StateTypeDef; - -/** - * @brief I2S handle Structure definition - */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1) -typedef struct __I2S_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -{ - SPI_TypeDef *Instance; /*!< I2S registers base address */ - - I2S_InitTypeDef Init; /*!< I2S communication parameters */ - - uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ - - __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ - - __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ - - uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ - - __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ - - __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter - (This field is initialized at the - same value as transfer size at the - beginning of the transfer and - decremented when a sample is received - NbSamplesReceived = RxBufferSize-RxBufferCount) */ - DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ - - __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ - - __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ - - __IO uint32_t ErrorCode; /*!< I2S Error code - This parameter can be a value of @ref I2S_Error */ - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ - void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ - void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ - void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ - void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ - void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ - void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ - -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} I2S_HandleTypeDef; - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -/** - * @brief HAL I2S Callback ID enumeration definition - */ -typedef enum -{ - HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ - HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ - HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ - HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ - HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ - HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ - HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ - -} HAL_I2S_CallbackIDTypeDef; - -/** - * @brief HAL I2S Callback pointer definition - */ -typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ - -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2S_Exported_Constants I2S Exported Constants - * @{ - */ -/** @defgroup I2S_Error I2S Error - * @{ - */ -#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ -#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ -#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ -#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ -#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup I2S_Mode I2S Mode - * @{ - */ -#define I2S_MODE_SLAVE_TX (0x00000000U) -#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) -#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) -#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) -/** - * @} - */ - -/** @defgroup I2S_Standard I2S Standard - * @{ - */ -#define I2S_STANDARD_PHILIPS (0x00000000U) -#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) -#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) -#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) -#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format I2S Data Format - * @{ - */ -#define I2S_DATAFORMAT_16B (0x00000000U) -#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) -#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) -#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output I2S MCLK Output - * @{ - */ -#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) -#define I2S_MCLKOUTPUT_DISABLE (0x00000000U) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency I2S Audio Frequency - * @{ - */ -#define I2S_AUDIOFREQ_192K (192000U) -#define I2S_AUDIOFREQ_96K (96000U) -#define I2S_AUDIOFREQ_48K (48000U) -#define I2S_AUDIOFREQ_44K (44100U) -#define I2S_AUDIOFREQ_32K (32000U) -#define I2S_AUDIOFREQ_22K (22050U) -#define I2S_AUDIOFREQ_16K (16000U) -#define I2S_AUDIOFREQ_11K (11025U) -#define I2S_AUDIOFREQ_8K (8000U) -#define I2S_AUDIOFREQ_DEFAULT (2U) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity I2S Clock Polarity - * @{ - */ -#define I2S_CPOL_LOW (0x00000000U) -#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) -/** - * @} - */ - -/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition - * @{ - */ -#define I2S_IT_TXE SPI_CR2_TXEIE -#define I2S_IT_RXNE SPI_CR2_RXNEIE -#define I2S_IT_ERR SPI_CR2_ERRIE -/** - * @} - */ - -/** @defgroup I2S_Flags_Definition I2S Flags Definition - * @{ - */ -#define I2S_FLAG_TXE SPI_SR_TXE -#define I2S_FLAG_RXNE SPI_SR_RXNE - -#define I2S_FLAG_UDR SPI_SR_UDR -#define I2S_FLAG_OVR SPI_SR_OVR -#define I2S_FLAG_FRE SPI_SR_FRE - -#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE -#define I2S_FLAG_BSY SPI_SR_BSY - -#define I2S_FLAG_MASK (SPI_SR_RXNE\ - | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup I2S_Exported_macros I2S Exported Macros - * @{ - */ - -/** @brief Reset I2S handle state - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - -/** @brief Enable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - -/** @brief Disable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - -/** @brief Enable the specified I2S interrupts. - * @param __HANDLE__ specifies the I2S Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) - -/** @brief Disable the specified I2S interrupts. - * @param __HANDLE__ specifies the I2S Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) - -/** @brief Checks if the specified I2S interrupt source is enabled or disabled. - * @param __HANDLE__ specifies the I2S Handle. - * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__ specifies the I2S interrupt source to check. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ - & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks whether the specified I2S flag is set or not. - * @param __HANDLE__ specifies the I2S Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2S_FLAG_RXNE: Receive buffer not empty flag - * @arg I2S_FLAG_TXE: Transmit buffer empty flag - * @arg I2S_FLAG_UDR: Underrun flag - * @arg I2S_FLAG_OVR: Overrun flag - * @arg I2S_FLAG_FRE: Frame error flag - * @arg I2S_FLAG_CHSIDE: Channel Side flag - * @arg I2S_FLAG_BSY: Busy flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the I2S OVR pending flag. - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ - __IO uint32_t tmpreg_ovr = 0x00U; \ - tmpreg_ovr = (__HANDLE__)->Instance->DR; \ - tmpreg_ovr = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_ovr); \ - }while(0U) -/** @brief Clears the I2S UDR pending flag. - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ - __IO uint32_t tmpreg_udr = 0x00U;\ - tmpreg_udr = ((__HANDLE__)->Instance->SR);\ - UNUSED(tmpreg_udr); \ - }while(0U) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2S_Exported_Functions - * @{ - */ - -/** @addtogroup I2S_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); -void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); -void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, - pI2S_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup I2S_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ***************************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); - -/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ -void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); -/** - * @} - */ - -/** @addtogroup I2S_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2S_Private_Macros I2S Private Macros - * @{ - */ - -/** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of I2S SR regsiter. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2S_FLAG_RXNE: Receive buffer not empty flag - * @arg I2S_FLAG_TXE: Transmit buffer empty flag - * @arg I2S_FLAG_UDR: Underrun error flag - * @arg I2S_FLAG_OVR: Overrun flag - * @arg I2S_FLAG_CHSIDE: Channel side flag - * @arg I2S_FLAG_BSY: Busy flag - * @retval SET or RESET. - */ -#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ - & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) - -/** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of I2S CR2 regsiter. - * @param __INTERRUPT__ specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval SET or RESET. - */ -#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ - & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks if I2S Mode parameter is in allowed range. - * @param __MODE__ specifies the I2S Mode. - * This parameter can be a value of @ref I2S_Mode - * @retval None - */ -#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ - ((__MODE__) == I2S_MODE_SLAVE_RX) || \ - ((__MODE__) == I2S_MODE_MASTER_TX) || \ - ((__MODE__) == I2S_MODE_MASTER_RX)) - -#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ - ((__STANDARD__) == I2S_STANDARD_MSB) || \ - ((__STANDARD__) == I2S_STANDARD_LSB) || \ - ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ - ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) - -#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ - ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ - ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ - ((__FORMAT__) == I2S_DATAFORMAT_32B)) - -#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ - ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) - -#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ - ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ - ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) - -/** @brief Checks if I2S Serial clock steady state parameter is in allowed range. - * @param __CPOL__ specifies the I2S serial clock steady state. - * This parameter can be a value of @ref I2S_Clock_Polarity - * @retval None - */ -#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ - ((__CPOL__) == I2S_CPOL_HIGH)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* SPI_I2S_SUPPORT */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32WBxx_HAL_I2S_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lcd.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lcd.h index 508940a..46cd03b 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lcd.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lcd.h @@ -545,9 +545,6 @@ typedef struct * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status. - * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR - * goes from 0 to 1. On deactivation it reflects the real status of - * LCD so it becomes 0 at the end of the last displayed frame. * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at * the beginning of a new frame, at the same time as the display data is * updated. @@ -558,6 +555,9 @@ typedef struct * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. * This flag is set by hardware each time the LCD_FCR register is updated * in the LCDCLK domain. + * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR + * goes from 0 to 1. On deactivation it reflects the real status of + * LCD so it becomes 0 at the end of the last displayed frame. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h index 60d9091..b582b80 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h @@ -317,9 +317,13 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #define LPTIM_INPUT1SOURCE_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */ +#if defined(COMP1) #define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */ +#endif +#if defined(COMP2) #define LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */ #define LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */ +#endif /** * @} */ @@ -329,7 +333,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #define LPTIM_INPUT2SOURCE_GPIO 0x00000000U /*!< For LPTIM1 */ +#if defined(COMP2) #define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */ +#endif /** * @} */ @@ -533,56 +539,12 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** - * @brief Enable the LPTIM1 EXTI line in interrupt mode. - * @retval None - */ #define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1) - -/** - * @brief Disable the LPTIM1 EXTI line in interrupt mode. - * @retval None - */ #define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1)) - -/** - * @brief Enable the LPTIM1 EXTI line in event mode. - * @retval None - */ -#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1) - -/** - * @brief Disable the LPTIM1 EXTI line in event mode. - * @retval None - */ -#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1)) - -/** - * @brief Enable the LPTIM2 EXTI line in interrupt mode. - * @retval None - */ #define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2) - -/** - * @brief Disable the LPTIM2 EXTI line in interrupt mode. - * @retval None - */ #define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2)) - -/** - * @brief Enable the LPTIM2 EXTI line in event mode. - * @retval None - */ -#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2) - -/** - * @brief Disable the LPTIM2 EXTI line in event mode. - * @retval None - */ -#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2)) - /** * @} */ @@ -806,6 +768,8 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) +#if defined(COMP1) +#if defined(COMP2) #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) && \ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ @@ -816,11 +780,35 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))) +#else +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))) +#endif +#else +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) && \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO))) +#endif +#if defined(COMP2) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ (((__INSTANCE__) == LPTIM1) && \ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) +#else +#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO))) +#endif /** * @} diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h index c076705..07b918a 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h @@ -196,7 +196,7 @@ typedef struct #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__))) #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) @@ -463,7 +463,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ /* toggle first bit ? */ \ @@ -487,7 +487,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ /* toggle first bit ? */ \ @@ -512,7 +512,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ /* toggle first bit ? */ \ @@ -576,7 +576,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_KIND(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ @@ -584,7 +584,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_SET_EP_KIND */ #define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ \ @@ -616,7 +616,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ \ @@ -624,7 +624,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_CLEAR_RX_EP_CTR */ #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ \ @@ -638,7 +638,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_RX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wEPVal; \ + uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ @@ -646,7 +646,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_RX_DTOG */ #define PCD_TX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wEPVal; \ + uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ @@ -659,7 +659,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ \ @@ -670,7 +670,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_CLEAR_RX_DTOG */ #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ \ @@ -688,7 +688,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ \ @@ -714,20 +714,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \ - register uint16_t *_wRegVal; \ - register uint32_t _wRegBase = (uint32_t)USBx; \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ *_wRegVal = ((wAddr) >> 1) << 1; \ } while(0) /* PCD_SET_EP_TX_ADDRESS */ #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \ - register uint16_t *_wRegVal; \ - register uint32_t _wRegBase = (uint32_t)USBx; \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ *_wRegVal = ((wAddr) >> 1) << 1; \ } while(0) /* PCD_SET_EP_RX_ADDRESS */ @@ -749,6 +749,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ #define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \ (wNBlocks) = (wCount) >> 5; \ + if (((wCount) & 0x1fU) == 0U) \ + { \ + (wNBlocks)--; \ + } \ *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ } while(0) /* PCD_CALC_BLK32 */ @@ -768,22 +772,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ *(pdwReg) |= USB_CNTRX_BLSIZE; \ } \ - else if((wCount) < 62U) \ + else if((wCount) <= 62U) \ { \ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - uint16_t *pdwReg; \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *pdwReg; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ - pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ } while(0) @@ -795,20 +799,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ *_wRegVal = (uint16_t)(wCount); \ } while(0) #define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ } while(0) @@ -883,8 +887,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* SetEPDblBuf0Count*/ #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \ - register uint32_t _wBase = (uint32_t)(USBx); \ - uint16_t *_wEPRegVal; \ + uint32_t _wBase = (uint32_t)(USBx); \ + __IO uint16_t *_wEPRegVal; \ \ if ((bDir) == 0U) \ { \ @@ -897,7 +901,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); { \ /* IN endpoint */ \ _wBase += (uint32_t)(USBx)->BTABLE; \ - _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ *_wEPRegVal = (uint16_t)(wCount); \ } \ } \ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h index 9d6a71a..4049791 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h @@ -105,7 +105,9 @@ typedef struct */ #define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */ #define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */ +#if defined(PWR_SUPPORT_STOP2) #define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/ +#endif #define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */ #define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */ /** diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h index c082821..edfa64b 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h @@ -366,7 +366,9 @@ typedef struct #endif #define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */ +#if defined(PWR_CR2_PVME1) #define PWR_FLAG_PVMO1 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO1_Pos) /*!< Power Voltage Monitoring 1 output flag */ +#endif #define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */ /*------------------------------EXTSCR---------------------------*/ @@ -938,7 +940,9 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); +#if defined(PWR_SUPPORT_STOP2) void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); +#endif void HAL_PWREx_EnterSHUTDOWNMode(void); void HAL_PWREx_PVD_PVM_IRQHandler(void); diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_qspi.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_qspi.h index 01ef0e0..47ead5c 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_qspi.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_qspi.h @@ -6,7 +6,8 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -422,7 +423,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); * @{ */ /** @brief Reset QSPI handle state. - * @param __HANDLE__ : QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) @@ -436,20 +437,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #endif /** @brief Enable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -462,8 +463,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -475,8 +476,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -489,8 +490,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -503,8 +504,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h index 1643d2f..4237c67 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h @@ -59,18 +59,27 @@ extern "C" { * @{ */ +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#else #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#endif -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON)) #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ ((__LSE__) == RCC_LSE_BYPASS)) @@ -89,9 +98,9 @@ extern "C" { #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) - +#if defined(RCC_HSI48_SUPPORT) #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) - +#endif #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ ((__PLL__) == RCC_PLL_ON)) @@ -173,16 +182,28 @@ extern "C" { ((__MCOX__) == RCC_MCO2)) #endif +#if defined(RCC_HSI48_SUPPORT) #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) +#else +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) +#endif #define IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__)) #define IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__)) @@ -275,8 +296,10 @@ typedef struct uint32_t MSIClockRange; /*!< The MSI frequency range. This parameter can be a value of @ref RCC_MSI_Clock_Range */ +#if defined(RCC_HSI48_SUPPORT) uint32_t HSI48State; /*!< The new state of the HSI48 . This parameter can be a value of @ref RCC_HSI48_Config */ +#endif RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ @@ -338,7 +361,9 @@ typedef struct #define RCC_OSCILLATORTYPE_LSI1 0x00000008U /*!< LSI1 to configure */ #define RCC_OSCILLATORTYPE_LSI2 0x00000010U /*!< LSI2 to configure */ #define RCC_OSCILLATORTYPE_MSI 0x00000020U /*!< MSI to configure */ +#if defined(RCC_HSI48_SUPPORT) #define RCC_OSCILLATORTYPE_HSI48 0x00000040U /*!< HSI48 to configure */ +#endif /** * @} */ @@ -348,7 +373,6 @@ typedef struct */ #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ -#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ /** * @} */ @@ -394,7 +418,7 @@ typedef struct * @} */ - +#if defined(RCC_HSI48_SUPPORT) /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ @@ -403,7 +427,7 @@ typedef struct /** * @} */ - +#endif /** @defgroup RCC_PLL_Config PLL Config * @{ @@ -517,9 +541,6 @@ typedef struct #define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */ #endif #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ -#if defined(SPI_I2S_SUPPORT) -#define RCC_PLL_I2SCLK RCC_PLLCFGR_PLLPEN /*!< PLLI2SCLK selection from main PLL */ -#endif /** * @} */ @@ -660,7 +681,9 @@ typedef struct #define RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1 /*!< LSI1 selection as MCO1 source */ #define RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2 /*!< LSI2 selection as MCO1 source */ #define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) #define RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48 /*!< HSI48 selection as MCO1 source */ +#endif #define RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB /*!< HSE before stabilization selection as MCO1 source */ /** @@ -720,7 +743,9 @@ typedef struct #endif #define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ #define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) #define RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /** * @} */ @@ -761,8 +786,9 @@ typedef struct #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ /* Flags in the CRRCR register */ +#if defined(RCC_HSI48_SUPPORT) #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ - +#endif /** * @} */ @@ -811,7 +837,9 @@ typedef struct #endif #define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_TSC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC) +#endif #define __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1) #if defined(DMA2) @@ -819,8 +847,9 @@ typedef struct #endif #define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_TSC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC) - +#endif /** * @} */ @@ -836,14 +865,14 @@ typedef struct #define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA) #define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB) #define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC) - #if defined(GPIOD) #define __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD) #endif #define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH) - +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1) #endif @@ -855,9 +884,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH) - +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC) - +#endif #if defined(AES1) #define __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1) #endif @@ -968,6 +997,9 @@ typedef struct * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) @@ -977,6 +1009,9 @@ typedef struct #define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) @@ -1004,7 +1039,9 @@ typedef struct #endif #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_TSC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC) +#endif #define __HAL_RCC_DMA1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)) #if defined(DMA2) @@ -1012,7 +1049,9 @@ typedef struct #endif #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)) #define __HAL_RCC_CRC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)) +#if defined(TSC) #define __HAL_RCC_TSC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)) +#endif /** * @} @@ -1034,7 +1073,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1) #endif @@ -1047,7 +1088,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)) #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)) +#endif #if defined(AES1) #define __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)) #endif @@ -1160,6 +1203,9 @@ typedef struct * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) @@ -1170,6 +1216,9 @@ typedef struct #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC)) +#endif #define __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)) #define __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)) @@ -1198,7 +1247,9 @@ typedef struct #define __HAL_RCC_C2DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_C2TSC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) +#endif #define __HAL_RCC_C2DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) #if defined(DMA2) @@ -1207,7 +1258,9 @@ typedef struct #define __HAL_RCC_C2DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_C2TSC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) +#endif /** * @} @@ -1229,7 +1282,9 @@ typedef struct #endif #define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) #endif @@ -1242,7 +1297,9 @@ typedef struct #endif #define __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) #endif @@ -1347,6 +1404,9 @@ typedef struct * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_C2TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_C2SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1) @@ -1356,6 +1416,9 @@ typedef struct #define __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1) @@ -1378,11 +1441,14 @@ typedef struct */ #define __HAL_RCC_C2BLE_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE) +#if defined(RCC_802_SUPPORT) #define __HAL_RCC_C2802_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802) +#endif #define __HAL_RCC_C2BLE_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE) +#if defined(RCC_802_SUPPORT) #define __HAL_RCC_C2802_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802) - +#endif /** * @} @@ -1403,7 +1469,9 @@ typedef struct #define __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_C2TSC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC) +#endif #define __HAL_RCC_C2DMA1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)) #if defined(DMA2) @@ -1412,7 +1480,9 @@ typedef struct #define __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)) #define __HAL_RCC_C2SRAM1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)) #define __HAL_RCC_C2CRC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)) +#if defined(TSC) #define __HAL_RCC_C2TSC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC)) +#endif /** * @} @@ -1434,7 +1504,9 @@ typedef struct #endif #define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1) #endif @@ -1447,7 +1519,9 @@ typedef struct #endif #define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)) #define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)) +#endif #if defined(AES1) #define __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)) #endif @@ -1552,6 +1626,9 @@ typedef struct * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_C2TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_C2SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1) @@ -1561,6 +1638,9 @@ typedef struct #define __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC)) +#endif #define __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)) #define __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)) #define __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)) @@ -1584,10 +1664,14 @@ typedef struct */ #define __HAL_RCC_C2BLE_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE) +#if defined(RCC_802_SUPPORT) #define __HAL_RCC_C2802_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802) +#endif #define __HAL_RCC_C2BLE_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)) +#if defined(RCC_802_SUPPORT) #define __HAL_RCC_C2802_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)) +#endif /** * @} @@ -1605,7 +1689,9 @@ typedef struct #endif #define __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_TSC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC) +#endif #define __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL) @@ -1615,7 +1701,9 @@ typedef struct #endif #define __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_TSC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC) +#endif /** @@ -1635,7 +1723,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1) #endif @@ -1649,7 +1739,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1) #endif @@ -1762,6 +1854,9 @@ typedef struct * @{ */ #define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL) +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) @@ -1772,6 +1867,9 @@ typedef struct #endif #define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL) +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) @@ -1813,7 +1911,9 @@ typedef struct #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) +#endif #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) #if defined(DMA2) @@ -1822,7 +1922,9 @@ typedef struct #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) +#endif #define __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) #if defined(DMA2) @@ -1831,7 +1933,9 @@ typedef struct #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) #define __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) +#endif #define __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) #if defined(DMA2) @@ -1841,7 +1945,9 @@ typedef struct #define __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) #define __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) +#if defined(TSC) #define __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) +#endif /** * @} @@ -1863,7 +1969,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) #endif @@ -1876,7 +1984,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) #endif @@ -1889,7 +1999,9 @@ typedef struct #endif #define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) #endif @@ -1902,7 +2014,9 @@ typedef struct #endif #define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) +#endif #if defined(AES1) #define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) #endif @@ -2071,6 +2185,9 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1) @@ -2080,6 +2197,9 @@ typedef struct #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1) @@ -2089,6 +2209,9 @@ typedef struct #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) @@ -2098,6 +2221,9 @@ typedef struct #define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) +#endif #define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) #define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) #define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) @@ -2125,7 +2251,9 @@ typedef struct #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) +#if defined(TSC) #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) +#endif #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) #if defined(DMA2) @@ -2134,7 +2262,9 @@ typedef struct #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) +#if defined(TSC) #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) +#endif #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET) #if defined(DMA2) @@ -2143,7 +2273,9 @@ typedef struct #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET) #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET) #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET) +#if defined(TSC) #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET) +#endif #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET) #if defined(DMA2) @@ -2152,7 +2284,9 @@ typedef struct #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET) #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET) #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET) +#if defined(TSC) #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) == RESET) +#endif /** * @} */ @@ -2173,7 +2307,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) +#endif #if defined(AES1) #define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET) #endif @@ -2186,7 +2322,9 @@ typedef struct #endif #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) +#endif #if defined(AES1) #define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET) #endif @@ -2199,7 +2337,9 @@ typedef struct #endif #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET) #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET) +#endif #if defined(AES1) #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET) #endif @@ -2212,7 +2352,9 @@ typedef struct #endif #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET) #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET) +#if defined(ADC_SUPPORT_5_MSPS) #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET) +#endif #if defined(AES1) #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET) #endif @@ -2379,6 +2521,9 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) != RESET) +#endif #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) @@ -2388,6 +2533,9 @@ typedef struct #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) == RESET) +#endif #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) @@ -2397,6 +2545,9 @@ typedef struct #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) != RESET) +#endif #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET) #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET) #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET) @@ -2406,6 +2557,9 @@ typedef struct #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET) #endif +#if defined(ADC_SUPPORT_2_5_MSPS) +#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) == RESET) +#endif #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET) #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET) #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET) @@ -2427,10 +2581,14 @@ typedef struct * @{ */ #define __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE) +#if defined(RCC_802_SUPPORT) #define __HAL_RCC_C2802_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802) +#endif #define __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE) +#if defined(RCC_802_SUPPORT) #define __HAL_RCC_C2802_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802) +#endif /** * @} */ @@ -2444,10 +2602,14 @@ typedef struct * @{ */ #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET) +#if defined(RCC_802_SUPPORT) #define __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET) +#endif #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET) +#if defined(RCC_802_SUPPORT) #define __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET) +#endif /** * @} */ @@ -2649,10 +2811,7 @@ typedef struct /** * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * @note After enabling the HSE (RCC_HSE_ON), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the @@ -2667,7 +2826,7 @@ typedef struct * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. - * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. + * @note (*) Value not defined for all devices * @retval None */ #define __HAL_RCC_HSE_CONFIG(__STATE__) \ @@ -2676,15 +2835,9 @@ typedef struct { \ LL_RCC_HSE_Enable(); \ } \ - else if((__STATE__) == RCC_HSE_BYPASS) \ - { \ - LL_RCC_HSE_EnableBypass(); \ - LL_RCC_HSE_Enable(); \ - } \ else \ { \ LL_RCC_HSE_Disable(); \ - LL_RCC_HSE_DisableBypass(); \ } \ } while(0U) @@ -2734,6 +2887,7 @@ typedef struct } while(0U) +#if defined(RCC_HSI48_SUPPORT) /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. * @note After enabling the HSI48, the application software should wait on HSI48RDY @@ -2743,6 +2897,7 @@ typedef struct */ #define __HAL_RCC_HSI48_ENABLE() LL_RCC_HSI48_Enable() #define __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable() +#endif /** @brief Macros to configure HSE sense amplifier threshold. * @note to configure HSE sense amplifier, first disable HSE @@ -2786,6 +2941,12 @@ typedef struct /** @brief Macros to configure the RTC clock (RTCCLK). + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure @@ -2793,14 +2954,6 @@ typedef struct * @note Once the RTC clock is configured it cannot be changed unless the * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). - * - * @param __RTC_CLKSOURCE__ specifies the RTC clock source. - * This parameter can be one of the following values:* - * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected - * * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC @@ -2833,13 +2986,13 @@ typedef struct #define __HAL_RCC_PLL_DISABLE() LL_RCC_PLL_Disable() /** @brief Macro to configure the PLL clock source. - * @note This function must be used only when the main PLL is disabled. * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @note This function must be used only when the main PLL is disabled. * @note This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1). * @retval None * @@ -2935,7 +3088,6 @@ typedef struct * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) - * @arg @ref RCC_PLL_I2SCLK This Clock is used to generate the clock for the I2S * @retval None */ #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) @@ -3016,8 +3168,8 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source - + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source (*) + * * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 @@ -3025,6 +3177,8 @@ typedef struct * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + * + * @note (*) Value not defined for all devices */ #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__)) @@ -3045,8 +3199,11 @@ typedef struct * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable - * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*) * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable + * + * @note (*) Value not defined for all devices + * * @retval None */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) @@ -3062,8 +3219,11 @@ typedef struct * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable - * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*) * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable + * + * @note (*) Value not defined for all devices + * * @retval None */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) @@ -3081,8 +3241,10 @@ typedef struct * @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt clear * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt clear * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt clear - * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt clear + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt clear (*) * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt clear + * + * @note (*) Value not defined for all devices */ #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) @@ -3098,8 +3260,11 @@ typedef struct * @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt flag * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt flag * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt flag - * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt flag + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt flag (*) * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt flag + * + * @note (*) Value not defined for all devices + * * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) @@ -3114,23 +3279,26 @@ typedef struct /** @brief Check whether the selected RCC flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready - * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready - * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready - * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready - * @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready - * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 - * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready - * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection - * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready - * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready - * @arg @ref RCC_FLAG_BORRST BOR reset - * @arg @ref RCC_FLAG_OBLRST OBLRST reset - * @arg @ref RCC_FLAG_PINRST Pin reset - * @arg @ref RCC_FLAG_SFTRST Software reset - * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset - * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready + * @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready + * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 (*) + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready + * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready + * @arg @ref RCC_FLAG_BORRST BOR reset + * @arg @ref RCC_FLAG_OBLRST OBLRST reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * + * @note (*) Value not defined for all devices + * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h index 789a288..7d527e9 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h @@ -86,21 +86,17 @@ extern "C" { (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)) -#elif defined(LPUART1) && defined(USB) && defined(RCC_SMPS_SUPPORT) && defined(SPI_I2S_SUPPORT) +#elif defined(LPUART1) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ - (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)) + (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)) #else #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ @@ -159,6 +155,7 @@ extern "C" { ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) +#if defined(RCC_HSI48_SUPPORT) #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ @@ -166,6 +163,14 @@ extern "C" { ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) +#else +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) +#endif #if defined(USB) #if defined(SAI1) @@ -182,18 +187,12 @@ extern "C" { #endif #endif -#if defined(STM32WB55xx) || defined (STM32WB5Mxx) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) -#elif defined(STM32WB35xx) -#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) #else #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ @@ -204,7 +203,6 @@ extern "C" { #define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024)) #if defined(RCC_SMPS_SUPPORT) @@ -220,13 +218,6 @@ extern "C" { ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE)) #endif -#if defined(SPI_I2S_SUPPORT) -#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2SCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_I2SCLKSOURCE_PIN)) -#endif #if defined(SAI1) #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) @@ -363,10 +354,6 @@ typedef struct This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ #endif -#if defined(SPI_I2S_SUPPORT) - uint32_t I2sClockSelection; /*!< Specifies I2s clock source. - This parameter can be a value of @ref RCCEx_I2s_Clock_Source */ -#endif } RCC_PeriphCLKInitTypeDef; @@ -478,9 +465,6 @@ typedef struct #if defined(RCC_SMPS_SUPPORT) #define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */ #endif -#if defined(SPI_I2S_SUPPORT) -#define RCC_PERIPHCLK_I2S 0x00004000U /*!< I2S Peripheral Clock Selection */ -#endif /** * @} */ @@ -599,10 +583,8 @@ typedef struct */ #define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */ -#if defined(STM32WB55xx) || defined (STM32WB5Mxx) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) #define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */ -#elif defined(STM32WB35xx) -#define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */ #endif #define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ @@ -626,9 +608,8 @@ typedef struct * @{ */ -#define RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE /*!< None clock selected as RF system wakeup clock */ -#define RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE /*!< LSE clock selected as RF system wakeup clock */ -#define RCC_RFWKPCLKSOURCE_LSI LL_RCC_RFWKP_CLKSOURCE_LSI /*!< LSI clock selected as RF system wakeup clock */ +#define RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE /*!< None clock selected as RF system wakeup clock */ +#define RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE /*!< LSE clock selected as RF system wakeup clock */ #define RCC_RFWKPCLKSOURCE_HSE_DIV1024 LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 /*!< HSE clock divided by 1024 selected as RF system wakeup clock */ /** @@ -669,18 +650,6 @@ typedef struct */ #endif -#if defined(SPI_I2S_SUPPORT) -/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source - * @{ - */ -#define RCC_I2SCLKSOURCE_NONE LL_RCC_I2S_CLKSOURCE_NONE /*!< No clock selected as I2S clock */ -#define RCC_I2SCLKSOURCE_PLL LL_RCC_I2S_CLKSOURCE_PLL /*!< PLL "Q" clock selected as I2S clock source */ -#define RCC_I2SCLKSOURCE_HSI LL_RCC_I2S_CLKSOURCE_HSI /*!< HSI clock selected as I2S clock */ -#define RCC_I2SCLKSOURCE_PIN LL_RCC_I2S_CLKSOURCE_PIN /*!< External clock selected as I2S clock */ -/** - * @} - */ -#endif /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ @@ -1219,7 +1188,6 @@ typedef struct * This parameter can be one of the following values: * @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock * @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock - * @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock * @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock * @retval None */ @@ -1229,7 +1197,6 @@ typedef struct * This parameter can be one of the following values: * @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock * @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock - * @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock * @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock */ #define __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource() @@ -1294,27 +1261,6 @@ typedef struct * @{ */ -#if defined(SPI_I2S_SUPPORT) -/** @brief Macro to configure the I2S clock (I2SCLK). - * @param __I2S_CLKSOURCE__ specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock - * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock - * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock - * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock - * @retval None - */ -#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) LL_RCC_SetI2SClockSource(__I2S_CLKSOURCE__) - -/** @brief Macro to get the I2S clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock - * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock - * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock - * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock - */ -#define __HAL_RCC_GET_I2S_SOURCE() LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE) -#endif #if defined(SAI1) /** @brief Enable PLLSAI1RDY interrupt. diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rng.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rng.h index 1c170b8..333d2f4 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rng.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rng.h @@ -22,7 +22,7 @@ #define STM32WBxx_HAL_RNG_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc.h index 2ac6577..dded802 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc.h @@ -725,7 +725,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not by core 2. * @retval Line Status. */ -#define __HAL_RTC_ALARM_EXTIC2_GET_FLAG() (EXTI->PR2 & RTC_EXTI_LINE_ALARM_EVENT) +#define __HAL_RTC_ALARM_EXTIC2_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT) /** * @brief Clear the RTC Alarm associated Exti line flag. @@ -737,7 +737,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @brief Clear the RTC Alarm associated Exti line flag. * @retval None. */ -#define __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG() (EXTI->PR2 = (RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG() (EXTI->PR1 = (RTC_EXTI_LINE_ALARM_EVENT)) /*----------------------------*/ /** diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h index fc236d1..65eae22 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h @@ -991,7 +991,7 @@ typedef struct * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 2. * @retval Line Status. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_GET_FLAG() (EXTI->PR2 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** * @brief Clear the RTC Tamper and Timestamp associated Exti line flag of core 1. diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smartcard.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smartcard.h index b732c25..bd4c0c0 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smartcard.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smartcard.h @@ -157,14 +157,14 @@ typedef struct * 01 : (Not Used) * 10 : Timeout * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (Peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -174,9 +174,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -234,7 +234,7 @@ typedef struct __SMARTCARD_HandleTypeDef __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ - uint32_t ErrorCode; /*!< SmartCard Error code */ + __IO uint32_t ErrorCode; /*!< SmartCard Error code */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */ @@ -253,7 +253,6 @@ typedef struct __SMARTCARD_HandleTypeDef void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */ - void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */ void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */ @@ -293,11 +292,11 @@ typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard) */ typedef enum { - SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */ } SMARTCARD_ClockSourceTypeDef; /** @@ -422,7 +421,6 @@ typedef enum * @} */ - /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable * @{ */ @@ -441,7 +439,7 @@ typedef enum * @} */ -/** @defgroup SMARTCARD_ClockPrescaler Clock Prescaler +/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler * @{ */ #define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ @@ -456,7 +454,6 @@ typedef enum #define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ - /** * @} */ @@ -560,15 +557,15 @@ typedef enum */ #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0U) #else #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ } while(0U) #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -576,11 +573,11 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0U) +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -606,7 +603,6 @@ typedef enum */ #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) - /** @brief Clear the SMARTCARD FE pending flag. * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None @@ -642,15 +638,15 @@ typedef enum * @arg @ref SMARTCARD_FLAG_EOBF End of block flag * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag - * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag - * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag * @arg @ref SMARTCARD_FLAG_NE Noise error flag * @arg @ref SMARTCARD_FLAG_FE Framing error flag * @arg @ref SMARTCARD_FLAG_PE Parity error flag + * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag + * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag * @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag * @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag * @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag @@ -666,14 +662,14 @@ typedef enum * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption @@ -691,14 +687,14 @@ typedef enum * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption @@ -709,7 +705,6 @@ typedef enum ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) - /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check. @@ -717,21 +712,22 @@ typedef enum * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -740,14 +736,14 @@ typedef enum * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption @@ -755,9 +751,8 @@ typedef enum * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) - + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -784,7 +779,6 @@ typedef enum * This parameter can be one of the following values: * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request - * * @retval None */ #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) @@ -799,7 +793,8 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -831,8 +826,8 @@ typedef enum do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ break; \ @@ -848,7 +843,7 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ @@ -885,102 +880,91 @@ typedef enum */ #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) -/** - * @brief Ensure that SMARTCARD frame length is valid. +/** @brief Ensure that SMARTCARD frame length is valid. * @param __LENGTH__ SMARTCARD frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) -/** - * @brief Ensure that SMARTCARD frame number of stop bits is valid. +/** @brief Ensure that SMARTCARD frame number of stop bits is valid. * @param __STOPBITS__ SMARTCARD frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)) -/** - * @brief Ensure that SMARTCARD frame parity is valid. +/** @brief Ensure that SMARTCARD frame parity is valid. * @param __PARITY__ SMARTCARD frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ ((__PARITY__) == SMARTCARD_PARITY_ODD)) -/** - * @brief Ensure that SMARTCARD communication mode is valid. +/** @brief Ensure that SMARTCARD communication mode is valid. * @param __MODE__ SMARTCARD communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that SMARTCARD frame polarity is valid. +/** @brief Ensure that SMARTCARD frame polarity is valid. * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ -#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\ + || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) -/** - * @brief Ensure that SMARTCARD frame phase is valid. +/** @brief Ensure that SMARTCARD frame phase is valid. * @param __CPHA__ SMARTCARD frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) -/** - * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. +/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame sampling is valid. +/** @brief Ensure that SMARTCARD frame sampling is valid. * @param __ONEBIT__ SMARTCARD frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) -/** - * @brief Ensure that SMARTCARD NACK transmission setting is valid. +/** @brief Ensure that SMARTCARD NACK transmission setting is valid. * @param __NACK__ SMARTCARD NACK transmission setting. * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) */ #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ ((__NACK__) == SMARTCARD_NACK_DISABLE)) -/** - * @brief Ensure that SMARTCARD receiver timeout setting is valid. +/** @brief Ensure that SMARTCARD receiver timeout setting is valid. * @param __TIMEOUT__ SMARTCARD receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) -/** - * @brief Ensure that SMARTCARD clock Prescaler is valid. +/** @brief Ensure that SMARTCARD clock Prescaler is valid. * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ -#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) - -/** - * @brief Ensure that SMARTCARD advanced features initialization is valid. +#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) + +/** @brief Ensure that SMARTCARD advanced features initialization is valid. * @param __INIT__ SMARTCARD advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ @@ -993,64 +977,56 @@ typedef enum SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) -/** - * @brief Ensure that SMARTCARD frame TX inversion setting is valid. +/** @brief Ensure that SMARTCARD frame TX inversion setting is valid. * @param __TXINV__ SMARTCARD frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame RX inversion setting is valid. +/** @brief Ensure that SMARTCARD frame RX inversion setting is valid. * @param __RXINV__ SMARTCARD frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame data inversion setting is valid. +/** @brief Ensure that SMARTCARD frame data inversion setting is valid. * @param __DATAINV__ SMARTCARD frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. +/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame overrun setting is valid. +/** @brief Ensure that SMARTCARD frame overrun setting is valid. * @param __OVERRUN__ SMARTCARD frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) -/** - * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. +/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) -/** - * @brief Ensure that SMARTCARD frame MSB first setting is valid. +/** @brief Ensure that SMARTCARD frame MSB first setting is valid. * @param __MSBFIRST__ SMARTCARD frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) -/** - * @brief Ensure that SMARTCARD request parameter is valid. +/** @brief Ensure that SMARTCARD request parameter is valid. * @param __PARAM__ SMARTCARD request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ @@ -1064,7 +1040,6 @@ typedef enum /* Include SMARTCARD HAL Extended module */ #include "stm32wbxx_hal_smartcard_ex.h" - /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMARTCARD_Exported_Functions * @{ @@ -1082,8 +1057,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** @@ -1095,8 +1072,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @{ */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smartcard_ex.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smartcard_ex.h index 1df86a7..64ec116 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smartcard_ex.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smartcard_ex.h @@ -68,7 +68,7 @@ extern "C" { * @} */ -/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode +/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode * @brief SMARTCARD FIFO mode * @{ */ @@ -78,7 +78,7 @@ extern "C" { * @} */ -/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level +/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level * @brief SMARTCARD TXFIFO level * @{ */ @@ -92,7 +92,7 @@ extern "C" { * @} */ -/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level +/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level * @brief SMARTCARD RXFIFO level * @{ */ @@ -207,7 +207,7 @@ extern "C" { do { \ if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ { \ - (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ + (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ } \ else \ { \ @@ -222,49 +222,45 @@ extern "C" { * reported. * @retval Transmission completion flag */ -#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ +#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) -/** - * @brief Ensure that SMARTCARD frame transmission completion used flag is valid. +/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid. * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) */ -#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\ +#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \ ((__TXCOMPLETE__) == SMARTCARD_TC)) -/** - * @brief Ensure that SMARTCARD FIFO mode is valid. +/** @brief Ensure that SMARTCARD FIFO mode is valid. * @param __STATE__ SMARTCARD FIFO mode. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ - ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) -/** - * @brief Ensure that SMARTCARD TXFIFO threshold level is valid. +/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid. * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) -/** - * @brief Ensure that SMARTCARD RXFIFO threshold level is valid. +/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid. * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) /** * @} @@ -323,7 +319,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs * @} */ - /* Private functions ---------------------------------------------------------*/ /** diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h index c67c0c4..f522139 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h @@ -65,7 +65,7 @@ typedef struct uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of @ref SMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. @@ -132,7 +132,11 @@ typedef struct * @brief SMBUS handle Structure definition * @{ */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) typedef struct __SMBUS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ { I2C_TypeDef *Instance; /*!< SMBUS registers base address */ @@ -326,6 +330,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) @@ -582,11 +587,12 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((REQUEST) == SMBUS_NO_STARTSTOP)) -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ ((REQUEST) == SMBUS_FIRST_FRAME) || \ ((REQUEST) == SMBUS_NEXT_FRAME) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h index 7b2a571..e247a1a 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h @@ -582,7 +582,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of SPI SR regsiter. + * @param __SR__ copy of SPI SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag @@ -596,10 +596,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_FLAG_FRLVL: SPI fifo reception level * @retval SET or RESET. */ -#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of SPI CR2 regsiter. + * @param __CR2__ copy of SPI CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable @@ -607,15 +608,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR: Error interrupt enable * @retval SET or RESET. */ -#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. * This parameter can be a value of @ref SPI_Mode * @retval None */ -#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ - ((__MODE__) == SPI_MODE_MASTER)) +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) /** @brief Checks if SPI Direction Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Direction Mode. @@ -663,33 +665,33 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_Clock_Polarity * @retval None */ -#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ - ((__CPOL__) == SPI_POLARITY_HIGH)) +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) /** @brief Checks if SPI Clock Phase parameter is in allowed range. * @param __CPHA__ specifies the SPI Clock Phase. * This parameter can be a value of @ref SPI_Clock_Phase * @retval None */ -#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ - ((__CPHA__) == SPI_PHASE_2EDGE)) +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) /** @brief Checks if SPI Slave Select parameter is in allowed range. * @param __NSS__ specifies the SPI Slave Select management parameter. * This parameter can be a value of @ref SPI_Slave_Select_management * @retval None */ -#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ - ((__NSS__) == SPI_NSS_HARD_INPUT) || \ - ((__NSS__) == SPI_NSS_HARD_OUTPUT)) +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) /** @brief Checks if SPI NSS Pulse parameter is in allowed range. * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. * This parameter can be a value of @ref SPI_NSSP_Mode * @retval None */ -#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ - ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. * @param __PRESCALER__ specifies the SPI Baudrate prescaler. @@ -710,16 +712,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_MSB_LSB_transmission * @retval None */ -#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ - ((__BIT__) == SPI_FIRSTBIT_LSB)) +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) /** @brief Checks if SPI TI mode parameter is in allowed range. * @param __MODE__ specifies the SPI TI mode. * This parameter can be a value of @ref SPI_TI_mode * @retval None */ -#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ - ((__MODE__) == SPI_TIMODE_ENABLE)) +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) /** @brief Checks if SPI CRC calculation enabled state is in allowed range. * @param __CALCULATION__ specifies the SPI CRC calculation enable state. @@ -734,8 +736,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_CRC_length * @retval None */ -#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. @@ -743,7 +745,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 * @retval None */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h index 0016aa6..eaad4ea 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h @@ -282,12 +282,16 @@ typedef struct This parameter can be a value of @ref TIM_Break_Polarity */ uint32_t BreakFilter; /*!< Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ uint32_t Break2State; /*!< TIM Break2 State This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ uint32_t Break2Polarity; /*!< TIM Break2 input polarity This parameter can be a value of @ref TIM_Break2_Polarity */ uint32_t Break2Filter; /*!< TIM break2 input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; @@ -304,6 +308,26 @@ typedef enum HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + /** * @brief HAL Active channel structures definition */ @@ -327,13 +351,16 @@ typedef struct __TIM_HandleTypeDef typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ @@ -373,35 +400,35 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - - ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ - ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** @@ -857,6 +884,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ + /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ */ @@ -875,6 +911,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ + /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ @@ -1101,25 +1146,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1828,12 +1897,20 @@ mode. #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + + #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ ((__STATE__) == TIM_BREAK2_DISABLE)) #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + + #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) @@ -1923,15 +2000,15 @@ mode. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ @@ -1942,6 +2019,8 @@ mode. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) @@ -1978,6 +2057,50 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + /** * @} */ @@ -2149,9 +2272,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -2197,6 +2326,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ @@ -2216,7 +2350,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim_ex.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim_ex.h index 0c53871..efd46fc 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim_ex.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim_ex.h @@ -89,8 +89,10 @@ TIMEx_BreakInputConfigTypeDef; */ #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is not connected to I/O */ #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */ +#if defined(ADC_SUPPORT_5_MSPS) #define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD3 */ +#endif #if defined(COMP1) #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ #endif /* COMP1 */ @@ -126,15 +128,19 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */ #endif /* COMP1 && COMP2 */ +#if defined(TIM16) #define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */ #define TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */ #define TIM_TIM16_TI1_LSE TIM16_OR_TI1_RMP_1 /* !< TIM16_TI1 is connected to LSE Clock */ #define TIM_TIM16_TI1_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_TI1_RMP_1) /* !< TIM16_TI1 is connected to RTC */ +#endif /* TIM16 */ +#if defined(TIM17) #define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to I/O */ #define TIM_TIM17_TI1_MSI TIM17_OR_TI1_RMP_0 /* !< TIM17_TI1 is connected to MSI */ #define TIM_TIM17_TI1_HSE TIM17_OR_TI1_RMP_1 /* !< TIM17_TI1 is connected to HSE/32 */ #define TIM_TIM17_TI1_MCO (TIM17_OR_TI1_RMP_0 | TIM17_OR_TI1_RMP_1) /* !< TIM17_TI1 is connected to MCO */ +#endif /* TIM17 */ /** * @} */ @@ -199,33 +205,46 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros * @{ */ +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFE3FECU) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFE3FF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) +#else #define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ - ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFE3FECU) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFE3FF0U) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \ - || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) + ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) +#endif -#define IS_TIM_BREAKINPUT(__BREAKINPUT__) \ - (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ - ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) \ + (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) -#if defined(COMP1) && defined(COMP2) -#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \ - (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) +#if defined(COMP1) +#if defined(COMP2) +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \ + (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) +#else +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \ + (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)) +#endif #else #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \ - (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)) + (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)) #endif -#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \ - (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ - ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \ + (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) -#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) \ - (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) \ + (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) /** * @} @@ -335,6 +354,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t B TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); /** * @} */ @@ -358,6 +380,7 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_uart.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_uart.h index 47f158b..178eda1 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_uart.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_uart.h @@ -1176,7 +1176,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)\ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) #endif @@ -1186,7 +1186,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U)\ + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. @@ -1195,7 +1195,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])\ + ((__BAUD__)/2U)) / (__BAUD__)) #if defined(LPUART1) @@ -1519,6 +1519,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #include "stm32wbxx_hal_uart_ex.h" +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART fonctions */ +extern const uint16_t UARTPrescTable[12]; + + /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_usart.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_usart.h index b1006e4..f751c0e 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_usart.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_usart.h @@ -138,7 +138,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value @@ -697,7 +697,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. * @retval Division result */ #define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_wwdg.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_wwdg.h index 8d69784..982848c 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_wwdg.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_wwdg.h @@ -56,7 +56,7 @@ typedef struct uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ - uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ } WWDG_InitTypeDef; @@ -68,17 +68,17 @@ typedef struct typedef struct __WWDG_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ { WWDG_TypeDef *Instance; /*!< Register base address */ WWDG_InitTypeDef Init; /*!< WWDG required parameters */ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ - void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ -#endif + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } WWDG_HandleTypeDef; #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) @@ -87,8 +87,8 @@ typedef struct */ typedef enum { - HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ - HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ + HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ } HAL_WWDG_CallbackIDTypeDef; /** @@ -96,7 +96,7 @@ typedef enum */ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} */ @@ -268,9 +268,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h index 4fbb1fd..57b51a7 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h @@ -53,6 +53,9 @@ extern "C" { /* Internal register offset for ADC group regular sequencer configuration */ /* (offset placed into a spare area of literal definition) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* No register ADC_SQRx on this ADC peripheral version */ +#else #define ADC_SQR1_REGOFFSET (0x00000000UL) #define ADC_SQR2_REGOFFSET (0x00000100UL) #define ADC_SQR3_REGOFFSET (0x00000200UL) @@ -60,10 +63,21 @@ extern "C" { #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ +#endif /* ADC_SUPPORT_2_5_MSPS */ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) /* Definition of ADC group regular sequencer bits information to be inserted */ /* into ADC group regular sequencer ranks literals definition. */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ +#else #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */ #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */ #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */ @@ -80,6 +94,7 @@ extern "C" { #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */ #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */ #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */ +#endif /* ADC_SUPPORT_2_5_MSPS */ @@ -176,11 +191,18 @@ extern "C" { /* - channel sampling time defined by SMPRx register offset */ /* and SMPx bits positions into SMPRx register */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) +#else #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) +#endif #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 serie, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ +#endif #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ /* Channel differentiation between external and internal channels */ #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ @@ -221,6 +243,27 @@ extern "C" { /* Definition of channels ID bitfield information to be inserted into */ /* channels literals definition. */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0) +#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1) +#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2) +#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3) +#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4) +#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5) +#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6) +#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7) +#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8) +#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9) +#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10) +#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11) +#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12) +#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13) +#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14) +#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15) +#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16) +#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17) +#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18) +#else #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0) #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1) #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2) @@ -240,6 +283,7 @@ extern "C" { #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16) #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17) #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18) +#endif /* Definition of channels sampling time information to be inserted into */ /* channels literals definition. */ @@ -264,6 +308,20 @@ extern "C" { #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */ +#if defined(ADC_SUPPORT_2_5_MSPS) +/* Internal mask for ADC channel sampling time: */ +/* To select into literals LL_ADC_SAMPLINGTIME_x */ +/* the relevant bits for: */ +/* (concatenation of multiple bits used in register SMPR) */ +/* - ADC channels sampling time: setting channel wise, to map each channel */ +/* on one of the common sampling time available. */ +/* - ADC channels common sampling time: set a sampling time into one of the */ +/* common sampling time available. */ +#define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS) +#define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1) +#define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS) + +#endif /* Internal mask for ADC mode single or differential ended: */ /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */ /* the relevant bits for: */ @@ -298,10 +356,16 @@ extern "C" { #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) +#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL) +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) +#else #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) +#endif #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ @@ -325,15 +389,49 @@ extern "C" { /* ADC registers bits positions */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */ +#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ +#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ +#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ +#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ +#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ +#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ +#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ +#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ +#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ +#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SMPR_SMP1" position in register */ +#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_SMPR_SMP2" position in register */ +#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ +#define ADC_CFGR_RES_BITOFFSET_POS ADC_CFGR1_RES_BITOFFSET_POS +#define ADC_CFGR_AWDSGL_BITOFFSET_POS ADC_CFGR1_AWDSGL_BITOFFSET_POS +#else #define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */ #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */ #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */ #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */ #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */ +#endif /* ADC registers bits groups */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ +#else #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ +#endif /* ADC internal channels related definitions */ @@ -424,6 +522,17 @@ typedef struct */ typedef struct { +#if defined (ADC_SUPPORT_2_5_MSPS) + uint32_t Clock; /*!< Set ADC instance clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE + @note On this STM32 serie, this parameter has some clock ratio constraints: + ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle + (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle). + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock(). + For more details, refer to description of this function. */ + +#endif uint32_t Resolution; /*!< Set ADC resolution. This parameter can be a value of @ref ADC_LL_EC_RESOLUTION @@ -501,6 +610,9 @@ typedef struct } LL_ADC_REG_InitTypeDef; +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Structure definition of some features of ADC group injected. * @note These parameters have an impact on ADC scope: ADC group injected. @@ -549,6 +661,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ } LL_ADC_INJ_InitTypeDef; +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} @@ -565,6 +678,10 @@ typedef struct * @{ */ #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */ +#else +#endif #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ @@ -575,6 +692,9 @@ typedef struct #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */ +#endif /** * @} */ @@ -584,6 +704,10 @@ typedef struct * @{ */ #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */ +#else +#endif #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ @@ -594,6 +718,9 @@ typedef struct #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */ +#endif /** * @} */ @@ -612,9 +739,11 @@ typedef struct /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ +#if !defined (ADC_SUPPORT_2_5_MSPS) #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ +#endif #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */ @@ -639,7 +768,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ @@ -647,6 +776,19 @@ typedef struct * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source + * @{ + */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */ +#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */ +/** + * @} + */ +#endif + /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution * @{ */ @@ -662,7 +804,7 @@ typedef struct * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -671,11 +813,37 @@ typedef struct * @{ */ #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ +#else #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode + * @{ + */ +#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +/** + * @} + */ + +#if defined(ADC_SUPPORT_2_5_MSPS) +/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels +* @{ +*/ +#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ +#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ /** * @} */ +#endif /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number * @{ */ @@ -700,8 +868,10 @@ typedef struct * @{ */ #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +#if !defined (ADC_SUPPORT_2_5_MSPS) #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/ #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ +#endif /** * @} */ @@ -709,6 +879,30 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ +#else #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ @@ -731,6 +925,8 @@ typedef struct #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. */ + +#endif /** * @} */ @@ -738,6 +934,15 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH4 ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#else #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ @@ -747,6 +952,7 @@ typedef struct #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#endif /** * @} */ @@ -791,9 +997,30 @@ typedef struct * @} */ +#if defined(ADC_SUPPORT_2_5_MSPS) +/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility +* @{ +*/ +#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ +#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */ +/** + * @} + */ + +#endif /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ +#else #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ @@ -810,14 +1037,29 @@ typedef struct #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ +#endif +/** + * @} + */ + +#if defined(ADC_SUPPORT_2_5_MSPS) +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 serie, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */ +#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 serie, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */ /** * @} */ +#endif /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +#else #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ @@ -826,6 +1068,7 @@ typedef struct #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} */ @@ -833,6 +1076,16 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ +#else #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ @@ -849,10 +1102,14 @@ typedef struct #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source * @{ */ @@ -926,10 +1183,21 @@ typedef struct /** * @} */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ +#else #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */ @@ -938,6 +1206,7 @@ typedef struct #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ +#endif /** * @} */ @@ -945,9 +1214,13 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_SINGLE_ENDED (0x00000000UL) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ +#else #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */ +#endif /** * @} */ @@ -956,8 +1229,12 @@ typedef struct * @{ */ #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */ +#else #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ +#endif /** * @} */ @@ -965,6 +1242,32 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ +#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ +#else #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ @@ -1035,6 +1338,7 @@ typedef struct #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} */ @@ -1052,11 +1356,16 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */ +#else #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ +#endif /** * @} */ @@ -1065,7 +1374,11 @@ typedef struct * @{ */ #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +#else #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +#endif /** * @} */ @@ -1144,7 +1457,8 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ @@ -1230,7 +1544,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval Value between Min_Data=0 and Max_Data=18 */ @@ -1276,12 +1590,19 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \ + ) +#else #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ (((__DECIMAL_NB__) <= 9UL) \ ? ( \ @@ -1296,6 +1617,7 @@ typedef struct (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ ) +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Helper macro to determine whether the selected channel @@ -1338,7 +1660,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. @@ -1383,7 +1705,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 @@ -1437,6 +1759,78 @@ typedef struct ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ ) +#if defined (ADC_SUPPORT_2_5_MSPS) +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 (7) + * @arg @ref LL_ADC_CHANNEL_2 (7) + * @arg @ref LL_ADC_CHANNEL_3 (7) + * @arg @ref LL_ADC_CHANNEL_4 (7) + * @arg @ref LL_ADC_CHANNEL_5 (7) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref LL_ADC_CHANNEL_VBAT (4) + * + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n + * (4) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0) + * + * (0) On STM32WB, parameter available only on analog watchdog number: AWD1. + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) +#else /** * @brief Helper macro to define ADC analog watchdog parameter: * define a single channel to monitor with analog watchdog @@ -1470,7 +1864,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done @@ -1482,76 +1876,77 @@ typedef struct * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) - * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0) - * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) * * (0) On STM32WB, parameter available only on analog watchdog number: AWD1. + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ @@ -1562,6 +1957,7 @@ typedef struct : \ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ ) +#endif /** * @brief Helper macro to set the value of ADC analog watchdog threshold high @@ -1993,9 +2389,9 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param CommonClock This parameter can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (*) + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 (*) + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 (*) * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 @@ -2008,11 +2404,17 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 + * + * (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx. * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock); +#else MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); +#endif } /** @@ -2022,9 +2424,9 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (*) + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 (*) + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 (*) * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 @@ -2037,10 +2439,16 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 + * + * (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx. */ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); +#else return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); +#endif } /** @@ -2186,6 +2594,95 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/** + * @brief Set ADC instance clock source and prescaler. + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 CKMODE LL_ADC_SetClock + * @param ADCx ADC instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) + * @arg @ref LL_ADC_CLOCK_ASYNC (1) + * + * (1) Asynchronous clock prescaler can be configured using + * function @ref LL_ADC_SetCommonClock().\n + * (2) Caution: This parameter has some clock ratio constraints: + * This configuration must be enabled only if PCLK has a 50% + * duty clock cycle (APB prescaler configured inside the RCC + * must be bypassed and the system clock must by 50% duty + * cycle). + * Refer to reference manual. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); +} + +/** + * @brief Get ADC instance clock source and prescaler. + * @rmtoll CFGR2 CKMODE LL_ADC_GetClock + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) + * @arg @ref LL_ADC_CLOCK_ASYNC (1) + * + * (1) Asynchronous clock prescaler can be retrieved using + * function @ref LL_ADC_GetCommonClock().\n + * (2) Caution: This parameter has some clock ratio constraints: + * This configuration must be enabled only if PCLK has a 50% + * duty clock cycle (APB prescaler configured inside the RCC + * must be bypassed and the system clock must by 50% duty + * cycle). + * Refer to reference manual. + */ +__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); +} +#endif + +#if defined (ADC_SUPPORT_2_5_MSPS) +/** + * @brief Set ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note This function is intended to set calibration parameters + * without having to perform a new calibration using + * @ref LL_ADC_StartCalibration(). + * @note For devices with differential mode available: + * Calibration of offset is specific to each of + * single-ended and differential modes + * (calibration factor must be specified for each of these + * differential modes, if used afterwards and if the application + * requires their calibration). + * @note In case of setting calibration factors of both modes single ended + * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): + * both calibration factors must be concatenated. + * To perform this processing, use helper macro + * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled, without calibration on going, without conversion + * on going on group regular. + * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n + * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor + * @param ADCx ADC instance + * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor) +{ + MODIFY_REG(ADCx->CALFACT, + ADC_CALFACT_CALFACT, + CalibrationFactor); +} +#else /** * @brief Set ADC calibration factor in the mode single-ended * or differential (for devices with differential mode available). @@ -2212,8 +2709,10 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED - * @arg @ref LL_ADC_DIFFERENTIAL_ENDED - * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED + * @arg @ref LL_ADC_DIFFERENTIAL_ENDED (1) + * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F * @retval None */ @@ -2223,7 +2722,27 @@ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t Sin SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); } +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/** + * @brief Get ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note Calibration factors are set by hardware after performing + * a calibration run using function @ref LL_ADC_StartCalibration(). + * @note For devices with differential mode available: + * Calibration of offset is specific to each of + * single-ended and differential modes + * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n + * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7F + */ +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); +} +#else /** * @brief Get ADC calibration factor in the mode single-ended * or differential (for devices with differential mode available). @@ -2248,7 +2767,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t /* containing other bits reserved for other purpose. */ return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); } - +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Set ADC resolution. * Refer to reference manual for alignments formats @@ -2268,7 +2787,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); +#endif } /** @@ -2285,7 +2808,11 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution */ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); +#endif } /** @@ -2305,7 +2832,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment); +#endif } /** @@ -2320,7 +2851,11 @@ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAli */ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); +#endif } /** @@ -2372,11 +2907,19 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * @param LowPowerMode This parameter can be one of the following values: * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT + * @arg @ref LL_ADC_LP_AUTOPOWEROFF (1) + * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (1) + * + * (1) On STM32WB serie, parameter available only on devices: STM32WB10xx, STM32WB15xx. * @retval None */ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode); +#endif } /** @@ -2424,14 +2967,159 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT + * @arg @ref LL_ADC_LP_AUTOPOWEROFF (1) + * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (1) + * + * (1) On STM32WB serie, parameter available only on devices: STM32WB10xx, STM32WB15xx. */ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF))); +#else return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); +#endif } -/** - * @brief Set ADC selected offset number 1, 2, 3 or 4. +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Set ADC trigger frequency mode. + * @note ADC trigger frequency mode must be set to low frequency when + * a duration is exceeded before ADC conversion start trigger event + * (between ADC enable and ADC conversion start trigger event + * or between two ADC conversion start trigger event). + * Duration value: Refer to device datasheet, parameter "tIdle". + * @note When ADC trigger frequency mode is set to low frequency, + * some rearm cycles are inserted before performing ADC conversion + * start, inducing a delay of 2 ADC clock cycles. + * @note Usage of ADC trigger frequency mode with ADC low power mode: + * - Low power mode auto wait: Only the first ADC conversion + * start trigger inserts the rearm delay. + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode + * @param ADCx ADC instance + * @param TriggerFrequencyMode This parameter can be one of the following values: + * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH + * @arg @ref LL_ADC_TRIGGER_FREQ_LOW + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); +} + +/** + * @brief Get ADC trigger frequency mode. + * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH + * @arg @ref LL_ADC_TRIGGER_FREQ_LOW + */ +__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); +} + +#endif +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Set sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this STM32 serie, sampling time scope is on ADC instance: + * Sampling time common to all channels, independently + * of channels mapped on ADC group regular or injected. + * (on some other STM32 families, sampling time is channel wise) + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 serie, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n + * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, uint32_t SamplingTime) +{ + MODIFY_REG(ADCx->SMPR, + ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK), + SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + +/** + * @brief Get sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this STM32 serie, sampling time scope is on ADC instance: + * Sampling time common to all channels, independently + * of channels mapped on ADC group regular or injected. + * (on some other STM32 families, sampling time is channel wise) + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 serie, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n + * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +{ + return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) + >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + +#endif + +#if defined(ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC offset" not available on ADC peripheral of this STM32WB device */ +#else +/** + * @brief Set ADC selected offset number 1, 2, 3 or 4. * @note This function set the 2 items of offset configuration: * - ADC channel to which the offset programmed will be applied * (independently of channel mapped on ADC group regular @@ -2449,7 +3137,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @note On STM32WB, some fast channels are available: fast analog inputs + * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n * OFR1 OFFSET1 LL_ADC_SetOffset\n @@ -2493,14 +3181,14 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, @@ -2523,7 +3211,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @note On STM32WB, some fast channels are available: fast analog inputs + * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n @@ -2559,7 +3247,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done @@ -2567,7 +3255,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -2593,7 +3281,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -2626,7 +3314,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, @@ -2652,11 +3340,12 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } +#endif /** * @} @@ -2676,6 +3365,10 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse * STM32 families having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_REG_SetTriggerEdge(). + * @note On devices STM32WB10xx, STM32WB15xx: ADC trigger frequency mode must be set + * in function of frequency of ADC group regular conversion trigger. + * Refer to description of function + * "LL_ADC_SetTriggerFrequencyMode()". * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 serie, setting of this feature is conditioned to @@ -2687,19 +3380,29 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. + * (2) On STM32WB serie, parameter available only devices: STM32WB10xx, STM32WB15xx. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource); +#endif } /** @@ -2719,22 +3422,42 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. + * (2) On STM32WB serie, parameter available only devices: STM32WB10xx, STM32WB15xx. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); +#if defined (ADC_SUPPORT_2_5_MSPS) + __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ + uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + + /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) + ); +#else + __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ @@ -2742,6 +3465,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL) | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN) ); +#endif } /** @@ -2757,7 +3481,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); +#else return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); +#endif } /** @@ -2777,7 +3505,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge); +#endif } /** @@ -2792,9 +3524,72 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); +#endif +} + +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Set ADC group regular sequencer configuration flexibility. + * @note On this STM32 serie, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" are + * available: + * - sequencer configured to fully configurable: + * sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerLength(). + * - sequencer configured to not fully configurable: + * sequencer length and each rank affectation to a channel + * are fixed by channel HW number. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerChannels(). + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable + * @param ADCx ADC instance + * @param Configurability This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_FIXED + * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability); +} + +/** + * @brief Get ADC group regular sequencer configuration flexibility. + * @note On this STM32 serie, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" are + * available: + * - sequencer configured to fully configurable: + * sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerLength(). + * - sequencer configured to not fully configurable: + * sequencer length and each rank affectation to a channel + * are fixed by channel HW number. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerChannels(). + * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_FIXED + * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD)); } +#endif /** * @brief Set ADC group regular sequencer length and scan direction. * @note Description of ADC group regular sequencer features: @@ -2822,13 +3617,30 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) * highest channel number). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerChannels()". + * To set scan direction differently, refer to function + * "LL_ADC_REG_SetSequencerScanDirection()". + * @note On devices STM32WB10xx, STM32WB15xx: after calling functions + * @ref LL_ADC_REG_SetSequencerLength() + * or @ref LL_ADC_REG_SetSequencerRanks(), + * it is mandatory to wait for the assertion of CCRDY flag + * using "LL_ADC_IsActiveFlag_CCRDY()". + * Otherwise, performing some actions (configuration update, + * ADC conversion start, ... ) will be ignored. + * Refer to reference manual for more details. * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ8 LL_ADC_REG_SetSequencerLength * @param ADCx ADC instance * @param SequencerNbRanks This parameter can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE @@ -2839,19 +3651,25 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) { +#if defined (ADC_SUPPORT_2_5_MSPS) + SET_BIT(ADCx->CHSELR, SequencerNbRanks); +#else MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); +#endif } /** @@ -2881,9 +3699,18 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * highest channel number). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerChannels()". + * To set scan direction differently, refer to function + * "LL_ADC_REG_SetSequencerScanDirection()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength + * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ8 LL_ADC_REG_GetSequencerLength * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE @@ -2894,20 +3721,80 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); + uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; + uint32_t RankIndex; + + /* Parse register for end of sequence identifier */ + for(RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex+=4U) + { + if((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex)) + { + SequencerLength = (ADC_CHSELR_SQ2 << RankIndex); + break; + } + } + + return SequencerLength; +#else return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); +#endif } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Set ADC group regular sequencer scan direction. + * @note On this STM32 serie, parameter relevant only is sequencer is set + * to mode not fully configurable, + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On some other STM32 families, this setting is not available and + * the default scan direction is forward. + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection + * @param ADCx ADC instance + * @param ScanDirection This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection); +} + +/** + * @brief Get ADC group regular sequencer scan direction. + * @note On some other STM32 families, this setting is not available and + * the default scan direction is forward. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); +} + +#endif /** * @brief Set ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected @@ -2926,18 +3813,24 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) * @param SeqDiscont This parameter can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont); +#endif } /** @@ -2950,17 +3843,23 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS (1) + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); +#endif } /** @@ -2979,6 +3878,14 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On devices STM32WB10xx, STM32WB15xx: after calling functions + * @ref LL_ADC_REG_SetSequencerLength() + * or @ref LL_ADC_REG_SetSequencerRanks(), + * it is mandatory to wait for the assertion of CCRDY flag + * using "LL_ADC_IsActiveFlag_CCRDY()". + * Otherwise, performing some actions (configuration update, + * ADC conversion start, ... ) will be ignored. + * Refer to reference manual for more details. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going @@ -3009,14 +3916,16 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_RANK_6 * @arg @ref LL_ADC_REG_RANK_7 * @arg @ref LL_ADC_REG_RANK_8 - * @arg @ref LL_ADC_REG_RANK_9 - * @arg @ref LL_ADC_REG_RANK_10 - * @arg @ref LL_ADC_REG_RANK_11 - * @arg @ref LL_ADC_REG_RANK_12 - * @arg @ref LL_ADC_REG_RANK_13 - * @arg @ref LL_ADC_REG_RANK_14 - * @arg @ref LL_ADC_REG_RANK_15 - * @arg @ref LL_ADC_REG_RANK_16 + * @arg @ref LL_ADC_REG_RANK_9 (1) + * @arg @ref LL_ADC_REG_RANK_10 (1) + * @arg @ref LL_ADC_REG_RANK_11 (1) + * @arg @ref LL_ADC_REG_RANK_12 (1) + * @arg @ref LL_ADC_REG_RANK_13 (1) + * @arg @ref LL_ADC_REG_RANK_14 (1) + * @arg @ref LL_ADC_REG_RANK_15 (1) + * @arg @ref LL_ADC_REG_RANK_16 (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (7) @@ -3041,21 +3950,31 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->CHSELR, + ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +#else /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +#endif } /** @@ -3104,14 +4023,16 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_REG_RANK_6 * @arg @ref LL_ADC_REG_RANK_7 * @arg @ref LL_ADC_REG_RANK_8 - * @arg @ref LL_ADC_REG_RANK_9 - * @arg @ref LL_ADC_REG_RANK_10 - * @arg @ref LL_ADC_REG_RANK_11 - * @arg @ref LL_ADC_REG_RANK_12 - * @arg @ref LL_ADC_REG_RANK_13 - * @arg @ref LL_ADC_REG_RANK_14 - * @arg @ref LL_ADC_REG_RANK_15 - * @arg @ref LL_ADC_REG_RANK_16 + * @arg @ref LL_ADC_REG_RANK_9 (1) + * @arg @ref LL_ADC_REG_RANK_10 (1) + * @arg @ref LL_ADC_REG_RANK_11 (1) + * @arg @ref LL_ADC_REG_RANK_12 (1) + * @arg @ref LL_ADC_REG_RANK_13 (1) + * @arg @ref LL_ADC_REG_RANK_14 (1) + * @arg @ref LL_ADC_REG_RANK_15 (1) + * @arg @ref LL_ADC_REG_RANK_16 (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (7) @@ -3136,7 +4057,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done @@ -3144,14 +4065,382 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t) ((READ_BIT(ADCx->CHSELR, + ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ); +#else + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); +#endif } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Set ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by overwriting the current sequencer + * configuration. + * @note On this STM32 serie, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs + * coming from GPIO pads (ADC_IN1..5). + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 (7) + * @arg @ref LL_ADC_CHANNEL_2 (7) + * @arg @ref LL_ADC_CHANNEL_3 (7) + * @arg @ref LL_ADC_CHANNEL_4 (7) + * @arg @ref LL_ADC_CHANNEL_5 (7) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Add channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by adding them to the current sequencer + * configuration. + * @note On this STM32 serie, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs + * coming from GPIO pads (ADC_IN1..5). + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 (7) + * @arg @ref LL_ADC_CHANNEL_2 (7) + * @arg @ref LL_ADC_CHANNEL_3 (7) + * @arg @ref LL_ADC_CHANNEL_4 (7) + * @arg @ref LL_ADC_CHANNEL_5 (7) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by removing them to the current sequencer + * configuration. + * @note On this STM32 serie, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs + * coming from GPIO pads (ADC_IN1..5). + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 (7) + * @arg @ref LL_ADC_CHANNEL_2 (7) + * @arg @ref LL_ADC_CHANNEL_3 (7) + * @arg @ref LL_ADC_CHANNEL_4 (7) + * @arg @ref LL_ADC_CHANNEL_5 (7) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels order reading into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * @note On this STM32 serie, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs + * coming from GPIO pads (ADC_IN1..5). +*/ +//TBC +/* + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be retrieved. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels + * @param ADCx ADC instance + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 (7) + * @arg @ref LL_ADC_CHANNEL_2 (7) + * @arg @ref LL_ADC_CHANNEL_3 (7) + * @arg @ref LL_ADC_CHANNEL_4 (7) + * @arg @ref LL_ADC_CHANNEL_5 (7) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) +{ + uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); + + return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18) + ); +} +#endif /** * @brief Set ADC continuous conversion mode on ADC group regular. * @note Description of ADC continuous conversion mode: @@ -3173,7 +4462,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ */ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous); +#endif } /** @@ -3190,7 +4483,11 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co */ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); +#endif } /** @@ -3228,7 +4525,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer); +#endif } /** @@ -3261,7 +4562,11 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATr */ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); +#endif } @@ -3287,7 +4592,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun); +#endif } /** @@ -3301,13 +4610,20 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) */ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); +#endif } /** * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected * @{ */ @@ -3372,11 +4688,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { - register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ @@ -3526,7 +4842,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On STM32WB, some fast channels are available: fast analog inputs + * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -3566,7 +4882,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval None */ @@ -3631,7 +4947,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n * (4) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done @@ -3776,7 +5092,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On STM32WB, some fast channels are available: fast analog inputs + * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -3834,7 +5150,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param Rank2_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 @@ -3860,7 +5176,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param Rank3_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 @@ -3886,7 +5202,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param Rank4_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 @@ -3912,7 +5228,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval None */ @@ -3931,7 +5247,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ - register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); + uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | @@ -3954,10 +5270,99 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * @} */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels * @{ */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 serie, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 (7) + * @arg @ref LL_ADC_CHANNEL_2 (7) + * @arg @ref LL_ADC_CHANNEL_3 (7) + * @arg @ref LL_ADC_CHANNEL_4 (7) + * @arg @ref LL_ADC_CHANNEL_5 (7) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->SMPR, + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS), + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK) + ); +} +#else /** * @brief Set sampling time of the selected ADC channel * Unit: ADC clock cycles. @@ -4028,32 +5433,118 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) +{ +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->SMPR, + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS), + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK) + ); +#else + /* Set bits with content of parameter "SamplingTime" with bits position */ + /* in register and register position depending on parameter "Channel". */ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), + SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); +#endif +} +#endif /* ADC_SUPPORT_2_5_MSPS */ + +#if defined (ADC_SUPPORT_2_5_MSPS) +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 serie, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 (7) + * @arg @ref LL_ADC_CHANNEL_2 (7) + * @arg @ref LL_ADC_CHANNEL_3 (7) + * @arg @ref LL_ADC_CHANNEL_4 (7) + * @arg @ref LL_ADC_CHANNEL_5 (7) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). - * @param SamplingTime This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 - * @retval None + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 */ -__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - /* Set bits with content of parameter "SamplingTime" with bits position */ - /* in register and register position depending on parameter "Channel". */ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + __IO uint32_t smpr = READ_REG(ADCx->SMPR); - MODIFY_REG(*preg, - ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), - SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); -} + /* Retrieve sampling time bit corresponding to the selected channel */ + /* and shift it to position 0. */ + uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) + >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL)); + /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ + return( (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) + | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2) ); +} +#else /** * @brief Get sampling time of the selected ADC channel * Unit: ADC clock cycles. @@ -4109,7 +5600,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @arg @ref LL_ADC_CHANNEL_VBAT * - * (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 @@ -4123,14 +5614,31 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); +#if defined (ADC_SUPPORT_2_5_MSPS) + __IO uint32_t smpr = READ_REG(ADCx->SMPR); + + /* Retrieve sampling time bit corresponding to the selected channel */ + /* and shift it to position 0. */ + uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) + >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL)); + + /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ + return( (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) + | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2) ); +#else + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) ); +#endif } +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC channel differential mode" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Set mode single-ended or differential input of the selected * ADC channel. @@ -4234,6 +5742,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} */ @@ -4290,90 +5799,100 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * @param AWDChannelGroup This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) - * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0) - * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) * * (0) On STM32WB, parameter available only on analog watchdog number: AWD1. + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) { +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Prevent unused argument(s) compilation warning */ + (void)(AWDy); + + MODIFY_REG(ADCx->CFGR1, + (LL_ADC_AWD1 & ADC_AWD_CR_ALL_CHANNEL_MASK), + AWDChannelGroup & LL_ADC_AWD1); +#else /* Set bits with content of parameter "AWDChannelGroup" with bits position */ /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), AWDChannelGroup & AWDy); +#endif } /** @@ -4425,85 +5944,117 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 (1) - * @arg @ref LL_ADC_AWD3 (1) + * @arg @ref LL_ADC_AWD2 (1)(2) + * @arg @ref LL_ADC_AWD3 (1)(2) * * (1) On this AWD number, monitored channel can be retrieved * if only 1 channel is programmed (or none or all channels). * This function cannot retrieve monitored channel if * multiple channels are programmed simultaneously * by bitfield. + * (2) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1) * * (0) On STM32WB, parameter available only on analog watchdog number: AWD1. + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Prevent unused argument(s) compilation warning */ + (void)(AWDy); + + uint32_t AnalogWDMonitChannels = (READ_BIT(ADCx->CFGR1, LL_ADC_AWD1) & LL_ADC_AWD1 & ADC_AWD_CR_ALL_CHANNEL_MASK); + + /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* (parameter value LL_ADC_AWD_DISABLE). */ + /* Else, the selected AWD is enabled and is monitoring a group of channels */ + /* or a single channel. */ + if(AnalogWDMonitChannels != 0UL) + { + if((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = (AnalogWDMonitChannels + & (~(ADC_CFGR1_AWD1CH)) + ); + } + else + { + /* AWD monitoring a single channel */ + AnalogWDMonitChannels = (AnalogWDMonitChannels + | (0x01UL << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos)) + ); + } + } + + return AnalogWDMonitChannels; +#else + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ @@ -4552,6 +6103,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint } return AnalogWDMonitChannels; +#endif } /** @@ -4600,8 +6152,10 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 + * @arg @ref LL_ADC_AWD2 (1) + * @arg @ref LL_ADC_AWD3 (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None @@ -4614,11 +6168,20 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Prevent unused argument(s) compilation warning */ + (void)(AWDy); + + MODIFY_REG(ADCx->TR1, + ADC_TR1_HT1 | ADC_TR1_LT1, + (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); +#else + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); +#endif } /** @@ -4667,8 +6230,10 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 + * @arg @ref LL_ADC_AWD2 (1) + * @arg @ref LL_ADC_AWD3 (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW @@ -4683,11 +6248,20 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Prevent unused argument(s) compilation warning */ + (void)(AWDy); + + MODIFY_REG(ADCx->TR1, + AWDThresholdsHighLow, + AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); +#else + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, AWDThresholdsHighLow, AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); +#endif } /** @@ -4710,8 +6284,10 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 + * @arg @ref LL_ADC_AWD2 (1) + * @arg @ref LL_ADC_AWD3 (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW @@ -4720,18 +6296,31 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Prevent unused argument(s) compilation warning */ + (void)(AWDy); + + return (uint32_t)(READ_BIT(ADCx->TR1, + (AWDThresholdsHighLow | ADC_TR1_LT1)) + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) + ); +#else + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) ); +#endif } /** * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */ +#else /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling * @{ */ @@ -4756,14 +6345,20 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ * @param OvsScope This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED - * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED - * @arg @ref LL_ADC_OVS_GRP_INJECTED - * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED + * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED (1) + * @arg @ref LL_ADC_OVS_GRP_INJECTED (1) + * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval None */ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); +#else MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); +#endif } /** @@ -4782,13 +6377,19 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED - * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED - * @arg @ref LL_ADC_OVS_GRP_INJECTED - * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED + * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED (1) + * @arg @ref LL_ADC_OVS_GRP_INJECTED (1) + * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); +#endif } /** @@ -4815,7 +6416,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) { +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); +#else MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont); +#endif } /** @@ -4834,7 +6439,11 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) { +#if defined (ADC_SUPPORT_2_5_MSPS) + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); +#else return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); +#endif } /** @@ -4921,10 +6530,14 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) * @} */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC deep power down" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Put ADC instance in deep power down state. * @note In case of ADC calibration necessary: When ADC is in deep-power-down @@ -4979,6 +6592,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Enable ADC instance internal voltage regulator. @@ -5100,6 +6714,37 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } +#if defined (ADC_SUPPORT_2_5_MSPS) +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @note On this STM32 serie, a minimum number of ADC clock cycles + * are required between ADC end of calibration and ADC enable. + * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. + * @note For devices with differential mode available: + * Calibration of offset is specific to each of + * single-ended and differential modes + * (calibration run must be performed for each of these + * differential modes, if used afterwards and if the application + * requires their calibration). + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADCAL LL_ADC_StartCalibration\n + * CR ADCALDIF LL_ADC_StartCalibration + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADCAL); +} +#else /** * @brief Start ADC calibration in the mode single-ended * or differential (for devices with differential mode available). @@ -5132,6 +6777,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleD ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK)); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Get ADC calibration state. @@ -5300,6 +6946,9 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected * @{ */ @@ -5393,7 +7042,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -5420,7 +7069,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -5447,7 +7096,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -5474,7 +7123,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -5501,7 +7150,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -5512,6 +7161,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32 * @} */ +#endif /* ADC_SUPPORT_2_5_MSPS */ /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management * @{ */ @@ -5530,6 +7180,23 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Get flag ADC channel configuration ready. + * @note Duration of ADC channel configuration ready: CCRDY handshake + * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration + * has been changed. + * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); +} + +#else +#endif /** * @brief Get flag ADC group regular end of unitary conversion. * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC @@ -5574,6 +7241,9 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Get flag ADC group injected end of unitary conversion. * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC @@ -5607,6 +7277,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Get flag ADC analog watchdog 1 flag * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 @@ -5640,6 +7311,19 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Get flag ADC end of calibration. + * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL); +} + +#endif /** * @brief Clear flag ADC ready. * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC @@ -5654,6 +7338,20 @@ __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Clear flag ADC channel configuration ready. + * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY); +} + +#else +#endif /** * @brief Clear flag ADC group regular end of unitary conversion. * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC @@ -5698,6 +7396,9 @@ __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Clear flag ADC group injected end of unitary conversion. * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC @@ -5731,6 +7432,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Clear flag ADC analog watchdog 1. * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 @@ -5764,6 +7466,19 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Clear flag ADC end of calibration. + * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL); +} + +#endif /** * @} */ @@ -5783,6 +7498,20 @@ __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Enable interruption ADC channel configuration ready. + * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY); +} + +#else +#endif /** * @brief Enable interruption ADC group regular end of unitary conversion. * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC @@ -5827,6 +7556,9 @@ __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Enable interruption ADC group injected end of unitary conversion. * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC @@ -5860,6 +7592,7 @@ __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Enable interruption ADC analog watchdog 1. * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 @@ -5893,6 +7626,19 @@ __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Enable interruption ADC end of calibration. + * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL); +} + +#endif /** * @brief Disable interruption ADC ready. * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY @@ -5904,6 +7650,20 @@ __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Disable interruption ADC channel configuration ready. + * @rmtoll IER ADRDYIE LL_ADC_DisableIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY); +} + +#else +#endif /** * @brief Disable interruption ADC group regular end of unitary conversion. * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC @@ -5948,6 +7708,9 @@ __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Disable interruption ADC group regular end of unitary conversion. * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC @@ -5981,6 +7744,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Disable interruption ADC analog watchdog 1. * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 @@ -6014,6 +7778,19 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Disable interruption ADC end of calibration. + * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL); +} + +#endif /** * @brief Get state of interruption ADC ready * (0: interrupt disabled, 1: interrupt enabled). @@ -6026,6 +7803,20 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Get state of interruption ADC channel configuration ready. + * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); +} + +#else +#endif /** * @brief Get state of interruption ADC group regular end of unitary conversion * (0: interrupt disabled, 1: interrupt enabled). @@ -6074,6 +7865,9 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Get state of interruption ADC group injected end of unitary conversion * (0: interrupt disabled, 1: interrupt enabled). @@ -6110,6 +7904,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Get state of interruption ADC analog watchdog 1 * (0: interrupt disabled, 1: interrupt enabled). @@ -6146,6 +7941,20 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } +#if defined(ADC_SUPPORT_2_5_MSPS) +/** + * @brief Get state of interruption ADC end of calibration + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); +} + +#endif /** * @} */ @@ -6172,10 +7981,14 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /* Initialization of some features of ADC instance and ADC group injected */ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); +#endif /** * @} */ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h index 825c83e..2463c08 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h @@ -81,7 +81,9 @@ extern "C" { #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#if defined(TSC) #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN +#endif /** * @} */ @@ -99,7 +101,9 @@ extern "C" { #endif #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN +#if defined(ADC_SUPPORT_5_MSPS) #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN +#endif #if defined(AES1) #define LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN #endif @@ -172,11 +176,18 @@ extern "C" { */ #define LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU) +#if defined(ADC_SUPPORT_2_5_MSPS) +#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2ENR_ADCEN +#endif #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(TIM16) #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#endif +#if defined(TIM17) #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#endif #if defined(SAI1) #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN #endif @@ -204,7 +215,9 @@ extern "C" { #define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN #define LL_C2_AHB1_GRP1_PERIPH_SRAM1 RCC_C2AHB1ENR_SRAM1EN #define LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN +#if defined(TSC) #define LL_C2_AHB1_GRP1_PERIPH_TSC RCC_C2AHB1ENR_TSCEN +#endif /** * @} */ @@ -221,7 +234,9 @@ extern "C" { #endif #define LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN #define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN +#if defined(ADC_SUPPORT_5_MSPS) #define LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN +#endif #if defined(AES1) #define LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN #endif @@ -283,11 +298,18 @@ extern "C" { /** @defgroup BUS_LL_EC_C2_APB2_GRP1_PERIPH C2 APB2 GRP1 PERIPH * @{ */ +#if defined(ADC_SUPPORT_2_5_MSPS) +#define LL_C2_APB2_GRP1_PERIPH_ADC RCC_C2APB2ENR_ADCEN +#endif #define LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN #define LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN #define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN +#if defined(TIM16) #define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN +#endif +#if defined(TIM17) #define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN +#endif #if defined(SAI1) #define LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN #endif @@ -300,7 +322,9 @@ extern "C" { * @{ */ #define LL_C2_APB3_GRP1_PERIPH_BLE RCC_C2APB3ENR_BLEEN +#if defined(RCC_802_SUPPORT) #define LL_C2_APB3_GRP1_PERIPH_802 RCC_C2APB3ENR_802EN +#endif /** * @} */ @@ -331,12 +355,13 @@ extern "C" { * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -355,12 +380,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -375,12 +401,13 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->AHB1ENR, Periphs); @@ -396,12 +423,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->AHB1RSTR, Periphs); @@ -417,12 +445,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->AHB1RSTR, Periphs); @@ -438,13 +467,14 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -464,13 +494,14 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->AHB1SMENR, Periphs); @@ -498,13 +529,14 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -528,13 +560,14 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -554,13 +587,14 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->AHB2ENR, Periphs); @@ -581,13 +615,14 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->AHB2RSTR, Periphs); @@ -608,13 +643,14 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->AHB2RSTR, Periphs); @@ -634,13 +670,14 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -664,13 +701,14 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->AHB2SMENR, Periphs); @@ -694,15 +732,16 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) * AHB3ENR IPCCEN LL_AHB3_GRP1_EnableClock\n * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*) * @arg @ref LL_AHB3_GRP1_PERIPH_PKA * @arg @ref LL_AHB3_GRP1_PERIPH_AES2 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -722,15 +761,16 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) * AHB3ENR IPCCEN LL_AHB3_GRP1_IsEnabledClock\n * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*) * @arg @ref LL_AHB3_GRP1_PERIPH_PKA * @arg @ref LL_AHB3_GRP1_PERIPH_AES2 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -746,15 +786,16 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) * AHB3ENR IPCCEN LL_AHB3_GRP1_DisableClock\n * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*) * @arg @ref LL_AHB3_GRP1_PERIPH_PKA * @arg @ref LL_AHB3_GRP1_PERIPH_AES2 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->AHB3ENR, Periphs); @@ -771,15 +812,16 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) * AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*) * @arg @ref LL_AHB3_GRP1_PERIPH_PKA * @arg @ref LL_AHB3_GRP1_PERIPH_AES2 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->AHB3RSTR, Periphs); @@ -796,15 +838,16 @@ __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) * AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*) * @arg @ref LL_AHB3_GRP1_PERIPH_PKA * @arg @ref LL_AHB3_GRP1_PERIPH_AES2 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->AHB3RSTR, Periphs); @@ -819,14 +862,15 @@ __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_EnableClockSleep\n * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*) * @arg @ref LL_AHB3_GRP1_PERIPH_PKA * @arg @ref LL_AHB3_GRP1_PERIPH_AES2 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2 + * @note (*) Not supported by all the devices * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -845,14 +889,15 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_DisableClockSleep\n * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*) * @arg @ref LL_AHB3_GRP1_PERIPH_PKA * @arg @ref LL_AHB3_GRP1_PERIPH_AES2 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->AHB3SMENR, Periphs); @@ -880,17 +925,18 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -905,10 +951,11 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -932,17 +979,18 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -953,10 +1001,11 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -975,17 +1024,18 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_ (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->APB1ENR1, Periphs); @@ -996,10 +1046,11 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->APB1ENR2, Periphs); @@ -1018,15 +1069,16 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_LCD - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB1RSTR1, Periphs); @@ -1038,10 +1090,11 @@ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB1RSTR2, Periphs); @@ -1060,15 +1113,16 @@ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_LCD - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB1RSTR1, Periphs); @@ -1080,10 +1134,11 @@ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB1RSTR2, Periphs); @@ -1103,17 +1158,18 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1128,10 +1184,11 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockSleep\n * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1155,17 +1212,18 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->APB1SMENR1, Periphs); @@ -1176,10 +1234,11 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockSleep\n * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->APB1SMENR2, Periphs); @@ -1195,21 +1254,24 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) /** * @brief Enable APB2 peripherals clock. - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1221,21 +1283,24 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if APB2 peripheral clock is enabled or not - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -1243,21 +1308,24 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable APB2 peripherals clock. - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->APB2ENR, Periphs); @@ -1265,7 +1333,8 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) /** * @brief Force APB2 peripherals reset. - * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n @@ -1273,14 +1342,16 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB2RSTR, Periphs); @@ -1288,7 +1359,8 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) /** * @brief Release APB2 peripherals reset. - * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n @@ -1296,14 +1368,16 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB2RSTR, Periphs); @@ -1311,21 +1385,24 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. - * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep\n + * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep\n * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockSleep\n * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1337,21 +1414,24 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) /** * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. - * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep\n + * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep\n * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockSleep\n * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->APB2SMENR, Periphs); @@ -1371,7 +1451,7 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_RF * @retval None -*/ + */ __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB3RSTR, Periphs); @@ -1383,7 +1463,7 @@ __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_RF * @retval None -*/ + */ __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB3RSTR, Periphs); @@ -1406,13 +1486,14 @@ __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) { @@ -1433,13 +1514,14 @@ __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { @@ -1456,13 +1538,14 @@ __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) { @@ -1479,13 +1562,14 @@ __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) * C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) { @@ -1506,13 +1590,14 @@ __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) * C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) { @@ -1541,13 +1626,14 @@ __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1571,13 +1657,14 @@ __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->C2AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -1597,13 +1684,14 @@ __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->C2AHB2ENR, Periphs); @@ -1623,13 +1711,14 @@ __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1653,13 +1742,14 @@ __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*) * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC - * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*) + * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->C2AHB2SMENR, Periphs); @@ -1689,7 +1779,7 @@ __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1715,7 +1805,7 @@ __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->C2AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -1737,7 +1827,7 @@ __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->C2AHB3ENR, Periphs); @@ -1757,7 +1847,7 @@ __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1781,7 +1871,7 @@ __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH * @retval None -*/ + */ __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->C2AHB3SMENR, Periphs); @@ -1808,16 +1898,17 @@ __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB - * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1832,10 +1923,11 @@ __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_EnableClock\n * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_EnableClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1858,16 +1950,17 @@ __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB - * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->C2APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -1878,10 +1971,11 @@ __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_IsEnabledClock\n * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->C2APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -1900,16 +1994,17 @@ __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB - * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->C2APB1ENR1, Periphs); @@ -1920,10 +2015,11 @@ __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_DisableClock\n * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_DisableClock * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->C2APB1ENR2, Periphs); @@ -1942,16 +2038,17 @@ __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB - * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1966,10 +2063,11 @@ __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_EnableClockSleep\n * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1992,16 +2090,17 @@ __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD + * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB - * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB + * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->C2APB1SMENR1, Periphs); @@ -2012,10 +2111,11 @@ __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_DisableClockSleep\n * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*) * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2 + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->C2APB1SMENR2, Periphs); @@ -2031,21 +2131,24 @@ __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) /** * @brief Enable C2APB2 peripherals clock. - * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n + * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_EnableClock\n + * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n * C2APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -2057,21 +2160,24 @@ __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if C2APB2 peripheral clock is enabled or not - * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_IsEnabledClock\n + * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n * C2APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->C2APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -2079,21 +2185,24 @@ __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable C2APB2 peripherals clock. - * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n + * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_DisableClock\n + * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n * C2APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->C2APB2ENR, Periphs); @@ -2101,21 +2210,24 @@ __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) /** * @brief Enable C2APB2 peripherals clock during Low Power (Sleep) mode. - * @rmtoll C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n + * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_EnableClockSleep\n + * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_EnableClockSleep\n * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_EnableClockSleep\n * C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_EnableClockSleep * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -2127,21 +2239,24 @@ __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) /** * @brief Disable C2APB2 peripherals clock during Low Power (Sleep) mode. - * @rmtoll C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n + * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_DisableClockSleep\n + * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_DisableClockSleep\n * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_DisableClockSleep\n * C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_DisableClockSleep * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*) * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->C2APB2SMENR, Periphs); @@ -2158,12 +2273,13 @@ __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) /** * @brief Enable C2APB3 peripherals clock. * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_EnableClock\n - * C2APB3ENR 802EN LL_C2_APB3_GRP1_EnableClock + * C2APB3ENR 802EN LL_C2_APB3_GRP1_EnableClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE - * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 + * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -2176,12 +2292,13 @@ __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if C2APB3 peripheral clock is enabled or not * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_IsEnabledClock\n - * C2APB3ENR 802EN LL_C2_APB3_GRP1_IsEnabledClock + * C2APB3ENR 802EN LL_C2_APB3_GRP1_IsEnabledClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE - * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 + * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*) + * @note (*) Not supported by all the devices * @retval uint32_t -*/ + */ __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->C2APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL); @@ -2190,12 +2307,13 @@ __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable C2APB3 peripherals clock. * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_DisableClock\n - * C2APB3ENR 802EN LL_C2_APB3_GRP1_DisableClock + * C2APB3ENR 802EN LL_C2_APB3_GRP1_DisableClock (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE - * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 + * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->C2APB3ENR, Periphs); @@ -2204,12 +2322,13 @@ __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) /** * @brief Enable C2APB3 peripherals clock during Low Power (Sleep) mode. * @rmtoll C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_EnableClockSleep\n - * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_EnableClockSleep + * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_EnableClockSleep (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE - * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 + * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -2222,12 +2341,13 @@ __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) /** * @brief Disable C2APB3 peripherals clock during Low Power (Sleep) mode. * @rmtoll C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_DisableClockSleep\n - * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_DisableClockSleep + * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_DisableClockSleep (*) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE - * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 + * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*) + * @note (*) Not supported by all the devices * @retval None -*/ + */ __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) { CLEAR_BIT(RCC->C2APB3SMENR, Periphs); diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h index 4348e8c..9785ee3 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h @@ -117,8 +117,10 @@ typedef struct /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ +#if defined(COMP2) #define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators 1 and 2 are independent */ #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +#endif /* COMP2 */ /** * @} */ @@ -136,7 +138,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection * @{ */ -#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ #define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ /** @@ -151,7 +153,7 @@ typedef struct #define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */ #define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */ #define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA9 for COMP1, pin PB3 for COMP2) */ -#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */ +#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */ #define LL_COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */ #define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */ #define LL_COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */ @@ -287,6 +289,7 @@ typedef struct * @{ */ +#if defined(COMP2) /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances * @{ */ @@ -304,7 +307,7 @@ typedef struct */ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode) { - /* Note: On this STM32 serie, window mode can be set only */ + /* Note: On this STM32 series, window mode can be set only */ /* from COMP instance: COMP2. */ MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode); } @@ -328,6 +331,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy * @} */ +#endif /* COMP2 */ /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes * @{ */ @@ -374,7 +378,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * @note In case of comparator input selected to be connected to IO: * GPIO pins are specific to each comparator instance. * Refer to description of parameters or to reference manual. - * @note On this STM32 serie, scaler bridge is configurable: + * @note On this STM32 series, scaler bridge is configurable: * to optimize power consumption, this function enables the * voltage scaler bridge only when required * (when selecting comparator input based on VrefInt: VrefInt or @@ -402,7 +406,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_MINUS_IO4 * @arg @ref LL_COMP_INPUT_MINUS_IO5 * @param InputPlus This parameter can be one of the following values: - * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO1 (*) * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_IO3 (*) * @@ -424,7 +428,7 @@ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMin * @rmtoll CSR INPSEL LL_COMP_SetInputPlus * @param COMPx Comparator instance * @param InputPlus This parameter can be one of the following values: - * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO1 (*) * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_IO3 (*) * @@ -444,7 +448,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @rmtoll CSR INPSEL LL_COMP_GetInputPlus * @param COMPx Comparator instance * @retval Returned value can be one of the following values: - * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO1 (*) * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_IO3 (*) * @@ -460,7 +464,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) * @note In case of comparator input selected to be connected to IO: * GPIO pins are specific to each comparator instance. * Refer to description of parameters or to reference manual. - * @note On this STM32 serie, scaler bridge is configurable: + * @note On this STM32 series, scaler bridge is configurable: * to optimize power consumption, this function enables the * voltage scaler bridge only when required * (when selecting comparator input based on VrefInt: VrefInt or diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dma.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dma.h index f22c6dc..ddb5847 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dma.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dma.h @@ -64,9 +64,7 @@ extern "C" { /** * @brief Helper macro to convert DMA Instance and index into DMAMUX channel * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. -#if defined (DMA2) - * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. -#endif + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @param __DMA_INSTANCE__ DMAx * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7 * @retval Pointer to the DMA channel @@ -961,7 +959,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe /** * @brief Configure the Source and Destination addresses. * @note This API must not be called when the DMA channel is enabled. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @note Each peripheral using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n * CMAR MA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance @@ -1169,9 +1167,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha /** * @brief Set DMA request for DMA Channels on DMAMUX Channel x. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. -#if defined(DMA2) - * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. -#endif + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1234,9 +1230,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel /** * @brief Get DMA request for DMA Channels on DMAMUX Channel x. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. -#if defined(DMA2) - * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. -#endif + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -2108,7 +2102,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Chann /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions * @{ */ - ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dmamux.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dmamux.h index 3eacfd6..6e68522 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dmamux.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dmamux.h @@ -78,7 +78,7 @@ extern "C" { #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ #define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ #define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ -#endif +#endif /* DMA2 */ #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ @@ -106,7 +106,7 @@ extern "C" { #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ #define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ #define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ -#endif +#endif /* DMA2 */ #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ @@ -342,9 +342,7 @@ extern "C" { /** * @brief Set DMAMUX request ID for DMAMUX Channel x. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. -#if defined(DMA2) - * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. -#endif + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -355,7 +353,8 @@ extern "C" { * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -363,7 +362,6 @@ extern "C" { * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @param Request This parameter can be one of the following values: * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 @@ -408,7 +406,7 @@ extern "C" { * @arg @ref LL_DMAMUX_REQ_AES2_OUT * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef* DMAMUXx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -417,9 +415,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef* DMAMUXx, uin /** * @brief Get DMAMUX request ID for DMAMUX Channel x. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. -#if defined(DMA2) - * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. -#endif + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -430,6 +426,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef* DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -488,6 +486,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, /** * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -498,6 +498,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -516,6 +518,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, /** * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -526,6 +530,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -543,6 +549,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM /** * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -553,6 +561,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -575,6 +585,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, /** * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -585,7 +597,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -593,7 +606,6 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval Returned value can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_NO_EVENT * @arg @ref LL_DMAMUX_SYNC_POL_RISING @@ -608,6 +620,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU /** * @brief Enable the Event Generation on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -618,7 +632,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -626,7 +641,6 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -637,6 +651,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA /** * @brief Disable the Event Generation on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -647,7 +663,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -655,7 +672,6 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -666,6 +682,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM /** * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -676,7 +694,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -684,17 +703,18 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); - return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); } /** * @brief Enable the synchronization mode. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SE LL_DMAMUX_EnableSync * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -705,7 +725,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -713,7 +734,6 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -724,6 +744,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 /** * @brief Disable the synchronization mode. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SE LL_DMAMUX_DisableSync * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -734,7 +756,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -742,7 +765,6 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -753,6 +775,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint /** * @brief Check if the synchronization mode is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -763,7 +787,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -771,17 +796,18 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); - return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); } /** * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -792,7 +818,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -800,7 +827,6 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @param SyncID This parameter can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 @@ -832,6 +858,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 /** * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -842,7 +870,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -850,7 +879,6 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval Returned value can be one of the following values: * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 @@ -927,7 +955,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); } /** @@ -1176,6 +1204,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); } +#if defined(DMAMUX1_Channel7) /** * @brief Get Synchronization Event Overrun Flag Channel 7. * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 @@ -1188,6 +1217,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); } +#endif +#if defined(DMAMUX1_Channel8) /** * @brief Get Synchronization Event Overrun Flag Channel 8. * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 @@ -1200,6 +1231,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); } +#endif +#if defined(DMAMUX1_Channel9) /** * @brief Get Synchronization Event Overrun Flag Channel 9. * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 @@ -1212,6 +1245,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); } +#endif +#if defined(DMAMUX1_Channel10) /** * @brief Get Synchronization Event Overrun Flag Channel 10. * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 @@ -1224,6 +1259,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); } +#endif +#if defined(DMAMUX1_Channel11) /** * @brief Get Synchronization Event Overrun Flag Channel 11. * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 @@ -1236,6 +1273,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); } +#endif +#if defined(DMAMUX1_Channel12) /** * @brief Get Synchronization Event Overrun Flag Channel 12. * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 @@ -1248,6 +1287,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); } +#endif +#if defined(DMAMUX1_Channel13) /** * @brief Get Synchronization Event Overrun Flag Channel 13. * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 @@ -1260,6 +1301,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); } +#endif /** * @brief Get Request Generator 0 Trigger Event Overrun Flag. * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 @@ -1392,6 +1434,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); } +#if defined(DMAMUX1_Channel7) /** * @brief Clear Synchronization Event Overrun Flag Channel 7. * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 @@ -1404,6 +1447,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); } +#endif +#if defined(DMAMUX1_Channel8) /** * @brief Clear Synchronization Event Overrun Flag Channel 8. * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 @@ -1416,6 +1461,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); } +#endif +#if defined(DMAMUX1_Channel9) /** * @brief Clear Synchronization Event Overrun Flag Channel 9. * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 @@ -1428,6 +1475,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); } +#endif +#if defined(DMAMUX1_Channel10) /** * @brief Clear Synchronization Event Overrun Flag Channel 10. * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 @@ -1440,6 +1489,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); } +#endif +#if defined(DMAMUX1_Channel11) /** * @brief Clear Synchronization Event Overrun Flag Channel 11. * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 @@ -1452,6 +1503,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); } +#endif +#if defined(DMAMUX1_Channel12) /** * @brief Clear Synchronization Event Overrun Flag Channel 12. * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 @@ -1464,6 +1517,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); } +#endif +#if defined(DMAMUX1_Channel13) /** * @brief Clear Synchronization Event Overrun Flag Channel 13. * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 @@ -1476,6 +1531,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); } +#endif /** * @brief Clear Request Generator 0 Trigger Event Overrun Flag. * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 @@ -1534,6 +1590,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) /** * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -1544,7 +1602,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -1552,7 +1611,6 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -1563,6 +1621,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint /** * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -1573,7 +1633,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -1581,7 +1642,6 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval None */ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) @@ -1592,6 +1652,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin /** * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****). * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO * @param DMAMUXx DMAMUXx Instance * @param Channel This parameter can be one of the following values: @@ -1602,7 +1664,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_4 * @arg @ref LL_DMAMUX_CHANNEL_5 * @arg @ref LL_DMAMUX_CHANNEL_6 -#if defined(DMA2) + * + * @arg All the next values are only available on chip which support DMA2: * @arg @ref LL_DMAMUX_CHANNEL_7 * @arg @ref LL_DMAMUX_CHANNEL_8 * @arg @ref LL_DMAMUX_CHANNEL_9 @@ -1610,13 +1673,12 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_11 * @arg @ref LL_DMAMUX_CHANNEL_12 * @arg @ref LL_DMAMUX_CHANNEL_13 -#endif * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); - return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL); } /** @@ -1667,7 +1729,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL); + return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); } /** diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h index 4f55490..25304cf 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h @@ -107,8 +107,10 @@ typedef struct #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ #define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ -#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx #define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#endif +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ #endif #define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ @@ -116,13 +118,15 @@ typedef struct #define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ #endif #define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ -#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx #define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#endif +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ #endif #define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ #define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ -#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx #define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ #endif @@ -161,19 +165,27 @@ typedef struct #endif #define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ #define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx) || defined (STM32WB35xx) || defined (STM32WB30xx) #define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ +#endif #define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ + #if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \ LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \ LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_43 | \ LL_EXTI_LINE_44 | LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | \ - LL_EXTI_LINE_48) /*!< All Extended line not reserved*/ -#else + LL_EXTI_LINE_48) /*!< All Extended line not reserved*/ +#elif defined (STM32WB50xx) || defined (STM32WB35xx) || defined (STM32WB30xx) #define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \ LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \ LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_44 | \ LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | LL_EXTI_LINE_48) /*!< All Extended line not reserved*/ +#else +#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \ + LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \ + LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_44 | \ + LL_EXTI_LINE_45 | LL_EXTI_LINE_48) /*!< All Extended line not reserved*/ #endif @@ -361,7 +373,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 - * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_46 (*) * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices @@ -387,7 +399,7 @@ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 - * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_46 (*) * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices @@ -499,7 +511,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 - * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_46 (*) * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices @@ -525,7 +537,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 - * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_46 (*) * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices @@ -637,7 +649,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 - * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_46 (*) * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices @@ -663,7 +675,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_43 (*) * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_45 - * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_46 (*) * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_gpio.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_gpio.h index 4e3b049..18b8f55 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_gpio.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_gpio.h @@ -948,7 +948,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas */ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); } /** diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_hsem.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_hsem.h index 997306f..711925d 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_hsem.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_hsem.h @@ -575,6 +575,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t { return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } + /** * @} */ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h index 6f33203..29160c3 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h @@ -67,38 +67,38 @@ extern "C" { typedef struct { uint32_t PeripheralMode; /*!< Specifies the peripheral mode. - This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and - the helper macro @ref __LL_I2C_CONVERT_TIMINGS() + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. - This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. - This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). - This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ } LL_I2C_InitTypeDef; @@ -578,7 +578,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) { @@ -664,7 +664,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) /** * @brief Enable Wakeup from STOP. - * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @note This bit can only be programmed when Digital Filter is disabled. * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop @@ -678,7 +678,7 @@ __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Disable Wakeup from STOP. - * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop * @param I2Cx I2C Instance. @@ -691,7 +691,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Check if Wakeup from STOP is enabled or disabled. - * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop * @param I2Cx I2C Instance. @@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) /** * @brief Configure peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n * CR1 SMBDEN LL_I2C_SetMode @@ -960,7 +960,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) /** * @brief Get peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n * CR1 SMBDEN LL_I2C_GetMode @@ -978,7 +978,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -996,7 +996,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -1014,7 +1014,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert * @param I2Cx I2C Instance. @@ -1027,7 +1027,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC * @param I2Cx I2C Instance. @@ -1040,7 +1040,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC * @param I2Cx I2C Instance. @@ -1053,7 +1053,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC * @param I2Cx I2C Instance. @@ -1066,7 +1066,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n @@ -1089,7 +1089,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA @@ -1104,7 +1104,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA * @param I2Cx I2C Instance. @@ -1117,7 +1117,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode @@ -1134,7 +1134,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode * @param I2Cx I2C Instance. @@ -1149,7 +1149,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB @@ -1163,8 +1163,8 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout } /** - * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB * @param I2Cx I2C Instance. @@ -1177,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout @@ -1195,7 +1195,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock /** * @brief Disable the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout @@ -1213,7 +1213,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout @@ -1443,7 +1443,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) /** * @brief Enable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1463,7 +1463,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) /** * @brief Disable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1645,7 +1645,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1660,7 +1660,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1675,7 +1675,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1782,7 +1782,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR * @param I2Cx I2C Instance. @@ -1795,7 +1795,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1808,7 +1808,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -2123,7 +2123,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. * This bit has no effect when RELOAD bit is set. @@ -2139,7 +2139,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare * @param I2Cx I2C Instance. @@ -2152,7 +2152,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll PECR PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h index fdc820b..b502fa0 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h @@ -268,26 +268,36 @@ typedef struct /** * @} */ +#if defined(LPTIM_OR_OR) /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source * @{ */ #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */ +#if defined(COMP1) #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */ +#endif +#if defined(COMP2) #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */ #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */ +#endif /** * @} */ +#endif /* LPTIM_OR_OR */ +#if defined(LPTIM_OR_OR) /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source * @{ */ #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */ +#if defined(COMP2) #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */ +#endif /** * @} */ +#endif /* LPTIM_OR_OR */ /** * @} @@ -687,6 +697,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } +#if defined(LPTIM_OR_OR) /** * @brief Set LPTIM input 1 source (default GPIO). @@ -695,14 +706,17 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) * @param Src This parameter can be one of the following values: * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1 - * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2 - * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2 + * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2 (*) + * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (*) + * (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) { MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src); } +#endif /* LPTIM_OR_OR */ +#if defined(LPTIM_OR_OR) /** * @brief Set LPTIM input 2 source (default GPIO). @@ -717,6 +731,7 @@ __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) { MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src); } +#endif /* LPTIM_OR_OR */ /** * @} diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lpuart.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lpuart.h index c141442..c1bd9a4 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lpuart.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lpuart.h @@ -1372,9 +1372,9 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri */ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) { - register uint32_t lpuartdiv; - register uint32_t brrresult; - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; @@ -2482,7 +2482,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUAR */ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) { diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h index d59f5a4..6b36cad 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h @@ -90,10 +90,12 @@ extern "C" { #endif #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 #define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF -#define LL_PWR_SCR_C802AF PWR_SCR_C802AF #define LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF #define LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF +#if defined(PWR_CR3_E802A) +#define LL_PWR_SCR_C802AF PWR_SCR_C802AF #define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF +#endif #define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF #if defined(PWR_CR5_SMPSEN) #define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF @@ -145,9 +147,12 @@ extern "C" { /* Radio (BLE or 802.15.4) flags */ #define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */ -#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */ + #define LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */ +#if defined(PWR_CR3_E802A) +#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */ #define LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */ +#endif #define LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */ #define LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */ @@ -179,7 +184,9 @@ extern "C" { */ #define LL_PWR_MODE_STOP0 (0x000000000U) #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0) +#if defined(PWR_SUPPORT_STOP2) #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1) +#endif #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2) /** @@ -521,9 +528,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) * @param LowPowerMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 - * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STOP2 (*) * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) @@ -537,9 +546,11 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 - * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STOP2 (*) * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx */ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) { @@ -557,7 +568,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) __STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode) { /* Unlock bit FPDR */ - WRITE_REG(PWR->CR1, 0x0000C1B0U); + WRITE_REG(PWR->CR1, 0x0000C1B0UL); /* Update bit FPDR */ MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode); @@ -640,7 +651,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) @@ -656,7 +667,7 @@ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) @@ -672,7 +683,7 @@ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) @@ -808,7 +819,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) } /** - * @brief Enable SRAM2 content retention in Standby mode + * @brief Enable SRAM2a content retention in Standby mode + * @note On devices STM32WB15xx, STM32WB10xx, retention is extended + * to SRAM1, SRAM2a and SRAM2b. * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention * @retval None */ @@ -818,7 +831,9 @@ __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) } /** - * @brief Disable SRAM2 content retention in Standby mode + * @brief Disable SRAM2a content retention in Standby mode + * @note On devices STM32WB15xx, STM32WB10xx, retention is extended + * to SRAM1, SRAM2a and SRAM2b. * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention * @retval None */ @@ -829,6 +844,8 @@ __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) /** * @brief Check if SRAM2 content retention in Standby mode is enabled + * @note On devices STM32WB15xx, STM32WB10xx, retention is extended + * to SRAM1, SRAM2a and SRAM2b. * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention * @retval State of bit (1 or 0). */ @@ -851,7 +868,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) @@ -873,7 +890,7 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) @@ -895,7 +912,7 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) @@ -972,7 +989,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) @@ -994,7 +1011,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) @@ -1016,7 +1033,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) @@ -1323,7 +1340,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetBORConfig(void) * * (1) SMPS operating mode step down or open depends on system low-power mode: * - step down mode if system low power mode is run, LP run or stop0, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown * @retval None */ __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode) @@ -1345,7 +1362,7 @@ __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode) * * (1) SMPS operating mode step down or open depends on system low-power mode: * - step down mode if system low power mode is run, LP run or stop0, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown */ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) { @@ -1353,7 +1370,7 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) /* for all SMPS operating mode functions: */ /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */ /* and "LL_PWR_SMPS_GetEffectiveMode()". */ - register uint32_t OperatingMode = (READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) >> (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos)); + uint32_t OperatingMode = (READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) >> (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos)); OperatingMode = (OperatingMode | ((~OperatingMode >> 1U) & PWR_SR2_SMPSBF)); @@ -1366,7 +1383,7 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) * requested operating mode can differ from effective low power mode. * - dependency on system low-power mode: * - step down mode if system low power mode is run, LP run or stop0, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown * - dependency on BOR level: * - bypass mode if supply voltage drops below BOR level * @note This functions check flags of SMPS operating modes step down @@ -1380,7 +1397,7 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) * * (1) SMPS operating mode step down or open depends on system low-power mode: * - step down mode if system low power mode is run, LP run or stop0, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown */ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void) { @@ -1486,9 +1503,9 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetStartupCurrent(void) */ __STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLevel) { - register __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */ - register int32_t TrimmingSteps; /* Trimming steps between theorical output voltage and calibrated output voltage */ - register int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */ + __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */ + int32_t TrimmingSteps; /* Trimming steps between theorical output voltage and calibrated output voltage */ + int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */ if(OutputVoltageLevel_calibration == 0UL) { @@ -1547,9 +1564,9 @@ __STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLev */ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel(void) { - register __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */ - register int32_t TrimmingSteps; /* Trimming steps between theorical output voltage and calibrated output voltage */ - register int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */ + __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */ + int32_t TrimmingSteps; /* Trimming steps between theorical output voltage and calibrated output voltage */ + int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */ if(OutputVoltageLevel_calibration == 0UL) { @@ -1637,9 +1654,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2(void) * @param LowPowerMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 - * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STOP2 (*) * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode) @@ -1653,9 +1672,11 @@ __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode) * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 - * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STOP2 (*) * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx */ __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void) { @@ -1673,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void) __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode) { /* Unlock bit FPDR */ - WRITE_REG(PWR->C2CR1, 0x0000C1B0U); + WRITE_REG(PWR->C2CR1, 0x0000C1B0UL); /* Update bit FPDR */ MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode); @@ -1761,7 +1782,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU(void) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin) @@ -1783,7 +1804,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin) @@ -1805,7 +1826,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) @@ -1874,6 +1895,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_BLE(void) return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP) == (PWR_C2CR1_BLEEWKUP)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Wakeup 802.15.4 controller from its sleep mode * @note This bit is automatically reset when 802.15.4 controller @@ -1896,6 +1918,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_802_15_4(void) { return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL); } +#endif /** * @} @@ -2179,6 +2202,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEWU(void) return ((READ_BIT(PWR->SR1, PWR_SR1_BLEWUF) == (PWR_SR1_BLEWUF)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Get 802.15.4 wakeup interrupt flag * @rmtoll SR1 802WUF LL_PWR_IsActiveFlag_802WU @@ -2188,6 +2212,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802WU(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL); } +#endif /** * @brief Get BLE end of activity interrupt flag @@ -2199,6 +2224,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEA(void) return ((READ_BIT(PWR->SR1, PWR_SR1_BLEAF) == (PWR_SR1_BLEAF)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Get 802.15.4 end of activity interrupt flag * @rmtoll SR1 802AF LL_PWR_IsActiveFlag_802A @@ -2208,6 +2234,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802A(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL); } +#endif /** * @brief Get critical radio phase end of activity interrupt flag @@ -2239,6 +2266,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_BLEWU(void) WRITE_REG(PWR->SCR, PWR_SCR_CBLEWUF); } +#if defined(PWR_CR3_E802A) /** * @brief Clear 802.15.4 wakeup interrupt flag * @rmtoll SCR 802WU LL_PWR_ClearFlag_802WU @@ -2248,6 +2276,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_802WU(void) { WRITE_REG(PWR->SCR, PWR_SCR_C802WUF); } +#endif /** * @brief Clear BLE end of activity interrupt flag @@ -2259,6 +2288,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_BLEA(void) WRITE_REG(PWR->SCR, PWR_SCR_CBLEAF); } +#if defined(PWR_CR3_E802A) /** * @brief Clear 802.15.4 end of activity interrupt flag * @rmtoll SCR 802AF LL_PWR_ClearFlag_802A @@ -2268,6 +2298,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_802A(void) { WRITE_REG(PWR->SCR, PWR_SCR_C802AF); } +#endif /** * @brief Clear critical radio phase end of activity interrupt flag @@ -2461,6 +2492,7 @@ __STATIC_INLINE void LL_PWR_EnableIT_BLEA(void) SET_BIT(PWR->CR3, PWR_CR3_EBLEA); } +#if defined(PWR_CR3_E802A) /** * @brief Enable 802.15.4 end of activity interrupt for CPU1 * @rmtoll CR3 E802A LL_PWR_EnableIT_802A @@ -2470,7 +2502,7 @@ __STATIC_INLINE void LL_PWR_EnableIT_802A(void) { SET_BIT(PWR->CR3, PWR_CR3_E802A); } - +#endif /** * @brief Disable BLE end of activity interrupt for CPU1 @@ -2482,6 +2514,7 @@ __STATIC_INLINE void LL_PWR_DisableIT_BLEA(void) CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA); } +#if defined(PWR_CR3_E802A) /** * @brief Disable 802.15.4 end of activity interrupt for CPU1 * @rmtoll CR3 E802A LL_PWR_DisableIT_802A @@ -2491,6 +2524,7 @@ __STATIC_INLINE void LL_PWR_DisableIT_802A(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_E802A); } +#endif /** * @brief Check if BLE end of activity interrupt is enabled for CPU1 @@ -2502,6 +2536,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BLEA(void) return ((READ_BIT(PWR->CR3, PWR_CR3_EBLEA) == (PWR_CR3_EBLEA)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Check if 802.15.4 end of activity interrupt is enabled for CPU1 * @rmtoll CR3 E802A LL_PWR_IsEnabledIT_802A @@ -2511,6 +2546,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_802A(void) { return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL); } +#endif /** * @brief Enable critical radio phase end of activity interrupt for CPU1 @@ -2598,6 +2634,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableIT_BLEWU(void) SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP); } +#if defined(PWR_CR3_E802A) /** * @brief Enable 802.15.4 host wakeup interrupt for CPU2 * @rmtoll C2CR3 E802WUP LL_C2_PWR_EnableIT_802WU @@ -2607,6 +2644,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableIT_802WU(void) { SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP); } +#endif /** * @brief Disable BLE host wakeup interrupt for CPU2 @@ -2618,6 +2656,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableIT_BLEWU(void) CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP); } +#if defined(PWR_CR3_E802A) /** * @brief Disable 802.15.4 host wakeup interrupt for CPU2 * @rmtoll C2CR3 E802WUP LL_C2_PWR_DisableIT_802WU @@ -2627,6 +2666,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableIT_802WU(void) { CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP); } +#endif /** * @brief Check if BLE host wakeup interrupt is enabled for CPU2 @@ -2638,6 +2678,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_BLEWU(void) return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP) == (PWR_C2CR3_EBLEWUP)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Check if 802.15.4 host wakeup interrupt is enabled for CPU2 * @rmtoll C2CR3 E802WUP LL_C2_PWR_IsEnabledIT_802WU @@ -2647,6 +2688,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_802WU(void) { return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL); } +#endif /** * @} diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h index e448827..4fb7caa 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h @@ -80,7 +80,7 @@ typedef struct uint32_t HCLK1_Frequency; /*!< HCLK1 clock frequency */ uint32_t HCLK2_Frequency; /*!< HCLK2 clock frequency */ uint32_t HCLK4_Frequency; /*!< HCLK4 clock frequency */ - uint32_t HCLK5_Frequency; /*!< HCLK5 clock frequency */ + uint32_t HCLK5_Frequency; /*!< HCLK5 clock frequency */ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ } LL_RCC_ClocksTypeDef; @@ -121,15 +121,12 @@ typedef struct #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ +#if defined(RCC_HSI48_SUPPORT) #if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ - -#if defined(SPI_I2S_SUPPORT) -#if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */ -#endif /* EXTERNAL_CLOCK_VALUE */ #endif + /** * @} */ @@ -138,19 +135,21 @@ typedef struct * @brief Flags defines which can be used with LL_RCC_WriteReg function * @{ */ -#define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */ -#define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI1 Ready Interrupt Clear */ -#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ -#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ -#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ -#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ -#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ -#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */ +#define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI1 Ready Interrupt Clear */ +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif #if defined(SAI1) -#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ +#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ #endif #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ -#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ +#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ /** * @} */ @@ -159,26 +158,28 @@ typedef struct * @brief Flags defines which can be used with LL_RCC_ReadReg function * @{ */ -#define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */ -#define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */ -#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ -#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ -#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */ +#define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */ +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif #if defined(SAI1) -#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ +#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ #endif #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ -#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ -#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ -#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ -#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ +#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ /** * @} */ @@ -187,18 +188,20 @@ typedef struct * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions * @{ */ -#define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */ -#define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI Ready Interrupt Enable */ -#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ -#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ -#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ -#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ -#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ -#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */ +#define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#endif #if defined(SAI1) #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ #endif -#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ +#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ /** * @} */ @@ -206,10 +209,10 @@ typedef struct /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability * @{ */ -#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ -#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ /** * @} */ @@ -237,13 +240,13 @@ typedef struct /** @defgroup RCC_LL_EC_HSE_CURRENT_CONTROL HSE current control max limits * @{ */ -#define LL_RCC_HSE_CURRENTMAX_0 0x000000000U /*!< HSE current control max limit = 0.18 ma/V*/ -#define LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0 /*!< HSE current control max limit = 0.57 ma/V*/ -#define LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1 /*!< HSE current control max limit = 0.78 ma/V*/ -#define LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.13 ma/V*/ -#define LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2 /*!< HSE current control max limit = 0.61 ma/V*/ -#define LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.65 ma/V*/ -#define LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1) /*!< HSE current control max limit = 2.12 ma/V*/ +#define LL_RCC_HSE_CURRENTMAX_0 0x000000000U /*!< HSE current control max limit = 0.18 ma/V*/ +#define LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0 /*!< HSE current control max limit = 0.57 ma/V*/ +#define LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1 /*!< HSE current control max limit = 0.78 ma/V*/ +#define LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.13 ma/V*/ +#define LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2 /*!< HSE current control max limit = 0.61 ma/V*/ +#define LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.65 ma/V*/ +#define LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1) /*!< HSE current control max limit = 2.12 ma/V*/ #define LL_RCC_HSE_CURRENTMAX_7 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 2.84 ma/V*/ /** * @} @@ -252,8 +255,8 @@ typedef struct /** @defgroup RCC_LL_EC_HSE_SENSE_AMPLIFIER HSE sense amplifier threshold * @{ */ -#define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U) /*!< HSE sense amplifier bias current factor = 1/2*/ -#define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES /*!< HSE sense amplifier bias current factor = 3/4*/ +#define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U) /*!< HSE sense amplifier bias current factor = 1/2*/ +#define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES /*!< HSE sense amplifier bias current factor = 3/4*/ /** * @} */ @@ -270,10 +273,10 @@ typedef struct /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch * @{ */ -#define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */ /** * @} */ @@ -281,10 +284,10 @@ typedef struct /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status * @{ */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */ /** * @} */ @@ -292,7 +295,7 @@ typedef struct /** @defgroup RCC_LL_EC_RF_CLKSOURCE_STATUS RF system clock switch status * @{ */ -#define LL_RCC_RF_CLKSOURCE_HSI 0x00000000U /*!< HSI used as RF system clock */ +#define LL_RCC_RF_CLKSOURCE_HSI 0x00000000U /*!< HSI used as RF system clock */ #define LL_RCC_RF_CLKSOURCE_HSE_DIV2 RCC_EXTCFGR_RFCSS /*!< HSE divided by 2 used as RF system clock */ /** * @} @@ -301,19 +304,19 @@ typedef struct /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler * @{ */ -#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ -#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ -#define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */ -#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ -#define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */ -#define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */ -#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ -#define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */ -#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ -#define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */ -#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ -#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ -#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */ +#define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */ +#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */ +#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ /** * @} @@ -322,10 +325,10 @@ typedef struct /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) * @{ */ -#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */ -#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */ -#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */ -#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */ +#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */ #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 16 */ /** * @} @@ -334,10 +337,10 @@ typedef struct /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) * @{ */ -#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */ -#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */ -#define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */ -#define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */ +#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */ +#define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */ +#define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */ #define LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 16 */ /** * @} @@ -355,17 +358,19 @@ typedef struct /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection * @{ */ -#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ -#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI1 selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI2 selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3) /*!< HSI48 selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< HSE before stabilization selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI1 selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI2 selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3) /*!< HSI48 selection as MCO1 source */ +#endif +#define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< HSE before stabilization selection as MCO1 source */ /** * @} */ @@ -373,11 +378,11 @@ typedef struct /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler * @{ */ -#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */ -#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ -#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ -#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ -#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ +#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ +#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ /** * @} */ @@ -396,9 +401,9 @@ typedef struct /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE_STATUS SMPS clock switch status * @{ */ -#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as SMPS clock */ -#define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */ -#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */ +#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as SMPS clock */ +#define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */ +#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1) /*!< No Clock used as SMPS clock */ /** * @} @@ -430,10 +435,10 @@ typedef struct /** @defgroup RCC_LL_EC_USART1_CLKSOURCE USART1 CLKSOURCE * @{ */ -#define LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 selected as USART1 clock */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 selected as USART1 clock */ #define LL_RCC_USART1_CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK selected as USART1 clock */ -#define LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI selected as USART1 clock */ -#define LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL /*!< LSE selected as USART1 clock */ +#define LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI selected as USART1 clock */ +#define LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL /*!< LSE selected as USART1 clock */ /** * @} */ @@ -444,8 +449,8 @@ typedef struct */ #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */ #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYCLK selected as LPUART1 clock */ -#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */ -#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */ /** * @} */ @@ -454,13 +459,13 @@ typedef struct /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE * @{ */ -#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */ #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */ -#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */ +#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */ #if defined(I2C3) -#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */ #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */ -#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */ +#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */ #endif /** * @} @@ -470,13 +475,13 @@ typedef struct * @{ */ #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */ #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM2 clock */ -#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */ -#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */ -#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */ /** * @} */ @@ -485,9 +490,9 @@ typedef struct /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE * @{ */ -#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U /*!< PLLSAI1 selected as SAI1 clock */ -#define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL selected as SAI1 clock */ -#define LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1 /*!< HSI selected as SAI1 clock */ +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U /*!< PLLSAI1 selected as SAI1 clock */ +#define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL selected as SAI1 clock */ +#define LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1 /*!< HSI selected as SAI1 clock */ #define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL /*!< External input selected as SAI1 clock */ /** * @} @@ -497,12 +502,14 @@ typedef struct /** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE * @{ */ -#define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock*/ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock */ +#endif #if defined(SAI1) -#define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock*/ +#define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock */ #endif -#define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock*/ -#define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock*/ +#define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock */ +#define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock */ /** * @} */ @@ -510,12 +517,14 @@ typedef struct /** @defgroup RCC_LL_EC_USB_CLKSOURCE USB CLKSOURCE * @{ */ -#define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock*/ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock */ +#endif #if defined(SAI1) -#define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock*/ +#define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock */ #endif -#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock*/ -#define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock*/ +#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock */ +#define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock */ /** * @} */ @@ -524,13 +533,11 @@ typedef struct * @{ */ #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/ -#if defined(STM32WB55xx) || defined (STM32WB5Mxx) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/ -#elif defined(STM32WB35xx) -#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock*/ #endif -#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/ -#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/ +#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */ /** * @} */ @@ -539,24 +546,12 @@ typedef struct * @{ */ #define LL_RCC_RNG_CLKSOURCE_CLK48 0x00000000U /*!< CLK48 divided by 3 selected as RNG Clock */ -#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as ADC clock*/ -#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as ADC clock*/ +#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as ADC clock */ +#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as ADC clock */ /** * @} */ -#if defined(SPI_I2S_SUPPORT) -/** @defgroup RCC_LL_EC_I2SCLKSOURCE Peripheral I2S clock source selection - * @{ - */ -#define LL_RCC_I2S_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as I2S clock*/ -#define LL_RCC_I2S_CLKSOURCE_HSI RCC_CCIPR_I2SSEL_0 /*!< HSI clock used as I2S clock source */ -#define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2SSEL_1 /*!< PLL clock used as I2S clock source */ -#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2SSEL /*!< External clock used as I2S clock source */ -/** - * @} - */ -#endif /** @defgroup RCC_LL_EC_USART1 USART1 * @{ @@ -636,22 +631,13 @@ typedef struct * @} */ -#if defined(SPI_I2S_SUPPORT) -/** @defgroup RCC_LL_EC_I2S I2S - * @{ - */ -#define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2SSEL /*!< I2S clock source selection bits */ -/** - * @} - */ -#endif /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ -#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** @@ -661,10 +647,9 @@ typedef struct /** @defgroup RCC_LL_EC_RFWKP_CLKSOURCE RF Wakeup clock source selection * @{ */ -#define LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RF Wakeup clock */ -#define LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0 /*!< LSE oscillator clock used as RF Wakeup clock */ -#define LL_RCC_RFWKP_CLKSOURCE_LSI RCC_CSR_RFWKPSEL_1 /*!< LSI oscillator clock used as RF Wakeup clock */ -#define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL /*!< HSE oscillator clock divided by 1024 used as RF Wakeup clock */ +#define LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RF Wakeup clock */ +#define LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0 /*!< LSE oscillator clock used as RF Wakeup clock */ +#define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL /*!< HSE oscillator clock divided by 1024 used as RF Wakeup clock */ /** * @} @@ -674,9 +659,9 @@ typedef struct /** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLSAI1 entry clock source * @{ */ -#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ -#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ +#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */ /** * @} @@ -714,37 +699,37 @@ typedef struct /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) * @{ */ -#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */ -#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */ -#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */ -#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */ -#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */ -#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */ -#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */ -#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */ -#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */ -#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */ -#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */ -#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */ -#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */ -#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */ -#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */ -#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */ -#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */ -#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */ -#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */ -#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */ -#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */ -#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */ -#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */ -#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */ -#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */ -#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/ -#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */ -#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */ -#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */ -#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */ -#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */ +#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */ +#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */ +#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */ +#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */ +#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */ +#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */ +#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */ +#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */ +#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */ +#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */ +#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 16 */ +#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */ +#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */ +#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */ +#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */ +#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */ +#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */ +#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */ +#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 24 */ +#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */ +#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */ +#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27 */ +#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 28 */ +#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */ +#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 30 */ +#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 31 */ +#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 32 */ /** * @} */ @@ -768,12 +753,12 @@ typedef struct /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLQ) * @{ */ -#define LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */ -#define LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 3 */ -#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */ -#define LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2) /*!< PLLSAI1 division factor for PLLSAI1Q output by 5 */ -#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */ -#define LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 7 */ +#define LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */ +#define LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 3 */ +#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */ +#define LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2) /*!< PLLSAI1 division factor for PLLSAI1Q output by 5 */ +#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */ +#define LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 7 */ #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */ /** * @} @@ -782,37 +767,37 @@ typedef struct /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLP) * @{ */ -#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */ -#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */ -#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */ -#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */ -#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */ -#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */ -#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)/*!< Main PLL division factor for PLLP output by 8 */ -#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */ -#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */ -#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */ -#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 12 */ -#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */ -#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 14 */ -#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 15 */ -#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */ -#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */ -#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */ -#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */ -#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 20 */ -#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */ -#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 22 */ -#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 23 */ -#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */ -#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */ -#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 26 */ -#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 27*/ -#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */ -#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 29 */ -#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */ -#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */ -#define LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */ +#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */ +#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */ +#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */ +#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */ +#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */ +#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */ +#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */ +#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */ +#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */ +#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */ +#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 16 */ +#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */ +#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */ +#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */ +#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */ +#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */ +#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */ +#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */ +#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 24 */ +#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */ +#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */ +#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/ +#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 28 */ +#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */ +#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 30 */ +#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 31 */ +#define LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 32 */ /** * @} */ @@ -820,12 +805,12 @@ typedef struct /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLR) * @{ */ -#define LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */ -#define LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 3 */ -#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */ -#define LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2) /*!< PLLSAI1 division factor for PLLSAI1R output by 5 */ -#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */ -#define LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 7 */ +#define LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */ +#define LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 3 */ +#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */ +#define LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2) /*!< PLLSAI1 division factor for PLLSAI1R output by 5 */ +#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */ +#define LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 7 */ #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */ /** * @} @@ -1000,59 +985,6 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) -#if defined(SPI_I2S_SUPPORT) -/** - * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain - * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_1 - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 - * @param __PLLP__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLP_DIV_2 - * @arg @ref LL_RCC_PLLP_DIV_3 - * @arg @ref LL_RCC_PLLP_DIV_4 - * @arg @ref LL_RCC_PLLP_DIV_5 - * @arg @ref LL_RCC_PLLP_DIV_6 - * @arg @ref LL_RCC_PLLP_DIV_7 - * @arg @ref LL_RCC_PLLP_DIV_8 - * @arg @ref LL_RCC_PLLP_DIV_9 - * @arg @ref LL_RCC_PLLP_DIV_10 - * @arg @ref LL_RCC_PLLP_DIV_11 - * @arg @ref LL_RCC_PLLP_DIV_12 - * @arg @ref LL_RCC_PLLP_DIV_13 - * @arg @ref LL_RCC_PLLP_DIV_14 - * @arg @ref LL_RCC_PLLP_DIV_15 - * @arg @ref LL_RCC_PLLP_DIV_16 - * @arg @ref LL_RCC_PLLP_DIV_17 - * @arg @ref LL_RCC_PLLP_DIV_18 - * @arg @ref LL_RCC_PLLP_DIV_19 - * @arg @ref LL_RCC_PLLP_DIV_20 - * @arg @ref LL_RCC_PLLP_DIV_21 - * @arg @ref LL_RCC_PLLP_DIV_22 - * @arg @ref LL_RCC_PLLP_DIV_23 - * @arg @ref LL_RCC_PLLP_DIV_24 - * @arg @ref LL_RCC_PLLP_DIV_25 - * @arg @ref LL_RCC_PLLP_DIV_26 - * @arg @ref LL_RCC_PLLP_DIV_27 - * @arg @ref LL_RCC_PLLP_DIV_28 - * @arg @ref LL_RCC_PLLP_DIV_29 - * @arg @ref LL_RCC_PLLP_DIV_30 - * @arg @ref LL_RCC_PLLP_DIV_31 - * @arg @ref LL_RCC_PLLP_DIV_32 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) -#endif /** * @brief Helper macro to calculate the PLLQCLK frequency used on 48M domain @@ -1364,26 +1296,6 @@ __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) SET_BIT(RCC->CR, RCC_CR_CSSON); } -/** - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); -} - /** * @brief Enable HSE crystal oscillator (HSE ON) * @rmtoll CR HSEON LL_RCC_HSE_Enable @@ -1635,6 +1547,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) * @} */ +#if defined(RCC_HSI48_SUPPORT) /** @defgroup RCC_LL_EF_HSI48 HSI48 * @{ */ @@ -1682,6 +1595,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) /** * @} */ +#endif /** @defgroup RCC_LL_EF_LSE LSE * @{ @@ -2164,7 +2078,6 @@ __STATIC_INLINE uint32_t LL_RCC_GetRFClockSource(void) * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE - * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI * @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 * @retval None */ @@ -2179,7 +2092,6 @@ __STATIC_INLINE void LL_RCC_SetRFWKPClockSource(uint32_t Source) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE - * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI * @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 */ __STATIC_INLINE uint32_t LL_RCC_GetRFWKPClockSource(void) @@ -2534,7 +2446,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler(void) * @arg @ref LL_RCC_MCO1SOURCE_MSI * @arg @ref LL_RCC_MCO1SOURCE_HSI * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_HSI48 + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK * @arg @ref LL_RCC_MCO1SOURCE_LSI1 * @arg @ref LL_RCC_MCO1SOURCE_LSI2 @@ -2546,6 +2458,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler(void) * @arg @ref LL_RCC_MCO1_DIV_4 * @arg @ref LL_RCC_MCO1_DIV_8 * @arg @ref LL_RCC_MCO1_DIV_16 + * @note (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) @@ -2600,9 +2513,10 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * @note (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) @@ -2665,7 +2579,7 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) * @brief Configure CLK48 clock source * @rmtoll CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource * @param CLK48xSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI @@ -2705,7 +2619,7 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE * @param CLK48xSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI @@ -2739,22 +2653,6 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); } -#if defined(SPI_I2S_SUPPORT) -/** - * @brief Configure I2Sx clock source - * @rmtoll CCIPR I2SSEL LL_RCC_SetI2SClockSource - * @param I2SxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE - * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL - * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) -{ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2SSEL, I2SxSource); -} -#endif /** * @brief Get USARTx clock source @@ -2800,9 +2698,10 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * @note (*) Value not defined for all devices */ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) { @@ -2869,7 +2768,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) * @param CLK48x This parameter can be one of the following values: * @arg @ref LL_RCC_CLK48_CLKSOURCE * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI @@ -2916,23 +2815,6 @@ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); } -#if defined(SPI_I2S_SUPPORT) -/** - * @brief Get I2Sx clock source - * @rmtoll CCIPR I2SSEL LL_RCC_GetI2SClockSource - * @param I2Sx This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE - * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL - * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN - */ -__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx)); -} -#endif /** * @} */ @@ -3920,6 +3802,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); } +#if defined(RCC_HSI48_SUPPORT) /** * @brief Clear HSI48 ready interrupt flag * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY @@ -3929,6 +3812,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) { SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); } +#endif #if defined(SAI1) /** @@ -4032,6 +3916,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); } +#if defined(RCC_HSI48_SUPPORT) /** * @brief Check if HSI48 ready interrupt occurred or not * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY @@ -4041,6 +3926,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) { return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); } +#endif #if defined(SAI1) /** @@ -4282,6 +4168,7 @@ __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); } +#if defined(RCC_HSI48_SUPPORT) /** * @brief Enable HSI48 ready interrupt * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY @@ -4291,6 +4178,7 @@ __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) { SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); } +#endif #if defined(SAI1) /** @@ -4383,6 +4271,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); } +#if defined(RCC_HSI48_SUPPORT) /** * @brief Disable HSI48 ready interrupt * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY @@ -4392,6 +4281,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) { CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); } +#endif #if defined(SAI1) /** @@ -4484,6 +4374,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL); } +#if defined(RCC_HSI48_SUPPORT) /** * @brief Checks if HSI48 ready interrupt source is enabled or disabled. * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY @@ -4493,6 +4384,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) { return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL); } +#endif #if defined(SAI1) /** @@ -4553,9 +4445,6 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); uint32_t LL_RCC_GetRTCClockFreq(void); uint32_t LL_RCC_GetRFWKPClockFreq(void); -#if defined(SPI_I2S_SUPPORT) -uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); -#endif /** * @} */ diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rtc.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rtc.h index 96d9e08..fb92e16 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rtc.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rtc.h @@ -1138,7 +1138,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU)); return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)); @@ -1176,7 +1176,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)); return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)); @@ -1214,7 +1214,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)); return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)); @@ -1243,7 +1243,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp; + uint32_t temp; temp = Format12_24 | \ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ @@ -1271,7 +1271,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ @@ -1410,7 +1410,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU)); return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)); @@ -1506,7 +1506,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)); return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)); @@ -1539,7 +1539,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU)); return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)); @@ -1582,7 +1582,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) { - register uint32_t temp; + uint32_t temp; temp = (WeekDay << RTC_DR_WDU_Pos) | \ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ @@ -1610,7 +1610,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ @@ -1739,7 +1739,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU)); return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos)); @@ -1834,7 +1834,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU)); return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos)); @@ -1865,7 +1865,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)); return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos)); @@ -1896,7 +1896,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos)); @@ -1922,7 +1922,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp; + uint32_t temp; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ @@ -2117,7 +2117,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU)); return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos)); @@ -2212,7 +2212,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU)); return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos)); @@ -2243,7 +2243,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)); return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos)); @@ -2274,7 +2274,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos)); @@ -2300,7 +2300,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp; + uint32_t temp; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ @@ -3081,7 +3081,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) { - register __IO uint32_t* tmp; + __IO uint32_t* tmp; tmp = &(RTCx->BKP0R) + BackupRegister; @@ -3117,7 +3117,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe */ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) { - register const __IO uint32_t *tmp; + const __IO uint32_t *tmp; tmp = &(RTCx->BKP0R) + BackupRegister; diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h index 9230ff7..35709d1 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h @@ -266,8 +266,8 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold * @{ */ -#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ -#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ /** * @} */ @@ -848,8 +848,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) */ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) { - register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); - register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); return (Ssm | Ssoe); } @@ -1405,872 +1405,6 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); * @} */ -#if defined(SPI_I2S_SUPPORT) -/** @defgroup I2S_LL I2S - * @{ - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure - * @{ - */ - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - uint32_t Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_LL_EC_MODE - - This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ - - uint32_t Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_LL_EC_STANDARD - - This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ - - - uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT - - This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ - - - uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT - - This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ - - - uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ - - Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity - and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ - - - uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_LL_EC_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ - -} LL_I2S_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants - * @{ - */ - -/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_I2S_ReadReg function - * @{ - */ -#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ -#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ -#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ -#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ -#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ -#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions - * @{ - */ -#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ -#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ -#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_DATA_FORMAT Data format - * @{ - */ -#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ -#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ -#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_STANDARD I2s Standard - * @{ - */ -#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ -#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ -#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ -#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ -#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_MODE Operation Mode - * @{ - */ -#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ -#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ -#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ -#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor - * @{ - */ -#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ -#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output - * @{ - */ -#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ -#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency - * @{ - */ - -#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ -#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ -#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ -#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ -#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ -#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ -#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ -#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ -#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ -#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros - * @{ - */ - -/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in I2S register - * @param __INSTANCE__ I2S Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in I2S register - * @param __INSTANCE__ I2S Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions - * @{ - */ - -/** @defgroup I2S_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Select I2S mode and Enable I2S peripheral - * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n - * I2SCFGR I2SE LL_I2S_Enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); -} - -/** - * @brief Disable I2S peripheral - * @rmtoll I2SCFGR I2SE LL_I2S_Disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); -} - -/** - * @brief Check if I2S peripheral is enabled - * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); -} - -/** - * @brief Set I2S data frame length - * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n - * I2SCFGR CHLEN LL_I2S_SetDataFormat - * @param SPIx SPI Instance - * @param DataFormat This parameter can be one of the following values: - * @arg @ref LL_I2S_DATAFORMAT_16B - * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED - * @arg @ref LL_I2S_DATAFORMAT_24B - * @arg @ref LL_I2S_DATAFORMAT_32B - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) -{ - MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); -} - -/** - * @brief Get I2S data frame length - * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n - * I2SCFGR CHLEN LL_I2S_GetDataFormat - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_DATAFORMAT_16B - * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED - * @arg @ref LL_I2S_DATAFORMAT_24B - * @arg @ref LL_I2S_DATAFORMAT_32B - */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); -} - -/** - * @brief Set I2S clock polarity - * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity - * @param SPIx SPI Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_I2S_POLARITY_LOW - * @arg @ref LL_I2S_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) -{ - SET_BIT(SPIx->I2SCFGR, ClockPolarity); -} - -/** - * @brief Get I2S clock polarity - * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_POLARITY_LOW - * @arg @ref LL_I2S_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); -} - -/** - * @brief Set I2S standard protocol - * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n - * I2SCFGR PCMSYNC LL_I2S_SetStandard - * @param SPIx SPI Instance - * @param Standard This parameter can be one of the following values: - * @arg @ref LL_I2S_STANDARD_PHILIPS - * @arg @ref LL_I2S_STANDARD_MSB - * @arg @ref LL_I2S_STANDARD_LSB - * @arg @ref LL_I2S_STANDARD_PCM_SHORT - * @arg @ref LL_I2S_STANDARD_PCM_LONG - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) -{ - MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); -} - -/** - * @brief Get I2S standard protocol - * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n - * I2SCFGR PCMSYNC LL_I2S_GetStandard - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_STANDARD_PHILIPS - * @arg @ref LL_I2S_STANDARD_MSB - * @arg @ref LL_I2S_STANDARD_LSB - * @arg @ref LL_I2S_STANDARD_PCM_SHORT - * @arg @ref LL_I2S_STANDARD_PCM_LONG - */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); -} - -/** - * @brief Set I2S transfer mode - * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode - * @param SPIx SPI Instance - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_I2S_MODE_SLAVE_TX - * @arg @ref LL_I2S_MODE_SLAVE_RX - * @arg @ref LL_I2S_MODE_MASTER_TX - * @arg @ref LL_I2S_MODE_MASTER_RX - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) -{ - MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); -} - -/** - * @brief Get I2S transfer mode - * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_MODE_SLAVE_TX - * @arg @ref LL_I2S_MODE_SLAVE_RX - * @arg @ref LL_I2S_MODE_MASTER_TX - * @arg @ref LL_I2S_MODE_MASTER_RX - */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); -} - -/** - * @brief Set I2S linear prescaler - * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear - * @param SPIx SPI Instance - * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) -{ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); -} - -/** - * @brief Get I2S linear prescaler - * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear - * @param SPIx SPI Instance - * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); -} - -/** - * @brief Set I2S parity prescaler - * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity - * @param SPIx SPI Instance - * @param PrescalerParity This parameter can be one of the following values: - * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN - * @arg @ref LL_I2S_PRESCALER_PARITY_ODD - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) -{ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); -} - -/** - * @brief Get I2S parity prescaler - * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN - * @arg @ref LL_I2S_PRESCALER_PARITY_ODD - */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); -} - -/** - * @brief Enable the master clock ouput (Pin MCK) - * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); -} - -/** - * @brief Disable the master clock ouput (Pin MCK) - * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); -} - -/** - * @brief Check if the master clock ouput (Pin MCK) is enabled - * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); -} - -#if defined(SPI_I2SCFGR_ASTRTEN) -/** - * @brief Enable asynchronous start - * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); -} - -/** - * @brief Disable asynchronous start - * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); -} - -/** - * @brief Check if asynchronous start is enabled - * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); -} -#endif /* SPI_I2SCFGR_ASTRTEN */ - -/** - * @} - */ - -/** @defgroup I2S_LL_EF_FLAG FLAG Management - * @{ - */ - -/** - * @brief Check if Rx buffer is not empty - * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_RXNE(SPIx); -} - -/** - * @brief Check if Tx buffer is empty - * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_TXE(SPIx); -} - -/** - * @brief Get busy flag - * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_BSY(SPIx); -} - -/** - * @brief Get overrun error flag - * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_OVR(SPIx); -} - -/** - * @brief Get underrun error flag - * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); -} - -/** - * @brief Get frame format error flag - * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_FRE(SPIx); -} - -/** - * @brief Get channel side flag. - * @note 0: Channel Left has to be transmitted or has been received\n - * 1: Channel Right has to be transmitted or has been received\n - * It has no significance in PCM mode. - * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); -} - -/** - * @brief Clear overrun error flag - * @rmtoll SR OVR LL_I2S_ClearFlag_OVR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) -{ - LL_SPI_ClearFlag_OVR(SPIx); -} - -/** - * @brief Clear underrun error flag - * @rmtoll SR UDR LL_I2S_ClearFlag_UDR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) -{ - __IO uint32_t tmpreg; - tmpreg = SPIx->SR; - (void)tmpreg; -} - -/** - * @brief Clear frame format error flag - * @rmtoll SR FRE LL_I2S_ClearFlag_FRE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) -{ - LL_SPI_ClearFlag_FRE(SPIx); -} - -/** - * @} - */ - -/** @defgroup I2S_LL_EF_IT Interrupt Management - * @{ - */ - -/** - * @brief Enable error IT - * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). - * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableIT_ERR(SPIx); -} - -/** - * @brief Enable Rx buffer not empty IT - * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableIT_RXNE(SPIx); -} - -/** - * @brief Enable Tx buffer empty IT - * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableIT_TXE(SPIx); -} - -/** - * @brief Disable error IT - * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). - * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableIT_ERR(SPIx); -} - -/** - * @brief Disable Rx buffer not empty IT - * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableIT_RXNE(SPIx); -} - -/** - * @brief Disable Tx buffer empty IT - * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableIT_TXE(SPIx); -} - -/** - * @brief Check if ERR IT is enabled - * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledIT_ERR(SPIx); -} - -/** - * @brief Check if RXNE IT is enabled - * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledIT_RXNE(SPIx); -} - -/** - * @brief Check if TXE IT is enabled - * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledIT_TXE(SPIx); -} - -/** - * @} - */ - -/** @defgroup I2S_LL_EF_DMA DMA Management - * @{ - */ - -/** - * @brief Enable DMA Rx - * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableDMAReq_RX(SPIx); -} - -/** - * @brief Disable DMA Rx - * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableDMAReq_RX(SPIx); -} - -/** - * @brief Check if DMA Rx is enabled - * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledDMAReq_RX(SPIx); -} - -/** - * @brief Enable DMA Tx - * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableDMAReq_TX(SPIx); -} - -/** - * @brief Disable DMA Tx - * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableDMAReq_TX(SPIx); -} - -/** - * @brief Check if DMA Tx is enabled - * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledDMAReq_TX(SPIx); -} - -/** - * @} - */ - -/** @defgroup I2S_LL_EF_DATA DATA Management - * @{ - */ - -/** - * @brief Read 16-Bits in data register - * @rmtoll DR DR LL_I2S_ReceiveData16 - * @param SPIx SPI Instance - * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) -{ - return LL_SPI_ReceiveData16(SPIx); -} - -/** - * @brief Write 16-Bits in data register - * @rmtoll DR DR LL_I2S_TransmitData16 - * @param SPIx SPI Instance - * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) -{ - LL_SPI_TransmitData16(SPIx, TxData); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); -void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); -void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* SPI_I2S_SUPPORT */ - #endif /* defined (SPI1) || defined (SPI2) */ /** diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h index 06de19e..d1cf11c 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h @@ -69,10 +69,6 @@ extern "C" { * @} */ -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ @@ -201,6 +197,7 @@ extern "C" { #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2B Write protection page 33 */ #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2B Write protection page 34 */ #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2B Write protection page 35 */ +#if defined(SYSCFG_SWPR2_PAGE36) #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2B Write protection page 36 */ #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2B Write protection page 37 */ #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2B Write protection page 38 */ @@ -229,6 +226,7 @@ extern "C" { #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2B Write protection page 61 */ #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2B Write protection page 62 */ #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2B Write protection page 63 */ +#endif /** * @} */ @@ -237,8 +235,12 @@ extern "C" { * @{ */ #define LL_SYSCFG_GRP1_TIM1 SYSCFG_IMR1_TIM1IM /*!< Enabling of interrupt from Timer 1 to CPU1 */ +#if defined(TIM16) #define LL_SYSCFG_GRP1_TIM16 SYSCFG_IMR1_TIM16IM /*!< Enabling of interrupt from Timer 16 to CPU1 */ +#endif +#if defined(TIM17) #define LL_SYSCFG_GRP1_TIM17 SYSCFG_IMR1_TIM17IM /*!< Enabling of interrupt from Timer 17 to CPU1 */ +#endif #define LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */ #define LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */ @@ -393,8 +395,12 @@ extern "C" { * @{ */ #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */ +#if defined(TIM16) #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */ +#endif +#if defined(TIM17) #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */ +#endif /** * @} */ @@ -403,8 +409,12 @@ extern "C" { * @{ */ #define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */ +#if defined(TIM16) #define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */ +#endif +#if defined(TIM17) #define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */ +#endif /** * @} */ @@ -514,6 +524,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } +#if defined(SYSCFG_CFGR1_ANASWVDD) /** * @brief Enable the Analog GPIO switch to control voltage selection * when the supply voltage is supplied by VDDA @@ -537,6 +548,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableAnalogGpioSwitch(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } +#endif /** * @brief Enable the I2C fast mode plus driving capability. @@ -2246,6 +2258,10 @@ __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void) * @} */ +/** + * @} + */ + #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ /** diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h index 6688456..a7bd336 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h @@ -127,9 +127,13 @@ static const uint8_t SHIFT_TAB_OISx[] = #define TIMx_OR_RMP_SHIFT 16U #define TIMx_OR_RMP_MASK 0x0000FFFFU #define TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT) -#define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT) +#define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP) << TIMx_OR_RMP_SHIFT) +#if defined(TIM16) #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) +#endif /* TIM16 */ +#if defined(TIM17) #define TIM17_OR_RMP_MASK (TIM17_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) +#endif /* TIM17 */ /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ #define DT_DELAY_1 ((uint8_t)0x7F) @@ -456,6 +460,15 @@ typedef struct @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE @@ -477,6 +490,15 @@ typedef struct @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK2() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE @@ -587,8 +609,8 @@ typedef struct */ #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -1987,8 +2044,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -2026,8 +2083,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -2060,7 +2117,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2092,7 +2149,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -2129,7 +2186,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } @@ -2161,7 +2218,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } @@ -2186,8 +2243,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2212,8 +2269,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2238,9 +2295,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2264,8 +2321,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2289,8 +2346,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2314,9 +2371,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2343,8 +2400,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2370,8 +2427,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2399,9 +2456,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2670,8 +2727,8 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -2698,8 +2755,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2722,8 +2779,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2748,8 +2805,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2773,8 +2830,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2811,8 +2868,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2848,8 +2905,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2877,7 +2934,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2905,7 +2962,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -3294,15 +3351,16 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @param ETRSource This parameter can be one of the following values: * @arg @ref LL_TIM_ETRSOURCE_GPIO * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1 - * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2 - * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3 - * @arg @ref LL_TIM_ETRSOURCE_COMP1 - * @arg @ref LL_TIM_ETRSOURCE_COMP2 + * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2 (*) + * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3 (*) + * @arg @ref LL_TIM_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_ETRSOURCE_COMP2 (*) + * + * (*) Value not defined in all devices. \n * @retval None */ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) { - MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); } @@ -3343,8 +3401,18 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) * @brief Configure the break input. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, BreakAFMode must be set to + * LL_TIM_BREAK_AFMODE_INPUT. * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n - * BDTR BKF LL_TIM_ConfigBRK + * BDTR BKF LL_TIM_ConfigBRK\n + * BDTR BKBID LL_TIM_ConfigBRK * @param TIMx Timer instance * @param BreakPolarity This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_POLARITY_LOW @@ -3366,12 +3434,42 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param BreakAFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL * @retval None */ -__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, - uint32_t BreakFilter) +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, + uint32_t BreakAFMode) { - MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); +} + +/** + * @brief Disarm the break input (when it operates in bidirectional mode). + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Re-arm the break input (when it operates in bidirectional mode). + * @note The Break input is automatically armed as soon as MOE bit is set. + * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } /** @@ -3404,8 +3502,18 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) * @brief Configure the break 2 input. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break 2 input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, Break2AFMode must be set to + * LL_TIM_BREAK2_AFMODE_INPUT. * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n - * BDTR BK2F LL_TIM_ConfigBRK2 + * BDTR BK2F LL_TIM_ConfigBRK2\n + * BDTR BK2BID LL_TIM_ConfigBRK2 * @param TIMx Timer instance * @param Break2Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK2_POLARITY_LOW @@ -3427,11 +3535,42 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param Break2AFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, + uint32_t Break2AFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); +} + +/** + * @brief Disarm the break 2 input (when it operates in bidirectional mode). + * @note The break 2 input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Re-arm the break 2 input (when it operates in bidirectional mode). + * @note The Break 2 input is automatically armed as soon as MOE bit is set. + * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 + * @param TIMx Timer instance * @retval None */ -__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) +__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) { - MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } /** @@ -3560,7 +3699,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); SET_BIT(*pReg, Source); } @@ -3588,7 +3727,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); CLEAR_BIT(*pReg, Source); } @@ -3620,7 +3759,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } /** @@ -3704,8 +3843,8 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n * TIM2_OR TI4_RMP LL_TIM_SetRemap\n * TIM2_OR TI1_RMP LL_TIM_SetRemap\n - * TIM16_OR TI1_RMP LL_TIM_SetRemap\n - * TIM17_OR TI1_RMP LL_TIM_SetRemap + * TIM16_OR TI1_RMP LL_TIM_SetRemap (***)\n + * TIM17_OR TI1_RMP LL_TIM_SetRemap (***) * @param TIMx Timer instance * @param Remap Remap param depends on the TIMx. Description available only * in CHM version of the User Manual (not in .pdf). @@ -3718,18 +3857,18 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB * . . ADC1_RMP can be one of the following values * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 - * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 - * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (**) + * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (**) * * . . TI1_RMP can be one of the following values * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (*) + * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (**) * * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where * * ITR1_RMP can be one of the following values * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE - * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF (*) + * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF (**) * * . . ETR1_RMP can be one of the following values * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO @@ -3737,25 +3876,27 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB * * . . TI4_RMP can be one of the following values * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO - * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 (*) - * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 (*) - * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (*) + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 (**) + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 (**) + * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (**) * - * TIM16: one of the following values + * TIM16: one of the following values (*) * * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC * - * TIM17: one of the following values + * TIM17: one of the following values (*) * * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO * - * (*) Value not defined in all devices. \n + * (*) Timer instance not available on all devices \n + * (**) Value not defined in all devices. + * (***) Register not available in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usart.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usart.h index 47e742f..1232185 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usart.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usart.h @@ -1867,8 +1867,8 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate) { - register uint32_t usartdiv; - register uint32_t brrtemp; + uint32_t usartdiv; + uint32_t brrtemp; if (OverSampling == LL_USART_OVERSAMPLING_8) { @@ -1911,9 +1911,9 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph */ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) { - register uint32_t usartdiv; - register uint32_t brrresult = 0x0U; - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue])); usartdiv = USARTx->BRR; @@ -4195,7 +4195,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx */ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { diff --git a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_utils.h b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_utils.h index e7c1722..927ff65 100644 --- a/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_utils.h +++ b/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_utils.h @@ -95,19 +95,19 @@ extern "C" { typedef struct { uint32_t PLLM; /*!< Division factor for PLL VCO input clock. - This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV + This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV. This feature can be modified afterwards using unitary function @ref LL_RCC_PLL_ConfigDomain_SYS(). */ uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 6 and Max_Data = 127 + This parameter must be a number between Min_Data = 6 and Max_Data = 127. This feature can be modified afterwards using unitary function @ref LL_RCC_PLL_ConfigDomain_SYS(). */ uint32_t PLLR; /*!< Division for the main system clock. - This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV + This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV. This feature can be modified afterwards using unitary function @ref LL_RCC_PLL_ConfigDomain_SYS(). */ @@ -119,31 +119,31 @@ typedef struct typedef struct { uint32_t CPU1CLKDivider; /*!< The CPU1 clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV. This feature can be modified afterwards using unitary function @ref LL_RCC_SetAHBPrescaler(). */ uint32_t CPU2CLKDivider; /*!< The CPU2 clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV. This feature can be modified afterwards using unitary function @ref LL_C2_RCC_SetAHBPrescaler(). */ uint32_t AHB4CLKDivider; /*!< The AHBS clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV. This feature can be modified afterwards using unitary function @ref LL_RCC_SetAHB4Prescaler(). */ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK1). - This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV. This feature can be modified afterwards using unitary function @ref LL_RCC_SetAPB1Prescaler(). */ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK1). - This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV. This feature can be modified afterwards using unitary function @ref LL_RCC_SetAPB2Prescaler(). */ @@ -171,12 +171,10 @@ typedef struct /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE * @{ */ -#define LL_UTILS_PACKAGETYPE_CSP100 0x00000011U /*!< CSP100 package type */ -#define LL_UTILS_PACKAGETYPE_CSP100_C 0x00000012U /*!< CSP100 package type w/ capfree LDO */ +#define LL_UTILS_PACKAGETYPE_CSP100 0x00000011U /*!< CSP100/BGA129 package type */ #define LL_UTILS_PACKAGETYPE_QFN68 0x00000013U /*!< QFN68 package type */ -#define LL_UTILS_PACKAGETYPE_QFN68_C 0x00000014U /*!< QFN68 package type w/ capfree LDO */ #define LL_UTILS_PACKAGETYPE_QFN48 0x0000000AU /*!< QFN48 package type */ -#define LL_UTILS_PACKAGETYPE_QFN48_C 0x00000015U /*!< QFN48 package type w/ capfree LDO */ + /** * @} */ @@ -237,11 +235,8 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @brief Get Package type * @retval Returned value can be one of the following values: * @arg @ref LL_UTILS_PACKAGETYPE_CSP100 - * @arg @ref LL_UTILS_PACKAGETYPE_CSP100_C * @arg @ref LL_UTILS_PACKAGETYPE_QFN68 - * @arg @ref LL_UTILS_PACKAGETYPE_QFN68_C * @arg @ref LL_UTILS_PACKAGETYPE_QFN48 - * @arg @ref LL_UTILS_PACKAGETYPE_QFN48_C * */ __STATIC_INLINE uint32_t LL_GetPackageType(void) @@ -286,6 +281,7 @@ void LL_mDelay(uint32_t Delay); */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency); ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c index 416f81c..e15aacb 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c @@ -56,7 +56,7 @@ * @brief STM32WBxx HAL Driver version number */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBxx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ +#define __STM32WBxx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ #define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ @@ -253,10 +253,10 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { HAL_StatusTypeDef status = HAL_OK; - if (uwTickFreq != 0U) + if ((uint32_t)uwTickFreq != 0U) { /*Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/ (1000U /uwTickFreq)) == 0U) + if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/ (1000U / (uint32_t)uwTickFreq)) == 0U) { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) @@ -759,6 +759,7 @@ void HAL_SYSCFG_DisableIOBooster(void) LL_SYSCFG_DisableAnalogBooster(); } +#if defined(SYSCFG_CFGR1_ANASWVDD) /** * @brief Enable the I/O analog switch supplied by VDD * @note To be used when I/O analog switch voltage booster is not enabled @@ -778,6 +779,7 @@ void HAL_SYSCFG_DisableIOVdd(void) { LL_SYSCFG_DisableAnalogGpioSwitch(); } +#endif /* SYSCFG_CFGR1_ANASWVDD */ /** * @brief Enable the access for security IP diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c index ecf52d2..47d3f1f 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c @@ -3,7 +3,7 @@ * @file stm32wbxx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) + * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Initialization and de-initialization functions * ++ Initialization and Configuration of ADC @@ -341,6 +341,11 @@ /* Unit: cycles of CPU clock. */ #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Register CHSELR bits corresponding to ranks 2 to 8 . */ +#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8) +#endif + /** * @} @@ -394,11 +399,15 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpCFGR; + uint32_t tmpCFGR = 0UL; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; +#if defined (ADC_SUPPORT_2_5_MSPS) + uint32_t tmpCFGR2 = 0UL; +#else uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; +#endif /* Check ADC handle */ if (hadc == NULL) @@ -419,6 +428,23 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); +#if defined (ADC_SUPPORT_2_5_MSPS) + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); + assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1)); + assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2)); + + assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); + + if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + + if(hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + } + } +#else assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) @@ -434,6 +460,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ @@ -445,8 +472,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ +#if !defined (ADC_SUPPORT_2_5_MSPS) hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */ +#endif hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ @@ -470,7 +499,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) hadc->Lock = HAL_UNLOCKED; } - /* - Exit from deep-power-down mode and ADC voltage regulator enable */ + /* - Exit from deep power-down mode and ADC voltage regulator enable */ +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Feature "deep power-down" not available on ADC peripheral of this STM32WB device */ +#else if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) { /* Disable ADC deep power down mode */ @@ -480,6 +512,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } +#endif if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { @@ -525,6 +558,219 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Configuration of common ADC parameters */ + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Internal voltage regulator (no parameter in HAL ADC init structure) */ + /* - Clock configuration */ + /* - ADC resolution */ + /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ + /* and disable phases are performed automatically by hardware */ + /* (in this case, flag ADC_FLAG_RDY is not set). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + /* Configuration of ADC resolution */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_RES , + hadc->Init.Resolution ); + + /* Configuration of ADC: */ + /* - clock */ + /* - oversampling enable */ + /* - oversampling ratio */ + /* - oversampling shift */ + /* - oversampling discontinuous mode (triggered mode) */ + /* - trigger frequency mode */ + tmpCFGR2 |= ( (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + hadc->Init.TriggerFrequencyMode + ); + + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_CKMODE | + ADC_CFGR2_LFTRIG , + tmpCFGR2 ); + + /* Configuration of ADC clock mode: asynchronous clock source */ + /* with selectable prescaler. */ + if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4)) + { + MODIFY_REG(ADC1_COMMON->CCR , + ADC_CCR_PRESC , + hadc->Init.ClockPrescaler & ADC_CCR_PRESC ); + } + } + + /* Configuration of ADC: */ + /* - discontinuous mode */ + /* - LowPowerAutoWait mode */ + /* - LowPowerAutoPowerOff mode */ + /* - continuous conversion mode */ + /* - overrun */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + /* - data alignment */ + /* - resolution */ + /* - scan direction */ + /* - DMA continuous request */ + tmpCFGR |= (ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + ADC_CFGR_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | + ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); + + /* Update setting of discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + if (hadc->Init.ContinuousConvMode == DISABLE) + { + /* Enable the selected ADC group regular discontinuous mode */ + tmpCFGR |= ADC_CFGR1_DISCEN; + } + else + { + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | + hadc->Init.ExternalTrigConvEdge ); + } + + /* Update ADC configuration register with previous settings */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | + ADC_CFGR1_WAIT | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG , + tmpCFGR ); + + /* Channel sampling time configuration */ + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); + + /* Configuration of regular group sequencer: */ + /* - if scan mode is disabled, regular channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "NbrOfConversion" is discarded. */ + /* Note: Scan mode is not present by hardware on this device, but */ + /* emulated by software for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion". */ + /* Channels must be configured into each rank using function */ + /* "HAL_ADC_ConfigChannel()". */ + if(hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) + { + /* Set sequencer scan length by clearing ranks above rank 1 */ + /* and do not modify rank 1 value. */ + SET_BIT(hadc->Instance->CHSELR, + ADC_CHSELR_SQ2_TO_SQ8); + } + else if(hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + /* Count number of ranks available in HAL ADC handle variable */ + uint32_t ADCGroupRegularSequencerRanksCount; + + /* Parse all ranks from 1 to 8 */ + for(ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); ADCGroupRegularSequencerRanksCount++) + { + /* Check each sequencer rank until value of end of sequence */ + if(((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) == ADC_CHSELR_SQ1) + { + break; + } + } + + if(ADCGroupRegularSequencerRanksCount == 1UL) + { + /* Set ADC group regular sequencer: */ + /* Set sequencer scan length by clearing ranks above rank 1 */ + /* and do not modify rank 1 value. */ + SET_BIT(hadc->Instance->CHSELR, + ADC_CHSELR_SQ2_TO_SQ8); + } + else + { + /* Set ADC group regular sequencer: */ + /* - Set ADC group regular sequencer to value memorized */ + /* in HAL ADC handle */ + /* Note: This value maybe be initialized at a unknown value, */ + /* therefore afer the first call of "HAL_ADC_Init()", */ + /* each rank corresponding to parameter "NbrOfConversion" */ + /* must be set using "HAL_ADC_ConfigChannel()". */ + /* - Set sequencer scan length by clearing ranks above maximum rank */ + /* and do not modify other ranks value. */ + MODIFY_REG(hadc->Instance->CHSELR, + ADC_CHSELR_SQ_ALL, + (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks) + ); + } + } + + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core peripheral clocking. */ + /* Check through register CFGR1 (excluding analog watchdog configuration: */ + /* set into separate dedicated function, and bits of ADC resolution set */ + /* out of temporary variable 'tmpCFGR'). */ + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_RES)) + == tmpCFGR) + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + +#else /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ @@ -564,7 +810,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ - tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + tmpCFGR |= (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | hadc->Init.Overrun | hadc->Init.DataAlign | hadc->Init.Resolution | @@ -662,6 +908,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); +#endif /* ADC_SUPPORT_2_5_MSPS */ } else { @@ -710,8 +957,15 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going */ +#if defined (ADC_SUPPORT_2_5_MSPS) + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); +#else tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /* Disable ADC peripheral if conversions are effectively stopped */ /* Flush register JSQR: reset the queue sequencer when injected */ /* queue sequencer is enabled and ADC disabled. */ @@ -719,6 +973,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* internally disabled just after the completion of the last valid */ /* injected sequence. */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); +#endif /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) @@ -741,18 +996,69 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* system RCC hard reset. */ /* ========== Reset ADC registers ========== */ +#if defined (ADC_SUPPORT_2_5_MSPS) /* Reset register IER */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | - ADC_IT_JQOVF | ADC_IT_OVR | - ADC_IT_JEOS | ADC_IT_JEOC | + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | + ADC_IT_AWD1 | ADC_IT_OVR | ADC_IT_EOS | ADC_IT_EOC | - ADC_IT_EOSMP | ADC_IT_RDY)); + ADC_IT_EOSMP | ADC_IT_RDY ) ); /* Reset register ISR */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | - ADC_FLAG_JQOVF | ADC_FLAG_OVR | - ADC_FLAG_JEOS | ADC_FLAG_JEOC | + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | + ADC_FLAG_AWD1 | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC | + ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + + /* Reset register CFGR1 */ + hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | + ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ); + + /* Reset register CFGR2 */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; + + /* Reset register SMPR */ + hadc->Instance->SMPR &= ~ADC_SMPR_SMP1; + + /* Reset register TR1 */ + hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1); + + /* Reset register CHSELR */ + hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + +#else + /* Reset register IER */ + __HAL_ADC_DISABLE_IT(hadc, ( +#if defined (ADC_SUPPORT_2_5_MSPS) + ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | + ADC_IT_EOCAL | ADC_IT_CCRDY | +#else + ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | + ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_JQOVF | +#endif + ADC_IT_EOS | ADC_IT_EOC | ADC_IT_OVR | + ADC_IT_EOSMP | ADC_IT_RDY)); + + /* Reset register ISR */ + __HAL_ADC_CLEAR_FLAG(hadc, ( +#if defined (ADC_SUPPORT_2_5_MSPS) + ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | + ADC_FLAG_EOCAL | ADC_FLAG_CCRDY | +#else + ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | + ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_JQOVF | +#endif + ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_OVR | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); /* Reset register CR */ @@ -831,6 +1137,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Reset register CALFACT */ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* ========== Reset common ADC registers ========== */ @@ -876,9 +1183,14 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Reset HAL ADC handle variable */ + hadc->ADCGroupRegularSequencerRanks = 0x00000000UL; +#else /* Reset injected channel configuration parameters */ hadc->InjectionConfig.ContextQueue = 0; hadc->InjectionConfig.ChannelCount = 0; +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; @@ -1094,6 +1406,9 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca hadc->ErrorCallback = HAL_ADC_ErrorCallback; break; +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; break; @@ -1101,6 +1416,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; break; +#endif case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; @@ -1225,6 +1541,10 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) HAL_ADC_STATE_REG_BUSY); /* Set ADC error code */ +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); +#else /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { @@ -1236,6 +1556,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ @@ -1287,8 +1608,13 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) /* Process locked */ __HAL_LOCK(hadc); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* 1. Stop potential conversion on going, on ADC group regular */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); +#else /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) @@ -1300,9 +1626,15 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) if (tmp_hal_status == HAL_OK) { /* Set ADC state */ +#if defined (ADC_SUPPORT_2_5_MSPS) + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); +#else ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); +#endif /* ADC_SUPPORT_2_5_MSPS */ } } @@ -1353,7 +1685,11 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if(READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) != 0UL) +#else if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) +#endif { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -1420,7 +1756,11 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_WAIT) == 0UL) +#else if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY) == 0UL) +#endif { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } @@ -1440,7 +1780,9 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) * @arg @ref ADC_OVR_EVENT ADC Overrun event - * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event + * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. * Indeed, the latter is reset only if hadc->Init.Overrun field is set @@ -1531,6 +1873,9 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy break; +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /* Injected context queue overflow event */ case ADC_JQOVF_EVENT: /* Set ADC state */ @@ -1543,6 +1888,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); break; +#endif /* Overrun event */ default: /* Case ADC_OVR_EVENT */ @@ -1617,6 +1963,10 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) HAL_ADC_STATE_REG_BUSY); /* Set ADC error code */ +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); +#else /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { @@ -1628,6 +1978,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ @@ -1702,8 +2053,13 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) /* Process locked */ __HAL_LOCK(hadc); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* 1. Stop potential conversion on going, on ADC group regular */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); +#else /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) @@ -1719,9 +2075,15 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) if (tmp_hal_status == HAL_OK) { /* Set ADC state */ +#if defined (ADC_SUPPORT_2_5_MSPS) + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); +#else ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); +#endif /* ADC_SUPPORT_2_5_MSPS */ } } @@ -1768,6 +2130,10 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); +#else /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { @@ -1779,6 +2145,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; @@ -1809,7 +2176,11 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable ADC DMA mode */ +#if defined (ADC_SUPPORT_2_5_MSPS) + SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); +#else SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); +#endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); @@ -1857,13 +2228,21 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) __HAL_LOCK(hadc); /* 1. Stop potential ADC group regular conversion on going */ +#if defined (ADC_SUPPORT_2_5_MSPS) + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); +#else tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ +#if defined (ADC_SUPPORT_2_5_MSPS) + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); +#else CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); +#endif /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ @@ -1898,9 +2277,15 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) if (tmp_hal_status == HAL_OK) { /* Set ADC state */ +#if defined (ADC_SUPPORT_2_5_MSPS) + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); +#else ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); +#endif /* ADC_SUPPORT_2_5_MSPS */ } } @@ -1953,9 +2338,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ uint32_t tmp_isr = hadc->Instance->ISR; uint32_t tmp_ier = hadc->Instance->IER; +#if !defined (ADC_SUPPORT_2_5_MSPS) uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1999,7 +2386,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Carry on if continuous mode is disabled */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if (READ_BIT (hadc->Instance->CFGR1, ADC_CFGR1_CONT) != ADC_CFGR1_CONT) +#else if (READ_BIT (hadc->Instance->CFGR, ADC_CFGR_CONT) != ADC_CFGR_CONT) +#endif { /* If End of Sequence is reached, disable interrupts */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) @@ -2053,6 +2444,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) @@ -2074,44 +2468,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) + if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) { - /* Particular case if injected contexts queue is enabled: */ - /* when the last context has been fully processed, JSQR is reset */ - /* by the hardware. Even if no injected conversion is planned to come */ - /* (queue empty, triggers are ignored), it can start again */ - /* immediately after setting a new context (JADSTART is still set). */ - /* Therefore, state of HAL ADC injected group is kept to busy. */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL) + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { - /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ - /* JADSTART==0 (no conversion on going) */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL) { - /* Disable ADC end of sequence conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); + /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ + /* JADSTART==0 (no conversion on going) */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of sequence conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } } } } @@ -2132,6 +2528,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /* ========== Check Analog watchdog 1 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) @@ -2230,6 +2627,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /* ========== Check Injected context queue overflow flag ========== */ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) { @@ -2249,6 +2649,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) HAL_ADCEx_InjectedQueueOverflowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } +#endif /* ADC_SUPPORT_2_5_MSPS */ } @@ -2357,12 +2758,190 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { +#if defined (ADC_SUPPORT_2_5_MSPS) + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_config_internal_channel; + __IO uint32_t wait_loop_index = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); + assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime)); + + if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) ) + { + assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank)); + } + else + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Channel sampling time */ + /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Configure channel: depending on rank setting, add it or remove it from */ + /* ADC sequencer. */ + /* If sequencer set to not fully configurable with channel rank set to */ + /* none, remove the channel from the sequencer. */ + /* Otherwise (sequencer set to fully configurable or to to not fully */ + /* configurable with channel rank to be set), configure the selected */ + /* channel. */ + if(sConfig->Rank != ADC_RANK_NONE) + { + /* Regular sequence configuration */ + /* Note: ADC channel configuration requires few ADC clock cycles */ + /* to be ready. Processing of ADC settings in this function */ + /* induce that a specific wait time is not necessary. */ + /* For more details on ADC channel configuration ready, */ + /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */ + if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) ) + { + /* Sequencer set to not fully configurable: */ + /* Set the channel by enabling the corresponding bitfield. */ + LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel); + } + else + { + /* Sequencer set to fully configurable: */ + /* Set the channel by entering it into the selected rank. */ + + /* Memorize the channel set into variable in HAL ADC handle */ + MODIFY_REG(hadc->ADCGroupRegularSequencerRanks, + ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL), + __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL)); + + /* If the selected rank is below ADC group regular sequencer length, */ + /* apply the configuration in ADC register. */ + /* Note: Otherwise, configuration is not applied. */ + /* To apply it, parameter'NbrOfConversion' must be increased. */ + if(((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) + { + LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + } + } + + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + + /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit() or removing the channel from sequencer with */ + /* channel configuration parameter "Rank". */ + if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + while(wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); + } + else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); + } + else + { + /* nothing to do */ + } + } + } + else + { + /* Regular sequencer configuration */ + /* Note: Case of sequencer set to fully configurable: */ + /* Sequencer rank cannot be disabled, only affected to */ + /* another channel. */ + /* To remove a rank, use parameter 'NbrOfConversion". */ + if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) ) + { + /* Sequencer set to not fully configurable: */ + /* Reset the channel by disabling the corresponding bitfield. */ + LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel); + } + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ + /* If internal channel selected, enable dedicated internal buffers and */ + /* paths. */ + if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel); + } + else if (sConfig->Channel == ADC_CHANNEL_VBAT) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel); + } + else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel); + } + else + { + /* nothing to do */ + } + } + } + } + + /* If a conversion is on going on regular group, no update on regular */ + /* channel could be done on neither of the channel configuration structure */ + /* parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + +#else HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; +#if !defined (ADC_SUPPORT_2_5_MSPS) uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2404,11 +2983,15 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) +#else tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) +#endif /* ADC_SUPPORT_2_5_MSPS */ { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); @@ -2549,6 +3132,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Process unlocked */ __HAL_UNLOCK(hadc); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Return function status */ return tmp_hal_status; @@ -2575,8 +3159,10 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpAWDHighThresholdShifted; uint32_t tmpAWDLowThresholdShifted; +#if !defined (ADC_SUPPORT_2_5_MSPS) uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2584,14 +3170,23 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); +#if defined (ADC_SUPPORT_2_5_MSPS) + if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) +#else if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) +#endif { assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel)); } /* Verify thresholds range */ +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Verify if thresholds are within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); +#else if (hadc->Init.OversamplingMode == ENABLE) { /* Case of oversampling enabled: depending on ratio and shift configuration, @@ -2606,6 +3201,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); } +#endif /* Process locked */ __HAL_LOCK(hadc); @@ -2615,11 +3211,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* conversion on going on ADC groups regular and injected: */ /* - Analog watchdog channels */ /* - Analog watchdog thresholds */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) +#else tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) +#endif /* ADC_SUPPORT_2_5_MSPS */ { /* Analog watchdog configuration */ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) @@ -2634,6 +3234,9 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_GROUP_REGULAR)); break; +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else case ADC_ANALOGWATCHDOG_SINGLE_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); @@ -2643,11 +3246,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); break; +#endif /* ADC_SUPPORT_2_5_MSPS */ case ADC_ANALOGWATCHDOG_ALL_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); break; +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else case ADC_ANALOGWATCHDOG_ALL_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); break; @@ -2655,6 +3262,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; +#endif /* ADC_SUPPORT_2_5_MSPS */ default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); @@ -2689,14 +3297,19 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_DisableIT_AWD1(hadc->Instance); } } +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */ +#else /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: +#if !defined (ADC_SUPPORT_2_5_MSPS) case ADC_ANALOGWATCHDOG_SINGLE_INJEC: case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: +#endif /* Update AWD by bitfield to keep the possibility to monitor */ /* several channels by successive calls of this function. */ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) @@ -2710,9 +3323,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG break; case ADC_ANALOGWATCHDOG_ALL_REG: +#if !defined (ADC_SUPPORT_2_5_MSPS) case ADC_ANALOGWATCHDOG_ALL_INJEC: case ADC_ANALOGWATCHDOG_ALL_REGINJEC: +#endif +#if defined (ADC_SUPPORT_2_5_MSPS) + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); +#else LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); +#endif break; default: /* ADC_ANALOGWATCHDOG_NONE */ @@ -2772,6 +3391,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG } } } +#endif /* ADC_SUPPORT_2_5_MSPS */ } /* If a conversion is on going on ADC group regular or injected, no update */ @@ -2861,13 +3481,55 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @param ConversionGroup ADC group regular and/or injected. * This parameter can be one of the following values: - * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. - * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. - * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. + * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. + * @arg @ref ADC_INJECTED_GROUP (1) ADC injected conversion type. + * @arg @ref ADC_REGULAR_INJECTED_GROUP (1) ADC regular and injected conversion type. + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) { +#if defined (ADC_SUPPORT_2_5_MSPS) + UNUSED(ConversionGroup); + + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Verification if ADC is not already stopped on regular group to bypass */ + /* this function if not needed. */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) + { + /* Stop potential conversion on going on regular group */ + /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group regular conversion */ + LL_ADC_REG_StopConversion(hadc->Instance); + } + + /* Wait for conversion effectively stopped */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) + { + if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + + } +#else uint32_t tickstart; uint32_t Conversion_Timeout_CPU_cycles = 0UL; uint32_t conversion_group_reassigned = ConversionGroup; @@ -2982,6 +3644,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio } } +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Return HAL status */ return HAL_OK; @@ -2999,6 +3662,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; + __IO uint32_t wait_loop_index = 0UL; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ @@ -3007,7 +3671,11 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Check if conditions to enable the ADC are fulfilled */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) +#else if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) +#endif { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -3021,33 +3689,54 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); - /* Wait for ADC effectively enabled */ - tickstart = HAL_GetTick(); - - while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - { - /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit - has been cleared (after a calibration), ADEN bit is reset by the - calibration logic. - The workaround is to continue setting ADEN until ADRDY is becomes 1. - Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this - 4 ADC clock cycle duration */ - /* Note: Test of ADC enabled required due to hardware constraint to */ - /* not enable ADC if already enabled. */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + if((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) + { + /* Delay for temperature sensor buffer stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + while(wait_loop_index != 0UL) { - LL_ADC_Enable(hadc->Instance); + wait_loop_index--; } + } + +#if defined (ADC_SUPPORT_2_5_MSPS) + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware and flag ADC ready is not set. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) +#endif /*ADC_SUPPORT_2_5_MSPS */ + { + /* Wait for ADC effectively enabled */ + tickstart = HAL_GetTick(); - if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the + calibration logic. + The workaround is to continue setting ADEN until ADRDY is becomes 1. + Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this + 4 ADC clock cycle duration */ + /* Note: Test of ADC enabled required due to hardware constraint to */ + /* not enable ADC if already enabled. */ + if(LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_Enable(hadc->Instance); + } - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - return HAL_ERROR; + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } } } } @@ -3076,7 +3765,11 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) ) { /* Check if conditions to disable the ADC are fulfilled */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) +#else if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) +#endif { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); @@ -3136,6 +3829,41 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if( (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + +#else if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) { /* Are conversions software-triggered ? */ @@ -3167,6 +3895,7 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) } } } +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c index 1327585..f29db42 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c @@ -3,18 +3,18 @@ * @file stm32wbxx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) + * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Operation functions * ++ Start, stop, get result of conversions of ADC group injected, - * using 2 possible modes: polling, interruption. + * using 2 possible modes: polling, interruption (not available on devices: STM32WB10xx, STM32WB15xx). * ++ Calibration * +++ ADC automatic self-calibration * +++ Calibration factors get or set * + Control functions - * ++ Channels configuration on ADC group injected + * ++ Channels configuration on ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx) * + State functions - * ++ ADC group injected contexts queue management + * ++ ADC group injected contexts queue management (not available on devices: STM32WB10xx, STM32WB15xx) * Other functions (generic functions) are available in file * "stm32wbxx_hal_adc.c". * @@ -99,12 +99,12 @@ (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. - (+) Start conversion of ADC group injected. - (+) Stop conversion of ADC group injected. - (+) Poll for conversion complete on ADC group injected. - (+) Get result of ADC group injected channel conversion. - (+) Start conversion of ADC group injected and enable interruptions. - (+) Stop conversion of ADC group injected and disable interruptions. + (+) Start conversion of ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx). + (+) Stop conversion of ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx). + (+) Poll for conversion complete on ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx). + (+) Get result of ADC group injected channel conversion (not available on devices: STM32WB10xx, STM32WB15xx). + (+) Start conversion of ADC group injected and enable interruptions (not available on devices: STM32WB10xx, STM32WB15xx). + (+) Stop conversion of ADC group injected and disable interruptions (not available on devices: STM32WB10xx, STM32WB15xx). @endverbatim * @{ @@ -118,11 +118,17 @@ * @param SingleDiff Selection of single-ended or differential input * This parameter can be one of the following values: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { +#if defined (ADC_SUPPORT_2_5_MSPS) + UNUSED(SingleDiff); +#endif + HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; @@ -142,12 +148,22 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t if (tmp_hal_status == HAL_OK) { /* Set ADC state */ +#if defined (ADC_SUPPORT_2_5_MSPS) + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); +#else ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Start ADC calibration in mode single-ended or differential */ +#if defined (ADC_SUPPORT_2_5_MSPS) + LL_ADC_StartCalibration(hadc->Instance); +#else LL_ADC_StartCalibration(hadc->Instance, SingleDiff); +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) @@ -192,17 +208,27 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t * @param hadc ADC handle. * @param SingleDiff This parameter can be only: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @retval Calibration value. */ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { +#if defined (ADC_SUPPORT_2_5_MSPS) + UNUSED(SingleDiff); +#endif + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Return the selected ADC calibration value */ +#if defined (ADC_SUPPORT_2_5_MSPS) + return LL_ADC_GetCalibrationFactor(hadc->Instance); +#else return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); +#endif } /** @@ -211,15 +237,25 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t Single * @param hadc ADC handle * @param SingleDiff This parameter can be only: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1) + * + * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { +#if defined (ADC_SUPPORT_2_5_MSPS) + UNUSED(SingleDiff); +#endif + HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_adc_is_conversion_on_going_regular; +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else uint32_t tmp_adc_is_conversion_on_going_injected; +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -232,15 +268,27 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); +#endif /* ADC_SUPPORT_2_5_MSPS */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_conversion_on_going_regular == 0UL) +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else && (tmp_adc_is_conversion_on_going_injected == 0UL) +#endif /* ADC_SUPPORT_2_5_MSPS */ ) { /* Set the selected ADC calibration value */ +#if defined (ADC_SUPPORT_2_5_MSPS) + LL_ADC_SetCalibrationFactor(hadc->Instance, CalibrationFactor); +#else LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor); +#endif } else { @@ -260,6 +308,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 return tmp_hal_status; } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Enable ADC, start conversion of injected group. * @note Interruptions enabled in this function: None. @@ -705,7 +756,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) /* Return function status */ return tmp_hal_status; } +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC @@ -797,6 +852,7 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Analog watchdog 2 callback in non-blocking mode. @@ -844,6 +900,9 @@ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) */ } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral if no @@ -1038,11 +1097,15 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) /* Return function status */ return tmp_hal_status; } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @} */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions * @brief ADC Extended Peripheral Control functions * @@ -1506,7 +1569,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Return function status */ return tmp_hal_status; } +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Enable Injected Queue * @note This function resets CFGR register JQDIS bit in order to enable the @@ -1584,6 +1651,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) return tmp_hal_status; } +#endif /* ADC_SUPPORT_2_5_MSPS */ /** * @brief Disable ADC voltage regulator. @@ -1615,8 +1683,11 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) return tmp_hal_status; } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */ +#else /** - * @brief Enter ADC deep-power-down mode + * @brief Enter ADC deep power-down mode * @note This mode is achieved in setting DEEPPWD bit and allows to save power * in reducing leakage currents. It is particularly interesting before * entering stop modes. @@ -1651,6 +1722,7 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) return tmp_hal_status; } +#endif /** * @} diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c index a113b0d..be27bc5 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c @@ -18,7 +18,10 @@ [..] The STM32WBxx device family integrates two analog comparators instances: - COMP1, COMP2. + COMP1, COMP2 except for the STM32WB15xx, STM32WB10xx products featuring only + one instance: COMP1. + In the rest of the file, all comments related to a pair of comparators are not + applicable to STM32WB15xx, STM32WB10xx. (#) Comparators input minus (inverting input) and input plus (non inverting input) can be set to internal references or to GPIO pins (refer to GPIO list in reference manual). @@ -91,11 +94,11 @@ The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_COMP_RegisterCallback() + Use Functions HAL_COMP_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks: + Function HAL_COMP_RegisterCallback() allows to register following callbacks: (+) TriggerCallback : callback for COMP trigger. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. @@ -103,11 +106,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default + Use function HAL_COMP_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TriggerCallback : callback for COMP trigger. @@ -115,27 +118,27 @@ (+) MspDeInitCallback : callback for Msp DeInit. [..] - By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET + By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET all callbacks are set to the corresponding weak functions: - example @ref HAL_COMP_TriggerCallback(). + example HAL_COMP_TriggerCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when + reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() + If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state, + in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit() - or @ref HAL_COMP_Init() function. + using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit() + or HAL_COMP_Init() function. [..] When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or @@ -258,7 +261,9 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); +#if defined(COMP2) assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); +#endif if(hcomp->State == HAL_COMP_STATE_RESET) { @@ -306,13 +311,23 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Set parameters in COMP register */ /* Note: Update all bits except read-only, lock and enable bits */ +#if defined (COMP_CSR_WINMODE) MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST | COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, tmp_csr ); +#else + MODIFY_REG(hcomp->Instance->CSR, + COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | + COMP_CSR_POLARITY | COMP_CSR_HYST | + COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, + tmp_csr + ); +#endif +#if defined(COMP2) /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ @@ -325,6 +340,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE); } +#endif /* COMP2 */ /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is required and not already enabled */ @@ -779,6 +795,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) /* Check COMP EXTI flag */ if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) { +#if defined(COMP2) /* Check whether comparator is in independent or window mode */ if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL) { @@ -792,6 +809,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) LL_EXTI_ClearFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); } else +#endif /* COMP2 */ { /* Clear COMP EXTI line pending bit */ LL_EXTI_ClearFlag_0_31(exti_line); diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c index 1e8fe2c..7018678 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c @@ -6,7 +6,7 @@ * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: * + Initialization, de-initialization, set config and get config functions - * + DES/TDES, AES processing functions + * + AES processing functions * + DMA callback functions * + CRYP IRQ handler management * + Peripheral State functions @@ -32,8 +32,8 @@ (+++) Associate the initialized DMA handle to the CRYP DMA handle using __HAL_LINKDMA() (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() + interrupt on the two DMA channels. The output channel should have higher + priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). (#)Initialize the CRYP according to the specified parameters : (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit. @@ -44,9 +44,13 @@ (+++) In some specific configurations, the key is written by the application code out of the HAL scope. In that case, user can still resort to the HAL APIs as usual but must make sure that pKey pointer is set to NULL. + (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication + algorithms) is in words or bytes. (##) The Header used only in AES GCM and CCM Algorithm for authentication. - (##) The HeaderSize The size of header buffer in word. - (##) The B0 block is the first authentication block used only in AES CCM mode. + (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field. + (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes. + (##) The B0 block is the first authentication block used only in AES CCM mode. + (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below). (#)Three processing (encryption/decryption) functions are available: (##) Polling mode: encryption and decryption APIs are blocking functions @@ -194,11 +198,11 @@ [..] The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() + Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() to register an interrupt callback. [..] - Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + Function HAL_CRYP_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. (+) OutCpltCallback : Output FIFO transfer completed callback. (+) ErrorCallback : callback for error detection. @@ -208,9 +212,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. @@ -220,13 +224,13 @@ (+) MspDeInitCallback : CRYP MspDeInit. [..] - By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET + By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET all callbacks are set to the corresponding weak functions : - examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). + examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when + reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) [..] @@ -235,8 +239,8 @@ in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() - or @ref HAL_CRYP_Init() function. + using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit() + or HAL_CRYP_Init() function. [..] When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or @@ -321,6 +325,7 @@ #define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */ #define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */ #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */ #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */ #define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */ @@ -345,9 +350,7 @@ * @{ */ -#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\ - (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\ - }while(0U) +#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__)) /** * @} @@ -361,6 +364,7 @@ */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); +static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size); static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAError(DMA_HandleTypeDef *hdma); @@ -370,6 +374,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); @@ -383,6 +388,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); @@ -418,13 +424,13 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); (+) DeInitialize the CRYP MSP (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef Parameters which are configured in This section are : - (+) Key size - (+) Data Type : 32,16, 8 or 1bit - (+) AlgoMode : - - for CRYP1 peripheral : + (++) Key size + (++) Data Type : 32,16, 8 or 1bit + (++) AlgoMode : + (+++) for CRYP1 peripheral : ECB and CBC in DES/TDES Standard ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. - - for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. + (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef @endverbatim @@ -1185,7 +1191,7 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (plaintext) - * @param Size Length of the plaintext buffer in word. + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(ciphertext) * @param Timeout Specify Timeout value * @retval HAL status @@ -1285,7 +1291,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (ciphertext ) - * @param Size Length of the plaintext buffer in word. + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(plaintext) * @param Timeout Specify Timeout value * @retval HAL status @@ -1385,7 +1391,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (plaintext) - * @param Size Length of the plaintext buffer in word + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(ciphertext) * @retval HAL status */ @@ -1495,7 +1501,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (ciphertext ) - * @param Size Length of the plaintext buffer in word. + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(plaintext) * @retval HAL status */ @@ -1604,7 +1610,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (plaintext) - * @param Size Length of the plaintext buffer in word. + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(ciphertext) * @retval HAL status */ @@ -1731,7 +1737,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (ciphertext ) - * @param Size Length of the plaintext buffer in word + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(plaintext) * @retval HAL status */ @@ -1869,7 +1875,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) { /* if header phase */ @@ -1882,18 +1888,6 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); } } - else if (hcryp->Init.Algorithm == CRYP_AES_CCM) - { - /* if header phase */ - if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount) - { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); - } - else /* if payload phase */ - { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); - } - } else /* AES Algorithm ECB,CBC or CTR*/ { CRYP_AES_IT(hcryp); @@ -2502,10 +2496,81 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) + { + /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if ((headersize_in_bytes % 16U) != 0U) + { + /* Write last words that couldn't be fed by DMA */ + hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U); + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + + /* Wait for computation completion before moving forward */ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + } /* if ((headersize_in_bytes % 16U) != 0U) */ + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Initiate payload DMA IN and processed data DMA OUT transfers */ + (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp); + } + /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /*Call registered Input complete callback*/ @@ -2526,7 +2591,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t count; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t mode; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -2579,44 +2644,21 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) } /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); /*Read the output block from the output FIFO */ for (count = 0U; count < 4U; count++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; + temp[count] = hcryp->Instance->DOUTR; + } - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + count = 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; hcryp->CrypOutCount++; + count++; } } @@ -2675,7 +2717,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param inputaddr address of the input buffer - * @param Size size of the input buffer, must be a multiple of 16. + * @param Size size of the input and output buffers in words, must be a multiple of 4 * @param outputaddr address of the output buffer * @retval None */ @@ -2733,6 +2775,43 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); } +/** + * @brief Set the DMA configuration and start the header DMA transfer + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param inputaddr address of the input buffer + * @param Size size of the input buffer in words, must be a multiple of 4 + * @retval None + */ +static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size) +{ + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; + + /* Set the DMA input error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_DMAError; + + /* Mark that header is fed to the peripheral in DMA mode */ + hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED; + /* Enable the DMA input stream */ + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK) + { + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + /* Call error callback */ + } + + /* Enable IN DMA requests */ + SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + + return HAL_OK; +} + /** * @brief Process Data: Write Input data in polling mode and used in AES functions. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -2743,7 +2822,8 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); @@ -2780,19 +2860,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i= 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } } /** @@ -2805,24 +2883,23 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; if (hcryp->State == HAL_CRYP_STATE_BUSY) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i= 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } if (hcryp->CrypOutCount == (hcryp->Size / 4U)) { /* Disable Computation Complete flag and errors interrupts */ @@ -2959,7 +3036,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t tickstart; uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ; uint32_t npblb; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t index; uint32_t lastwordsize; uint32_t incount; /* Temporary CrypInCount Value */ @@ -3138,9 +3215,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t for (index = 0U; index < 4U; index++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; - - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; hcryp->CrypOutCount++; } } @@ -3162,6 +3241,12 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t lastwordsize; uint32_t npblb; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -3171,6 +3256,17 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) } #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + /* Manage header size given in bytes to handle cases where + header size is not a multiple of 4 bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -3337,27 +3433,43 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) } } } - else if ((hcryp->Init.HeaderSize) < 4U) + /* Enter header data */ + /* Cher first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) { - for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) + /* Write header data, padded with zeros if need be */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++ ; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; + hcryp->CrypHeaderCount++; + } } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3370,7 +3482,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) } else { - /* Write the input block in the IN FIFO */ + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -3482,12 +3595,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count; - uint16_t wordsize = hcryp->Size / 4U ; - uint32_t index; - uint32_t npblb; - uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t count; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -3566,167 +3674,63 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) return HAL_ERROR; } - /************************ Payload phase ************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - } /* if (DoKeyIVConfig == 1U) */ - - if (hcryp->Size == 0U) - { - /* Process unLocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - else if (hcryp->Size >= 16U) - { - /*DMA transfer must not include the last block in case of Size is not %16 */ - wordsize = wordsize - (wordsize % 4U); - - /*DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); } - else /* length of input data is < 16 */ + else { - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U - (uint32_t)hcryp->Size; - - /* Set Npblb in case of AES GCM payload encryption to get right tag*/ - if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + /* Initialization and header phases already done, only do payload phase */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) { - /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + return HAL_ERROR; } + } /* if (DoKeyIVConfig == 1U) */ - /* Enable CRYP to start the final phase */ - __HAL_CRYP_ENABLE(hcryp); + /* Return function status */ + return HAL_OK; +} - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) + +/** + * @brief AES CCM encryption/decryption processing in polling mode + * for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ; + uint32_t loopcounter; + uint32_t npblb; + uint32_t lastwordsize; + uint32_t temp[4] ; /* Temporary CrypOutBuff */ + uint32_t incount; /* Temporary CrypInCount Value */ + uint32_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) { - lastwordsize = (16U - npblb) / 4U; + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ } else { - lastwordsize = ((16U - npblb) / 4U) + 1U; + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ } - - /* last block optionally pad the data with zeros*/ - for (index = 0U; index < lastwordsize; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - index++; - } - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /*Read the output block from the output FIFO */ - for (index = 0U; index < 4U; index++) - { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; - - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - } - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief AES CCM encryption/decryption processing in polling mode - * for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation. - * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ; - uint32_t loopcounter; - uint32_t npblb; - uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ - uint32_t incount; /* Temporary CrypInCount Value */ - uint32_t outcount; /* Temporary CrypOutCount Value */ - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ - } - } - else - { - hcryp->SizesSum = hcryp->Size; - } + } + else + { + hcryp->SizesSum = hcryp->Size; + } if (DoKeyIVConfig == 1U) { @@ -3872,9 +3876,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t for (loopcounter = 0U; loopcounter < 4U; loopcounter++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; - - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + temp[loopcounter] = hcryp->Instance->DOUTR; + } + for (loopcounter = 0U; loopcounterpCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; hcryp->CrypOutCount++; } } @@ -4192,12 +4198,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count = 0U; - uint16_t wordsize = hcryp->Size / 4U ; - uint32_t index; - uint32_t npblb; - uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t count; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -4278,116 +4279,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) return HAL_ERROR; } - /******************** Payload phase *****************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - - } /* if (DoKeyIVConfig == 1U) */ - - if (hcryp->Size == 0U) - { - /* Process unLocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - else if (hcryp->Size >= 16U) - { - /*DMA transfer must not include the last block in case of Size is not %16 */ - wordsize = wordsize - (wordsize % 4U); - - /*DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); } - else /* length of input data is < 16 */ + else { - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U - (uint32_t)hcryp->Size; - - /* Set Npblb in case of AES CCM payload decryption to get right tag*/ - if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) - { - /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); - } - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* last block optionally pad the data with zeros*/ - for (index = 0U; index < lastwordsize; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - index++; - } - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /*Read the output block from the output FIFO */ - for (index = 0U; index < 4U; index++) + /* Initialization and header phases already done, only do payload phase */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; - - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; + return HAL_ERROR; } - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } + } /* if (DoKeyIVConfig == 1U) */ /* Return function status */ return HAL_OK; @@ -4402,29 +4302,28 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; uint32_t mode; uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t i; /***************************** Payload phase *******************************/ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i= 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } incount = hcryp->CrypInCount; outcount = hcryp->CrypOutCount; if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) @@ -4541,42 +4440,172 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /** - * @brief Sets the header phase in polling mode + * @brief Sets the payload phase in DMA mode * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module(Header & HeaderSize) - * @param Timeout Timeout value + * the configuration information for CRYP module * @retval state */ -static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp) { - uint32_t loopcounter; + uint16_t wordsize = hcryp->Size / 4U ; + uint32_t index; + uint32_t npblb; + uint32_t lastwordsize; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t count; + uint32_t reg; - /***************************** Header phase for GCM/GMAC or CCM *********************************/ + /************************ Payload phase ************************************/ + if (hcryp->Size == 0U) + { + /* Process unLocked */ + __HAL_UNLOCK(hcryp); - if ((hcryp->Init.HeaderSize != 0U)) + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } + else if (hcryp->Size >= 16U) { - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /*DMA transfer must not include the last block in case of Size is not %16 */ + wordsize = wordsize - (wordsize % 4U); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /*DMA transfer */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else /* length of input data is < 16 */ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; - if ((hcryp->Init.HeaderSize % 4U) == 0U) + /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/ + reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE); + if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\ + (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT))) { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (index = 0U; index < lastwordsize; index ++) + { + /* Write the last Input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (index < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0U; + index++; + } + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + hcryp->CrypOutCount++; + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + + return HAL_OK; +} + +/** + * @brief Sets the header phase in polling mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @param Timeout Timeout value + * @retval state + */ +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t loopcounter; + uint32_t size_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + + /***************************** Header phase for GCM/GMAC or CCM *********************************/ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + size_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + size_in_bytes = hcryp->Init.HeaderSize; + } + + if ((size_in_bytes != 0U)) + { + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */ + if ((size_in_bytes % 16U) == 0U) + { + /* No padding */ + for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U) + { + /* Write the input block in the data input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4595,8 +4624,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + /* Write header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U) { /* Write the input block in the data input register */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -4624,17 +4653,35 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((size_in_bytes % 4U) == 0U) { - /*Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) @@ -4656,17 +4703,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); } /* Return function status */ return HAL_OK; @@ -4680,143 +4724,112 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u */ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count = 0U; uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if ((hcryp->Init.HeaderSize != 0U)) + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - if ((hcryp->Init.HeaderSize % 4U) == 0U) - { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } + /* If header size is at least equal to 16 bytes, feed the header through DMA. + If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ), + last bytes feeding and padding will be done in CRYP_DMAInCplt() */ + if (headersize_in_bytes >= 16U) + { + /* Initiate header DMA transfer */ + if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) + { + return HAL_ERROR; } - else + } + else + { + if (headersize_in_bytes != 0U) { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + /* Header length is larger than 0 and strictly less than 16 bytes */ + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) { - /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } - while (loopcounter < 4U) + else { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do + if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK) { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } /* if (headersize_in_bytes != 0U) */ + + /* Move to payload phase if header length is null or + if the header length was less than 16 and header written by software instead of DMA */ + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Initiate payload DMA IN and processed data DMA OUT transfers */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; } - } - else - { - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + } /* if (headersize_in_bytes >= 16U) */ - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } /* Return function status */ return HAL_OK; } @@ -4833,9 +4846,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t lastwordsize; uint32_t npblb; uint32_t mode; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } /***************************** Header phase *********************************/ - if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + /* Test whether or not the header phase is over. + If the test below is true, move to payload phase */ + if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -4920,9 +4949,9 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) } } } - else if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) + else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) { - + /* Can enter full 4 header words */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) /* If suspension flag has been raised, suspend processing only if not already at the end of the header */ @@ -4957,19 +4986,40 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; } } - else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ + else /* Write last header block (4 words), padded with zeros if needed */ { - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; + hcryp->CrypHeaderCount++; + } } } } @@ -4979,6 +5029,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @param Timeout Timeout duration. + * @note This function can only be used in thread mode. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5002,6 +5053,47 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T return HAL_OK; } +/** + * @brief Wait for Computation Complete Flag (CCF) to raise then clear it. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout Timeout duration. + * @note This function can be used in thread or handler mode. + * @retval HAL status + */ +static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t count = Timeout; + + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + hcryp->State = HAL_CRYP_STATE_READY; + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); +} #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) /** diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c index e320e5e..963a39c 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c @@ -99,10 +99,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) { uint32_t tickstart; + /* Assume first Init.HeaderSize is in words */ uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */ - uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */ + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; + /* Correct headerlength if Init.HeaderSize is actually in bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) + { + headerlength /= 4U; + } + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Process locked */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c index c1ed560..95c4fae 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c @@ -727,6 +727,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)); + /* Process unlocked */ + __HAL_UNLOCK(hdma); + /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; @@ -737,9 +740,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)); } - /* Process unlocked */ - __HAL_UNLOCK(hdma); - return HAL_OK; } @@ -1075,7 +1075,9 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) #endif channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; - hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); + + /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); } /** diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c index ce93882..e7c9a5c 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c @@ -607,6 +607,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32 * @arg @ref OB_STOP_RST or @ref OB_STOP_NORST * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST + * @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*) * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW * @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN * @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN @@ -616,6 +617,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32 * @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE * @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN * @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET + * @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*) * @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7 * @param RDPLevel: specifies the read protection level. * This parameter can be one of the following values: @@ -768,21 +770,35 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam) MODIFY_REG(sfr_reg_val, FLASH_SFR_SFSA, (((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_SFSA_Pos)); /* Configure SRRVR register */ +#if defined(FLASH_SRRVR_SBRSA_A) + MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA_A | FLASH_SRRVR_SBRSA_B), \ + (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_A_Pos)) | \ + ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_B_Pos)))); +#else MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \ (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \ ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos)))); +#endif /* If Full System Secure mode is requested, clear all the corresponding bit */ /* Else set the corresponding bit */ if (pOBParam->SecureMode == SYSTEM_IN_SECURE_MODE) { CLEAR_BIT(sfr_reg_val, FLASH_SFR_FSD); +#if defined(FLASH_SRRVR_BRSD_A) + CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B)); +#else CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD)); +#endif } else { SET_BIT(sfr_reg_val, FLASH_SFR_FSD); +#if defined(FLASH_SRRVR_BRSD_A) + SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B)); +#else SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD)); +#endif } /* Update Flash registers */ @@ -870,6 +886,7 @@ static uint32_t FLASH_OB_GetRDP(void) * @arg @ref OB_STOP_RST or @ref OB_STOP_RST * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST + * @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*) * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW * @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN * @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN @@ -879,6 +896,7 @@ static uint32_t FLASH_OB_GetRDP(void) * @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE * @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN * @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET + * @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*) * @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7 */ static uint32_t FLASH_OB_GetUser(void) @@ -952,12 +970,20 @@ static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint3 *SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE); /* Get Secure SRAM2a start address */ +#if defined(FLASH_SRRVR_SBRSA_A) + user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_A) >> FLASH_SRRVR_SBRSA_A_Pos); +#else user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos); +#endif *SecureRAM2aStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2A_BASE); /* Get Secure SRAM2b start address */ +#if defined(FLASH_SRRVR_SBRSA_B) + user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_B) >> FLASH_SRRVR_SBRSA_B_Pos); +#else user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos); +#endif *SecureRAM2bStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2B_BASE); diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c index ba71ef5..3cbd0fd 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c @@ -428,17 +428,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { + uint32_t odr; + /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) != 0x00u) - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } + /* get current Ouput Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c index 436dda9..2847d60 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c @@ -101,6 +101,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #if defined(DUAL_CORE) +/** @defgroup HSEM_Private_Constants HSEM Private Constants + * @{ + */ + #ifndef HSEM_R_MASTERID #define HSEM_R_MASTERID HSEM_R_COREID #endif @@ -112,6 +116,10 @@ #ifndef HSEM_CR_MASTERID #define HSEM_CR_MASTERID HSEM_CR_COREID #endif + +/** + * @} + */ #endif /* DUAL_CORE */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c index c047cd0..6e9af79 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c @@ -93,7 +93,7 @@ [..] (+) A specific option field manage the different steps of a sequential transfer (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address @@ -112,7 +112,7 @@ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential interface. @@ -122,7 +122,7 @@ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. - (+) Differents sequential I2C interfaces are listed below: + (+) Different sequential I2C interfaces are listed below: (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can @@ -3203,7 +3203,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3288,7 +3288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3449,7 +3449,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3534,7 +3534,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -4835,7 +4835,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ + /* Check if all data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { @@ -5719,7 +5719,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ I2C_ITSlaveSeqCplt(hi2c); hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -5856,7 +5856,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - /* If state is an abort treatment on goind, don't change state */ + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { @@ -6570,7 +6570,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) } /** - * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. * @param hi2c I2C handle. * @retval None */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c deleted file mode 100644 index 22a0782..0000000 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c +++ /dev/null @@ -1,1802 +0,0 @@ -/** - ****************************************************************************** - * @file stm32wbxx_hal_i2s.c - * @author MCD Application Team - * @brief I2S HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Integrated Interchip Sound (I2S) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The I2S HAL driver can be used as follow: - - (#) Declare a I2S_HandleTypeDef handle structure. - (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: - (##) Enable the SPIx interface clock. - (##) I2S pins configuration: - (+++) Enable the clock for the I2S GPIOs. - (+++) Configure these I2S pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() - and HAL_I2S_Receive_IT() APIs). - (+++) Configure the I2Sx interrupt priority. - (+++) Enable the NVIC I2S IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() - and HAL_I2S_Receive_DMA() APIs: - (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream/Channel. - (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA Tx/Rx Stream/Channel. - - (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity - using HAL_I2S_Init() function. - - -@- The specific I2S interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. - -@- Make sure that either: - (+@) PLLPCLK output is configured or - (+@) HSI is enabled or - (+@) External clock source is configured after setting correctly - the define constant EXTERNAL_CLOCK_VALUE in the stm32wbxx_hal_conf.h file. - - (#) Three mode of operations are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() - (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2S_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2S_ErrorCallback - (+) Pause the DMA Transfer using HAL_I2S_DMAPause() - (+) Resume the DMA Transfer using HAL_I2S_DMAResume() - (+) Stop the DMA Transfer using HAL_I2S_DMAStop() - - *** I2S HAL driver macros list *** - =================================== - [..] - Below the list of most used macros in I2S HAL driver. - - (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts - (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts - (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not - - [..] - (@) You can refer to the I2S HAL driver header file for more useful macros - - *** I2S HAL driver macros list *** - =================================== - [..] - Callback registration: - - (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback. - - Function HAL_I2S_RegisterCallback() allows to register following callbacks: - (++) TxCpltCallback : I2S Tx Completed callback - (++) RxCpltCallback : I2S Rx Completed callback - (++) TxHalfCpltCallback : I2S Tx Half Completed callback - (++) RxHalfCpltCallback : I2S Rx Half Completed callback - (++) ErrorCallback : I2S Error callback - (++) MspInitCallback : I2S Msp Init callback - (++) MspDeInitCallback : I2S Msp DeInit callback - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - - (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default - weak function. - HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (++) TxCpltCallback : I2S Tx Completed callback - (++) RxCpltCallback : I2S Rx Completed callback - (++) TxHalfCpltCallback : I2S Tx Half Completed callback - (++) RxHalfCpltCallback : I2S Rx Half Completed callback - (++) ErrorCallback : I2S Error callback - (++) MspInitCallback : I2S Msp Init callback - (++) MspDeInitCallback : I2S Msp DeInit callback - - [..] - By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when - these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - - [..] - Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() - or HAL_I2S_Init() function. - - [..] - When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32wbxx_hal.h" - -#ifdef HAL_I2S_MODULE_ENABLED - -#if defined(SPI_I2S_SUPPORT) -/** @addtogroup STM32WBxx_HAL_Driver - * @{ - */ - -/** @defgroup I2S I2S - * @brief I2S HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup I2S_Private_Functions I2S Private Functions - * @{ - */ -static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMAError(DMA_HandleTypeDef *hdma); -static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); -static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, - uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup I2S_Exported_Functions I2S Exported Functions - * @{ - */ - -/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the I2Sx peripheral in simplex mode: - - (+) User must Implement HAL_I2S_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2S_Init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Standard - (++) Data Format - (++) MCLK Output - (++) Audio frequency - (++) Polarity - - (+) Call the function HAL_I2S_DeInit() to restore the default configuration - of the selected I2Sx peripheral. - @endverbatim - * @{ - */ - -/** - * @brief Initializes the I2S according to the specified parameters - * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) -{ - uint32_t i2sdiv; - uint32_t i2sodd; - uint32_t packetlength; - uint32_t tmp; - uint32_t i2sclk = 0U; - - /* Check the I2S handle allocation */ - if (hi2s == NULL) - { - return HAL_ERROR; - } - - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); - assert_param(IS_I2S_MODE(hi2s->Init.Mode)); - assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); - assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); - assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); - - if (hi2s->State == HAL_I2S_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2s->Lock = HAL_UNLOCKED; - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - /* Init the I2S Callback settings */ - hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hi2s->MspInitCallback == NULL) - { - hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - hi2s->MspInitCallback(hi2s); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2S_MspInit(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - } - - hi2s->State = HAL_I2S_STATE_BUSY; - - /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ - SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ - SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); - hi2s->Instance->I2SPR = 0x0002U; - - /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/ - /* If the requested audio frequency is not the default, compute the prescaler */ - if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) - { - /* Check the frame length (For the Prescaler computing) ********************/ - if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) - { - /* Packet length is 16 bits */ - packetlength = 16U; - } - else - { - /* Packet length is 32 bits */ - packetlength = 32U; - } - - /* I2S standard */ - if (hi2s->Init.Standard <= I2S_STANDARD_LSB) - { - /* In I2S standard packet lenght is multiplied by 2 */ - packetlength = packetlength * 2U; - } - - /* Get the source clock value: based on System Clock value */ - i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) - { - /* MCLK output is enabled */ - if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) - { - tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); - } - else - { - tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); - } - } - else - { - /* MCLK output is disabled */ - tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U); - } - - /* Remove the flatting point */ - tmp = tmp / 10U; - - /* Check the parity of the divider */ - i2sodd = (uint32_t)(tmp & (uint32_t)1U); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint32_t)((tmp - i2sodd) / 2U); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint32_t)(i2sodd << 8U); - } - else - { - /* Set the default values */ - i2sdiv = 2U; - i2sodd = 0U; - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) - { - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); - return HAL_ERROR; - } - - /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ - - /* Write to SPIx I2SPR register the computed value */ - hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); - - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - /* And configure the I2S with the I2S_InitStruct values */ - MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ - SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ - SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ - SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \ - (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ - hi2s->Init.Standard | hi2s->Init.DataFormat | \ - hi2s->Init.CPOL)); - -#if defined(SPI_I2SCFGR_ASTRTEN) - if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))) - { - /* Write to SPIx I2SCFGR */ - SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN); - } -#endif /* SPI_I2SCFGR_ASTRTEN */ - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the I2S peripheral - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) -{ - /* Check the I2S handle allocation */ - if (hi2s == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); - - hi2s->State = HAL_I2S_STATE_BUSY; - - /* Disable the I2S Peripheral Clock */ - __HAL_I2S_DISABLE(hi2s); - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - if (hi2s->MspDeInitCallback == NULL) - { - hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - hi2s->MspDeInitCallback(hi2s); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_I2S_MspDeInit(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief I2S MSP Init - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspInit could be implemented in the user file - */ -} - -/** - * @brief I2S MSP DeInit - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User I2S Callback - * To be used instead of the weak predefined callback - * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for the specified I2S. - * @param CallbackID ID of the callback to be registered - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, - pI2S_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hi2s); - - if (HAL_I2S_STATE_READY == hi2s->State) - { - switch (CallbackID) - { - case HAL_I2S_TX_COMPLETE_CB_ID : - hi2s->TxCpltCallback = pCallback; - break; - - case HAL_I2S_RX_COMPLETE_CB_ID : - hi2s->RxCpltCallback = pCallback; - break; - - case HAL_I2S_TX_HALF_COMPLETE_CB_ID : - hi2s->TxHalfCpltCallback = pCallback; - break; - - case HAL_I2S_RX_HALF_COMPLETE_CB_ID : - hi2s->RxHalfCpltCallback = pCallback; - break; - - case HAL_I2S_ERROR_CB_ID : - hi2s->ErrorCallback = pCallback; - break; - - case HAL_I2S_MSPINIT_CB_ID : - hi2s->MspInitCallback = pCallback; - break; - - case HAL_I2S_MSPDEINIT_CB_ID : - hi2s->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_I2S_STATE_RESET == hi2s->State) - { - switch (CallbackID) - { - case HAL_I2S_MSPINIT_CB_ID : - hi2s->MspInitCallback = pCallback; - break; - - case HAL_I2S_MSPDEINIT_CB_ID : - hi2s->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hi2s); - return status; -} - -/** - * @brief Unregister an I2S Callback - * I2S callback is redirected to the weak predefined callback - * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for the specified I2S. - * @param CallbackID ID of the callback to be unregistered - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hi2s); - - if (HAL_I2S_STATE_READY == hi2s->State) - { - switch (CallbackID) - { - case HAL_I2S_TX_COMPLETE_CB_ID : - hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_I2S_RX_COMPLETE_CB_ID : - hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_I2S_TX_HALF_COMPLETE_CB_ID : - hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_I2S_RX_HALF_COMPLETE_CB_ID : - hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_I2S_ERROR_CB_ID : - hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_I2S_MSPINIT_CB_ID : - hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_I2S_MSPDEINIT_CB_ID : - hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_I2S_STATE_RESET == hi2s->State) - { - switch (CallbackID) - { - case HAL_I2S_MSPINIT_CB_ID : - hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_I2S_MSPDEINIT_CB_ID : - hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hi2s); - return status; -} -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup I2S_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2S data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2S_Transmit() - (++) HAL_I2S_Receive() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2S_Transmit_IT() - (++) HAL_I2S_Receive_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2S_Transmit_DMA() - (++) HAL_I2S_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2S_TxCpltCallback() - (++) HAL_I2S_RxCpltCallback() - (++) HAL_I2S_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @param Timeout Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1U); - hi2s->TxXferCount = (Size << 1U); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - tmpreg_cfgr = hi2s->Instance->I2SCFGR; - - /* Check if the I2S is already enabled */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Wait until TXE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - while (hi2s->TxXferCount > 0U) - { - hi2s->Instance->DR = (*hi2s->pTxBuffPtr); - hi2s->pTxBuffPtr++; - hi2s->TxXferCount--; - - /* Wait until TXE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - /* Check if an underrun occurs */ - if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) - { - /* Clear underrun flag */ - __HAL_I2S_CLEAR_UDRFLAG(hi2s); - - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); - } - } - - /* Check if Slave mode is selected */ - if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) - || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) - { - /* Wait until Busy flag is reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - } - - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Receive an amount of data in blocking mode - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @param Timeout Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate - * in continuous way and as the I2S is not disabled at the end of the I2S transaction. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pRxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1U); - hi2s->RxXferCount = (Size << 1U); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - /* Check if the I2S is already enabled */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if Master Receiver mode is selected */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) - { - /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read - access to the SPI_SR register. */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - } - - /* Receive data */ - while (hi2s->RxXferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; - hi2s->pRxBuffPtr++; - hi2s->RxXferCount--; - - /* Check if an overrun occurs */ - if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) - { - /* Clear overrun flag */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); - } - } - - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1U); - hi2s->TxXferCount = (Size << 1U); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Enable TXE and ERR interrupt */ - __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to the Receive data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization - * between Master and Slave otherwise the I2S interrupt should be optimized. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pRxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1U); - hi2s->RxXferCount = (Size << 1U); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - /* Enable RXNE and ERR interrupt */ - __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to the Transmit data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1U); - hi2s->TxXferCount = (Size << 1U); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Set the I2S Tx DMA Half transfer complete callback */ - hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; - - /* Set the I2S Tx DMA transfer complete callback */ - hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; - - /* Set the DMA error callback */ - hi2s->hdmatx->XferErrorCallback = I2S_DMAError; - - /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, - (uint32_t)hi2s->pTxBuffPtr, - (uint32_t)&hi2s->Instance->DR, - hi2s->TxXferSize)) - { - /* Update SPI error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - hi2s->State = HAL_I2S_STATE_READY; - - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if the I2S Tx request is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) - { - /* Enable Tx DMA Request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to the Receive data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pRxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1U); - hi2s->RxXferCount = (Size << 1U); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - /* Set the I2S Rx DMA Half transfer complete callback */ - hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; - - /* Set the I2S Rx DMA transfer complete callback */ - hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; - - /* Set the DMA error callback */ - hi2s->hdmarx->XferErrorCallback = I2S_DMAError; - - /* Check if Master Receiver mode is selected */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) - { - /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read - access to the SPI_SR register. */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - } - - /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, - hi2s->RxXferSize)) - { - /* Update SPI error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - hi2s->State = HAL_I2S_STATE_READY; - - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if the I2S Rx request is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) - { - /* Enable Rx DMA Request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Pauses the audio DMA Stream/Channel playing from the Media. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Disable the I2S DMA Tx request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* Disable the I2S DMA Rx request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - else - { - /* nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief Resumes the audio DMA Stream/Channel playing from the Media. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Enable the I2S DMA Tx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* Enable the I2S DMA Rx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - else - { - /* nothing to do */ - } - - /* If the I2S peripheral is still not enabled, enable it */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief Stops the audio DMA Stream/Channel playing from the Media. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() - when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() - */ - - /* Disable the I2S Tx/Rx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Abort the I2S DMA tx Stream/Channel */ - if (hi2s->hdmatx != NULL) - { - /* Disable the I2S DMA tx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) - { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; - } - } - - /* Abort the I2S DMA rx Stream/Channel */ - if (hi2s->hdmarx != NULL) - { - /* Disable the I2S DMA rx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) - { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; - } - } - - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); - - hi2s->State = HAL_I2S_STATE_READY; - - return errorcode; -} - -/** - * @brief This function handles I2S interrupt request. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) -{ - uint32_t itsource = hi2s->Instance->CR2; - uint32_t itflag = hi2s->Instance->SR; - - /* I2S in mode Receiver ------------------------------------------------*/ - if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && - (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET)) - { - I2S_Receive_IT(hi2s); - return; - } - - /* I2S in mode Tramitter -----------------------------------------------*/ - if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET)) - { - I2S_Transmit_IT(hi2s); - return; - } - - /* I2S interrupt error -------------------------------------------------*/ - if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET) - { - /* I2S Overrun error interrupt occurred ---------------------------------*/ - if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); - } - - /* I2S Underrun error interrupt occurred --------------------------------*/ - if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); - } - - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - - /* Call user error callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->ErrorCallback(hi2s); -#else - HAL_I2S_ErrorCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Tx Transfer Half completed callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer completed callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer half completed callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2S error callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2S state - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL state - */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) -{ - return hi2s->State; -} - -/** - * @brief Return the I2S error code - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval I2S Error Code - */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) -{ - return hi2s->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2S_Private_Functions I2S Private Functions - * @{ - */ -/** - * @brief DMA I2S transmit process complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* if DMA is configured in DMA_NORMAL Mode */ - if (hdma->Init.Mode == DMA_NORMAL) - { - /* Disable Tx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - - hi2s->TxXferCount = 0U; - hi2s->State = HAL_I2S_STATE_READY; - } - /* Call user Tx complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->TxCpltCallback(hi2s); -#else - HAL_I2S_TxCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA I2S transmit process half complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* Call user Tx half complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->TxHalfCpltCallback(hi2s); -#else - HAL_I2S_TxHalfCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA I2S receive process complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* if DMA is configured in DMA_NORMAL Mode */ - if (hdma->Init.Mode == DMA_NORMAL) - { - /* Disable Rx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - hi2s->RxXferCount = 0U; - hi2s->State = HAL_I2S_STATE_READY; - } - /* Call user Rx complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->RxCpltCallback(hi2s); -#else - HAL_I2S_RxCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA I2S receive process half complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* Call user Rx half complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->RxHalfCpltCallback(hi2s); -#else - HAL_I2S_RxHalfCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA I2S communication error callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMAError(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* Disable Rx and Tx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); - hi2s->TxXferCount = 0U; - hi2s->RxXferCount = 0U; - - hi2s->State = HAL_I2S_STATE_READY; - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - /* Call user error callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->ErrorCallback(hi2s); -#else - HAL_I2S_ErrorCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) -{ - /* Transmit data */ - hi2s->Instance->DR = (*hi2s->pTxBuffPtr); - hi2s->pTxBuffPtr++; - hi2s->TxXferCount--; - - if (hi2s->TxXferCount == 0U) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - /* Call user Tx complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->TxCpltCallback(hi2s); -#else - HAL_I2S_TxCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) -{ - /* Receive data */ - (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; - hi2s->pRxBuffPtr++; - hi2s->RxXferCount--; - - if (hi2s->RxXferCount == 0U) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - /* Call user Rx complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->RxCpltCallback(hi2s); -#else - HAL_I2S_RxCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - } -} - -/** - * @brief This function handles I2S Communication Timeout. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param Flag Flag checked - * @param State Value of the flag expected - * @param Timeout Duration of the timeout - * @retval HAL status - */ -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, - uint32_t Timeout) -{ - uint32_t tickstart; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set to status*/ - while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* SPI_I2S_SUPPORT */ - -#endif /* HAL_I2S_MODULE_ENABLED */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c index b6db8e5..3174654 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c @@ -16,33 +16,43 @@ (+) The IWDG can be started by either software or hardware (configurable through option byte). - (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even - if the main clock fails. + (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays + active even if the main clock fails. - (+) Once the IWDG is started, the LSI is forced ON and both can not be + (+) Once the IWDG is started, the LSI is forced ON and both cannot be disabled. The counter starts counting down from the reset value (0xFFF). When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, - the IWDG_RLR value is reloaded in the counter and the watchdog reset is - prevented. + the IWDG_RLR value is reloaded into the counter and the watchdog reset + is prevented. (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). IWDGRST flag in RCC_CSR register can be used to inform when an IWDG reset occurs. - (+) Debug mode : When the microcontroller enters debug mode (core halted), + (+) Debug mode: When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI frequency dispersion. STM32WBxx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM16 CH1 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. + The IWDG timeout may vary due to LSI clock frequency dispersion. + STM32WBxx devices provide the capability to measure the LSI clock + frequency (LSI clock is internally connected to TIM16 CH1 input capture). + The measured value can be used to have an IWDG timeout with an + acceptable accuracy. + + [..] Default timeout value (necessary for IWDG_SR status register update): + Constant LSI_VALUE is defined based on the nominal LSI clock frequency. + This frequency being subject to variations as mentioned above, the + default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT + below) may become too short or too long. + In such cases, this default timeout value can be tuned by redefining + the constant LSI_VALUE at user-application level (based, for instance, + on the measured LSI clock frequency as explained above). ##### How to use this driver ##### ============================================================================== @@ -108,10 +118,14 @@ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ -/* Status register need 5 RC LSI divided by prescaler clock to be updated. With - higher prescaler (256), and according to LSI variation, we need to wait at - least 6 cycles so 48 ms. */ -#define HAL_IWDG_DEFAULT_TIMEOUT 48u +/* Status register needs up to 5 LSI clock periods divided by the clock + prescaler to be updated. The number of LSI clock periods is upper-rounded to + 6 for the timeout value calculation. + The timeout value is also calculated using the highest prescaler (256) and + the LSI_VALUE constant. The value of this constant can be changed by the user + to take into account possible LSI clock period variations. + The timeout value is multiplied by 1000 to be converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) /** * @} */ @@ -126,8 +140,8 @@ */ /** @addtogroup IWDG_Exported_Functions_Group1 - * @brief Initialization and Start functions. - * + * @brief Initialization and Start functions. + * @verbatim =============================================================================== ##### Initialization and Start functions ##### @@ -215,8 +229,8 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /** @addtogroup IWDG_Exported_Functions_Group2 - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lcd.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lcd.c index 091af69..ee957b4 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lcd.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lcd.c @@ -329,19 +329,24 @@ __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd) [..] Using its double buffer memory the LCD controller ensures the coherency of the displayed information without having to use interrupts to control LCD_RAM modification. - The application software can access the first buffer level (LCD_RAM) through + + [..] The application software can access the first buffer level (LCD_RAM) through the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API, it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API. - This UDR flag (update display request) requests the updated information to be + + [..] This UDR flag (update display request) requests the updated information to be moved into the second buffer level (LCD_DISPLAY). - This operation is done synchronously with the frame (at the beginning of the + + [..] This operation is done synchronously with the frame (at the beginning of the next frame), until the update is completed, the LCD_RAM is write protected and the UDR flag stays high. - Once the update is completed another flag (UDD - Update Display Done) is set and + + [..] Once the update is completed another flag (UDD - Update Display Done) is set and generates an interrupt if the UDDIE bit in the LCD_FCR register is set. The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one even frame. - The update will not occur (UDR = 1 and UDD = 0) until the display is + + [..] The update will not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1). @endverbatim diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c index df3c8bf..2023624 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c @@ -349,16 +349,25 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Write to LPTIMx CFGR */ hlptim->Instance->CFGR = tmpcfgr; +#if defined(LPTIM_OR_OR) /* Configure LPTIM input sources */ if (hlptim->Instance == LPTIM1) { +#if defined(LPTIM_OR_OR_1) /* Check LPTIM Input1 and Input2 sources */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source)); /* Configure LPTIM Input1 and Input2 sources */ hlptim->Instance->OR = (hlptim->Init.Input1Source | hlptim->Init.Input2Source); +#else + /* Check LPTIM Input1 source */ + assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); + + /* Configure LPTIM Input1 source */ + hlptim->Instance->OR = hlptim->Init.Input1Source; +#endif /* LPTIM_OR_OR_1 */ } else { @@ -368,6 +377,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Configure LPTIM2 Input1 source */ hlptim->Instance->OR = hlptim->Init.Input1Source; } +#endif /* LPTIM_OR_OR */ /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; @@ -2380,7 +2390,9 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; +#if defined(LPTIM_OR_OR) uint32_t tmpOR; +#endif /* LPTIM_OR_OR */ __disable_irq(); @@ -2405,7 +2417,9 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) tmpCFGR = hlptim->Instance->CFGR; tmpCMP = hlptim->Instance->CMP; tmpARR = hlptim->Instance->ARR; +#if defined(LPTIM_OR_OR) tmpOR = hlptim->Instance->OR; +#endif /* LPTIM_OR_OR */ /*********** Reset LPTIM ***********/ switch ((uint32_t)hlptim->Instance) @@ -2491,7 +2505,9 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE); hlptim->Instance->IER = tmpIER; hlptim->Instance->CFGR = tmpCFGR; +#if defined(LPTIM_OR_OR) hlptim->Instance->OR = tmpOR; +#endif /* LPTIM_OR_OR */ __enable_irq(); } diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c index ad58b42..84ca4c3 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c @@ -1050,21 +1050,18 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP)) { /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U) - { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); + hpcd->SuspendCallback(hpcd); #else - HAL_PCD_SuspendCallback(hpcd); + HAL_PCD_SuspendCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } } /* Handle LPM Interrupt */ @@ -1074,8 +1071,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (hpcd->LPM_State == LPM_L0) { /* Force suspend and low-power mode before going to L1 state*/ - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; hpcd->LPM_State = LPM_L1; hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; @@ -1680,8 +1677,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /* DIR = 0 */ - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); ep = &hpcd->IN_ep[0]; @@ -1705,20 +1702,20 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /* DIR = 1 */ - /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); if ((wEPVal & USB_EP_SETUP) != 0U) { - /* Get SETUP Packet*/ + /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ + /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Process SETUP Packet*/ @@ -1733,7 +1730,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ + /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) @@ -1743,7 +1740,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet*/ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, 0U); #else @@ -1758,7 +1755,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - /* Decode and service non control endpoints interrupt */ + /* Decode and service non control endpoints interrupt */ /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); @@ -1768,7 +1765,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); ep = &hpcd->OUT_ep[epindex]; - /* OUT double Buffering*/ + /* OUT double Buffering */ if (ep->doublebuffer == 0U) { count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); @@ -1779,9 +1776,12 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { + /* free EP OUT Buffer */ + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) { - /*read from endpoint BUF0Addr buffer*/ + /* read from endpoint BUF0Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); if (count != 0U) { @@ -1790,17 +1790,15 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - /*read from endpoint BUF1Addr buffer*/ + /* read from endpoint BUF1Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } } - /* free EP OUT Buffer */ - PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); } - /*multi-packet on the NON control OUT endpoint*/ + /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; ep->xfer_buff += count; @@ -1827,7 +1825,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - /*multi-packet on the NON control IN endpoint*/ + /* multi-packet on the NON control IN endpoint */ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_buff += ep->xfer_count; diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c index d722c0a..6a356ae 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c @@ -128,10 +128,12 @@ void HAL_PWR_DeInit(void) /* Clear all flags */ LL_PWR_WriteReg(SCR, LL_PWR_SCR_CC2HF - | LL_PWR_SCR_C802AF | LL_PWR_SCR_CBLEAF | LL_PWR_SCR_CCRPEF +#if defined(PWR_CR3_E802A) + | LL_PWR_SCR_C802AF | LL_PWR_SCR_C802WUF +#endif | LL_PWR_SCR_CBLEWUF #if defined(PWR_CR5_SMPSEN) | LL_PWR_SCR_CBORHF @@ -222,8 +224,9 @@ void HAL_PWR_DisableBkUpAccess(void) (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on. (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode. - (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. - (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off. + (+) Standby mode with SRAM2a: all clocks are stopped except LSI and LSE, SRAM2a content preserved, main regulator off, low power regulator on. + Note: On devices STM32WB15xx, STM32WB10xx, retention is extended to SRAM1, SRAM2a, SRAM2b. + (+) Standby mode without SRAM2a: all clocks are stopped except LSI and LSE, main and low power regulators off. (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. @@ -266,6 +269,7 @@ void HAL_PWR_DisableBkUpAccess(void) The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's: (++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2 or for porting reasons HAL_PWR_EnterSTOPMode(). + Note: Low power Stop2 mode is not available on devices STM32WB15xx, STM32WB10xx. (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): (++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode) diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c index 4f28fe6..b1d857a 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c @@ -281,7 +281,7 @@ void HAL_PWREx_DisableBLEActivityIT(void) CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA); } - +#if defined(PWR_CR3_E802A) /** * @brief Enable 802.15.4 Activity interrupt. * @retval None @@ -299,6 +299,7 @@ void HAL_PWREx_Disable802ActivityIT(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_E802A); } +#endif /** * @brief Enable CPU2 on-Hold interrupt. @@ -640,9 +641,11 @@ void HAL_PWREx_ReleaseCore(uint32_t CPU) /****************************************************************************/ /** - * @brief Enable BKRAM content retention in Standby mode. - * @note When RRS bit is set, SRAM is powered by the low-power regulator in + * @brief Enable SRAM2a content retention in Standby mode. + * @note When RRS bit is set, SRAM2a is powered by the low-power regulator in * Standby mode and its content is kept. + * @note On devices STM32WB15xx, STM32WB10xx, retention is extended + * to SRAM1, SRAM2a and SRAM2b. * @retval None */ void HAL_PWREx_EnableSRAMRetention(void) @@ -651,9 +654,11 @@ void HAL_PWREx_EnableSRAMRetention(void) } /** - * @brief Disable BKRAM content retention in Standby mode. - * @note When RRS bit is reset, SRAM is powered off in Standby mode + * @brief Disable SRAM2a content retention in Standby mode. + * @note When RRS bit is reset, SRAM2a is powered off in Standby mode * and its content is lost. + * @note On devices STM32WB15xx, STM32WB10xx, retention is extended + * to SRAM1, SRAM2a and SRAM2b. * @retval None */ void HAL_PWREx_DisableSRAMRetention(void) @@ -678,7 +683,7 @@ void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode) if((PowerMode & PWR_FLASHPD_LPRUN) != 0U) { /* Unlock bit FPDR */ - WRITE_REG(PWR->CR1, 0x0000C1B0U); + WRITE_REG(PWR->CR1, 0x0000C1B0UL); } /* Set flash power down mode */ @@ -910,7 +915,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS) * * (1) SMPS operating mode step down or open depends on system low-power mode: * - step down mode if system low power mode is run, LP run or stop, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown * @retval None */ void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode) @@ -924,7 +929,7 @@ void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode) * requested operating mode can differ from effective low power mode. * - dependency on system low-power mode: * - step down mode if system low power mode is run, LP run or stop, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown * - dependency on BOR level: * - bypass mode if supply voltage drops below BOR level * @note This functions check flags of SMPS operating modes step down @@ -936,7 +941,7 @@ void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode) * * (1) SMPS operating mode step down or open depends on system low-power mode: * - step down mode if system low power mode is run, LP run or stop, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown */ uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void) { @@ -1129,7 +1134,6 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } - /** * @brief Enter Stop 1 mode. * @note In Stop 1 mode, only low power voltage regulator is ON. @@ -1182,7 +1186,7 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } - +#if defined(PWR_SUPPORT_STOP2) /** * @brief Enter Stop 2 mode. * @note In Stop 2 mode, only low power voltage regulator is ON. @@ -1244,10 +1248,7 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } - - - - +#endif /** * @brief Enter Shutdown mode. diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c index ae83a7a..2401c52 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c @@ -111,7 +111,7 @@ ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and flushes the fifo : (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. @@ -132,7 +132,7 @@ The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback, + Use Functions HAL_QSPI_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -149,7 +149,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default + Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -165,12 +165,12 @@ (+) MspDeInitCallback : QSPI MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init - and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -178,8 +178,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit - or @ref HAL_QSPI_Init function. + using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit + or HAL_QSPI_Init function. When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -195,7 +195,8 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -283,7 +284,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initialize the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and initialize the associated handle. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -381,7 +382,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -425,7 +426,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Initialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -440,7 +441,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -479,7 +480,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -765,9 +766,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @param cmd : structure that contains the command configuration information - * @param Timeout : Timeout duration + * @param Timeout Timeout duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -854,8 +855,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -952,9 +953,9 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1035,9 +1036,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1121,8 +1122,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1181,8 +1182,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1245,8 +1246,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1389,8 +1390,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1537,10 +1538,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1637,9 +1638,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1740,9 +1741,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the memory mapped configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1828,7 +1829,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1843,7 +1844,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1858,7 +1859,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1873,7 +1874,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1888,7 +1889,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1903,7 +1904,7 @@ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1918,7 +1919,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1933,7 +1934,7 @@ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1948,7 +1949,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1963,7 +1964,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1979,8 +1980,8 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Register a User QSPI Callback * To be used instead of the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be registered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -1994,7 +1995,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID - * @param pCallback : pointer to the Callback function + * @param pCallback pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) @@ -2093,8 +2094,8 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI /** * @brief Unregister a User QSPI Callback * QSPI Callback is redirected to the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be unregistered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2221,7 +2222,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS /** * @brief Return the QSPI handle state. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2232,7 +2233,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2242,7 +2243,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2298,7 +2299,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2353,8 +2354,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } /** @brief Set QSPI timeout. - * @param hqspi : QSPI handle. - * @param Timeout : Timeout for the QSPI memory access. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2363,8 +2364,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi : QSPI handle. - * @param Threshold : Threshold of the Fifo (value between 1 and 16). + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2396,7 +2397,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi : QSPI handle. + * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2418,7 +2419,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) /** * @brief DMA QSPI receive process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -2432,7 +2433,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -2446,7 +2447,7 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI receive process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2462,7 +2463,7 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2478,7 +2479,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) @@ -2499,7 +2500,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI abort complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) @@ -2538,11 +2539,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /** * @brief Wait for a flag state until timeout. - * @param hqspi : QSPI handle - * @param Flag : Flag checked - * @param State : Value of the flag expected - * @param Tickstart : Tick start value - * @param Timeout : Duration of the timeout + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Tickstart Tick start value + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2568,9 +2569,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information - * @param FunctionalMode : functional mode to configured + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c index c0a8841..518c255 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c @@ -158,7 +158,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. It can be used to generate the clock for the USB FS (48 MHz). The number of flash wait states is automatically adjusted when MSI range is updated with - @ref HAL_RCC_OscConfig() and the MSI is used as System clock source. + HAL_RCC_OscConfig() and the MSI is used as System clock source. (+) LSI1/LSI2 (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC clock source. @@ -207,7 +207,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these buses. You can use - "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + HAL_RCC_GetSysClockFreq() function to retrieve the frequencies of these clocks. The AHB4 clock (HCLK4) is derived from System clock through configurable prescaler and used to clock the FLASH @@ -215,16 +215,16 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSYS) or from an external clock mapped on the SAI_CKIN pin. - You have to use @ref HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 32. - You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() function + You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz to work correctly, while RNG peripherals requires a frequency equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1 through PLLQ divider. You have to enable the peripheral clock and use - @ref HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) IWDG clock which is always the LSI clock. @@ -257,14 +257,14 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t /** * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: - * - MSI ON and used as system clock source - * - HSE, HSI, PLL, PLLSAI1 - * - HCLK1, HCLK2, HCLK4, PCLK1 and PCLK2 prescalers set to 1. - * - CSS, MCO OFF - * - All interrupts disabled + * - MSI ON and used as system clock source + * - HSE, HSI, PLL, PLLSAI1 + * - HCLK1, HCLK2, HCLK4, PCLK1 and PCLK2 prescalers set to 1. + * - CSS, MCO OFF + * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks + * - Peripheral clocks + * - LSI, LSE and RTC clocks * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_DeInit(void) @@ -320,9 +320,6 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON); #endif - /* Reset HSEBYP bit once HSE is OFF */ - LL_RCC_HSE_DisableBypass(); - /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -452,7 +449,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Update the SystemCoreClock global variable */ - SystemCoreClockUpdate(); + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; @@ -820,6 +818,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } +#if defined(RCC_HSI48_SUPPORT) /*------------------------------ HSI48 Configuration -----------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) { @@ -862,6 +861,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } +#endif /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); @@ -1259,7 +1259,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /*---------------------------------------------------------------------------*/ /* Update the SystemCoreClock global variable */ - SystemCoreClockUpdate(); + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(HAL_GetTickPrio()); } @@ -1528,15 +1529,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ - RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2 | RCC_OSCILLATORTYPE_HSI48; + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2; +#if defined(RCC_HSI48_SUPPORT) + RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; +#endif /* Get the HSE configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } @@ -1595,6 +1595,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } +#if defined(RCC_HSI48_SUPPORT) /* Get the HSI48 configuration ---------------------------------------------*/ if ((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) { @@ -1604,7 +1605,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; } - +#endif /* Get the PLL configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c index b8cd418..28be15c 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c @@ -111,7 +111,7 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void); This subsection provides a set of functions allowing to control the RCC Clocks frequencies. [..] - (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) and RCC_BDCR register are set to their reset values. @@ -139,7 +139,6 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void); * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock * @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * * * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select @@ -429,23 +428,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif -#if defined(SPI_I2S_SUPPORT) - /*-------------------- I2S clock source configuration ----------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); - - /* Configure the I2S clock source */ - __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - - if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) - { - /* Enable RCC_PLL_I2SCLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2SCLK); - } - } -#endif return status; } @@ -456,7 +438,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals * clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1, - * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS, I2S). + * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -487,9 +469,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS; #endif -#if defined(SPI_I2S_SUPPORT) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S; -#endif #if defined(SAI1) /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ @@ -551,10 +530,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE(); #endif -#if defined(SPI_I2S_SUPPORT) - /* Get the I2S clock source -----------------------------------------------*/ - PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); -#endif } /** @@ -575,7 +550,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock * @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @retval Frequency in Hz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) @@ -724,6 +698,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else /* HSI48 clock divided by 3 used as RNG clock source */ { +#if defined(RCC_HSI48_SUPPORT) if (LL_RCC_HSI48_IsReady() == 1U) { frequency = HSI48_VALUE / 3U; @@ -732,6 +707,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* Nothing to do as frequency already initialized to 0U */ } +#else + /* Nothing to do as frequency already initialized to 0U */ +#endif } } #if defined(USB) @@ -865,7 +843,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)) { -#if defined(STM32WB55xx) || defined (STM32WB5Mxx) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ if (LL_RCC_PLLSAI1_IsReady() == 1U) { @@ -876,22 +854,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Nothing to do as frequency already initialized to 0U */ } break; -#elif defined(STM32WB35xx) - case LL_RCC_ADC_CLKSOURCE_HSI: /* HSI clock used as ADC clock source */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - /* Nothing to do as frequency already initialized to 0U */ - } - break; #endif case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ frequency = HAL_RCC_GetSysClockFreq(); break; - case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */ if (LL_RCC_PLL_IsReady() == 1U) { @@ -1062,19 +1028,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Nothing to do as frequency already initialized to 0U */ } } - else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSI) /* LSI clock used as RF Wakeup clock source */ - { - const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); - const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); - if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U)) - { - frequency = LSI_VALUE; - } - else - { - /* Nothing to do as frequency already initialized to 0U */ - } - } else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) /* HSE clock used as RF Wakeup clock source */ { frequency = HSE_VALUE / 1024U; @@ -1139,32 +1092,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Nothing to do as frequency already initialized to 0U */ } } -#endif -#if defined(SPI_I2S_SUPPORT) - if (PeriphClk == RCC_PERIPHCLK_I2S) - { - switch (LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE)) - { - case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - - case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - break; - - case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL */ - frequency = RCC_PLL_GetFreqDomain_P(); - break; - - case LL_RCC_I2S_CLKSOURCE_NONE: /* No clock used as I2S clock source */ - default: - break; - } - } #endif return (frequency); } @@ -1395,7 +1322,7 @@ void HAL_RCCEx_LSECSS_IRQHandler(void) __weak void HAL_RCCEx_LSECSS_Callback(void) { /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + the HAL_RCCEx_LSECSS_Callback should be implemented in the user file */ } @@ -1644,9 +1571,9 @@ HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType) (##) Prepare synchronization configuration necessary for HSI48 calibration (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. - (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate directly reload value with target and sychronization frequencies values - (##) Call function @ref HAL_RCCEx_CRSConfig which + (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. (+++) Configures CRS registers with synchronization configuration (+++) Enables automatic calibration and frequency error counter feature @@ -1657,12 +1584,12 @@ HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType) should be used as SYNC signal. (##) A polling function is provided to wait for complete synchronization - (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() (+++) According to CRS status, user can decide to adjust again the calibration or continue application if synchronization is OK (#) User can retrieve information related to synchronization in calling function - @ref HAL_RCCEx_CRSGetSynchronizationInfo() + HAL_RCCEx_CRSGetSynchronizationInfo() (#) Regarding synchronization status and synchronization information, user can try a new calibration in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. @@ -1673,18 +1600,18 @@ HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType) (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go through CRS Handler (CRS_IRQn/CRS_IRQHandler) - (++) Call function @ref HAL_RCCEx_CRSConfig() + (++) Call function HAL_RCCEx_CRSConfig() (++) Enable CRS_IRQn (thanks to NVIC functions) - (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) (++) Implement CRS status management in the following user callbacks called from HAL_RCCEx_CRS_IRQHandler(): - (+++) @ref HAL_RCCEx_CRS_SyncOkCallback() - (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback() - (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback() - (+++) @ref HAL_RCCEx_CRS_ErrorCallback() + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() - (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). - This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler) + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) @endverbatim * @{ @@ -1943,7 +1870,7 @@ __weak void HAL_RCCEx_CRS_SyncOkCallback(void) __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + the HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file */ } @@ -1954,7 +1881,7 @@ __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + the HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file */ } diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c index 68e182b..fd68e02 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c @@ -318,44 +318,44 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call { switch (CallbackID) { - case HAL_RNG_ERROR_CB_ID : - hrng->ErrorCallback = pCallback; - break; - - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = pCallback; - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = pCallback; + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_RNG_STATE_RESET == hrng->State) { switch (CallbackID) { - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = pCallback; - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -393,44 +393,44 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { switch (CallbackID) { - case HAL_RNG_ERROR_CB_ID : - hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_RNG_STATE_RESET == hrng->State) { switch (CallbackID) { - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c index a8993e1..4dc1510 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c @@ -2334,7 +2334,7 @@ static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef */ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) { - register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); + uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); HAL_StatusTypeDef status = HAL_OK; /* Disable the SAI instance */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c index 6f38d0c..22f84da 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c @@ -123,9 +123,9 @@ and a pointer to the user callback function. [..] - Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -196,8 +196,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ + * @{ + */ #define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ @@ -231,7 +231,8 @@ void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -481,7 +482,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -603,7 +605,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -795,7 +798,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint8_t *ptmpdata = pData; @@ -819,14 +823,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; @@ -841,19 +854,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, + Timeout) != HAL_OK) { return HAL_TIMEOUT; } - /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { - /* Disable the Peripheral first to update modes */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* At end of Tx process, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -882,7 +904,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint8_t *ptmpdata = pData; @@ -973,14 +996,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + /* Configure Tx interrupt processing */ if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) { @@ -1100,8 +1132,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef status; - /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { @@ -1123,14 +1153,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; @@ -1141,9 +1180,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA channel */ - status = HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size); - - if(status == HAL_OK) + if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, + Size) == HAL_OK) { /* Clear the TC flag in the ICR register */ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); @@ -1192,8 +1230,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef status; - /* Check that a Rx process is not already ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { @@ -1221,9 +1257,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - status = HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size); - - if(status == HAL_OK) + if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, + Size) == HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -1275,8 +1310,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* Disable the SMARTCARD DMA Tx request if enabled */ @@ -1298,9 +1335,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Set error code to DMA */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - return HAL_TIMEOUT; } } @@ -1326,9 +1360,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Set error code to DMA */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - return HAL_TIMEOUT; } } @@ -1340,7 +1371,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1397,9 +1430,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /* Set error code to DMA */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - return HAL_TIMEOUT; } } @@ -1463,9 +1493,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Set error code to DMA */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - return HAL_TIMEOUT; } } @@ -1476,7 +1503,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1504,7 +1533,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) uint32_t abortcplt = 1U; /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised @@ -1601,7 +1632,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1729,7 +1762,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1771,7 +1804,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc hsmartcard->RxISR = NULL; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1795,7 +1830,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc hsmartcard->RxISR = NULL; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1825,6 +1862,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); uint32_t errorflags; + uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); @@ -1906,16 +1944,17 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } /* If Error is to be considered as blocking : - - Receiver Timeout error in Reception - - Overrun error in Reception - - any error occurs in DMA mode reception + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception */ + errorcode = hsmartcard->ErrorCode; if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - || ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) + || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ SMARTCARD_EndRxTransfer(hsmartcard); /* Disable the SMARTCARD DMA Rx request if enabled */ @@ -1960,14 +1999,14 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } } /* other error type to be considered as blocking : - - Frame error in Transmission + - Frame error in Transmission */ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != 0U)) + && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U)) { /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ + Set the SMARTCARD state ready to be able to start again the process, + Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ SMARTCARD_EndTxTransfer(hsmartcard); /* Disable the SMARTCARD DMA Tx request if enabled */ @@ -2042,7 +2081,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) HAL_SMARTCARD_RxCpltCallback(hsmartcard); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information - * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + to be available during HAL_SMARTCARD_RxCpltCallback() processing */ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); return; } @@ -2062,7 +2101,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { - if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { SMARTCARD_EndTransmit_IT(hsmartcard); return; @@ -2224,7 +2263,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = (uint32_t)hsmartcard->gState; temp2 = (uint32_t)hsmartcard->RxState; @@ -2285,7 +2325,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { uint32_t tmpreg; SMARTCARD_ClockSourceTypeDef clocksource; - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; @@ -2481,7 +2521,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2491,7 +2532,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2518,7 +2560,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) @@ -2642,7 +2685,7 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) /* Stop SMARTCARD DMA Tx request if ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { hsmartcard->TxXferCount = 0U; SMARTCARD_EndTxTransfer(hsmartcard); @@ -2721,7 +2764,9 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2768,7 +2813,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2828,7 +2875,9 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2931,15 +2980,22 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { - /* Disable the Peripheral first to update modes */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* Tx process is ended, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard_ex.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard_ex.c index ffcac33..aac6bfb 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard_ex.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard_ex.c @@ -8,7 +8,6 @@ * + Initialization and de-initialization functions * + Peripheral Control functions * - * @verbatim ============================================================================= ##### SMARTCARD peripheral extended features ##### @@ -56,11 +55,17 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants + * @{ + */ /* UART RX FIFO depth */ #define RX_FIFO_DEPTH 8U /* UART TX FIFO depth */ #define TX_FIFO_DEPTH 8U +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -90,8 +95,7 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard); * @{ */ -/** - * @brief Update on the fly the SMARTCARD block length in RTOR register. +/** @brief Update on the fly the SMARTCARD block length in RTOR register. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @param BlockLength SMARTCARD block length (8-bit long at most) @@ -102,8 +106,7 @@ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uin MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos)); } -/** - * @brief Update on the fly the receiver timeout value in RTOR register. +/** @brief Update on the fly the receiver timeout value in RTOR register. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout @@ -116,15 +119,13 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); } -/** - * @brief Enable the SMARTCARD receiver timeout feature. +/** @brief Enable the SMARTCARD receiver timeout feature. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Process Locked */ @@ -148,15 +149,13 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef } } -/** - * @brief Disable the SMARTCARD receiver timeout feature. +/** @brief Disable the SMARTCARD receiver timeout feature. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Process Locked */ @@ -191,12 +190,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of FIFO mode related callback functions. (#) TX/RX Fifos Callbacks: - (+) HAL_SMARTCARDEx_RxFifoFullCallback() - (+) HAL_SMARTCARDEx_TxFifoEmptyCallback() - + (++) HAL_SMARTCARDEx_RxFifoFullCallback() + (++) HAL_SMARTCARDEx_TxFifoEmptyCallback() @endverbatim * @{ @@ -238,15 +237,16 @@ __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartc * @} */ -/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions +/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions * @brief SMARTCARD control functions * @verbatim =============================================================================== - ##### Peripheral Control functions ##### + ##### Peripheral FIFO Control functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the SMARTCARD. + This subsection provides a set of functions allowing to control the SMARTCARD + FIFO feature. (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold @@ -440,7 +440,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs * @} */ -/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions +/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions * @{ */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c index 4c76d77..9d336dd 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c @@ -203,18 +203,18 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} */ @@ -1801,7 +1801,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint16_t DevAddress; @@ -1854,7 +1854,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* REenable the selected SMBUS peripheral */ + /* Re-enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); /* Call the corresponding callback to inform upper layer of End of Transfer */ @@ -2085,7 +2085,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint8_t TransferDirection; uint16_t SlaveAddrCode; @@ -2341,7 +2341,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; @@ -2381,7 +2381,7 @@ static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Inte * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; uint32_t tmpstate = hsmbus->State; @@ -2453,7 +2453,7 @@ static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Int * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t itflags = READ_REG(hsmbus->Instance->ISR); uint32_t itsources = READ_REG(hsmbus->Instance->CR1); @@ -2554,7 +2554,7 @@ static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2603,7 +2603,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeD * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2616,11 +2616,11 @@ static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t } /** - * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions. * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) { /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c index 1011413..416c8b6 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c @@ -131,7 +131,7 @@ DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | @@ -156,7 +156,7 @@ DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | @@ -337,6 +337,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; } #if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); @@ -400,44 +418,56 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; } - /* Align the CRC Length on the data size */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) - { - /* CRC Length aligned on the data size : value set by default */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; - } - else - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; - } - } - /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ - WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); #if (USE_SPI_CRC != 0U) - /* Configure : CRC Length */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + /*---------------------------- SPIx CRCL Configuration -------------------*/ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCL; + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | - hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + (hspi->Init.TIMode & SPI_CR2_FRF) | + (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + (frxth & SPI_CR2_FRXTH))); #if (USE_SPI_CRC != 0U) /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); } #endif /* USE_SPI_CRC */ @@ -835,6 +865,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1042,6 +1074,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1544,6 +1578,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1635,6 +1671,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1835,6 +1873,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1965,6 +2005,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -3051,8 +3093,17 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } #endif /* USE_SPI_CRC */ - /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) @@ -3469,7 +3520,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 8bit CRC to flush Data Regsiter */ + /* Read 8bit CRC to flush Data Register */ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); hspi->CRCSize--; @@ -3577,7 +3628,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 16bit CRC to flush Data Regsiter */ + /* Read 16bit CRC to flush Data Register */ READ_REG(hspi->Instance->DR); /* Disable RXNE interrupt */ @@ -3794,15 +3845,26 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) { if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); @@ -3827,6 +3889,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; } } @@ -3846,6 +3914,17 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + while ((hspi->Instance->SR & Fifo) != State) { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) @@ -3856,7 +3935,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -3885,6 +3964,12 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; } } @@ -3971,7 +4056,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { uint32_t tickstart; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Disable ERR interrupt */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c index 3116b78..ed23122 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c @@ -207,7 +207,7 @@ all interrupt callbacks are set to the corresponding weak functions: * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions @@ -229,6 +229,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -314,6 +315,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -347,6 +355,13 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -399,19 +414,29 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } - /* Change the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -426,13 +451,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the TIM state*/ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -451,12 +473,28 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -474,12 +512,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -498,6 +540,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; @@ -515,7 +558,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else { - /* nothing to do */ + return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ @@ -528,6 +571,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -535,8 +579,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -563,7 +614,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -646,6 +697,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -679,6 +737,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -738,6 +803,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -748,8 +822,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -788,6 +869,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -810,6 +894,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -854,8 +947,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -926,6 +1026,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -950,11 +1053,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -962,12 +1066,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -984,6 +1088,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1004,6 +1109,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1024,6 +1130,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1043,6 +1150,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1064,8 +1172,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1140,8 +1255,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1223,6 +1338,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1256,6 +1378,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1315,6 +1444,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -1325,8 +1463,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1365,8 +1510,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1389,6 +1534,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1433,8 +1587,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1505,6 +1666,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1529,11 +1693,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1541,12 +1706,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -1563,6 +1728,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1583,6 +1749,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1602,6 +1769,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ @@ -1621,6 +1789,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1642,8 +1811,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1718,8 +1894,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1801,6 +1977,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1834,6 +2017,13 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1887,16 +2077,36 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1927,6 +2137,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1945,10 +2159,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1986,8 +2213,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2052,6 +2286,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2072,16 +2310,21 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2089,12 +2332,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -2111,6 +2355,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -2130,6 +2375,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -2149,6 +2395,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -2168,6 +2415,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2183,8 +2431,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2210,6 +2465,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2248,14 +2506,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2292,6 +2548,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: @@ -2347,6 +2606,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2380,6 +2648,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2430,9 +2707,29 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2487,6 +2784,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2502,9 +2805,29 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2570,6 +2893,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2608,6 +2937,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status @@ -2705,6 +3037,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2739,6 +3080,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2790,9 +3140,59 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + /* Enable the encoder interface channels */ switch (Channel) { @@ -2864,6 +3264,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + /* Return function status */ return HAL_OK; } @@ -2880,9 +3294,59 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ switch (Channel) @@ -2962,8 +3426,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -2985,27 +3460,95 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) { - return HAL_BUSY; + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } - else if (htim->State == HAL_TIM_STATE_READY) + else if (Channel == TIM_CHANNEL_2) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { - return HAL_ERROR; + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } } else { - htim->State = HAL_TIM_STATE_BUSY; + return HAL_ERROR; } } else { - /* nothing to do */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } switch (Channel) @@ -3022,6 +3565,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3046,6 +3590,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3071,6 +3616,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -3084,6 +3630,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ @@ -3103,6 +3650,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch default: break; } + /* Return function status */ return HAL_OK; } @@ -3155,8 +3703,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -3425,8 +3984,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3493,8 +4050,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3525,8 +4080,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ @@ -3590,8 +4143,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3625,8 +4176,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3735,8 +4284,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3906,20 +4453,74 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -3927,7 +4528,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -3946,8 +4547,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3963,8 +4566,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3980,8 +4584,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3997,8 +4602,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4014,8 +4620,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4031,8 +4638,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4048,8 +4656,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4057,14 +4666,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t default: break; } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4077,7 +4684,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4086,51 +4692,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4179,18 +4785,72 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4198,7 +4858,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -4217,8 +4877,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4233,15 +4895,17 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { - /* Set the DMA capture/compare callbacks */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; @@ -4249,8 +4913,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4265,8 +4931,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4281,8 +4949,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4297,8 +4967,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4313,8 +4985,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4323,14 +4997,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B break; } - /* configure the DMA Burst Mode */ + /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4343,7 +5015,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4352,51 +5023,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4752,13 +5423,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: break; @@ -5698,6 +6369,54 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + /** * @} */ @@ -5719,13 +6438,38 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** @@ -5733,27 +6477,45 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -5778,8 +6540,6 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -5819,23 +6579,45 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -5860,8 +6642,6 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -5901,7 +6681,10 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); @@ -5919,8 +6702,6 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else @@ -5937,7 +6718,10 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); @@ -5955,8 +6739,6 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else @@ -6015,7 +6797,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6090,7 +6872,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6166,7 +6948,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6240,7 +7022,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6300,7 +7082,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, @@ -6353,7 +7135,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, @@ -6457,7 +7239,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) { return HAL_ERROR; } @@ -6509,11 +7291,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } default: break; diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c index 503cb0c..1343a82 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c @@ -56,7 +56,7 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @@ -92,20 +92,40 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ /** @addtogroup TIMEx_Private_Macros * @{ */ +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) #define TIM_GET_OR_MASK(__INSTANCE__) \ (((__INSTANCE__) == TIM1) ? (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) : \ ((__INSTANCE__) == TIM2) ? (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) : \ ((__INSTANCE__) == TIM16) ? TIM16_OR_TI1_RMP : TIM17_OR_TI1_RMP) +#else +#define TIM_GET_OR_MASK(__INSTANCE__) \ + (((__INSTANCE__) == TIM1) ? (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) : \ + ((__INSTANCE__) == TIM2) ? TIM2_OR_ETR_RMP : \ + ((__INSTANCE__) == TIM16) ? TIM16_OR_TI1_RMP : TIM17_OR_TI1_RMP) +#endif /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ @@ -136,6 +156,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status @@ -221,6 +244,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -254,6 +286,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -301,17 +342,43 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -337,6 +404,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -349,10 +422,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -361,8 +453,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -391,6 +490,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -405,29 +510,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -441,14 +553,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -476,9 +596,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -525,6 +650,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -532,8 +666,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -567,6 +708,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -589,6 +733,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -627,8 +780,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -697,6 +857,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -721,24 +884,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -746,15 +910,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -765,15 +930,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -784,15 +950,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -811,8 +978,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -876,8 +1050,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -934,6 +1108,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -941,8 +1124,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -975,6 +1165,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -997,6 +1190,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1034,8 +1236,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1105,6 +1314,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1129,39 +1341,42 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -1172,15 +1387,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1191,15 +1407,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1218,8 +1435,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1283,8 +1507,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1324,11 +1548,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Enable the complementary One Pulse output */ + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1349,12 +1589,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1362,6 +1604,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1378,17 +1624,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - /* Enable the complementary One Pulse output */ + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1409,6 +1671,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1418,8 +1682,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1427,6 +1692,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1746,6 +2015,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Set BREAK AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + } + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { /* Check the parameters */ @@ -1757,6 +2035,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set BREAK2 AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } } /* Set TIMx_BDTR */ @@ -1891,8 +2178,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * field1 can have the following values: * @arg TIM_TIM1_ETR_ADC1_GPIO: TIM1_ETR is connected to I/O * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 (*) + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 (*) * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output (*) * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output (*) * field2 can have the following values: @@ -2014,6 +2301,130 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan return HAL_OK; } +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + break; + } + + return HAL_OK; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + do + { + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM) + { + return HAL_OK; + } + } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); + + return HAL_TIMEOUT; + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + do + { + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM) + { + return HAL_OK; + } + } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); + + return HAL_TIMEOUT; + } + break; + } + default: + break; + } + + return HAL_OK; +} + /** * @} */ @@ -2121,6 +2532,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} /** * @} */ @@ -2173,6 +2605,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) } +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c index 64323f9..a692a5c 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c @@ -182,7 +182,7 @@ #if defined(LPUART1) #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ -#endif +#endif /* LPUART1 */ #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ @@ -193,6 +193,8 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -314,7 +316,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); #else assert_param(IS_UART_INSTANCE(huart->Instance)); -#endif +#endif /* LPUART1 */ } if (huart->gState == HAL_UART_STATE_RESET) @@ -628,7 +630,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); #else assert_param(IS_UART_INSTANCE(huart->Instance)); -#endif +#endif /* LPUART1 */ huart->gState = HAL_UART_STATE_BUSY; @@ -2867,11 +2869,11 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; - uint32_t usartdiv = 0x00000000U; + uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; #if defined(LPUART1) - uint32_t lpuart_ker_ck_pres = 0x00000000U; -#endif + uint32_t lpuart_ker_ck_pres; +#endif /* LPUART1 */ uint32_t pclk; /* Check the parameters */ @@ -2890,7 +2892,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) #else assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); -#endif +#endif /* LPUART1 */ assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); @@ -2929,7 +2931,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) } #else tmpreg |= huart->Init.OneBitSampling; -#endif +#endif /* LPUART1 */ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); /*-------------------------- USART PRESC Configuration -----------------------*/ @@ -2948,26 +2950,30 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); break; case UART_CLOCKSOURCE_HSI: - lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: - lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); break; case UART_CLOCKSOURCE_LSE: - lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } - /* if proper clock source reported */ - if (lpuart_ker_ck_pres != 0U) + /* If proper clock source reported */ + if (pclk != 0U) { - /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) { @@ -2975,28 +2981,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) } else { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_HSI: - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_LSE: - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - default: - ret = HAL_ERROR; - break; - } - - /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, (uint64_t)huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { huart->Instance->BRR = usartdiv; @@ -3005,8 +2992,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { ret = HAL_ERROR; } - } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ - } /* if (lpuart_ker_ck_pres != 0) */ + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) @@ -3018,33 +3005,36 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } } } else @@ -3053,31 +3043,34 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } } } diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c index 0bc1ac1..e67f5b2 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c @@ -49,7 +49,7 @@ by calling the customized HAL_USART_MspInit(&husart) API. [..] - (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's + (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to USART API's HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. @@ -529,9 +529,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US } /** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @param husart uart handle + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID @@ -732,7 +732,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /** * @brief Simplex send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -830,7 +830,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -942,7 +942,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -1091,7 +1091,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -1175,7 +1175,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Receive an amount of data in interrupt mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -1279,7 +1279,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -1377,7 +1377,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -1463,7 +1463,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -1580,7 +1580,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c index 457d6a9..e0305e1 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c @@ -57,10 +57,10 @@ /** @defgroup USARTEx_Private_Constants USARTEx Private Constants * @{ */ -/* UART RX FIFO depth */ +/* USART RX FIFO depth */ #define RX_FIFO_DEPTH 8U -/* UART TX FIFO depth */ +/* USART TX FIFO depth */ #define TX_FIFO_DEPTH 8U /** * @} @@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - husart->SlaveMode = USART_SLAVEMODE_ENABLE; + husart->SlaveMode = USART_SLAVEMODE_DISABLE; husart->State = HAL_USART_STATE_READY; diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c index e70227c..87874df 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c @@ -21,6 +21,13 @@ before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) If required by application, an Early Wakeup Interrupt can be triggered + in order to be warned before WWDG expiration. The Early Wakeup Interrupt + (EWI) can be used if specific safety operations or data logging must + be performed before the actual reset is generated. When the downcounter + reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt + line to be enabled in NVIC. Once enabled, EWI interrupt cannot be + disabled except by a system reset. (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG reset occurs. (+) The WWDG counter input clock is derived from the APB clock divided @@ -34,7 +41,8 @@ (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler: max timeout before reset: approximately 64us - (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler dividing by 128: + (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler + dividing by 128: max timeout before reset: approximately 524.28ms ##### How to use this driver ##### @@ -45,16 +53,16 @@ [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window and counter value - using HAL_WWDG_Init() function. - (+) Start the WWDG using HAL_WWDG_Start() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is - generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can - add his own code by customization of callback HAL_WWDG_WakeupCallback. - Once enabled, EWI interrupt cannot be disabled except by a system reset. + (+) Configure the WWDG prescaler, refresh window value, counter value and early + interrupt status using HAL_WWDG_Init() function. This will automatically + enable WWDG and start its downcounter. Time reference can be taken from + function exit. Care must be taken to provide a counter value + greater than 0x40 to prevent generation of immediate reset. + (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is + generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is + triggered by the interrupt service routine, flag will be automatically + cleared and HAL_WWDG_WakeupCallback user callback will be executed. User + can add his own code by customization of callback HAL_WWDG_WakeupCallback. (+) Then the application program must refresh the WWDG counter at regular intervals during normal operation to prevent an MCU reset, using HAL_WWDG_Refresh() function. This operation must occur only when @@ -64,7 +72,7 @@ ============================= [..] - The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions HAL_WWDG_RegisterCallback() to register a user callback. @@ -96,7 +104,7 @@ *** WWDG HAL driver macros list *** =================================== [..] - Below the list of most used macros in WWDG HAL driver. + Below the list of available macros in WWDG HAL driver. (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags @@ -197,7 +205,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) #else /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /* Set WWDG Counter */ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); @@ -242,7 +250,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -303,7 +312,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD return status; } -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} @@ -371,7 +380,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) #else /* Early Wakeup callback */ HAL_WWDG_EarlyWakeupCallback(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } } } diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c index 2aa46ee..f79f745 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c @@ -67,6 +67,12 @@ #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL) #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */ +/* after the channel configuration has been changed. */ +/* Driver timeout is approximated to 6 CPU cycles. */ +#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL) +#endif /** * @} @@ -80,6 +86,22 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* common to several ADC instances. */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ + ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ + ) +#else #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ @@ -97,9 +119,19 @@ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ ) +#endif /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC instance. */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_LL_ADC_CLOCK(__CLOCK__) \ + ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \ + ) + +#endif #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ @@ -112,13 +144,32 @@ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ ) +#if defined (ADC_SUPPORT_2_5_MSPS) #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ + || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \ + || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \ ) - +#else +#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ + ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ + || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ + ) +#endif /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC group regular */ +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) +#else #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ @@ -130,6 +181,7 @@ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) +#endif #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ @@ -147,6 +199,25 @@ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ ) +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \ + ( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \ + || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \ + ) +#endif + +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ + ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ + ) +#else #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ @@ -165,7 +236,13 @@ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ ) - +#endif +#if defined (ADC_SUPPORT_2_5_MSPS) +#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + ) +#else #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ @@ -177,7 +254,7 @@ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ ) - +#endif /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC group injected */ #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ @@ -245,11 +322,19 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Force reset of ADC clock (core clock) */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); + + /* Release reset of ADC clock (core clock) */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); +#else /* Force reset of ADC clock (core clock) */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC); /* Release reset of ADC clock (core clock) */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC); +#endif /* ADC_SUPPORT_2_5_MSPS */ return SUCCESS; } @@ -342,7 +427,11 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) /* Set ADC_CommonInitStruct fields to default values */ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ +#if defined (ADC_SUPPORT_2_5_MSPS) + ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; +#else ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; +#endif /* ADC_SUPPORT_2_5_MSPS */ } @@ -387,6 +476,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) } } +#if !defined (ADC_SUPPORT_2_5_MSPS) /* Set ADC group injected trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ @@ -414,12 +504,28 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) break; } } +#else + /* Wait for ADC conversions are effectively stopped */ + timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; + while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL) + { + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } +#endif /* ADC_SUPPORT_2_5_MSPS */ +#if !defined (ADC_SUPPORT_2_5_MSPS) /* Flush group injected contexts queue (register JSQR): */ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ /* contexts queue is maintained with the last active context). */ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); +#endif /* Disable the ADC instance */ LL_ADC_Disable(ADCx); @@ -438,11 +544,19 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) } /* Check whether ADC state is compliant with expected state */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if (READ_BIT(ADCx->CR, + (ADC_CR_ADSTP | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN ) + ) + == 0UL) +#else if (READ_BIT(ADCx->CR, (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) ) == 0UL) +#endif { /* ========== Reset ADC registers ========== */ /* Reset register IER */ @@ -452,12 +566,17 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | LL_ADC_IT_EOS | LL_ADC_IT_OVR | LL_ADC_IT_EOSMP +#if !defined (ADC_SUPPORT_2_5_MSPS) | LL_ADC_IT_JEOC | LL_ADC_IT_JEOS | LL_ADC_IT_JQOVF +#endif | LL_ADC_IT_AWD1 | LL_ADC_IT_AWD2 | LL_ADC_IT_AWD3 +#if defined (ADC_SUPPORT_2_5_MSPS) + | LL_ADC_IT_CCRDY +#endif ) ); @@ -468,15 +587,26 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_EOSMP +#if !defined (ADC_SUPPORT_2_5_MSPS) | LL_ADC_FLAG_JEOC | LL_ADC_FLAG_JEOS | LL_ADC_FLAG_JQOVF +#endif | LL_ADC_FLAG_AWD1 | LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD3 +#if defined (ADC_SUPPORT_2_5_MSPS) + | LL_ADC_FLAG_CCRDY +#endif ) ); +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN); +#else /* Reset register CR */ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ @@ -489,7 +619,66 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* already done above. */ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); +#endif + +#if defined (ADC_SUPPORT_2_5_MSPS) + /* Reset register CFGR1 */ + CLEAR_BIT(ADCx->CFGR1, + ( ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN + | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD + | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES + | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ) + ); + /* Reset register SMPR */ + CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL); + + /* Reset register TR1 */ + MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); + + /* Reset register CHSELR */ + CLEAR_BIT(ADCx->CHSELR, + ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 + | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 + | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 + | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 + | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ) + ); + + /* Wait for ADC channel configuration ready */ + timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES; + while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL) + { + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } + + /* Clear flag ADC channel configuration ready */ + LL_ADC_ClearFlag_CCRDY(ADCx); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset register CALFACT */ + CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT); + + /* Reset register CFGR2 */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + /* Note: Register reset last due to selection of asynchronous clock, */ + /* ADC clock then depends of configuration clock source at system */ + /* level. */ + CLEAR_BIT(ADCx->CFGR2, + ( ADC_CFGR2_CKMODE + | ADC_CFGR2_LFTRIG ) + ); + +#else /* Reset register CFGR */ MODIFY_REG(ADCx->CFGR, (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN @@ -507,6 +696,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) ); + /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 @@ -585,6 +775,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register CALFACT */ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); +#endif } else { @@ -640,6 +831,9 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); +#if defined (ADC_SUPPORT_2_5_MSPS) + assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock)); +#endif assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); @@ -653,6 +847,24 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* - Set ADC data resolution */ /* - Set ADC conversion data alignment */ /* - Set ADC low power mode */ +#if defined (ADC_SUPPORT_2_5_MSPS) + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_RES + | ADC_CFGR1_ALIGN + | ADC_CFGR1_WAIT + | ADC_CFGR1_AUTOFF + , + ADC_InitStruct->Resolution + | ADC_InitStruct->DataAlignment + | ADC_InitStruct->LowPowerMode + ); + + MODIFY_REG(ADCx->CFGR2, + ADC_CFGR2_CKMODE + , + ADC_InitStruct->Clock + ); +#else MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES | ADC_CFGR_ALIGN @@ -662,7 +874,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) | ADC_InitStruct->DataAlignment | ADC_InitStruct->LowPowerMode ); - +#endif } else { @@ -682,6 +894,9 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) { /* Set ADC_InitStruct fields to default values */ /* Set fields of ADC instance */ +#if defined (ADC_SUPPORT_2_5_MSPS) + ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; +#endif ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; @@ -706,6 +921,9 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. + * @note On devices STM32WB10xx, STM32WB15xx: Before using this function, + * ADC group regular sequencer must be configured: refer to function + * @ref LL_ADC_REG_SetSequencerConfigurable(). * @note After using this function, other features must be configured * using LL unitary functions. * The minimum configuration remaining to be done is: @@ -727,11 +945,34 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); +#if defined (ADC_SUPPORT_2_5_MSPS) + if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); + } + if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) + || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + ) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + } +#else assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } +#endif assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); @@ -751,6 +992,52 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular overrun behavior */ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if( (LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) + || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + ) + { + /* Case of sequencer mode fixed + or sequencer length >= 2 ranks with sequencer mode fully configurable: + discontinuous mode configured */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_EXTSEL + | ADC_CFGR1_EXTEN + | ADC_CFGR1_DISCEN + | ADC_CFGR1_CONT + | ADC_CFGR1_DMAEN + | ADC_CFGR1_DMACFG + | ADC_CFGR1_OVRMOD + , + ADC_REG_InitStruct->TriggerSource + | ADC_REG_InitStruct->SequencerDiscont + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->DMATransfer + | ADC_REG_InitStruct->Overrun + ); + } + else + { + /* Case of sequencer mode fully configurable + and sequencer length 1 rank (sequencer disabled): + discontinuous mode discarded (fixed to disable) */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_EXTSEL + | ADC_CFGR1_EXTEN + | ADC_CFGR1_DISCEN + | ADC_CFGR1_CONT + | ADC_CFGR1_DMAEN + | ADC_CFGR1_DMACFG + | ADC_CFGR1_OVRMOD + , + ADC_REG_InitStruct->TriggerSource + | LL_ADC_REG_SEQ_DISCONT_DISABLE + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->DMATransfer + | ADC_REG_InitStruct->Overrun + ); + } +#else if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, @@ -789,9 +1076,17 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_REG_InitStruct->Overrun ); } +#endif /* ADC_SUPPORT_2_5_MSPS */ /* Set ADC group regular sequencer length and scan direction */ +#if defined (ADC_SUPPORT_2_5_MSPS) + if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) + { + LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + } +#else LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); +#endif } else { @@ -821,6 +1116,9 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; } +#if defined (ADC_SUPPORT_2_5_MSPS) +/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */ +#else /** * @brief Initialize some features of ADC group injected. * @note These parameters have an impact on ADC scope: ADC group injected. @@ -847,6 +1145,12 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); + * @note Caution if feature ADC group injected contexts queue is enabled + * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ): + * using successively several times this function will appear as + * having no effect. + * To set several features of ADC group injected, use + * function @ref LL_ADC_INJ_ConfigQueueContext(). * @param ADCx ADC instance * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * @retval An ErrorStatus enumeration value: @@ -934,6 +1238,7 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; } +#endif /** * @} */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c index 772ae4c..7495e21 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c @@ -55,20 +55,28 @@ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \ ) -/* Note: On this STM32 serie, comparator input plus parameters are */ +/* Note: On this STM32 series, comparator input plus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ +#if defined(LL_COMP_INPUT_PLUS_IO1) #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ ) +#else +#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ + ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ + || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ + ) +#endif -/* Note: On this STM32 serie, comparator input minus parameters are */ +/* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ +#if defined(LL_COMP_INPUT_MINUS_IO2) #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ @@ -80,6 +88,18 @@ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5) \ ) +#else +#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5) \ + ) +#endif #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \ ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \ @@ -226,7 +246,11 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) { /* Set COMP_InitStruct fields to default values */ COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_ULTRALOWPOWER; +#if defined(LL_COMP_INPUT_PLUS_IO1) COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1; +#else + COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO2; +#endif COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT; COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE; COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED; diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c index f862bf5..5d99575 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c @@ -145,7 +145,7 @@ * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @arg @ref LL_DMA_CHANNEL_ALL - * @retval An ErrorStatus enumeration value: + * @retval ErrorStatus * - SUCCESS: DMA registers are de-initialized * - ERROR: DMA registers are not de-initialized */ @@ -226,7 +226,6 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) /* Reset interrupt pending bits for DMAx Channel5 */ LL_DMA_ClearFlag_GI5(DMAx); } - else if (Channel == LL_DMA_CHANNEL_6) { /* Reset interrupt pending bits for DMAx Channel6 */ @@ -261,7 +260,7 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: + * @retval ErrorStatus * - SUCCESS: DMA registers are initialized * - ERROR: Not applicable */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c index ea02936..bc305e6 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c @@ -196,7 +196,9 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; +#if defined(LPTIM_OR_OR) uint32_t tmpOR; +#endif /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); @@ -224,7 +226,9 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) tmpCFGR = LPTIMx->CFGR; tmpCMP = LPTIMx->CMP; tmpARR = LPTIMx->ARR; +#if defined(LPTIM_OR_OR) tmpOR = LPTIMx->OR; +#endif /************* Reset LPTIM ************/ (void)LL_LPTIM_DeInit(LPTIMx); @@ -290,7 +294,9 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) LPTIMx->CR &= ~(LPTIM_CR_ENABLE); LPTIMx->IER = tmpIER; LPTIMx->CFGR = tmpCFGR; +#if defined(LPTIM_OR_OR) LPTIMx->OR = tmpOR; +#endif __enable_irq(); } diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c index 33723ca..7036dc5 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c @@ -109,10 +109,12 @@ ErrorStatus LL_PWR_DeInit(void) /* Clear all flags */ LL_PWR_WriteReg(SCR, LL_PWR_SCR_CC2HF - | LL_PWR_SCR_C802AF | LL_PWR_SCR_CBLEAF | LL_PWR_SCR_CCRPEF +#if defined(PWR_CR3_E802A) + | LL_PWR_SCR_C802AF | LL_PWR_SCR_C802WUF +#endif | LL_PWR_SCR_CBLEWUF #if defined(PWR_CR5_SMPSEN) | LL_PWR_SCR_CBORHF diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c index 23aa838..ee185ee 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c @@ -72,9 +72,6 @@ #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) -#if defined(SPI_I2S_SUPPORT) -#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE) -#endif /** * @} */ @@ -96,9 +93,6 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); #endif -#if defined(SPI_I2S_SUPPORT) -uint32_t RCC_PLL_GetFreqDomain_I2S(void); -#endif uint32_t RCC_GetSystemClockFreq(void); @@ -190,13 +184,17 @@ ErrorStatus LL_RCC_DeInit(void) LL_RCC_WriteReg(CIER, 0x00000000U); /* Clear all interrupt flags */ -#if defined(SAI1) - vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLLSAI1RDYC | \ - RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC; -#else vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \ - RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC; + RCC_CICR_CSSC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC; + +#if defined(SAI1) + vl_mask |= RCC_CICR_PLLSAI1RDYC; +#endif + +#if defined(RCC_HSI48_SUPPORT) + vl_mask |= RCC_CICR_HSI48RDYC; #endif + LL_RCC_WriteReg(CICR, vl_mask); /* Clear reset flags */ @@ -210,8 +208,10 @@ ErrorStatus LL_RCC_DeInit(void) /* RF Wakeup Clock Source selection */ LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_NONE); +#if defined(RCC_HSI48_SUPPORT) /* HSI48 reset */ LL_RCC_HSI48_Disable(); +#endif /* HSECR register write unlock & then reset*/ LL_RCC_WriteReg(HSECR, HSE_CONTROL_UNLOCK_KEY); @@ -407,7 +407,8 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) * @brief Return I2Cx clock frequency * @param I2CxSource This parameter can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE - * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) + * @note (*) Value not defined for all devices * @retval I2C clock frequency (in Hz) * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready */ @@ -689,6 +690,7 @@ uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource) } break; +#if defined(RCC_HSI48_SUPPORT) case LL_RCC_CLK48_CLKSOURCE_HSI48: /* HSI48 clock used as CLK48 clock source */ default: if (LL_RCC_HSI48_IsReady() == 1U) @@ -696,6 +698,11 @@ uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource) clk48_frequency = HSI48_VALUE; } break; +#else + default: + /* Nothing to do */ + break; +#endif } return clk48_frequency; @@ -853,7 +860,6 @@ uint32_t LL_RCC_GetRTCClockFreq(void) uint32_t LL_RCC_GetRFWKPClockFreq(void) { uint32_t rfwkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - uint32_t temp = LL_RCC_LSI2_IsReady(); /* RTCCLK clock frequency */ switch (LL_RCC_GetRFWKPClockSource()) @@ -865,13 +871,6 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void) } break; - case LL_RCC_RFWKP_CLKSOURCE_LSI: /* LSI clock used as RF Wakeup clock source */ - if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL)) - { - rfwkp_frequency = LSI_VALUE; - } - break; - case LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024: /* HSE clock used as RF Wakeup clock source */ rfwkp_frequency = HSE_VALUE / 1024U; break; @@ -885,46 +884,6 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void) return rfwkp_frequency; } -#if defined(SPI_I2S_SUPPORT) -/** - * @brief Return I2Sx clock frequency - * @param I2SxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S_CLKSOURCE - * @retval I2S clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLLs (PLL) is not ready - */ -uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) -{ - uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); - - /* I2SCLK clock frequency */ - switch (LL_RCC_GetI2SClockSource(I2SxSource)) - { - case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */ - if (LL_RCC_PLL_IsReady() == 1U) - { - i2s_frequency = RCC_PLL_GetFreqDomain_I2S(); - } - break; - - case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S2 Clock is External clock */ - i2s_frequency = EXTERNAL_CLOCK_VALUE; - break; - - case LL_RCC_I2S_CLKSOURCE_HSI: /* HSI clock used as I2S clock source */ - default: - if (LL_RCC_HSI_IsReady() == 1U) - { - i2s_frequency = HSI_VALUE; - } - break; - } - return i2s_frequency; -} -#endif /** * @} @@ -1363,35 +1322,6 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) } #endif -#if defined(SPI_I2S_SUPPORT) -/** - * @brief Return PLL clock frequency used for I2S domain - * @retval PLL clock frequency (in Hz) - */ -uint32_t RCC_PLL_GetFreqDomain_I2S(void) -{ - uint32_t pllinputfreq, pllsource; - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - I2S Domain clock = PLL_VCO / PLLP - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllinputfreq = HSE_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); -} -#endif /** * @} diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c index 1301719..8d8c422 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c @@ -21,7 +21,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_ll_spi.h" #include "stm32wbxx_ll_bus.h" -#include "stm32wbxx_ll_rcc.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" @@ -233,10 +232,6 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) status = SUCCESS; } -#if defined (SPI_I2S_SUPPORT) - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); -#endif /* SPI_I2S_SUPPORT */ return status; } @@ -273,251 +268,6 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * @} */ -#if defined(SPI_I2S_SUPPORT) -/** @addtogroup I2S_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2S_LL_Private_Constants I2S Private Constants - * @{ - */ -/* I2S registers Masks */ -#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ - SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ - SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) - -#define I2S_I2SPR_CLEAR_MASK 0x0002U -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2S_LL_Private_Macros I2S Private Macros - * @{ - */ - -#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) - -#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ - || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) - -#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ - || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) - -#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ - || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) - -#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ - || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) - -#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ - && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ - || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) - -#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) - -#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ - || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2S_LL_Exported_Functions - * @{ - */ - -/** @addtogroup I2S_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the SPI/I2S registers to their default reset values. - * @param SPIx SPI Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: SPI registers are de-initialized - * - ERROR: SPI registers are not de-initialized - */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) -{ - return LL_SPI_DeInit(SPIx); -} - -/** - * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @param SPIx SPI Instance - * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: SPI registers are Initialized - * - ERROR: SPI registers are not Initialized - */ -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) -{ - uint32_t i2sdiv = 2U; - uint32_t i2sodd = 0U; - uint32_t packetlength = 1U; - uint32_t tmp; - uint32_t sourceclock; - ErrorStatus status = ERROR; - - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(SPIx)); - assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); - assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); - assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); - assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); - assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); - assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); - - if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) - { - /*---------------------------- SPIx I2SCFGR Configuration -------------------- - * Configure SPIx I2SCFGR with parameters: - * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit - * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits - * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits - * - ClockPolarity: SPI_I2SCFGR_CKPOL bit - */ - - /* Write to SPIx I2SCFGR */ - MODIFY_REG(SPIx->I2SCFGR, - I2S_I2SCFGR_CLEAR_MASK, - I2S_InitStruct->Mode | I2S_InitStruct->Standard | - I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | - SPI_I2SCFGR_I2SMOD); - - /*---------------------------- SPIx I2SPR Configuration ---------------------- - * Configure SPIx I2SPR with parameters: - * - MCLKOutput: SPI_I2SPR_MCKOE bit - * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits - */ - - /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) - * else, default values are used: i2sodd = 0U, i2sdiv = 2U. - */ - if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) - { - /* Check the frame length (For the Prescaler computing) - * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). - */ - if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) - { - /* Packet length is 32 bits */ - packetlength = 2U; - } - - /* If an external I2S clock has to be used, the specific define should be set - in the project configuration or in the stm32wbxx_ll_rcc.h file */ - /* Get the I2S source clock value */ - sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE); - - /* Compute the Real divider depending on the MCLK output state with a floating point */ - if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) - { - /* MCLK output is enabled */ - tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); - } - else - { - /* MCLK output is disabled */ - tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); - } - - /* Remove the floating point */ - tmp = tmp / 10U; - - /* Check the parity of the divider */ - i2sodd = (tmp & (uint16_t)0x0001U); - - /* Compute the i2sdiv prescaler */ - i2sdiv = ((tmp - i2sodd) / 2U); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (i2sodd << 8U); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) - { - /* Set the default values */ - i2sdiv = 2U; - i2sodd = 0U; - } - - /* Write to SPIx I2SPR register the computed value */ - WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); - - status = SUCCESS; - } - return status; -} - -/** - * @brief Set each @ref LL_I2S_InitTypeDef field to default value. - * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) -{ - /*--------------- Reset I2S init structure parameters values -----------------*/ - I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; - I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; - I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; - I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; - I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; - I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; -} - -/** - * @brief Set linear and parity prescaler. - * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n - * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). - * @param SPIx SPI Instance - * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. - * @param PrescalerParity This parameter can be one of the following values: - * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN - * @arg @ref LL_I2S_PRESCALER_PARITY_ODD - * @retval None - */ -void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) -{ - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(SPIx)); - assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); - assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); - - /* Write to SPIx I2SPR */ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* SPI_I2S_SUPPORT */ - #endif /* defined (SPI1) || defined (SPI2) */ /** diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c index ba79b2a..f07d16a 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c @@ -150,6 +150,9 @@ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) +#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) + #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) @@ -173,6 +176,9 @@ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) +#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) /** @@ -231,16 +237,20 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } +#if defined(TIM16) else if (TIMx == TIM16) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); } +#endif +#if defined(TIM17) else if (TIMx == TIM17) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); } +#endif else { result = ERROR; @@ -642,9 +652,11 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; + TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT; TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT; TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; } @@ -692,7 +704,9 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT if (IS_TIM_ADVANCED_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); } if (IS_TIM_BKIN2_INSTANCE(TIMx)) @@ -700,11 +714,13 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); + assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode)); /* Set the BREAK2 input related BDTR bit-fields */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode); } /* Set TIMx_BDTR */ diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c index 1e6b6ea..2a6d2a4 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c @@ -83,7 +83,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { - uint16_t winterruptmask; + uint32_t winterruptmask; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | @@ -92,7 +92,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Set interrupt mask */ - USBx->CNTR |= winterruptmask; + USBx->CNTR |= (uint16_t)winterruptmask; return HAL_OK; } @@ -105,7 +105,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { - uint16_t winterruptmask; + uint32_t winterruptmask; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | @@ -114,7 +114,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Clear interrupt mask */ - USBx->CNTR &= ~winterruptmask; + USBx->CNTR &= (uint16_t)(~winterruptmask); return HAL_OK; } @@ -155,13 +155,13 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) /* Init Device */ /*CNTR_FRES = 1*/ - USBx->CNTR = USB_CNTR_FRES; + USBx->CNTR = (uint16_t)USB_CNTR_FRES; /*CNTR_FRES = 0*/ - USBx->CNTR = 0; + USBx->CNTR = 0U; /*Clear pending interrupts*/ - USBx->ISTR = 0; + USBx->ISTR = 0U; /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; @@ -270,7 +270,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) break; } - PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX); + PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); @@ -591,13 +591,13 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) { /* disable all interrupts and force USB reset */ - USBx->CNTR = USB_CNTR_FRES; + USBx->CNTR = (uint16_t)USB_CNTR_FRES; /* clear interrupt status register */ - USBx->ISTR = 0; + USBx->ISTR = 0U; /* switch-off device */ - USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); + USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); return HAL_OK; } @@ -614,7 +614,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) if (address == 0U) { /* set device address and enable function */ - USBx->DADDR = USB_DADDR_EF; + USBx->DADDR = (uint16_t)USB_DADDR_EF; } return HAL_OK; @@ -628,7 +628,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ - USBx->BCDR |= USB_BCDR_DPPU; + USBx->BCDR |= (uint16_t)USB_BCDR_DPPU; return HAL_OK; } @@ -771,7 +771,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) { - USBx->CNTR |= USB_CNTR_RESUME; + USBx->CNTR |= (uint16_t)USB_CNTR_RESUME; return HAL_OK; } @@ -783,7 +783,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) { - USBx->CNTR &= ~(USB_CNTR_RESUME); + USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME); return HAL_OK; } diff --git a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c index ce9cbc1..d77d920 100644 --- a/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c +++ b/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c @@ -132,7 +132,6 @@ * @{ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK4_Frequency); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); @@ -249,6 +248,104 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) SystemCoreClock = HCLKFrequency; } +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLK4Frequency HCLK4 frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency) +{ + ErrorStatus status = ERROR; + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + uint16_t index; + uint32_t timeout; + uint32_t getlatency; +#if defined(PWR_CR1_VOS) + uint32_t voltagescaling = LL_PWR_GetRegulVoltageScaling(); + uint32_t maxfreq = (voltagescaling == LL_PWR_REGU_VOLTAGE_SCALE1) ? UTILS_MAX_FREQUENCY_SCALE1 : UTILS_MAX_FREQUENCY_SCALE2; +#else + uint32_t maxfreq = UTILS_MAX_FREQUENCY_SCALE1; +#endif + + /* Array used for FLASH latency according to HCLK4 Frequency */ + /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ + const uint32_t UTILS_CLK_SRC_RANGE_VOS1[] = {18000000U, 36000000U, 54000000U, UTILS_MAX_FREQUENCY_SCALE1}; + +#if defined(PWR_CR1_VOS) + /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ + const uint32_t UTILS_CLK_SRC_RANGE_VOS2[] = {6000000U, 12000000U, UTILS_MAX_FREQUENCY_SCALE2}; +#endif + + /* Flash Latency range */ + const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3}; + + /* Frequency cannot be equal to 0 or greater than max clock */ + if ((HCLK4Frequency > 0U) && (HCLK4Frequency <= maxfreq)) + { +#if defined(PWR_CR1_VOS) + if (voltagescaling == LL_PWR_REGU_VOLTAGE_SCALE1) + { + for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++) + { + if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index]) + { + latency = UTILS_LATENCY_RANGE[index]; + status = SUCCESS; + break; + } + } + } + else /* SCALE2 */ + { + for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS2); index++) + { + if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS2[index]) + { + latency = UTILS_LATENCY_RANGE[index]; + status = SUCCESS; + break; + } + } + } +#else + for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++) + { + if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index]) + { + latency = UTILS_LATENCY_RANGE[index]; + status = SUCCESS; + break; + } + } +#endif + } + + if (status != ERROR) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2U; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } + while ((getlatency != latency) && (timeout > 0U)); + + if (getlatency != latency) + { + status = ERROR; + } + } + return status; +} + /** * @brief This function configures system clock with MSI as clock source of the PLL * @note The application needs to ensure that PLL and PLLSAI1 are disabled. @@ -462,6 +559,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTyp /* Enable HSE if not enabled */ if (LL_RCC_HSE_IsReady() != 1U) { +#if defined(RCC_CR_HSEBYP) /* Check if need to enable HSE bypass feature or not */ if (HSEBypass == LL_UTILS_HSEBYPASS_ON) { @@ -471,7 +569,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTyp { LL_RCC_HSE_DisableBypass(); } - +#endif /* Enable HSE */ LL_RCC_HSE_Enable(); while (LL_RCC_HSE_IsReady() != 1U) @@ -510,84 +608,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTyp /** @addtogroup UTILS_LL_Private_Functions * @{ */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param HCLK4_Frequency HCLK4 frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK4_Frequency) -{ - ErrorStatus status = SUCCESS; - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - uint16_t index; - - /* Array used for FLASH latency according to HCLK4 Frequency */ - /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ - const uint32_t UTILS_CLK_SRC_RANGE_VOS1[] = {18000000U, 36000000U, 54000000U, UTILS_MAX_FREQUENCY_SCALE1}; - -#if defined(PWR_CR1_VOS) - /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ - const uint32_t UTILS_CLK_SRC_RANGE_VOS2[] = {6000000U, 12000000U, UTILS_MAX_FREQUENCY_SCALE2}; -#endif - - /* Flash Latency range */ - const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3}; - - /* Frequency cannot be equal to 0 */ - if (HCLK4_Frequency == 0U) - { - status = ERROR; - } - else - { -#if defined(PWR_CR1_VOS) - if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) - { - for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++) - { - if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index]) - { - latency = UTILS_LATENCY_RANGE[index]; - break; - } - } - } - else /* SCALE2 */ - { - for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS2); index++) - { - if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS2[index]) - { - latency = UTILS_LATENCY_RANGE[index]; - break; - } - } - } -#else - for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++) - { - if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index]) - { - latency = UTILS_LATENCY_RANGE[index]; - break; - } - } -#endif - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - while (LL_FLASH_GetLatency() != latency) - { - } - } - return status; -} - /** * @brief Function to check that PLL can be modified * @param PLL_InputFrequency PLL input frequency (in Hz) @@ -679,7 +699,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if (hclks_frequency_current < hclks_frequency_target) { /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(hclks_frequency_target); + status = LL_SetFlashLatency(hclks_frequency_target); } /* Update system clock configuration */ @@ -712,7 +732,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if (hclks_frequency_current > hclks_frequency_target) { /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(hclks_frequency_target); + status = LL_SetFlashLatency(hclks_frequency_target); } /* Update SystemCoreClock variable */