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stm32lib/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32wbxx_hal.h

  4.   * @author  MCD Application Team

  5.   * @brief   This file contains all the functions prototypes for the HAL

  6.   *          module driver.

  7.   ******************************************************************************

  8.   * @attention

  9.   *

  10.   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

  11.   * All rights reserved.</center></h2>

  12.   *

  13.   * This software component is licensed by ST under BSD 3-Clause license,

  14.   * the "License"; You may not use this file except in compliance with the

  15.   * License. You may obtain a copy of the License at:

  16.   *                        opensource.org/licenses/BSD-3-Clause

  17.   *

  18.   ******************************************************************************

  19.   */

  20. 

  21. /* Define to prevent recursive inclusion -------------------------------------*/

  22. #ifndef STM32WBxx_HAL_H

  23. #define STM32WBxx_HAL_H

  24. 

  25. #ifdef __cplusplus

  26.  extern "C" {

  27. #endif

  28. 

  29. /* Includes ------------------------------------------------------------------*/

  30. #include "stm32wbxx_hal_conf.h"

  31. #include "stm32wbxx_ll_system.h"

  32. 

  33. /** @addtogroup STM32WBxx_HAL_Driver

  34.   * @{

  35.   */

  36. 

  37. /** @defgroup HAL HAL

  38.   * @{

  39.   */

  40. 

  41. /** @defgroup HAL_TICK_FREQ Tick Frequency

  42.   * @{

  43.   */

  44. typedef enum

  45. {

  46.   HAL_TICK_FREQ_10HZ         = 100U,

  47.   HAL_TICK_FREQ_100HZ        = 10U,

  48.   HAL_TICK_FREQ_1KHZ         = 1U,

  49.   HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ

  50. } HAL_TickFreqTypeDef;

  51. 

  52. /**

  53.   * @}

  54.   */

  55. 

  56. /* Exported constants --------------------------------------------------------*/

  57. /** @defgroup HAL_Exported_Constants HAL Exported Constants

  58.   * @{

  59.   */

  60. 

  61. /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants

  62.   * @{

  63.   */

  64. 

  65. /** @defgroup SYSCFG_BootMode BOOT Mode

  66.   * @{

  67.   */

  68. #define SYSCFG_BOOT_MAINFLASH           LL_SYSCFG_REMAP_FLASH           /*!< Main Flash memory mapped at 0x00000000   */

  69. #define SYSCFG_BOOT_SYSTEMFLASH         LL_SYSCFG_REMAP_SYSTEMFLASH     /*!< System Flash memory mapped at 0x00000000 */

  70. #define SYSCFG_BOOT_SRAM                LL_SYSCFG_REMAP_SRAM            /*!< SRAM1 mapped at 0x00000000               */

  71. #if defined(LL_SYSCFG_REMAP_QUADSPI)

  72. #define SYSCFG_BOOT_QUADSPI             LL_SYSCFG_REMAP_QUADSPI         /*!< QUADSPI memory mapped at 0x00000000      */

  73. #endif

  74. /**

  75.   * @}

  76.   */

  77. 

  78. /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts

  79.   * @{

  80.   */

  81. #define SYSCFG_IT_FPU_IOC               SYSCFG_CFGR1_FPU_IE_0           /*!< Floating Point Unit Invalid operation Interrupt */

  82. #define SYSCFG_IT_FPU_DZC               SYSCFG_CFGR1_FPU_IE_1           /*!< Floating Point Unit Divide-by-zero Interrupt    */

  83. #define SYSCFG_IT_FPU_UFC               SYSCFG_CFGR1_FPU_IE_2           /*!< Floating Point Unit Underflow Interrupt         */

  84. #define SYSCFG_IT_FPU_OFC               SYSCFG_CFGR1_FPU_IE_3           /*!< Floating Point Unit Overflow Interrupt          */

  85. #define SYSCFG_IT_FPU_IDC               SYSCFG_CFGR1_FPU_IE_4           /*!< Floating Point Unit Input denormal Interrupt    */

  86. #define SYSCFG_IT_FPU_IXC               SYSCFG_CFGR1_FPU_IE_5           /*!< Floating Point Unit Inexact Interrupt           */

  87. 

  88. /**

  89.   * @}

  90.   */

  91. 

  92. /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)

  93.   * @{

  94.   */

  95. #define SYSCFG_SRAM2WRP_PAGE0           LL_SYSCFG_SRAM2WRP_PAGE0        /*!< SRAM2A Write protection page 0  */

  96. #define SYSCFG_SRAM2WRP_PAGE1           LL_SYSCFG_SRAM2WRP_PAGE1        /*!< SRAM2A Write protection page 1  */

  97. #define SYSCFG_SRAM2WRP_PAGE2           LL_SYSCFG_SRAM2WRP_PAGE2        /*!< SRAM2A Write protection page 2  */

  98. #define SYSCFG_SRAM2WRP_PAGE3           LL_SYSCFG_SRAM2WRP_PAGE3        /*!< SRAM2A Write protection page 3  */

  99. #define SYSCFG_SRAM2WRP_PAGE4           LL_SYSCFG_SRAM2WRP_PAGE4        /*!< SRAM2A Write protection page 4  */

  100. #define SYSCFG_SRAM2WRP_PAGE5           LL_SYSCFG_SRAM2WRP_PAGE5        /*!< SRAM2A Write protection page 5  */

  101. #define SYSCFG_SRAM2WRP_PAGE6           LL_SYSCFG_SRAM2WRP_PAGE6        /*!< SRAM2A Write protection page 6  */

  102. #define SYSCFG_SRAM2WRP_PAGE7           LL_SYSCFG_SRAM2WRP_PAGE7        /*!< SRAM2A Write protection page 7  */

  103. #define SYSCFG_SRAM2WRP_PAGE8           LL_SYSCFG_SRAM2WRP_PAGE8        /*!< SRAM2A Write protection page 8  */

  104. #define SYSCFG_SRAM2WRP_PAGE9           LL_SYSCFG_SRAM2WRP_PAGE9        /*!< SRAM2A Write protection page 9  */

  105. #define SYSCFG_SRAM2WRP_PAGE10          LL_SYSCFG_SRAM2WRP_PAGE10       /*!< SRAM2A Write protection page 10 */

  106. #define SYSCFG_SRAM2WRP_PAGE11          LL_SYSCFG_SRAM2WRP_PAGE11       /*!< SRAM2A Write protection page 11 */

  107. #define SYSCFG_SRAM2WRP_PAGE12          LL_SYSCFG_SRAM2WRP_PAGE12       /*!< SRAM2A Write protection page 12 */

  108. #define SYSCFG_SRAM2WRP_PAGE13          LL_SYSCFG_SRAM2WRP_PAGE13       /*!< SRAM2A Write protection page 13 */

  109. #define SYSCFG_SRAM2WRP_PAGE14          LL_SYSCFG_SRAM2WRP_PAGE14       /*!< SRAM2A Write protection page 14 */

  110. #define SYSCFG_SRAM2WRP_PAGE15          LL_SYSCFG_SRAM2WRP_PAGE15       /*!< SRAM2A Write protection page 15 */

  111. #define SYSCFG_SRAM2WRP_PAGE16          LL_SYSCFG_SRAM2WRP_PAGE16       /*!< SRAM2A Write protection page 16 */

  112. #define SYSCFG_SRAM2WRP_PAGE17          LL_SYSCFG_SRAM2WRP_PAGE17       /*!< SRAM2A Write protection page 17 */

  113. #define SYSCFG_SRAM2WRP_PAGE18          LL_SYSCFG_SRAM2WRP_PAGE18       /*!< SRAM2A Write protection page 18 */

  114. #define SYSCFG_SRAM2WRP_PAGE19          LL_SYSCFG_SRAM2WRP_PAGE19       /*!< SRAM2A Write protection page 19 */

  115. #define SYSCFG_SRAM2WRP_PAGE20          LL_SYSCFG_SRAM2WRP_PAGE20       /*!< SRAM2A Write protection page 20 */

  116. #define SYSCFG_SRAM2WRP_PAGE21          LL_SYSCFG_SRAM2WRP_PAGE21       /*!< SRAM2A Write protection page 21 */

  117. #define SYSCFG_SRAM2WRP_PAGE22          LL_SYSCFG_SRAM2WRP_PAGE22       /*!< SRAM2A Write protection page 22 */

  118. #define SYSCFG_SRAM2WRP_PAGE23          LL_SYSCFG_SRAM2WRP_PAGE23       /*!< SRAM2A Write protection page 23 */

  119. #define SYSCFG_SRAM2WRP_PAGE24          LL_SYSCFG_SRAM2WRP_PAGE24       /*!< SRAM2A Write protection page 24 */

  120. #define SYSCFG_SRAM2WRP_PAGE25          LL_SYSCFG_SRAM2WRP_PAGE25       /*!< SRAM2A Write protection page 25 */

  121. #define SYSCFG_SRAM2WRP_PAGE26          LL_SYSCFG_SRAM2WRP_PAGE26       /*!< SRAM2A Write protection page 26 */

  122. #define SYSCFG_SRAM2WRP_PAGE27          LL_SYSCFG_SRAM2WRP_PAGE27       /*!< SRAM2A Write protection page 27 */

  123. #define SYSCFG_SRAM2WRP_PAGE28          LL_SYSCFG_SRAM2WRP_PAGE28       /*!< SRAM2A Write protection page 28 */

  124. #define SYSCFG_SRAM2WRP_PAGE29          LL_SYSCFG_SRAM2WRP_PAGE29       /*!< SRAM2A Write protection page 29 */

  125. #define SYSCFG_SRAM2WRP_PAGE30          LL_SYSCFG_SRAM2WRP_PAGE30       /*!< SRAM2A Write protection page 30 */

  126. #define SYSCFG_SRAM2WRP_PAGE31          LL_SYSCFG_SRAM2WRP_PAGE31       /*!< SRAM2A Write protection page 31 */

  127. 

  128. /**

  129.   * @}

  130.   */

  131. 

  132. /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)

  133.   * @{

  134.   */

  135. #define SYSCFG_SRAM2WRP_PAGE32          LL_SYSCFG_SRAM2WRP_PAGE32       /*!< SRAM2B Write protection page 32 */

  136. #define SYSCFG_SRAM2WRP_PAGE33          LL_SYSCFG_SRAM2WRP_PAGE33       /*!< SRAM2B Write protection page 33 */

  137. #define SYSCFG_SRAM2WRP_PAGE34          LL_SYSCFG_SRAM2WRP_PAGE34       /*!< SRAM2B Write protection page 34 */

  138. #define SYSCFG_SRAM2WRP_PAGE35          LL_SYSCFG_SRAM2WRP_PAGE35       /*!< SRAM2B Write protection page 35 */

  139. #if defined(LL_SYSCFG_SRAM2WRP_PAGE36)

  140. #define SYSCFG_SRAM2WRP_PAGE36          LL_SYSCFG_SRAM2WRP_PAGE36       /*!< SRAM2B Write protection page 36 */

  141. #define SYSCFG_SRAM2WRP_PAGE37          LL_SYSCFG_SRAM2WRP_PAGE37       /*!< SRAM2B Write protection page 37 */

  142. #define SYSCFG_SRAM2WRP_PAGE38          LL_SYSCFG_SRAM2WRP_PAGE38       /*!< SRAM2B Write protection page 38 */

  143. #define SYSCFG_SRAM2WRP_PAGE39          LL_SYSCFG_SRAM2WRP_PAGE39       /*!< SRAM2B Write protection page 39 */

  144. #define SYSCFG_SRAM2WRP_PAGE40          LL_SYSCFG_SRAM2WRP_PAGE40       /*!< SRAM2B Write protection page 40 */

  145. #define SYSCFG_SRAM2WRP_PAGE41          LL_SYSCFG_SRAM2WRP_PAGE41       /*!< SRAM2B Write protection page 41 */

  146. #define SYSCFG_SRAM2WRP_PAGE42          LL_SYSCFG_SRAM2WRP_PAGE42       /*!< SRAM2B Write protection page 42 */

  147. #define SYSCFG_SRAM2WRP_PAGE43          LL_SYSCFG_SRAM2WRP_PAGE43       /*!< SRAM2B Write protection page 43 */

  148. #define SYSCFG_SRAM2WRP_PAGE44          LL_SYSCFG_SRAM2WRP_PAGE44       /*!< SRAM2B Write protection page 44 */

  149. #define SYSCFG_SRAM2WRP_PAGE45          LL_SYSCFG_SRAM2WRP_PAGE45       /*!< SRAM2B Write protection page 45 */

  150. #define SYSCFG_SRAM2WRP_PAGE46          LL_SYSCFG_SRAM2WRP_PAGE46       /*!< SRAM2B Write protection page 46 */

  151. #define SYSCFG_SRAM2WRP_PAGE47          LL_SYSCFG_SRAM2WRP_PAGE47       /*!< SRAM2B Write protection page 47 */

  152. #define SYSCFG_SRAM2WRP_PAGE48          LL_SYSCFG_SRAM2WRP_PAGE48       /*!< SRAM2B Write protection page 48 */

  153. #define SYSCFG_SRAM2WRP_PAGE49          LL_SYSCFG_SRAM2WRP_PAGE49       /*!< SRAM2B Write protection page 49 */

  154. #define SYSCFG_SRAM2WRP_PAGE50          LL_SYSCFG_SRAM2WRP_PAGE50       /*!< SRAM2B Write protection page 50 */

  155. #define SYSCFG_SRAM2WRP_PAGE51          LL_SYSCFG_SRAM2WRP_PAGE51       /*!< SRAM2B Write protection page 51 */

  156. #define SYSCFG_SRAM2WRP_PAGE52          LL_SYSCFG_SRAM2WRP_PAGE52       /*!< SRAM2B Write protection page 52 */

  157. #define SYSCFG_SRAM2WRP_PAGE53          LL_SYSCFG_SRAM2WRP_PAGE53       /*!< SRAM2B Write protection page 53 */

  158. #define SYSCFG_SRAM2WRP_PAGE54          LL_SYSCFG_SRAM2WRP_PAGE54       /*!< SRAM2B Write protection page 54 */

  159. #define SYSCFG_SRAM2WRP_PAGE55          LL_SYSCFG_SRAM2WRP_PAGE55       /*!< SRAM2B Write protection page 55 */

  160. #define SYSCFG_SRAM2WRP_PAGE56          LL_SYSCFG_SRAM2WRP_PAGE56       /*!< SRAM2B Write protection page 56 */

  161. #define SYSCFG_SRAM2WRP_PAGE57          LL_SYSCFG_SRAM2WRP_PAGE57       /*!< SRAM2B Write protection page 57 */

  162. #define SYSCFG_SRAM2WRP_PAGE58          LL_SYSCFG_SRAM2WRP_PAGE58       /*!< SRAM2B Write protection page 58 */

  163. #define SYSCFG_SRAM2WRP_PAGE59          LL_SYSCFG_SRAM2WRP_PAGE59       /*!< SRAM2B Write protection page 59 */

  164. #define SYSCFG_SRAM2WRP_PAGE60          LL_SYSCFG_SRAM2WRP_PAGE60       /*!< SRAM2B Write protection page 60 */

  165. #define SYSCFG_SRAM2WRP_PAGE61          LL_SYSCFG_SRAM2WRP_PAGE61       /*!< SRAM2B Write protection page 61 */

  166. #define SYSCFG_SRAM2WRP_PAGE62          LL_SYSCFG_SRAM2WRP_PAGE62       /*!< SRAM2B Write protection page 62 */

  167. #define SYSCFG_SRAM2WRP_PAGE63          LL_SYSCFG_SRAM2WRP_PAGE63       /*!< SRAM2B Write protection page 63 */

  168. #endif /* LL_SYSCFG_SRAM2WRP_PAGE36 */

  169. 

  170. /**

  171.   * @}

  172.   */

  173. 

  174. #if defined(VREFBUF)

  175. /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale

  176.   * @{

  177.   */

  178. #define SYSCFG_VREFBUF_VOLTAGE_SCALE0   LL_VREFBUF_VOLTAGE_SCALE0       /*!< Voltage reference scale 0 (VREF_OUT1) */

  179. #define SYSCFG_VREFBUF_VOLTAGE_SCALE1   LL_VREFBUF_VOLTAGE_SCALE1       /*!< Voltage reference scale 1 (VREF_OUT2) */

  180. 

  181. /**

  182.   * @}

  183.   */

  184. 

  185. /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance

  186.   * @{

  187.   */

  188. #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   0x00000000U             /*!< VREF_plus pin is internally connected to Voltage reference buffer output */

  189. #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_CSR_HIZ         /*!< VREF_plus pin is high impedance */

  190. 

  191. /**

  192.   * @}

  193.   */

  194. #endif /* VREFBUF */

  195. 

  196. /** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags

  197.   * @{

  198.   */

  199. 

  200. #define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF                /*!< SRAM2 parity error */

  201. #define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY            /*!< SRAM2 busy by erase operation */

  202. 

  203. /**

  204.   * @}

  205.   */

  206. 

  207. /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO

  208.   * @{

  209.   */

  210. 

  211. /** @brief  Fast-mode Plus driving capability on a specific GPIO

  212.   */

  213. #define SYSCFG_FASTMODEPLUS_PB6         SYSCFG_CFGR1_I2C_PB6_FMP        /*!< Enable Fast-mode Plus on PB6 */

  214. #define SYSCFG_FASTMODEPLUS_PB7         SYSCFG_CFGR1_I2C_PB7_FMP        /*!< Enable Fast-mode Plus on PB7 */

  215. #define SYSCFG_FASTMODEPLUS_PB8         SYSCFG_CFGR1_I2C_PB8_FMP        /*!< Enable Fast-mode Plus on PB8 */

  216. #define SYSCFG_FASTMODEPLUS_PB9         SYSCFG_CFGR1_I2C_PB9_FMP        /*!< Enable Fast-mode Plus on PB9 */

  217. 

  218. /**

  219.  * @}

  220.  */

  221. 

  222. /** @defgroup Secure_IP_Write_Access Secure IP Write Access

  223.   * @{

  224.   */

  225. #if defined(LL_SYSCFG_SECURE_ACCESS_AES1)

  226. #define HAL_SYSCFG_SECURE_ACCESS_AES1   LL_SYSCFG_SECURE_ACCESS_AES1    /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */

  227. #endif

  228. #define HAL_SYSCFG_SECURE_ACCESS_AES2   LL_SYSCFG_SECURE_ACCESS_AES2    /*!< Enabling the security access of Advanced Encryption Standard 2          */

  229. #define HAL_SYSCFG_SECURE_ACCESS_PKA    LL_SYSCFG_SECURE_ACCESS_PKA     /*!< Enabling the security access of Public Key Accelerator                  */

  230. #define HAL_SYSCFG_SECURE_ACCESS_RNG    LL_SYSCFG_SECURE_ACCESS_RNG     /*!< Enabling the security access of Random Number Generator                 */

  231. /**

  232.   * @}

  233.   */

  234. 

  235. /**

  236.   * @}

  237.   */

  238. 

  239. /**

  240.   * @}

  241.   */

  242. 

  243. /* Exported macros -----------------------------------------------------------*/

  244. /** @defgroup HAL_Exported_Macros HAL Exported Macros

  245.   * @{

  246.   */

  247. 

  248. /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros

  249.   * @{

  250.   */

  251. 

  252. /** @brief  Freeze and Unfreeze Peripherals in Debug mode

  253.   */

  254. 

  255. /** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP

  256.   * @{

  257.   */

  258. #if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

  259. #define __HAL_DBGMCU_FREEZE_TIM2()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

  260. #define __HAL_DBGMCU_UNFREEZE_TIM2()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

  261. #endif

  262. 

  263. #if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)

  264. #define __HAL_DBGMCU_FREEZE_RTC()               LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)

  265. #define __HAL_DBGMCU_UNFREEZE_RTC()             LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)

  266. #endif

  267. 

  268. #if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

  269. #define __HAL_DBGMCU_FREEZE_WWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

  270. #define __HAL_DBGMCU_UNFREEZE_WWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

  271. #endif

  272. 

  273. #if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

  274. #define __HAL_DBGMCU_FREEZE_IWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

  275. #define __HAL_DBGMCU_UNFREEZE_IWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

  276. #endif

  277. 

  278. #if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

  279. #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

  280. #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

  281. #endif

  282. 

  283. #if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

  284. #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

  285. #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

  286. #endif

  287. 

  288. #if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  289. #define __HAL_DBGMCU_FREEZE_LPTIM1()            LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  290. #define __HAL_DBGMCU_UNFREEZE_LPTIM1()          LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  291. #endif

  292. 

  293. #if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  294. #define __HAL_DBGMCU_FREEZE_LPTIM2()            LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  295. #define __HAL_DBGMCU_UNFREEZE_LPTIM2()          LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  296. #endif

  297. 

  298. #if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

  299. #define __HAL_DBGMCU_FREEZE_TIM1()              LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

  300. #define __HAL_DBGMCU_UNFREEZE_TIM1()            LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

  301. #endif

  302. 

  303. #if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

  304. #define __HAL_DBGMCU_FREEZE_TIM16()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

  305. #define __HAL_DBGMCU_UNFREEZE_TIM16()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

  306. #endif

  307. 

  308. #if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

  309. #define __HAL_DBGMCU_FREEZE_TIM17()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

  310. #define __HAL_DBGMCU_UNFREEZE_TIM17()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

  311. #endif

  312. 

  313. /**

  314.   * @}

  315.   */

  316. 

  317. /** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP

  318.   * @{

  319.   */

  320. #if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

  321. #define __HAL_C2_DBGMCU_FREEZE_TIM2()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

  322. #define __HAL_C2_DBGMCU_UNFREEZE_TIM2()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

  323. #endif

  324. 

  325. #if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

  326. #define __HAL_C2_DBGMCU_FREEZE_RTC()            LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

  327. #define __HAL_C2_DBGMCU_UNFREEZE_RTC()          LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

  328. #endif

  329. 

  330. #if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

  331. #define __HAL_C2_DBGMCU_FREEZE_IWDG()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

  332. #define __HAL_C2_DBGMCU_UNFREEZE_IWDG()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

  333. #endif

  334. 

  335. #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

  336. #define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

  337. #define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

  338. #endif

  339. 

  340. #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

  341. #define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

  342. #define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

  343. #endif

  344. 

  345. #if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  346. #define __HAL_C2_DBGMCU_FREEZE_LPTIM1()         LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  347. #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1()       LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  348. #endif

  349. 

  350. #if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  351. #define __HAL_C2_DBGMCU_FREEZE_LPTIM2()         LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  352. #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2()       LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  353. #endif

  354. 

  355. #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

  356. #define __HAL_C2_DBGMCU_FREEZE_TIM1()           LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

  357. #define __HAL_C2_DBGMCU_UNFREEZE_TIM1()         LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

  358. #endif

  359. 

  360. #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

  361. #define __HAL_C2_DBGMCU_FREEZE_TIM16()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

  362. #define __HAL_C2_DBGMCU_UNFREEZE_TIM16()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

  363. #endif

  364. 

  365. #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

  366. #define __HAL_C2_DBGMCU_FREEZE_TIM17()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

  367. #define __HAL_C2_DBGMCU_UNFREEZE_TIM17()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

  368. #endif

  369. 

  370. /**

  371.   * @}

  372.   */

  373. 

  374. /**

  375.   * @}

  376.   */

  377. 

  378. /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros

  379.   * @{

  380.   */

  381. 

  382. /** @brief  Main Flash memory mapped at 0x00000000

  383.   */

  384. #define __HAL_SYSCFG_REMAPMEMORY_FLASH()        LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)

  385. 

  386. /** @brief  System Flash memory mapped at 0x00000000

  387.   */

  388. #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()  LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)

  389. 

  390. /** @brief  Embedded SRAM mapped at 0x00000000

  391.   */

  392. #define __HAL_SYSCFG_REMAPMEMORY_SRAM()         LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)

  393. 

  394. #if defined(LL_SYSCFG_REMAP_QUADSPI)

  395. /** @brief  QUADSPI mapped at 0x00000000.

  396.   */

  397. #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()      LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)

  398. #endif

  399. 

  400. /**

  401.   * @brief  Return the boot mode as configured by user.

  402.   * @retval The boot mode as configured by user. The returned value can be one

  403.   *         of the following values:

  404.   *           @arg @ref SYSCFG_BOOT_MAINFLASH

  405.   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH

  406.   *           @arg @ref SYSCFG_BOOT_SRAM

  407. #if defined(LL_SYSCFG_REMAP_QUADSPI)

  408.   *           @arg @ref SYSCFG_BOOT_QUADSPI

  409. #endif

  410.   */

  411. #define __HAL_SYSCFG_GET_BOOT_MODE()            LL_SYSCFG_GetRemapMemory()

  412. 

  413. /** @brief  SRAM2 page 0 to 31 write protection enable macro

  414.   * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP

  415.   * @note   Write protection can only be disabled by a system reset

  416.   */

  417. /* Legacy define */

  418. #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE      __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE

  419. #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\

  420.                                                                 LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\

  421.                                                             }while(0)

  422. 

  423. /** @brief  SRAM2 page 32 to 63 write protection enable macro

  424.   * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63

  425.   * @note   Write protection can only be disabled by a system reset

  426.   */

  427. #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP2_PAGE((__SRAM2WRP__)));\

  428.                                                                 LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\

  429.                                                             }while(0)

  430. 

  431. /** @brief  SRAM2 page write protection unlock prior to erase

  432.   * @note   Writing a wrong key reactivates the write protection

  433.   */

  434. #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()         LL_SYSCFG_UnlockSRAM2WRP()

  435. 

  436. /** @brief  SRAM2 erase

  437.   * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase

  438.   */

  439. #define __HAL_SYSCFG_SRAM2_ERASE()              LL_SYSCFG_EnableSRAM2Erase()

  440. 

  441. /** @brief  Floating Point Unit interrupt enable/disable macros

  442.   * @param __INTERRUPT__  This parameter can be a value of @ref SYSCFG_FPU_Interrupts

  443.   */

  444. #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\

  445.                                                                 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\

  446.                                                             }while(0)

  447. 

  448. #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\

  449.                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\

  450.                                                             }while(0)

  451. 

  452. /** @brief  SYSCFG Break ECC lock.

  453.   *         Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.

  454.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  455.   */

  456. #define __HAL_SYSCFG_BREAK_ECC_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)

  457. 

  458. /** @brief  SYSCFG Break Cortex-M4 Lockup lock.

  459.   *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input.

  460.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  461.   */

  462. #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()        LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)

  463. 

  464. /** @brief  SYSCFG Break PVD lock.

  465.   *         Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

  466.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  467.   */

  468. #define __HAL_SYSCFG_BREAK_PVD_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)

  469. 

  470. /** @brief  SYSCFG Break SRAM2 parity lock.

  471.   *         Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input.

  472.   * @note   The selected configuration is locked and can be unlocked by system reset.

  473.   */

  474. #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()   LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)

  475. 

  476. /** @brief  Check SYSCFG flag is set or not.

  477.   * @param  __FLAG__  specifies the flag to check.

  478.   *         This parameter can be one of the following values:

  479.   *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag

  480.   *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing

  481.   * @retval The new state of __FLAG__ (TRUE or FALSE).

  482.   */

  483. #define __HAL_SYSCFG_GET_FLAG(__FLAG__)         ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)

  484. 

  485. /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.

  486.   */

  487. #define __HAL_SYSCFG_CLEAR_FLAG()               LL_SYSCFG_ClearFlag_SP()

  488. 

  489. /** @brief  Fast mode Plus driving capability enable/disable macros

  490.   * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO

  491.   */

  492. #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \

  493.                                                                 LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__);           \

  494.                                                                }while(0)

  495. 

  496. #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \

  497.                                                                 LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__);          \

  498.                                                                }while(0)

  499. 

  500. /**

  501.   * @}

  502.   */

  503. 

  504. /**

  505.   * @}

  506.   */

  507. 

  508. /* Private macros ------------------------------------------------------------*/

  509. /** @defgroup HAL_Private_Macros HAL Private Macros

  510.   * @{

  511.   */

  512. 

  513. /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros

  514.   * @{

  515.   */

  516. 

  517. #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)          ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \

  518.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \

  519.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \

  520.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \

  521.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \

  522.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))

  523. 

  524. #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)               (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))

  525. #define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__)              IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)

  526. 

  527. #if defined(VREFBUF)

  528. #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)      (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \

  529.                                                          ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))

  530. 

  531. #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)     (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \

  532.                                                          ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

  533. 

  534. #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)           (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

  535. #endif

  536. 

  537. #define IS_SYSCFG_FASTMODEPLUS(__PIN__)                 ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \

  538.                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \

  539.                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \

  540.                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))

  541. 

  542. #if defined(LL_SYSCFG_SECURE_ACCESS_AES1)

  543. #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__)            ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1)  == HAL_SYSCFG_SECURE_ACCESS_AES1)  || \

  544.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2)  == HAL_SYSCFG_SECURE_ACCESS_AES2)  || \

  545.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA)   == HAL_SYSCFG_SECURE_ACCESS_PKA)   || \

  546.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG)   == HAL_SYSCFG_SECURE_ACCESS_RNG))

  547. #else

  548. #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__)            ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2)  == HAL_SYSCFG_SECURE_ACCESS_AES2)  || \

  549.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA)   == HAL_SYSCFG_SECURE_ACCESS_PKA)   || \

  550.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG)   == HAL_SYSCFG_SECURE_ACCESS_RNG))

  551. #endif

  552. 

  553. /**

  554.   * @}

  555.   */

  556. 

  557. /**

  558.   * @}

  559.   */

  560. 

  561. /** @defgroup HAL_Private_Macros HAL Private Macros

  562.   * @{

  563.   */

  564. #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \

  565.                            ((FREQ) == HAL_TICK_FREQ_100HZ) || \

  566.                            ((FREQ) == HAL_TICK_FREQ_1KHZ))

  567. /**

  568.   * @}

  569.   */

  570. 

  571. 

  572. /* Exported functions --------------------------------------------------------*/

  573. 

  574. /** @defgroup HAL_Exported_Functions HAL Exported Functions

  575.   * @{

  576.   */

  577. 

  578. /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions

  579.   * @{

  580.   */

  581. 

  582. /* Initialization and Configuration functions  ******************************/

  583. HAL_StatusTypeDef HAL_Init(void);

  584. HAL_StatusTypeDef HAL_DeInit(void);

  585. void HAL_MspInit(void);

  586. void HAL_MspDeInit(void);

  587. 

  588. HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);

  589. 

  590. /**

  591.   * @}

  592.   */

  593. 

  594. /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions

  595.   * @{

  596.   */

  597. 

  598. /* Peripheral Control functions  ************************************************/

  599. void HAL_IncTick(void);

  600. void HAL_Delay(uint32_t Delay);

  601. uint32_t HAL_GetTick(void);

  602. uint32_t HAL_GetTickPrio(void);

  603. HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);

  604. HAL_TickFreqTypeDef HAL_GetTickFreq(void);

  605. void HAL_SuspendTick(void);

  606. void HAL_ResumeTick(void);

  607. uint32_t HAL_GetHalVersion(void);

  608. uint32_t HAL_GetREVID(void);

  609. uint32_t HAL_GetDEVID(void);

  610. uint32_t HAL_GetUIDw0(void);

  611. uint32_t HAL_GetUIDw1(void);

  612. uint32_t HAL_GetUIDw2(void);

  613. 

  614. /**

  615.   * @}

  616.   */

  617. 

  618. /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions

  619.   * @{

  620.   */

  621. 

  622. /* DBGMCU Peripheral Control functions  *****************************************/

  623. void HAL_DBGMCU_EnableDBGSleepMode(void);

  624. void HAL_DBGMCU_DisableDBGSleepMode(void);

  625. void HAL_DBGMCU_EnableDBGStopMode(void);

  626. void HAL_DBGMCU_DisableDBGStopMode(void);

  627. void HAL_DBGMCU_EnableDBGStandbyMode(void);

  628. void HAL_DBGMCU_DisableDBGStandbyMode(void);

  629. /**

  630.   * @}

  631.   */

  632. 

  633. /* Exported variables ---------------------------------------------------------*/

  634. /** @addtogroup HAL_Exported_Variables

  635.   * @{

  636.   */

  637. extern __IO uint32_t uwTick;

  638. extern uint32_t uwTickPrio;

  639. extern HAL_TickFreqTypeDef uwTickFreq;

  640. /**

  641.   * @}

  642.   */

  643. 

  644. /** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions

  645.   * @{

  646.   */

  647. 

  648. /* SYSCFG Control functions  ****************************************************/

  649. void HAL_SYSCFG_SRAM2Erase(void);

  650. void HAL_SYSCFG_DisableSRAMFetch(void);

  651. uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void);

  652. 

  653. #if defined(VREFBUF)

  654. void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);

  655. void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);

  656. void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);

  657. HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);

  658. void HAL_SYSCFG_DisableVREFBUF(void);

  659. #endif

  660. 

  661. void HAL_SYSCFG_EnableIOBooster(void);

  662. void HAL_SYSCFG_DisableIOBooster(void);

  663. #if defined(SYSCFG_CFGR1_ANASWVDD)

  664. void HAL_SYSCFG_EnableIOVdd(void);

  665. void HAL_SYSCFG_DisableIOVdd(void);

  666. #endif

  667. 

  668. void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess);

  669. void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess);

  670. uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess);

  671. 

  672. /**

  673.   * @}

  674.   */

  675. 

  676. /**

  677.   * @}

  678.   */

  679. 

  680. /**

  681.   * @}

  682.   */

  683. 

  684. /**

  685.   * @}

  686.   */

  687. 

  688. #ifdef __cplusplus

  689. }

  690. #endif

  691. 

  692. #endif /* STM32WBxx_HAL_H */

  693. 

  694. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/