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stm32lib/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32wbxx_ll_adc.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of ADC LL module.

  6.   ******************************************************************************

  7.   * @attention

  8.   *

  9.   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

  10.   * All rights reserved.</center></h2>

  11.   *

  12.   * This software component is licensed by ST under BSD 3-Clause license,

  13.   * the "License"; You may not use this file except in compliance with the

  14.   * License. You may obtain a copy of the License at:

  15.   *                        opensource.org/licenses/BSD-3-Clause

  16.   *

  17.   ******************************************************************************

  18.   */

  19. 

  20. /* Define to prevent recursive inclusion -------------------------------------*/

  21. #ifndef STM32WBxx_LL_ADC_H

  22. #define STM32WBxx_LL_ADC_H

  23. 

  24. #ifdef __cplusplus

  25. extern "C" {

  26. #endif

  27. 

  28. /* Includes ------------------------------------------------------------------*/

  29. #include "stm32wbxx.h"

  30. 

  31. /** @addtogroup STM32WBxx_LL_Driver

  32.   * @{

  33.   */

  34. 

  35. #if defined (ADC1)

  36. 

  37. /** @defgroup ADC_LL ADC

  38.   * @{

  39.   */

  40. 

  41. /* Private types -------------------------------------------------------------*/

  42. /* Private variables ---------------------------------------------------------*/

  43. 

  44. /* Private constants ---------------------------------------------------------*/

  45. /** @defgroup ADC_LL_Private_Constants ADC Private Constants

  46.   * @{

  47.   */

  48. 

  49. /* Internal mask for ADC group regular sequencer:                             */

  50. /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */

  51. /* - sequencer register offset                                                */

  52. /* - sequencer rank bits position into the selected register                  */

  53. 

  54. /* Internal register offset for ADC group regular sequencer configuration */

  55. /* (offset placed into a spare area of literal definition) */

  56. #if defined (ADC_SUPPORT_2_5_MSPS)

  57. /* No register ADC_SQRx on this ADC peripheral version */

  58. #else

  59. #define ADC_SQR1_REGOFFSET                 (0x00000000UL)

  60. #define ADC_SQR2_REGOFFSET                 (0x00000100UL)

  61. #define ADC_SQR3_REGOFFSET                 (0x00000200UL)

  62. #define ADC_SQR4_REGOFFSET                 (0x00000300UL)

  63. 

  64. #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

  65. #define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */

  66. #endif /* ADC_SUPPORT_2_5_MSPS */

  67. #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  68. 

  69. /* Definition of ADC group regular sequencer bits information to be inserted  */

  70. /* into ADC group regular sequencer ranks literals definition.                */

  71. #if defined (ADC_SUPPORT_2_5_MSPS)

  72. #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */

  73. #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */

  74. #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */

  75. #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ4" position in register */

  76. #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (16UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ5" position in register */

  77. #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (20UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ6" position in register */

  78. #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ7" position in register */

  79. #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (28UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ8" position in register */

  80. #else

  81. #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */

  82. #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */

  83. #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */

  84. #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */

  85. #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */

  86. #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */

  87. #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */

  88. #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */

  89. #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */

  90. #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */

  91. #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */

  92. #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */

  93. #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */

  94. #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */

  95. #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */

  96. #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */

  97. #endif /* ADC_SUPPORT_2_5_MSPS */

  98. 

  99. 

  100. 

  101. /* Internal mask for ADC group injected sequencer:                            */

  102. /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */

  103. /* - data register offset                                                     */

  104. /* - sequencer rank bits position into the selected register                  */

  105. 

  106. /* Internal register offset for ADC group injected data register */

  107. /* (offset placed into a spare area of literal definition) */

  108. #define ADC_JDR1_REGOFFSET                 (0x00000000UL)

  109. #define ADC_JDR2_REGOFFSET                 (0x00000100UL)

  110. #define ADC_JDR3_REGOFFSET                 (0x00000200UL)

  111. #define ADC_JDR4_REGOFFSET                 (0x00000300UL)

  112. 

  113. #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

  114. #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  115. #define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */

  116. 

  117. /* Definition of ADC group injected sequencer bits information to be inserted */

  118. /* into ADC group injected sequencer ranks literals definition.               */

  119. #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */

  120. #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */

  121. #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */

  122. #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */

  123. 

  124. 

  125. 

  126. /* Internal mask for ADC group regular trigger:                               */

  127. /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */

  128. /* - regular trigger source                                                   */

  129. /* - regular trigger edge                                                     */

  130. #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  131. 

  132. /* Mask containing trigger source masks for each of possible                  */

  133. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  134. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  135. #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \

  136.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \

  137.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \

  138.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )

  139. 

  140. /* Mask containing trigger edge masks for each of possible                    */

  141. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  142. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  143. #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \

  144.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \

  145.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \

  146.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )

  147. 

  148. /* Definition of ADC group regular trigger bits information.                  */

  149. #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */

  150. #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */

  151. 

  152. 

  153. 

  154. /* Internal mask for ADC group injected trigger:                              */

  155. /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */

  156. /* - injected trigger source                                                  */

  157. /* - injected trigger edge                                                    */

  158. #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  159. 

  160. /* Mask containing trigger source masks for each of possible                  */

  161. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  162. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  163. #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \

  164.                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \

  165.                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \

  166.                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )

  167. 

  168. /* Mask containing trigger edge masks for each of possible                    */

  169. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  170. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  171. #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \

  172.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \

  173.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \

  174.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

  175. 

  176. /* Definition of ADC group injected trigger bits information.                 */

  177. #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */

  178. #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */

  179. 

  180. 

  181. 

  182. 

  183. 

  184. 

  185. /* Internal mask for ADC channel:                                             */

  186. /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */

  187. /* - channel identifier defined by number                                     */

  188. /* - channel identifier defined by bitfield                                   */

  189. /* - channel differentiation between external channels (connected to          */

  190. /*   GPIO pins) and internal channels (connected to internal paths)           */

  191. /* - channel sampling time defined by SMPRx register offset                   */

  192. /*   and SMPx bits positions into SMPRx register                              */

  193. #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)

  194. #if defined (ADC_SUPPORT_2_5_MSPS)

  195. #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_CHSELR_CHSEL)

  196. #else

  197. #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)

  198. #endif

  199. #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */

  200. #if defined(ADC_SUPPORT_2_5_MSPS)

  201. #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ     (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 serie, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */

  202. #endif

  203. #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  204. /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */

  205. #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

  206. 

  207. /* Channel differentiation between external and internal channels */

  208. #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */

  209. #define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */

  210. #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

  211. 

  212. /* Internal register offset for ADC channel sampling time configuration */

  213. /* (offset placed into a spare area of literal definition) */

  214. #define ADC_SMPR1_REGOFFSET                (0x00000000UL)

  215. #define ADC_SMPR2_REGOFFSET                (0x02000000UL)

  216. #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

  217. #define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */

  218. 

  219. #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)

  220. #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */

  221. 

  222. /* Definition of channels ID number information to be inserted into           */

  223. /* channels literals definition.                                              */

  224. #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)

  225. #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)

  226. #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )

  227. #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  228. #define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )

  229. #define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)

  230. #define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )

  231. #define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  232. #define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )

  233. #define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)

  234. #define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )

  235. #define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  236. #define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )

  237. #define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)

  238. #define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )

  239. #define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  240. #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )

  241. #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)

  242. #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )

  243. 

  244. /* Definition of channels ID bitfield information to be inserted into         */

  245. /* channels literals definition.                                              */

  246. #if defined (ADC_SUPPORT_2_5_MSPS)

  247. #define ADC_CHANNEL_0_BITFIELD             (ADC_CHSELR_CHSEL0)

  248. #define ADC_CHANNEL_1_BITFIELD             (ADC_CHSELR_CHSEL1)

  249. #define ADC_CHANNEL_2_BITFIELD             (ADC_CHSELR_CHSEL2)

  250. #define ADC_CHANNEL_3_BITFIELD             (ADC_CHSELR_CHSEL3)

  251. #define ADC_CHANNEL_4_BITFIELD             (ADC_CHSELR_CHSEL4)

  252. #define ADC_CHANNEL_5_BITFIELD             (ADC_CHSELR_CHSEL5)

  253. #define ADC_CHANNEL_6_BITFIELD             (ADC_CHSELR_CHSEL6)

  254. #define ADC_CHANNEL_7_BITFIELD             (ADC_CHSELR_CHSEL7)

  255. #define ADC_CHANNEL_8_BITFIELD             (ADC_CHSELR_CHSEL8)

  256. #define ADC_CHANNEL_9_BITFIELD             (ADC_CHSELR_CHSEL9)

  257. #define ADC_CHANNEL_10_BITFIELD            (ADC_CHSELR_CHSEL10)

  258. #define ADC_CHANNEL_11_BITFIELD            (ADC_CHSELR_CHSEL11)

  259. #define ADC_CHANNEL_12_BITFIELD            (ADC_CHSELR_CHSEL12)

  260. #define ADC_CHANNEL_13_BITFIELD            (ADC_CHSELR_CHSEL13)

  261. #define ADC_CHANNEL_14_BITFIELD            (ADC_CHSELR_CHSEL14)

  262. #define ADC_CHANNEL_15_BITFIELD            (ADC_CHSELR_CHSEL15)

  263. #define ADC_CHANNEL_16_BITFIELD            (ADC_CHSELR_CHSEL16)

  264. #define ADC_CHANNEL_17_BITFIELD            (ADC_CHSELR_CHSEL17)

  265. #define ADC_CHANNEL_18_BITFIELD            (ADC_CHSELR_CHSEL18)

  266. #else

  267. #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)

  268. #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)

  269. #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)

  270. #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)

  271. #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)

  272. #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)

  273. #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)

  274. #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)

  275. #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)

  276. #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)

  277. #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)

  278. #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)

  279. #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)

  280. #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)

  281. #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)

  282. #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)

  283. #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)

  284. #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)

  285. #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)

  286. #endif

  287. 

  288. /* Definition of channels sampling time information to be inserted into       */

  289. /* channels literals definition.                                              */

  290. #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */

  291. #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */

  292. #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */

  293. #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */

  294. #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */

  295. #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */

  296. #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */

  297. #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */

  298. #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */

  299. #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */

  300. #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */

  301. #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */

  302. #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */

  303. #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */

  304. #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */

  305. #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */

  306. #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */

  307. #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */

  308. #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */

  309. 

  310. 

  311. #if defined(ADC_SUPPORT_2_5_MSPS)

  312. /* Internal mask for ADC channel sampling time:                               */

  313. /* To select into literals LL_ADC_SAMPLINGTIME_x                              */

  314. /* the relevant bits for:                                                     */

  315. /* (concatenation of multiple bits used in register SMPR)                     */

  316. /* - ADC channels sampling time: setting channel wise, to map each channel    */

  317. /*   on one of the common sampling time available.                            */

  318. /* - ADC channels common sampling time: set a sampling time into one of the   */

  319. /*   common sampling time available.                                          */

  320. #define ADC_SAMPLING_TIME_CH_MASK          (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)

  321. #define ADC_SAMPLING_TIME_SMP_MASK         (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)

  322. #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK   (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)

  323. 

  324. #endif

  325. /* Internal mask for ADC mode single or differential ended:                   */

  326. /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */

  327. /* the relevant bits for:                                                     */

  328. /* (concatenation of multiple bits used in different registers)               */

  329. /* - ADC calibration: calibration start, calibration factor get or set        */

  330. /* - ADC channels: set each ADC channel ending mode                           */

  331. #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)

  332. #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

  333. #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

  334. #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */

  335. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection of 1 bit to discriminate differential mode: mask of bit */

  336. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection of 1 bit to discriminate differential mode: position of bit */

  337. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */

  338. 

  339. /* Internal mask for ADC analog watchdog:                                     */

  340. /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */

  341. /* (concatenation of multiple bits used in different analog watchdogs,        */

  342. /* (feature of several watchdogs not available on all STM32 families)).       */

  343. /* - analog watchdog 1: monitored channel defined by number,                  */

  344. /*   selection of ADC group (ADC groups regular and-or injected).             */

  345. /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */

  346. /*   selection on groups.                                                     */

  347. 

  348. /* Internal register offset for ADC analog watchdog channel configuration */

  349. #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)

  350. #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)

  351. #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)

  352. 

  353. /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */

  354. /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */

  355. #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)

  356. #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)

  357. 

  358. #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

  359. #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)

  360. 

  361. #if defined (ADC_SUPPORT_2_5_MSPS)

  362. #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

  363. #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)

  364. #else

  365. #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

  366. #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)

  367. #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

  368. #endif

  369. 

  370. #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

  371. 

  372. /* Internal register offset for ADC analog watchdog threshold configuration */

  373. #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)

  374. #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)

  375. #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)

  376. #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

  377. #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */

  378. #define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit to discriminate threshold high: mask of bit */

  379. #define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit to discriminate threshold high: position of bit */

  380. #define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */

  381. 

  382. /* Internal mask for ADC offset:                                              */

  383. /* Internal register offset for ADC offset number configuration */

  384. #define ADC_OFR1_REGOFFSET                 (0x00000000UL)

  385. #define ADC_OFR2_REGOFFSET                 (0x00000001UL)

  386. #define ADC_OFR3_REGOFFSET                 (0x00000002UL)

  387. #define ADC_OFR4_REGOFFSET                 (0x00000003UL)

  388. #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

  389. 

  390. 

  391. /* ADC registers bits positions */

  392. #if defined (ADC_SUPPORT_2_5_MSPS)

  393. #define ADC_CFGR1_RES_BITOFFSET_POS        ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */

  394. #define ADC_CFGR1_AWDSGL_BITOFFSET_POS     (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */

  395. #define ADC_TR1_HT1_BITOFFSET_POS          (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */

  396. #define ADC_CHSELR_CHSEL0_BITOFFSET_POS    ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */

  397. #define ADC_CHSELR_CHSEL1_BITOFFSET_POS    ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */

  398. #define ADC_CHSELR_CHSEL2_BITOFFSET_POS    ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */

  399. #define ADC_CHSELR_CHSEL3_BITOFFSET_POS    ( 3UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */

  400. #define ADC_CHSELR_CHSEL4_BITOFFSET_POS    ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */

  401. #define ADC_CHSELR_CHSEL5_BITOFFSET_POS    ( 5UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */

  402. #define ADC_CHSELR_CHSEL6_BITOFFSET_POS    ( 6UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */

  403. #define ADC_CHSELR_CHSEL7_BITOFFSET_POS    ( 7UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */

  404. #define ADC_CHSELR_CHSEL8_BITOFFSET_POS    ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */

  405. #define ADC_CHSELR_CHSEL9_BITOFFSET_POS    ( 9UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */

  406. #define ADC_CHSELR_CHSEL10_BITOFFSET_POS   (10UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */

  407. #define ADC_CHSELR_CHSEL11_BITOFFSET_POS   (11UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */

  408. #define ADC_CHSELR_CHSEL12_BITOFFSET_POS   (12UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */

  409. #define ADC_CHSELR_CHSEL13_BITOFFSET_POS   (13UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */

  410. #define ADC_CHSELR_CHSEL14_BITOFFSET_POS   (14UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */

  411. #define ADC_CHSELR_CHSEL15_BITOFFSET_POS   (15UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */

  412. #define ADC_CHSELR_CHSEL16_BITOFFSET_POS   (16UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */

  413. #define ADC_CHSELR_CHSEL17_BITOFFSET_POS   (17UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */

  414. #define ADC_CHSELR_CHSEL18_BITOFFSET_POS   (18UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */

  415. #define ADC_SMPR_SMP1_BITOFFSET_POS        ( 0UL) /* Value equivalent to bitfield "ADC_SMPR_SMP1" position in register */

  416. #define ADC_SMPR_SMP2_BITOFFSET_POS        ( 4UL) /* Value equivalent to bitfield "ADC_SMPR_SMP2" position in register */

  417. #define ADC_SMPR_SMPSEL0_BITOFFSET_POS     ( 8UL) /* Value equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */

  418. #define ADC_CFGR_RES_BITOFFSET_POS         ADC_CFGR1_RES_BITOFFSET_POS

  419. #define ADC_CFGR_AWDSGL_BITOFFSET_POS      ADC_CFGR1_AWDSGL_BITOFFSET_POS

  420. #else

  421. #define ADC_CFGR_RES_BITOFFSET_POS         ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */

  422. #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */

  423. #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */

  424. #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */

  425. #define ADC_TR1_HT1_BITOFFSET_POS          (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */

  426. #endif

  427. 

  428. 

  429. /* ADC registers bits groups */

  430. #if defined (ADC_SUPPORT_2_5_MSPS)

  431. #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

  432. #else

  433. #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

  434. #endif

  435. 

  436. 

  437. /* ADC internal channels related definitions */

  438. /* Internal voltage reference VrefInt */

  439. #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.6 V (tolerance: +-10 mV). */

  440. #define VREFINT_CAL_VREF                   (3600UL)                     /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

  441. /* Temperature sensor */

  442. #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32WB, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

  443. #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32WB, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

  444. #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  445. #define TEMPSENSOR_CAL2_TEMP               (130L)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  446. #define TEMPSENSOR_CAL_VREFANALOG          (3000UL)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

  447. 

  448. 

  449. /**

  450.   * @}

  451.   */

  452. 

  453. 

  454. /* Private macros ------------------------------------------------------------*/

  455. /** @defgroup ADC_LL_Private_Macros ADC Private Macros

  456.   * @{

  457.   */

  458. 

  459. /**

  460.   * @brief  Driver macro reserved for internal use: set a pointer to

  461.   *         a register from a register basis from which an offset

  462.   *         is applied.

  463.   * @param  __REG__ Register basis from which the offset is applied.

  464.   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).

  465.   * @retval Pointer to register address

  466.   */

  467. #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \

  468.   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

  469. 

  470. /**

  471.   * @}

  472.   */

  473. 

  474. 

  475. /* Exported types ------------------------------------------------------------*/

  476. #if defined(USE_FULL_LL_DRIVER)

  477. /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure

  478.   * @{

  479.   */

  480. 

  481. /**

  482.   * @brief  Structure definition of some features of ADC common parameters

  483.   *         and multimode

  484.   *         (all ADC instances belonging to the same ADC common instance).

  485.   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()

  486.   *         is conditioned to ADC instances state (all ADC instances

  487.   *         sharing the same ADC common instance):

  488.   *         All ADC instances sharing the same ADC common instance must be

  489.   *         disabled.

  490.   */

  491. typedef struct

  492. {

  493.   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.

  494.                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE

  495.                                              @note On this STM32 serie, if ADC group injected is used, some

  496.                                                    clock ratio constraints between ADC clock and AHB clock

  497.                                                    must be respected. Refer to reference manual.

  498. 

  499.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */

  500. 

  501. } LL_ADC_CommonInitTypeDef;

  502. 

  503. /**

  504.   * @brief  Structure definition of some features of ADC instance.

  505.   * @note   These parameters have an impact on ADC scope: ADC instance.

  506.   *         Affects both group regular and group injected (availability

  507.   *         of ADC group injected depends on STM32 families).

  508.   *         Refer to corresponding unitary functions into

  509.   *         @ref ADC_LL_EF_Configuration_ADC_Instance .

  510.   * @note   The setting of these parameters by function @ref LL_ADC_Init()

  511.   *         is conditioned to ADC state:

  512.   *         ADC instance must be disabled.

  513.   *         This condition is applied to all ADC features, for efficiency

  514.   *         and compatibility over all STM32 families. However, the different

  515.   *         features can be set under different ADC state conditions

  516.   *         (setting possible with ADC enabled without conversion on going,

  517.   *         ADC enabled with conversion on going, ...)

  518.   *         Each feature can be updated afterwards with a unitary function

  519.   *         and potentially with ADC in a different state than disabled,

  520.   *         refer to description of each function for setting

  521.   *         conditioned to ADC state.

  522.   */

  523. typedef struct

  524. {

  525. #if defined (ADC_SUPPORT_2_5_MSPS)

  526.   uint32_t Clock;                       /*!< Set ADC instance clock source and prescaler.

  527.                                              This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE

  528.                                              @note On this STM32 serie, this parameter has some clock ratio constraints:

  529.                                                    ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle

  530.                                                    (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).

  531. 

  532.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().

  533.                                              For more details, refer to description of this function. */

  534. 

  535. #endif

  536.   uint32_t Resolution;                  /*!< Set ADC resolution.

  537.                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION

  538. 

  539.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */

  540. 

  541.   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.

  542.                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN

  543. 

  544.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */

  545. 

  546.   uint32_t LowPowerMode;                /*!< Set ADC low power mode.

  547.                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE

  548. 

  549.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */

  550. 

  551. } LL_ADC_InitTypeDef;

  552. 

  553. /**

  554.   * @brief  Structure definition of some features of ADC group regular.

  555.   * @note   These parameters have an impact on ADC scope: ADC group regular.

  556.   *         Refer to corresponding unitary functions into

  557.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  558.   *         (functions with prefix "REG").

  559.   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()

  560.   *         is conditioned to ADC state:

  561.   *         ADC instance must be disabled.

  562.   *         This condition is applied to all ADC features, for efficiency

  563.   *         and compatibility over all STM32 families. However, the different

  564.   *         features can be set under different ADC state conditions

  565.   *         (setting possible with ADC enabled without conversion on going,

  566.   *         ADC enabled with conversion on going, ...)

  567.   *         Each feature can be updated afterwards with a unitary function

  568.   *         and potentially with ADC in a different state than disabled,

  569.   *         refer to description of each function for setting

  570.   *         conditioned to ADC state.

  571.   */

  572. typedef struct

  573. {

  574.   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

  575.                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE

  576.                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge

  577.                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).

  578.                                                    In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().

  579. 

  580.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */

  581. 

  582.   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.

  583.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH

  584. 

  585.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */

  586. 

  587.   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  588.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE

  589.                                              @note This parameter has an effect only if group regular sequencer is enabled

  590.                                                    (scan length of 2 ranks or more).

  591. 

  592.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */

  593. 

  594.   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).

  595.                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE

  596.                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

  597. 

  598.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */

  599. 

  600.   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

  601.                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER

  602. 

  603.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */

  604. 

  605.   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:

  606.                                              data preserved or overwritten.

  607.                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR

  608. 

  609.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */

  610. 

  611. } LL_ADC_REG_InitTypeDef;

  612. 

  613. #if defined (ADC_SUPPORT_2_5_MSPS)

  614. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  615. #else

  616. /**

  617.   * @brief  Structure definition of some features of ADC group injected.

  618.   * @note   These parameters have an impact on ADC scope: ADC group injected.

  619.   *         Refer to corresponding unitary functions into

  620.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  621.   *         (functions with prefix "INJ").

  622.   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()

  623.   *         is conditioned to ADC state:

  624.   *         ADC instance must be disabled.

  625.   *         This condition is applied to all ADC features, for efficiency

  626.   *         and compatibility over all STM32 families. However, the different

  627.   *         features can be set under different ADC state conditions

  628.   *         (setting possible with ADC enabled without conversion on going,

  629.   *         ADC enabled with conversion on going, ...)

  630.   *         Each feature can be updated afterwards with a unitary function

  631.   *         and potentially with ADC in a different state than disabled,

  632.   *         refer to description of each function for setting

  633.   *         conditioned to ADC state.

  634.   */

  635. typedef struct

  636. {

  637.   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

  638.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE

  639.                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge

  640.                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).

  641.                                                    In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().

  642. 

  643.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */

  644. 

  645.   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.

  646.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH

  647. 

  648.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */

  649. 

  650.   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  651.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE

  652.                                              @note This parameter has an effect only if group injected sequencer is enabled

  653.                                                    (scan length of 2 ranks or more).

  654. 

  655.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */

  656. 

  657.   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.

  658.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO

  659.                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

  660. 

  661.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */

  662. 

  663. } LL_ADC_INJ_InitTypeDef;

  664. #endif /* ADC_SUPPORT_2_5_MSPS */

  665. 

  666. /**

  667.   * @}

  668.   */

  669. #endif /* USE_FULL_LL_DRIVER */

  670. 

  671. /* Exported constants --------------------------------------------------------*/

  672. /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants

  673.   * @{

  674.   */

  675. 

  676. /** @defgroup ADC_LL_EC_FLAG ADC flags

  677.   * @brief    Flags defines which can be used with LL_ADC_ReadReg function

  678.   * @{

  679.   */

  680. #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */

  681. #if defined(ADC_SUPPORT_2_5_MSPS)

  682. #define LL_ADC_FLAG_CCRDY                  ADC_ISR_CCRDY      /*!< ADC flag ADC channel configuration ready */

  683. #else

  684. #endif

  685. #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */

  686. #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */

  687. #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */

  688. #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */

  689. #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */

  690. #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */

  691. #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */

  692. #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */

  693. #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */

  694. #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */

  695. #if defined(ADC_SUPPORT_2_5_MSPS)

  696. #define LL_ADC_FLAG_EOCAL                  ADC_ISR_EOCAL      /*!< ADC flag end of calibration */

  697. #endif

  698. /**

  699.   * @}

  700.   */

  701. 

  702. /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)

  703.   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions

  704.   * @{

  705.   */

  706. #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */

  707. #if defined(ADC_SUPPORT_2_5_MSPS)

  708. #define LL_ADC_IT_CCRDY                    ADC_IER_CCRDYIE    /*!< ADC interruption channel configuration ready */

  709. #else

  710. #endif

  711. #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */

  712. #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */

  713. #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */

  714. #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */

  715. #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */

  716. #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */

  717. #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */

  718. #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */

  719. #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */

  720. #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */

  721. #if defined(ADC_SUPPORT_2_5_MSPS)

  722. #define LL_ADC_IT_EOCAL                    ADC_IER_EOCALIE    /*!< ADC interruption ADC end of calibration */

  723. #endif

  724. /**

  725.   * @}

  726.   */

  727. 

  728. /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose

  729.   * @{

  730.   */

  731. /* List of ADC registers intended to be used (most commonly) with             */

  732. /* DMA transfer.                                                              */

  733. /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */

  734. #define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

  735. /**

  736.   * @}

  737.   */

  738. 

  739. /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source

  740.   * @{

  741.   */

  742. #if !defined (ADC_SUPPORT_2_5_MSPS)

  743. #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */

  744. #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */

  745. #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */

  746. #endif

  747. #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */

  748. #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */

  749. #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */

  750. #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */

  751. #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */

  752. #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */

  753. #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */

  754. #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */

  755. #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */

  756. #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */

  757. #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */

  758. #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */

  759. /**

  760.   * @}

  761.   */

  762. 

  763. /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels

  764.   * @{

  765.   */

  766. /* Note: Other measurement paths to internal channels may be available        */

  767. /*       (connections to other peripherals).                                  */

  768. /*       If they are not listed below, they do not require any specific       */

  769. /*       path enable. In this case, Access to measurement path is done        */

  770. /*       only by selecting the corresponding ADC internal channel.            */

  771. #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement paths all disabled */

  772. #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */

  773. #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */

  774. #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */

  775. /**

  776.   * @}

  777.   */

  778. 

  779. #if defined (ADC_SUPPORT_2_5_MSPS)

  780. /** @defgroup ADC_LL_EC_CLOCK_SOURCE  ADC instance - Clock source

  781.   * @{

  782.   */

  783. #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CFGR2_CKMODE_1)                                  /*!< ADC synchronous clock derived from AHB clock divided by 4 */

  784. #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CFGR2_CKMODE_0)                                  /*!< ADC synchronous clock derived from AHB clock divided by 2 */

  785. #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0)             /*!< ADC synchronous clock derived from AHB clock not divided  */

  786. #define LL_ADC_CLOCK_ASYNC                 (0x00000000UL)                                        /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */

  787. /**

  788.   * @}

  789.   */

  790. #endif

  791. 

  792. /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution

  793.   * @{

  794.   */

  795. #define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */

  796. #define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */

  797. #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */

  798. #define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */

  799. /**

  800.   * @}

  801.   */

  802. 

  803. /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment

  804.   * @{

  805.   */

  806. #define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)         /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/

  807. #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/

  808. /**

  809.   * @}

  810.   */

  811. 

  812. /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode

  813.   * @{

  814.   */

  815. #define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low power mode activated */

  816. #if defined (ADC_SUPPORT_2_5_MSPS)

  817. #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR1_WAIT)                    /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */

  818. #define LL_ADC_LP_AUTOPOWEROFF             (ADC_CFGR1_AUTOFF)                  /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */

  819. #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF    (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */

  820. #else

  821. #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */

  822. #endif

  823. /**

  824.   * @}

  825.   */

  826. 

  827. /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ  ADC group regular - Trigger frequency mode

  828.   * @{

  829.   */

  830. #define LL_ADC_TRIGGER_FREQ_HIGH           (0x00000000UL)            /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */

  831. #define LL_ADC_TRIGGER_FREQ_LOW            (ADC_CFGR2_LFTRIG)        /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */

  832. /**

  833.   * @}

  834.   */

  835. 

  836. #if defined(ADC_SUPPORT_2_5_MSPS)

  837. /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON  ADC instance - Sampling time common to a group of channels

  838. * @{

  839. */

  840. #define LL_ADC_SAMPLINGTIME_COMMON_1       (ADC_SMPR_SMP1_BITOFFSET_POS)                             /*!< Set sampling time common to a group of channels: sampling time nb 1 */

  841. #define LL_ADC_SAMPLINGTIME_COMMON_2       (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */

  842. /**

  843.   * @}

  844.   */

  845. 

  846. #endif

  847. /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number

  848.   * @{

  849.   */

  850. #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  851. #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  852. #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  853. #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  854. /**

  855.   * @}

  856.   */

  857. 

  858. /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state

  859.   * @{

  860.   */

  861. #define LL_ADC_OFFSET_DISABLE              (0x00000000UL)         /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */

  862. #define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */

  863. /**

  864.   * @}

  865.   */

  866. 

  867. /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups

  868.   * @{

  869.   */

  870. #define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */

  871. #if !defined (ADC_SUPPORT_2_5_MSPS)

  872. #define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/

  873. #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected */

  874. #endif

  875. /**

  876.   * @}

  877.   */

  878. 

  879. /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number

  880.   * @{

  881.   */

  882. #if defined (ADC_SUPPORT_2_5_MSPS)

  883. #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */

  884. #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */

  885. #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */

  886. #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */

  887. #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */

  888. #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */

  889. #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */

  890. #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */

  891. #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */

  892. #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */

  893. #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */

  894. #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */

  895. #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */

  896. #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */

  897. #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */

  898. #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */

  899. #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */

  900. #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */

  901. #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */

  902. #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */

  903. #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Temperature sensor. */

  904. #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */

  905. #else

  906. #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */

  907. #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */

  908. #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */

  909. #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */

  910. #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */

  911. #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */

  912. #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */

  913. #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */

  914. #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */

  915. #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */

  916. #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */

  917. #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */

  918. #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */

  919. #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */

  920. #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */

  921. #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */

  922. #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */

  923. #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */

  924. #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */

  925. #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_0  | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */

  926. #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Temperature sensor. */

  927. #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. */

  928. 

  929. #endif

  930. /**

  931.   * @}

  932.   */

  933. 

  934. /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source

  935.   * @{

  936.   */

  937. #if defined(ADC_SUPPORT_2_5_MSPS)

  938. #define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                                                                                  /*!< ADC group regular conversion trigger internal: SW start. */

  939. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (                                                               ADC_REG_TRIG_EXT_EDGE_DEFAULT)                  /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */

  940. #define LL_ADC_REG_TRIG_EXT_TIM1_CH4       (                                          ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                  /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  941. #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (                     ADC_CFGR1_EXTSEL_1                      | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                  /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */

  942. #define LL_ADC_REG_TRIG_EXT_TIM2_CH4       (                     ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                  /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  943. #define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CFGR1_EXTSEL_2                      | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                  /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  944. #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                  /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */

  945. #else

  946. #define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                                                                                  /*!< ADC group regular conversion trigger internal: SW start. */

  947. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */

  948. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */

  949. #define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  950. #define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  951. #define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  952. #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */

  953. #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  954. #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */

  955. #endif

  956. /**

  957.   * @}

  958.   */

  959. 

  960. /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge

  961.   * @{

  962.   */

  963. #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */

  964. #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */

  965. #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */

  966. /**

  967.   * @}

  968.   */

  969. 

  970. /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode

  971.   * @{

  972.   */

  973. #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are performed in single mode: one conversion per trigger */

  974. #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */

  975. /**

  976.   * @}

  977.   */

  978. 

  979. /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data

  980.   * @{

  981.   */

  982. #define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)                        /*!< ADC conversions are not transferred by DMA */

  983. #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)    /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */

  984. #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)    /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */

  985. /**

  986.   * @}

  987.   */

  988. 

  989. 

  990. 

  991. /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data

  992.   * @{

  993.   */

  994. #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior in case of overrun: data preserved */

  995. #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */

  996. /**

  997.   * @}

  998.   */

  999. 

  1000. #if defined(ADC_SUPPORT_2_5_MSPS)

  1001. /** @defgroup ADC_LL_EC_REG_SEQ_MODE  ADC group regular - Sequencer configuration flexibility

  1002. * @{

  1003. */

  1004. #define LL_ADC_REG_SEQ_FIXED               (0x00000000UL)         /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */

  1005. #define LL_ADC_REG_SEQ_CONFIGURABLE        (ADC_CFGR1_CHSELRMOD)  /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */

  1006. /**

  1007.   * @}

  1008.   */

  1009. 

  1010. #endif

  1011. /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length

  1012.   * @{

  1013.   */

  1014. #if  defined(ADC_SUPPORT_2_5_MSPS)

  1015. #define LL_ADC_REG_SEQ_SCAN_DISABLE        (ADC_CHSELR_SQ2)       /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  1016. #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (ADC_CHSELR_SQ3)       /*!< ADC group regular sequencer enable with 2 ranks in the sequence */

  1017. #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (ADC_CHSELR_SQ4)       /*!< ADC group regular sequencer enable with 3 ranks in the sequence */

  1018. #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (ADC_CHSELR_SQ5)       /*!< ADC group regular sequencer enable with 4 ranks in the sequence */

  1019. #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (ADC_CHSELR_SQ6)       /*!< ADC group regular sequencer enable with 5 ranks in the sequence */

  1020. #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (ADC_CHSELR_SQ7)       /*!< ADC group regular sequencer enable with 6 ranks in the sequence */

  1021. #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (ADC_CHSELR_SQ8)       /*!< ADC group regular sequencer enable with 7 ranks in the sequence */

  1022. #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (0x00000000UL)         /*!< ADC group regular sequencer enable with 8 ranks in the sequence */

  1023. #else

  1024. #define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                              /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  1025. #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */

  1026. #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */

  1027. #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */

  1028. #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */

  1029. #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */

  1030. #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */

  1031. #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */

  1032. #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */

  1033. #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */

  1034. #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */

  1035. #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */

  1036. #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */

  1037. #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */

  1038. #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */

  1039. #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */

  1040. #endif

  1041. /**

  1042.   * @}

  1043.   */

  1044. 

  1045. #if defined(ADC_SUPPORT_2_5_MSPS)

  1046. /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION  ADC group regular - Sequencer scan direction

  1047.   * @{

  1048.   */

  1049. #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD    (0x00000000UL)         /*!< On this STM32 serie, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */

  1050. #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD   (ADC_CFGR1_SCANDIR)    /*!< On this STM32 serie, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */

  1051. /**

  1052.   * @}

  1053.   */

  1054. 

  1055. #endif

  1056. /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode

  1057.   * @{

  1058.   */

  1059. #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                                               /*!< ADC group regular sequencer discontinuous mode disable */

  1060. #if defined (ADC_SUPPORT_2_5_MSPS)

  1061. #define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR1_DISCEN)                                                               /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */

  1062. #else

  1063. #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */

  1064. #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */

  1065. #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */

  1066. #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */

  1067. #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */

  1068. #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */

  1069. #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */

  1070. #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */

  1071. #endif /* ADC_SUPPORT_2_5_MSPS */

  1072. /**

  1073.   * @}

  1074.   */

  1075. 

  1076. /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks

  1077.   * @{

  1078.   */

  1079. #if defined (ADC_SUPPORT_2_5_MSPS)

  1080. #define LL_ADC_REG_RANK_1                  (ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */

  1081. #define LL_ADC_REG_RANK_2                  (ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */

  1082. #define LL_ADC_REG_RANK_3                  (ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */

  1083. #define LL_ADC_REG_RANK_4                  (ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */

  1084. #define LL_ADC_REG_RANK_5                  (ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */

  1085. #define LL_ADC_REG_RANK_6                  (ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */

  1086. #define LL_ADC_REG_RANK_7                  (ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */

  1087. #define LL_ADC_REG_RANK_8                  (ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */

  1088. #else

  1089. #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */

  1090. #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */

  1091. #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */

  1092. #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */

  1093. #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */

  1094. #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */

  1095. #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */

  1096. #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */

  1097. #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */

  1098. #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */

  1099. #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */

  1100. #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */

  1101. #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */

  1102. #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */

  1103. #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */

  1104. #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */

  1105. #endif /* ADC_SUPPORT_2_5_MSPS */

  1106. /**

  1107.   * @}

  1108.   */

  1109. 

  1110. #if defined (ADC_SUPPORT_2_5_MSPS)

  1111. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  1112. #else

  1113. /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source

  1114.   * @{

  1115.   */

  1116. #define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                                                                                      /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */

  1117. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                     /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */

  1118. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */

  1119. #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1120. #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */

  1121. #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1122. #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */

  1123. /**

  1124.   * @}

  1125.   */

  1126. 

  1127. /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge

  1128.   * @{

  1129.   */

  1130. #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */

  1131. #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */

  1132. #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */

  1133. /**

  1134.   * @}

  1135.   */

  1136. 

  1137. /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode

  1138.   * @{

  1139.   */

  1140. #define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */

  1141. #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */

  1142. /**

  1143.   * @}

  1144.   */

  1145. 

  1146. /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode

  1147.   * @{

  1148.   */

  1149. #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */

  1150. #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */

  1151. #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

  1152. /**

  1153.   * @}

  1154.   */

  1155. 

  1156. /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length

  1157.   * @{

  1158.   */

  1159. #define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  1160. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */

  1161. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */

  1162. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */

  1163. /**

  1164.   * @}

  1165.   */

  1166. 

  1167. /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode

  1168.   * @{

  1169.   */

  1170. #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer discontinuous mode disable */

  1171. #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */

  1172. /**

  1173.   * @}

  1174.   */

  1175. 

  1176. /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks

  1177.   * @{

  1178.   */

  1179. #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */

  1180. #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */

  1181. #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */

  1182. #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */

  1183. /**

  1184.   * @}

  1185.   */

  1186. #endif /* ADC_SUPPORT_2_5_MSPS */

  1187. 

  1188. /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time

  1189.   * @{

  1190.   */

  1191. #if defined (ADC_SUPPORT_2_5_MSPS)

  1192. #define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000UL)                                        /*!< Sampling time 1.5 ADC clock cycle */

  1193. #define LL_ADC_SAMPLINGTIME_3CYCLES_5      (ADC_SMPR_SMP1_0)                                     /*!< Sampling time 3.5 ADC clock cycles */

  1194. #define LL_ADC_SAMPLINGTIME_7CYCLES_5      (ADC_SMPR_SMP1_1)                                     /*!< Sampling time 7.5 ADC clock cycles */

  1195. #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0)                   /*!< Sampling time 12.5 ADC clock cycles */

  1196. #define LL_ADC_SAMPLINGTIME_19CYCLES_5     (ADC_SMPR_SMP1_2)                                     /*!< Sampling time 19.5 ADC clock cycles */

  1197. #define LL_ADC_SAMPLINGTIME_39CYCLES_5     (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0)                   /*!< Sampling time 39.5 ADC clock cycles */

  1198. #define LL_ADC_SAMPLINGTIME_79CYCLES_5     (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1)                   /*!< Sampling time 79.5 ADC clock cycles */

  1199. #define LL_ADC_SAMPLINGTIME_160CYCLES_5    (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */

  1200. #else

  1201. #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)                                              /*!< Sampling time 2.5 ADC clock cycles */

  1202. #define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */

  1203. #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 12.5 ADC clock cycles */

  1204. #define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */

  1205. #define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 47.5 ADC clock cycles */

  1206. #define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */

  1207. #define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */

  1208. #define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */

  1209. #endif

  1210. /**

  1211.   * @}

  1212.   */

  1213. 

  1214. /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending

  1215.   * @{

  1216.   */

  1217. #if defined (ADC_SUPPORT_2_5_MSPS)

  1218. #define LL_ADC_SINGLE_ENDED                (0x00000000UL)                                    /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */

  1219. #else

  1220. #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */

  1221. #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */

  1222. #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */

  1223. #endif

  1224. /**

  1225.   * @}

  1226.   */

  1227. 

  1228. /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number

  1229.   * @{

  1230.   */

  1231. #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */

  1232. #if defined (ADC_SUPPORT_2_5_MSPS)

  1233. /* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */

  1234. #else

  1235. #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */

  1236. #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */

  1237. #endif

  1238. /**

  1239.   * @}

  1240.   */

  1241. 

  1242. /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels

  1243.   * @{

  1244.   */

  1245. #if defined (ADC_SUPPORT_2_5_MSPS)

  1246. #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                             /*!< ADC analog watchdog monitoring disabled */

  1247. #define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                    ADC_CFGR1_AWD1EN                    ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */

  1248. #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */

  1249. #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */

  1250. #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */

  1251. #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */

  1252. #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */

  1253. #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */

  1254. #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */

  1255. #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */

  1256. #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */

  1257. #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */

  1258. #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */

  1259. #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */

  1260. #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */

  1261. #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */

  1262. #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */

  1263. #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */

  1264. #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */

  1265. #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */

  1266. #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */

  1267. #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */

  1268. #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */

  1269. #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */

  1270. #else

  1271. #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                                      /*!< ADC analog watchdog monitoring disabled */

  1272. #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */

  1273. #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */

  1274. #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */

  1275. #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */

  1276. #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */

  1277. #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */

  1278. #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */

  1279. #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */

  1280. #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */

  1281. #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */

  1282. #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */

  1283. #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */

  1284. #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */

  1285. #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */

  1286. #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */

  1287. #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */

  1288. #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */

  1289. #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */

  1290. #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */

  1291. #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */

  1292. #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */

  1293. #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */

  1294. #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */

  1295. #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */

  1296. #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */

  1297. #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */

  1298. #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */

  1299. #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */

  1300. #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */

  1301. #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */

  1302. #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */

  1303. #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */

  1304. #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */

  1305. #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */

  1306. #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */

  1307. #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */

  1308. #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */

  1309. #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */

  1310. #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */

  1311. #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */

  1312. #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */

  1313. #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */

  1314. #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */

  1315. #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */

  1316. #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */

  1317. #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */

  1318. #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */

  1319. #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */

  1320. #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */

  1321. #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */

  1322. #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */

  1323. #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */

  1324. #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */

  1325. #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */

  1326. #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */

  1327. #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */

  1328. #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */

  1329. #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */

  1330. #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */

  1331. #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */

  1332. #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */

  1333. #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */

  1334. #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */

  1335. #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */

  1336. #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */

  1337. #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */

  1338. #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */

  1339. #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */

  1340. #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */

  1341. #endif /* ADC_SUPPORT_2_5_MSPS */

  1342. /**

  1343.   * @}

  1344.   */

  1345. 

  1346. /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds

  1347.   * @{

  1348.   */

  1349. #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */

  1350. #define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */

  1351. #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */

  1352. /**

  1353.   * @}

  1354.   */

  1355. 

  1356. /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope

  1357.   * @{

  1358.   */

  1359. #if defined (ADC_SUPPORT_2_5_MSPS)

  1360. #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */

  1361. #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_OVSE)  /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */

  1362. #else

  1363. #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */

  1364. #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */

  1365. #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */

  1366. #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */

  1367. #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */

  1368. #endif

  1369. /**

  1370.   * @}

  1371.   */

  1372. 

  1373. /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode

  1374.   * @{

  1375.   */

  1376. #define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */

  1377. #if defined (ADC_SUPPORT_2_5_MSPS)

  1378. #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TOVS)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */

  1379. #else

  1380. #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */

  1381. #endif

  1382. /**

  1383.   * @}

  1384.   */

  1385. 

  1386. /** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio

  1387.   * @{

  1388.   */

  1389. #define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                                           /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */

  1390. #define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */

  1391. #define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */

  1392. #define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */

  1393. #define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */

  1394. #define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */

  1395. #define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */

  1396. #define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */

  1397. /**

  1398.   * @}

  1399.   */

  1400. 

  1401. /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift

  1402.   * @{

  1403.   */

  1404. #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                                              /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */

  1405. #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */

  1406. #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */

  1407. #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */

  1408. #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */

  1409. #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */

  1410. #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */

  1411. #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */

  1412. #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */

  1413. /**

  1414.   * @}

  1415.   */

  1416. 

  1417. 

  1418. /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays

  1419.   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,

  1420.   *         not timeout values.

  1421.   *         For details on delays values, refer to descriptions in source code

  1422.   *         above each literal definition.

  1423.   * @{

  1424.   */

  1425. 

  1426. /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */

  1427. /*       not timeout values.                                                  */

  1428. /*       Timeout values for ADC operations are dependent to device clock      */

  1429. /*       configuration (system clock versus ADC clock),                       */

  1430. /*       and therefore must be defined in user application.                   */

  1431. /*       Indications for estimation of ADC timeout delays, for this           */

  1432. /*       STM32 serie:                                                         */

  1433. /*       - ADC calibration time: maximum delay is 112/fADC.                   */

  1434. /*         (refer to device datasheet, parameter "tCAL")                      */

  1435. /*       - ADC enable time: maximum delay is 1 conversion cycle.              */

  1436. /*         (refer to device datasheet, parameter "tSTAB")                     */

  1437. /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */

  1438. /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */

  1439. /*         cycles                                                             */

  1440. /*       - ADC conversion time: duration depending on ADC clock and ADC       */

  1441. /*         configuration.                                                     */

  1442. /*         (refer to device reference manual, section "Timing")               */

  1443. 

  1444. /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */

  1445. /* Delay set to maximum value (refer to device datasheet,                     */

  1446. /* parameter "tADCVREG_STUP").                                                */

  1447. /* Unit: us                                                                   */

  1448. #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */

  1449. 

  1450. /* Delay for internal voltage reference stabilization time.                   */

  1451. /* Delay set to maximum value (refer to device datasheet,                     */

  1452. /* parameter "tstart_vrefint").                                               */

  1453. /* Unit: us                                                                   */

  1454. #define LL_ADC_DELAY_VREFINT_STAB_US       ( 12UL)  /*!< Delay for internal voltage reference stabilization time */

  1455. 

  1456. /* Delay for temperature sensor stabilization time.                           */

  1457. /* Literal set to maximum value (refer to device datasheet,                   */

  1458. /* parameter "tSTART").                                                       */

  1459. /* Unit: us                                                                   */

  1460. #define LL_ADC_DELAY_TEMPSENSOR_STAB_US        (120UL)  /*!< Delay for temperature sensor stabilization time */

  1461. #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)  /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */

  1462. 

  1463. /* Delay required between ADC end of calibration and ADC enable.              */

  1464. /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */

  1465. /*       are required between ADC end of calibration and ADC enable.          */

  1466. /*       Wait time can be computed in user application by waiting for the     */

  1467. /*       equivalent number of CPU cycles, by taking into account              */

  1468. /*       ratio of CPU clock versus ADC clock prescalers.                      */

  1469. /* Unit: ADC clock cycles.                                                    */

  1470. #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (  4UL)  /*!< Delay required between ADC end of calibration and ADC enable */

  1471. 

  1472. /**

  1473.   * @}

  1474.   */

  1475. 

  1476. /**

  1477.   * @}

  1478.   */

  1479. 

  1480. 

  1481. /* Exported macro ------------------------------------------------------------*/

  1482. /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros

  1483.   * @{

  1484.   */

  1485. 

  1486. /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros

  1487.   * @{

  1488.   */

  1489. 

  1490. /**

  1491.   * @brief  Write a value in ADC register

  1492.   * @param  __INSTANCE__ ADC Instance

  1493.   * @param  __REG__ Register to be written

  1494.   * @param  __VALUE__ Value to be written in the register

  1495.   * @retval None

  1496.   */

  1497. #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

  1498. 

  1499. /**

  1500.   * @brief  Read a value in ADC register

  1501.   * @param  __INSTANCE__ ADC Instance

  1502.   * @param  __REG__ Register to be read

  1503.   * @retval Register value

  1504.   */

  1505. #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

  1506. /**

  1507.   * @}

  1508.   */

  1509. 

  1510. /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro

  1511.   * @{

  1512.   */

  1513. 

  1514. /**

  1515.   * @brief  Helper macro to get ADC channel number in decimal format

  1516.   *         from literals LL_ADC_CHANNEL_x.

  1517.   * @note   Example:

  1518.   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)

  1519.   *           will return decimal number "4".

  1520.   * @note   The input can be a value from functions where a channel

  1521.   *         number is returned, either defined with number

  1522.   *         or with bitfield (only one bit must be set).

  1523.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1524.   *         @arg @ref LL_ADC_CHANNEL_0

  1525.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  1526.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  1527.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  1528.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  1529.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  1530.   *         @arg @ref LL_ADC_CHANNEL_6

  1531.   *         @arg @ref LL_ADC_CHANNEL_7

  1532.   *         @arg @ref LL_ADC_CHANNEL_8

  1533.   *         @arg @ref LL_ADC_CHANNEL_9

  1534.   *         @arg @ref LL_ADC_CHANNEL_10

  1535.   *         @arg @ref LL_ADC_CHANNEL_11

  1536.   *         @arg @ref LL_ADC_CHANNEL_12

  1537.   *         @arg @ref LL_ADC_CHANNEL_13

  1538.   *         @arg @ref LL_ADC_CHANNEL_14

  1539.   *         @arg @ref LL_ADC_CHANNEL_15

  1540.   *         @arg @ref LL_ADC_CHANNEL_16

  1541.   *         @arg @ref LL_ADC_CHANNEL_17

  1542.   *         @arg @ref LL_ADC_CHANNEL_18

  1543.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  1544.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  1545.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  1546.   *

  1547.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  1548.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  1549.   * @retval Value between Min_Data=0 and Max_Data=18

  1550.   */

  1551. #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \

  1552.   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL)                                 \

  1553.    ? (                                                                                     \

  1554.        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \

  1555.      )                                                                                     \

  1556.    :                                                                                       \

  1557.    (                                                                                       \

  1558.        (uint32_t)POSITION_VAL((__CHANNEL__))                                               \

  1559.    )                                                                                       \

  1560.   )

  1561. 

  1562. /**

  1563.   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x

  1564.   *         from number in decimal format.

  1565.   * @note   Example:

  1566.   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)

  1567.   *           will return a data equivalent to "LL_ADC_CHANNEL_4".

  1568.   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18

  1569.   * @retval Returned value can be one of the following values:

  1570.   *         @arg @ref LL_ADC_CHANNEL_0

  1571.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  1572.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  1573.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  1574.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  1575.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  1576.   *         @arg @ref LL_ADC_CHANNEL_6

  1577.   *         @arg @ref LL_ADC_CHANNEL_7

  1578.   *         @arg @ref LL_ADC_CHANNEL_8

  1579.   *         @arg @ref LL_ADC_CHANNEL_9

  1580.   *         @arg @ref LL_ADC_CHANNEL_10

  1581.   *         @arg @ref LL_ADC_CHANNEL_11

  1582.   *         @arg @ref LL_ADC_CHANNEL_12

  1583.   *         @arg @ref LL_ADC_CHANNEL_13

  1584.   *         @arg @ref LL_ADC_CHANNEL_14

  1585.   *         @arg @ref LL_ADC_CHANNEL_15

  1586.   *         @arg @ref LL_ADC_CHANNEL_16

  1587.   *         @arg @ref LL_ADC_CHANNEL_17

  1588.   *         @arg @ref LL_ADC_CHANNEL_18

  1589.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (4)

  1590.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)

  1591.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)

  1592.   *

  1593.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  1594.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n

  1595.   *         (4) For ADC channel read back from ADC register,

  1596.   *             comparison with internal channel parameter to be done

  1597.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1598.   */

  1599. #if defined (ADC_SUPPORT_2_5_MSPS)

  1600. #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \

  1601.   (                                                                            \

  1602.    ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) |                 \

  1603.    (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__))                                     \

  1604.   )

  1605. #else

  1606. #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \

  1607.   (((__DECIMAL_NB__) <= 9UL)                                                                            \

  1608.    ? (                                                                                                  \

  1609.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \

  1610.        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \

  1611.        (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \

  1612.      )                                                                                                  \

  1613.    :                                                                                                    \

  1614.    (                                                                                                    \

  1615.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \

  1616.        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \

  1617.        (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \

  1618.    )                                                                                                    \

  1619.   )

  1620. #endif /* ADC_SUPPORT_2_5_MSPS */

  1621. 

  1622. /**

  1623.   * @brief  Helper macro to determine whether the selected channel

  1624.   *         corresponds to literal definitions of driver.

  1625.   * @note   The different literal definitions of ADC channels are:

  1626.   *         - ADC internal channel:

  1627.   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...

  1628.   *         - ADC external channel (channel connected to a GPIO pin):

  1629.   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...

  1630.   * @note   The channel parameter must be a value defined from literal

  1631.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1632.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1633.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),

  1634.   *         must not be a value from functions where a channel number is

  1635.   *         returned from ADC registers,

  1636.   *         because internal and external channels share the same channel

  1637.   *         number in ADC registers. The differentiation is made only with

  1638.   *         parameters definitions of driver.

  1639.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1640.   *         @arg @ref LL_ADC_CHANNEL_0

  1641.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  1642.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  1643.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  1644.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  1645.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  1646.   *         @arg @ref LL_ADC_CHANNEL_6

  1647.   *         @arg @ref LL_ADC_CHANNEL_7

  1648.   *         @arg @ref LL_ADC_CHANNEL_8

  1649.   *         @arg @ref LL_ADC_CHANNEL_9

  1650.   *         @arg @ref LL_ADC_CHANNEL_10

  1651.   *         @arg @ref LL_ADC_CHANNEL_11

  1652.   *         @arg @ref LL_ADC_CHANNEL_12

  1653.   *         @arg @ref LL_ADC_CHANNEL_13

  1654.   *         @arg @ref LL_ADC_CHANNEL_14

  1655.   *         @arg @ref LL_ADC_CHANNEL_15

  1656.   *         @arg @ref LL_ADC_CHANNEL_16

  1657.   *         @arg @ref LL_ADC_CHANNEL_17

  1658.   *         @arg @ref LL_ADC_CHANNEL_18

  1659.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  1660.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  1661.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  1662.   *

  1663.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  1664.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  1665.   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).

  1666.   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

  1667.   */

  1668. #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \

  1669.   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)

  1670. 

  1671. /**

  1672.   * @brief  Helper macro to convert a channel defined from parameter

  1673.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1674.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1675.   *         to its equivalent parameter definition of a ADC external channel

  1676.   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

  1677.   * @note   The channel parameter can be, additionally to a value

  1678.   *         defined from parameter definition of a ADC internal channel

  1679.   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1680.   *         a value defined from parameter definition of

  1681.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1682.   *         or a value from functions where a channel number is returned

  1683.   *         from ADC registers.

  1684.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1685.   *         @arg @ref LL_ADC_CHANNEL_0

  1686.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  1687.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  1688.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  1689.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  1690.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  1691.   *         @arg @ref LL_ADC_CHANNEL_6

  1692.   *         @arg @ref LL_ADC_CHANNEL_7

  1693.   *         @arg @ref LL_ADC_CHANNEL_8

  1694.   *         @arg @ref LL_ADC_CHANNEL_9

  1695.   *         @arg @ref LL_ADC_CHANNEL_10

  1696.   *         @arg @ref LL_ADC_CHANNEL_11

  1697.   *         @arg @ref LL_ADC_CHANNEL_12

  1698.   *         @arg @ref LL_ADC_CHANNEL_13

  1699.   *         @arg @ref LL_ADC_CHANNEL_14

  1700.   *         @arg @ref LL_ADC_CHANNEL_15

  1701.   *         @arg @ref LL_ADC_CHANNEL_16

  1702.   *         @arg @ref LL_ADC_CHANNEL_17

  1703.   *         @arg @ref LL_ADC_CHANNEL_18

  1704.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  1705.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  1706.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  1707.   *

  1708.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  1709.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  1710.   * @retval Returned value can be one of the following values:

  1711.   *         @arg @ref LL_ADC_CHANNEL_0

  1712.   *         @arg @ref LL_ADC_CHANNEL_1

  1713.   *         @arg @ref LL_ADC_CHANNEL_2

  1714.   *         @arg @ref LL_ADC_CHANNEL_3

  1715.   *         @arg @ref LL_ADC_CHANNEL_4

  1716.   *         @arg @ref LL_ADC_CHANNEL_5

  1717.   *         @arg @ref LL_ADC_CHANNEL_6

  1718.   *         @arg @ref LL_ADC_CHANNEL_7

  1719.   *         @arg @ref LL_ADC_CHANNEL_8

  1720.   *         @arg @ref LL_ADC_CHANNEL_9

  1721.   *         @arg @ref LL_ADC_CHANNEL_10

  1722.   *         @arg @ref LL_ADC_CHANNEL_11

  1723.   *         @arg @ref LL_ADC_CHANNEL_12

  1724.   *         @arg @ref LL_ADC_CHANNEL_13

  1725.   *         @arg @ref LL_ADC_CHANNEL_14

  1726.   *         @arg @ref LL_ADC_CHANNEL_15

  1727.   *         @arg @ref LL_ADC_CHANNEL_16

  1728.   *         @arg @ref LL_ADC_CHANNEL_17

  1729.   *         @arg @ref LL_ADC_CHANNEL_18

  1730.   */

  1731. #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \

  1732.   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  1733. 

  1734. /**

  1735.   * @brief  Helper macro to determine whether the internal channel

  1736.   *         selected is available on the ADC instance selected.

  1737.   * @note   The channel parameter must be a value defined from parameter

  1738.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1739.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1740.   *         must not be a value defined from parameter definition of

  1741.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1742.   *         or a value from functions where a channel number is

  1743.   *         returned from ADC registers,

  1744.   *         because internal and external channels share the same channel

  1745.   *         number in ADC registers. The differentiation is made only with

  1746.   *         parameters definitions of driver.

  1747.   * @param  __ADC_INSTANCE__ ADC instance

  1748.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1749.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  1750.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  1751.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  1752.   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.

  1753.   *         Value "1" if the internal channel selected is available on the ADC instance selected.

  1754.   */

  1755. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

  1756.   (                                                                            \

  1757.     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \

  1758.     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \

  1759.     ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                     \

  1760.   )

  1761. 

  1762. #if defined (ADC_SUPPORT_2_5_MSPS)

  1763. /**

  1764.   * @brief  Helper macro to define ADC analog watchdog parameter:

  1765.   *         define a single channel to monitor with analog watchdog

  1766.   *         from sequencer channel and groups definition.

  1767.   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().

  1768.   *         Example:

  1769.   *           LL_ADC_SetAnalogWDMonitChannels(

  1770.   *             ADC1, LL_ADC_AWD1,

  1771.   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))

  1772.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1773.   *         @arg @ref LL_ADC_CHANNEL_0

  1774.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  1775.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  1776.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  1777.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  1778.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  1779.   *         @arg @ref LL_ADC_CHANNEL_6

  1780.   *         @arg @ref LL_ADC_CHANNEL_7

  1781.   *         @arg @ref LL_ADC_CHANNEL_8

  1782.   *         @arg @ref LL_ADC_CHANNEL_9

  1783.   *         @arg @ref LL_ADC_CHANNEL_10

  1784.   *         @arg @ref LL_ADC_CHANNEL_11

  1785.   *         @arg @ref LL_ADC_CHANNEL_12

  1786.   *         @arg @ref LL_ADC_CHANNEL_13

  1787.   *         @arg @ref LL_ADC_CHANNEL_14

  1788.   *         @arg @ref LL_ADC_CHANNEL_15

  1789.   *         @arg @ref LL_ADC_CHANNEL_16

  1790.   *         @arg @ref LL_ADC_CHANNEL_17

  1791.   *         @arg @ref LL_ADC_CHANNEL_18

  1792.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (4)

  1793.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)

  1794.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)

  1795.   *

  1796.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  1797.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n

  1798.   *         (4) For ADC channel read back from ADC register,

  1799.   *             comparison with internal channel parameter to be done

  1800.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1801.   * @param  __GROUP__ This parameter can be one of the following values:

  1802.   *         @arg @ref LL_ADC_GROUP_REGULAR

  1803.   * @retval Returned value can be one of the following values:

  1804.   *         @arg @ref LL_ADC_AWD_DISABLE

  1805.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  1806.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  1807.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  1808.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  1809.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  1810.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  1811.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  1812.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  1813.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  1814.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  1815.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  1816.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  1817.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  1818.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  1819.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  1820.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  1821.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  1822.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  1823.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  1824.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  1825.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)

  1826.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)

  1827.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)

  1828.   *

  1829.   *         (0) On STM32WB, parameter available only on analog watchdog number: AWD1.

  1830.   */

  1831. #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \

  1832.   (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

  1833. #else

  1834. /**

  1835.   * @brief  Helper macro to define ADC analog watchdog parameter:

  1836.   *         define a single channel to monitor with analog watchdog

  1837.   *         from sequencer channel and groups definition.

  1838.   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().

  1839.   *         Example:

  1840.   *           LL_ADC_SetAnalogWDMonitChannels(

  1841.   *             ADC1, LL_ADC_AWD1,

  1842.   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))

  1843.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1844.   *         @arg @ref LL_ADC_CHANNEL_0

  1845.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  1846.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  1847.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  1848.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  1849.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  1850.   *         @arg @ref LL_ADC_CHANNEL_6

  1851.   *         @arg @ref LL_ADC_CHANNEL_7

  1852.   *         @arg @ref LL_ADC_CHANNEL_8

  1853.   *         @arg @ref LL_ADC_CHANNEL_9

  1854.   *         @arg @ref LL_ADC_CHANNEL_10

  1855.   *         @arg @ref LL_ADC_CHANNEL_11

  1856.   *         @arg @ref LL_ADC_CHANNEL_12

  1857.   *         @arg @ref LL_ADC_CHANNEL_13

  1858.   *         @arg @ref LL_ADC_CHANNEL_14

  1859.   *         @arg @ref LL_ADC_CHANNEL_15

  1860.   *         @arg @ref LL_ADC_CHANNEL_16

  1861.   *         @arg @ref LL_ADC_CHANNEL_17

  1862.   *         @arg @ref LL_ADC_CHANNEL_18

  1863.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (4)

  1864.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)

  1865.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)

  1866.   *

  1867.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  1868.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n

  1869.   *         (4) For ADC channel read back from ADC register,

  1870.   *             comparison with internal channel parameter to be done

  1871.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1872.   * @param  __GROUP__ This parameter can be one of the following values:

  1873.   *         @arg @ref LL_ADC_GROUP_REGULAR

  1874.   *         @arg @ref LL_ADC_GROUP_INJECTED

  1875.   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED

  1876.   * @retval Returned value can be one of the following values:

  1877.   *         @arg @ref LL_ADC_AWD_DISABLE

  1878.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  1879.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)(1)

  1880.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ       (1)

  1881.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  1882.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)(1)

  1883.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ          (1)

  1884.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  1885.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)(1)

  1886.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ          (1)

  1887.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  1888.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)(1)

  1889.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ          (1)

  1890.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  1891.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)(1)

  1892.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ          (1)

  1893.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  1894.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)(1)

  1895.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ          (1)

  1896.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  1897.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)(1)

  1898.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ          (1)

  1899.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  1900.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)(1)

  1901.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ         (1)

  1902.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  1903.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)(1)

  1904.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ          (1)

  1905.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  1906.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)(1)

  1907.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ          (1)

  1908.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  1909.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)(1)

  1910.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ          (1)

  1911.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  1912.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)(1)

  1913.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ         (1)

  1914.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  1915.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)(1)

  1916.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ         (1)

  1917.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  1918.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)(1)

  1919.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ         (1)

  1920.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  1921.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)(1)

  1922.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ         (1)

  1923.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  1924.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)(1)

  1925.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ         (1)

  1926.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  1927.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)(1)

  1928.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ         (1)

  1929.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  1930.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)(1)

  1931.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ         (1)

  1932.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  1933.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)(1)

  1934.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ         (1)

  1935.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  1936.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)(1)

  1937.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ         (1)

  1938.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)

  1939.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)

  1940.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)

  1941.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)

  1942.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)

  1943.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)

  1944.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)

  1945.   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)

  1946.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)

  1947.   *

  1948.   *         (0) On STM32WB, parameter available only on analog watchdog number: AWD1.

  1949.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  1950.   */

  1951. #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \

  1952.   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \

  1953.    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \

  1954.    :                                                                                                      \

  1955.    ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \

  1956.    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \

  1957.    :                                                                                                      \

  1958.    (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \

  1959.   )

  1960. #endif

  1961. 

  1962. /**

  1963.   * @brief  Helper macro to set the value of ADC analog watchdog threshold high

  1964.   *         or low in function of ADC resolution, when ADC resolution is

  1965.   *         different of 12 bits.

  1966.   * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()

  1967.   *         or @ref LL_ADC_SetAnalogWDThresholds().

  1968.   *         Example, with a ADC resolution of 8 bits, to set the value of

  1969.   *         analog watchdog threshold high (on 8 bits):

  1970.   *           LL_ADC_SetAnalogWDThresholds

  1971.   *            (< ADCx param >,

  1972.   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)

  1973.   *            );

  1974.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1975.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1976.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1977.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1978.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1979.   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF

  1980.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  1981.   */

  1982. #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \

  1983.   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

  1984. 

  1985. /**

  1986.   * @brief  Helper macro to get the value of ADC analog watchdog threshold high

  1987.   *         or low in function of ADC resolution, when ADC resolution is

  1988.   *         different of 12 bits.

  1989.   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().

  1990.   *         Example, with a ADC resolution of 8 bits, to get the value of

  1991.   *         analog watchdog threshold high (on 8 bits):

  1992.   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION

  1993.   *            (LL_ADC_RESOLUTION_8B,

  1994.   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)

  1995.   *            );

  1996.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1997.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1998.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1999.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2000.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2001.   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF

  2002.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  2003.   */

  2004. #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \

  2005.   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

  2006. 

  2007. /**

  2008.   * @brief  Helper macro to get the ADC analog watchdog threshold high

  2009.   *         or low from raw value containing both thresholds concatenated.

  2010.   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().

  2011.   *         Example, to get analog watchdog threshold high from the register raw value:

  2012.   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);

  2013.   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:

  2014.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  2015.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  2016.   * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  2017.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  2018.   */

  2019. #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \

  2020.   (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)

  2021. 

  2022. /**

  2023.   * @brief  Helper macro to set the ADC calibration value with both single ended

  2024.   *         and differential modes calibration factors concatenated.

  2025.   * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().

  2026.   *         Example, to set calibration factors single ended to 0x55

  2027.   *         and differential ended to 0x2A:

  2028.   *           LL_ADC_SetCalibrationFactor(

  2029.   *             ADC1,

  2030.   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))

  2031.   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F

  2032.   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F

  2033.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  2034.   */

  2035. #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \

  2036.   (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))

  2037. 

  2038. /**

  2039.   * @brief  Helper macro to select the ADC common instance

  2040.   *         to which is belonging the selected ADC instance.

  2041.   * @note   ADC common register instance can be used for:

  2042.   *         - Set parameters common to several ADC instances

  2043.   *         - Multimode (for devices with several ADC instances)

  2044.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  2045.   * @param  __ADCx__ ADC instance

  2046.   * @retval ADC common register instance

  2047.   */

  2048. #if defined(ADC1) && defined(ADC2) && defined(ADC3)

  2049. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  2050.   (ADC123_COMMON)

  2051. #elif defined(ADC1) && defined(ADC2)

  2052. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  2053.   (ADC12_COMMON)

  2054. #else

  2055. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  2056.   (ADC1_COMMON)

  2057. #endif

  2058. 

  2059. /**

  2060.   * @brief  Helper macro to check if all ADC instances sharing the same

  2061.   *         ADC common instance are disabled.

  2062.   * @note   This check is required by functions with setting conditioned to

  2063.   *         ADC state:

  2064.   *         All ADC instances of the ADC common group must be disabled.

  2065.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  2066.   * @note   On devices with only 1 ADC common instance, parameter of this macro

  2067.   *         is useless and can be ignored (parameter kept for compatibility

  2068.   *         with devices featuring several ADC common instances).

  2069.   * @param  __ADCXY_COMMON__ ADC common instance

  2070.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2071.   * @retval Value "0" if all ADC instances sharing the same ADC common instance

  2072.   *         are disabled.

  2073.   *         Value "1" if at least one ADC instance sharing the same ADC common instance

  2074.   *         is enabled.

  2075.   */

  2076. #if defined(ADC1) && defined(ADC2) && defined(ADC3)

  2077. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  2078.   (LL_ADC_IsEnabled(ADC1) |                                                    \

  2079.    LL_ADC_IsEnabled(ADC2) |                                                    \

  2080.    LL_ADC_IsEnabled(ADC3)  )

  2081. #elif defined(ADC1) && defined(ADC2)

  2082. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  2083.   (LL_ADC_IsEnabled(ADC1) |                                                    \

  2084.    LL_ADC_IsEnabled(ADC2)  )

  2085. #else

  2086. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  2087.   (LL_ADC_IsEnabled(ADC1))

  2088. #endif

  2089. 

  2090. /**

  2091.   * @brief  Helper macro to define the ADC conversion data full-scale digital

  2092.   *         value corresponding to the selected ADC resolution.

  2093.   * @note   ADC conversion data full-scale corresponds to voltage range

  2094.   *         determined by analog voltage references Vref+ and Vref-

  2095.   *         (refer to reference manual).

  2096.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  2097.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2098.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2099.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2100.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2101.   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)

  2102.   */

  2103. #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \

  2104.   (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))

  2105. 

  2106. /**

  2107.   * @brief  Helper macro to convert the ADC conversion data from

  2108.   *         a resolution to another resolution.

  2109.   * @param  __DATA__ ADC conversion data to be converted

  2110.   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted

  2111.   *         This parameter can be one of the following values:

  2112.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2113.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2114.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2115.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2116.   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion

  2117.   *         This parameter can be one of the following values:

  2118.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2119.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2120.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2121.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2122.   * @retval ADC conversion data to the requested resolution

  2123.   */

  2124. #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\

  2125.                                          __ADC_RESOLUTION_CURRENT__,\

  2126.                                          __ADC_RESOLUTION_TARGET__)            \

  2127.   (((__DATA__)                                                                 \

  2128.     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \

  2129.    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \

  2130.   )

  2131. 

  2132. /**

  2133.   * @brief  Helper macro to calculate the voltage (unit: mVolt)

  2134.   *         corresponding to a ADC conversion data (unit: digital value).

  2135.   * @note   Analog reference voltage (Vref+) must be either known from

  2136.   *         user board environment or can be calculated using ADC measurement

  2137.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2138.   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)

  2139.   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)

  2140.   *                       (unit: digital value).

  2141.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  2142.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2143.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2144.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2145.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2146.   * @retval ADC conversion data equivalent voltage value (unit: mVolt)

  2147.   */

  2148. #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\

  2149.                                       __ADC_DATA__,\

  2150.                                       __ADC_RESOLUTION__)                      \

  2151.   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \

  2152.    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \

  2153.   )

  2154. 

  2155. /**

  2156.   * @brief  Helper macro to calculate analog reference voltage (Vref+)

  2157.   *         (unit: mVolt) from ADC conversion data of internal voltage

  2158.   *         reference VrefInt.

  2159.   * @note   Computation is using VrefInt calibration value

  2160.   *         stored in system memory for each device during production.

  2161.   * @note   This voltage depends on user board environment: voltage level

  2162.   *         connected to pin Vref+.

  2163.   *         On devices with small package, the pin Vref+ is not present

  2164.   *         and internally bonded to pin Vdda.

  2165.   * @note   On this STM32 serie, calibration data of internal voltage reference

  2166.   *         VrefInt corresponds to a resolution of 12 bits,

  2167.   *         this is the recommended ADC resolution to convert voltage of

  2168.   *         internal voltage reference VrefInt.

  2169.   *         Otherwise, this macro performs the processing to scale

  2170.   *         ADC conversion data to 12 bits.

  2171.   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)

  2172.   *         of internal voltage reference VrefInt (unit: digital value).

  2173.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  2174.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2175.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2176.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2177.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2178.   * @retval Analog reference voltage (unit: mV)

  2179.   */

  2180. #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\

  2181.                                          __ADC_RESOLUTION__)                   \

  2182.   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \

  2183.    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \

  2184.                                       (__ADC_RESOLUTION__),                    \

  2185.                                       LL_ADC_RESOLUTION_12B))

  2186. 

  2187. /**

  2188.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  2189.   *         from ADC conversion data of internal temperature sensor.

  2190.   * @note   Computation is using temperature sensor calibration values

  2191.   *         stored in system memory for each device during production.

  2192.   * @note   Calculation formula:

  2193.   *           Temperature = ((TS_ADC_DATA - TS_CAL1)

  2194.   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))

  2195.   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP

  2196.   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC

  2197.   *                Avg_Slope = (TS_CAL2 - TS_CAL1)

  2198.   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)

  2199.   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature

  2200.   *                            TEMP_DEGC_CAL1 (calibrated in factory)

  2201.   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature

  2202.   *                            TEMP_DEGC_CAL2 (calibrated in factory)

  2203.   *         Caution: Calculation relevancy under reserve that calibration

  2204.   *                  parameters are correct (address and data).

  2205.   *                  To calculate temperature using temperature sensor

  2206.   *                  datasheet typical values (generic values less, therefore

  2207.   *                  less accurate than calibrated values),

  2208.   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().

  2209.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  2210.   *         defined as it impacts the ADC LSB equivalent voltage.

  2211.   * @note   Analog reference voltage (Vref+) must be either known from

  2212.   *         user board environment or can be calculated using ADC measurement

  2213.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2214.   * @note   On this STM32 serie, calibration data of temperature sensor

  2215.   *         corresponds to a resolution of 12 bits,

  2216.   *         this is the recommended ADC resolution to convert voltage of

  2217.   *         temperature sensor.

  2218.   *         Otherwise, this macro performs the processing to scale

  2219.   *         ADC conversion data to 12 bits.

  2220.   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)

  2221.   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal

  2222.   *                                 temperature sensor (unit: digital value).

  2223.   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature

  2224.   *                                 sensor voltage has been measured.

  2225.   *         This parameter can be one of the following values:

  2226.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2227.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2228.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2229.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2230.   * @retval Temperature (unit: degree Celsius)

  2231.   */

  2232. #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\

  2233.                                   __TEMPSENSOR_ADC_DATA__,\

  2234.                                   __ADC_RESOLUTION__)                              \

  2235.   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \

  2236.                                                     (__ADC_RESOLUTION__),          \

  2237.                                                     LL_ADC_RESOLUTION_12B)         \

  2238.                    * (__VREFANALOG_VOLTAGE__))                                     \

  2239.                   / TEMPSENSOR_CAL_VREFANALOG)                                     \

  2240.         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \

  2241.      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \

  2242.     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \

  2243.    ) + TEMPSENSOR_CAL1_TEMP                                                        \

  2244.   )

  2245. 

  2246. /**

  2247.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  2248.   *         from ADC conversion data of internal temperature sensor.

  2249.   * @note   Computation is using temperature sensor typical values

  2250.   *         (refer to device datasheet).

  2251.   * @note   Calculation formula:

  2252.   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)

  2253.   *                         / Avg_Slope + CALx_TEMP

  2254.   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC

  2255.   *                                   (unit: digital value)

  2256.   *                Avg_Slope        = temperature sensor slope

  2257.   *                                   (unit: uV/Degree Celsius)

  2258.   *                TS_TYP_CALx_VOLT = temperature sensor digital value at

  2259.   *                                   temperature CALx_TEMP (unit: mV)

  2260.   *         Caution: Calculation relevancy under reserve the temperature sensor

  2261.   *                  of the current device has characteristics in line with

  2262.   *                  datasheet typical values.

  2263.   *                  If temperature sensor calibration values are available on

  2264.   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),

  2265.   *                  temperature calculation will be more accurate using

  2266.   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().

  2267.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  2268.   *         defined as it impacts the ADC LSB equivalent voltage.

  2269.   * @note   Analog reference voltage (Vref+) must be either known from

  2270.   *         user board environment or can be calculated using ADC measurement

  2271.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2272.   * @note   ADC measurement data must correspond to a resolution of 12 bits

  2273.   *         (full scale digital value 4095). If not the case, the data must be

  2274.   *         preliminarily rescaled to an equivalent resolution of 12 bits.

  2275.   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).

  2276.   *                                       On STM32WB, refer to device datasheet parameter "Avg_Slope".

  2277.   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).

  2278.   *                                       On STM32WB, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).

  2279.   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)

  2280.   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)

  2281.   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).

  2282.   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.

  2283.   *         This parameter can be one of the following values:

  2284.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2285.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2286.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2287.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2288.   * @retval Temperature (unit: degree Celsius)

  2289.   */

  2290. #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\

  2291.                                              __TEMPSENSOR_TYP_CALX_V__,\

  2292.                                              __TEMPSENSOR_CALX_TEMP__,\

  2293.                                              __VREFANALOG_VOLTAGE__,\

  2294.                                              __TEMPSENSOR_ADC_DATA__,\

  2295.                                              __ADC_RESOLUTION__)               \

  2296.   ((( (                                                                        \

  2297.        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \

  2298.                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \

  2299.                  * 1000UL)                                                     \

  2300.        -                                                                       \

  2301.        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \

  2302.                  * 1000UL)                                                     \

  2303.       )                                                                        \

  2304.     ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                 \

  2305.    ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                     \

  2306.   )

  2307. 

  2308. /**

  2309.   * @}

  2310.   */

  2311. 

  2312. /**

  2313.   * @}

  2314.   */

  2315. 

  2316. 

  2317. /* Exported functions --------------------------------------------------------*/

  2318. /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions

  2319.   * @{

  2320.   */

  2321. 

  2322. /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management

  2323.   * @{

  2324.   */

  2325. /* Note: LL ADC functions to set DMA transfer are located into sections of    */

  2326. /*       configuration of ADC instance, groups and multimode (if available):  */

  2327. /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */

  2328. 

  2329. /**

  2330.   * @brief  Function to help to configure DMA transfer from ADC: retrieve the

  2331.   *         ADC register address from ADC instance and a list of ADC registers

  2332.   *         intended to be used (most commonly) with DMA transfer.

  2333.   * @note   These ADC registers are data registers:

  2334.   *         when ADC conversion data is available in ADC data registers,

  2335.   *         ADC generates a DMA transfer request.

  2336.   * @note   This macro is intended to be used with LL DMA driver, refer to

  2337.   *         function "LL_DMA_ConfigAddresses()".

  2338.   *         Example:

  2339.   *           LL_DMA_ConfigAddresses(DMA1,

  2340.   *                                  LL_DMA_CHANNEL_1,

  2341.   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),

  2342.   *                                  (uint32_t)&< array or variable >,

  2343.   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

  2344.   * @note   For devices with several ADC: in multimode, some devices

  2345.   *         use a different data register outside of ADC instance scope

  2346.   *         (common data register). This macro manages this register difference,

  2347.   *         only ADC instance has to be set as parameter.

  2348.   * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr

  2349.   * @param  ADCx ADC instance

  2350.   * @param  Register This parameter can be one of the following values:

  2351.   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA

  2352.   * @retval ADC register address

  2353.   */

  2354. __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)

  2355. {

  2356.   /* Prevent unused argument(s) compilation warning */

  2357.   (void)(Register);

  2358. 

  2359.   /* Retrieve address of register DR */

  2360.   return (uint32_t)&(ADCx->DR);

  2361. }

  2362. 

  2363. /**

  2364.   * @}

  2365.   */

  2366. 

  2367. /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances

  2368.   * @{

  2369.   */

  2370. 

  2371. /**

  2372.   * @brief  Set parameter common to several ADC: Clock source and prescaler.

  2373.   * @note   ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices.

  2374.   *         Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum)

  2375.   *         Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum)

  2376.   *         For ADC maximum frequency, refer to datasheet of the selected device.

  2377.   * @note   On this STM32 serie, if ADC group injected is used, some

  2378.   *         clock ratio constraints between ADC clock and AHB clock

  2379.   *         must be respected.

  2380.   *         Refer to reference manual.

  2381.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2382.   *         ADC state:

  2383.   *         All ADC instances of the ADC common group must be disabled.

  2384.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  2385.   *         ADC instance or by using helper macro helper macro

  2386.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  2387.   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n

  2388.   *         CCR      PRESC          LL_ADC_SetCommonClock

  2389.   * @param  ADCxy_COMMON ADC common instance

  2390.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2391.   * @param  CommonClock This parameter can be one of the following values:

  2392.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (*)

  2393.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 (*)

  2394.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 (*)

  2395.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

  2396.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

  2397.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

  2398.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6

  2399.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8

  2400.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10

  2401.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12

  2402.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16

  2403.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32

  2404.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64

  2405.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128

  2406.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256

  2407.   *

  2408.   *         (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx.

  2409.   * @retval None

  2410.   */

  2411. __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)

  2412. {

  2413. #if defined (ADC_SUPPORT_2_5_MSPS)

  2414.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);

  2415. #else

  2416.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);

  2417. #endif

  2418. }

  2419. 

  2420. /**

  2421.   * @brief  Get parameter common to several ADC: Clock source and prescaler.

  2422.   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n

  2423.   *         CCR      PRESC          LL_ADC_GetCommonClock

  2424.   * @param  ADCxy_COMMON ADC common instance

  2425.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2426.   * @retval Returned value can be one of the following values:

  2427.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (*)

  2428.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 (*)

  2429.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 (*)

  2430.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

  2431.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

  2432.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

  2433.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6

  2434.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8

  2435.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10

  2436.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12

  2437.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16

  2438.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32

  2439.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64

  2440.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128

  2441.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256

  2442.   *

  2443.   *         (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx.

  2444.   */

  2445. __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)

  2446. {

  2447. #if defined (ADC_SUPPORT_2_5_MSPS)

  2448.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));

  2449. #else

  2450.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));

  2451. #endif

  2452. }

  2453. 

  2454. /**

  2455.   * @brief  Set parameter common to several ADC: measurement path to

  2456.   *         internal channels (VrefInt, temperature sensor, ...).

  2457.   *         Configure all paths (overwrite current configuration).

  2458.   * @note   One or several values can be selected.

  2459.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2460.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2461.   *         The values not selected are removed from configuration.

  2462.   * @note   Stabilization time of measurement path to internal channel:

  2463.   *         After enabling internal paths, before starting ADC conversion,

  2464.   *         a delay is required for internal voltage reference and

  2465.   *         temperature sensor stabilization time.

  2466.   *         Refer to device datasheet.

  2467.   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.

  2468.   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.

  2469.   * @note   ADC internal channel sampling time constraint:

  2470.   *         For ADC conversion of internal channels,

  2471.   *         a sampling time minimum value is required.

  2472.   *         Refer to device datasheet.

  2473.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2474.   *         ADC state:

  2475.   *         All ADC instances of the ADC common group must be disabled.

  2476.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  2477.   *         ADC instance or by using helper macro helper macro

  2478.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  2479.   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n

  2480.   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n

  2481.   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh

  2482.   * @param  ADCxy_COMMON ADC common instance

  2483.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2484.   * @param  PathInternal This parameter can be a combination of the following values:

  2485.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2486.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2487.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2488.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  2489.   * @retval None

  2490.   */

  2491. __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)

  2492. {

  2493.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);

  2494. }

  2495. 

  2496. /**

  2497.   * @brief  Set parameter common to several ADC: measurement path to

  2498.   *         internal channels (VrefInt, temperature sensor, ...).

  2499.   *         Add paths to the current configuration.

  2500.   * @note   One or several values can be selected.

  2501.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2502.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2503.   * @note   Stabilization time of measurement path to internal channel:

  2504.   *         After enabling internal paths, before starting ADC conversion,

  2505.   *         a delay is required for internal voltage reference and

  2506.   *         temperature sensor stabilization time.

  2507.   *         Refer to device datasheet.

  2508.   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.

  2509.   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.

  2510.   * @note   ADC internal channel sampling time constraint:

  2511.   *         For ADC conversion of internal channels,

  2512.   *         a sampling time minimum value is required.

  2513.   *         Refer to device datasheet.

  2514.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2515.   *         ADC state:

  2516.   *         All ADC instances of the ADC common group must be disabled.

  2517.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  2518.   *         ADC instance or by using helper macro helper macro

  2519.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  2520.   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n

  2521.   *         CCR      TSEN           LL_ADC_SetCommonPathInternalChAdd\n

  2522.   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalChAdd

  2523.   * @param  ADCxy_COMMON ADC common instance

  2524.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2525.   * @param  PathInternal This parameter can be a combination of the following values:

  2526.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2527.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2528.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2529.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  2530.   * @retval None

  2531.   */

  2532. __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)

  2533. {

  2534.   SET_BIT(ADCxy_COMMON->CCR, PathInternal);

  2535. }

  2536. 

  2537. /**

  2538.   * @brief  Set parameter common to several ADC: measurement path to

  2539.   *         internal channels (VrefInt, temperature sensor, ...).

  2540.   *         Remove paths to the current configuration.

  2541.   * @note   One or several values can be selected.

  2542.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2543.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2544.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2545.   *         ADC state:

  2546.   *         All ADC instances of the ADC common group must be disabled.

  2547.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  2548.   *         ADC instance or by using helper macro helper macro

  2549.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  2550.   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n

  2551.   *         CCR      TSEN           LL_ADC_SetCommonPathInternalChRem\n

  2552.   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalChRem

  2553.   * @param  ADCxy_COMMON ADC common instance

  2554.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2555.   * @param  PathInternal This parameter can be a combination of the following values:

  2556.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2557.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2558.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2559.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  2560.   * @retval None

  2561.   */

  2562. __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)

  2563. {

  2564.   CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);

  2565. }

  2566. 

  2567. /**

  2568.   * @brief  Get parameter common to several ADC: measurement path to internal

  2569.   *         channels (VrefInt, temperature sensor, ...).

  2570.   * @note   One or several values can be selected.

  2571.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2572.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2573.   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n

  2574.   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n

  2575.   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh

  2576.   * @param  ADCxy_COMMON ADC common instance

  2577.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2578.   * @retval Returned value can be a combination of the following values:

  2579.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2580.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2581.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2582.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  2583.   */

  2584. __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)

  2585. {

  2586.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));

  2587. }

  2588. 

  2589. /**

  2590.   * @}

  2591.   */

  2592. 

  2593. /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance

  2594.   * @{

  2595.   */

  2596. 

  2597. #if defined (ADC_SUPPORT_2_5_MSPS)

  2598. /**

  2599.   * @brief  Set ADC instance clock source and prescaler.

  2600.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2601.   *         ADC state:

  2602.   *         ADC must be disabled.

  2603.   * @rmtoll CFGR2    CKMODE         LL_ADC_SetClock

  2604.   * @param  ADCx ADC instance

  2605.   * @param  ClockSource This parameter can be one of the following values:

  2606.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

  2607.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

  2608.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)

  2609.   *         @arg @ref LL_ADC_CLOCK_ASYNC (1)

  2610.   *

  2611.   *         (1) Asynchronous clock prescaler can be configured using

  2612.   *             function @ref LL_ADC_SetCommonClock().\n

  2613.   *         (2) Caution: This parameter has some clock ratio constraints:

  2614.   *             This configuration must be enabled only if PCLK has a 50%

  2615.   *             duty clock cycle (APB prescaler configured inside the RCC

  2616.   *             must be bypassed and the system clock must by 50% duty

  2617.   *             cycle).

  2618.   *             Refer to reference manual.

  2619.   * @retval None

  2620.   */

  2621. __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)

  2622. {

  2623.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);

  2624. }

  2625. 

  2626. /**

  2627.   * @brief  Get ADC instance clock source and prescaler.

  2628.   * @rmtoll CFGR2    CKMODE         LL_ADC_GetClock

  2629.   * @param  ADCx ADC instance

  2630.   * @retval Returned value can be one of the following values:

  2631.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

  2632.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

  2633.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)

  2634.   *         @arg @ref LL_ADC_CLOCK_ASYNC (1)

  2635.   *

  2636.   *         (1) Asynchronous clock prescaler can be retrieved using

  2637.   *             function @ref LL_ADC_GetCommonClock().\n

  2638.   *         (2) Caution: This parameter has some clock ratio constraints:

  2639.   *             This configuration must be enabled only if PCLK has a 50%

  2640.   *             duty clock cycle (APB prescaler configured inside the RCC

  2641.   *             must be bypassed and the system clock must by 50% duty

  2642.   *             cycle).

  2643.   *             Refer to reference manual.

  2644.   */

  2645. __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)

  2646. {

  2647.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));

  2648. }

  2649. #endif

  2650. 

  2651. #if defined (ADC_SUPPORT_2_5_MSPS)

  2652. /**

  2653.   * @brief  Set ADC calibration factor in the mode single-ended

  2654.   *         or differential (for devices with differential mode available).

  2655.   * @note   This function is intended to set calibration parameters

  2656.   *         without having to perform a new calibration using

  2657.   *         @ref LL_ADC_StartCalibration().

  2658.   * @note   For devices with differential mode available:

  2659.   *         Calibration of offset is specific to each of

  2660.   *         single-ended and differential modes

  2661.   *         (calibration factor must be specified for each of these

  2662.   *         differential modes, if used afterwards and if the application

  2663.   *         requires their calibration).

  2664.   * @note   In case of setting calibration factors of both modes single ended

  2665.   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):

  2666.   *         both calibration factors must be concatenated.

  2667.   *         To perform this processing, use helper macro

  2668.   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().

  2669.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2670.   *         ADC state:

  2671.   *         ADC must be enabled, without calibration on going, without conversion

  2672.   *         on going on group regular.

  2673.   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n

  2674.   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor

  2675.   * @param  ADCx ADC instance

  2676.   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F

  2677.   * @retval None

  2678.   */

  2679. __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)

  2680. {

  2681.   MODIFY_REG(ADCx->CALFACT,

  2682.              ADC_CALFACT_CALFACT,

  2683.              CalibrationFactor);

  2684. }

  2685. #else

  2686. /**

  2687.   * @brief  Set ADC calibration factor in the mode single-ended

  2688.   *         or differential (for devices with differential mode available).

  2689.   * @note   This function is intended to set calibration parameters

  2690.   *         without having to perform a new calibration using

  2691.   *         @ref LL_ADC_StartCalibration().

  2692.   * @note   For devices with differential mode available:

  2693.   *         Calibration of offset is specific to each of

  2694.   *         single-ended and differential modes

  2695.   *         (calibration factor must be specified for each of these

  2696.   *         differential modes, if used afterwards and if the application

  2697.   *         requires their calibration).

  2698.   * @note   In case of setting calibration factors of both modes single ended

  2699.   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):

  2700.   *         both calibration factors must be concatenated.

  2701.   *         To perform this processing, use helper macro

  2702.   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().

  2703.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2704.   *         ADC state:

  2705.   *         ADC must be enabled, without calibration on going, without conversion

  2706.   *         on going on group regular.

  2707.   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n

  2708.   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor

  2709.   * @param  ADCx ADC instance

  2710.   * @param  SingleDiff This parameter can be one of the following values:

  2711.   *         @arg @ref LL_ADC_SINGLE_ENDED

  2712.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED     (1)

  2713.   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED (1)

  2714.   *

  2715.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  2716.   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F

  2717.   * @retval None

  2718.   */

  2719. __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)

  2720. {

  2721.   MODIFY_REG(ADCx->CALFACT,

  2722.              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,

  2723.              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));

  2724. }

  2725. #endif /* ADC_SUPPORT_2_5_MSPS */

  2726. 

  2727. #if defined (ADC_SUPPORT_2_5_MSPS)

  2728. /**

  2729.   * @brief  Get ADC calibration factor in the mode single-ended

  2730.   *         or differential (for devices with differential mode available).

  2731.   * @note   Calibration factors are set by hardware after performing

  2732.   *         a calibration run using function @ref LL_ADC_StartCalibration().

  2733.   * @note   For devices with differential mode available:

  2734.   *         Calibration of offset is specific to each of

  2735.   *         single-ended and differential modes

  2736.   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n

  2737.   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor

  2738.   * @param  ADCx ADC instance

  2739.   * @retval Value between Min_Data=0x00 and Max_Data=0x7F

  2740.   */

  2741. __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)

  2742. {

  2743.   return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));

  2744. }

  2745. #else

  2746. /**

  2747.   * @brief  Get ADC calibration factor in the mode single-ended

  2748.   *         or differential (for devices with differential mode available).

  2749.   * @note   Calibration factors are set by hardware after performing

  2750.   *         a calibration run using function @ref LL_ADC_StartCalibration().

  2751.   * @note   For devices with differential mode available:

  2752.   *         Calibration of offset is specific to each of

  2753.   *         single-ended and differential modes

  2754.   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n

  2755.   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor

  2756.   * @param  ADCx ADC instance

  2757.   * @param  SingleDiff This parameter can be one of the following values:

  2758.   *         @arg @ref LL_ADC_SINGLE_ENDED

  2759.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  2760.   * @retval Value between Min_Data=0x00 and Max_Data=0x7F

  2761.   */

  2762. __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)

  2763. {

  2764.   /* Retrieve bits with position in register depending on parameter           */

  2765.   /* "SingleDiff".                                                            */

  2766.   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */

  2767.   /* containing other bits reserved for other purpose.                        */

  2768.   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));

  2769. }

  2770. #endif /* ADC_SUPPORT_2_5_MSPS */

  2771. /**

  2772.   * @brief  Set ADC resolution.

  2773.   *         Refer to reference manual for alignments formats

  2774.   *         dependencies to ADC resolutions.

  2775.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2776.   *         ADC state:

  2777.   *         ADC must be disabled or enabled without conversion on going

  2778.   *         on either groups regular or injected.

  2779.   * @rmtoll CFGR     RES            LL_ADC_SetResolution

  2780.   * @param  ADCx ADC instance

  2781.   * @param  Resolution This parameter can be one of the following values:

  2782.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2783.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2784.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2785.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2786.   * @retval None

  2787.   */

  2788. __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)

  2789. {

  2790. #if defined (ADC_SUPPORT_2_5_MSPS)

  2791.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);

  2792. #else

  2793.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

  2794. #endif

  2795. }

  2796. 

  2797. /**

  2798.   * @brief  Get ADC resolution.

  2799.   *         Refer to reference manual for alignments formats

  2800.   *         dependencies to ADC resolutions.

  2801.   * @rmtoll CFGR     RES            LL_ADC_GetResolution

  2802.   * @param  ADCx ADC instance

  2803.   * @retval Returned value can be one of the following values:

  2804.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2805.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2806.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2807.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2808.   */

  2809. __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)

  2810. {

  2811. #if defined (ADC_SUPPORT_2_5_MSPS)

  2812.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));

  2813. #else

  2814.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

  2815. #endif

  2816. }

  2817. 

  2818. /**

  2819.   * @brief  Set ADC conversion data alignment.

  2820.   * @note   Refer to reference manual for alignments formats

  2821.   *         dependencies to ADC resolutions.

  2822.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2823.   *         ADC state:

  2824.   *         ADC must be disabled or enabled without conversion on going

  2825.   *         on either groups regular or injected.

  2826.   * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment

  2827.   * @param  ADCx ADC instance

  2828.   * @param  DataAlignment This parameter can be one of the following values:

  2829.   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT

  2830.   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT

  2831.   * @retval None

  2832.   */

  2833. __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)

  2834. {

  2835. #if defined (ADC_SUPPORT_2_5_MSPS)

  2836.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);

  2837. #else

  2838.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);

  2839. #endif

  2840. }

  2841. 

  2842. /**

  2843.   * @brief  Get ADC conversion data alignment.

  2844.   * @note   Refer to reference manual for alignments formats

  2845.   *         dependencies to ADC resolutions.

  2846.   * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment

  2847.   * @param  ADCx ADC instance

  2848.   * @retval Returned value can be one of the following values:

  2849.   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT

  2850.   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT

  2851.   */

  2852. __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)

  2853. {

  2854. #if defined (ADC_SUPPORT_2_5_MSPS)

  2855.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));

  2856. #else

  2857.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));

  2858. #endif

  2859. }

  2860. 

  2861. /**

  2862.   * @brief  Set ADC low power mode.

  2863.   * @note   Description of ADC low power modes:

  2864.   *         - ADC low power mode "auto wait": Dynamic low power mode,

  2865.   *           ADC conversions occurrences are limited to the minimum necessary

  2866.   *           in order to reduce power consumption.

  2867.   *           New ADC conversion starts only when the previous

  2868.   *           unitary conversion data (for ADC group regular)

  2869.   *           or previous sequence conversions data (for ADC group injected)

  2870.   *           has been retrieved by user software.

  2871.   *           In the meantime, ADC remains idle: does not performs any

  2872.   *           other conversion.

  2873.   *           This mode allows to automatically adapt the ADC conversions

  2874.   *           triggers to the speed of the software that reads the data.

  2875.   *           Moreover, this avoids risk of overrun for low frequency

  2876.   *           applications.

  2877.   *           How to use this low power mode:

  2878.   *           - It is not recommended to use with interruption or DMA

  2879.   *             since these modes have to clear immediately the EOC flag

  2880.   *             (by CPU to free the IRQ pending event or by DMA).

  2881.   *             Auto wait will work but fort a very short time, discarding

  2882.   *             its intended benefit (except specific case of high load of CPU

  2883.   *             or DMA transfers which can justify usage of auto wait).

  2884.   *           - Do use with polling: 1. Start conversion,

  2885.   *             2. Later on, when conversion data is needed: poll for end of

  2886.   *             conversion  to ensure that conversion is completed and

  2887.   *             retrieve ADC conversion data. This will trig another

  2888.   *             ADC conversion start.

  2889.   *         - ADC low power mode "auto power-off" (feature available on

  2890.   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):

  2891.   *           the ADC automatically powers-off after a conversion and

  2892.   *           automatically wakes up when a new conversion is triggered

  2893.   *           (with startup time between trigger and start of sampling).

  2894.   *           This feature can be combined with low power mode "auto wait".

  2895.   * @note   With ADC low power mode "auto wait", the ADC conversion data read

  2896.   *         is corresponding to previous ADC conversion start, independently

  2897.   *         of delay during which ADC was idle.

  2898.   *         Therefore, the ADC conversion data may be outdated: does not

  2899.   *         correspond to the current voltage level on the selected

  2900.   *         ADC channel.

  2901.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2902.   *         ADC state:

  2903.   *         ADC must be disabled or enabled without conversion on going

  2904.   *         on either groups regular or injected.

  2905.   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode

  2906.   * @param  ADCx ADC instance

  2907.   * @param  LowPowerMode This parameter can be one of the following values:

  2908.   *         @arg @ref LL_ADC_LP_MODE_NONE

  2909.   *         @arg @ref LL_ADC_LP_AUTOWAIT

  2910.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF          (1)

  2911.   *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (1)

  2912.   *

  2913.   *         (1) On STM32WB serie, parameter available only on devices: STM32WB10xx, STM32WB15xx.

  2914.   * @retval None

  2915.   */

  2916. __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)

  2917. {

  2918. #if defined (ADC_SUPPORT_2_5_MSPS)

  2919.   MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);

  2920. #else

  2921.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);

  2922. #endif

  2923. }

  2924. 

  2925. /**

  2926.   * @brief  Get ADC low power mode:

  2927.   * @note   Description of ADC low power modes:

  2928.   *         - ADC low power mode "auto wait": Dynamic low power mode,

  2929.   *           ADC conversions occurrences are limited to the minimum necessary

  2930.   *           in order to reduce power consumption.

  2931.   *           New ADC conversion starts only when the previous

  2932.   *           unitary conversion data (for ADC group regular)

  2933.   *           or previous sequence conversions data (for ADC group injected)

  2934.   *           has been retrieved by user software.

  2935.   *           In the meantime, ADC remains idle: does not performs any

  2936.   *           other conversion.

  2937.   *           This mode allows to automatically adapt the ADC conversions

  2938.   *           triggers to the speed of the software that reads the data.

  2939.   *           Moreover, this avoids risk of overrun for low frequency

  2940.   *           applications.

  2941.   *           How to use this low power mode:

  2942.   *           - It is not recommended to use with interruption or DMA

  2943.   *             since these modes have to clear immediately the EOC flag

  2944.   *             (by CPU to free the IRQ pending event or by DMA).

  2945.   *             Auto wait will work but fort a very short time, discarding

  2946.   *             its intended benefit (except specific case of high load of CPU

  2947.   *             or DMA transfers which can justify usage of auto wait).

  2948.   *           - Do use with polling: 1. Start conversion,

  2949.   *             2. Later on, when conversion data is needed: poll for end of

  2950.   *             conversion  to ensure that conversion is completed and

  2951.   *             retrieve ADC conversion data. This will trig another

  2952.   *             ADC conversion start.

  2953.   *         - ADC low power mode "auto power-off" (feature available on

  2954.   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):

  2955.   *           the ADC automatically powers-off after a conversion and

  2956.   *           automatically wakes up when a new conversion is triggered

  2957.   *           (with startup time between trigger and start of sampling).

  2958.   *           This feature can be combined with low power mode "auto wait".

  2959.   * @note   With ADC low power mode "auto wait", the ADC conversion data read

  2960.   *         is corresponding to previous ADC conversion start, independently

  2961.   *         of delay during which ADC was idle.

  2962.   *         Therefore, the ADC conversion data may be outdated: does not

  2963.   *         correspond to the current voltage level on the selected

  2964.   *         ADC channel.

  2965.   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode

  2966.   * @param  ADCx ADC instance

  2967.   * @retval Returned value can be one of the following values:

  2968.   *         @arg @ref LL_ADC_LP_MODE_NONE

  2969.   *         @arg @ref LL_ADC_LP_AUTOWAIT

  2970.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF          (1)

  2971.   *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (1)

  2972.   *

  2973.   *         (1) On STM32WB serie, parameter available only on devices: STM32WB10xx, STM32WB15xx.

  2974.   */

  2975. __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)

  2976. {

  2977. #if defined (ADC_SUPPORT_2_5_MSPS)

  2978.   return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));

  2979. #else

  2980.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));

  2981. #endif

  2982. }

  2983. 

  2984. #if defined(ADC_SUPPORT_2_5_MSPS)

  2985. /**

  2986.   * @brief  Set ADC trigger frequency mode.

  2987.   * @note   ADC trigger frequency mode must be set to low frequency when

  2988.   *         a duration is exceeded before ADC conversion start trigger event

  2989.   *         (between ADC enable and ADC conversion start trigger event

  2990.   *         or between two ADC conversion start trigger event).

  2991.   *         Duration value: Refer to device datasheet, parameter "tIdle".

  2992.   * @note   When ADC trigger frequency mode is set to low frequency,

  2993.   *         some rearm cycles are inserted before performing ADC conversion

  2994.   *         start, inducing a delay of 2 ADC clock cycles.

  2995.   * @note   Usage of ADC trigger frequency mode with ADC low power mode:

  2996.   *         - Low power mode auto wait: Only the first ADC conversion

  2997.   *           start trigger inserts the rearm delay.

  2998.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2999.   *         ADC state:

  3000.   *         ADC must be disabled or enabled without conversion on going

  3001.   *         on group regular.

  3002.   * @rmtoll CFGR2    LFTRIG         LL_ADC_SetTriggerFrequencyMode

  3003.   * @param  ADCx ADC instance

  3004.   * @param  TriggerFrequencyMode This parameter can be one of the following values:

  3005.   *         @arg @ref LL_ADC_TRIGGER_FREQ_HIGH

  3006.   *         @arg @ref LL_ADC_TRIGGER_FREQ_LOW

  3007.   * @retval None

  3008.   */

  3009. __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)

  3010. {

  3011.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);

  3012. }

  3013. 

  3014. /**

  3015.   * @brief  Get ADC trigger frequency mode.

  3016.   * @rmtoll CFGR2    LFTRIG         LL_ADC_GetTriggerFrequencyMode

  3017.   * @param  ADCx ADC instance

  3018.   * @retval Returned value can be one of the following values:

  3019.   *         @arg @ref LL_ADC_TRIGGER_FREQ_HIGH

  3020.   *         @arg @ref LL_ADC_TRIGGER_FREQ_LOW

  3021.   */

  3022. __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx)

  3023. {

  3024.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));

  3025. }

  3026. 

  3027. #endif

  3028. #if defined(ADC_SUPPORT_2_5_MSPS)

  3029. /**

  3030.   * @brief  Set sampling time common to a group of channels.

  3031.   * @note   Unit: ADC clock cycles.

  3032.   * @note   On this STM32 serie, sampling time scope is on ADC instance:

  3033.   *         Sampling time common to all channels, independently

  3034.   *         of channels mapped on ADC group regular or injected.

  3035.   *         (on some other STM32 families, sampling time is channel wise)

  3036.   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be

  3037.   *         converted:

  3038.   *         sampling time constraints must be respected (sampling time can be

  3039.   *         adjusted in function of ADC clock frequency and sampling time

  3040.   *         setting).

  3041.   *         Refer to device datasheet for timings values (parameters TS_vrefint,

  3042.   *         TS_temp, ...).

  3043.   * @note   Conversion time is the addition of sampling time and processing time.

  3044.   *         On this STM32 serie, ADC processing time is:

  3045.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  3046.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  3047.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  3048.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  3049.   * @note   In case of ADC conversion of internal channel (VrefInt,

  3050.   *         temperature sensor, ...), a sampling time minimum value

  3051.   *         is required.

  3052.   *         Refer to device datasheet.

  3053.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3054.   *         ADC state:

  3055.   *         ADC must be disabled or enabled without conversion on going

  3056.   *         on either groups regular or injected.

  3057.   * @rmtoll SMPR     SMP1           LL_ADC_SetSamplingTimeCommonChannels\n

  3058.   * @rmtoll SMPR     SMP2           LL_ADC_SetSamplingTimeCommonChannels

  3059.   * @param  ADCx ADC instance

  3060.   * @param  SamplingTimeY This parameter can be one of the following values:

  3061.   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1

  3062.   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2

  3063.   * @param  SamplingTime This parameter can be one of the following values:

  3064.   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5

  3065.   *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5

  3066.   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5

  3067.   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5

  3068.   *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5

  3069.   *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5

  3070.   *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5

  3071.   *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5

  3072.   * @retval None

  3073.   */

  3074. __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, uint32_t SamplingTime)

  3075. {

  3076.   MODIFY_REG(ADCx->SMPR,

  3077.              ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),

  3078.              SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));

  3079. }

  3080. 

  3081. /**

  3082.   * @brief  Get sampling time common to a group of channels.

  3083.   * @note   Unit: ADC clock cycles.

  3084.   * @note   On this STM32 serie, sampling time scope is on ADC instance:

  3085.   *         Sampling time common to all channels, independently

  3086.   *         of channels mapped on ADC group regular or injected.

  3087.   *         (on some other STM32 families, sampling time is channel wise)

  3088.   * @note   Conversion time is the addition of sampling time and processing time.

  3089.   *         On this STM32 serie, ADC processing time is:

  3090.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  3091.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  3092.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  3093.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  3094.   * @rmtoll SMPR     SMP1           LL_ADC_GetSamplingTimeCommonChannels\n

  3095.   * @rmtoll SMPR     SMP2           LL_ADC_GetSamplingTimeCommonChannels

  3096.   * @param  ADCx ADC instance

  3097.   * @param  SamplingTimeY This parameter can be one of the following values:

  3098.   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1

  3099.   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2

  3100.   * @retval Returned value can be one of the following values:

  3101.   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5

  3102.   *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5

  3103.   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5

  3104.   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5

  3105.   *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5

  3106.   *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5

  3107.   *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5

  3108.   *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5

  3109.   */

  3110. __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)

  3111. {

  3112.   return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))

  3113.                     >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));

  3114. }

  3115. 

  3116. #endif

  3117. 

  3118. #if defined(ADC_SUPPORT_2_5_MSPS)

  3119. /* Feature "ADC offset" not available on ADC peripheral of this STM32WB device */

  3120. #else

  3121. /**

  3122.   * @brief  Set ADC selected offset number 1, 2, 3 or 4.

  3123.   * @note   This function set the 2 items of offset configuration:

  3124.   *         - ADC channel to which the offset programmed will be applied

  3125.   *           (independently of channel mapped on ADC group regular

  3126.   *           or group injected)

  3127.   *         - Offset level (offset to be subtracted from the raw

  3128.   *           converted data).

  3129.   * @note   Caution: Offset format is dependent to ADC resolution:

  3130.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  3131.   *         are set to 0.

  3132.   * @note   This function enables the offset, by default. It can be forced

  3133.   *         to disable state using function LL_ADC_SetOffsetState().

  3134.   * @note   If a channel is mapped on several offsets numbers, only the offset

  3135.   *         with the lowest value is considered for the subtraction.

  3136.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3137.   *         ADC state:

  3138.   *         ADC must be disabled or enabled without conversion on going

  3139.   *         on either groups regular or injected.

  3140.   * @note   On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs

  3141.   *         coming from GPIO pads (ADC_IN1..5).

  3142.   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n

  3143.   *         OFR1     OFFSET1        LL_ADC_SetOffset\n

  3144.   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n

  3145.   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n

  3146.   *         OFR2     OFFSET2        LL_ADC_SetOffset\n

  3147.   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n

  3148.   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n

  3149.   *         OFR3     OFFSET3        LL_ADC_SetOffset\n

  3150.   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n

  3151.   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n

  3152.   *         OFR4     OFFSET4        LL_ADC_SetOffset\n

  3153.   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset

  3154.   * @param  ADCx ADC instance

  3155.   * @param  Offsety This parameter can be one of the following values:

  3156.   *         @arg @ref LL_ADC_OFFSET_1

  3157.   *         @arg @ref LL_ADC_OFFSET_2

  3158.   *         @arg @ref LL_ADC_OFFSET_3

  3159.   *         @arg @ref LL_ADC_OFFSET_4

  3160.   * @param  Channel This parameter can be one of the following values:

  3161.   *         @arg @ref LL_ADC_CHANNEL_0

  3162.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  3163.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  3164.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  3165.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  3166.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  3167.   *         @arg @ref LL_ADC_CHANNEL_6

  3168.   *         @arg @ref LL_ADC_CHANNEL_7

  3169.   *         @arg @ref LL_ADC_CHANNEL_8

  3170.   *         @arg @ref LL_ADC_CHANNEL_9

  3171.   *         @arg @ref LL_ADC_CHANNEL_10

  3172.   *         @arg @ref LL_ADC_CHANNEL_11

  3173.   *         @arg @ref LL_ADC_CHANNEL_12

  3174.   *         @arg @ref LL_ADC_CHANNEL_13

  3175.   *         @arg @ref LL_ADC_CHANNEL_14

  3176.   *         @arg @ref LL_ADC_CHANNEL_15

  3177.   *         @arg @ref LL_ADC_CHANNEL_16

  3178.   *         @arg @ref LL_ADC_CHANNEL_17

  3179.   *         @arg @ref LL_ADC_CHANNEL_18

  3180.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  3181.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  3182.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  3183.   *

  3184.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  3185.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  3186.   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF

  3187.   * @retval None

  3188.   */

  3189. __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)

  3190. {

  3191.   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  3192. 

  3193.   MODIFY_REG(*preg,

  3194.              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,

  3195.              ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);

  3196. }

  3197. 

  3198. /**

  3199.   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

  3200.   *         Channel to which the offset programmed will be applied

  3201.   *         (independently of channel mapped on ADC group regular

  3202.   *         or group injected)

  3203.   * @note   Usage of the returned channel number:

  3204.   *         - To reinject this channel into another function LL_ADC_xxx:

  3205.   *           the returned channel number is only partly formatted on definition

  3206.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  3207.   *           with parts of literals LL_ADC_CHANNEL_x or using

  3208.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3209.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3210.   *           as parameter for another function.

  3211.   *         - To get the channel number in decimal format:

  3212.   *           process the returned value with the helper macro

  3213.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3214.   * @note   On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs

  3215.   *         coming from GPIO pads (ADC_IN1..5).

  3216.   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n

  3217.   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n

  3218.   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n

  3219.   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel

  3220.   * @param  ADCx ADC instance

  3221.   * @param  Offsety This parameter can be one of the following values:

  3222.   *         @arg @ref LL_ADC_OFFSET_1

  3223.   *         @arg @ref LL_ADC_OFFSET_2

  3224.   *         @arg @ref LL_ADC_OFFSET_3

  3225.   *         @arg @ref LL_ADC_OFFSET_4

  3226.   * @retval Returned value can be one of the following values:

  3227.   *         @arg @ref LL_ADC_CHANNEL_0

  3228.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  3229.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  3230.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  3231.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  3232.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  3233.   *         @arg @ref LL_ADC_CHANNEL_6

  3234.   *         @arg @ref LL_ADC_CHANNEL_7

  3235.   *         @arg @ref LL_ADC_CHANNEL_8

  3236.   *         @arg @ref LL_ADC_CHANNEL_9

  3237.   *         @arg @ref LL_ADC_CHANNEL_10

  3238.   *         @arg @ref LL_ADC_CHANNEL_11

  3239.   *         @arg @ref LL_ADC_CHANNEL_12

  3240.   *         @arg @ref LL_ADC_CHANNEL_13

  3241.   *         @arg @ref LL_ADC_CHANNEL_14

  3242.   *         @arg @ref LL_ADC_CHANNEL_15

  3243.   *         @arg @ref LL_ADC_CHANNEL_16

  3244.   *         @arg @ref LL_ADC_CHANNEL_17

  3245.   *         @arg @ref LL_ADC_CHANNEL_18

  3246.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (4)

  3247.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)

  3248.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)

  3249.   *

  3250.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  3251.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n

  3252.   *         (4) For ADC channel read back from ADC register,

  3253.   *             comparison with internal channel parameter to be done

  3254.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  3255.   */

  3256. __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)

  3257. {

  3258.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  3259. 

  3260.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);

  3261. }

  3262. 

  3263. /**

  3264.   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

  3265.   *         Offset level (offset to be subtracted from the raw

  3266.   *         converted data).

  3267.   * @note   Caution: Offset format is dependent to ADC resolution:

  3268.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  3269.   *         are set to 0.

  3270.   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n

  3271.   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n

  3272.   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n

  3273.   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel

  3274.   * @param  ADCx ADC instance

  3275.   * @param  Offsety This parameter can be one of the following values:

  3276.   *         @arg @ref LL_ADC_OFFSET_1

  3277.   *         @arg @ref LL_ADC_OFFSET_2

  3278.   *         @arg @ref LL_ADC_OFFSET_3

  3279.   *         @arg @ref LL_ADC_OFFSET_4

  3280.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  3281.   */

  3282. __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)

  3283. {

  3284.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  3285. 

  3286.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);

  3287. }

  3288. 

  3289. /**

  3290.   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:

  3291.   *         force offset state disable or enable

  3292.   *         without modifying offset channel or offset value.

  3293.   * @note   This function should be needed only in case of offset to be

  3294.   *         enabled-disabled dynamically, and should not be needed in other cases:

  3295.   *         function LL_ADC_SetOffset() automatically enables the offset.

  3296.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3297.   *         ADC state:

  3298.   *         ADC must be disabled or enabled without conversion on going

  3299.   *         on either groups regular or injected.

  3300.   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n

  3301.   *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n

  3302.   *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n

  3303.   *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState

  3304.   * @param  ADCx ADC instance

  3305.   * @param  Offsety This parameter can be one of the following values:

  3306.   *         @arg @ref LL_ADC_OFFSET_1

  3307.   *         @arg @ref LL_ADC_OFFSET_2

  3308.   *         @arg @ref LL_ADC_OFFSET_3

  3309.   *         @arg @ref LL_ADC_OFFSET_4

  3310.   * @param  OffsetState This parameter can be one of the following values:

  3311.   *         @arg @ref LL_ADC_OFFSET_DISABLE

  3312.   *         @arg @ref LL_ADC_OFFSET_ENABLE

  3313.   * @retval None

  3314.   */

  3315. __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)

  3316. {

  3317.   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  3318. 

  3319.   MODIFY_REG(*preg,

  3320.              ADC_OFR1_OFFSET1_EN,

  3321.              OffsetState);

  3322. }

  3323. 

  3324. /**

  3325.   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

  3326.   *         offset state disabled or enabled.

  3327.   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n

  3328.   *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n

  3329.   *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n

  3330.   *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState

  3331.   * @param  ADCx ADC instance

  3332.   * @param  Offsety This parameter can be one of the following values:

  3333.   *         @arg @ref LL_ADC_OFFSET_1

  3334.   *         @arg @ref LL_ADC_OFFSET_2

  3335.   *         @arg @ref LL_ADC_OFFSET_3

  3336.   *         @arg @ref LL_ADC_OFFSET_4

  3337.   * @retval Returned value can be one of the following values:

  3338.   *         @arg @ref LL_ADC_OFFSET_DISABLE

  3339.   *         @arg @ref LL_ADC_OFFSET_ENABLE

  3340.   */

  3341. __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)

  3342. {

  3343.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  3344. 

  3345.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);

  3346. }

  3347. 

  3348. #endif

  3349. 

  3350. /**

  3351.   * @}

  3352.   */

  3353. 

  3354. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular

  3355.   * @{

  3356.   */

  3357. 

  3358. /**

  3359.   * @brief  Set ADC group regular conversion trigger source:

  3360.   *         internal (SW start) or from external peripheral (timer event,

  3361.   *         external interrupt line).

  3362.   * @note   On this STM32 serie, setting trigger source to external trigger

  3363.   *         also set trigger polarity to rising edge

  3364.   *         (default setting for compatibility with some ADC on other

  3365.   *         STM32 families having this setting set by HW default value).

  3366.   *         In case of need to modify trigger edge, use

  3367.   *         function @ref LL_ADC_REG_SetTriggerEdge().

  3368.   * @note   On devices STM32WB10xx, STM32WB15xx: ADC trigger frequency mode must be set

  3369.   *         in function of frequency of ADC group regular conversion trigger.

  3370.   *         Refer to description of function

  3371.   *         "LL_ADC_SetTriggerFrequencyMode()".

  3372.   * @note   Availability of parameters of trigger sources from timer

  3373.   *         depends on timers availability on the selected device.

  3374.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3375.   *         ADC state:

  3376.   *         ADC must be disabled or enabled without conversion on going

  3377.   *         on group regular.

  3378.   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n

  3379.   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource

  3380.   * @param  ADCx ADC instance

  3381.   * @param  TriggerSource This parameter can be one of the following values:

  3382.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  3383.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO  (1)

  3384.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

  3385.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1   (1)

  3386.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2   (1)

  3387.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3   (1)

  3388.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4   (2)

  3389.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  3390.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  3391.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3   (2)

  3392.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4   (2)

  3393.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  3394.   *

  3395.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  3396.   *         (2) On STM32WB serie, parameter available only devices: STM32WB10xx, STM32WB15xx.

  3397.   * @retval None

  3398.   */

  3399. __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  3400. {

  3401. #if defined (ADC_SUPPORT_2_5_MSPS)

  3402.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);

  3403. #else

  3404.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);

  3405. #endif

  3406. }

  3407. 

  3408. /**

  3409.   * @brief  Get ADC group regular conversion trigger source:

  3410.   *         internal (SW start) or from external peripheral (timer event,

  3411.   *         external interrupt line).

  3412.   * @note   To determine whether group regular trigger source is

  3413.   *         internal (SW start) or external, without detail

  3414.   *         of which peripheral is selected as external trigger,

  3415.   *         (equivalent to

  3416.   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")

  3417.   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.

  3418.   * @note   Availability of parameters of trigger sources from timer

  3419.   *         depends on timers availability on the selected device.

  3420.   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n

  3421.   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource

  3422.   * @param  ADCx ADC instance

  3423.   * @retval Returned value can be one of the following values:

  3424.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  3425.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO  (1)

  3426.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

  3427.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1   (1)

  3428.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2   (1)

  3429.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3   (1)

  3430.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4   (2)

  3431.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  3432.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  3433.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3   (2)

  3434.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4   (2)

  3435.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  3436.   *

  3437.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  3438.   *         (2) On STM32WB serie, parameter available only devices: STM32WB10xx, STM32WB15xx.

  3439.   */

  3440. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)

  3441. {

  3442. #if defined (ADC_SUPPORT_2_5_MSPS)

  3443.   __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);

  3444. 

  3445.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  3446.   /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}.                           */

  3447.   uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));

  3448. 

  3449.   /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL       */

  3450.   /* to match with triggers literals definition.                              */

  3451.   return ((TriggerSource

  3452.            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)

  3453.           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)

  3454.          );

  3455. #else

  3456.   __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);

  3457. 

  3458.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  3459.   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */

  3460.   uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));

  3461. 

  3462.   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */

  3463.   /* to match with triggers literals definition.                              */

  3464.   return ((TriggerSource

  3465.            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)

  3466.           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)

  3467.          );

  3468. #endif

  3469. }

  3470. 

  3471. /**

  3472.   * @brief  Get ADC group regular conversion trigger source internal (SW start)

  3473.   *         or external.

  3474.   * @note   In case of group regular trigger source set to external trigger,

  3475.   *         to determine which peripheral is selected as external trigger,

  3476.   *         use function @ref LL_ADC_REG_GetTriggerSource().

  3477.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart

  3478.   * @param  ADCx ADC instance

  3479.   * @retval Value "0" if trigger source external trigger

  3480.   *         Value "1" if trigger source SW start.

  3481.   */

  3482. __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  3483. {

  3484. #if defined (ADC_SUPPORT_2_5_MSPS)

  3485.   return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);

  3486. #else

  3487.   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);

  3488. #endif

  3489. }

  3490. 

  3491. /**

  3492.   * @brief  Set ADC group regular conversion trigger polarity.

  3493.   * @note   Applicable only for trigger source set to external trigger.

  3494.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3495.   *         ADC state:

  3496.   *         ADC must be disabled or enabled without conversion on going

  3497.   *         on group regular.

  3498.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge

  3499.   * @param  ADCx ADC instance

  3500.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  3501.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  3502.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  3503.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  3504.   * @retval None

  3505.   */

  3506. __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  3507. {

  3508. #if defined (ADC_SUPPORT_2_5_MSPS)

  3509.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);

  3510. #else

  3511.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);

  3512. #endif

  3513. }

  3514. 

  3515. /**

  3516.   * @brief  Get ADC group regular conversion trigger polarity.

  3517.   * @note   Applicable only for trigger source set to external trigger.

  3518.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge

  3519.   * @param  ADCx ADC instance

  3520.   * @retval Returned value can be one of the following values:

  3521.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  3522.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  3523.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  3524.   */

  3525. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)

  3526. {

  3527. #if defined (ADC_SUPPORT_2_5_MSPS)

  3528.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));

  3529. #else

  3530.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));

  3531. #endif

  3532. }

  3533. 

  3534. #if defined(ADC_SUPPORT_2_5_MSPS)

  3535. /**

  3536.   * @brief  Set ADC group regular sequencer configuration flexibility.

  3537.   * @note   On this STM32 serie, ADC group regular sequencer both modes

  3538.   *         "fully configurable" or "not fully configurable" are

  3539.   *         available:

  3540.   *         - sequencer configured to fully configurable:

  3541.   *           sequencer length and each rank

  3542.   *           affectation to a channel are configurable.

  3543.   *           Refer to description of function

  3544.   *           @ref LL_ADC_REG_SetSequencerLength().

  3545.   *         - sequencer configured to not fully configurable:

  3546.   *           sequencer length and each rank affectation to a channel

  3547.   *           are fixed by channel HW number.

  3548.   *           Refer to description of function

  3549.   *           @ref LL_ADC_REG_SetSequencerChannels().

  3550.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3551.   *         ADC state:

  3552.   *         ADC must be disabled or enabled without conversion on going

  3553.   *         on group regular.

  3554.   * @rmtoll CFGR     CHSELRMOD      LL_ADC_REG_SetSequencerConfigurable

  3555.   * @param  ADCx ADC instance

  3556.   * @param  Configurability This parameter can be one of the following values:

  3557.   *         @arg @ref LL_ADC_REG_SEQ_FIXED

  3558.   *         @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE

  3559.   * @retval None

  3560.   */

  3561. __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)

  3562. {

  3563.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);

  3564. }

  3565. 

  3566. /**

  3567.   * @brief  Get ADC group regular sequencer configuration flexibility.

  3568.   * @note   On this STM32 serie, ADC group regular sequencer both modes

  3569.   *         "fully configurable" or "not fully configurable" are

  3570.   *         available:

  3571.   *         - sequencer configured to fully configurable:

  3572.   *           sequencer length and each rank

  3573.   *           affectation to a channel are configurable.

  3574.   *           Refer to description of function

  3575.   *           @ref LL_ADC_REG_SetSequencerLength().

  3576.   *         - sequencer configured to not fully configurable:

  3577.   *           sequencer length and each rank affectation to a channel

  3578.   *           are fixed by channel HW number.

  3579.   *           Refer to description of function

  3580.   *           @ref LL_ADC_REG_SetSequencerChannels().

  3581.   * @rmtoll CFGR     CHSELRMOD      LL_ADC_REG_SetSequencerConfigurable

  3582.   * @param  ADCx ADC instance

  3583.   * @retval Returned value can be one of the following values:

  3584.   *         @arg @ref LL_ADC_REG_SEQ_FIXED

  3585.   *         @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE

  3586.   */

  3587. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)

  3588. {

  3589.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));

  3590. }

  3591. 

  3592. #endif

  3593. /**

  3594.   * @brief  Set ADC group regular sequencer length and scan direction.

  3595.   * @note   Description of ADC group regular sequencer features:

  3596.   *         - For devices with sequencer fully configurable

  3597.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  3598.   *           sequencer length and each rank affectation to a channel

  3599.   *           are configurable.

  3600.   *           This function performs configuration of:

  3601.   *           - Sequence length: Number of ranks in the scan sequence.

  3602.   *           - Sequence direction: Unless specified in parameters, sequencer

  3603.   *             scan direction is forward (from rank 1 to rank n).

  3604.   *           Sequencer ranks are selected using

  3605.   *           function "LL_ADC_REG_SetSequencerRanks()".

  3606.   *         - For devices with sequencer not fully configurable

  3607.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  3608.   *           sequencer length and each rank affectation to a channel

  3609.   *           are defined by channel number.

  3610.   *           This function performs configuration of:

  3611.   *           - Sequence length: Number of ranks in the scan sequence is

  3612.   *             defined by number of channels set in the sequence,

  3613.   *             rank of each channel is fixed by channel HW number.

  3614.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  3615.   *           - Sequence direction: Unless specified in parameters, sequencer

  3616.   *             scan direction is forward (from lowest channel number to

  3617.   *             highest channel number).

  3618.   *           Sequencer ranks are selected using

  3619.   *           function "LL_ADC_REG_SetSequencerChannels()".

  3620.   *           To set scan direction differently, refer to function

  3621.   *           "LL_ADC_REG_SetSequencerScanDirection()".

  3622.   * @note   On devices STM32WB10xx, STM32WB15xx: after calling functions

  3623.   *         @ref LL_ADC_REG_SetSequencerLength()

  3624.   *         or @ref LL_ADC_REG_SetSequencerRanks(),

  3625.   *         it is mandatory to wait for the assertion of CCRDY flag

  3626.   *         using "LL_ADC_IsActiveFlag_CCRDY()".

  3627.   *         Otherwise, performing some actions (configuration update,

  3628.   *         ADC conversion start, ... ) will be ignored.

  3629.   *         Refer to reference manual for more details.

  3630.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3631.   *         ADC conversion on only 1 channel.

  3632.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3633.   *         ADC state:

  3634.   *         ADC must be disabled or enabled without conversion on going

  3635.   *         on group regular.

  3636.   * @rmtoll CHSELR   SQ1            LL_ADC_REG_SetSequencerLength\n

  3637.   *         CHSELR   SQ2            LL_ADC_REG_SetSequencerLength\n

  3638.   *         CHSELR   SQ3            LL_ADC_REG_SetSequencerLength\n

  3639.   *         CHSELR   SQ4            LL_ADC_REG_SetSequencerLength\n

  3640.   *         CHSELR   SQ5            LL_ADC_REG_SetSequencerLength\n

  3641.   *         CHSELR   SQ6            LL_ADC_REG_SetSequencerLength\n

  3642.   *         CHSELR   SQ7            LL_ADC_REG_SetSequencerLength\n

  3643.   *         CHSELR   SQ8            LL_ADC_REG_SetSequencerLength

  3644.   * @param  ADCx ADC instance

  3645.   * @param  SequencerNbRanks This parameter can be one of the following values:

  3646.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  3647.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  3648.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  3649.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  3650.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  3651.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  3652.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  3653.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  3654.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (1)

  3655.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (1)

  3656.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (1)

  3657.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (1)

  3658.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (1)

  3659.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (1)

  3660.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (1)

  3661.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (1)

  3662.   *

  3663.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  3664.   * @retval None

  3665.   */

  3666. __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  3667. {

  3668. #if defined (ADC_SUPPORT_2_5_MSPS)

  3669.   SET_BIT(ADCx->CHSELR, SequencerNbRanks);

  3670. #else

  3671.   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);

  3672. #endif

  3673. }

  3674. 

  3675. /**

  3676.   * @brief  Get ADC group regular sequencer length and scan direction.

  3677.   * @note   Description of ADC group regular sequencer features:

  3678.   *         - For devices with sequencer fully configurable

  3679.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  3680.   *           sequencer length and each rank affectation to a channel

  3681.   *           are configurable.

  3682.   *           This function retrieves:

  3683.   *           - Sequence length: Number of ranks in the scan sequence.

  3684.   *           - Sequence direction: Unless specified in parameters, sequencer

  3685.   *             scan direction is forward (from rank 1 to rank n).

  3686.   *           Sequencer ranks are selected using

  3687.   *           function "LL_ADC_REG_SetSequencerRanks()".

  3688.   *         - For devices with sequencer not fully configurable

  3689.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  3690.   *           sequencer length and each rank affectation to a channel

  3691.   *           are defined by channel number.

  3692.   *           This function retrieves:

  3693.   *           - Sequence length: Number of ranks in the scan sequence is

  3694.   *             defined by number of channels set in the sequence,

  3695.   *             rank of each channel is fixed by channel HW number.

  3696.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  3697.   *           - Sequence direction: Unless specified in parameters, sequencer

  3698.   *             scan direction is forward (from lowest channel number to

  3699.   *             highest channel number).

  3700.   *           Sequencer ranks are selected using

  3701.   *           function "LL_ADC_REG_SetSequencerChannels()".

  3702.   *          To set scan direction differently, refer to function

  3703.   *          "LL_ADC_REG_SetSequencerScanDirection()".

  3704.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3705.   *         ADC conversion on only 1 channel.

  3706.   * @rmtoll CHSELR   SQ1            LL_ADC_REG_GetSequencerLength\n

  3707.   *         CHSELR   SQ2            LL_ADC_REG_GetSequencerLength\n

  3708.   *         CHSELR   SQ3            LL_ADC_REG_GetSequencerLength\n

  3709.   *         CHSELR   SQ4            LL_ADC_REG_GetSequencerLength\n

  3710.   *         CHSELR   SQ5            LL_ADC_REG_GetSequencerLength\n

  3711.   *         CHSELR   SQ6            LL_ADC_REG_GetSequencerLength\n

  3712.   *         CHSELR   SQ7            LL_ADC_REG_GetSequencerLength\n

  3713.   *         CHSELR   SQ8            LL_ADC_REG_GetSequencerLength

  3714.   * @param  ADCx ADC instance

  3715.   * @retval Returned value can be one of the following values:

  3716.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  3717.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  3718.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  3719.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  3720.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  3721.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  3722.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  3723.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  3724.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (1)

  3725.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (1)

  3726.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (1)

  3727.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (1)

  3728.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (1)

  3729.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (1)

  3730.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (1)

  3731.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (1)

  3732.   *

  3733.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  3734.   */

  3735. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)

  3736. {

  3737. #if defined (ADC_SUPPORT_2_5_MSPS)

  3738.   __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);

  3739.   uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;

  3740.   uint32_t RankIndex;

  3741. 

  3742.   /* Parse register for end of sequence identifier */

  3743.   for(RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex+=4U)

  3744.   {

  3745.     if((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex))

  3746.     {

  3747.       SequencerLength = (ADC_CHSELR_SQ2 << RankIndex);

  3748.       break;

  3749.     }

  3750.   }

  3751. 

  3752.   return SequencerLength;

  3753. #else

  3754.   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));

  3755. #endif

  3756. }

  3757. 

  3758. #if defined(ADC_SUPPORT_2_5_MSPS)

  3759. /**

  3760.   * @brief  Set ADC group regular sequencer scan direction.

  3761.   * @note   On this STM32 serie, parameter relevant only is sequencer is set

  3762.   *         to mode not fully configurable,

  3763.   *         refer to function @ref LL_ADC_REG_SetSequencerConfigurable().

  3764.   * @note   On some other STM32 families, this setting is not available and

  3765.   *         the default scan direction is forward.

  3766.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3767.   *         ADC state:

  3768.   *         ADC must be disabled or enabled without conversion on going

  3769.   *         on group regular.

  3770.   * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_SetSequencerScanDirection

  3771.   * @param  ADCx ADC instance

  3772.   * @param  ScanDirection This parameter can be one of the following values:

  3773.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD

  3774.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD

  3775.   * @retval None

  3776.   */

  3777. __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)

  3778. {

  3779.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);

  3780. }

  3781. 

  3782. /**

  3783.   * @brief  Get ADC group regular sequencer scan direction.

  3784.   * @note   On some other STM32 families, this setting is not available and

  3785.   *         the default scan direction is forward.

  3786.   * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_GetSequencerScanDirection

  3787.   * @param  ADCx ADC instance

  3788.   * @retval Returned value can be one of the following values:

  3789.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD

  3790.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD

  3791.   */

  3792. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)

  3793. {

  3794.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));

  3795. }

  3796. 

  3797. #endif

  3798. /**

  3799.   * @brief  Set ADC group regular sequencer discontinuous mode:

  3800.   *         sequence subdivided and scan conversions interrupted every selected

  3801.   *         number of ranks.

  3802.   * @note   It is not possible to enable both ADC group regular

  3803.   *         continuous mode and sequencer discontinuous mode.

  3804.   * @note   It is not possible to enable both ADC auto-injected mode

  3805.   *         and ADC group regular sequencer discontinuous mode.

  3806.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3807.   *         ADC state:

  3808.   *         ADC must be disabled or enabled without conversion on going

  3809.   *         on group regular.

  3810.   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n

  3811.   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont

  3812.   * @param  ADCx ADC instance

  3813.   * @param  SeqDiscont This parameter can be one of the following values:

  3814.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  3815.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  3816.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS (1)

  3817.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS (1)

  3818.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS (1)

  3819.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS (1)

  3820.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS (1)

  3821.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS (1)

  3822.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS (1)

  3823.   *

  3824.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  3825.   * @retval None

  3826.   */

  3827. __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  3828. {

  3829. #if defined (ADC_SUPPORT_2_5_MSPS)

  3830.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);

  3831. #else

  3832.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);

  3833. #endif

  3834. }

  3835. 

  3836. /**

  3837.   * @brief  Get ADC group regular sequencer discontinuous mode:

  3838.   *         sequence subdivided and scan conversions interrupted every selected

  3839.   *         number of ranks.

  3840.   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n

  3841.   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont

  3842.   * @param  ADCx ADC instance

  3843.   * @retval Returned value can be one of the following values:

  3844.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  3845.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  3846.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS (1)

  3847.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS (1)

  3848.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS (1)

  3849.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS (1)

  3850.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS (1)

  3851.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS (1)

  3852.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS (1)

  3853.   *

  3854.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  3855.   */

  3856. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)

  3857. {

  3858. #if defined (ADC_SUPPORT_2_5_MSPS)

  3859.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));

  3860. #else

  3861.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));

  3862. #endif

  3863. }

  3864. 

  3865. /**

  3866.   * @brief  Set ADC group regular sequence: channel on the selected

  3867.   *         scan sequence rank.

  3868.   * @note   This function performs configuration of:

  3869.   *         - Channels ordering into each rank of scan sequence:

  3870.   *           whatever channel can be placed into whatever rank.

  3871.   * @note   On this STM32 serie, ADC group regular sequencer is

  3872.   *         fully configurable: sequencer length and each rank

  3873.   *         affectation to a channel are configurable.

  3874.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  3875.   * @note   Depending on devices and packages, some channels may not be available.

  3876.   *         Refer to device datasheet for channels availability.

  3877.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  3878.   *         TempSensor, ...), measurement paths to internal channels must be

  3879.   *         enabled separately.

  3880.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  3881.   * @note   On devices STM32WB10xx, STM32WB15xx: after calling functions

  3882.   *         @ref LL_ADC_REG_SetSequencerLength()

  3883.   *         or @ref LL_ADC_REG_SetSequencerRanks(),

  3884.   *         it is mandatory to wait for the assertion of CCRDY flag

  3885.   *         using "LL_ADC_IsActiveFlag_CCRDY()".

  3886.   *         Otherwise, performing some actions (configuration update,

  3887.   *         ADC conversion start, ... ) will be ignored.

  3888.   *         Refer to reference manual for more details.

  3889.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3890.   *         ADC state:

  3891.   *         ADC must be disabled or enabled without conversion on going

  3892.   *         on group regular.

  3893.   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n

  3894.   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n

  3895.   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n

  3896.   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n

  3897.   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n

  3898.   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n

  3899.   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n

  3900.   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n

  3901.   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n

  3902.   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n

  3903.   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n

  3904.   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n

  3905.   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n

  3906.   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n

  3907.   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n

  3908.   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks

  3909.   * @param  ADCx ADC instance

  3910.   * @param  Rank This parameter can be one of the following values:

  3911.   *         @arg @ref LL_ADC_REG_RANK_1

  3912.   *         @arg @ref LL_ADC_REG_RANK_2

  3913.   *         @arg @ref LL_ADC_REG_RANK_3

  3914.   *         @arg @ref LL_ADC_REG_RANK_4

  3915.   *         @arg @ref LL_ADC_REG_RANK_5

  3916.   *         @arg @ref LL_ADC_REG_RANK_6

  3917.   *         @arg @ref LL_ADC_REG_RANK_7

  3918.   *         @arg @ref LL_ADC_REG_RANK_8

  3919.   *         @arg @ref LL_ADC_REG_RANK_9  (1)

  3920.   *         @arg @ref LL_ADC_REG_RANK_10 (1)

  3921.   *         @arg @ref LL_ADC_REG_RANK_11 (1)

  3922.   *         @arg @ref LL_ADC_REG_RANK_12 (1)

  3923.   *         @arg @ref LL_ADC_REG_RANK_13 (1)

  3924.   *         @arg @ref LL_ADC_REG_RANK_14 (1)

  3925.   *         @arg @ref LL_ADC_REG_RANK_15 (1)

  3926.   *         @arg @ref LL_ADC_REG_RANK_16 (1)

  3927.   *

  3928.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  3929.   * @param  Channel This parameter can be one of the following values:

  3930.   *         @arg @ref LL_ADC_CHANNEL_0

  3931.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  3932.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  3933.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  3934.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  3935.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  3936.   *         @arg @ref LL_ADC_CHANNEL_6

  3937.   *         @arg @ref LL_ADC_CHANNEL_7

  3938.   *         @arg @ref LL_ADC_CHANNEL_8

  3939.   *         @arg @ref LL_ADC_CHANNEL_9

  3940.   *         @arg @ref LL_ADC_CHANNEL_10

  3941.   *         @arg @ref LL_ADC_CHANNEL_11

  3942.   *         @arg @ref LL_ADC_CHANNEL_12

  3943.   *         @arg @ref LL_ADC_CHANNEL_13

  3944.   *         @arg @ref LL_ADC_CHANNEL_14

  3945.   *         @arg @ref LL_ADC_CHANNEL_15

  3946.   *         @arg @ref LL_ADC_CHANNEL_16

  3947.   *         @arg @ref LL_ADC_CHANNEL_17

  3948.   *         @arg @ref LL_ADC_CHANNEL_18

  3949.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  3950.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  3951.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  3952.   *

  3953.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  3954.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  3955.   * @retval None

  3956.   */

  3957. __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  3958. {

  3959. #if defined (ADC_SUPPORT_2_5_MSPS)

  3960.   /* Set bits with content of parameter "Channel" with bits position          */

  3961.   /* in register depending on parameter "Rank".                               */

  3962.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  3963.   /* other bits reserved for other purpose.                                   */

  3964.   MODIFY_REG(ADCx->CHSELR,

  3965.              ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),

  3966.              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));

  3967. #else

  3968.   /* Set bits with content of parameter "Channel" with bits position          */

  3969.   /* in register and register position depending on parameter "Rank".         */

  3970.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  3971.   /* other bits reserved for other purpose.                                   */

  3972.   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));

  3973. 

  3974.   MODIFY_REG(*preg,

  3975.              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),

  3976.              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));

  3977. #endif

  3978. }

  3979. 

  3980. /**

  3981.   * @brief  Get ADC group regular sequence: channel on the selected

  3982.   *         scan sequence rank.

  3983.   * @note   On this STM32 serie, ADC group regular sequencer is

  3984.   *         fully configurable: sequencer length and each rank

  3985.   *         affectation to a channel are configurable.

  3986.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  3987.   * @note   Depending on devices and packages, some channels may not be available.

  3988.   *         Refer to device datasheet for channels availability.

  3989.   * @note   Usage of the returned channel number:

  3990.   *         - To reinject this channel into another function LL_ADC_xxx:

  3991.   *           the returned channel number is only partly formatted on definition

  3992.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  3993.   *           with parts of literals LL_ADC_CHANNEL_x or using

  3994.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3995.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3996.   *           as parameter for another function.

  3997.   *         - To get the channel number in decimal format:

  3998.   *           process the returned value with the helper macro

  3999.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4000.   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n

  4001.   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n

  4002.   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n

  4003.   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n

  4004.   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n

  4005.   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n

  4006.   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n

  4007.   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n

  4008.   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n

  4009.   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n

  4010.   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n

  4011.   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n

  4012.   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n

  4013.   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n

  4014.   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n

  4015.   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks

  4016.   * @param  ADCx ADC instance

  4017.   * @param  Rank This parameter can be one of the following values:

  4018.   *         @arg @ref LL_ADC_REG_RANK_1

  4019.   *         @arg @ref LL_ADC_REG_RANK_2

  4020.   *         @arg @ref LL_ADC_REG_RANK_3

  4021.   *         @arg @ref LL_ADC_REG_RANK_4

  4022.   *         @arg @ref LL_ADC_REG_RANK_5

  4023.   *         @arg @ref LL_ADC_REG_RANK_6

  4024.   *         @arg @ref LL_ADC_REG_RANK_7

  4025.   *         @arg @ref LL_ADC_REG_RANK_8

  4026.   *         @arg @ref LL_ADC_REG_RANK_9  (1)

  4027.   *         @arg @ref LL_ADC_REG_RANK_10 (1)

  4028.   *         @arg @ref LL_ADC_REG_RANK_11 (1)

  4029.   *         @arg @ref LL_ADC_REG_RANK_12 (1)

  4030.   *         @arg @ref LL_ADC_REG_RANK_13 (1)

  4031.   *         @arg @ref LL_ADC_REG_RANK_14 (1)

  4032.   *         @arg @ref LL_ADC_REG_RANK_15 (1)

  4033.   *         @arg @ref LL_ADC_REG_RANK_16 (1)

  4034.   *

  4035.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  4036.   * @retval Returned value can be one of the following values:

  4037.   *         @arg @ref LL_ADC_CHANNEL_0

  4038.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  4039.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  4040.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  4041.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  4042.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  4043.   *         @arg @ref LL_ADC_CHANNEL_6

  4044.   *         @arg @ref LL_ADC_CHANNEL_7

  4045.   *         @arg @ref LL_ADC_CHANNEL_8

  4046.   *         @arg @ref LL_ADC_CHANNEL_9

  4047.   *         @arg @ref LL_ADC_CHANNEL_10

  4048.   *         @arg @ref LL_ADC_CHANNEL_11

  4049.   *         @arg @ref LL_ADC_CHANNEL_12

  4050.   *         @arg @ref LL_ADC_CHANNEL_13

  4051.   *         @arg @ref LL_ADC_CHANNEL_14

  4052.   *         @arg @ref LL_ADC_CHANNEL_15

  4053.   *         @arg @ref LL_ADC_CHANNEL_16

  4054.   *         @arg @ref LL_ADC_CHANNEL_17

  4055.   *         @arg @ref LL_ADC_CHANNEL_18

  4056.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (4)

  4057.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)

  4058.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)

  4059.   *

  4060.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  4061.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n

  4062.   *         (4) For ADC channel read back from ADC register,

  4063.   *             comparison with internal channel parameter to be done

  4064.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  4065.   */

  4066. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  4067. {

  4068. #if defined (ADC_SUPPORT_2_5_MSPS)

  4069.   return (uint32_t) ((READ_BIT(ADCx->CHSELR,

  4070.                                ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))

  4071.                       >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)

  4072.                      ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)

  4073.                     );

  4074. #else

  4075.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));

  4076. 

  4077.   return (uint32_t)((READ_BIT(*preg,

  4078.                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))

  4079.                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

  4080.                    );

  4081. #endif

  4082. }

  4083. 

  4084. #if defined(ADC_SUPPORT_2_5_MSPS)

  4085. /**

  4086.   * @brief  Set ADC group regular sequence: channel on rank corresponding to

  4087.   *         channel number.

  4088.   * @note   This function performs:

  4089.   *         - Channels ordering into each rank of scan sequence:

  4090.   *           rank of each channel is fixed by channel HW number

  4091.   *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  4092.   *         - Set channels selected by overwriting the current sequencer

  4093.   *           configuration.

  4094.   * @note   On this STM32 serie, ADC group regular sequencer both modes

  4095.   *         "fully configurable" or "not fully configurable"

  4096.   *         are available, they can be chosen using

  4097.   *         function @ref LL_ADC_REG_SetSequencerConfigurable().

  4098.   *         This function can be used with setting "not fully configurable".

  4099.   *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()

  4100.   *         and @ref LL_ADC_REG_SetSequencerLength().

  4101.   * @note   Depending on devices and packages, some channels may not be available.

  4102.   *         Refer to device datasheet for channels availability.

  4103.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  4104.   *         TempSensor, ...), measurement paths to internal channels must be

  4105.   *         enabled separately.

  4106.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  4107.   * @note   On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs

  4108.   *         coming from GPIO pads (ADC_IN1..5).

  4109.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4110.   *         ADC state:

  4111.   *         ADC must be disabled or enabled without conversion on going

  4112.   *         on group regular.

  4113.   * @note   One or several values can be selected.

  4114.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  4115.   * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChannels\n

  4116.   *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChannels\n

  4117.   *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChannels\n

  4118.   *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChannels\n

  4119.   *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChannels\n

  4120.   *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChannels\n

  4121.   *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChannels\n

  4122.   *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChannels\n

  4123.   *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChannels\n

  4124.   *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChannels\n

  4125.   *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChannels\n

  4126.   *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChannels\n

  4127.   *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChannels\n

  4128.   *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChannels\n

  4129.   *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChannels\n

  4130.   *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChannels\n

  4131.   *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChannels\n

  4132.   *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChannels\n

  4133.   *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChannels

  4134.   * @param  ADCx ADC instance

  4135.   * @param  Channel This parameter can be a combination of the following values:

  4136.   *         @arg @ref LL_ADC_CHANNEL_0

  4137.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  4138.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  4139.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  4140.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  4141.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  4142.   *         @arg @ref LL_ADC_CHANNEL_6

  4143.   *         @arg @ref LL_ADC_CHANNEL_7

  4144.   *         @arg @ref LL_ADC_CHANNEL_8

  4145.   *         @arg @ref LL_ADC_CHANNEL_9

  4146.   *         @arg @ref LL_ADC_CHANNEL_10

  4147.   *         @arg @ref LL_ADC_CHANNEL_11

  4148.   *         @arg @ref LL_ADC_CHANNEL_12

  4149.   *         @arg @ref LL_ADC_CHANNEL_13

  4150.   *         @arg @ref LL_ADC_CHANNEL_14

  4151.   *         @arg @ref LL_ADC_CHANNEL_15

  4152.   *         @arg @ref LL_ADC_CHANNEL_16

  4153.   *         @arg @ref LL_ADC_CHANNEL_17

  4154.   *         @arg @ref LL_ADC_CHANNEL_18

  4155.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  4156.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  4157.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  4158.   *

  4159.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  4160.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  4161.   * @retval None

  4162.   */

  4163. __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)

  4164. {

  4165.   /* Parameter "Channel" is used with masks because containing                */

  4166.   /* other bits reserved for other purpose.                                   */

  4167.   WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));

  4168. }

  4169. 

  4170. /**

  4171.   * @brief  Add channel to ADC group regular sequence: channel on rank corresponding to

  4172.   *         channel number.

  4173.   * @note   This function performs:

  4174.   *         - Channels ordering into each rank of scan sequence:

  4175.   *           rank of each channel is fixed by channel HW number

  4176.   *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  4177.   *         - Set channels selected by adding them to the current sequencer

  4178.   *           configuration.

  4179.   * @note   On this STM32 serie, ADC group regular sequencer both modes

  4180.   *         "fully configurable" or "not fully configurable"

  4181.   *         are available, they can be chosen using

  4182.   *         function @ref LL_ADC_REG_SetSequencerConfigurable().

  4183.   *         This function can be used with setting "not fully configurable".

  4184.   *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()

  4185.   *         and @ref LL_ADC_REG_SetSequencerLength().

  4186.   * @note   Depending on devices and packages, some channels may not be available.

  4187.   *         Refer to device datasheet for channels availability.

  4188.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  4189.   *         TempSensor, ...), measurement paths to internal channels must be

  4190.   *         enabled separately.

  4191.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  4192.   * @note   On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs

  4193.   *         coming from GPIO pads (ADC_IN1..5).

  4194.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4195.   *         ADC state:

  4196.   *         ADC must be disabled or enabled without conversion on going

  4197.   *         on group regular.

  4198.   * @note   One or several values can be selected.

  4199.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  4200.   * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChAdd\n

  4201.   *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChAdd\n

  4202.   *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChAdd\n

  4203.   *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChAdd\n

  4204.   *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChAdd\n

  4205.   *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChAdd\n

  4206.   *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChAdd\n

  4207.   *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChAdd\n

  4208.   *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChAdd\n

  4209.   *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChAdd\n

  4210.   *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChAdd\n

  4211.   *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChAdd\n

  4212.   *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChAdd\n

  4213.   *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChAdd\n

  4214.   *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChAdd\n

  4215.   *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChAdd\n

  4216.   *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChAdd\n

  4217.   *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChAdd\n

  4218.   *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChAdd

  4219.   * @param  ADCx ADC instance

  4220.   * @param  Channel This parameter can be a combination of the following values:

  4221.   *         @arg @ref LL_ADC_CHANNEL_0

  4222.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  4223.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  4224.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  4225.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  4226.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  4227.   *         @arg @ref LL_ADC_CHANNEL_6

  4228.   *         @arg @ref LL_ADC_CHANNEL_7

  4229.   *         @arg @ref LL_ADC_CHANNEL_8

  4230.   *         @arg @ref LL_ADC_CHANNEL_9

  4231.   *         @arg @ref LL_ADC_CHANNEL_10

  4232.   *         @arg @ref LL_ADC_CHANNEL_11

  4233.   *         @arg @ref LL_ADC_CHANNEL_12

  4234.   *         @arg @ref LL_ADC_CHANNEL_13

  4235.   *         @arg @ref LL_ADC_CHANNEL_14

  4236.   *         @arg @ref LL_ADC_CHANNEL_15

  4237.   *         @arg @ref LL_ADC_CHANNEL_16

  4238.   *         @arg @ref LL_ADC_CHANNEL_17

  4239.   *         @arg @ref LL_ADC_CHANNEL_18

  4240.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  4241.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  4242.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  4243.   *

  4244.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  4245.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  4246.   * @retval None

  4247.   */

  4248. __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)

  4249. {

  4250.   /* Parameter "Channel" is used with masks because containing                */

  4251.   /* other bits reserved for other purpose.                                   */

  4252.   SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));

  4253. }

  4254. 

  4255. /**

  4256.   * @brief  Remove channel to ADC group regular sequence: channel on rank corresponding to

  4257.   *         channel number.

  4258.   * @note   This function performs:

  4259.   *         - Channels ordering into each rank of scan sequence:

  4260.   *           rank of each channel is fixed by channel HW number

  4261.   *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  4262.   *         - Set channels selected by removing them to the current sequencer

  4263.   *           configuration.

  4264.   * @note   On this STM32 serie, ADC group regular sequencer both modes

  4265.   *         "fully configurable" or "not fully configurable"

  4266.   *         are available, they can be chosen using

  4267.   *         function @ref LL_ADC_REG_SetSequencerConfigurable().

  4268.   *         This function can be used with setting "not fully configurable".

  4269.   *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()

  4270.   *         and @ref LL_ADC_REG_SetSequencerLength().

  4271.   * @note   Depending on devices and packages, some channels may not be available.

  4272.   *         Refer to device datasheet for channels availability.

  4273.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  4274.   *         TempSensor, ...), measurement paths to internal channels must be

  4275.   *         enabled separately.

  4276.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  4277.   * @note   On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs

  4278.   *         coming from GPIO pads (ADC_IN1..5).

  4279.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4280.   *         ADC state:

  4281.   *         ADC must be disabled or enabled without conversion on going

  4282.   *         on group regular.

  4283.   * @note   One or several values can be selected.

  4284.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  4285.   * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChRem\n

  4286.   *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChRem\n

  4287.   *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChRem\n

  4288.   *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChRem\n

  4289.   *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChRem\n

  4290.   *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChRem\n

  4291.   *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChRem\n

  4292.   *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChRem\n

  4293.   *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChRem\n

  4294.   *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChRem\n

  4295.   *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChRem\n

  4296.   *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChRem\n

  4297.   *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChRem\n

  4298.   *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChRem\n

  4299.   *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChRem\n

  4300.   *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChRem\n

  4301.   *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChRem\n

  4302.   *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChRem\n

  4303.   *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChRem

  4304.   * @param  ADCx ADC instance

  4305.   * @param  Channel This parameter can be a combination of the following values:

  4306.   *         @arg @ref LL_ADC_CHANNEL_0

  4307.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  4308.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  4309.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  4310.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  4311.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  4312.   *         @arg @ref LL_ADC_CHANNEL_6

  4313.   *         @arg @ref LL_ADC_CHANNEL_7

  4314.   *         @arg @ref LL_ADC_CHANNEL_8

  4315.   *         @arg @ref LL_ADC_CHANNEL_9

  4316.   *         @arg @ref LL_ADC_CHANNEL_10

  4317.   *         @arg @ref LL_ADC_CHANNEL_11

  4318.   *         @arg @ref LL_ADC_CHANNEL_12

  4319.   *         @arg @ref LL_ADC_CHANNEL_13

  4320.   *         @arg @ref LL_ADC_CHANNEL_14

  4321.   *         @arg @ref LL_ADC_CHANNEL_15

  4322.   *         @arg @ref LL_ADC_CHANNEL_16

  4323.   *         @arg @ref LL_ADC_CHANNEL_17

  4324.   *         @arg @ref LL_ADC_CHANNEL_18

  4325.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  4326.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  4327.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  4328.   *

  4329.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  4330.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  4331.   * @retval None

  4332.   */

  4333. __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)

  4334. {

  4335.   /* Parameter "Channel" is used with masks because containing                */

  4336.   /* other bits reserved for other purpose.                                   */

  4337.   CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));

  4338. }

  4339. 

  4340. /**

  4341.   * @brief  Get ADC group regular sequence: channel on rank corresponding to

  4342.   *         channel number.

  4343.   * @note   This function performs:

  4344.   *         - Channels order reading into each rank of scan sequence:

  4345.   *           rank of each channel is fixed by channel HW number

  4346.   *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  4347.   * @note   On this STM32 serie, ADC group regular sequencer both modes

  4348.   *         "fully configurable" or "not fully configurable"

  4349.   *         are available, they can be chosen using

  4350.   *         function @ref LL_ADC_REG_SetSequencerConfigurable().

  4351.   *         This function can be used with setting "not fully configurable".

  4352.   *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()

  4353.   *         and @ref LL_ADC_REG_SetSequencerLength().

  4354.   * @note   Depending on devices and packages, some channels may not be available.

  4355.   *         Refer to device datasheet for channels availability.

  4356.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  4357.   *         TempSensor, ...), measurement paths to internal channels must be

  4358.   *         enabled separately.

  4359.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  4360.   * @note   On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs

  4361.   *         coming from GPIO pads (ADC_IN1..5).

  4362. */

  4363. //TBC

  4364. /*

  4365.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4366.   *         ADC state:

  4367.   *         ADC must be disabled or enabled without conversion on going

  4368.   *         on group regular.

  4369.   * @note   One or several values can be retrieved.

  4370.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  4371.   * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_GetSequencerChannels\n

  4372.   *         CHSELR   CHSEL1         LL_ADC_REG_GetSequencerChannels\n

  4373.   *         CHSELR   CHSEL2         LL_ADC_REG_GetSequencerChannels\n

  4374.   *         CHSELR   CHSEL3         LL_ADC_REG_GetSequencerChannels\n

  4375.   *         CHSELR   CHSEL4         LL_ADC_REG_GetSequencerChannels\n

  4376.   *         CHSELR   CHSEL5         LL_ADC_REG_GetSequencerChannels\n

  4377.   *         CHSELR   CHSEL6         LL_ADC_REG_GetSequencerChannels\n

  4378.   *         CHSELR   CHSEL7         LL_ADC_REG_GetSequencerChannels\n

  4379.   *         CHSELR   CHSEL8         LL_ADC_REG_GetSequencerChannels\n

  4380.   *         CHSELR   CHSEL9         LL_ADC_REG_GetSequencerChannels\n

  4381.   *         CHSELR   CHSEL10        LL_ADC_REG_GetSequencerChannels\n

  4382.   *         CHSELR   CHSEL11        LL_ADC_REG_GetSequencerChannels\n

  4383.   *         CHSELR   CHSEL12        LL_ADC_REG_GetSequencerChannels\n

  4384.   *         CHSELR   CHSEL13        LL_ADC_REG_GetSequencerChannels\n

  4385.   *         CHSELR   CHSEL14        LL_ADC_REG_GetSequencerChannels\n

  4386.   *         CHSELR   CHSEL15        LL_ADC_REG_GetSequencerChannels\n

  4387.   *         CHSELR   CHSEL16        LL_ADC_REG_GetSequencerChannels\n

  4388.   *         CHSELR   CHSEL17        LL_ADC_REG_GetSequencerChannels\n

  4389.   *         CHSELR   CHSEL18        LL_ADC_REG_GetSequencerChannels

  4390.   * @param  ADCx ADC instance

  4391.   * @retval Returned value can be a combination of the following values:

  4392.   *         @arg @ref LL_ADC_CHANNEL_0

  4393.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  4394.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  4395.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  4396.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  4397.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  4398.   *         @arg @ref LL_ADC_CHANNEL_6

  4399.   *         @arg @ref LL_ADC_CHANNEL_7

  4400.   *         @arg @ref LL_ADC_CHANNEL_8

  4401.   *         @arg @ref LL_ADC_CHANNEL_9

  4402.   *         @arg @ref LL_ADC_CHANNEL_10

  4403.   *         @arg @ref LL_ADC_CHANNEL_11

  4404.   *         @arg @ref LL_ADC_CHANNEL_12

  4405.   *         @arg @ref LL_ADC_CHANNEL_13

  4406.   *         @arg @ref LL_ADC_CHANNEL_14

  4407.   *         @arg @ref LL_ADC_CHANNEL_15

  4408.   *         @arg @ref LL_ADC_CHANNEL_16

  4409.   *         @arg @ref LL_ADC_CHANNEL_17

  4410.   *         @arg @ref LL_ADC_CHANNEL_18

  4411.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  4412.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  4413.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  4414.   *

  4415.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  4416.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  4417.   */

  4418. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)

  4419. {

  4420.   uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);

  4421. 

  4422.   return (   (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)

  4423.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)

  4424.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)

  4425.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)

  4426.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)

  4427.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)

  4428.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)

  4429.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)

  4430.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)

  4431.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)

  4432.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)

  4433.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)

  4434.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)

  4435.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)

  4436.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)

  4437.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)

  4438.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)

  4439.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)

  4440.            | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)

  4441.          );

  4442. }

  4443. #endif

  4444. /**

  4445.   * @brief  Set ADC continuous conversion mode on ADC group regular.

  4446.   * @note   Description of ADC continuous conversion mode:

  4447.   *         - single mode: one conversion per trigger

  4448.   *         - continuous mode: after the first trigger, following

  4449.   *           conversions launched successively automatically.

  4450.   * @note   It is not possible to enable both ADC group regular

  4451.   *         continuous mode and sequencer discontinuous mode.

  4452.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4453.   *         ADC state:

  4454.   *         ADC must be disabled or enabled without conversion on going

  4455.   *         on group regular.

  4456.   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode

  4457.   * @param  ADCx ADC instance

  4458.   * @param  Continuous This parameter can be one of the following values:

  4459.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  4460.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  4461.   * @retval None

  4462.   */

  4463. __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)

  4464. {

  4465. #if defined (ADC_SUPPORT_2_5_MSPS)

  4466.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);

  4467. #else

  4468.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);

  4469. #endif

  4470. }

  4471. 

  4472. /**

  4473.   * @brief  Get ADC continuous conversion mode on ADC group regular.

  4474.   * @note   Description of ADC continuous conversion mode:

  4475.   *         - single mode: one conversion per trigger

  4476.   *         - continuous mode: after the first trigger, following

  4477.   *           conversions launched successively automatically.

  4478.   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode

  4479.   * @param  ADCx ADC instance

  4480.   * @retval Returned value can be one of the following values:

  4481.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  4482.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  4483.   */

  4484. __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)

  4485. {

  4486. #if defined (ADC_SUPPORT_2_5_MSPS)

  4487.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));

  4488. #else

  4489.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));

  4490. #endif

  4491. }

  4492. 

  4493. /**

  4494.   * @brief  Set ADC group regular conversion data transfer: no transfer or

  4495.   *         transfer by DMA, and DMA requests mode.

  4496.   * @note   If transfer by DMA selected, specifies the DMA requests

  4497.   *         mode:

  4498.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  4499.   *           when number of DMA data transfers (number of

  4500.   *           ADC conversions) is reached.

  4501.   *           This ADC mode is intended to be used with DMA mode non-circular.

  4502.   *         - Unlimited mode: DMA transfer requests are unlimited,

  4503.   *           whatever number of DMA data transfers (number of

  4504.   *           ADC conversions).

  4505.   *           This ADC mode is intended to be used with DMA mode circular.

  4506.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  4507.   *         mode non-circular:

  4508.   *         when DMA transfers size will be reached, DMA will stop transfers of

  4509.   *         ADC conversions data ADC will raise an overrun error

  4510.   *        (overrun flag and interruption if enabled).

  4511.   * @note   To configure DMA source address (peripheral address),

  4512.   *         use function @ref LL_ADC_DMA_GetRegAddr().

  4513.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4514.   *         ADC state:

  4515.   *         ADC must be disabled or enabled without conversion on going

  4516.   *         on either groups regular or injected.

  4517.   * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n

  4518.   *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer

  4519.   * @param  ADCx ADC instance

  4520.   * @param  DMATransfer This parameter can be one of the following values:

  4521.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE

  4522.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  4523.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  4524.   * @retval None

  4525.   */

  4526. __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)

  4527. {

  4528. #if defined (ADC_SUPPORT_2_5_MSPS)

  4529.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);

  4530. #else

  4531.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);

  4532. #endif

  4533. }

  4534. 

  4535. /**

  4536.   * @brief  Get ADC group regular conversion data transfer: no transfer or

  4537.   *         transfer by DMA, and DMA requests mode.

  4538.   * @note   If transfer by DMA selected, specifies the DMA requests

  4539.   *         mode:

  4540.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  4541.   *           when number of DMA data transfers (number of

  4542.   *           ADC conversions) is reached.

  4543.   *           This ADC mode is intended to be used with DMA mode non-circular.

  4544.   *         - Unlimited mode: DMA transfer requests are unlimited,

  4545.   *           whatever number of DMA data transfers (number of

  4546.   *           ADC conversions).

  4547.   *           This ADC mode is intended to be used with DMA mode circular.

  4548.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  4549.   *         mode non-circular:

  4550.   *         when DMA transfers size will be reached, DMA will stop transfers of

  4551.   *         ADC conversions data ADC will raise an overrun error

  4552.   *         (overrun flag and interruption if enabled).

  4553.   * @note   To configure DMA source address (peripheral address),

  4554.   *         use function @ref LL_ADC_DMA_GetRegAddr().

  4555.   * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n

  4556.   *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer

  4557.   * @param  ADCx ADC instance

  4558.   * @retval Returned value can be one of the following values:

  4559.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE

  4560.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  4561.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  4562.   */

  4563. __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)

  4564. {

  4565. #if defined (ADC_SUPPORT_2_5_MSPS)

  4566.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));

  4567. #else

  4568.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));

  4569. #endif

  4570. }

  4571. 

  4572. 

  4573. /**

  4574.   * @brief  Set ADC group regular behavior in case of overrun:

  4575.   *         data preserved or overwritten.

  4576.   * @note   Compatibility with devices without feature overrun:

  4577.   *         other devices without this feature have a behavior

  4578.   *         equivalent to data overwritten.

  4579.   *         The default setting of overrun is data preserved.

  4580.   *         Therefore, for compatibility with all devices, parameter

  4581.   *         overrun should be set to data overwritten.

  4582.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4583.   *         ADC state:

  4584.   *         ADC must be disabled or enabled without conversion on going

  4585.   *         on group regular.

  4586.   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun

  4587.   * @param  ADCx ADC instance

  4588.   * @param  Overrun This parameter can be one of the following values:

  4589.   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED

  4590.   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN

  4591.   * @retval None

  4592.   */

  4593. __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)

  4594. {

  4595. #if defined (ADC_SUPPORT_2_5_MSPS)

  4596.   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);

  4597. #else

  4598.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);

  4599. #endif

  4600. }

  4601. 

  4602. /**

  4603.   * @brief  Get ADC group regular behavior in case of overrun:

  4604.   *         data preserved or overwritten.

  4605.   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun

  4606.   * @param  ADCx ADC instance

  4607.   * @retval Returned value can be one of the following values:

  4608.   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED

  4609.   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN

  4610.   */

  4611. __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)

  4612. {

  4613. #if defined (ADC_SUPPORT_2_5_MSPS)

  4614.   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));

  4615. #else

  4616.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));

  4617. #endif

  4618. }

  4619. 

  4620. /**

  4621.   * @}

  4622.   */

  4623. 

  4624. #if defined (ADC_SUPPORT_2_5_MSPS)

  4625. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  4626. #else

  4627. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected

  4628.   * @{

  4629.   */

  4630. 

  4631. /**

  4632.   * @brief  Set ADC group injected conversion trigger source:

  4633.   *         internal (SW start) or from external peripheral (timer event,

  4634.   *         external interrupt line).

  4635.   * @note   On this STM32 serie, setting trigger source to external trigger

  4636.   *         also set trigger polarity to rising edge

  4637.   *         (default setting for compatibility with some ADC on other

  4638.   *         STM32 families having this setting set by HW default value).

  4639.   *         In case of need to modify trigger edge, use

  4640.   *         function @ref LL_ADC_INJ_SetTriggerEdge().

  4641.   * @note   Availability of parameters of trigger sources from timer

  4642.   *         depends on timers availability on the selected device.

  4643.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4644.   *         ADC state:

  4645.   *         ADC must not be disabled. Can be enabled with or without conversion

  4646.   *         on going on either groups regular or injected.

  4647.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n

  4648.   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource

  4649.   * @param  ADCx ADC instance

  4650.   * @param  TriggerSource This parameter can be one of the following values:

  4651.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  4652.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  4653.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  4654.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  4655.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  4656.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  4657.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  4658.   * @retval None

  4659.   */

  4660. __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  4661. {

  4662.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);

  4663. }

  4664. 

  4665. /**

  4666.   * @brief  Get ADC group injected conversion trigger source:

  4667.   *         internal (SW start) or from external peripheral (timer event,

  4668.   *         external interrupt line).

  4669.   * @note   To determine whether group injected trigger source is

  4670.   *         internal (SW start) or external, without detail

  4671.   *         of which peripheral is selected as external trigger,

  4672.   *         (equivalent to

  4673.   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")

  4674.   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.

  4675.   * @note   Availability of parameters of trigger sources from timer

  4676.   *         depends on timers availability on the selected device.

  4677.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n

  4678.   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource

  4679.   * @param  ADCx ADC instance

  4680.   * @retval Returned value can be one of the following values:

  4681.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  4682.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  4683.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  4684.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  4685.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  4686.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  4687.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  4688.   */

  4689. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)

  4690. {

  4691.   __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);

  4692. 

  4693.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  4694.   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */

  4695.   uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));

  4696. 

  4697.   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */

  4698.   /* to match with triggers literals definition.                              */

  4699.   return ((TriggerSource

  4700.            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)

  4701.           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)

  4702.          );

  4703. }

  4704. 

  4705. /**

  4706.   * @brief  Get ADC group injected conversion trigger source internal (SW start)

  4707.             or external

  4708.   * @note   In case of group injected trigger source set to external trigger,

  4709.   *         to determine which peripheral is selected as external trigger,

  4710.   *         use function @ref LL_ADC_INJ_GetTriggerSource.

  4711.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart

  4712.   * @param  ADCx ADC instance

  4713.   * @retval Value "0" if trigger source external trigger

  4714.   *         Value "1" if trigger source SW start.

  4715.   */

  4716. __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  4717. {

  4718.   return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);

  4719. }

  4720. 

  4721. /**

  4722.   * @brief  Set ADC group injected conversion trigger polarity.

  4723.   *         Applicable only for trigger source set to external trigger.

  4724.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4725.   *         ADC state:

  4726.   *         ADC must not be disabled. Can be enabled with or without conversion

  4727.   *         on going on either groups regular or injected.

  4728.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge

  4729.   * @param  ADCx ADC instance

  4730.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  4731.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  4732.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  4733.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  4734.   * @retval None

  4735.   */

  4736. __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  4737. {

  4738.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);

  4739. }

  4740. 

  4741. /**

  4742.   * @brief  Get ADC group injected conversion trigger polarity.

  4743.   *         Applicable only for trigger source set to external trigger.

  4744.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge

  4745.   * @param  ADCx ADC instance

  4746.   * @retval Returned value can be one of the following values:

  4747.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  4748.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  4749.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  4750.   */

  4751. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)

  4752. {

  4753.   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));

  4754. }

  4755. 

  4756. /**

  4757.   * @brief  Set ADC group injected sequencer length and scan direction.

  4758.   * @note   This function performs configuration of:

  4759.   *         - Sequence length: Number of ranks in the scan sequence.

  4760.   *         - Sequence direction: Unless specified in parameters, sequencer

  4761.   *           scan direction is forward (from rank 1 to rank n).

  4762.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  4763.   *         ADC conversion on only 1 channel.

  4764.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4765.   *         ADC state:

  4766.   *         ADC must not be disabled. Can be enabled with or without conversion

  4767.   *         on going on either groups regular or injected.

  4768.   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength

  4769.   * @param  ADCx ADC instance

  4770.   * @param  SequencerNbRanks This parameter can be one of the following values:

  4771.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  4772.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  4773.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  4774.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  4775.   * @retval None

  4776.   */

  4777. __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  4778. {

  4779.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);

  4780. }

  4781. 

  4782. /**

  4783.   * @brief  Get ADC group injected sequencer length and scan direction.

  4784.   * @note   This function retrieves:

  4785.   *         - Sequence length: Number of ranks in the scan sequence.

  4786.   *         - Sequence direction: Unless specified in parameters, sequencer

  4787.   *           scan direction is forward (from rank 1 to rank n).

  4788.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  4789.   *         ADC conversion on only 1 channel.

  4790.   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength

  4791.   * @param  ADCx ADC instance

  4792.   * @retval Returned value can be one of the following values:

  4793.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  4794.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  4795.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  4796.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  4797.   */

  4798. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)

  4799. {

  4800.   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));

  4801. }

  4802. 

  4803. /**

  4804.   * @brief  Set ADC group injected sequencer discontinuous mode:

  4805.   *         sequence subdivided and scan conversions interrupted every selected

  4806.   *         number of ranks.

  4807.   * @note   It is not possible to enable both ADC group injected

  4808.   *         auto-injected mode and sequencer discontinuous mode.

  4809.   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont

  4810.   * @param  ADCx ADC instance

  4811.   * @param  SeqDiscont This parameter can be one of the following values:

  4812.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  4813.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  4814.   * @retval None

  4815.   */

  4816. __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  4817. {

  4818.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);

  4819. }

  4820. 

  4821. /**

  4822.   * @brief  Get ADC group injected sequencer discontinuous mode:

  4823.   *         sequence subdivided and scan conversions interrupted every selected

  4824.   *         number of ranks.

  4825.   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont

  4826.   * @param  ADCx ADC instance

  4827.   * @retval Returned value can be one of the following values:

  4828.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  4829.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  4830.   */

  4831. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)

  4832. {

  4833.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));

  4834. }

  4835. 

  4836. /**

  4837.   * @brief  Set ADC group injected sequence: channel on the selected

  4838.   *         sequence rank.

  4839.   * @note   Depending on devices and packages, some channels may not be available.

  4840.   *         Refer to device datasheet for channels availability.

  4841.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  4842.   *         TempSensor, ...), measurement paths to internal channels must be

  4843.   *         enabled separately.

  4844.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  4845.   * @note   On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs

  4846.   *         coming from GPIO pads (ADC_IN1..5).

  4847.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4848.   *         ADC state:

  4849.   *         ADC must not be disabled. Can be enabled with or without conversion

  4850.   *         on going on either groups regular or injected.

  4851.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n

  4852.   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n

  4853.   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n

  4854.   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks

  4855.   * @param  ADCx ADC instance

  4856.   * @param  Rank This parameter can be one of the following values:

  4857.   *         @arg @ref LL_ADC_INJ_RANK_1

  4858.   *         @arg @ref LL_ADC_INJ_RANK_2

  4859.   *         @arg @ref LL_ADC_INJ_RANK_3

  4860.   *         @arg @ref LL_ADC_INJ_RANK_4

  4861.   * @param  Channel This parameter can be one of the following values:

  4862.   *         @arg @ref LL_ADC_CHANNEL_0

  4863.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  4864.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  4865.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  4866.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  4867.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  4868.   *         @arg @ref LL_ADC_CHANNEL_6

  4869.   *         @arg @ref LL_ADC_CHANNEL_7

  4870.   *         @arg @ref LL_ADC_CHANNEL_8

  4871.   *         @arg @ref LL_ADC_CHANNEL_9

  4872.   *         @arg @ref LL_ADC_CHANNEL_10

  4873.   *         @arg @ref LL_ADC_CHANNEL_11

  4874.   *         @arg @ref LL_ADC_CHANNEL_12

  4875.   *         @arg @ref LL_ADC_CHANNEL_13

  4876.   *         @arg @ref LL_ADC_CHANNEL_14

  4877.   *         @arg @ref LL_ADC_CHANNEL_15

  4878.   *         @arg @ref LL_ADC_CHANNEL_16

  4879.   *         @arg @ref LL_ADC_CHANNEL_17

  4880.   *         @arg @ref LL_ADC_CHANNEL_18

  4881.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  4882.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  4883.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  4884.   *

  4885.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  4886.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  4887.   * @retval None

  4888.   */

  4889. __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  4890. {

  4891.   /* Set bits with content of parameter "Channel" with bits position          */

  4892.   /* in register depending on parameter "Rank".                               */

  4893.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  4894.   /* other bits reserved for other purpose.                                   */

  4895.   MODIFY_REG(ADCx->JSQR,

  4896.              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),

  4897.              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));

  4898. }

  4899. 

  4900. /**

  4901.   * @brief  Get ADC group injected sequence: channel on the selected

  4902.   *         sequence rank.

  4903.   * @note   Depending on devices and packages, some channels may not be available.

  4904.   *         Refer to device datasheet for channels availability.

  4905.   * @note   Usage of the returned channel number:

  4906.   *         - To reinject this channel into another function LL_ADC_xxx:

  4907.   *           the returned channel number is only partly formatted on definition

  4908.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  4909.   *           with parts of literals LL_ADC_CHANNEL_x or using

  4910.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4911.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  4912.   *           as parameter for another function.

  4913.   *         - To get the channel number in decimal format:

  4914.   *           process the returned value with the helper macro

  4915.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4916.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n

  4917.   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n

  4918.   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n

  4919.   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks

  4920.   * @param  ADCx ADC instance

  4921.   * @param  Rank This parameter can be one of the following values:

  4922.   *         @arg @ref LL_ADC_INJ_RANK_1

  4923.   *         @arg @ref LL_ADC_INJ_RANK_2

  4924.   *         @arg @ref LL_ADC_INJ_RANK_3

  4925.   *         @arg @ref LL_ADC_INJ_RANK_4

  4926.   * @retval Returned value can be one of the following values:

  4927.   *         @arg @ref LL_ADC_CHANNEL_0

  4928.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  4929.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  4930.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  4931.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  4932.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  4933.   *         @arg @ref LL_ADC_CHANNEL_6

  4934.   *         @arg @ref LL_ADC_CHANNEL_7

  4935.   *         @arg @ref LL_ADC_CHANNEL_8

  4936.   *         @arg @ref LL_ADC_CHANNEL_9

  4937.   *         @arg @ref LL_ADC_CHANNEL_10

  4938.   *         @arg @ref LL_ADC_CHANNEL_11

  4939.   *         @arg @ref LL_ADC_CHANNEL_12

  4940.   *         @arg @ref LL_ADC_CHANNEL_13

  4941.   *         @arg @ref LL_ADC_CHANNEL_14

  4942.   *         @arg @ref LL_ADC_CHANNEL_15

  4943.   *         @arg @ref LL_ADC_CHANNEL_16

  4944.   *         @arg @ref LL_ADC_CHANNEL_17

  4945.   *         @arg @ref LL_ADC_CHANNEL_18

  4946.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (4)

  4947.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)

  4948.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)

  4949.   *

  4950.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  4951.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n

  4952.   *         (4) For ADC channel read back from ADC register,

  4953.   *             comparison with internal channel parameter to be done

  4954.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  4955.   */

  4956. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  4957. {

  4958.   return (uint32_t)((READ_BIT(ADCx->JSQR,

  4959.                               (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))

  4960.                      >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

  4961.                    );

  4962. }

  4963. 

  4964. /**

  4965.   * @brief  Set ADC group injected conversion trigger:

  4966.   *         independent or from ADC group regular.

  4967.   * @note   This mode can be used to extend number of data registers

  4968.   *         updated after one ADC conversion trigger and with data

  4969.   *         permanently kept (not erased by successive conversions of scan of

  4970.   *         ADC sequencer ranks), up to 5 data registers:

  4971.   *         1 data register on ADC group regular, 4 data registers

  4972.   *         on ADC group injected.

  4973.   * @note   If ADC group injected injected trigger source is set to an

  4974.   *         external trigger, this feature must be must be set to

  4975.   *         independent trigger.

  4976.   *         ADC group injected automatic trigger is compliant only with

  4977.   *         group injected trigger source set to SW start, without any

  4978.   *         further action on  ADC group injected conversion start or stop:

  4979.   *         in this case, ADC group injected is controlled only

  4980.   *         from ADC group regular.

  4981.   * @note   It is not possible to enable both ADC group injected

  4982.   *         auto-injected mode and sequencer discontinuous mode.

  4983.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4984.   *         ADC state:

  4985.   *         ADC must be disabled or enabled without conversion on going

  4986.   *         on either groups regular or injected.

  4987.   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto

  4988.   * @param  ADCx ADC instance

  4989.   * @param  TrigAuto This parameter can be one of the following values:

  4990.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  4991.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  4992.   * @retval None

  4993.   */

  4994. __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)

  4995. {

  4996.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);

  4997. }

  4998. 

  4999. /**

  5000.   * @brief  Get ADC group injected conversion trigger:

  5001.   *         independent or from ADC group regular.

  5002.   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto

  5003.   * @param  ADCx ADC instance

  5004.   * @retval Returned value can be one of the following values:

  5005.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  5006.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  5007.   */

  5008. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)

  5009. {

  5010.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));

  5011. }

  5012. 

  5013. /**

  5014.   * @brief  Set ADC group injected contexts queue mode.

  5015.   * @note   A context is a setting of group injected sequencer:

  5016.   *         - group injected trigger

  5017.   *         - sequencer length

  5018.   *         - sequencer ranks

  5019.   *         If contexts queue is disabled:

  5020.   *         - only 1 sequence can be configured

  5021.   *           and is active perpetually.

  5022.   *         If contexts queue is enabled:

  5023.   *         - up to 2 contexts can be queued

  5024.   *           and are checked in and out as a FIFO stack (first-in, first-out).

  5025.   *         - If a new context is set when queues is full, error is triggered

  5026.   *           by interruption "Injected Queue Overflow".

  5027.   *         - Two behaviors are possible when all contexts have been processed:

  5028.   *           the contexts queue can maintain the last context active perpetually

  5029.   *           or can be empty and injected group triggers are disabled.

  5030.   *         - Triggers can be only external (not internal SW start)

  5031.   *         - Caution: The sequence must be fully configured in one time

  5032.   *           (one write of register JSQR makes a check-in of a new context

  5033.   *           into the queue).

  5034.   *           Therefore functions to set separately injected trigger and

  5035.   *           sequencer channels cannot be used, register JSQR must be set

  5036.   *           using function @ref LL_ADC_INJ_ConfigQueueContext().

  5037.   * @note   This parameter can be modified only when no conversion is on going

  5038.   *         on either groups regular or injected.

  5039.   * @note   A modification of the context mode (bit JQDIS) causes the contexts

  5040.   *         queue to be flushed and the register JSQR is cleared.

  5041.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5042.   *         ADC state:

  5043.   *         ADC must be disabled or enabled without conversion on going

  5044.   *         on either groups regular or injected.

  5045.   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n

  5046.   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode

  5047.   * @param  ADCx ADC instance

  5048.   * @param  QueueMode This parameter can be one of the following values:

  5049.   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE

  5050.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE

  5051.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

  5052.   * @retval None

  5053.   */

  5054. __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)

  5055. {

  5056.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);

  5057. }

  5058. 

  5059. /**

  5060.   * @brief  Get ADC group injected context queue mode.

  5061.   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n

  5062.   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode

  5063.   * @param  ADCx ADC instance

  5064.   * @retval Returned value can be one of the following values:

  5065.   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE

  5066.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE

  5067.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

  5068.   */

  5069. __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)

  5070. {

  5071.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));

  5072. }

  5073. 

  5074. /**

  5075.   * @brief  Set one context on ADC group injected that will be checked in

  5076.   *         contexts queue.

  5077.   * @note   A context is a setting of group injected sequencer:

  5078.   *         - group injected trigger

  5079.   *         - sequencer length

  5080.   *         - sequencer ranks

  5081.   *         This function is intended to be used when contexts queue is enabled,

  5082.   *         because the sequence must be fully configured in one time

  5083.   *         (functions to set separately injected trigger and sequencer channels

  5084.   *         cannot be used):

  5085.   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().

  5086.   * @note   In the contexts queue, only the active context can be read.

  5087.   *         The parameters of this function can be read using functions:

  5088.   *         @arg @ref LL_ADC_INJ_GetTriggerSource()

  5089.   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()

  5090.   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()

  5091.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  5092.   *         TempSensor, ...), measurement paths to internal channels must be

  5093.   *         enabled separately.

  5094.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  5095.   * @note   On STM32WB (except devices: STM32WB10xx, STM32WB15xx), some fast channels are available: fast analog inputs

  5096.   *         coming from GPIO pads (ADC_IN1..5).

  5097.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5098.   *         ADC state:

  5099.   *         ADC must not be disabled. Can be enabled with or without conversion

  5100.   *         on going on either groups regular or injected.

  5101.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n

  5102.   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n

  5103.   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n

  5104.   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n

  5105.   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n

  5106.   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n

  5107.   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext

  5108.   * @param  ADCx ADC instance

  5109.   * @param  TriggerSource This parameter can be one of the following values:

  5110.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  5111.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  5112.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  5113.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  5114.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  5115.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  5116.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  5117.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  5118.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  5119.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  5120.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  5121.   *

  5122.   *         Note: This parameter is discarded in case of SW start:

  5123.   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".

  5124.   * @param  SequencerNbRanks This parameter can be one of the following values:

  5125.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  5126.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  5127.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  5128.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  5129.   * @param  Rank1_Channel This parameter can be one of the following values:

  5130.   *         @arg @ref LL_ADC_CHANNEL_0

  5131.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  5132.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  5133.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  5134.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  5135.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  5136.   *         @arg @ref LL_ADC_CHANNEL_6

  5137.   *         @arg @ref LL_ADC_CHANNEL_7

  5138.   *         @arg @ref LL_ADC_CHANNEL_8

  5139.   *         @arg @ref LL_ADC_CHANNEL_9

  5140.   *         @arg @ref LL_ADC_CHANNEL_10

  5141.   *         @arg @ref LL_ADC_CHANNEL_11

  5142.   *         @arg @ref LL_ADC_CHANNEL_12

  5143.   *         @arg @ref LL_ADC_CHANNEL_13

  5144.   *         @arg @ref LL_ADC_CHANNEL_14

  5145.   *         @arg @ref LL_ADC_CHANNEL_15

  5146.   *         @arg @ref LL_ADC_CHANNEL_16

  5147.   *         @arg @ref LL_ADC_CHANNEL_17

  5148.   *         @arg @ref LL_ADC_CHANNEL_18

  5149.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  5150.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  5151.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  5152.   *

  5153.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  5154.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  5155.   * @param  Rank2_Channel This parameter can be one of the following values:

  5156.   *         @arg @ref LL_ADC_CHANNEL_0

  5157.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  5158.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  5159.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  5160.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  5161.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  5162.   *         @arg @ref LL_ADC_CHANNEL_6

  5163.   *         @arg @ref LL_ADC_CHANNEL_7

  5164.   *         @arg @ref LL_ADC_CHANNEL_8

  5165.   *         @arg @ref LL_ADC_CHANNEL_9

  5166.   *         @arg @ref LL_ADC_CHANNEL_10

  5167.   *         @arg @ref LL_ADC_CHANNEL_11

  5168.   *         @arg @ref LL_ADC_CHANNEL_12

  5169.   *         @arg @ref LL_ADC_CHANNEL_13

  5170.   *         @arg @ref LL_ADC_CHANNEL_14

  5171.   *         @arg @ref LL_ADC_CHANNEL_15

  5172.   *         @arg @ref LL_ADC_CHANNEL_16

  5173.   *         @arg @ref LL_ADC_CHANNEL_17

  5174.   *         @arg @ref LL_ADC_CHANNEL_18

  5175.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  5176.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  5177.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  5178.   *

  5179.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  5180.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  5181.   * @param  Rank3_Channel This parameter can be one of the following values:

  5182.   *         @arg @ref LL_ADC_CHANNEL_0

  5183.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  5184.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  5185.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  5186.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  5187.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  5188.   *         @arg @ref LL_ADC_CHANNEL_6

  5189.   *         @arg @ref LL_ADC_CHANNEL_7

  5190.   *         @arg @ref LL_ADC_CHANNEL_8

  5191.   *         @arg @ref LL_ADC_CHANNEL_9

  5192.   *         @arg @ref LL_ADC_CHANNEL_10

  5193.   *         @arg @ref LL_ADC_CHANNEL_11

  5194.   *         @arg @ref LL_ADC_CHANNEL_12

  5195.   *         @arg @ref LL_ADC_CHANNEL_13

  5196.   *         @arg @ref LL_ADC_CHANNEL_14

  5197.   *         @arg @ref LL_ADC_CHANNEL_15

  5198.   *         @arg @ref LL_ADC_CHANNEL_16

  5199.   *         @arg @ref LL_ADC_CHANNEL_17

  5200.   *         @arg @ref LL_ADC_CHANNEL_18

  5201.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  5202.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  5203.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  5204.   *

  5205.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  5206.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  5207.   * @param  Rank4_Channel This parameter can be one of the following values:

  5208.   *         @arg @ref LL_ADC_CHANNEL_0

  5209.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  5210.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  5211.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  5212.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  5213.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  5214.   *         @arg @ref LL_ADC_CHANNEL_6

  5215.   *         @arg @ref LL_ADC_CHANNEL_7

  5216.   *         @arg @ref LL_ADC_CHANNEL_8

  5217.   *         @arg @ref LL_ADC_CHANNEL_9

  5218.   *         @arg @ref LL_ADC_CHANNEL_10

  5219.   *         @arg @ref LL_ADC_CHANNEL_11

  5220.   *         @arg @ref LL_ADC_CHANNEL_12

  5221.   *         @arg @ref LL_ADC_CHANNEL_13

  5222.   *         @arg @ref LL_ADC_CHANNEL_14

  5223.   *         @arg @ref LL_ADC_CHANNEL_15

  5224.   *         @arg @ref LL_ADC_CHANNEL_16

  5225.   *         @arg @ref LL_ADC_CHANNEL_17

  5226.   *         @arg @ref LL_ADC_CHANNEL_18

  5227.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  5228.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  5229.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  5230.   *

  5231.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  5232.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  5233.   * @retval None

  5234.   */

  5235. __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,

  5236.                                                    uint32_t TriggerSource,

  5237.                                                    uint32_t ExternalTriggerEdge,

  5238.                                                    uint32_t SequencerNbRanks,

  5239.                                                    uint32_t Rank1_Channel,

  5240.                                                    uint32_t Rank2_Channel,

  5241.                                                    uint32_t Rank3_Channel,

  5242.                                                    uint32_t Rank4_Channel)

  5243. {

  5244.   /* Set bits with content of parameter "Rankx_Channel" with bits position    */

  5245.   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */

  5246.   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */

  5247.   /* because containing other bits reserved for other purpose.                */

  5248.   /* If parameter "TriggerSource" is set to SW start, then parameter          */

  5249.   /* "ExternalTriggerEdge" is discarded.                                      */

  5250.   uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);

  5251.   MODIFY_REG(ADCx->JSQR,

  5252.              ADC_JSQR_JEXTSEL |

  5253.              ADC_JSQR_JEXTEN  |

  5254.              ADC_JSQR_JSQ4    |

  5255.              ADC_JSQR_JSQ3    |

  5256.              ADC_JSQR_JSQ2    |

  5257.              ADC_JSQR_JSQ1    |

  5258.              ADC_JSQR_JL,

  5259.              (TriggerSource & ADC_JSQR_JEXTSEL)          |

  5260.              (ExternalTriggerEdge * (is_trigger_not_sw)) |

  5261.              (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  5262.              (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  5263.              (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  5264.              (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  5265.              SequencerNbRanks

  5266.             );

  5267. }

  5268. 

  5269. /**

  5270.   * @}

  5271.   */

  5272. 

  5273. #endif /* ADC_SUPPORT_2_5_MSPS */

  5274. /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels

  5275.   * @{

  5276.   */

  5277. 

  5278. #if defined (ADC_SUPPORT_2_5_MSPS)

  5279. /**

  5280.   * @brief  Set sampling time of the selected ADC channel

  5281.   *         Unit: ADC clock cycles.

  5282.   * @note   On this device, sampling time is on channel scope: independently

  5283.   *         of channel mapped on ADC group regular or injected.

  5284.   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be

  5285.   *         converted:

  5286.   *         sampling time constraints must be respected (sampling time can be

  5287.   *         adjusted in function of ADC clock frequency and sampling time

  5288.   *         setting).

  5289.   *         Refer to device datasheet for timings values (parameters TS_vrefint,

  5290.   *         TS_temp, ...).

  5291.   * @note   Conversion time is the addition of sampling time and processing time.

  5292.   *         On this STM32 serie, ADC processing time is:

  5293.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  5294.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  5295.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  5296.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  5297.   * @note   In case of ADC conversion of internal channel (VrefInt,

  5298.   *         temperature sensor, ...), a sampling time minimum value

  5299.   *         is required.

  5300.   *         Refer to device datasheet.

  5301.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5302.   *         ADC state:

  5303.   *         ADC must be disabled or enabled without conversion on going

  5304.   *         on either groups regular or injected.

  5305.   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n

  5306.   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n

  5307.   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n

  5308.   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n

  5309.   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n

  5310.   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n

  5311.   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n

  5312.   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n

  5313.   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n

  5314.   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n

  5315.   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n

  5316.   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n

  5317.   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n

  5318.   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n

  5319.   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n

  5320.   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n

  5321.   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n

  5322.   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n

  5323.   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime

  5324.   * @param  ADCx ADC instance

  5325.   * @param  Channel This parameter can be one of the following values:

  5326.   *         @arg @ref LL_ADC_CHANNEL_0

  5327.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  5328.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  5329.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  5330.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  5331.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  5332.   *         @arg @ref LL_ADC_CHANNEL_6

  5333.   *         @arg @ref LL_ADC_CHANNEL_7

  5334.   *         @arg @ref LL_ADC_CHANNEL_8

  5335.   *         @arg @ref LL_ADC_CHANNEL_9

  5336.   *         @arg @ref LL_ADC_CHANNEL_10

  5337.   *         @arg @ref LL_ADC_CHANNEL_11

  5338.   *         @arg @ref LL_ADC_CHANNEL_12

  5339.   *         @arg @ref LL_ADC_CHANNEL_13

  5340.   *         @arg @ref LL_ADC_CHANNEL_14

  5341.   *         @arg @ref LL_ADC_CHANNEL_15

  5342.   *         @arg @ref LL_ADC_CHANNEL_16

  5343.   *         @arg @ref LL_ADC_CHANNEL_17

  5344.   *         @arg @ref LL_ADC_CHANNEL_18

  5345.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  5346.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  5347.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  5348.   *

  5349.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  5350.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  5351.   * @param  SamplingTimeY This parameter can be one of the following values:

  5352.   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1

  5353.   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2

  5354.   * @retval None

  5355.   */

  5356. __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)

  5357. {

  5358.   /* Parameter "Channel" is used with masks because containing                */

  5359.   /* other bits reserved for other purpose.                                   */

  5360.   MODIFY_REG(ADCx->SMPR,

  5361.              (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),

  5362.              (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)

  5363.             );

  5364. }

  5365. #else

  5366. /**

  5367.   * @brief  Set sampling time of the selected ADC channel

  5368.   *         Unit: ADC clock cycles.

  5369.   * @note   On this device, sampling time is on channel scope: independently

  5370.   *         of channel mapped on ADC group regular or injected.

  5371.   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be

  5372.   *         converted:

  5373.   *         sampling time constraints must be respected (sampling time can be

  5374.   *         adjusted in function of ADC clock frequency and sampling time

  5375.   *         setting).

  5376.   *         Refer to device datasheet for timings values (parameters TS_vrefint,

  5377.   *         TS_temp, ...).

  5378.   * @note   Conversion time is the addition of sampling time and processing time.

  5379.   *         On this STM32 serie, ADC processing time is:

  5380.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  5381.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  5382.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  5383.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  5384.   * @note   In case of ADC conversion of internal channel (VrefInt,

  5385.   *         temperature sensor, ...), a sampling time minimum value

  5386.   *         is required.

  5387.   *         Refer to device datasheet.

  5388.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5389.   *         ADC state:

  5390.   *         ADC must be disabled or enabled without conversion on going

  5391.   *         on either groups regular or injected.

  5392.   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n

  5393.   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n

  5394.   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n

  5395.   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n

  5396.   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n

  5397.   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n

  5398.   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n

  5399.   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n

  5400.   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n

  5401.   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n

  5402.   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n

  5403.   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n

  5404.   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n

  5405.   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n

  5406.   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n

  5407.   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n

  5408.   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n

  5409.   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n

  5410.   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime

  5411.   * @param  ADCx ADC instance

  5412.   * @param  Channel This parameter can be one of the following values:

  5413.   *         @arg @ref LL_ADC_CHANNEL_0

  5414.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  5415.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  5416.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  5417.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  5418.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  5419.   *         @arg @ref LL_ADC_CHANNEL_6

  5420.   *         @arg @ref LL_ADC_CHANNEL_7

  5421.   *         @arg @ref LL_ADC_CHANNEL_8

  5422.   *         @arg @ref LL_ADC_CHANNEL_9

  5423.   *         @arg @ref LL_ADC_CHANNEL_10

  5424.   *         @arg @ref LL_ADC_CHANNEL_11

  5425.   *         @arg @ref LL_ADC_CHANNEL_12

  5426.   *         @arg @ref LL_ADC_CHANNEL_13

  5427.   *         @arg @ref LL_ADC_CHANNEL_14

  5428.   *         @arg @ref LL_ADC_CHANNEL_15

  5429.   *         @arg @ref LL_ADC_CHANNEL_16

  5430.   *         @arg @ref LL_ADC_CHANNEL_17

  5431.   *         @arg @ref LL_ADC_CHANNEL_18

  5432.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  5433.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  5434.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  5435.   *

  5436.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  5437.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  5438.   * @param  SamplingTime This parameter can be one of the following values:

  5439.   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5

  5440.   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5

  5441.   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5

  5442.   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5

  5443.   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5

  5444.   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5

  5445.   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5

  5446.   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5

  5447.   * @retval None

  5448.   */

  5449. __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)

  5450. {

  5451. #if defined (ADC_SUPPORT_2_5_MSPS)

  5452.   /* Parameter "Channel" is used with masks because containing                */

  5453.   /* other bits reserved for other purpose.                                   */

  5454.   MODIFY_REG(ADCx->SMPR,

  5455.              (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),

  5456.              (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)

  5457.             );

  5458. #else

  5459.   /* Set bits with content of parameter "SamplingTime" with bits position     */

  5460.   /* in register and register position depending on parameter "Channel".      */

  5461.   /* Parameter "Channel" is used with masks because containing                */

  5462.   /* other bits reserved for other purpose.                                   */

  5463.   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));

  5464. 

  5465.   MODIFY_REG(*preg,

  5466.              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),

  5467.              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));

  5468. #endif

  5469. }

  5470. #endif /* ADC_SUPPORT_2_5_MSPS */

  5471. 

  5472. #if defined (ADC_SUPPORT_2_5_MSPS)

  5473. /**

  5474.   * @brief  Get sampling time of the selected ADC channel

  5475.   *         Unit: ADC clock cycles.

  5476.   * @note   On this device, sampling time is on channel scope: independently

  5477.   *         of channel mapped on ADC group regular or injected.

  5478.   * @note   Conversion time is the addition of sampling time and processing time.

  5479.   *         On this STM32 serie, ADC processing time is:

  5480.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  5481.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  5482.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  5483.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  5484.   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n

  5485.   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n

  5486.   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n

  5487.   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n

  5488.   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n

  5489.   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n

  5490.   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n

  5491.   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n

  5492.   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n

  5493.   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n

  5494.   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n

  5495.   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n

  5496.   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n

  5497.   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n

  5498.   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n

  5499.   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n

  5500.   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n

  5501.   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n

  5502.   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime

  5503.   * @param  ADCx ADC instance

  5504.   * @param  Channel This parameter can be one of the following values:

  5505.   *         @arg @ref LL_ADC_CHANNEL_0

  5506.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  5507.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  5508.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  5509.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  5510.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  5511.   *         @arg @ref LL_ADC_CHANNEL_6

  5512.   *         @arg @ref LL_ADC_CHANNEL_7

  5513.   *         @arg @ref LL_ADC_CHANNEL_8

  5514.   *         @arg @ref LL_ADC_CHANNEL_9

  5515.   *         @arg @ref LL_ADC_CHANNEL_10

  5516.   *         @arg @ref LL_ADC_CHANNEL_11

  5517.   *         @arg @ref LL_ADC_CHANNEL_12

  5518.   *         @arg @ref LL_ADC_CHANNEL_13

  5519.   *         @arg @ref LL_ADC_CHANNEL_14

  5520.   *         @arg @ref LL_ADC_CHANNEL_15

  5521.   *         @arg @ref LL_ADC_CHANNEL_16

  5522.   *         @arg @ref LL_ADC_CHANNEL_17

  5523.   *         @arg @ref LL_ADC_CHANNEL_18

  5524.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  5525.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  5526.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  5527.   *

  5528.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  5529.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  5530.   * @retval Returned value can be one of the following values:

  5531.   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1

  5532.   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2

  5533.   */

  5534. __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)

  5535. {

  5536.   __IO uint32_t smpr = READ_REG(ADCx->SMPR);

  5537. 

  5538.   /* Retrieve sampling time bit corresponding to the selected channel            */

  5539.   /* and shift it to position 0.                                                 */

  5540.   uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)

  5541.                                            >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL));

  5542. 

  5543.   /* Select sampling time bitfield depending on sampling time bit value 0 or 1.  */

  5544.   return(  (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)

  5545.          | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2)   );

  5546. }

  5547. #else

  5548. /**

  5549.   * @brief  Get sampling time of the selected ADC channel

  5550.   *         Unit: ADC clock cycles.

  5551.   * @note   On this device, sampling time is on channel scope: independently

  5552.   *         of channel mapped on ADC group regular or injected.

  5553.   * @note   Conversion time is the addition of sampling time and processing time.

  5554.   *         On this STM32 serie, ADC processing time is:

  5555.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  5556.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  5557.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  5558.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  5559.   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n

  5560.   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n

  5561.   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n

  5562.   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n

  5563.   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n

  5564.   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n

  5565.   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n

  5566.   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n

  5567.   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n

  5568.   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n

  5569.   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n

  5570.   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n

  5571.   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n

  5572.   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n

  5573.   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n

  5574.   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n

  5575.   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n

  5576.   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n

  5577.   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime

  5578.   * @param  ADCx ADC instance

  5579.   * @param  Channel This parameter can be one of the following values:

  5580.   *         @arg @ref LL_ADC_CHANNEL_0

  5581.   *         @arg @ref LL_ADC_CHANNEL_1            (7)

  5582.   *         @arg @ref LL_ADC_CHANNEL_2            (7)

  5583.   *         @arg @ref LL_ADC_CHANNEL_3            (7)

  5584.   *         @arg @ref LL_ADC_CHANNEL_4            (7)

  5585.   *         @arg @ref LL_ADC_CHANNEL_5            (7)

  5586.   *         @arg @ref LL_ADC_CHANNEL_6

  5587.   *         @arg @ref LL_ADC_CHANNEL_7

  5588.   *         @arg @ref LL_ADC_CHANNEL_8

  5589.   *         @arg @ref LL_ADC_CHANNEL_9

  5590.   *         @arg @ref LL_ADC_CHANNEL_10

  5591.   *         @arg @ref LL_ADC_CHANNEL_11

  5592.   *         @arg @ref LL_ADC_CHANNEL_12

  5593.   *         @arg @ref LL_ADC_CHANNEL_13

  5594.   *         @arg @ref LL_ADC_CHANNEL_14

  5595.   *         @arg @ref LL_ADC_CHANNEL_15

  5596.   *         @arg @ref LL_ADC_CHANNEL_16

  5597.   *         @arg @ref LL_ADC_CHANNEL_17

  5598.   *         @arg @ref LL_ADC_CHANNEL_18

  5599.   *         @arg @ref LL_ADC_CHANNEL_VREFINT

  5600.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR

  5601.   *         @arg @ref LL_ADC_CHANNEL_VBAT

  5602.   *

  5603.   *         (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).

  5604.   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  5605.   * @retval Returned value can be one of the following values:

  5606.   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5

  5607.   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5

  5608.   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5

  5609.   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5

  5610.   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5

  5611.   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5

  5612.   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5

  5613.   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5

  5614.   */

  5615. __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)

  5616. {

  5617. #if defined (ADC_SUPPORT_2_5_MSPS)

  5618.   __IO uint32_t smpr = READ_REG(ADCx->SMPR);

  5619. 

  5620.   /* Retrieve sampling time bit corresponding to the selected channel            */

  5621.   /* and shift it to position 0.                                                 */

  5622.   uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)

  5623.                                            >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL));

  5624. 

  5625.   /* Select sampling time bitfield depending on sampling time bit value 0 or 1.  */

  5626.   return(  (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)

  5627.          | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2)   );

  5628. #else

  5629.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));

  5630. 

  5631.   return (uint32_t)(READ_BIT(*preg,

  5632.                              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))

  5633.                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)

  5634.                    );

  5635. #endif

  5636. }

  5637. #endif /* ADC_SUPPORT_2_5_MSPS */

  5638. 

  5639. #if defined (ADC_SUPPORT_2_5_MSPS)

  5640. /* Feature "ADC channel differential mode" not available on ADC peripheral of this STM32WB device */

  5641. #else

  5642. /**

  5643.   * @brief  Set mode single-ended or differential input of the selected

  5644.   *         ADC channel.

  5645.   * @note   Channel ending is on channel scope: independently of channel mapped

  5646.   *         on ADC group regular or injected.

  5647.   *         In differential mode: Differential measurement is carried out

  5648.   *         between the selected channel 'i' (positive input) and

  5649.   *         channel 'i+1' (negative input). Only channel 'i' has to be

  5650.   *         configured, channel 'i+1' is configured automatically.

  5651.   * @note   Refer to Reference Manual to ensure the selected channel is

  5652.   *         available in differential mode.

  5653.   *         For example, internal channels (VrefInt, TempSensor, ...) are

  5654.   *         not available in differential mode.

  5655.   * @note   When configuring a channel 'i' in differential mode,

  5656.   *         the channel 'i+1' is not usable separately.

  5657.   * @note   On STM32WB, channels 16, 17, 18 of ADC1

  5658.   *         are internally fixed to single-ended inputs configuration.

  5659.   * @note   For ADC channels configured in differential mode, both inputs

  5660.   *         should be biased at (Vref+)/2 +/-200mV.

  5661.   *         (Vref+ is the analog voltage reference)

  5662.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5663.   *         ADC state:

  5664.   *         ADC must be ADC disabled.

  5665.   * @note   One or several values can be selected.

  5666.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  5667.   * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff

  5668.   * @param  ADCx ADC instance

  5669.   * @param  Channel This parameter can be one of the following values:

  5670.   *         @arg @ref LL_ADC_CHANNEL_1

  5671.   *         @arg @ref LL_ADC_CHANNEL_2

  5672.   *         @arg @ref LL_ADC_CHANNEL_3

  5673.   *         @arg @ref LL_ADC_CHANNEL_4

  5674.   *         @arg @ref LL_ADC_CHANNEL_5

  5675.   *         @arg @ref LL_ADC_CHANNEL_6

  5676.   *         @arg @ref LL_ADC_CHANNEL_7

  5677.   *         @arg @ref LL_ADC_CHANNEL_8

  5678.   *         @arg @ref LL_ADC_CHANNEL_9

  5679.   *         @arg @ref LL_ADC_CHANNEL_10

  5680.   *         @arg @ref LL_ADC_CHANNEL_11

  5681.   *         @arg @ref LL_ADC_CHANNEL_12

  5682.   *         @arg @ref LL_ADC_CHANNEL_13

  5683.   *         @arg @ref LL_ADC_CHANNEL_14

  5684.   *         @arg @ref LL_ADC_CHANNEL_15

  5685.   * @param  SingleDiff This parameter can be a combination of the following values:

  5686.   *         @arg @ref LL_ADC_SINGLE_ENDED

  5687.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  5688.   * @retval None

  5689.   */

  5690. __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)

  5691. {

  5692.   /* Bits of channels in single or differential mode are set only for         */

  5693.   /* differential mode (for single mode, mask of bits allowed to be set is    */

  5694.   /* shifted out of range of bits of channels in single or differential mode. */

  5695.   MODIFY_REG(ADCx->DIFSEL,

  5696.              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,

  5697.              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));

  5698. }

  5699. 

  5700. /**

  5701.   * @brief  Get mode single-ended or differential input of the selected

  5702.   *         ADC channel.

  5703.   * @note   When configuring a channel 'i' in differential mode,

  5704.   *         the channel 'i+1' is not usable separately.

  5705.   *         Therefore, to ensure a channel is configured in single-ended mode,

  5706.   *         the configuration of channel itself and the channel 'i-1' must be

  5707.   *         read back (to ensure that the selected channel channel has not been

  5708.   *         configured in differential mode by the previous channel).

  5709.   * @note   Refer to Reference Manual to ensure the selected channel is

  5710.   *         available in differential mode.

  5711.   *         For example, internal channels (VrefInt, TempSensor, ...) are

  5712.   *         not available in differential mode.

  5713.   * @note   When configuring a channel 'i' in differential mode,

  5714.   *         the channel 'i+1' is not usable separately.

  5715.   * @note   On STM32WB, channels 16, 17, 18 of ADC1

  5716.   *         are internally fixed to single-ended inputs configuration.

  5717.   * @note   One or several values can be selected. In this case, the value

  5718.   *         returned is null if all channels are in single ended-mode.

  5719.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  5720.   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff

  5721.   * @param  ADCx ADC instance

  5722.   * @param  Channel This parameter can be a combination of the following values:

  5723.   *         @arg @ref LL_ADC_CHANNEL_1

  5724.   *         @arg @ref LL_ADC_CHANNEL_2

  5725.   *         @arg @ref LL_ADC_CHANNEL_3

  5726.   *         @arg @ref LL_ADC_CHANNEL_4

  5727.   *         @arg @ref LL_ADC_CHANNEL_5

  5728.   *         @arg @ref LL_ADC_CHANNEL_6

  5729.   *         @arg @ref LL_ADC_CHANNEL_7

  5730.   *         @arg @ref LL_ADC_CHANNEL_8

  5731.   *         @arg @ref LL_ADC_CHANNEL_9

  5732.   *         @arg @ref LL_ADC_CHANNEL_10

  5733.   *         @arg @ref LL_ADC_CHANNEL_11

  5734.   *         @arg @ref LL_ADC_CHANNEL_12

  5735.   *         @arg @ref LL_ADC_CHANNEL_13

  5736.   *         @arg @ref LL_ADC_CHANNEL_14

  5737.   *         @arg @ref LL_ADC_CHANNEL_15

  5738.   * @retval 0: channel in single-ended mode, else: channel in differential mode

  5739.   */

  5740. __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)

  5741. {

  5742.   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));

  5743. }

  5744. 

  5745. #endif /* ADC_SUPPORT_2_5_MSPS */

  5746. /**

  5747.   * @}

  5748.   */

  5749. 

  5750. /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog

  5751.   * @{

  5752.   */

  5753. 

  5754. /**

  5755.   * @brief  Set ADC analog watchdog monitored channels:

  5756.   *         a single channel, multiple channels or all channels,

  5757.   *         on ADC groups regular and-or injected.

  5758.   * @note   Once monitored channels are selected, analog watchdog

  5759.   *         is enabled.

  5760.   * @note   In case of need to define a single channel to monitor

  5761.   *         with analog watchdog from sequencer channel definition,

  5762.   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().

  5763.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  5764.   *         instance:

  5765.   *         - AWD standard (instance AWD1):

  5766.   *           - channels monitored: can monitor 1 channel or all channels.

  5767.   *           - groups monitored: ADC groups regular and-or injected.

  5768.   *           - resolution: resolution is not limited (corresponds to

  5769.   *             ADC resolution configured).

  5770.   *         - AWD flexible (instances AWD2, AWD3):

  5771.   *           - channels monitored: flexible on channels monitored, selection is

  5772.   *             channel wise, from from 1 to all channels.

  5773.   *             Specificity of this analog watchdog: Multiple channels can

  5774.   *             be selected. For example:

  5775.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  5776.   *           - groups monitored: not selection possible (monitoring on both

  5777.   *             groups regular and injected).

  5778.   *             Channels selected are monitored on groups regular and injected:

  5779.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  5780.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  5781.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  5782.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  5783.   *             the 2 LSB are ignored.

  5784.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5785.   *         ADC state:

  5786.   *         ADC must be disabled or enabled without conversion on going

  5787.   *         on either groups regular or injected.

  5788.   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n

  5789.   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n

  5790.   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n

  5791.   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n

  5792.   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n

  5793.   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels

  5794.   * @param  ADCx ADC instance

  5795.   * @param  AWDy This parameter can be one of the following values:

  5796.   *         @arg @ref LL_ADC_AWD1

  5797.   *         @arg @ref LL_ADC_AWD2

  5798.   *         @arg @ref LL_ADC_AWD3

  5799.   * @param  AWDChannelGroup This parameter can be one of the following values:

  5800.   *         @arg @ref LL_ADC_AWD_DISABLE

  5801.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  5802.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)(1)

  5803.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ       (1)

  5804.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  5805.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)(1)

  5806.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ          (1)

  5807.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  5808.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)(1)

  5809.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ          (1)

  5810.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  5811.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)(1)

  5812.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ          (1)

  5813.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  5814.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)(1)

  5815.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ          (1)

  5816.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  5817.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)(1)

  5818.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ          (1)

  5819.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  5820.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)(1)

  5821.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ          (1)

  5822.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  5823.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)(1)

  5824.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ          (1)

  5825.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  5826.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)(1)

  5827.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ          (1)

  5828.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  5829.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)(1)

  5830.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ          (1)

  5831.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  5832.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)(1)

  5833.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ          (1)

  5834.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  5835.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)(1)

  5836.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ         (1)

  5837.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  5838.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)(1)

  5839.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ         (1)

  5840.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  5841.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)(1)

  5842.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ         (1)

  5843.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  5844.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)(1)

  5845.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ         (1)

  5846.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  5847.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)(1)

  5848.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ         (1)

  5849.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  5850.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)(1)

  5851.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ         (1)

  5852.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  5853.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)(1)

  5854.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ         (1)

  5855.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  5856.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)(1)

  5857.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ         (1)

  5858.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  5859.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)(1)

  5860.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ         (1)

  5861.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)

  5862.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)

  5863.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)

  5864.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)

  5865.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)

  5866.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)

  5867.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)

  5868.   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)

  5869.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)

  5870.   *

  5871.   *         (0) On STM32WB, parameter available only on analog watchdog number: AWD1.

  5872.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  5873.   * @retval None

  5874.   */

  5875. __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)

  5876. {

  5877. #if defined (ADC_SUPPORT_2_5_MSPS)

  5878.   /* Prevent unused argument(s) compilation warning */

  5879.   (void)(AWDy);

  5880. 

  5881.   MODIFY_REG(ADCx->CFGR1,

  5882.              (LL_ADC_AWD1 & ADC_AWD_CR_ALL_CHANNEL_MASK),

  5883.              AWDChannelGroup & LL_ADC_AWD1);

  5884. #else

  5885.   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */

  5886.   /* in register and register position depending on parameter "AWDy".         */

  5887.   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */

  5888.   /* containing other bits reserved for other purpose.                        */

  5889.   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)

  5890.                                                       + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));

  5891. 

  5892.   MODIFY_REG(*preg,

  5893.              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),

  5894.              AWDChannelGroup & AWDy);

  5895. #endif

  5896. }

  5897. 

  5898. /**

  5899.   * @brief  Get ADC analog watchdog monitored channel.

  5900.   * @note   Usage of the returned channel number:

  5901.   *         - To reinject this channel into another function LL_ADC_xxx:

  5902.   *           the returned channel number is only partly formatted on definition

  5903.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  5904.   *           with parts of literals LL_ADC_CHANNEL_x or using

  5905.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  5906.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  5907.   *           as parameter for another function.

  5908.   *         - To get the channel number in decimal format:

  5909.   *           process the returned value with the helper macro

  5910.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  5911.   *           Applicable only when the analog watchdog is set to monitor

  5912.   *           one channel.

  5913.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  5914.   *         instance:

  5915.   *         - AWD standard (instance AWD1):

  5916.   *           - channels monitored: can monitor 1 channel or all channels.

  5917.   *           - groups monitored: ADC groups regular and-or injected.

  5918.   *           - resolution: resolution is not limited (corresponds to

  5919.   *             ADC resolution configured).

  5920.   *         - AWD flexible (instances AWD2, AWD3):

  5921.   *           - channels monitored: flexible on channels monitored, selection is

  5922.   *             channel wise, from from 1 to all channels.

  5923.   *             Specificity of this analog watchdog: Multiple channels can

  5924.   *             be selected. For example:

  5925.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  5926.   *           - groups monitored: not selection possible (monitoring on both

  5927.   *             groups regular and injected).

  5928.   *             Channels selected are monitored on groups regular and injected:

  5929.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  5930.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  5931.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  5932.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  5933.   *             the 2 LSB are ignored.

  5934.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5935.   *         ADC state:

  5936.   *         ADC must be disabled or enabled without conversion on going

  5937.   *         on either groups regular or injected.

  5938.   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n

  5939.   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n

  5940.   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n

  5941.   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n

  5942.   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n

  5943.   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels

  5944.   * @param  ADCx ADC instance

  5945.   * @param  AWDy This parameter can be one of the following values:

  5946.   *         @arg @ref LL_ADC_AWD1

  5947.   *         @arg @ref LL_ADC_AWD2 (1)(2)

  5948.   *         @arg @ref LL_ADC_AWD3 (1)(2)

  5949.   *

  5950.   *         (1) On this AWD number, monitored channel can be retrieved

  5951.   *             if only 1 channel is programmed (or none or all channels).

  5952.   *             This function cannot retrieve monitored channel if

  5953.   *             multiple channels are programmed simultaneously

  5954.   *             by bitfield.

  5955.   *         (2) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  5956.   * @retval Returned value can be one of the following values:

  5957.   *         @arg @ref LL_ADC_AWD_DISABLE

  5958.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  5959.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)(1)

  5960.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ       (1)

  5961.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  5962.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)(1)

  5963.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ          (1)

  5964.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  5965.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)(1)

  5966.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ          (1)

  5967.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  5968.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)(1)

  5969.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ          (1)

  5970.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  5971.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)(1)

  5972.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ          (1)

  5973.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  5974.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)(1)

  5975.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ          (1)

  5976.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  5977.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)(1)

  5978.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ          (1)

  5979.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  5980.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)(1)

  5981.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ         (1)

  5982.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  5983.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)(1)

  5984.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ          (1)

  5985.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  5986.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)(1)

  5987.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ          (1)

  5988.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  5989.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)(1)

  5990.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ          (1)

  5991.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  5992.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)(1)

  5993.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ         (1)

  5994.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  5995.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)(1)

  5996.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ         (1)

  5997.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  5998.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)(1)

  5999.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ         (1)

  6000.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  6001.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)(1)

  6002.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ         (1)

  6003.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  6004.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)(1)

  6005.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ         (1)

  6006.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  6007.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)(1)

  6008.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ         (1)

  6009.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  6010.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)(1)

  6011.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ         (1)

  6012.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  6013.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)(1)

  6014.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ         (1)

  6015.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  6016.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)(1)

  6017.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ         (1)

  6018.   *

  6019.   *         (0) On STM32WB, parameter available only on analog watchdog number: AWD1.

  6020.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  6021.   */

  6022. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)

  6023. {

  6024. #if defined (ADC_SUPPORT_2_5_MSPS)

  6025.   /* Prevent unused argument(s) compilation warning */

  6026.   (void)(AWDy);

  6027. 

  6028.   uint32_t AnalogWDMonitChannels = (READ_BIT(ADCx->CFGR1, LL_ADC_AWD1) & LL_ADC_AWD1 & ADC_AWD_CR_ALL_CHANNEL_MASK);

  6029. 

  6030.   /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */

  6031.   /* (parameter value LL_ADC_AWD_DISABLE).                                    */

  6032.   /* Else, the selected AWD is enabled and is monitoring a group of channels  */

  6033.   /* or a single channel.                                                     */

  6034.   if(AnalogWDMonitChannels != 0UL)

  6035.   {

  6036.     if((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL)

  6037.     {

  6038.       /* AWD monitoring a group of channels */

  6039.       AnalogWDMonitChannels = (AnalogWDMonitChannels

  6040.                                & (~(ADC_CFGR1_AWD1CH))

  6041.                               );

  6042.     }

  6043.     else

  6044.     {

  6045.       /* AWD monitoring a single channel */

  6046.       AnalogWDMonitChannels = (AnalogWDMonitChannels

  6047.                                | (0x01UL << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos))

  6048.                               );

  6049.     }

  6050.   }

  6051. 

  6052.   return AnalogWDMonitChannels;

  6053. #else

  6054.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)

  6055.                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));

  6056. 

  6057.   uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);

  6058. 

  6059.   /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */

  6060.   /* (parameter value LL_ADC_AWD_DISABLE).                                    */

  6061.   /* Else, the selected AWD is enabled and is monitoring a group of channels  */

  6062.   /* or a single channel.                                                     */

  6063.   if (AnalogWDMonitChannels != 0UL)

  6064.   {

  6065.     if (AWDy == LL_ADC_AWD1)

  6066.     {

  6067.       if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)

  6068.       {

  6069.         /* AWD monitoring a group of channels */

  6070.         AnalogWDMonitChannels = ((AnalogWDMonitChannels

  6071.                                   | (ADC_AWD_CR23_CHANNEL_MASK)

  6072.                                  )

  6073.                                  & (~(ADC_CFGR_AWD1CH))

  6074.                                 );

  6075.       }

  6076.       else

  6077.       {

  6078.         /* AWD monitoring a single channel */

  6079.         AnalogWDMonitChannels = (AnalogWDMonitChannels

  6080.                                  | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))

  6081.                                 );

  6082.       }

  6083.     }

  6084.     else

  6085.     {

  6086.       if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)

  6087.       {

  6088.         /* AWD monitoring a group of channels */

  6089.         AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK

  6090.                                  | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))

  6091.                                 );

  6092.       }

  6093.       else

  6094.       {

  6095.         /* AWD monitoring a single channel */

  6096.         /* AWD monitoring a group of channels */

  6097.         AnalogWDMonitChannels = (AnalogWDMonitChannels

  6098.                                  | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

  6099.                                  | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)

  6100.                                 );

  6101.       }

  6102.     }

  6103.   }

  6104. 

  6105.   return AnalogWDMonitChannels;

  6106. #endif

  6107. }

  6108. 

  6109. /**

  6110.   * @brief  Set ADC analog watchdog thresholds value of both thresholds

  6111.   *         high and low.

  6112.   * @note   If value of only one threshold high or low must be set,

  6113.   *         use function @ref LL_ADC_SetAnalogWDThresholds().

  6114.   * @note   In case of ADC resolution different of 12 bits,

  6115.   *         analog watchdog thresholds data require a specific shift.

  6116.   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().

  6117.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  6118.   *         instance:

  6119.   *         - AWD standard (instance AWD1):

  6120.   *           - channels monitored: can monitor 1 channel or all channels.

  6121.   *           - groups monitored: ADC groups regular and-or injected.

  6122.   *           - resolution: resolution is not limited (corresponds to

  6123.   *             ADC resolution configured).

  6124.   *         - AWD flexible (instances AWD2, AWD3):

  6125.   *           - channels monitored: flexible on channels monitored, selection is

  6126.   *             channel wise, from from 1 to all channels.

  6127.   *             Specificity of this analog watchdog: Multiple channels can

  6128.   *             be selected. For example:

  6129.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  6130.   *           - groups monitored: not selection possible (monitoring on both

  6131.   *             groups regular and injected).

  6132.   *             Channels selected are monitored on groups regular and injected:

  6133.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  6134.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  6135.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  6136.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  6137.   *             the 2 LSB are ignored.

  6138.   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are

  6139.   *         impacted: the comparison of analog watchdog thresholds is done on

  6140.   *         oversampling final computation (after ratio and shift application):

  6141.   *         ADC data register bitfield [15:4] (12 most significant bits).

  6142.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6143.   *         ADC state:

  6144.   *         ADC must be disabled or enabled without conversion on going

  6145.   *         on either groups regular or injected.

  6146.   * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n

  6147.   *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n

  6148.   *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n

  6149.   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n

  6150.   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n

  6151.   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds

  6152.   * @param  ADCx ADC instance

  6153.   * @param  AWDy This parameter can be one of the following values:

  6154.   *         @arg @ref LL_ADC_AWD1

  6155.   *         @arg @ref LL_ADC_AWD2 (1)

  6156.   *         @arg @ref LL_ADC_AWD3 (1)

  6157.   *

  6158.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  6159.   * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF

  6160.   * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF

  6161.   * @retval None

  6162.   */

  6163. __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,

  6164.                                                      uint32_t AWDThresholdLowValue)

  6165. {

  6166.   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */

  6167.   /* position in register and register position depending on parameter        */

  6168.   /* "AWDy".                                                                  */

  6169.   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */

  6170.   /* containing other bits reserved for other purpose.                        */

  6171. #if defined (ADC_SUPPORT_2_5_MSPS)

  6172.   /* Prevent unused argument(s) compilation warning */

  6173.   (void)(AWDy);

  6174. 

  6175.   MODIFY_REG(ADCx->TR1,

  6176.              ADC_TR1_HT1 | ADC_TR1_LT1,

  6177.              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);

  6178. #else

  6179.   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));

  6180. 

  6181.   MODIFY_REG(*preg,

  6182.              ADC_TR1_HT1 | ADC_TR1_LT1,

  6183.              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);

  6184. #endif

  6185. }

  6186. 

  6187. /**

  6188.   * @brief  Set ADC analog watchdog threshold value of threshold

  6189.   *         high or low.

  6190.   * @note   If values of both thresholds high or low must be set,

  6191.   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().

  6192.   * @note   In case of ADC resolution different of 12 bits,

  6193.   *         analog watchdog thresholds data require a specific shift.

  6194.   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().

  6195.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  6196.   *         instance:

  6197.   *         - AWD standard (instance AWD1):

  6198.   *           - channels monitored: can monitor 1 channel or all channels.

  6199.   *           - groups monitored: ADC groups regular and-or injected.

  6200.   *           - resolution: resolution is not limited (corresponds to

  6201.   *             ADC resolution configured).

  6202.   *         - AWD flexible (instances AWD2, AWD3):

  6203.   *           - channels monitored: flexible on channels monitored, selection is

  6204.   *             channel wise, from from 1 to all channels.

  6205.   *             Specificity of this analog watchdog: Multiple channels can

  6206.   *             be selected. For example:

  6207.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  6208.   *           - groups monitored: not selection possible (monitoring on both

  6209.   *             groups regular and injected).

  6210.   *             Channels selected are monitored on groups regular and injected:

  6211.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  6212.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  6213.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  6214.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  6215.   *             the 2 LSB are ignored.

  6216.   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are

  6217.   *         impacted: the comparison of analog watchdog thresholds is done on

  6218.   *         oversampling final computation (after ratio and shift application):

  6219.   *         ADC data register bitfield [15:4] (12 most significant bits).

  6220.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6221.   *         ADC state:

  6222.   *         ADC must be disabled or enabled without conversion on going

  6223.   *         on either ADC groups regular or injected.

  6224.   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n

  6225.   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n

  6226.   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n

  6227.   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n

  6228.   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n

  6229.   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds

  6230.   * @param  ADCx ADC instance

  6231.   * @param  AWDy This parameter can be one of the following values:

  6232.   *         @arg @ref LL_ADC_AWD1

  6233.   *         @arg @ref LL_ADC_AWD2 (1)

  6234.   *         @arg @ref LL_ADC_AWD3 (1)

  6235.   *

  6236.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  6237.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  6238.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  6239.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  6240.   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF

  6241.   * @retval None

  6242.   */

  6243. __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,

  6244.                                                   uint32_t AWDThresholdValue)

  6245. {

  6246.   /* Set bits with content of parameter "AWDThresholdValue" with bits         */

  6247.   /* position in register and register position depending on parameters       */

  6248.   /* "AWDThresholdsHighLow" and "AWDy".                                       */

  6249.   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */

  6250.   /* containing other bits reserved for other purpose.                        */

  6251. #if defined (ADC_SUPPORT_2_5_MSPS)

  6252.   /* Prevent unused argument(s) compilation warning */

  6253.   (void)(AWDy);

  6254. 

  6255.   MODIFY_REG(ADCx->TR1,

  6256.              AWDThresholdsHighLow,

  6257.              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));

  6258. #else

  6259.   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));

  6260. 

  6261.   MODIFY_REG(*preg,

  6262.              AWDThresholdsHighLow,

  6263.              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));

  6264. #endif

  6265. }

  6266. 

  6267. /**

  6268.   * @brief  Get ADC analog watchdog threshold value of threshold high,

  6269.   *         threshold low or raw data with ADC thresholds high and low

  6270.   *         concatenated.

  6271.   * @note   If raw data with ADC thresholds high and low is retrieved,

  6272.   *         the data of each threshold high or low can be isolated

  6273.   *         using helper macro:

  6274.   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().

  6275.   * @note   In case of ADC resolution different of 12 bits,

  6276.   *         analog watchdog thresholds data require a specific shift.

  6277.   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().

  6278.   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n

  6279.   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n

  6280.   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n

  6281.   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n

  6282.   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n

  6283.   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds

  6284.   * @param  ADCx ADC instance

  6285.   * @param  AWDy This parameter can be one of the following values:

  6286.   *         @arg @ref LL_ADC_AWD1

  6287.   *         @arg @ref LL_ADC_AWD2 (1)

  6288.   *         @arg @ref LL_ADC_AWD3 (1)

  6289.   *

  6290.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  6291.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  6292.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  6293.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  6294.   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW

  6295.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  6296.   */

  6297. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)

  6298. {

  6299. #if defined (ADC_SUPPORT_2_5_MSPS)

  6300.   /* Prevent unused argument(s) compilation warning */

  6301.   (void)(AWDy);

  6302. 

  6303.   return (uint32_t)(READ_BIT(ADCx->TR1,

  6304.                              (AWDThresholdsHighLow | ADC_TR1_LT1))

  6305.                     >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))

  6306.                    );

  6307. #else

  6308.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));

  6309. 

  6310.   return (uint32_t)(READ_BIT(*preg,

  6311.                              (AWDThresholdsHighLow | ADC_TR1_LT1))

  6312.                     >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))

  6313.                    );

  6314. #endif

  6315. }

  6316. 

  6317. /**

  6318.   * @}

  6319.   */

  6320. 

  6321. #if defined (ADC_SUPPORT_2_5_MSPS)

  6322. /* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */

  6323. #else

  6324. /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling

  6325.   * @{

  6326.   */

  6327. 

  6328. /**

  6329.   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected

  6330.   *         (availability of ADC group injected depends on STM32 families).

  6331.   * @note   If both groups regular and injected are selected,

  6332.   *         specify behavior of ADC group injected interrupting

  6333.   *         group regular: when ADC group injected is triggered,

  6334.   *         the oversampling on ADC group regular is either

  6335.   *         temporary stopped and continued, or resumed from start

  6336.   *         (oversampler buffer reset).

  6337.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6338.   *         ADC state:

  6339.   *         ADC must be disabled or enabled without conversion on going

  6340.   *         on either groups regular or injected.

  6341.   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n

  6342.   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n

  6343.   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope

  6344.   * @param  ADCx ADC instance

  6345.   * @param  OvsScope This parameter can be one of the following values:

  6346.   *         @arg @ref LL_ADC_OVS_DISABLE

  6347.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED

  6348.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED (1)

  6349.   *         @arg @ref LL_ADC_OVS_GRP_INJECTED        (1)

  6350.   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED (1)

  6351.   *

  6352.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  6353.   * @retval None

  6354.   */

  6355. __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)

  6356. {

  6357. #if defined (ADC_SUPPORT_2_5_MSPS)

  6358.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);

  6359. #else

  6360.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);

  6361. #endif

  6362. }

  6363. 

  6364. /**

  6365.   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected

  6366.   *         (availability of ADC group injected depends on STM32 families).

  6367.   * @note   If both groups regular and injected are selected,

  6368.   *         specify behavior of ADC group injected interrupting

  6369.   *         group regular: when ADC group injected is triggered,

  6370.   *         the oversampling on ADC group regular is either

  6371.   *         temporary stopped and continued, or resumed from start

  6372.   *         (oversampler buffer reset).

  6373.   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n

  6374.   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n

  6375.   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope

  6376.   * @param  ADCx ADC instance

  6377.   * @retval Returned value can be one of the following values:

  6378.   *         @arg @ref LL_ADC_OVS_DISABLE

  6379.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED

  6380.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED (1)

  6381.   *         @arg @ref LL_ADC_OVS_GRP_INJECTED        (1)

  6382.   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED (1)

  6383.   *

  6384.   *         (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.

  6385.   */

  6386. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)

  6387. {

  6388. #if defined (ADC_SUPPORT_2_5_MSPS)

  6389.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));

  6390. #else

  6391.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));

  6392. #endif

  6393. }

  6394. 

  6395. /**

  6396.   * @brief  Set ADC oversampling discontinuous mode (triggered mode)

  6397.   *         on the selected ADC group.

  6398.   * @note   Number of oversampled conversions are done either in:

  6399.   *         - continuous mode (all conversions of oversampling ratio

  6400.   *           are done from 1 trigger)

  6401.   *         - discontinuous mode (each conversion of oversampling ratio

  6402.   *           needs a trigger)

  6403.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6404.   *         ADC state:

  6405.   *         ADC must be disabled or enabled without conversion on going

  6406.   *         on group regular.

  6407.   * @note   On this STM32 serie, oversampling discontinuous mode

  6408.   *         (triggered mode) can be used only when oversampling is

  6409.   *         set on group regular only and in resumed mode.

  6410.   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont

  6411.   * @param  ADCx ADC instance

  6412.   * @param  OverSamplingDiscont This parameter can be one of the following values:

  6413.   *         @arg @ref LL_ADC_OVS_REG_CONT

  6414.   *         @arg @ref LL_ADC_OVS_REG_DISCONT

  6415.   * @retval None

  6416.   */

  6417. __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)

  6418. {

  6419. #if defined (ADC_SUPPORT_2_5_MSPS)

  6420.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);

  6421. #else

  6422.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);

  6423. #endif

  6424. }

  6425. 

  6426. /**

  6427.   * @brief  Get ADC oversampling discontinuous mode (triggered mode)

  6428.   *         on the selected ADC group.

  6429.   * @note   Number of oversampled conversions are done either in:

  6430.   *         - continuous mode (all conversions of oversampling ratio

  6431.   *           are done from 1 trigger)

  6432.   *         - discontinuous mode (each conversion of oversampling ratio

  6433.   *           needs a trigger)

  6434.   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont

  6435.   * @param  ADCx ADC instance

  6436.   * @retval Returned value can be one of the following values:

  6437.   *         @arg @ref LL_ADC_OVS_REG_CONT

  6438.   *         @arg @ref LL_ADC_OVS_REG_DISCONT

  6439.   */

  6440. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)

  6441. {

  6442. #if defined (ADC_SUPPORT_2_5_MSPS)

  6443.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));

  6444. #else

  6445.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));

  6446. #endif

  6447. }

  6448. 

  6449. /**

  6450.   * @brief  Set ADC oversampling

  6451.   *         (impacting both ADC groups regular and injected)

  6452.   * @note   This function set the 2 items of oversampling configuration:

  6453.   *         - ratio

  6454.   *         - shift

  6455.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6456.   *         ADC state:

  6457.   *         ADC must be disabled or enabled without conversion on going

  6458.   *         on either groups regular or injected.

  6459.   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n

  6460.   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift

  6461.   * @param  ADCx ADC instance

  6462.   * @param  Ratio This parameter can be one of the following values:

  6463.   *         @arg @ref LL_ADC_OVS_RATIO_2

  6464.   *         @arg @ref LL_ADC_OVS_RATIO_4

  6465.   *         @arg @ref LL_ADC_OVS_RATIO_8

  6466.   *         @arg @ref LL_ADC_OVS_RATIO_16

  6467.   *         @arg @ref LL_ADC_OVS_RATIO_32

  6468.   *         @arg @ref LL_ADC_OVS_RATIO_64

  6469.   *         @arg @ref LL_ADC_OVS_RATIO_128

  6470.   *         @arg @ref LL_ADC_OVS_RATIO_256

  6471.   * @param  Shift This parameter can be one of the following values:

  6472.   *         @arg @ref LL_ADC_OVS_SHIFT_NONE

  6473.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1

  6474.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2

  6475.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3

  6476.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4

  6477.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5

  6478.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6

  6479.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7

  6480.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8

  6481.   * @retval None

  6482.   */

  6483. __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)

  6484. {

  6485.   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));

  6486. }

  6487. 

  6488. /**

  6489.   * @brief  Get ADC oversampling ratio

  6490.   *        (impacting both ADC groups regular and injected)

  6491.   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio

  6492.   * @param  ADCx ADC instance

  6493.   * @retval Ratio This parameter can be one of the following values:

  6494.   *         @arg @ref LL_ADC_OVS_RATIO_2

  6495.   *         @arg @ref LL_ADC_OVS_RATIO_4

  6496.   *         @arg @ref LL_ADC_OVS_RATIO_8

  6497.   *         @arg @ref LL_ADC_OVS_RATIO_16

  6498.   *         @arg @ref LL_ADC_OVS_RATIO_32

  6499.   *         @arg @ref LL_ADC_OVS_RATIO_64

  6500.   *         @arg @ref LL_ADC_OVS_RATIO_128

  6501.   *         @arg @ref LL_ADC_OVS_RATIO_256

  6502.   */

  6503. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)

  6504. {

  6505.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));

  6506. }

  6507. 

  6508. /**

  6509.   * @brief  Get ADC oversampling shift

  6510.   *        (impacting both ADC groups regular and injected)

  6511.   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift

  6512.   * @param  ADCx ADC instance

  6513.   * @retval Shift This parameter can be one of the following values:

  6514.   *         @arg @ref LL_ADC_OVS_SHIFT_NONE

  6515.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1

  6516.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2

  6517.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3

  6518.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4

  6519.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5

  6520.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6

  6521.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7

  6522.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8

  6523.   */

  6524. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)

  6525. {

  6526.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));

  6527. }

  6528. 

  6529. /**

  6530.   * @}

  6531.   */

  6532. 

  6533. #endif /* ADC_SUPPORT_2_5_MSPS */

  6534. /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance

  6535.   * @{

  6536.   */

  6537. 

  6538. #if defined(ADC_SUPPORT_2_5_MSPS)

  6539. /* Feature "ADC deep power down" not available on ADC peripheral of this STM32WB device */

  6540. #else

  6541. /**

  6542.   * @brief  Put ADC instance in deep power down state.

  6543.   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down

  6544.   *         state, the internal analog calibration is lost. After exiting from

  6545.   *         deep power down, calibration must be relaunched or calibration factor

  6546.   *         (preliminarily saved) must be set back into calibration register.

  6547.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6548.   *         ADC state:

  6549.   *         ADC must be ADC disabled.

  6550.   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown

  6551.   * @param  ADCx ADC instance

  6552.   * @retval None

  6553.   */

  6554. __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)

  6555. {

  6556.   /* Note: Write register with some additional bits forced to state reset     */

  6557.   /*       instead of modifying only the selected bit for this function,      */

  6558.   /*       to not interfere with bits with HW property "rs".                  */

  6559.   MODIFY_REG(ADCx->CR,

  6560.              ADC_CR_BITS_PROPERTY_RS,

  6561.              ADC_CR_DEEPPWD);

  6562. }

  6563. 

  6564. /**

  6565.   * @brief  Disable ADC deep power down mode.

  6566.   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down

  6567.   *         state, the internal analog calibration is lost. After exiting from

  6568.   *         deep power down, calibration must be relaunched or calibration factor

  6569.   *         (preliminarily saved) must be set back into calibration register.

  6570.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6571.   *         ADC state:

  6572.   *         ADC must be ADC disabled.

  6573.   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown

  6574.   * @param  ADCx ADC instance

  6575.   * @retval None

  6576.   */

  6577. __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)

  6578. {

  6579.   /* Note: Write register with some additional bits forced to state reset     */

  6580.   /*       instead of modifying only the selected bit for this function,      */

  6581.   /*       to not interfere with bits with HW property "rs".                  */

  6582.   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));

  6583. }

  6584. 

  6585. /**

  6586.   * @brief  Get the selected ADC instance deep power down state.

  6587.   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled

  6588.   * @param  ADCx ADC instance

  6589.   * @retval 0: deep power down is disabled, 1: deep power down is enabled.

  6590.   */

  6591. __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)

  6592. {

  6593.   return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);

  6594. }

  6595. #endif /* ADC_SUPPORT_2_5_MSPS */

  6596. 

  6597. /**

  6598.   * @brief  Enable ADC instance internal voltage regulator.

  6599.   * @note   On this STM32 serie, after ADC internal voltage regulator enable,

  6600.   *         a delay for ADC internal voltage regulator stabilization

  6601.   *         is required before performing a ADC calibration or ADC enable.

  6602.   *         Refer to device datasheet, parameter tADCVREG_STUP.

  6603.   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.

  6604.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6605.   *         ADC state:

  6606.   *         ADC must be ADC disabled.

  6607.   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator

  6608.   * @param  ADCx ADC instance

  6609.   * @retval None

  6610.   */

  6611. __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)

  6612. {

  6613.   /* Note: Write register with some additional bits forced to state reset     */

  6614.   /*       instead of modifying only the selected bit for this function,      */

  6615.   /*       to not interfere with bits with HW property "rs".                  */

  6616.   MODIFY_REG(ADCx->CR,

  6617.              ADC_CR_BITS_PROPERTY_RS,

  6618.              ADC_CR_ADVREGEN);

  6619. }

  6620. 

  6621. /**

  6622.   * @brief  Disable ADC internal voltage regulator.

  6623.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6624.   *         ADC state:

  6625.   *         ADC must be ADC disabled.

  6626.   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator

  6627.   * @param  ADCx ADC instance

  6628.   * @retval None

  6629.   */

  6630. __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)

  6631. {

  6632.   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));

  6633. }

  6634. 

  6635. /**

  6636.   * @brief  Get the selected ADC instance internal voltage regulator state.

  6637.   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled

  6638.   * @param  ADCx ADC instance

  6639.   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.

  6640.   */

  6641. __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)

  6642. {

  6643.   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);

  6644. }

  6645. 

  6646. /**

  6647.   * @brief  Enable the selected ADC instance.

  6648.   * @note   On this STM32 serie, after ADC enable, a delay for

  6649.   *         ADC internal analog stabilization is required before performing a

  6650.   *         ADC conversion start.

  6651.   *         Refer to device datasheet, parameter tSTAB.

  6652.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  6653.   *         is enabled and when conversion clock is active.

  6654.   *         (not only core clock: this ADC has a dual clock domain)

  6655.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6656.   *         ADC state:

  6657.   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.

  6658.   * @rmtoll CR       ADEN           LL_ADC_Enable

  6659.   * @param  ADCx ADC instance

  6660.   * @retval None

  6661.   */

  6662. __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)

  6663. {

  6664.   /* Note: Write register with some additional bits forced to state reset     */

  6665.   /*       instead of modifying only the selected bit for this function,      */

  6666.   /*       to not interfere with bits with HW property "rs".                  */

  6667.   MODIFY_REG(ADCx->CR,

  6668.              ADC_CR_BITS_PROPERTY_RS,

  6669.              ADC_CR_ADEN);

  6670. }

  6671. 

  6672. /**

  6673.   * @brief  Disable the selected ADC instance.

  6674.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6675.   *         ADC state:

  6676.   *         ADC must be not disabled. Must be enabled without conversion on going

  6677.   *         on either groups regular or injected.

  6678.   * @rmtoll CR       ADDIS          LL_ADC_Disable

  6679.   * @param  ADCx ADC instance

  6680.   * @retval None

  6681.   */

  6682. __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)

  6683. {

  6684.   /* Note: Write register with some additional bits forced to state reset     */

  6685.   /*       instead of modifying only the selected bit for this function,      */

  6686.   /*       to not interfere with bits with HW property "rs".                  */

  6687.   MODIFY_REG(ADCx->CR,

  6688.              ADC_CR_BITS_PROPERTY_RS,

  6689.              ADC_CR_ADDIS);

  6690. }

  6691. 

  6692. /**

  6693.   * @brief  Get the selected ADC instance enable state.

  6694.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  6695.   *         is enabled and when conversion clock is active.

  6696.   *         (not only core clock: this ADC has a dual clock domain)

  6697.   * @rmtoll CR       ADEN           LL_ADC_IsEnabled

  6698.   * @param  ADCx ADC instance

  6699.   * @retval 0: ADC is disabled, 1: ADC is enabled.

  6700.   */

  6701. __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)

  6702. {

  6703.   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);

  6704. }

  6705. 

  6706. /**

  6707.   * @brief  Get the selected ADC instance disable state.

  6708.   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing

  6709.   * @param  ADCx ADC instance

  6710.   * @retval 0: no ADC disable command on going.

  6711.   */

  6712. __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)

  6713. {

  6714.   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);

  6715. }

  6716. 

  6717. #if defined (ADC_SUPPORT_2_5_MSPS)

  6718. /**

  6719.   * @brief  Start ADC calibration in the mode single-ended

  6720.   *         or differential (for devices with differential mode available).

  6721.   * @note   On this STM32 serie, a minimum number of ADC clock cycles

  6722.   *         are required between ADC end of calibration and ADC enable.

  6723.   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.

  6724.   * @note   For devices with differential mode available:

  6725.   *         Calibration of offset is specific to each of

  6726.   *         single-ended and differential modes

  6727.   *         (calibration run must be performed for each of these

  6728.   *         differential modes, if used afterwards and if the application

  6729.   *         requires their calibration).

  6730.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6731.   *         ADC state:

  6732.   *         ADC must be ADC disabled.

  6733.   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n

  6734.   *         CR       ADCALDIF       LL_ADC_StartCalibration

  6735.   * @param  ADCx ADC instance

  6736.   * @retval None

  6737.   */

  6738. __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)

  6739. {

  6740.   /* Note: Write register with some additional bits forced to state reset     */

  6741.   /*       instead of modifying only the selected bit for this function,      */

  6742.   /*       to not interfere with bits with HW property "rs".                  */

  6743.   MODIFY_REG(ADCx->CR,

  6744.              ADC_CR_BITS_PROPERTY_RS,

  6745.              ADC_CR_ADCAL);

  6746. }

  6747. #else

  6748. /**

  6749.   * @brief  Start ADC calibration in the mode single-ended

  6750.   *         or differential (for devices with differential mode available).

  6751.   * @note   On this STM32 serie, a minimum number of ADC clock cycles

  6752.   *         are required between ADC end of calibration and ADC enable.

  6753.   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.

  6754.   * @note   For devices with differential mode available:

  6755.   *         Calibration of offset is specific to each of

  6756.   *         single-ended and differential modes

  6757.   *         (calibration run must be performed for each of these

  6758.   *         differential modes, if used afterwards and if the application

  6759.   *         requires their calibration).

  6760.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6761.   *         ADC state:

  6762.   *         ADC must be ADC disabled.

  6763.   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n

  6764.   *         CR       ADCALDIF       LL_ADC_StartCalibration

  6765.   * @param  ADCx ADC instance

  6766.   * @param  SingleDiff This parameter can be one of the following values:

  6767.   *         @arg @ref LL_ADC_SINGLE_ENDED

  6768.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  6769.   * @retval None

  6770.   */

  6771. __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)

  6772. {

  6773.   /* Note: Write register with some additional bits forced to state reset     */

  6774.   /*       instead of modifying only the selected bit for this function,      */

  6775.   /*       to not interfere with bits with HW property "rs".                  */

  6776.   MODIFY_REG(ADCx->CR,

  6777.              ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,

  6778.              ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));

  6779. }

  6780. #endif /* ADC_SUPPORT_2_5_MSPS */

  6781. 

  6782. /**

  6783.   * @brief  Get ADC calibration state.

  6784.   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing

  6785.   * @param  ADCx ADC instance

  6786.   * @retval 0: calibration complete, 1: calibration in progress.

  6787.   */

  6788. __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)

  6789. {

  6790.   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);

  6791. }

  6792. 

  6793. /**

  6794.   * @}

  6795.   */

  6796. 

  6797. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular

  6798.   * @{

  6799.   */

  6800. 

  6801. /**

  6802.   * @brief  Start ADC group regular conversion.

  6803.   * @note   On this STM32 serie, this function is relevant for both

  6804.   *         internal trigger (SW start) and external trigger:

  6805.   *         - If ADC trigger has been set to software start, ADC conversion

  6806.   *           starts immediately.

  6807.   *         - If ADC trigger has been set to external trigger, ADC conversion

  6808.   *           will start at next trigger event (on the selected trigger edge)

  6809.   *           following the ADC start conversion command.

  6810.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6811.   *         ADC state:

  6812.   *         ADC must be enabled without conversion on going on group regular,

  6813.   *         without conversion stop command on going on group regular,

  6814.   *         without ADC disable command on going.

  6815.   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion

  6816.   * @param  ADCx ADC instance

  6817.   * @retval None

  6818.   */

  6819. __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)

  6820. {

  6821.   /* Note: Write register with some additional bits forced to state reset     */

  6822.   /*       instead of modifying only the selected bit for this function,      */

  6823.   /*       to not interfere with bits with HW property "rs".                  */

  6824.   MODIFY_REG(ADCx->CR,

  6825.              ADC_CR_BITS_PROPERTY_RS,

  6826.              ADC_CR_ADSTART);

  6827. }

  6828. 

  6829. /**

  6830.   * @brief  Stop ADC group regular conversion.

  6831.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6832.   *         ADC state:

  6833.   *         ADC must be enabled with conversion on going on group regular,

  6834.   *         without ADC disable command on going.

  6835.   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion

  6836.   * @param  ADCx ADC instance

  6837.   * @retval None

  6838.   */

  6839. __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)

  6840. {

  6841.   /* Note: Write register with some additional bits forced to state reset     */

  6842.   /*       instead of modifying only the selected bit for this function,      */

  6843.   /*       to not interfere with bits with HW property "rs".                  */

  6844.   MODIFY_REG(ADCx->CR,

  6845.              ADC_CR_BITS_PROPERTY_RS,

  6846.              ADC_CR_ADSTP);

  6847. }

  6848. 

  6849. /**

  6850.   * @brief  Get ADC group regular conversion state.

  6851.   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing

  6852.   * @param  ADCx ADC instance

  6853.   * @retval 0: no conversion is on going on ADC group regular.

  6854.   */

  6855. __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)

  6856. {

  6857.   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);

  6858. }

  6859. 

  6860. /**

  6861.   * @brief  Get ADC group regular command of conversion stop state

  6862.   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing

  6863.   * @param  ADCx ADC instance

  6864.   * @retval 0: no command of conversion stop is on going on ADC group regular.

  6865.   */

  6866. __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)

  6867. {

  6868.   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);

  6869. }

  6870. 

  6871. /**

  6872.   * @brief  Get ADC group regular conversion data, range fit for

  6873.   *         all ADC configurations: all ADC resolutions and

  6874.   *         all oversampling increased data width (for devices

  6875.   *         with feature oversampling).

  6876.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32

  6877.   * @param  ADCx ADC instance

  6878.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  6879.   */

  6880. __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)

  6881. {

  6882.   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  6883. }

  6884. 

  6885. /**

  6886.   * @brief  Get ADC group regular conversion data, range fit for

  6887.   *         ADC resolution 12 bits.

  6888.   * @note   For devices with feature oversampling: Oversampling

  6889.   *         can increase data width, function for extended range

  6890.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  6891.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12

  6892.   * @param  ADCx ADC instance

  6893.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  6894.   */

  6895. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)

  6896. {

  6897.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  6898. }

  6899. 

  6900. /**

  6901.   * @brief  Get ADC group regular conversion data, range fit for

  6902.   *         ADC resolution 10 bits.

  6903.   * @note   For devices with feature oversampling: Oversampling

  6904.   *         can increase data width, function for extended range

  6905.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  6906.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10

  6907.   * @param  ADCx ADC instance

  6908.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  6909.   */

  6910. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)

  6911. {

  6912.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  6913. }

  6914. 

  6915. /**

  6916.   * @brief  Get ADC group regular conversion data, range fit for

  6917.   *         ADC resolution 8 bits.

  6918.   * @note   For devices with feature oversampling: Oversampling

  6919.   *         can increase data width, function for extended range

  6920.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  6921.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8

  6922.   * @param  ADCx ADC instance

  6923.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  6924.   */

  6925. __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)

  6926. {

  6927.   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  6928. }

  6929. 

  6930. /**

  6931.   * @brief  Get ADC group regular conversion data, range fit for

  6932.   *         ADC resolution 6 bits.

  6933.   * @note   For devices with feature oversampling: Oversampling

  6934.   *         can increase data width, function for extended range

  6935.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  6936.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6

  6937.   * @param  ADCx ADC instance

  6938.   * @retval Value between Min_Data=0x00 and Max_Data=0x3F

  6939.   */

  6940. __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)

  6941. {

  6942.   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  6943. }

  6944. 

  6945. /**

  6946.   * @}

  6947.   */

  6948. 

  6949. #if defined (ADC_SUPPORT_2_5_MSPS)

  6950. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  6951. #else

  6952. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected

  6953.   * @{

  6954.   */

  6955. 

  6956. /**

  6957.   * @brief  Start ADC group injected conversion.

  6958.   * @note   On this STM32 serie, this function is relevant for both

  6959.   *         internal trigger (SW start) and external trigger:

  6960.   *         - If ADC trigger has been set to software start, ADC conversion

  6961.   *           starts immediately.

  6962.   *         - If ADC trigger has been set to external trigger, ADC conversion

  6963.   *           will start at next trigger event (on the selected trigger edge)

  6964.   *           following the ADC start conversion command.

  6965.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6966.   *         ADC state:

  6967.   *         ADC must be enabled without conversion on going on group injected,

  6968.   *         without conversion stop command on going on group injected,

  6969.   *         without ADC disable command on going.

  6970.   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion

  6971.   * @param  ADCx ADC instance

  6972.   * @retval None

  6973.   */

  6974. __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)

  6975. {

  6976.   /* Note: Write register with some additional bits forced to state reset     */

  6977.   /*       instead of modifying only the selected bit for this function,      */

  6978.   /*       to not interfere with bits with HW property "rs".                  */

  6979.   MODIFY_REG(ADCx->CR,

  6980.              ADC_CR_BITS_PROPERTY_RS,

  6981.              ADC_CR_JADSTART);

  6982. }

  6983. 

  6984. /**

  6985.   * @brief  Stop ADC group injected conversion.

  6986.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6987.   *         ADC state:

  6988.   *         ADC must be enabled with conversion on going on group injected,

  6989.   *         without ADC disable command on going.

  6990.   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion

  6991.   * @param  ADCx ADC instance

  6992.   * @retval None

  6993.   */

  6994. __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)

  6995. {

  6996.   /* Note: Write register with some additional bits forced to state reset     */

  6997.   /*       instead of modifying only the selected bit for this function,      */

  6998.   /*       to not interfere with bits with HW property "rs".                  */

  6999.   MODIFY_REG(ADCx->CR,

  7000.              ADC_CR_BITS_PROPERTY_RS,

  7001.              ADC_CR_JADSTP);

  7002. }

  7003. 

  7004. /**

  7005.   * @brief  Get ADC group injected conversion state.

  7006.   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing

  7007.   * @param  ADCx ADC instance

  7008.   * @retval 0: no conversion is on going on ADC group injected.

  7009.   */

  7010. __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)

  7011. {

  7012.   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);

  7013. }

  7014. 

  7015. /**

  7016.   * @brief  Get ADC group injected command of conversion stop state

  7017.   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing

  7018.   * @param  ADCx ADC instance

  7019.   * @retval 0: no command of conversion stop is on going on ADC group injected.

  7020.   */

  7021. __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)

  7022. {

  7023.   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);

  7024. }

  7025. 

  7026. /**

  7027.   * @brief  Get ADC group injected conversion data, range fit for

  7028.   *         all ADC configurations: all ADC resolutions and

  7029.   *         all oversampling increased data width (for devices

  7030.   *         with feature oversampling).

  7031.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n

  7032.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n

  7033.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n

  7034.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32

  7035.   * @param  ADCx ADC instance

  7036.   * @param  Rank This parameter can be one of the following values:

  7037.   *         @arg @ref LL_ADC_INJ_RANK_1

  7038.   *         @arg @ref LL_ADC_INJ_RANK_2

  7039.   *         @arg @ref LL_ADC_INJ_RANK_3

  7040.   *         @arg @ref LL_ADC_INJ_RANK_4

  7041.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  7042.   */

  7043. __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)

  7044. {

  7045.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  7046. 

  7047.   return (uint32_t)(READ_BIT(*preg,

  7048.                              ADC_JDR1_JDATA)

  7049.                    );

  7050. }

  7051. 

  7052. /**

  7053.   * @brief  Get ADC group injected conversion data, range fit for

  7054.   *         ADC resolution 12 bits.

  7055.   * @note   For devices with feature oversampling: Oversampling

  7056.   *         can increase data width, function for extended range

  7057.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  7058.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n

  7059.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n

  7060.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n

  7061.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12

  7062.   * @param  ADCx ADC instance

  7063.   * @param  Rank This parameter can be one of the following values:

  7064.   *         @arg @ref LL_ADC_INJ_RANK_1

  7065.   *         @arg @ref LL_ADC_INJ_RANK_2

  7066.   *         @arg @ref LL_ADC_INJ_RANK_3

  7067.   *         @arg @ref LL_ADC_INJ_RANK_4

  7068.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  7069.   */

  7070. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)

  7071. {

  7072.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  7073. 

  7074.   return (uint16_t)(READ_BIT(*preg,

  7075.                              ADC_JDR1_JDATA)

  7076.                    );

  7077. }

  7078. 

  7079. /**

  7080.   * @brief  Get ADC group injected conversion data, range fit for

  7081.   *         ADC resolution 10 bits.

  7082.   * @note   For devices with feature oversampling: Oversampling

  7083.   *         can increase data width, function for extended range

  7084.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  7085.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n

  7086.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n

  7087.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n

  7088.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10

  7089.   * @param  ADCx ADC instance

  7090.   * @param  Rank This parameter can be one of the following values:

  7091.   *         @arg @ref LL_ADC_INJ_RANK_1

  7092.   *         @arg @ref LL_ADC_INJ_RANK_2

  7093.   *         @arg @ref LL_ADC_INJ_RANK_3

  7094.   *         @arg @ref LL_ADC_INJ_RANK_4

  7095.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  7096.   */

  7097. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)

  7098. {

  7099.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  7100. 

  7101.   return (uint16_t)(READ_BIT(*preg,

  7102.                              ADC_JDR1_JDATA)

  7103.                    );

  7104. }

  7105. 

  7106. /**

  7107.   * @brief  Get ADC group injected conversion data, range fit for

  7108.   *         ADC resolution 8 bits.

  7109.   * @note   For devices with feature oversampling: Oversampling

  7110.   *         can increase data width, function for extended range

  7111.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  7112.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n

  7113.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n

  7114.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n

  7115.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8

  7116.   * @param  ADCx ADC instance

  7117.   * @param  Rank This parameter can be one of the following values:

  7118.   *         @arg @ref LL_ADC_INJ_RANK_1

  7119.   *         @arg @ref LL_ADC_INJ_RANK_2

  7120.   *         @arg @ref LL_ADC_INJ_RANK_3

  7121.   *         @arg @ref LL_ADC_INJ_RANK_4

  7122.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  7123.   */

  7124. __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)

  7125. {

  7126.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  7127. 

  7128.   return (uint8_t)(READ_BIT(*preg,

  7129.                             ADC_JDR1_JDATA)

  7130.                   );

  7131. }

  7132. 

  7133. /**

  7134.   * @brief  Get ADC group injected conversion data, range fit for

  7135.   *         ADC resolution 6 bits.

  7136.   * @note   For devices with feature oversampling: Oversampling

  7137.   *         can increase data width, function for extended range

  7138.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  7139.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n

  7140.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n

  7141.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n

  7142.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6

  7143.   * @param  ADCx ADC instance

  7144.   * @param  Rank This parameter can be one of the following values:

  7145.   *         @arg @ref LL_ADC_INJ_RANK_1

  7146.   *         @arg @ref LL_ADC_INJ_RANK_2

  7147.   *         @arg @ref LL_ADC_INJ_RANK_3

  7148.   *         @arg @ref LL_ADC_INJ_RANK_4

  7149.   * @retval Value between Min_Data=0x00 and Max_Data=0x3F

  7150.   */

  7151. __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)

  7152. {

  7153.   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  7154. 

  7155.   return (uint8_t)(READ_BIT(*preg,

  7156.                             ADC_JDR1_JDATA)

  7157.                   );

  7158. }

  7159. 

  7160. /**

  7161.   * @}

  7162.   */

  7163. 

  7164. #endif /* ADC_SUPPORT_2_5_MSPS */

  7165. /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management

  7166.   * @{

  7167.   */

  7168. 

  7169. /**

  7170.   * @brief  Get flag ADC ready.

  7171.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  7172.   *         is enabled and when conversion clock is active.

  7173.   *         (not only core clock: this ADC has a dual clock domain)

  7174.   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY

  7175.   * @param  ADCx ADC instance

  7176.   * @retval State of bit (1 or 0).

  7177.   */

  7178. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)

  7179. {

  7180.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);

  7181. }

  7182. 

  7183. #if defined(ADC_SUPPORT_2_5_MSPS)

  7184. /**

  7185.   * @brief  Get flag ADC channel configuration ready.

  7186.   * @note   Duration of ADC channel configuration ready: CCRDY handshake

  7187.   *         requires 1APB + 2 ADC + 3 APB cycles after the channel configuration

  7188.   *         has been changed.

  7189.   * @rmtoll ISR      CCRDY          LL_ADC_IsActiveFlag_CCRDY

  7190.   * @param  ADCx ADC instance

  7191.   * @retval State of bit (1 or 0).

  7192.   */

  7193. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx)

  7194. {

  7195.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);

  7196. }

  7197. 

  7198. #else

  7199. #endif

  7200. /**

  7201.   * @brief  Get flag ADC group regular end of unitary conversion.

  7202.   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC

  7203.   * @param  ADCx ADC instance

  7204.   * @retval State of bit (1 or 0).

  7205.   */

  7206. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)

  7207. {

  7208.   return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);

  7209. }

  7210. 

  7211. /**

  7212.   * @brief  Get flag ADC group regular end of sequence conversions.

  7213.   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS

  7214.   * @param  ADCx ADC instance

  7215.   * @retval State of bit (1 or 0).

  7216.   */

  7217. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)

  7218. {

  7219.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);

  7220. }

  7221. 

  7222. /**

  7223.   * @brief  Get flag ADC group regular overrun.

  7224.   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR

  7225.   * @param  ADCx ADC instance

  7226.   * @retval State of bit (1 or 0).

  7227.   */

  7228. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)

  7229. {

  7230.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);

  7231. }

  7232. 

  7233. /**

  7234.   * @brief  Get flag ADC group regular end of sampling phase.

  7235.   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP

  7236.   * @param  ADCx ADC instance

  7237.   * @retval State of bit (1 or 0).

  7238.   */

  7239. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)

  7240. {

  7241.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);

  7242. }

  7243. 

  7244. #if defined (ADC_SUPPORT_2_5_MSPS)

  7245. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  7246. #else

  7247. /**

  7248.   * @brief  Get flag ADC group injected end of unitary conversion.

  7249.   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC

  7250.   * @param  ADCx ADC instance

  7251.   * @retval State of bit (1 or 0).

  7252.   */

  7253. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)

  7254. {

  7255.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);

  7256. }

  7257. 

  7258. /**

  7259.   * @brief  Get flag ADC group injected end of sequence conversions.

  7260.   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS

  7261.   * @param  ADCx ADC instance

  7262.   * @retval State of bit (1 or 0).

  7263.   */

  7264. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)

  7265. {

  7266.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);

  7267. }

  7268. 

  7269. /**

  7270.   * @brief  Get flag ADC group injected contexts queue overflow.

  7271.   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF

  7272.   * @param  ADCx ADC instance

  7273.   * @retval State of bit (1 or 0).

  7274.   */

  7275. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)

  7276. {

  7277.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);

  7278. }

  7279. 

  7280. #endif /* ADC_SUPPORT_2_5_MSPS */

  7281. /**

  7282.   * @brief  Get flag ADC analog watchdog 1 flag

  7283.   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1

  7284.   * @param  ADCx ADC instance

  7285.   * @retval State of bit (1 or 0).

  7286.   */

  7287. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)

  7288. {

  7289.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);

  7290. }

  7291. 

  7292. /**

  7293.   * @brief  Get flag ADC analog watchdog 2.

  7294.   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2

  7295.   * @param  ADCx ADC instance

  7296.   * @retval State of bit (1 or 0).

  7297.   */

  7298. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)

  7299. {

  7300.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);

  7301. }

  7302. 

  7303. /**

  7304.   * @brief  Get flag ADC analog watchdog 3.

  7305.   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3

  7306.   * @param  ADCx ADC instance

  7307.   * @retval State of bit (1 or 0).

  7308.   */

  7309. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)

  7310. {

  7311.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);

  7312. }

  7313. 

  7314. #if defined(ADC_SUPPORT_2_5_MSPS)

  7315. /**

  7316.   * @brief  Get flag ADC end of calibration.

  7317.   * @rmtoll ISR      EOCAL          LL_ADC_IsActiveFlag_EOCAL

  7318.   * @param  ADCx ADC instance

  7319.   * @retval State of bit (1 or 0).

  7320.   */

  7321. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)

  7322. {

  7323.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);

  7324. }

  7325. 

  7326. #endif

  7327. /**

  7328.   * @brief  Clear flag ADC ready.

  7329.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  7330.   *         is enabled and when conversion clock is active.

  7331.   *         (not only core clock: this ADC has a dual clock domain)

  7332.   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY

  7333.   * @param  ADCx ADC instance

  7334.   * @retval None

  7335.   */

  7336. __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)

  7337. {

  7338.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);

  7339. }

  7340. 

  7341. #if defined(ADC_SUPPORT_2_5_MSPS)

  7342. /**

  7343.   * @brief  Clear flag ADC channel configuration ready.

  7344.   * @rmtoll ISR      CCRDY          LL_ADC_ClearFlag_CCRDY

  7345.   * @param  ADCx ADC instance

  7346.   * @retval State of bit (1 or 0).

  7347.   */

  7348. __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)

  7349. {

  7350.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);

  7351. }

  7352. 

  7353. #else

  7354. #endif

  7355. /**

  7356.   * @brief  Clear flag ADC group regular end of unitary conversion.

  7357.   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC

  7358.   * @param  ADCx ADC instance

  7359.   * @retval None

  7360.   */

  7361. __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)

  7362. {

  7363.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);

  7364. }

  7365. 

  7366. /**

  7367.   * @brief  Clear flag ADC group regular end of sequence conversions.

  7368.   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS

  7369.   * @param  ADCx ADC instance

  7370.   * @retval None

  7371.   */

  7372. __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)

  7373. {

  7374.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);

  7375. }

  7376. 

  7377. /**

  7378.   * @brief  Clear flag ADC group regular overrun.

  7379.   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR

  7380.   * @param  ADCx ADC instance

  7381.   * @retval None

  7382.   */

  7383. __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)

  7384. {

  7385.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);

  7386. }

  7387. 

  7388. /**

  7389.   * @brief  Clear flag ADC group regular end of sampling phase.

  7390.   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP

  7391.   * @param  ADCx ADC instance

  7392.   * @retval None

  7393.   */

  7394. __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)

  7395. {

  7396.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);

  7397. }

  7398. 

  7399. #if defined (ADC_SUPPORT_2_5_MSPS)

  7400. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  7401. #else

  7402. /**

  7403.   * @brief  Clear flag ADC group injected end of unitary conversion.

  7404.   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC

  7405.   * @param  ADCx ADC instance

  7406.   * @retval None

  7407.   */

  7408. __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)

  7409. {

  7410.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);

  7411. }

  7412. 

  7413. /**

  7414.   * @brief  Clear flag ADC group injected end of sequence conversions.

  7415.   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS

  7416.   * @param  ADCx ADC instance

  7417.   * @retval None

  7418.   */

  7419. __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)

  7420. {

  7421.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);

  7422. }

  7423. 

  7424. /**

  7425.   * @brief  Clear flag ADC group injected contexts queue overflow.

  7426.   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF

  7427.   * @param  ADCx ADC instance

  7428.   * @retval None

  7429.   */

  7430. __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)

  7431. {

  7432.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);

  7433. }

  7434. 

  7435. #endif /* ADC_SUPPORT_2_5_MSPS */

  7436. /**

  7437.   * @brief  Clear flag ADC analog watchdog 1.

  7438.   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1

  7439.   * @param  ADCx ADC instance

  7440.   * @retval None

  7441.   */

  7442. __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)

  7443. {

  7444.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);

  7445. }

  7446. 

  7447. /**

  7448.   * @brief  Clear flag ADC analog watchdog 2.

  7449.   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2

  7450.   * @param  ADCx ADC instance

  7451.   * @retval None

  7452.   */

  7453. __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)

  7454. {

  7455.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);

  7456. }

  7457. 

  7458. /**

  7459.   * @brief  Clear flag ADC analog watchdog 3.

  7460.   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3

  7461.   * @param  ADCx ADC instance

  7462.   * @retval None

  7463.   */

  7464. __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)

  7465. {

  7466.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);

  7467. }

  7468. 

  7469. #if defined(ADC_SUPPORT_2_5_MSPS)

  7470. /**

  7471.   * @brief  Clear flag ADC end of calibration.

  7472.   * @rmtoll ISR      EOCAL          LL_ADC_ClearFlag_EOCAL

  7473.   * @param  ADCx ADC instance

  7474.   * @retval None

  7475.   */

  7476. __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)

  7477. {

  7478.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);

  7479. }

  7480. 

  7481. #endif

  7482. /**

  7483.   * @}

  7484.   */

  7485. 

  7486. /** @defgroup ADC_LL_EF_IT_Management ADC IT management

  7487.   * @{

  7488.   */

  7489. 

  7490. /**

  7491.   * @brief  Enable ADC ready.

  7492.   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY

  7493.   * @param  ADCx ADC instance

  7494.   * @retval None

  7495.   */

  7496. __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)

  7497. {

  7498.   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);

  7499. }

  7500. 

  7501. #if defined(ADC_SUPPORT_2_5_MSPS)

  7502. /**

  7503.   * @brief  Enable interruption ADC channel configuration ready.

  7504.   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_CCRDY

  7505.   * @param  ADCx ADC instance

  7506.   * @retval State of bit (1 or 0).

  7507.   */

  7508. __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)

  7509. {

  7510.   SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);

  7511. }

  7512. 

  7513. #else

  7514. #endif

  7515. /**

  7516.   * @brief  Enable interruption ADC group regular end of unitary conversion.

  7517.   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC

  7518.   * @param  ADCx ADC instance

  7519.   * @retval None

  7520.   */

  7521. __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)

  7522. {

  7523.   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);

  7524. }

  7525. 

  7526. /**

  7527.   * @brief  Enable interruption ADC group regular end of sequence conversions.

  7528.   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS

  7529.   * @param  ADCx ADC instance

  7530.   * @retval None

  7531.   */

  7532. __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)

  7533. {

  7534.   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);

  7535. }

  7536. 

  7537. /**

  7538.   * @brief  Enable ADC group regular interruption overrun.

  7539.   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR

  7540.   * @param  ADCx ADC instance

  7541.   * @retval None

  7542.   */

  7543. __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)

  7544. {

  7545.   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);

  7546. }

  7547. 

  7548. /**

  7549.   * @brief  Enable interruption ADC group regular end of sampling.

  7550.   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP

  7551.   * @param  ADCx ADC instance

  7552.   * @retval None

  7553.   */

  7554. __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)

  7555. {

  7556.   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);

  7557. }

  7558. 

  7559. #if defined (ADC_SUPPORT_2_5_MSPS)

  7560. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  7561. #else

  7562. /**

  7563.   * @brief  Enable interruption ADC group injected end of unitary conversion.

  7564.   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC

  7565.   * @param  ADCx ADC instance

  7566.   * @retval None

  7567.   */

  7568. __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)

  7569. {

  7570.   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);

  7571. }

  7572. 

  7573. /**

  7574.   * @brief  Enable interruption ADC group injected end of sequence conversions.

  7575.   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS

  7576.   * @param  ADCx ADC instance

  7577.   * @retval None

  7578.   */

  7579. __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)

  7580. {

  7581.   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);

  7582. }

  7583. 

  7584. /**

  7585.   * @brief  Enable interruption ADC group injected context queue overflow.

  7586.   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF

  7587.   * @param  ADCx ADC instance

  7588.   * @retval None

  7589.   */

  7590. __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)

  7591. {

  7592.   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);

  7593. }

  7594. 

  7595. #endif /* ADC_SUPPORT_2_5_MSPS */

  7596. /**

  7597.   * @brief  Enable interruption ADC analog watchdog 1.

  7598.   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1

  7599.   * @param  ADCx ADC instance

  7600.   * @retval None

  7601.   */

  7602. __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)

  7603. {

  7604.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);

  7605. }

  7606. 

  7607. /**

  7608.   * @brief  Enable interruption ADC analog watchdog 2.

  7609.   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2

  7610.   * @param  ADCx ADC instance

  7611.   * @retval None

  7612.   */

  7613. __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)

  7614. {

  7615.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);

  7616. }

  7617. 

  7618. /**

  7619.   * @brief  Enable interruption ADC analog watchdog 3.

  7620.   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3

  7621.   * @param  ADCx ADC instance

  7622.   * @retval None

  7623.   */

  7624. __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)

  7625. {

  7626.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);

  7627. }

  7628. 

  7629. #if defined(ADC_SUPPORT_2_5_MSPS)

  7630. /**

  7631.   * @brief  Enable interruption ADC end of calibration.

  7632.   * @rmtoll IER      EOCALIE        LL_ADC_EnableIT_EOCAL

  7633.   * @param  ADCx ADC instance

  7634.   * @retval None

  7635.   */

  7636. __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)

  7637. {

  7638.   SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);

  7639. }

  7640. 

  7641. #endif

  7642. /**

  7643.   * @brief  Disable interruption ADC ready.

  7644.   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY

  7645.   * @param  ADCx ADC instance

  7646.   * @retval None

  7647.   */

  7648. __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)

  7649. {

  7650.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);

  7651. }

  7652. 

  7653. #if defined(ADC_SUPPORT_2_5_MSPS)

  7654. /**

  7655.   * @brief  Disable interruption ADC channel configuration ready.

  7656.   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_CCRDY

  7657.   * @param  ADCx ADC instance

  7658.   * @retval State of bit (1 or 0).

  7659.   */

  7660. __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)

  7661. {

  7662.   CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);

  7663. }

  7664. 

  7665. #else

  7666. #endif

  7667. /**

  7668.   * @brief  Disable interruption ADC group regular end of unitary conversion.

  7669.   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC

  7670.   * @param  ADCx ADC instance

  7671.   * @retval None

  7672.   */

  7673. __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)

  7674. {

  7675.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);

  7676. }

  7677. 

  7678. /**

  7679.   * @brief  Disable interruption ADC group regular end of sequence conversions.

  7680.   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS

  7681.   * @param  ADCx ADC instance

  7682.   * @retval None

  7683.   */

  7684. __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)

  7685. {

  7686.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);

  7687. }

  7688. 

  7689. /**

  7690.   * @brief  Disable interruption ADC group regular overrun.

  7691.   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR

  7692.   * @param  ADCx ADC instance

  7693.   * @retval None

  7694.   */

  7695. __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)

  7696. {

  7697.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);

  7698. }

  7699. 

  7700. /**

  7701.   * @brief  Disable interruption ADC group regular end of sampling.

  7702.   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP

  7703.   * @param  ADCx ADC instance

  7704.   * @retval None

  7705.   */

  7706. __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)

  7707. {

  7708.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);

  7709. }

  7710. 

  7711. #if defined (ADC_SUPPORT_2_5_MSPS)

  7712. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  7713. #else

  7714. /**

  7715.   * @brief  Disable interruption ADC group regular end of unitary conversion.

  7716.   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC

  7717.   * @param  ADCx ADC instance

  7718.   * @retval None

  7719.   */

  7720. __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)

  7721. {

  7722.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);

  7723. }

  7724. 

  7725. /**

  7726.   * @brief  Disable interruption ADC group injected end of sequence conversions.

  7727.   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS

  7728.   * @param  ADCx ADC instance

  7729.   * @retval None

  7730.   */

  7731. __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)

  7732. {

  7733.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);

  7734. }

  7735. 

  7736. /**

  7737.   * @brief  Disable interruption ADC group injected context queue overflow.

  7738.   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF

  7739.   * @param  ADCx ADC instance

  7740.   * @retval None

  7741.   */

  7742. __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)

  7743. {

  7744.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);

  7745. }

  7746. 

  7747. #endif /* ADC_SUPPORT_2_5_MSPS */

  7748. /**

  7749.   * @brief  Disable interruption ADC analog watchdog 1.

  7750.   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1

  7751.   * @param  ADCx ADC instance

  7752.   * @retval None

  7753.   */

  7754. __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)

  7755. {

  7756.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);

  7757. }

  7758. 

  7759. /**

  7760.   * @brief  Disable interruption ADC analog watchdog 2.

  7761.   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2

  7762.   * @param  ADCx ADC instance

  7763.   * @retval None

  7764.   */

  7765. __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)

  7766. {

  7767.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);

  7768. }

  7769. 

  7770. /**

  7771.   * @brief  Disable interruption ADC analog watchdog 3.

  7772.   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3

  7773.   * @param  ADCx ADC instance

  7774.   * @retval None

  7775.   */

  7776. __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)

  7777. {

  7778.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);

  7779. }

  7780. 

  7781. #if defined(ADC_SUPPORT_2_5_MSPS)

  7782. /**

  7783.   * @brief  Disable interruption ADC end of calibration.

  7784.   * @rmtoll IER      EOCALIE        LL_ADC_DisableIT_EOCAL

  7785.   * @param  ADCx ADC instance

  7786.   * @retval None

  7787.   */

  7788. __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)

  7789. {

  7790.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);

  7791. }

  7792. 

  7793. #endif

  7794. /**

  7795.   * @brief  Get state of interruption ADC ready

  7796.   *         (0: interrupt disabled, 1: interrupt enabled).

  7797.   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY

  7798.   * @param  ADCx ADC instance

  7799.   * @retval State of bit (1 or 0).

  7800.   */

  7801. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)

  7802. {

  7803.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);

  7804. }

  7805. 

  7806. #if defined(ADC_SUPPORT_2_5_MSPS)

  7807. /**

  7808.   * @brief  Get state of interruption ADC channel configuration ready.

  7809.   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_CCRDY

  7810.   * @param  ADCx ADC instance

  7811.   * @retval State of bit (1 or 0).

  7812.   */

  7813. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx)

  7814. {

  7815.   return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);

  7816. }

  7817. 

  7818. #else

  7819. #endif

  7820. /**

  7821.   * @brief  Get state of interruption ADC group regular end of unitary conversion

  7822.   *         (0: interrupt disabled, 1: interrupt enabled).

  7823.   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC

  7824.   * @param  ADCx ADC instance

  7825.   * @retval State of bit (1 or 0).

  7826.   */

  7827. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)

  7828. {

  7829.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);

  7830. }

  7831. 

  7832. /**

  7833.   * @brief  Get state of interruption ADC group regular end of sequence conversions

  7834.   *         (0: interrupt disabled, 1: interrupt enabled).

  7835.   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS

  7836.   * @param  ADCx ADC instance

  7837.   * @retval State of bit (1 or 0).

  7838.   */

  7839. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)

  7840. {

  7841.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);

  7842. }

  7843. 

  7844. /**

  7845.   * @brief  Get state of interruption ADC group regular overrun

  7846.   *         (0: interrupt disabled, 1: interrupt enabled).

  7847.   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR

  7848.   * @param  ADCx ADC instance

  7849.   * @retval State of bit (1 or 0).

  7850.   */

  7851. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)

  7852. {

  7853.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);

  7854. }

  7855. 

  7856. /**

  7857.   * @brief  Get state of interruption ADC group regular end of sampling

  7858.   *         (0: interrupt disabled, 1: interrupt enabled).

  7859.   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP

  7860.   * @param  ADCx ADC instance

  7861.   * @retval State of bit (1 or 0).

  7862.   */

  7863. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)

  7864. {

  7865.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);

  7866. }

  7867. 

  7868. #if defined (ADC_SUPPORT_2_5_MSPS)

  7869. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  7870. #else

  7871. /**

  7872.   * @brief  Get state of interruption ADC group injected end of unitary conversion

  7873.   *         (0: interrupt disabled, 1: interrupt enabled).

  7874.   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC

  7875.   * @param  ADCx ADC instance

  7876.   * @retval State of bit (1 or 0).

  7877.   */

  7878. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)

  7879. {

  7880.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);

  7881. }

  7882. 

  7883. /**

  7884.   * @brief  Get state of interruption ADC group injected end of sequence conversions

  7885.   *         (0: interrupt disabled, 1: interrupt enabled).

  7886.   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS

  7887.   * @param  ADCx ADC instance

  7888.   * @retval State of bit (1 or 0).

  7889.   */

  7890. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)

  7891. {

  7892.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);

  7893. }

  7894. 

  7895. /**

  7896.   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state

  7897.   *         (0: interrupt disabled, 1: interrupt enabled).

  7898.   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF

  7899.   * @param  ADCx ADC instance

  7900.   * @retval State of bit (1 or 0).

  7901.   */

  7902. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)

  7903. {

  7904.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);

  7905. }

  7906. 

  7907. #endif /* ADC_SUPPORT_2_5_MSPS */

  7908. /**

  7909.   * @brief  Get state of interruption ADC analog watchdog 1

  7910.   *         (0: interrupt disabled, 1: interrupt enabled).

  7911.   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1

  7912.   * @param  ADCx ADC instance

  7913.   * @retval State of bit (1 or 0).

  7914.   */

  7915. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)

  7916. {

  7917.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);

  7918. }

  7919. 

  7920. /**

  7921.   * @brief  Get state of interruption Get ADC analog watchdog 2

  7922.   *         (0: interrupt disabled, 1: interrupt enabled).

  7923.   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2

  7924.   * @param  ADCx ADC instance

  7925.   * @retval State of bit (1 or 0).

  7926.   */

  7927. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)

  7928. {

  7929.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);

  7930. }

  7931. 

  7932. /**

  7933.   * @brief  Get state of interruption Get ADC analog watchdog 3

  7934.   *         (0: interrupt disabled, 1: interrupt enabled).

  7935.   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3

  7936.   * @param  ADCx ADC instance

  7937.   * @retval State of bit (1 or 0).

  7938.   */

  7939. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)

  7940. {

  7941.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);

  7942. }

  7943. 

  7944. #if defined(ADC_SUPPORT_2_5_MSPS)

  7945. /**

  7946.   * @brief  Get state of interruption ADC end of calibration

  7947.   *         (0: interrupt disabled, 1: interrupt enabled).

  7948.   * @rmtoll IER      EOCALIE        LL_ADC_IsEnabledIT_EOCAL

  7949.   * @param  ADCx ADC instance

  7950.   * @retval State of bit (1 or 0).

  7951.   */

  7952. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)

  7953. {

  7954.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);

  7955. }

  7956. 

  7957. #endif

  7958. /**

  7959.   * @}

  7960.   */

  7961. 

  7962. #if defined(USE_FULL_LL_DRIVER)

  7963. /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions

  7964.   * @{

  7965.   */

  7966. 

  7967. /* Initialization of some features of ADC common parameters and multimode */

  7968. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);

  7969. ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  7970. void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  7971. 

  7972. /* De-initialization of ADC instance, ADC group regular and ADC group injected */

  7973. /* (availability of ADC group injected depends on STM32 families) */

  7974. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);

  7975. 

  7976. /* Initialization of some features of ADC instance */

  7977. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);

  7978. void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);

  7979. 

  7980. /* Initialization of some features of ADC instance and ADC group regular */

  7981. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  7982. void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  7983. 

  7984. #if defined (ADC_SUPPORT_2_5_MSPS)

  7985. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */

  7986. #else

  7987. /* Initialization of some features of ADC instance and ADC group injected */

  7988. ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  7989. void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  7990. 

  7991. #endif

  7992. /**

  7993.   * @}

  7994.   */

  7995. #endif /* USE_FULL_LL_DRIVER */

  7996. 

  7997. /**

  7998.   * @}

  7999.   */

  8000. 

  8001. /**

  8002.   * @}

  8003.   */

  8004. 

  8005. #endif /* ADC1 */

  8006. 

  8007. /**

  8008.   * @}

  8009.   */

  8010. 

  8011. #ifdef __cplusplus

  8012. }

  8013. #endif

  8014. 

  8015. #endif /* STM32WBxx_LL_ADC_H */

  8016. 

  8017. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/