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stm32lib/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32wbxx_ll_bus.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of BUS LL module.

  6. 

  7.   @verbatim

  8.                       ##### RCC Limitations #####

  9.   ==============================================================================

  10.     [..]

  11.       A delay between an RCC peripheral clock enable and the effective peripheral

  12.       enabling should be taken into account in order to manage the peripheral read/write

  13.       from/to registers.

  14.       (+) This delay depends on the peripheral mapping.

  15.         (++) AHB & APB peripherals, 1 dummy read is necessary

  16. 

  17.     [..]

  18.       Workarounds:

  19.       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been

  20.           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

  21. 

  22.   @endverbatim

  23.   ******************************************************************************

  24.   * @attention

  25.   *

  26.   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

  27.   * All rights reserved.</center></h2>

  28.   *

  29.   * This software component is licensed by ST under BSD 3-Clause license,

  30.   * the "License"; You may not use this file except in compliance with the

  31.   * License. You may obtain a copy of the License at:

  32.   *                        opensource.org/licenses/BSD-3-Clause

  33.   *

  34.   ******************************************************************************

  35.   */

  36. 

  37. /* Define to prevent recursive inclusion -------------------------------------*/

  38. #ifndef STM32WBxx_LL_BUS_H

  39. #define STM32WBxx_LL_BUS_H

  40. 

  41. #ifdef __cplusplus

  42. extern "C" {

  43. #endif

  44. 

  45. /* Includes ------------------------------------------------------------------*/

  46. #include "stm32wbxx.h"

  47. 

  48. /** @addtogroup STM32WBxx_LL_Driver

  49.   * @{

  50.   */

  51. 

  52. #if defined(RCC)

  53. 

  54. /** @defgroup BUS_LL BUS

  55.   * @{

  56.   */

  57. 

  58. /* Private types -------------------------------------------------------------*/

  59. /* Private variables ---------------------------------------------------------*/

  60. 

  61. /* Private constants ---------------------------------------------------------*/

  62. 

  63. /* Private macros ------------------------------------------------------------*/

  64. 

  65. /* Exported types ------------------------------------------------------------*/

  66. 

  67. /* Exported constants --------------------------------------------------------*/

  68. /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants

  69.   * @{

  70.   */

  71. 

  72. /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH

  73.   * @{

  74.   */

  75. #define LL_AHB1_GRP1_PERIPH_ALL            (0xFFFFFFFFU)

  76. 

  77. #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN

  78. #if defined(DMA2)

  79. #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN

  80. #endif

  81. #define LL_AHB1_GRP1_PERIPH_DMAMUX1        RCC_AHB1ENR_DMAMUX1EN

  82. #define LL_AHB1_GRP1_PERIPH_SRAM1          RCC_AHB1SMENR_SRAM1SMEN

  83. #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN

  84. #if defined(TSC)

  85. #define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHB1ENR_TSCEN

  86. #endif

  87. /**

  88.   * @}

  89.   */

  90. 

  91. /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH

  92.   * @{

  93.   */

  94. #define LL_AHB2_GRP1_PERIPH_ALL            (0xFFFFFFFFU)

  95. 

  96. #define LL_AHB2_GRP1_PERIPH_GPIOA          RCC_AHB2ENR_GPIOAEN

  97. #define LL_AHB2_GRP1_PERIPH_GPIOB          RCC_AHB2ENR_GPIOBEN

  98. #define LL_AHB2_GRP1_PERIPH_GPIOC          RCC_AHB2ENR_GPIOCEN

  99. #if defined(GPIOD)

  100. #define LL_AHB2_GRP1_PERIPH_GPIOD          RCC_AHB2ENR_GPIODEN

  101. #endif

  102. #define LL_AHB2_GRP1_PERIPH_GPIOE          RCC_AHB2ENR_GPIOEEN

  103. #define LL_AHB2_GRP1_PERIPH_GPIOH          RCC_AHB2ENR_GPIOHEN

  104. #if defined(ADC_SUPPORT_5_MSPS)

  105. #define LL_AHB2_GRP1_PERIPH_ADC            RCC_AHB2ENR_ADCEN

  106. #endif

  107. #if defined(AES1)

  108. #define LL_AHB2_GRP1_PERIPH_AES1           RCC_AHB2ENR_AES1EN

  109. #endif

  110. /**

  111.   * @}

  112.   */

  113. 

  114. /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH

  115.   * @{

  116.   */

  117. #define LL_AHB3_GRP1_PERIPH_ALL            (0xFFFFFFFFU)

  118. #if defined(QUADSPI)

  119. #define LL_AHB3_GRP1_PERIPH_QUADSPI        RCC_AHB3ENR_QUADSPIEN

  120. #endif

  121. #define LL_AHB3_GRP1_PERIPH_PKA            RCC_AHB3ENR_PKAEN

  122. #define LL_AHB3_GRP1_PERIPH_AES2           RCC_AHB3ENR_AES2EN

  123. #define LL_AHB3_GRP1_PERIPH_RNG            RCC_AHB3ENR_RNGEN

  124. #define LL_AHB3_GRP1_PERIPH_HSEM           RCC_AHB3ENR_HSEMEN

  125. #define LL_AHB3_GRP1_PERIPH_IPCC           RCC_AHB3ENR_IPCCEN

  126. #define LL_AHB3_GRP1_PERIPH_SRAM2          RCC_AHB3SMENR_SRAM2SMEN

  127. #define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3ENR_FLASHEN

  128. /**

  129.   * @}

  130.   */

  131. 

  132. /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH

  133.   * @{

  134.   */

  135. #define LL_APB1_GRP1_PERIPH_ALL            (0xFFFFFFFFU)

  136. #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR1_TIM2EN

  137. #if defined(LCD)

  138. #define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR1_LCDEN

  139. #endif

  140. #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR1_RTCAPBEN

  141. #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR1_WWDGEN

  142. #if defined(SPI2)

  143. #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR1_SPI2EN

  144. #endif

  145. #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR1_I2C1EN

  146. #if defined(I2C3)

  147. #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR1_I2C3EN

  148. #endif

  149. #if defined(CRS)

  150. #define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR1_CRSEN

  151. #endif

  152. #if defined(USB)

  153. #define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR1_USBEN

  154. #endif

  155. #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR1_LPTIM1EN

  156. /**

  157.   * @}

  158.   */

  159. 

  160. 

  161. /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH

  162.   * @{

  163.   */

  164. #define LL_APB1_GRP2_PERIPH_ALL            (0xFFFFFFFFU)

  165. 

  166. #if defined(LPUART1)

  167. #define LL_APB1_GRP2_PERIPH_LPUART1        RCC_APB1ENR2_LPUART1EN

  168. #endif

  169. #define LL_APB1_GRP2_PERIPH_LPTIM2         RCC_APB1ENR2_LPTIM2EN

  170. /**

  171.   * @}

  172.   */

  173. 

  174. /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH

  175.   * @{

  176.   */

  177. #define LL_APB2_GRP1_PERIPH_ALL            (0xFFFFFFFFU)

  178. 

  179. #if defined(ADC_SUPPORT_2_5_MSPS)

  180. #define LL_APB2_GRP1_PERIPH_ADC            RCC_APB2ENR_ADCEN

  181. #endif

  182. #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN

  183. #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN

  184. #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN

  185. #if defined(TIM16)

  186. #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN

  187. #endif

  188. #if defined(TIM17)

  189. #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN

  190. #endif

  191. #if defined(SAI1)

  192. #define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN

  193. #endif

  194. /**

  195.   * @}

  196.   */

  197. 

  198. /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH

  199.   * @{

  200.   */

  201. #define LL_APB3_GRP1_PERIPH_ALL            (0xFFFFFFFFU)

  202. #define LL_APB3_GRP1_PERIPH_RF             RCC_APB3RSTR_RFRST

  203. /**

  204.   * @}

  205.   */

  206. 

  207. 

  208. /** @defgroup BUS_LL_EC_C2_AHB1_GRP1_PERIPH  C2 AHB1 GRP1 PERIPH

  209.   * @{

  210.   */

  211. #define LL_C2_AHB1_GRP1_PERIPH_DMA1         RCC_C2AHB1ENR_DMA1EN

  212. #if defined(DMA2)

  213. #define LL_C2_AHB1_GRP1_PERIPH_DMA2         RCC_C2AHB1ENR_DMA2EN

  214. #endif

  215. #define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1      RCC_C2AHB1ENR_DMAMUX1EN

  216. #define LL_C2_AHB1_GRP1_PERIPH_SRAM1        RCC_C2AHB1ENR_SRAM1EN

  217. #define LL_C2_AHB1_GRP1_PERIPH_CRC          RCC_C2AHB1ENR_CRCEN

  218. #if defined(TSC)

  219. #define LL_C2_AHB1_GRP1_PERIPH_TSC          RCC_C2AHB1ENR_TSCEN

  220. #endif

  221. /**

  222.   * @}

  223.   */

  224. 

  225. 

  226. /** @defgroup BUS_LL_EC_C2_AHB2_GRP1_PERIPH  C2 AHB2 GRP1 PERIPH

  227.   * @{

  228.   */

  229. #define LL_C2_AHB2_GRP1_PERIPH_GPIOA        RCC_C2AHB2ENR_GPIOAEN

  230. #define LL_C2_AHB2_GRP1_PERIPH_GPIOB        RCC_C2AHB2ENR_GPIOBEN

  231. #define LL_C2_AHB2_GRP1_PERIPH_GPIOC        RCC_C2AHB2ENR_GPIOCEN

  232. #if defined(GPIOD)

  233. #define LL_C2_AHB2_GRP1_PERIPH_GPIOD        RCC_C2AHB2ENR_GPIODEN

  234. #endif

  235. #define LL_C2_AHB2_GRP1_PERIPH_GPIOE        RCC_C2AHB2ENR_GPIOEEN

  236. #define LL_C2_AHB2_GRP1_PERIPH_GPIOH        RCC_C2AHB2ENR_GPIOHEN

  237. #if defined(ADC_SUPPORT_5_MSPS)

  238. #define LL_C2_AHB2_GRP1_PERIPH_ADC          RCC_C2AHB2ENR_ADCEN

  239. #endif

  240. #if defined(AES1)

  241. #define LL_C2_AHB2_GRP1_PERIPH_AES1         RCC_C2AHB2ENR_AES1EN

  242. #endif

  243. /**

  244.   * @}

  245.   */

  246. 

  247. 

  248. /** @defgroup BUS_LL_EC_C2_AHB3_GRP1_PERIPH  C2 AHB3 GRP1 PERIPH

  249.   * @{

  250.   */

  251. #define LL_C2_AHB3_GRP1_PERIPH_PKA          RCC_C2AHB3ENR_PKAEN

  252. #define LL_C2_AHB3_GRP1_PERIPH_AES2         RCC_C2AHB3ENR_AES2EN

  253. #define LL_C2_AHB3_GRP1_PERIPH_RNG          RCC_C2AHB3ENR_RNGEN

  254. #define LL_C2_AHB3_GRP1_PERIPH_HSEM         RCC_C2AHB3ENR_HSEMEN

  255. #define LL_C2_AHB3_GRP1_PERIPH_IPCC         RCC_C2AHB3ENR_IPCCEN

  256. #define LL_C2_AHB3_GRP1_PERIPH_FLASH        RCC_C2AHB3ENR_FLASHEN

  257. #define LL_C2_AHB3_GRP1_PERIPH_SRAM2        RCC_C2AHB3SMENR_SRAM2SMEN

  258. /**

  259.   * @}

  260.   */

  261. 

  262. 

  263. /** @defgroup BUS_LL_EC_C2_APB1_GRP1_PERIPH  C2 APB1 GRP1 PERIPH

  264.   * @{

  265.   */

  266. #define LL_C2_APB1_GRP1_PERIPH_TIM2         RCC_C2APB1ENR1_TIM2EN

  267. #if defined(LCD)

  268. #define LL_C2_APB1_GRP1_PERIPH_LCD          RCC_C2APB1ENR1_LCDEN

  269. #endif

  270. #define LL_C2_APB1_GRP1_PERIPH_RTCAPB       RCC_C2APB1ENR1_RTCAPBEN

  271. #if defined(SPI2)

  272. #define LL_C2_APB1_GRP1_PERIPH_SPI2         RCC_C2APB1ENR1_SPI2EN

  273. #endif

  274. #define LL_C2_APB1_GRP1_PERIPH_I2C1         RCC_C2APB1ENR1_I2C1EN

  275. #if defined(I2C3)

  276. #define LL_C2_APB1_GRP1_PERIPH_I2C3         RCC_C2APB1ENR1_I2C3EN

  277. #define LL_C2_APB1_GRP1_PERIPH_CRS          RCC_C2APB1ENR1_CRSEN

  278. #define LL_C2_APB1_GRP1_PERIPH_USB          RCC_C2APB1ENR1_USBEN

  279. #endif

  280. #define LL_C2_APB1_GRP1_PERIPH_LPTIM1       RCC_C2APB1ENR1_LPTIM1EN

  281. /**

  282.   * @}

  283.   */

  284. 

  285. 

  286. /** @defgroup BUS_LL_EC_C2_APB1_GRP2_PERIPH  C2 APB1 GRP2 PERIPH

  287.   * @{

  288.   */

  289. #if defined(LPUART1)

  290. #define LL_C2_APB1_GRP2_PERIPH_LPUART1      RCC_C2APB1ENR2_LPUART1EN

  291. #endif

  292. #define LL_C2_APB1_GRP2_PERIPH_LPTIM2       RCC_C2APB1ENR2_LPTIM2EN

  293. /**

  294.   * @}

  295.   */

  296. 

  297. 

  298. /** @defgroup BUS_LL_EC_C2_APB2_GRP1_PERIPH  C2 APB2 GRP1 PERIPH

  299.   * @{

  300.   */

  301. #if defined(ADC_SUPPORT_2_5_MSPS)

  302. #define LL_C2_APB2_GRP1_PERIPH_ADC          RCC_C2APB2ENR_ADCEN

  303. #endif

  304. #define LL_C2_APB2_GRP1_PERIPH_TIM1         RCC_C2APB2ENR_TIM1EN

  305. #define LL_C2_APB2_GRP1_PERIPH_SPI1         RCC_C2APB2ENR_SPI1EN

  306. #define LL_C2_APB2_GRP1_PERIPH_USART1       RCC_C2APB2ENR_USART1EN

  307. #if defined(TIM16)

  308. #define LL_C2_APB2_GRP1_PERIPH_TIM16        RCC_C2APB2ENR_TIM16EN

  309. #endif

  310. #if defined(TIM17)

  311. #define LL_C2_APB2_GRP1_PERIPH_TIM17        RCC_C2APB2ENR_TIM17EN

  312. #endif

  313. #if defined(SAI1)

  314. #define LL_C2_APB2_GRP1_PERIPH_SAI1         RCC_C2APB2ENR_SAI1EN

  315. #endif

  316. /**

  317.   * @}

  318.   */

  319. 

  320. 

  321. /** @defgroup BUS_LL_EC_C2_APB3_GRP1_PERIPH  C2 APB3 GRP1 PERIPH

  322.   * @{

  323.   */

  324. #define LL_C2_APB3_GRP1_PERIPH_BLE          RCC_C2APB3ENR_BLEEN

  325. #if defined(RCC_802_SUPPORT)

  326. #define LL_C2_APB3_GRP1_PERIPH_802          RCC_C2APB3ENR_802EN

  327. #endif

  328. /**

  329.   * @}

  330.   */

  331. 

  332. 

  333. /**

  334.   * @}

  335.   */

  336. 

  337. /* Exported macro ------------------------------------------------------------*/

  338. 

  339. /* Exported functions --------------------------------------------------------*/

  340. 

  341. /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions

  342.   * @{

  343.   */

  344. 

  345. /** @defgroup BUS_LL_EF_AHB1 AHB1

  346.   * @{

  347.   */

  348. 

  349. /**

  350.   * @brief  Enable AHB1 peripherals clock.

  351.   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n

  352.   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n

  353.   *         AHB1ENR      DMAMUX1EN      LL_AHB1_GRP1_EnableClock\n

  354.   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock\n

  355.   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_EnableClock

  356.   * @param  Periphs This parameter can be a combination of the following values:

  357.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  358.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)

  359.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1

  360.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  361.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC

  362.   * @note  (*) Not supported by all the devices

  363.   * @retval None

  364.   */

  365. __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)

  366. {

  367.   __IO uint32_t tmpreg;

  368.   SET_BIT(RCC->AHB1ENR, Periphs);

  369.   /* Delay after an RCC peripheral clock enabling */

  370.   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);

  371.   (void)tmpreg;

  372. }

  373. 

  374. /**

  375.   * @brief  Check if AHB1 peripheral clock is enabled or not

  376.   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n

  377.   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n

  378.   *         AHB1ENR      DMAMUX1EN      LL_AHB1_GRP1_IsEnabledClock\n

  379.   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n

  380.   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_IsEnabledClock

  381.   * @param  Periphs This parameter can be a combination of the following values:

  382.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  383.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)

  384.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1

  385.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  386.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC

  387.   * @note  (*) Not supported by all the devices

  388.   * @retval uint32_t

  389.   */

  390. __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

  391. {

  392.   return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  393. }

  394. 

  395. /**

  396.   * @brief  Disable AHB1 peripherals clock.

  397.   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n

  398.   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n

  399.   *         AHB1ENR      DMAMUX1EN      LL_AHB1_GRP1_DisableClock\n

  400.   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock\n

  401.   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_DisableClock

  402.   * @param  Periphs This parameter can be a combination of the following values:

  403.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  404.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)

  405.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1

  406.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  407.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC

  408.   * @note  (*) Not supported by all the devices

  409.   * @retval None

  410.   */

  411. __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)

  412. {

  413.   CLEAR_BIT(RCC->AHB1ENR, Periphs);

  414. }

  415. 

  416. /**

  417.   * @brief  Force AHB1 peripherals reset.

  418.   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n

  419.   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n

  420.   *         AHB1RSTR     DMAMUX1RST     LL_AHB1_GRP1_ForceReset\n

  421.   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n

  422.   *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ForceReset

  423.   * @param  Periphs This parameter can be a combination of the following values:

  424.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL

  425.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  426.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)

  427.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1

  428.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  429.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC

  430.   * @note  (*) Not supported by all the devices

  431.   * @retval None

  432.   */

  433. __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)

  434. {

  435.   SET_BIT(RCC->AHB1RSTR, Periphs);

  436. }

  437. 

  438. /**

  439.   * @brief  Release AHB1 peripherals reset.

  440.   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n

  441.   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n

  442.   *         AHB1RSTR     DMAMUX1RST     LL_AHB1_GRP1_ReleaseReset\n

  443.   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n

  444.   *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ReleaseReset

  445.   * @param  Periphs This parameter can be a combination of the following values:

  446.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL

  447.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  448.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)

  449.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1

  450.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  451.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC

  452.   * @note  (*) Not supported by all the devices

  453.   * @retval None

  454.   */

  455. __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)

  456. {

  457.   CLEAR_BIT(RCC->AHB1RSTR, Periphs);

  458. }

  459. 

  460. /**

  461.   * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.

  462.   * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_EnableClockSleep\n

  463.   *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_EnableClockSleep\n

  464.   *         AHB1SMENR    DMAMUX1SMEN    LL_AHB1_GRP1_EnableClockSleep\n

  465.   *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_EnableClockSleep\n

  466.   *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_EnableClockSleep\n

  467.   *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_EnableClockSleep

  468.   * @param  Periphs This parameter can be a combination of the following values:

  469.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  470.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)

  471.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1

  472.   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1

  473.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  474.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC

  475.   * @note  (*) Not supported by all the devices

  476.   * @retval None

  477.   */

  478. __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

  479. {

  480.   __IO uint32_t tmpreg;

  481.   SET_BIT(RCC->AHB1SMENR, Periphs);

  482.   /* Delay after an RCC peripheral clock enabling */

  483.   tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);

  484.   (void)tmpreg;

  485. }

  486. 

  487. /**

  488.   * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.

  489.   * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_DisableClockSleep\n

  490.   *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_DisableClockSleep\n

  491.   *         AHB1SMENR    DMAMUX1SMEN    LL_AHB1_GRP1_DisableClockSleep\n

  492.   *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockSleep\n

  493.   *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_DisableClockSleep\n

  494.   *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_DisableClockSleep

  495.   * @param  Periphs This parameter can be a combination of the following values:

  496.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  497.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)

  498.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1

  499.   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1

  500.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  501.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC

  502.   * @note  (*) Not supported by all the devices

  503.   * @retval None

  504.   */

  505. __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

  506. {

  507.   CLEAR_BIT(RCC->AHB1SMENR, Periphs);

  508. }

  509. 

  510. /**

  511.   * @}

  512.   */

  513. 

  514. /** @defgroup BUS_LL_EF_AHB2 AHB2

  515.   * @{

  516.   */

  517. 

  518. /**

  519.   * @brief  Enable AHB2 peripherals clock.

  520.   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_EnableClock\n

  521.   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_EnableClock\n

  522.   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_EnableClock\n

  523.   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_EnableClock\n

  524.   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_EnableClock\n

  525.   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_EnableClock\n

  526.   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_EnableClock\n

  527.   *         AHB2ENR      AES1EN        LL_AHB2_GRP1_EnableClock

  528.   * @param  Periphs This parameter can be a combination of the following values:

  529.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA

  530.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB

  531.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC

  532.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)

  533.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE

  534.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH

  535.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)

  536.   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)

  537.   * @note  (*) Not supported by all the devices

  538.   * @retval None

  539.   */

  540. __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)

  541. {

  542.   __IO uint32_t tmpreg;

  543.   SET_BIT(RCC->AHB2ENR, Periphs);

  544.   /* Delay after an RCC peripheral clock enabling */

  545.   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);

  546.   (void)tmpreg;

  547. }

  548. 

  549. /**

  550.   * @brief  Check if AHB2 peripheral clock is enabled or not

  551.   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_IsEnabledClock\n

  552.   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_IsEnabledClock\n

  553.   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_IsEnabledClock\n

  554.   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_IsEnabledClock\n

  555.   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_IsEnabledClock\n

  556.   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_IsEnabledClock\n

  557.   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_IsEnabledClock\n

  558.   *         AHB2ENR      AES1EN        LL_AHB2_GRP1_IsEnabledClock

  559.   * @param  Periphs This parameter can be a combination of the following values:

  560.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA

  561.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB

  562.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC

  563.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)

  564.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE

  565.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH

  566.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)

  567.   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)

  568.   * @note  (*) Not supported by all the devices

  569.   * @retval uint32_t

  570.   */

  571. __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)

  572. {

  573.   return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  574. }

  575. 

  576. /**

  577.   * @brief  Disable AHB2 peripherals clock.

  578.   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_DisableClock\n

  579.   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_DisableClock\n

  580.   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_DisableClock\n

  581.   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_DisableClock\n

  582.   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_DisableClock\n

  583.   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_DisableClock\n

  584.   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_DisableClock\n

  585.   *         AHB2ENR      AES1EN        LL_AHB2_GRP1_DisableClock

  586.   * @param  Periphs This parameter can be a combination of the following values:

  587.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA

  588.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB

  589.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC

  590.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)

  591.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE

  592.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH

  593.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)

  594.   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)

  595.   * @note  (*) Not supported by all the devices

  596.   * @retval None

  597.   */

  598. __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)

  599. {

  600.   CLEAR_BIT(RCC->AHB2ENR, Periphs);

  601. }

  602. 

  603. /**

  604.   * @brief  Force AHB2 peripherals reset.

  605.   * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ForceReset\n

  606.   *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ForceReset\n

  607.   *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ForceReset\n

  608.   *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ForceReset\n

  609.   *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ForceReset\n

  610.   *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ForceReset\n

  611.   *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ForceReset\n

  612.   *         AHB2RSTR     AES1RST       LL_AHB2_GRP1_ForceReset

  613.   * @param  Periphs This parameter can be a combination of the following values:

  614.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL

  615.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA

  616.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB

  617.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC

  618.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)

  619.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE

  620.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH

  621.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)

  622.   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)

  623.   * @note  (*) Not supported by all the devices

  624.   * @retval None

  625.   */

  626. __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)

  627. {

  628.   SET_BIT(RCC->AHB2RSTR, Periphs);

  629. }

  630. 

  631. /**

  632.   * @brief  Release AHB2 peripherals reset.

  633.   * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ReleaseReset\n

  634.   *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ReleaseReset\n

  635.   *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ReleaseReset\n

  636.   *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ReleaseReset\n

  637.   *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ReleaseReset\n

  638.   *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ReleaseReset\n

  639.   *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ReleaseReset\n

  640.   *         AHB2RSTR     AES1RST       LL_AHB2_GRP1_ReleaseReset

  641.   * @param  Periphs This parameter can be a combination of the following values:

  642.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL

  643.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA

  644.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB

  645.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC

  646.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)

  647.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE

  648.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH

  649.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)

  650.   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)

  651.   * @note  (*) Not supported by all the devices

  652.   * @retval None

  653.   */

  654. __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)

  655. {

  656.   CLEAR_BIT(RCC->AHB2RSTR, Periphs);

  657. }

  658. 

  659. /**

  660.   * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.

  661.   * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_EnableClockSleep\n

  662.   *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_EnableClockSleep\n

  663.   *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_EnableClockSleep\n

  664.   *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_EnableClockSleep\n

  665.   *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_EnableClockSleep\n

  666.   *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_EnableClockSleep\n

  667.   *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_EnableClockSleep\n

  668.   *         AHB2SMENR    AES1SMEN      LL_AHB2_GRP1_EnableClockSleep

  669.   * @param  Periphs This parameter can be a combination of the following values:

  670.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA

  671.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB

  672.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC

  673.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)

  674.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE

  675.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH

  676.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)

  677.   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)

  678.   * @note  (*) Not supported by all the devices

  679.   * @retval None

  680.   */

  681. __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)

  682. {

  683.   __IO uint32_t tmpreg;

  684.   SET_BIT(RCC->AHB2SMENR, Periphs);

  685.   /* Delay after an RCC peripheral clock enabling */

  686.   tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);

  687.   (void)tmpreg;

  688. }

  689. 

  690. /**

  691.   * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.

  692.   * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_DisableClockSleep\n

  693.   *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_DisableClockSleep\n

  694.   *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_DisableClockSleep\n

  695.   *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_DisableClockSleep\n

  696.   *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_DisableClockSleep\n

  697.   *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_DisableClockSleep\n

  698.   *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_DisableClockSleep\n

  699.   *         AHB2SMENR    AES1SMEN      LL_AHB2_GRP1_DisableClockSleep

  700.   * @param  Periphs This parameter can be a combination of the following values:

  701.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA

  702.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB

  703.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC

  704.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)

  705.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE

  706.   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH

  707.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)

  708.   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)

  709.   * @note  (*) Not supported by all the devices

  710.   * @retval None

  711.   */

  712. __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)

  713. {

  714.   CLEAR_BIT(RCC->AHB2SMENR, Periphs);

  715. }

  716. 

  717. /**

  718.   * @}

  719.   */

  720. 

  721. /** @defgroup BUS_LL_EF_AHB3 AHB3

  722.   * @{

  723.   */

  724. 

  725. /**

  726.   * @brief  Enable AHB3 peripherals clock.

  727.   * @rmtoll AHB3ENR      QUADSPIEN     LL_AHB3_GRP1_EnableClock\n

  728.   *         AHB3ENR      PKAEN         LL_AHB3_GRP1_EnableClock\n

  729.   *         AHB3ENR      AES2EN        LL_AHB3_GRP1_EnableClock\n

  730.   *         AHB3ENR      RNGEN         LL_AHB3_GRP1_EnableClock\n

  731.   *         AHB3ENR      HSEMEN        LL_AHB3_GRP1_EnableClock\n

  732.   *         AHB3ENR      IPCCEN        LL_AHB3_GRP1_EnableClock\n

  733.   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock

  734.   * @param  Periphs This parameter can be a combination of the following values:

  735.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)

  736.   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA

  737.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2

  738.   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG

  739.   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM

  740.   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC

  741.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  742.   * @note  (*) Not supported by all the devices

  743.   * @retval None

  744.   */

  745. __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)

  746. {

  747.   __IO uint32_t tmpreg;

  748.   SET_BIT(RCC->AHB3ENR, Periphs);

  749.   /* Delay after an RCC peripheral clock enabling */

  750.   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);

  751.   (void)tmpreg;

  752. }

  753. 

  754. /**

  755.   * @brief  Check if AHB3 peripheral clock is enabled or not

  756.   * @rmtoll AHB3ENR      QUADSPIEN     LL_AHB3_GRP1_IsEnabledClock\n

  757.   *         AHB3ENR      PKAEN         LL_AHB3_GRP1_IsEnabledClock\n

  758.   *         AHB3ENR      AES2EN        LL_AHB3_GRP1_IsEnabledClock\n

  759.   *         AHB3ENR      RNGEN         LL_AHB3_GRP1_IsEnabledClock\n

  760.   *         AHB3ENR      HSEMEN        LL_AHB3_GRP1_IsEnabledClock\n

  761.   *         AHB3ENR      IPCCEN        LL_AHB3_GRP1_IsEnabledClock\n

  762.   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock

  763.   * @param  Periphs This parameter can be a combination of the following values:

  764.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)

  765.   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA

  766.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2

  767.   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG

  768.   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM

  769.   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC

  770.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  771.   * @note  (*) Not supported by all the devices

  772.   * @retval uint32_t

  773.   */

  774. __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)

  775. {

  776.   return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  777. }

  778. 

  779. /**

  780.   * @brief  Disable AHB3 peripherals clock.

  781.   * @rmtoll AHB3ENR      QUADSPIEN     LL_AHB3_GRP1_DisableClock\n

  782.   *         AHB3ENR      PKAEN         LL_AHB3_GRP1_DisableClock\n

  783.   *         AHB3ENR      AES2EN        LL_AHB3_GRP1_DisableClock\n

  784.   *         AHB3ENR      RNGEN         LL_AHB3_GRP1_DisableClock\n

  785.   *         AHB3ENR      HSEMEN        LL_AHB3_GRP1_DisableClock\n

  786.   *         AHB3ENR      IPCCEN        LL_AHB3_GRP1_DisableClock\n

  787.   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock

  788.   * @param  Periphs This parameter can be a combination of the following values:

  789.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)

  790.   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA

  791.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2

  792.   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG

  793.   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM

  794.   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC

  795.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  796.   * @note  (*) Not supported by all the devices

  797.   * @retval None

  798.   */

  799. __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)

  800. {

  801.   CLEAR_BIT(RCC->AHB3ENR, Periphs);

  802. }

  803. 

  804. /**

  805.   * @brief  Force AHB3 peripherals reset.

  806.   * @rmtoll AHB3RSTR     QUADSPIRST       LL_AHB3_GRP1_ForceReset\n

  807.   *         AHB3RSTR     PKARST        LL_AHB3_GRP1_ForceReset\n

  808.   *         AHB3RSTR     AES2RST       LL_AHB3_GRP1_ForceReset\n

  809.   *         AHB3RSTR     RNGRST        LL_AHB3_GRP1_ForceReset\n

  810.   *         AHB3RSTR     HSEMRST       LL_AHB3_GRP1_ForceReset\n

  811.   *         AHB3RSTR     IPCCRST       LL_AHB3_GRP1_ForceReset\n

  812.   *         AHB3RSTR     FLASHRST      LL_AHB3_GRP1_ForceReset

  813.   * @param  Periphs This parameter can be a combination of the following values:

  814.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL

  815.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)

  816.   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA

  817.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2

  818.   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG

  819.   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM

  820.   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC

  821.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  822.   * @note  (*) Not supported by all the devices

  823.   * @retval None

  824.   */

  825. __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)

  826. {

  827.   SET_BIT(RCC->AHB3RSTR, Periphs);

  828. }

  829. 

  830. /**

  831.   * @brief  Release AHB3 peripherals reset.

  832.   * @rmtoll AHB3RSTR     QUADSPIRST    LL_AHB3_GRP1_ReleaseReset\n

  833.   *         AHB3RSTR     PKARST        LL_AHB3_GRP1_ReleaseReset\n

  834.   *         AHB3RSTR     AES2RST       LL_AHB3_GRP1_ReleaseReset\n

  835.   *         AHB3RSTR     RNGRST        LL_AHB3_GRP1_ReleaseReset\n

  836.   *         AHB3RSTR     HSEMRST       LL_AHB3_GRP1_ReleaseReset\n

  837.   *         AHB3RSTR     IPCCRST       LL_AHB3_GRP1_ReleaseReset\n

  838.   *         AHB3RSTR     FLASHRST      LL_AHB3_GRP1_ReleaseReset

  839.   * @param  Periphs This parameter can be a combination of the following values:

  840.   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL

  841.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)

  842.   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA

  843.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2

  844.   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG

  845.   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM

  846.   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC

  847.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  848.   * @note  (*) Not supported by all the devices

  849.   * @retval None

  850.   */

  851. __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)

  852. {

  853.   CLEAR_BIT(RCC->AHB3RSTR, Periphs);

  854. }

  855. 

  856. /**

  857.   * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.

  858.   * @rmtoll AHB3SMENR    QUADSPISMEN   LL_AHB3_GRP1_EnableClockSleep\n

  859.   *         AHB3SMENR    PKASMEN       LL_AHB3_GRP1_EnableClockSleep\n

  860.   *         AHB3SMENR    AES2SMEN      LL_AHB3_GRP1_EnableClockSleep\n

  861.   *         AHB3SMENR    RNGSMEN       LL_AHB3_GRP1_EnableClockSleep\n

  862.   *         AHB3SMENR    SRAM2SMEN     LL_AHB3_GRP1_EnableClockSleep\n

  863.   *         AHB3SMENR    FLASHSMEN     LL_AHB3_GRP1_EnableClockSleep

  864.   * @param  Periphs This parameter can be a combination of the following values:

  865.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)

  866.   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA

  867.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2

  868.   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG

  869.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2

  870.   * @note  (*) Not supported by all the devices

  871.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  872.   * @retval None

  873.   */

  874. __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)

  875. {

  876.   __IO uint32_t tmpreg;

  877.   SET_BIT(RCC->AHB3SMENR, Periphs);

  878.   /* Delay after an RCC peripheral clock enabling */

  879.   tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);

  880.   (void)tmpreg;

  881. }

  882. 

  883. /**

  884.   * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.

  885.   * @rmtoll AHB3SMENR    QUADSPISMEN   LL_AHB3_GRP1_DisableClockSleep\n

  886.   *         AHB3SMENR    PKASMEN       LL_AHB3_GRP1_DisableClockSleep\n

  887.   *         AHB3SMENR    AES2SMEN      LL_AHB3_GRP1_DisableClockSleep\n

  888.   *         AHB3SMENR    RNGSMEN       LL_AHB3_GRP1_DisableClockSleep\n

  889.   *         AHB3SMENR    SRAM2SMEN     LL_AHB3_GRP1_DisableClockSleep\n

  890.   *         AHB3SMENR    FLASHSMEN     LL_AHB3_GRP1_DisableClockSleep

  891.   * @param  Periphs This parameter can be a combination of the following values:

  892.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)

  893.   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA

  894.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2

  895.   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG

  896.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2

  897.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  898.   * @note  (*) Not supported by all the devices

  899.   * @retval None

  900.   */

  901. __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)

  902. {

  903.   CLEAR_BIT(RCC->AHB3SMENR, Periphs);

  904. }

  905. 

  906. /**

  907.   * @}

  908.   */

  909. 

  910. /** @defgroup BUS_LL_EF_APB1 APB1

  911.   * @{

  912.   */

  913. 

  914. /**

  915.   * @brief  Enable APB1 peripherals clock.

  916.   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_EnableClock\n

  917.   *         APB1ENR1     LCDEN         LL_APB1_GRP1_EnableClock\n

  918.   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_EnableClock\n

  919.   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_EnableClock\n

  920.   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_EnableClock\n

  921.   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_EnableClock\n

  922.   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_EnableClock\n

  923.   *         APB1ENR1     CRSEN         LL_APB1_GRP1_EnableClock\n

  924.   *         APB1ENR1     USBEN         LL_APB1_GRP1_EnableClock\n

  925.   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_EnableClock

  926.   * @param  Periphs This parameter can be a combination of the following values:

  927.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  928.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  929.   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB

  930.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  931.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  932.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  933.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  934.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  935.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  936.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  937.   * @note  (*) Not supported by all the devices

  938.   * @retval None

  939.   */

  940. __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)

  941. {

  942.   __IO uint32_t tmpreg;

  943.   SET_BIT(RCC->APB1ENR1, Periphs);

  944.   /* Delay after an RCC peripheral clock enabling */

  945.   tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);

  946.   (void)tmpreg;

  947. }

  948. 

  949. /**

  950.   * @brief  Enable APB1 peripherals clock.

  951.   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_EnableClock\n

  952.   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_EnableClock

  953.   * @param  Periphs This parameter can be a combination of the following values:

  954.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)

  955.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2

  956.   * @note  (*) Not supported by all the devices

  957.   * @retval None

  958.   */

  959. __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)

  960. {

  961.   __IO uint32_t tmpreg;

  962.   SET_BIT(RCC->APB1ENR2, Periphs);

  963.   /* Delay after an RCC peripheral clock enabling */

  964.   tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);

  965.   (void)tmpreg;

  966. }

  967. 

  968. /**

  969.   * @brief  Check if APB1 peripheral clock is enabled or not

  970.   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n

  971.   *         APB1ENR1     LCDEN         LL_APB1_GRP1_IsEnabledClock\n

  972.   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n

  973.   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n

  974.   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n

  975.   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n

  976.   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n

  977.   *         APB1ENR1     CRSEN         LL_APB1_GRP1_IsEnabledClock\n

  978.   *         APB1ENR1     USBEN         LL_APB1_GRP1_IsEnabledClock\n

  979.   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock

  980.   * @param  Periphs This parameter can be a combination of the following values:

  981.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  982.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  983.   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB

  984.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  985.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  986.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  987.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  988.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  989.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  990.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  991.   * @note  (*) Not supported by all the devices

  992.   * @retval uint32_t

  993.   */

  994. __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

  995. {

  996.   return ((READ_BIT(RCC->APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);

  997. }

  998. 

  999. /**

  1000.   * @brief  Check if APB1 peripheral clock is enabled or not

  1001.   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_IsEnabledClock\n

  1002.   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_IsEnabledClock

  1003.   * @param  Periphs This parameter can be a combination of the following values:

  1004.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)

  1005.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2

  1006.   * @note  (*) Not supported by all the devices

  1007.   * @retval uint32_t

  1008.   */

  1009. __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)

  1010. {

  1011.   return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);

  1012. }

  1013. 

  1014. /**

  1015.   * @brief  Disable APB1 peripherals clock.

  1016.   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_DisableClock\n

  1017.   *         APB1ENR1     LCDEN         LL_APB1_GRP1_DisableClock\n

  1018.   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_DisableClock\n

  1019.   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_DisableClock\n

  1020.   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_DisableClock\n

  1021.   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_DisableClock\n

  1022.   *         APB1ENR1     CRSEN         LL_APB1_GRP1_DisableClock\n

  1023.   *         APB1ENR1     USBEN         LL_APB1_GRP1_DisableClock\n

  1024.   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_DisableClock

  1025.   * @param  Periphs This parameter can be a combination of the following values:

  1026.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1027.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  1028.   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB

  1029.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  1030.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  1031.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1032.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  1033.   *         @arg @ref LL_APB1_GRP1_PERIPH_ (*)

  1034.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  1035.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1036.   * @note  (*) Not supported by all the devices

  1037.   * @retval None

  1038.   */

  1039. __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)

  1040. {

  1041.   CLEAR_BIT(RCC->APB1ENR1, Periphs);

  1042. }

  1043. 

  1044. /**

  1045.   * @brief  Disable APB1 peripherals clock.

  1046.   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_DisableClock\n

  1047.   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_DisableClock

  1048.   * @param  Periphs This parameter can be a combination of the following values:

  1049.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)

  1050.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2

  1051.   * @note  (*) Not supported by all the devices

  1052.   * @retval None

  1053.   */

  1054. __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)

  1055. {

  1056.   CLEAR_BIT(RCC->APB1ENR2, Periphs);

  1057. }

  1058. 

  1059. /**

  1060.   * @brief  Force APB1 peripherals reset.

  1061.   * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ForceReset\n

  1062.   *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ForceReset\n

  1063.   *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ForceReset\n

  1064.   *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ForceReset\n

  1065.   *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ForceReset\n

  1066.   *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ForceReset\n

  1067.   *         APB1RSTR1    USBRST        LL_APB1_GRP1_ForceReset\n

  1068.   *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ForceReset

  1069.   * @param  Periphs This parameter can be a combination of the following values:

  1070.   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL

  1071.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1072.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  1073.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  1074.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1075.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  1076.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  1077.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  1078.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1079.   * @note  (*) Not supported by all the devices

  1080.   * @retval None

  1081.   */

  1082. __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)

  1083. {

  1084.   SET_BIT(RCC->APB1RSTR1, Periphs);

  1085. }

  1086. 

  1087. /**

  1088.   * @brief  Force APB1 peripherals reset.

  1089.   * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ForceReset\n

  1090.   *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ForceReset

  1091.   * @param  Periphs This parameter can be a combination of the following values:

  1092.   *         @arg @ref LL_APB1_GRP2_PERIPH_ALL

  1093.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)

  1094.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2

  1095.   * @note  (*) Not supported by all the devices

  1096.   * @retval None

  1097.   */

  1098. __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)

  1099. {

  1100.   SET_BIT(RCC->APB1RSTR2, Periphs);

  1101. }

  1102. 

  1103. /**

  1104.   * @brief  Release APB1 peripherals reset.

  1105.   * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ReleaseReset\n

  1106.   *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ReleaseReset\n

  1107.   *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ReleaseReset\n

  1108.   *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ReleaseReset\n

  1109.   *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ReleaseReset\n

  1110.   *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ReleaseReset\n

  1111.   *         APB1RSTR1    USBRST        LL_APB1_GRP1_ReleaseReset\n

  1112.   *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ReleaseReset

  1113.   * @param  Periphs This parameter can be a combination of the following values:

  1114.   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL

  1115.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1116.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  1117.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  1118.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1119.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  1120.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  1121.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  1122.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1123.   * @note  (*) Not supported by all the devices

  1124.   * @retval None

  1125.   */

  1126. __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)

  1127. {

  1128.   CLEAR_BIT(RCC->APB1RSTR1, Periphs);

  1129. }

  1130. 

  1131. /**

  1132.   * @brief  Release APB1 peripherals reset.

  1133.   * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ReleaseReset\n

  1134.   *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ReleaseReset

  1135.   * @param  Periphs This parameter can be a combination of the following values:

  1136.   *         @arg @ref LL_APB1_GRP2_PERIPH_ALL

  1137.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)

  1138.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2

  1139.   * @note  (*) Not supported by all the devices

  1140.   * @retval None

  1141.   */

  1142. __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)

  1143. {

  1144.   CLEAR_BIT(RCC->APB1RSTR2, Periphs);

  1145. }

  1146. 

  1147. /**

  1148.   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.

  1149.   * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_EnableClockSleep\n

  1150.   *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_EnableClockSleep\n

  1151.   *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_EnableClockSleep\n

  1152.   *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_EnableClockSleep\n

  1153.   *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_EnableClockSleep\n

  1154.   *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_EnableClockSleep\n

  1155.   *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_EnableClockSleep\n

  1156.   *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_EnableClockSleep\n

  1157.   *         APB1SMENR1   USBSMEN       LL_APB1_GRP1_EnableClockSleep\n

  1158.   *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_EnableClockSleep

  1159.   * @param  Periphs This parameter can be a combination of the following values:

  1160.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1161.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  1162.   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB

  1163.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  1164.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  1165.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1166.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  1167.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  1168.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  1169.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1170.   * @note  (*) Not supported by all the devices

  1171.   * @retval None

  1172.   */

  1173. __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

  1174. {

  1175.   __IO uint32_t tmpreg;

  1176.   SET_BIT(RCC->APB1SMENR1, Periphs);

  1177.   /* Delay after an RCC peripheral clock enabling */

  1178.   tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);

  1179.   (void)tmpreg;

  1180. }

  1181. 

  1182. /**

  1183.   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.

  1184.   * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_EnableClockSleep\n

  1185.   *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_EnableClockSleep

  1186.   * @param  Periphs This parameter can be a combination of the following values:

  1187.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)

  1188.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2

  1189.   * @note  (*) Not supported by all the devices

  1190.   * @retval None

  1191.   */

  1192. __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)

  1193. {

  1194.   __IO uint32_t tmpreg;

  1195.   SET_BIT(RCC->APB1SMENR2, Periphs);

  1196.   /* Delay after an RCC peripheral clock enabling */

  1197.   tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);

  1198.   (void)tmpreg;

  1199. }

  1200. 

  1201. /**

  1202.   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.

  1203.   * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_DisableClockSleep\n

  1204.   *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_DisableClockSleep\n

  1205.   *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_DisableClockSleep\n

  1206.   *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_DisableClockSleep\n

  1207.   *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_DisableClockSleep\n

  1208.   *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_DisableClockSleep\n

  1209.   *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_DisableClockSleep\n

  1210.   *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_DisableClockSleep\n

  1211.   *         APB1SMENR1   USBSMEN       LL_APB1_GRP1_DisableClockSleep\n

  1212.   *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_DisableClockSleep

  1213.   * @param  Periphs This parameter can be a combination of the following values:

  1214.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1215.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  1216.   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB

  1217.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  1218.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  1219.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1220.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  1221.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  1222.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  1223.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1224.   * @note  (*) Not supported by all the devices

  1225.   * @retval None

  1226.   */

  1227. __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

  1228. {

  1229.   CLEAR_BIT(RCC->APB1SMENR1, Periphs);

  1230. }

  1231. 

  1232. /**

  1233.   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.

  1234.   * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_DisableClockSleep\n

  1235.   *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_DisableClockSleep

  1236.   * @param  Periphs This parameter can be a combination of the following values:

  1237.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)

  1238.   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2

  1239.   * @note  (*) Not supported by all the devices

  1240.   * @retval None

  1241.   */

  1242. __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)

  1243. {

  1244.   CLEAR_BIT(RCC->APB1SMENR2, Periphs);

  1245. }

  1246. 

  1247. /**

  1248.   * @}

  1249.   */

  1250. 

  1251. /** @defgroup BUS_LL_EF_APB2 APB2

  1252.   * @{

  1253.   */

  1254. 

  1255. /**

  1256.   * @brief  Enable APB2 peripherals clock.

  1257.   * @rmtoll APB2ENR      ADCEN         LL_APB2_GRP1_EnableClock\n

  1258.   *         APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n

  1259.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n

  1260.   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n

  1261.   *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n

  1262.   *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n

  1263.   *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock

  1264.   * @param  Periphs This parameter can be a combination of the following values:

  1265.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)

  1266.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  1267.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  1268.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  1269.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)

  1270.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)

  1271.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)

  1272.   * @note  (*) Not supported by all the devices

  1273.   * @retval None

  1274.   */

  1275. __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)

  1276. {

  1277.   __IO uint32_t tmpreg;

  1278.   SET_BIT(RCC->APB2ENR, Periphs);

  1279.   /* Delay after an RCC peripheral clock enabling */

  1280.   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);

  1281.   (void)tmpreg;

  1282. }

  1283. 

  1284. /**

  1285.   * @brief  Check if APB2 peripheral clock is enabled or not

  1286.   * @rmtoll APB2ENR      ADCEN         LL_APB2_GRP1_IsEnabledClock\n

  1287.   *         APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n

  1288.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n

  1289.   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n

  1290.   *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n

  1291.   *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n

  1292.   *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock

  1293.   * @param  Periphs This parameter can be a combination of the following values:

  1294.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)

  1295.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  1296.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  1297.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  1298.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)

  1299.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)

  1300.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)

  1301.   * @note  (*) Not supported by all the devices

  1302.   * @retval uint32_t

  1303.   */

  1304. __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

  1305. {

  1306.   return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  1307. }

  1308. 

  1309. /**

  1310.   * @brief  Disable APB2 peripherals clock.

  1311.   * @rmtoll APB2ENR      ADCEN         LL_APB2_GRP1_DisableClock\n

  1312.   *         APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n

  1313.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n

  1314.   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n

  1315.   *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n

  1316.   *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n

  1317.   *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock

  1318.   * @param  Periphs This parameter can be a combination of the following values:

  1319.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)

  1320.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  1321.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  1322.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  1323.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)

  1324.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)

  1325.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)

  1326.   * @note  (*) Not supported by all the devices

  1327.   * @retval None

  1328.   */

  1329. __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)

  1330. {

  1331.   CLEAR_BIT(RCC->APB2ENR, Periphs);

  1332. }

  1333. 

  1334. /**

  1335.   * @brief  Force APB2 peripherals reset.

  1336.   * @rmtoll APB2RSTR     ADCRST        LL_APB2_GRP1_ForceReset\n

  1337.   *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n

  1338.   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n

  1339.   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n

  1340.   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n

  1341.   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n

  1342.   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset

  1343.   * @param  Periphs This parameter can be a combination of the following values:

  1344.   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL

  1345.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)

  1346.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  1347.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  1348.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  1349.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)

  1350.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)

  1351.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)

  1352.   * @note  (*) Not supported by all the devices

  1353.   * @retval None

  1354.   */

  1355. __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)

  1356. {

  1357.   SET_BIT(RCC->APB2RSTR, Periphs);

  1358. }

  1359. 

  1360. /**

  1361.   * @brief  Release APB2 peripherals reset.

  1362.   * @rmtoll APB2RSTR     ADCRST        LL_APB2_GRP1_ReleaseReset\n

  1363.   *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n

  1364.   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n

  1365.   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n

  1366.   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n

  1367.   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n

  1368.   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset

  1369.   * @param  Periphs This parameter can be a combination of the following values:

  1370.   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL

  1371.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)

  1372.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  1373.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  1374.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  1375.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)

  1376.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)

  1377.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)

  1378.   * @note  (*) Not supported by all the devices

  1379.   * @retval None

  1380.   */

  1381. __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)

  1382. {

  1383.   CLEAR_BIT(RCC->APB2RSTR, Periphs);

  1384. }

  1385. 

  1386. /**

  1387.   * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.

  1388.   * @rmtoll APB2SMENR    ADCSMEN       LL_APB2_GRP1_EnableClockSleep\n

  1389.   *         APB2SMENR    TIM1SMEN      LL_APB2_GRP1_EnableClockSleep\n

  1390.   *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_EnableClockSleep\n

  1391.   *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_EnableClockSleep\n

  1392.   *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_EnableClockSleep\n

  1393.   *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_EnableClockSleep\n

  1394.   *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_EnableClockSleep

  1395.   * @param  Periphs This parameter can be a combination of the following values:

  1396.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)

  1397.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  1398.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  1399.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  1400.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)

  1401.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)

  1402.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)

  1403.   * @note  (*) Not supported by all the devices

  1404.   * @retval None

  1405.   */

  1406. __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

  1407. {

  1408.   __IO uint32_t tmpreg;

  1409.   SET_BIT(RCC->APB2SMENR, Periphs);

  1410.   /* Delay after an RCC peripheral clock enabling */

  1411.   tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);

  1412.   (void)tmpreg;

  1413. }

  1414. 

  1415. /**

  1416.   * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.

  1417.   * @rmtoll APB2SMENR    ADCSMEN       LL_APB2_GRP1_DisableClockSleep\n

  1418.   *         APB2SMENR    TIM1SMEN      LL_APB2_GRP1_DisableClockSleep\n

  1419.   *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_DisableClockSleep\n

  1420.   *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_DisableClockSleep\n

  1421.   *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_DisableClockSleep\n

  1422.   *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_DisableClockSleep\n

  1423.   *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_DisableClockSleep

  1424.   * @param  Periphs This parameter can be a combination of the following values:

  1425.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)

  1426.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  1427.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  1428.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  1429.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)

  1430.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)

  1431.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)

  1432.   * @note  (*) Not supported by all the devices

  1433.   * @retval None

  1434.   */

  1435. __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

  1436. {

  1437.   CLEAR_BIT(RCC->APB2SMENR, Periphs);

  1438. }

  1439. 

  1440. /**

  1441.   * @}

  1442.   */

  1443. 

  1444. /** @defgroup BUS_LL_EF_APB3 APB3

  1445.   * @{

  1446.   */

  1447. 

  1448. /**

  1449.   * @brief  Force APB3 peripherals reset.

  1450.   * @rmtoll APB3RSTR     RFRST        LL_APB3_GRP1_ForceReset

  1451.   * @param  Periphs This parameter can be a combination of the following values:

  1452.   *         @arg @ref LL_APB3_GRP1_PERIPH_RF

  1453.   * @retval None

  1454.   */

  1455. __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)

  1456. {

  1457.   SET_BIT(RCC->APB3RSTR, Periphs);

  1458. }

  1459. 

  1460. /**

  1461.   * @brief  Release APB3 peripherals reset.

  1462.   * @rmtoll APB3RSTR     RFRST        LL_APB3_GRP1_ReleaseReset

  1463.   * @param  Periphs This parameter can be a combination of the following values:

  1464.   *         @arg @ref LL_APB3_GRP1_PERIPH_RF

  1465.   * @retval None

  1466.   */

  1467. __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)

  1468. {

  1469.   CLEAR_BIT(RCC->APB3RSTR, Periphs);

  1470. }

  1471. 

  1472. /**

  1473.   * @}

  1474.   */

  1475. 

  1476. /** @defgroup BUS_LL_EF_C2_AHB1 C2 AHB1

  1477.   * @{

  1478.   */

  1479. /**

  1480.   * @brief  Enable C2AHB1 peripherals clock.

  1481.   * @rmtoll C2AHB1ENR    DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n

  1482.   *         C2AHB1ENR    DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n

  1483.   *         C2AHB1ENR    DMAMUX1EN     LL_C2_AHB1_GRP1_EnableClock\n

  1484.   *         C2AHB1ENR    SRAM1EN       LL_C2_AHB1_GRP1_EnableClock\n

  1485.   *         C2AHB1ENR    CRCEN         LL_C2_AHB1_GRP1_EnableClock\n

  1486.   *         C2AHB1ENR    TSCEN         LL_C2_AHB1_GRP1_EnableClock

  1487.   * @param  Periphs This parameter can be a combination of the following values:

  1488.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1

  1489.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)

  1490.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1

  1491.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1

  1492.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC

  1493.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC

  1494.   * @note  (*) Not supported by all the devices

  1495.   * @retval None

  1496.   */

  1497. 

  1498. __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)

  1499. {

  1500.   __IO uint32_t tmpreg;

  1501.   SET_BIT(RCC->C2AHB1ENR, Periphs);

  1502.   /* Delay after an RCC peripheral clock enabling */

  1503.   tmpreg = READ_BIT(RCC->C2AHB1ENR, Periphs);

  1504.   (void)tmpreg;

  1505. }

  1506. 

  1507. /**

  1508.   * @brief  Check if C2AHB1 peripheral clock is enabled or not

  1509.   * @rmtoll C2AHB1ENR    DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n

  1510.   *         C2AHB1ENR    DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n

  1511.   *         C2AHB1ENR    DMAMUX1EN     LL_C2_AHB1_GRP1_IsEnabledClock\n

  1512.   *         C2AHB1ENR    SRAM1EN       LL_C2_AHB1_GRP1_IsEnabledClock\n

  1513.   *         C2AHB1ENR    CRCEN         LL_C2_AHB1_GRP1_IsEnabledClock\n

  1514.   *         C2AHB1ENR    TSCEN         LL_C2_AHB1_GRP1_IsEnabledClock

  1515.   * @param  Periphs This parameter can be a combination of the following values:

  1516.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1

  1517.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)

  1518.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1

  1519.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1

  1520.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC

  1521.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC

  1522.   * @note  (*) Not supported by all the devices

  1523.   * @retval uint32_t

  1524.   */

  1525. 

  1526. __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

  1527. {

  1528.   return ((READ_BIT(RCC->C2AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  1529. }

  1530. 

  1531. /**

  1532.   * @brief  Disable C2AHB1 peripherals clock.

  1533.   * @rmtoll C2AHB1ENR    DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n

  1534.   *         C2AHB1ENR    DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n

  1535.   *         C2AHB1ENR    DMAMUX1EN     LL_C2_AHB1_GRP1_DisableClock\n

  1536.   *         C2AHB1ENR    SRAM1EN       LL_C2_AHB1_GRP1_DisableClock\n

  1537.   *         C2AHB1ENR    CRCEN         LL_C2_AHB1_GRP1_DisableClock\n

  1538.   *         C2AHB1ENR    TSCEN         LL_C2_AHB1_GRP1_DisableClock

  1539.   * @param  Periphs This parameter can be a combination of the following values:

  1540.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1

  1541.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)

  1542.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1

  1543.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1

  1544.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC

  1545.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC

  1546.   * @note  (*) Not supported by all the devices

  1547.   * @retval None

  1548.   */

  1549. 

  1550. __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)

  1551. {

  1552.   CLEAR_BIT(RCC->C2AHB1ENR, Periphs);

  1553. }

  1554. 

  1555. /**

  1556.   * @brief  Enable C2AHB1 peripherals clock during Low Power (Sleep) mode.

  1557.   * @rmtoll C2AHB1SMENR  DMA1SMEN      LL_C2_AHB1_GRP1_EnableClockSleep\n

  1558.   *         C2AHB1SMENR  DMA2SMEN      LL_C2_AHB1_GRP1_EnableClockSleep\n

  1559.   *         C2AHB1SMENR  DMAMUX1SMEN   LL_C2_AHB1_GRP1_EnableClockSleep\n

  1560.   *         C2AHB1ENR    SRAM1SMEN     LL_C2_AHB1_GRP1_EnableClockSleep\n

  1561.   *         C2AHB1SMENR  CRCSMEN       LL_C2_AHB1_GRP1_EnableClockSleep\n

  1562.   *         C2AHB1SMENR  TSCSMEN       LL_C2_AHB1_GRP1_EnableClockSleep

  1563.   * @param  Periphs This parameter can be a combination of the following values:

  1564.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1

  1565.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)

  1566.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1

  1567.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1

  1568.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC

  1569.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC

  1570.   * @note  (*) Not supported by all the devices

  1571.   * @retval None

  1572.   */

  1573. 

  1574. __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

  1575. {

  1576.   __IO uint32_t tmpreg;

  1577.   SET_BIT(RCC->C2AHB1SMENR, Periphs);

  1578.   /* Delay after an RCC peripheral clock enabling */

  1579.   tmpreg = READ_BIT(RCC->C2AHB1SMENR, Periphs);

  1580.   (void)tmpreg;

  1581. }

  1582. 

  1583. /**

  1584.   * @brief  Disable C2AHB1 peripherals clock during Low Power (Sleep) mode.

  1585.   * @rmtoll C2AHB1SMENR  DMA1SMEN      LL_C2_AHB1_GRP1_DisableClockSleep\n

  1586.   *         C2AHB1SMENR  DMA2SMEN      LL_C2_AHB1_GRP1_DisableClockSleep\n

  1587.   *         C2AHB1SMENR  DMAMUX1SMEN    LL_C2_AHB1_GRP1_DisableClockSleep\n

  1588.   *         C2AHB1ENR    SRAM1SMEN     LL_C2_AHB1_GRP1_DisableClockSleep\n

  1589.   *         C2AHB1SMENR  CRCSMEN       LL_C2_AHB1_GRP1_DisableClockSleep\n

  1590.   *         C2AHB1SMENR  TSCSMEN       LL_C2_AHB1_GRP1_DisableClockSleep

  1591.   * @param  Periphs This parameter can be a combination of the following values:

  1592.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1

  1593.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)

  1594.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1

  1595.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1

  1596.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC

  1597.   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC

  1598.   * @note  (*) Not supported by all the devices

  1599.   * @retval None

  1600.   */

  1601. 

  1602. __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

  1603. {

  1604.   CLEAR_BIT(RCC->C2AHB1SMENR, Periphs);

  1605. }

  1606. 

  1607. /**

  1608.   * @}

  1609.   */

  1610. 

  1611. /** @defgroup BUS_LL_EF_C2_AHB2 C2 AHB2

  1612.   * @{

  1613.   */

  1614. 

  1615. /**

  1616.   * @brief  Enable C2AHB2 peripherals clock.

  1617.   * @rmtoll C2AHB2ENR    GPIOAEN       LL_C2_AHB2_GRP1_EnableClock\n

  1618.   *         C2AHB2ENR    GPIOBEN       LL_C2_AHB2_GRP1_EnableClock\n

  1619.   *         C2AHB2ENR    GPIOCEN       LL_C2_AHB2_GRP1_EnableClock\n

  1620.   *         C2AHB2ENR    GPIODEN       LL_C2_AHB2_GRP1_EnableClock\n

  1621.   *         C2AHB2ENR    GPIOEEN       LL_C2_AHB2_GRP1_EnableClock\n

  1622.   *         C2AHB2ENR    GPIOHEN       LL_C2_AHB2_GRP1_EnableClock\n

  1623.   *         C2AHB2ENR    ADCEN         LL_C2_AHB2_GRP1_EnableClock\n

  1624.   *         C2AHB2ENR    AES1EN        LL_C2_AHB2_GRP1_EnableClock

  1625.   * @param  Periphs This parameter can be a combination of the following values:

  1626.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA

  1627.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB

  1628.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC

  1629.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)

  1630.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE

  1631.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH

  1632.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)

  1633.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)

  1634.   * @note  (*) Not supported by all the devices

  1635.   * @retval None

  1636.   */

  1637. __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)

  1638. {

  1639.   __IO uint32_t tmpreg;

  1640.   SET_BIT(RCC->C2AHB2ENR, Periphs);

  1641.   /* Delay after an RCC peripheral clock enabling */

  1642.   tmpreg = READ_BIT(RCC->C2AHB2ENR, Periphs);

  1643.   (void)tmpreg;

  1644. }

  1645. 

  1646. /**

  1647.   * @brief  Check if C2AHB2 peripheral clock is enabled or not

  1648.   * @rmtoll C2AHB2ENR    GPIOAEN       LL_C2_AHB2_GRP1_IsEnabledClock\n

  1649.   *         C2AHB2ENR    GPIOBEN       LL_C2_AHB2_GRP1_IsEnabledClock\n

  1650.   *         C2AHB2ENR    GPIOCEN       LL_C2_AHB2_GRP1_IsEnabledClock\n

  1651.   *         C2AHB2ENR    GPIODEN       LL_C2_AHB2_GRP1_IsEnabledClock\n

  1652.   *         C2AHB2ENR    GPIOEEN       LL_C2_AHB2_GRP1_IsEnabledClock\n

  1653.   *         C2AHB2ENR    GPIOHEN       LL_C2_AHB2_GRP1_IsEnabledClock\n

  1654.   *         C2AHB2ENR    ADCEN         LL_C2_AHB2_GRP1_IsEnabledClock\n

  1655.   *         C2AHB2ENR    AES1EN        LL_C2_AHB2_GRP1_IsEnabledClock

  1656.   * @param  Periphs This parameter can be a combination of the following values:

  1657.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA

  1658.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB

  1659.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC

  1660.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)

  1661.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE

  1662.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH

  1663.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)

  1664.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)

  1665.   * @note  (*) Not supported by all the devices

  1666.   * @retval uint32_t

  1667.   */

  1668. __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)

  1669. {

  1670.   return ((READ_BIT(RCC->C2AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  1671. }

  1672. 

  1673. /**

  1674.   * @brief  Disable C2AHB2 peripherals clock.

  1675.   * @rmtoll C2AHB2ENR    GPIOAEN       LL_C2_AHB2_GRP1_DisableClock\n

  1676.   *         C2AHB2ENR    GPIOBEN       LL_C2_AHB2_GRP1_DisableClock\n

  1677.   *         C2AHB2ENR    GPIOCEN       LL_C2_AHB2_GRP1_DisableClock\n

  1678.   *         C2AHB2ENR    GPIODEN       LL_C2_AHB2_GRP1_DisableClock\n

  1679.   *         C2AHB2ENR    GPIOEEN       LL_C2_AHB2_GRP1_DisableClock\n

  1680.   *         C2AHB2ENR    GPIOHEN       LL_C2_AHB2_GRP1_DisableClock\n

  1681.   *         C2AHB2ENR    ADCEN         LL_C2_AHB2_GRP1_DisableClock\n

  1682.   *         C2AHB2ENR    AES1EN        LL_C2_AHB2_GRP1_DisableClock

  1683.   * @param  Periphs This parameter can be a combination of the following values:

  1684.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA

  1685.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB

  1686.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC

  1687.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)

  1688.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE

  1689.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH

  1690.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)

  1691.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)

  1692.   * @note  (*) Not supported by all the devices

  1693.   * @retval None

  1694.   */

  1695. __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)

  1696. {

  1697.   CLEAR_BIT(RCC->C2AHB2ENR, Periphs);

  1698. }

  1699. 

  1700. /**

  1701.   * @brief  Enable C2AHB2 peripherals clock during Low Power (Sleep) mode.

  1702.   * @rmtoll C2AHB2SMENR  GPIOASMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n

  1703.   *         C2AHB2SMENR  GPIOBSMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n

  1704.   *         C2AHB2SMENR  GPIOCSMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n

  1705.   *         C2AHB2SMENR  GPIODSMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n

  1706.   *         C2AHB2SMENR  GPIOESMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n

  1707.   *         C2AHB2SMENR  GPIOHSMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n

  1708.   *         C2AHB2SMENR  ADCSMEN       LL_C2_AHB2_GRP1_EnableClockSleep\n

  1709.   *         C2AHB2SMENR  AES1SMEN      LL_C2_AHB2_GRP1_EnableClockSleep

  1710.   * @param  Periphs This parameter can be a combination of the following values:

  1711.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA

  1712.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB

  1713.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC

  1714.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)

  1715.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE

  1716.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH

  1717.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)

  1718.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)

  1719.   * @note  (*) Not supported by all the devices

  1720.   * @retval None

  1721.   */

  1722. __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)

  1723. {

  1724.   __IO uint32_t tmpreg;

  1725.   SET_BIT(RCC->C2AHB2SMENR, Periphs);

  1726.   /* Delay after an RCC peripheral clock enabling */

  1727.   tmpreg = READ_BIT(RCC->C2AHB2SMENR, Periphs);

  1728.   (void)tmpreg;

  1729. }

  1730. 

  1731. /**

  1732.   * @brief  Disable C2AHB2 peripherals clock during Low Power (Sleep) mode.

  1733.   * @rmtoll C2AHB2SMENR  GPIOASMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n

  1734.   *         C2AHB2SMENR  GPIOBSMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n

  1735.   *         C2AHB2SMENR  GPIOCSMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n

  1736.   *         C2AHB2SMENR  GPIODSMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n

  1737.   *         C2AHB2SMENR  GPIOESMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n

  1738.   *         C2AHB2SMENR  GPIOHSMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n

  1739.   *         C2AHB2SMENR  ADCSMEN       LL_C2_AHB2_GRP1_DisableClockSleep\n

  1740.   *         C2AHB2SMENR  AES1SMEN      LL_C2_AHB2_GRP1_DisableClockSleep

  1741.   * @param  Periphs This parameter can be a combination of the following values:

  1742.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA

  1743.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB

  1744.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC

  1745.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)

  1746.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE

  1747.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH

  1748.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)

  1749.   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)

  1750.   * @note  (*) Not supported by all the devices

  1751.   * @retval None

  1752.   */

  1753. __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)

  1754. {

  1755.   CLEAR_BIT(RCC->C2AHB2SMENR, Periphs);

  1756. }

  1757. 

  1758. /**

  1759.   * @}

  1760.   */

  1761. 

  1762. /** @defgroup BUS_LL_EF_C2_AHB3 C2 AHB3

  1763.   * @{

  1764.   */

  1765. 

  1766. /**

  1767.   * @brief  Enable C2AHB3 peripherals clock.

  1768.   * @rmtoll C2AHB3ENR    PKAEN         LL_C2_AHB3_GRP1_EnableClock\n

  1769.   *         C2AHB3ENR    AES2EN        LL_C2_AHB3_GRP1_EnableClock\n

  1770.   *         C2AHB3ENR    RNGEN         LL_C2_AHB3_GRP1_EnableClock\n

  1771.   *         C2AHB3ENR    HSEMEN        LL_C2_AHB3_GRP1_EnableClock\n

  1772.   *         C2AHB3ENR    IPCCEN        LL_C2_AHB3_GRP1_EnableClock\n

  1773.   *         C2AHB3ENR    FLASHEN       LL_C2_AHB3_GRP1_EnableClock

  1774.   * @param  Periphs This parameter can be a combination of the following values:

  1775.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA

  1776.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2

  1777.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG

  1778.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM

  1779.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC

  1780.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH

  1781.   * @retval None

  1782.   */

  1783. __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)

  1784. {

  1785.   __IO uint32_t tmpreg;

  1786.   SET_BIT(RCC->C2AHB3ENR, Periphs);

  1787.   /* Delay after an RCC peripheral clock enabling */

  1788.   tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs);

  1789.   (void)tmpreg;

  1790. }

  1791. 

  1792. /**

  1793.   * @brief  Check if C2AHB3 peripheral clock is enabled or not

  1794.   * @rmtoll C2AHB3ENR    PKAEN         LL_C2_AHB3_GRP1_IsEnabledClock\n

  1795.   *         C2AHB3ENR    AES2EN        LL_C2_AHB3_GRP1_IsEnabledClock\n

  1796.   *         C2AHB3ENR    RNGEN         LL_C2_AHB3_GRP1_IsEnabledClock\n

  1797.   *         C2AHB3ENR    HSEMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n

  1798.   *         C2AHB3ENR    IPCCEN        LL_C2_AHB3_GRP1_IsEnabledClock\n

  1799.   *         C2AHB3ENR    FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock

  1800.   * @param  Periphs This parameter can be a combination of the following values:

  1801.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA

  1802.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2

  1803.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG

  1804.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM

  1805.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC

  1806.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH

  1807.   * @retval uint32_t

  1808.   */

  1809. __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)

  1810. {

  1811.   return ((READ_BIT(RCC->C2AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  1812. }

  1813. 

  1814. /**

  1815.   * @brief  Disable C2AHB3 peripherals clock.

  1816.   * @rmtoll C2AHB3ENR    PKAEN         LL_C2_AHB3_GRP1_DisableClock\n

  1817.   *         C2AHB3ENR    AES2EN        LL_C2_AHB3_GRP1_DisableClock\n

  1818.   *         C2AHB3ENR    RNGEN         LL_C2_AHB3_GRP1_DisableClock\n

  1819.   *         C2AHB3ENR    HSEMEN        LL_C2_AHB3_GRP1_DisableClock\n

  1820.   *         C2AHB3ENR    IPCCEN        LL_C2_AHB3_GRP1_DisableClock\n

  1821.   *         C2AHB3ENR    FLASHEN       LL_C2_AHB3_GRP1_DisableClock

  1822.   * @param  Periphs This parameter can be a combination of the following values:

  1823.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA

  1824.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2

  1825.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG

  1826.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM

  1827.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC

  1828.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH

  1829.   * @retval None

  1830.   */

  1831. __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)

  1832. {

  1833.   CLEAR_BIT(RCC->C2AHB3ENR, Periphs);

  1834. }

  1835. 

  1836. /**

  1837.   * @brief  Enable C2AHB3 peripherals clock during Low Power (Sleep) mode.

  1838.   * @rmtoll C2AHB3SMENR  PKASMEN       LL_C2_AHB3_GRP1_EnableClockSleep\n

  1839.   *         C2AHB3SMENR  AES2SMEN      LL_C2_AHB3_GRP1_EnableClockSleep\n

  1840.   *         C2AHB3SMENR  RNGSMEN       LL_C2_AHB3_GRP1_EnableClockSleep\n

  1841.   *         C2AHB3SMENR  SRAM2SMEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

  1842.   *         C2AHB3SMENR  FLASHSMEN     LL_C2_AHB3_GRP1_EnableClockSleep

  1843.   * @param  Periphs This parameter can be a combination of the following values:

  1844.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA

  1845.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2

  1846.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG

  1847.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2

  1848.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH

  1849.   * @retval None

  1850.   */

  1851. __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)

  1852. {

  1853.   __IO uint32_t tmpreg;

  1854.   SET_BIT(RCC->C2AHB3SMENR, Periphs);

  1855.   /* Delay after an RCC peripheral clock enabling */

  1856.   tmpreg = READ_BIT(RCC->C2AHB3SMENR, Periphs);

  1857.   (void)tmpreg;

  1858. }

  1859. 

  1860. /**

  1861.   * @brief  Disable C2AHB3 peripherals clock during Low Power (Sleep) mode.

  1862.   * @rmtoll C2AHB3SMENR  PKASMEN       LL_C2_AHB3_GRP1_DisableClockSleep\n

  1863.   *         C2AHB3SMENR  AES2SMEN      LL_C2_AHB3_GRP1_DisableClockSleep\n

  1864.   *         C2AHB3SMENR  RNGSMEN       LL_C2_AHB3_GRP1_DisableClockSleep\n

  1865.   *         C2AHB3SMENR  SRAM2SMEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

  1866.   *         C2AHB3SMENR  FLASHSMEN     LL_C2_AHB3_GRP1_DisableClockSleep

  1867.   * @param  Periphs This parameter can be a combination of the following values:

  1868.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA

  1869.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2

  1870.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG

  1871.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2

  1872.   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH

  1873.   * @retval None

  1874.   */

  1875. __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)

  1876. {

  1877.   CLEAR_BIT(RCC->C2AHB3SMENR, Periphs);

  1878. }

  1879. 

  1880. /**

  1881.   * @}

  1882.   */

  1883. 

  1884. /** @defgroup BUS_LL_EF_C2_APB1 C2 APB1

  1885.   * @{

  1886.   */

  1887. 

  1888. /**

  1889.   * @brief  Enable C2APB1 peripherals clock.

  1890.   * @rmtoll C2APB1ENR1   TIM2EN        LL_C2_APB1_GRP1_EnableClock\n

  1891.   *         C2APB1ENR1   LCDEN         LL_C2_APB1_GRP1_EnableClock\n

  1892.   *         C2APB1ENR1   RTCAPBEN      LL_C2_APB1_GRP1_EnableClock\n

  1893.   *         C2APB1ENR1   SPI2EN        LL_C2_APB1_GRP1_EnableClock\n

  1894.   *         C2APB1ENR1   I2C1EN        LL_C2_APB1_GRP1_EnableClock\n

  1895.   *         C2APB1ENR1   I2C3EN        LL_C2_APB1_GRP1_EnableClock\n

  1896.   *         C2APB1ENR1   CRSEN         LL_C2_APB1_GRP1_EnableClock\n

  1897.   *         C2APB1ENR1   USBEN         LL_C2_APB1_GRP1_EnableClock\n

  1898.   *         C2APB1ENR1   LPTIM1EN      LL_C2_APB1_GRP1_EnableClock

  1899.   * @param  Periphs This parameter can be a combination of the following values:

  1900.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2

  1901.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)

  1902.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB

  1903.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)

  1904.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1

  1905.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)

  1906.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)

  1907.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)

  1908.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1

  1909.   * @note  (*) Not supported by all the devices

  1910.   * @retval None

  1911.   */

  1912. __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)

  1913. {

  1914.   __IO uint32_t tmpreg;

  1915.   SET_BIT(RCC->C2APB1ENR1, Periphs);

  1916.   /* Delay after an RCC peripheral clock enabling */

  1917.   tmpreg = READ_BIT(RCC->C2APB1ENR1, Periphs);

  1918.   (void)tmpreg;

  1919. }

  1920. 

  1921. /**

  1922.   * @brief  Enable C2APB1 peripherals clock.

  1923.   * @rmtoll C2APB1ENR2   LPUART1EN     LL_C2_APB1_GRP2_EnableClock\n

  1924.   *         C2APB1ENR2   LPTIM2EN      LL_C2_APB1_GRP2_EnableClock

  1925.   * @param  Periphs This parameter can be a combination of the following values:

  1926.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)

  1927.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2

  1928.   * @note  (*) Not supported by all the devices

  1929.   * @retval None

  1930.   */

  1931. __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)

  1932. {

  1933.   __IO uint32_t tmpreg;

  1934.   SET_BIT(RCC->C2APB1ENR2, Periphs);

  1935.   /* Delay after an RCC peripheral clock enabling */

  1936.   tmpreg = READ_BIT(RCC->C2APB1ENR2, Periphs);

  1937.   (void)tmpreg;

  1938. }

  1939. 

  1940. /**

  1941.   * @brief  Check if C2APB1 peripheral clock is enabled or not

  1942.   * @rmtoll C2APB1ENR1   TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  1943.   *         C2APB1ENR1   LCDEN         LL_C2_APB1_GRP1_IsEnabledClock\n

  1944.   *         C2APB1ENR1   RTCAPBEN      LL_C2_APB1_GRP1_IsEnabledClock\n

  1945.   *         C2APB1ENR1   SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  1946.   *         C2APB1ENR1   I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  1947.   *         C2APB1ENR1   I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  1948.   *         C2APB1ENR1   CRSEN         LL_C2_APB1_GRP1_IsEnabledClock\n

  1949.   *         C2APB1ENR1   USBEN         LL_C2_APB1_GRP1_IsEnabledClock\n

  1950.   *         C2APB1ENR1   LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock

  1951.   * @param  Periphs This parameter can be a combination of the following values:

  1952.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2

  1953.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)

  1954.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB

  1955.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)

  1956.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1

  1957.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)

  1958.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)

  1959.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)

  1960.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1

  1961.   * @note  (*) Not supported by all the devices

  1962.   * @retval uint32_t

  1963.   */

  1964. __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

  1965. {

  1966.   return ((READ_BIT(RCC->C2APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);

  1967. }

  1968. 

  1969. /**

  1970.   * @brief  Check if C2APB1 peripheral clock is enabled or not

  1971.   * @rmtoll C2APB1ENR2   LPUART1EN     LL_C2_APB1_GRP2_IsEnabledClock\n

  1972.   *         C2APB1ENR2   LPTIM2EN      LL_C2_APB1_GRP2_IsEnabledClock

  1973.   * @param  Periphs This parameter can be a combination of the following values:

  1974.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)

  1975.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2

  1976.   * @note  (*) Not supported by all the devices

  1977.   * @retval uint32_t

  1978.   */

  1979. __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)

  1980. {

  1981.   return ((READ_BIT(RCC->C2APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);

  1982. }

  1983. 

  1984. /**

  1985.   * @brief  Disable C2APB1 peripherals clock.

  1986.   * @rmtoll C2APB1ENR1   TIM2EN        LL_C2_APB1_GRP1_DisableClock\n

  1987.   *         C2APB1ENR1   LCDEN         LL_C2_APB1_GRP1_DisableClock\n

  1988.   *         C2APB1ENR1   RTCAPBEN      LL_C2_APB1_GRP1_DisableClock\n

  1989.   *         C2APB1ENR1   SPI2EN        LL_C2_APB1_GRP1_DisableClock\n

  1990.   *         C2APB1ENR1   I2C1EN        LL_C2_APB1_GRP1_DisableClock\n

  1991.   *         C2APB1ENR1   I2C3EN        LL_C2_APB1_GRP1_DisableClock\n

  1992.   *         C2APB1ENR1   CRSEN         LL_C2_APB1_GRP1_DisableClock\n

  1993.   *         C2APB1ENR1   USBEN         LL_C2_APB1_GRP1_DisableClock\n

  1994.   *         C2APB1ENR1   LPTIM1EN      LL_C2_APB1_GRP1_DisableClock

  1995.   * @param  Periphs This parameter can be a combination of the following values:

  1996.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2

  1997.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)

  1998.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB

  1999.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)

  2000.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1

  2001.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)

  2002.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)

  2003.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)

  2004.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1

  2005.   * @note  (*) Not supported by all the devices

  2006.   * @retval None

  2007.   */

  2008. __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)

  2009. {

  2010.   CLEAR_BIT(RCC->C2APB1ENR1, Periphs);

  2011. }

  2012. 

  2013. /**

  2014.   * @brief  Disable C2APB1 peripherals clock.

  2015.   * @rmtoll C2APB1ENR2   LPUART1EN     LL_C2_APB1_GRP2_DisableClock\n

  2016.   *         C2APB1ENR2   LPTIM2EN      LL_C2_APB1_GRP2_DisableClock

  2017.   * @param  Periphs This parameter can be a combination of the following values:

  2018.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)

  2019.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2

  2020.   * @note  (*) Not supported by all the devices

  2021.   * @retval None

  2022.   */

  2023. __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)

  2024. {

  2025.   CLEAR_BIT(RCC->C2APB1ENR2, Periphs);

  2026. }

  2027. 

  2028. /**

  2029.   * @brief  Enable C2APB1 peripherals clock during Low Power (Sleep) mode.

  2030.   * @rmtoll C2APB1SMENR1 TIM2SMEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  2031.   *         C2APB1SMENR1 LCDSMEN       LL_C2_APB1_GRP1_EnableClockSleep\n

  2032.   *         C2APB1SMENR1 RTCAPBSMEN    LL_C2_APB1_GRP1_EnableClockSleep\n

  2033.   *         C2APB1SMENR1 SPI2SMEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  2034.   *         C2APB1SMENR1 I2C1SMEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  2035.   *         C2APB1SMENR1 I2C3SMEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  2036.   *         C2APB1SMENR1 CRSSMEN       LL_C2_APB1_GRP1_EnableClockSleep\n

  2037.   *         C2APB1SMENR1 USBSMEN       LL_C2_APB1_GRP1_EnableClockSleep\n

  2038.   *         C2APB1SMENR1 LPTIM1SMEN    LL_C2_APB1_GRP1_EnableClockSleep

  2039.   * @param  Periphs This parameter can be a combination of the following values:

  2040.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2

  2041.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)

  2042.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB

  2043.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)

  2044.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1

  2045.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)

  2046.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)

  2047.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)

  2048.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1

  2049.   * @note  (*) Not supported by all the devices

  2050.   * @retval None

  2051.   */

  2052. __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

  2053. {

  2054.   __IO uint32_t tmpreg;

  2055.   SET_BIT(RCC->C2APB1SMENR1, Periphs);

  2056.   /* Delay after an RCC peripheral clock enabling */

  2057.   tmpreg = READ_BIT(RCC->C2APB1SMENR1, Periphs);

  2058.   (void)tmpreg;

  2059. }

  2060. 

  2061. /**

  2062.   * @brief  Enable C2APB1 peripherals clock during Low Power (Sleep) mode.

  2063.   * @rmtoll C2APB1SMENR2 LPUART1SMEN   LL_C2_APB1_GRP2_EnableClockSleep\n

  2064.   *         C2APB1SMENR2 LPTIM2SMEN    LL_C2_APB1_GRP2_EnableClockSleep

  2065.   * @param  Periphs This parameter can be a combination of the following values:

  2066.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)

  2067.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2

  2068.   * @note  (*) Not supported by all the devices

  2069.   * @retval None

  2070.   */

  2071. __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)

  2072. {

  2073.   __IO uint32_t tmpreg;

  2074.   SET_BIT(RCC->C2APB1SMENR2, Periphs);

  2075.   /* Delay after an RCC peripheral clock enabling */

  2076.   tmpreg = READ_BIT(RCC->C2APB1SMENR2, Periphs);

  2077.   (void)tmpreg;

  2078. }

  2079. 

  2080. /**

  2081.   * @brief  Disable C2APB1 peripherals clock during Low Power (Sleep) mode.

  2082.   * @rmtoll C2APB1SMENR1 TIM2SMEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  2083.   *         C2APB1SMENR1 LCDSMEN       LL_C2_APB1_GRP1_DisableClockSleep\n

  2084.   *         C2APB1SMENR1 RTCAPBSMEN    LL_C2_APB1_GRP1_DisableClockSleep\n

  2085.   *         C2APB1SMENR1 SPI2SMEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  2086.   *         C2APB1SMENR1 I2C1SMEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  2087.   *         C2APB1SMENR1 I2C3SMEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  2088.   *         C2APB1SMENR1 CRSSMEN       LL_C2_APB1_GRP1_DisableClockSleep\n

  2089.   *         C2APB1SMENR1 USBSMEN       LL_C2_APB1_GRP1_DisableClockSleep\n

  2090.   *         C2APB1SMENR1 LPTIM1SMEN    LL_C2_APB1_GRP1_DisableClockSleep

  2091.   * @param  Periphs This parameter can be a combination of the following values:

  2092.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2

  2093.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)

  2094.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB

  2095.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)

  2096.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1

  2097.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)

  2098.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)

  2099.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)

  2100.   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1

  2101.   * @note  (*) Not supported by all the devices

  2102.   * @retval None

  2103.   */

  2104. __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

  2105. {

  2106.   CLEAR_BIT(RCC->C2APB1SMENR1, Periphs);

  2107. }

  2108. 

  2109. /**

  2110.   * @brief  Disable C2APB1 peripherals clock during Low Power (Sleep) mode.

  2111.   * @rmtoll C2APB1SMENR2 LPUART1SMEN   LL_C2_APB1_GRP2_DisableClockSleep\n

  2112.   *         C2APB1SMENR2 LPTIM2SMEN    LL_C2_APB1_GRP2_DisableClockSleep

  2113.   * @param  Periphs This parameter can be a combination of the following values:

  2114.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)

  2115.   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2

  2116.   * @note  (*) Not supported by all the devices

  2117.   * @retval None

  2118.   */

  2119. __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)

  2120. {

  2121.   CLEAR_BIT(RCC->C2APB1SMENR2, Periphs);

  2122. }

  2123. 

  2124. /**

  2125.   * @}

  2126.   */

  2127. 

  2128. /** @defgroup BUS_LL_EF_C2_APB2 C2 APB2

  2129.   * @{

  2130.   */

  2131. 

  2132. /**

  2133.   * @brief  Enable C2APB2 peripherals clock.

  2134.   * @rmtoll C2APB2ENR    ADCEN         LL_C2_APB2_GRP1_EnableClock\n

  2135.   *         C2APB2ENR    TIM1EN        LL_C2_APB2_GRP1_EnableClock\n

  2136.   *         C2APB2ENR    SPI1EN        LL_C2_APB2_GRP1_EnableClock\n

  2137.   *         C2APB2ENR    USART1EN      LL_C2_APB2_GRP1_EnableClock\n

  2138.   *         C2APB2ENR    TIM16EN       LL_C2_APB2_GRP1_EnableClock\n

  2139.   *         C2APB2ENR    TIM17EN       LL_C2_APB2_GRP1_EnableClock\n

  2140.   *         C2APB2ENR    SAI1EN        LL_C2_APB2_GRP1_EnableClock

  2141.   * @param  Periphs This parameter can be a combination of the following values:

  2142.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)

  2143.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1

  2144.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1

  2145.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1

  2146.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)

  2147.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)

  2148.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)

  2149.   * @note  (*) Not supported by all the devices

  2150.   * @retval None

  2151.   */

  2152. __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)

  2153. {

  2154.   __IO uint32_t tmpreg;

  2155.   SET_BIT(RCC->C2APB2ENR, Periphs);

  2156.   /* Delay after an RCC peripheral clock enabling */

  2157.   tmpreg = READ_BIT(RCC->C2APB2ENR, Periphs);

  2158.   (void)tmpreg;

  2159. }

  2160. 

  2161. /**

  2162.   * @brief  Check if C2APB2 peripheral clock is enabled or not

  2163.   * @rmtoll C2APB2ENR    ADCEN         LL_C2_APB2_GRP1_IsEnabledClock\n

  2164.   *         C2APB2ENR    TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  2165.   *         C2APB2ENR    SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  2166.   *         C2APB2ENR    USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n

  2167.   *         C2APB2ENR    TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n

  2168.   *         C2APB2ENR    TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n

  2169.   *         C2APB2ENR    SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock

  2170.   * @param  Periphs This parameter can be a combination of the following values:

  2171.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)

  2172.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1

  2173.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1

  2174.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1

  2175.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)

  2176.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)

  2177.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)

  2178.   * @note  (*) Not supported by all the devices

  2179.   * @retval uint32_t

  2180.   */

  2181. __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

  2182. {

  2183.   return ((READ_BIT(RCC->C2APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  2184. }

  2185. 

  2186. /**

  2187.   * @brief  Disable C2APB2 peripherals clock.

  2188.   * @rmtoll C2APB2ENR    ADCEN         LL_C2_APB2_GRP1_DisableClock\n

  2189.   *         C2APB2ENR    TIM1EN        LL_C2_APB2_GRP1_DisableClock\n

  2190.   *         C2APB2ENR    SPI1EN        LL_C2_APB2_GRP1_DisableClock\n

  2191.   *         C2APB2ENR    USART1EN      LL_C2_APB2_GRP1_DisableClock\n

  2192.   *         C2APB2ENR    TIM16EN       LL_C2_APB2_GRP1_DisableClock\n

  2193.   *         C2APB2ENR    TIM17EN       LL_C2_APB2_GRP1_DisableClock\n

  2194.   *         C2APB2ENR    SAI1EN        LL_C2_APB2_GRP1_DisableClock

  2195.   * @param  Periphs This parameter can be a combination of the following values:

  2196.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)

  2197.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1

  2198.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1

  2199.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1

  2200.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)

  2201.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)

  2202.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)

  2203.   * @note  (*) Not supported by all the devices

  2204.   * @retval None

  2205.   */

  2206. __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)

  2207. {

  2208.   CLEAR_BIT(RCC->C2APB2ENR, Periphs);

  2209. }

  2210. 

  2211. /**

  2212.   * @brief  Enable C2APB2 peripherals clock during Low Power (Sleep) mode.

  2213.   * @rmtoll C2APB2SMENR  ADCSMEN       LL_C2_APB2_GRP1_EnableClockSleep\n

  2214.   *         C2APB2SMENR  TIM1SMEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  2215.   *         C2APB2SMENR  SPI1SMEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  2216.   *         C2APB2SMENR  USART1SMEN    LL_C2_APB2_GRP1_EnableClockSleep\n

  2217.   *         C2APB2SMENR  TIM16SMEN     LL_C2_APB2_GRP1_EnableClockSleep\n

  2218.   *         C2APB2SMENR  TIM17SMEN     LL_C2_APB2_GRP1_EnableClockSleep\n

  2219.   *         C2APB2SMENR  SAI1SMEN      LL_C2_APB2_GRP1_EnableClockSleep

  2220.   * @param  Periphs This parameter can be a combination of the following values:

  2221.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)

  2222.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1

  2223.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1

  2224.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1

  2225.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)

  2226.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)

  2227.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)

  2228.   * @note  (*) Not supported by all the devices

  2229.   * @retval None

  2230.   */

  2231. __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

  2232. {

  2233.   __IO uint32_t tmpreg;

  2234.   SET_BIT(RCC->C2APB2SMENR, Periphs);

  2235.   /* Delay after an RCC peripheral clock enabling */

  2236.   tmpreg = READ_BIT(RCC->C2APB2SMENR, Periphs);

  2237.   (void)tmpreg;

  2238. }

  2239. 

  2240. /**

  2241.   * @brief  Disable C2APB2 peripherals clock during Low Power (Sleep) mode.

  2242.   * @rmtoll C2APB2SMENR  ADCSMEN       LL_C2_APB2_GRP1_DisableClockSleep\n

  2243.   *         C2APB2SMENR  TIM1SMEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  2244.   *         C2APB2SMENR  SPI1SMEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  2245.   *         C2APB2SMENR  USART1SMEN    LL_C2_APB2_GRP1_DisableClockSleep\n

  2246.   *         C2APB2SMENR  TIM16SMEN     LL_C2_APB2_GRP1_DisableClockSleep\n

  2247.   *         C2APB2SMENR  TIM17SMEN     LL_C2_APB2_GRP1_DisableClockSleep\n

  2248.   *         C2APB2SMENR  SAI1SMEN      LL_C2_APB2_GRP1_DisableClockSleep

  2249.   * @param  Periphs This parameter can be a combination of the following values:

  2250.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)

  2251.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1

  2252.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1

  2253.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1

  2254.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)

  2255.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)

  2256.   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)

  2257.   * @note  (*) Not supported by all the devices

  2258.   * @retval None

  2259.   */

  2260. __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

  2261. {

  2262.   CLEAR_BIT(RCC->C2APB2SMENR, Periphs);

  2263. }

  2264. 

  2265. /**

  2266.   * @}

  2267.   */

  2268. 

  2269. /** @defgroup BUS_LL_EF_C2_APB3 C2 APB3

  2270.   * @{

  2271.   */

  2272. 

  2273. /**

  2274.   * @brief  Enable C2APB3 peripherals clock.

  2275.   * @rmtoll C2APB3ENR    BLEEN         LL_C2_APB3_GRP1_EnableClock\n

  2276.   *         C2APB3ENR    802EN         LL_C2_APB3_GRP1_EnableClock (*)

  2277.   * @param  Periphs This parameter can be a combination of the following values:

  2278.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE

  2279.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)

  2280.   * @note  (*) Not supported by all the devices

  2281.   * @retval None

  2282.   */

  2283. __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)

  2284. {

  2285.   __IO uint32_t tmpreg;

  2286.   SET_BIT(RCC->C2APB3ENR, Periphs);

  2287.   /* Delay after an RCC peripheral clock enabling */

  2288.   tmpreg = READ_BIT(RCC->C2APB3ENR, Periphs);

  2289.   (void)tmpreg;

  2290. }

  2291. 

  2292. /**

  2293.   * @brief  Check if C2APB3 peripheral clock is enabled or not

  2294.   * @rmtoll C2APB3ENR    BLEEN         LL_C2_APB3_GRP1_IsEnabledClock\n

  2295.   *         C2APB3ENR    802EN         LL_C2_APB3_GRP1_IsEnabledClock (*)

  2296.   * @param  Periphs This parameter can be a combination of the following values:

  2297.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE

  2298.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)

  2299.   * @note  (*) Not supported by all the devices

  2300.   * @retval uint32_t

  2301.   */

  2302. __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)

  2303. {

  2304.   return ((READ_BIT(RCC->C2APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  2305. }

  2306. 

  2307. /**

  2308.   * @brief  Disable C2APB3 peripherals clock.

  2309.   * @rmtoll C2APB3ENR    BLEEN         LL_C2_APB3_GRP1_DisableClock\n

  2310.   *         C2APB3ENR    802EN         LL_C2_APB3_GRP1_DisableClock (*)

  2311.   * @param  Periphs This parameter can be a combination of the following values:

  2312.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE

  2313.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)

  2314.   * @note  (*) Not supported by all the devices

  2315.   * @retval None

  2316.   */

  2317. __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)

  2318. {

  2319.   CLEAR_BIT(RCC->C2APB3ENR, Periphs);

  2320. }

  2321. 

  2322. /**

  2323.   * @brief  Enable C2APB3 peripherals clock during Low Power (Sleep) mode.

  2324.   * @rmtoll C2APB3SMENR  BLESMEN       LL_C2_APB3_GRP1_EnableClockSleep\n

  2325.   *         C2APB3SMENR  802SMEN       LL_C2_APB3_GRP1_EnableClockSleep (*)

  2326.   * @param  Periphs This parameter can be a combination of the following values:

  2327.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE

  2328.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)

  2329.   * @note  (*) Not supported by all the devices

  2330.   * @retval None

  2331.   */

  2332. __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)

  2333. {

  2334.   __IO uint32_t tmpreg;

  2335.   SET_BIT(RCC->C2APB3SMENR, Periphs);

  2336.   /* Delay after an RCC peripheral clock enabling */

  2337.   tmpreg = READ_BIT(RCC->C2APB3SMENR, Periphs);

  2338.   (void)tmpreg;

  2339. }

  2340. 

  2341. /**

  2342.   * @brief  Disable C2APB3 peripherals clock during Low Power (Sleep) mode.

  2343.   * @rmtoll C2APB3SMENR  BLESMEN       LL_C2_APB3_GRP1_DisableClockSleep\n

  2344.   *         C2APB3SMENR  802SMEN       LL_C2_APB3_GRP1_DisableClockSleep (*)

  2345.   * @param  Periphs This parameter can be a combination of the following values:

  2346.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE

  2347.   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)

  2348.   * @note  (*) Not supported by all the devices

  2349.   * @retval None

  2350.   */

  2351. __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)

  2352. {

  2353.   CLEAR_BIT(RCC->C2APB3SMENR, Periphs);

  2354. }

  2355. 

  2356. /**

  2357.   * @}

  2358.   */

  2359. 

  2360. /**

  2361.   * @}

  2362.   */

  2363. 

  2364. /**

  2365.   * @}

  2366.   */

  2367. 

  2368. #endif /* defined(RCC) */

  2369. 

  2370. /**

  2371.   * @}

  2372.   */

  2373. 

  2374. #ifdef __cplusplus

  2375. }

  2376. #endif

  2377. 

  2378. #endif /* STM32WBxx_LL_BUS_H */

  2379. 

  2380. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/