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  1. /**
  2. ******************************************************************************
  3. * @file stm32wbxx_hal_flash_ex.c
  4. * @author MCD Application Team
  5. * @brief Extended FLASH HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the FLASH extended peripheral:
  8. * + Extended programming operations functions
  9. *
  10. @verbatim
  11. ==============================================================================
  12. ##### Flash Extended features #####
  13. ==============================================================================
  14. [..] Comparing to other previous devices, the FLASH interface for STM32WBxx
  15. devices contains the following additional features
  16. (+) Capacity up to 1 Mbyte with single bank architecture supporting read-while-write
  17. capability (RWW)
  18. (+) Single bank memory organization
  19. (+) PCROP protection
  20. (+) WRP protection
  21. (+) CPU2 Security area
  22. (+) Program Erase Suspend feature
  23. ##### How to use this driver #####
  24. ==============================================================================
  25. [..] This driver provides functions to configure and program the FLASH memory
  26. of all STM32WBxx devices. It includes
  27. (#) Flash Memory Erase functions:
  28. (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
  29. HAL_FLASH_Lock() functions
  30. (++) Erase function: Erase page, erase all sectors
  31. (++) There are two modes of erase :
  32. (+++) Polling Mode using HAL_FLASHEx_Erase()
  33. (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
  34. (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
  35. (++) Set/Reset the write protection (per 4 KByte)
  36. (++) Set the Read protection Level
  37. (++) Program the user Option Bytes
  38. (++) Configure the PCROP protection (per 2 KByte)
  39. (++) Configure the IPCC Buffer start Address
  40. (++) Configure the CPU2 boot region and reset vector start Address
  41. (++) Configure the Flash and SRAM2 secure area
  42. (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
  43. (++) Get the value of a write protection area
  44. (++) Know if the read protection is activated
  45. (++) Get the value of the user Option Bytes
  46. (++) Get the value of a PCROP area
  47. (++) Get the IPCC Buffer start Address
  48. (++) Get the CPU2 boot region and reset vector start Address
  49. (++) Get the Flash and SRAM2 secure area
  50. (#) Flash Suspend, Allow functions:
  51. (++) Suspend or Allow new program or erase operation request using HAL_FLASHEx_SuspendOperation() and
  52. HAL_FLASHEx_AllowOperation() functions
  53. (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck().
  54. and modify this setting (for flash loader purpose e.g.) using
  55. HAL_FLASHEx_ForceFlashEmpty().
  56. @endverbatim
  57. ******************************************************************************
  58. * @attention
  59. *
  60. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
  61. * All rights reserved.</center></h2>
  62. *
  63. * This software component is licensed by ST under BSD 3-Clause license,
  64. * the "License"; You may not use this file except in compliance with the
  65. * License. You may obtain a copy of the License at:
  66. * opensource.org/licenses/BSD-3-Clause
  67. *
  68. ******************************************************************************
  69. */
  70. /* Includes ------------------------------------------------------------------*/
  71. #include "stm32wbxx_hal.h"
  72. /** @addtogroup STM32WBxx_HAL_Driver
  73. * @{
  74. */
  75. /** @defgroup FLASHEx FLASHEx
  76. * @brief FLASH Extended HAL module driver
  77. * @{
  78. */
  79. #ifdef HAL_FLASH_MODULE_ENABLED
  80. /* Private typedef -----------------------------------------------------------*/
  81. /* Private define ------------------------------------------------------------*/
  82. /* Private macro -------------------------------------------------------------*/
  83. /* Private variables ---------------------------------------------------------*/
  84. /* Private function prototypes -----------------------------------------------*/
  85. /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
  86. * @{
  87. */
  88. static void FLASH_AcknowledgePageErase(void);
  89. static void FLASH_FlushCaches(void);
  90. static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
  91. static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel);
  92. static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr);
  93. static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr);
  94. static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr);
  95. static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam);
  96. static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset);
  97. static uint32_t FLASH_OB_GetRDP(void);
  98. static uint32_t FLASH_OB_GetUser(void);
  99. static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr);
  100. static uint32_t FLASH_OB_GetIPCCBufferAddr(void);
  101. static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode);
  102. static void FLASH_OB_GetC2BootResetConfig(uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion);
  103. static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void);
  104. /**
  105. * @}
  106. */
  107. /* Exported functions -------------------------------------------------------*/
  108. /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
  109. * @{
  110. */
  111. /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
  112. * @brief Extended IO operation functions
  113. *
  114. @verbatim
  115. ===============================================================================
  116. ##### Extended programming operation functions #####
  117. ===============================================================================
  118. [..]
  119. This subsection provides a set of functions allowing to manage the Extended FLASH
  120. programming operations Operations.
  121. @endverbatim
  122. * @{
  123. */
  124. /**
  125. * @brief Perform an erase of the specified FLASH memory pages.
  126. * @note Before any operation, it is possible to check there is no operation suspended
  127. * by call HAL_FLASHEx_IsOperationSuspended()
  128. * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
  129. * contains the configuration information for the erasing.
  130. * @param[out] PageError Pointer to variable that contains the configuration
  131. * information on faulty page in case of error (0xFFFFFFFF means that all
  132. * the pages have been correctly erased)
  133. * @retval HAL Status
  134. */
  135. HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
  136. {
  137. HAL_StatusTypeDef status;
  138. uint32_t index;
  139. /* Check the parameters */
  140. assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
  141. /* Process Locked */
  142. __HAL_LOCK(&pFlash);
  143. /* Reset error code */
  144. pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
  145. /* Verify that next operation can be proceed */
  146. status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  147. if (status == HAL_OK)
  148. {
  149. if (pEraseInit->TypeErase == FLASH_TYPEERASE_PAGES)
  150. {
  151. /*Initialization of PageError variable*/
  152. *PageError = 0xFFFFFFFFU;
  153. for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++)
  154. {
  155. /* Start erase page */
  156. FLASH_PageErase(index);
  157. /* Wait for last operation to be completed */
  158. status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  159. if (status != HAL_OK)
  160. {
  161. /* In case of error, stop erase procedure and return the faulty address */
  162. *PageError = index;
  163. break;
  164. }
  165. }
  166. /* If operation is completed or interrupted, disable the Page Erase Bit */
  167. FLASH_AcknowledgePageErase();
  168. }
  169. /* Flush the caches to be sure of the data consistency */
  170. FLASH_FlushCaches();
  171. }
  172. /* Process Unlocked */
  173. __HAL_UNLOCK(&pFlash);
  174. return status;
  175. }
  176. /**
  177. * @brief Perform an erase of the specified FLASH memory pages with interrupt enabled.
  178. * @note Before any operation, it is possible to check there is no operation suspended
  179. * by call HAL_FLASHEx_IsOperationSuspended()
  180. * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
  181. * contains the configuration information for the erasing.
  182. * @retval HAL Status
  183. */
  184. HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
  185. {
  186. HAL_StatusTypeDef status;
  187. /* Check the parameters */
  188. assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
  189. /* Process Locked */
  190. __HAL_LOCK(&pFlash);
  191. /* Reset error code */
  192. pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
  193. /* save procedure for interrupt treatment */
  194. pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
  195. /* Verify that next operation can be proceed */
  196. status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  197. if (status != HAL_OK)
  198. {
  199. /* Process Unlocked */
  200. __HAL_UNLOCK(&pFlash);
  201. }
  202. else
  203. {
  204. /* Enable End of Operation and Error interrupts */
  205. __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
  206. if (pEraseInit->TypeErase == FLASH_TYPEERASE_PAGES)
  207. {
  208. /* Erase by page to be done */
  209. pFlash.NbPagesToErase = pEraseInit->NbPages;
  210. pFlash.Page = pEraseInit->Page;
  211. /*Erase 1st page and wait for IT */
  212. FLASH_PageErase(pEraseInit->Page);
  213. }
  214. }
  215. /* return status */
  216. return status;
  217. }
  218. /**
  219. * @brief Program Option bytes.
  220. * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that
  221. * contains the configuration information for the programming.
  222. * @note To configure any option bytes, the option lock bit OPTLOCK must be
  223. * cleared with the call of @ref HAL_FLASH_OB_Unlock() function.
  224. * @note New option bytes configuration will be taken into account only
  225. * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch()
  226. * - a Power On Reset
  227. * - an exit from Standby or Shutdown mode.
  228. * @retval HAL Status
  229. */
  230. HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
  231. {
  232. uint32_t optr;
  233. HAL_StatusTypeDef status;
  234. /* Check the parameters */
  235. assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
  236. /* Process Locked */
  237. __HAL_LOCK(&pFlash);
  238. pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
  239. /* Write protection configuration */
  240. if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
  241. {
  242. /* Configure of Write protection on the selected area */
  243. FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
  244. }
  245. /* Option register */
  246. if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER))
  247. {
  248. /* Fully modify OPTR register with RDP & user datas */
  249. FLASH_OB_OptrConfig(pOBInit->UserType, pOBInit->UserConfig, pOBInit->RDPLevel);
  250. }
  251. else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
  252. {
  253. /* Only modify RDP so get current user data */
  254. optr = FLASH_OB_GetUser();
  255. /* Remove BOR LEVEL User Type*/
  256. optr &= ~OB_USER_BOR_LEV;
  257. FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel);
  258. }
  259. else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
  260. {
  261. /* Only modify user so get current RDP level */
  262. optr = FLASH_OB_GetRDP();
  263. FLASH_OB_OptrConfig(pOBInit->UserType, pOBInit->UserConfig, optr);
  264. }
  265. else
  266. {
  267. /* Do Nothing */
  268. }
  269. /* PCROP Configuration */
  270. if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
  271. {
  272. /* Check the parameters */
  273. assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig));
  274. if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0U)
  275. {
  276. /* Configure the Zone 1A Proprietary code readout protection */
  277. FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr);
  278. }
  279. if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0U)
  280. {
  281. /* Configure the Zone 1B Proprietary code readout protection */
  282. FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr);
  283. }
  284. }
  285. /* Secure mode and CPU2 Boot Vector */
  286. if ((pOBInit->OptionType & (OPTIONBYTE_SECURE_MODE | OPTIONBYTE_C2_BOOT_VECT)) != 0U)
  287. {
  288. /* Set the secure flash and SRAM memory start address */
  289. FLASH_OB_SecureConfig(pOBInit);
  290. }
  291. /* IPCC mailbox data buffer address */
  292. if ((pOBInit->OptionType & OPTIONBYTE_IPCC_BUF_ADDR) != 0U)
  293. {
  294. /* Configure the IPCC data buffer address */
  295. FLASH_OB_IPCCBufferAddrConfig(pOBInit->IPCCdataBufAddr);
  296. }
  297. /* Proceed the OB Write Operation */
  298. status = FLASH_OB_ProceedWriteOperation();
  299. /* Process Unlocked */
  300. __HAL_UNLOCK(&pFlash);
  301. /* return status */
  302. return status;
  303. }
  304. /**
  305. * @brief Get the Option bytes configuration.
  306. * @note warning: this API only read flash register, it does not reflect any
  307. * change that would have been programmed between previous Option byte
  308. * loading and current call.
  309. * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the
  310. * configuration information. The fields pOBInit->WRPArea and
  311. * pOBInit->PCROPConfig should indicate which area is requested
  312. * for the WRP and PCROP.
  313. * @retval None
  314. */
  315. void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
  316. {
  317. pOBInit->OptionType = OPTIONBYTE_ALL;
  318. if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
  319. {
  320. /* Get write protection on the selected area */
  321. FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
  322. }
  323. /* Get Read protection level */
  324. pOBInit->RDPLevel = FLASH_OB_GetRDP();
  325. /* Get the user option bytes */
  326. pOBInit->UserConfig = FLASH_OB_GetUser();
  327. pOBInit->UserType = OB_USER_ALL;
  328. /* Get the Zone 1A and 1B Proprietary code readout protection */
  329. FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr), &(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr));
  330. pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B);
  331. /* Get the IPCC start Address */
  332. pOBInit->IPCCdataBufAddr = FLASH_OB_GetIPCCBufferAddr();
  333. /* Get the Secure Flash start address, Secure Backup RAM2a start address, Secure non-Backup RAM2b start address and the Security Mode, */
  334. FLASH_OB_GetSecureMemoryConfig(&(pOBInit->SecureFlashStartAddr), &(pOBInit->SecureRAM2aStartAddr), &(pOBInit->SecureRAM2bStartAddr), &(pOBInit->SecureMode));
  335. /* Get the M0+ Secure Boot reset vector and Secure Boot memory selection */
  336. FLASH_OB_GetC2BootResetConfig(&(pOBInit->C2SecureBootVectAddr), &(pOBInit->C2BootRegion));
  337. }
  338. /**
  339. * @brief Flash Empty check
  340. * @note This API checks if first location in Flash is programmed or not.
  341. * This check is done once by Option Byte Loader.
  342. * @retval Returned value can be one of the following values:
  343. * @arg @ref FLASH_PROG_NOT_EMPTY 1st location in Flash is programmed
  344. * @arg @ref FLASH_PROG_EMPTY 1st location in Flash is empty
  345. */
  346. uint32_t HAL_FLASHEx_FlashEmptyCheck(void)
  347. {
  348. return (READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY));
  349. }
  350. /**
  351. * @brief Force Empty check value.
  352. * @note Allows to modify program empty check value in order to force this
  353. * information in Flash Interface, for all next reset that do not launch
  354. * Option Byte Loader.
  355. * @param FlashEmpty Specifies the empty check value
  356. * This parameter can be one of the following values:
  357. * @arg @ref FLASH_PROG_NOT_EMPTY 1st location in Flash is programmed
  358. * @arg @ref FLASH_PROG_EMPTY 1st location in Flash is empty
  359. * @retval None
  360. */
  361. void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty)
  362. {
  363. assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty));
  364. MODIFY_REG(FLASH->ACR, FLASH_ACR_EMPTY, FlashEmpty);
  365. }
  366. /**
  367. * @brief Suspend new program or erase operation request.
  368. * @note Any new Flash program and erase operation on both CPU side will be suspended
  369. * until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are
  370. * cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash
  371. * CPU2 status register (FLASH_C2SR) register will be set when at least one PES
  372. * bit in FLASH_ACR or FLASH_C2ACR is set.
  373. * @retval None
  374. */
  375. void HAL_FLASHEx_SuspendOperation(void)
  376. {
  377. SET_BIT(FLASH->ACR, FLASH_ACR_PES);
  378. }
  379. /**
  380. * @brief Allow new program or erase operation request.
  381. * @note Any new Flash program and erase operation on both CPU side will be allowed
  382. * until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is
  383. * set. The PESD bit in both the Flash status register (FLASH_SR) and Flash
  384. * CPU2 status register (FLASH_C2SR) register will be clear when both PES
  385. * bit in FLASH_ACR or FLASH_C2ACR is cleared.
  386. * @retval None
  387. */
  388. void HAL_FLASHEx_AllowOperation(void)
  389. {
  390. CLEAR_BIT(FLASH->ACR, FLASH_ACR_PES);
  391. }
  392. /**
  393. * @brief Check if new program or erase operation request from CPU1 or CPU2 is suspended
  394. * @note Any new Flash program and erase operation on both CPU side will be allowed
  395. * until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is
  396. * set. The PESD bit in both the Flash status register (FLASH_SR) and Flash
  397. * CPU2 status register (FLASH_C2SR) register will be cleared when both PES
  398. * bit in FLASH_ACR and FLASH_C2ACR are cleared.
  399. * @retval Status
  400. * - 0 : No suspended flash operation
  401. * - 1 : Flash operation is suspended
  402. */
  403. uint32_t HAL_FLASHEx_IsOperationSuspended(void)
  404. {
  405. uint32_t status = 0U;
  406. if (READ_BIT(FLASH->SR, FLASH_SR_PESD) == FLASH_SR_PESD)
  407. {
  408. status = 1U;
  409. }
  410. return status;
  411. }
  412. /**
  413. * @}
  414. */
  415. /**
  416. * @}
  417. */
  418. /* Private functions ---------------------------------------------------------*/
  419. /** @addtogroup FLASHEx_Private_Functions
  420. * @{
  421. */
  422. /**
  423. * @brief Erase the specified FLASH memory page.
  424. * @param Page FLASH page to erase
  425. * This parameter must be a value between 0 and (max number of pages in Flash - 1)
  426. * @retval None
  427. */
  428. void FLASH_PageErase(uint32_t Page)
  429. {
  430. /* Check the parameters */
  431. assert_param(IS_FLASH_PAGE(Page));
  432. /* Proceed to erase the page */
  433. MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER | FLASH_CR_STRT));
  434. }
  435. /**
  436. * @brief Flush the instruction and data caches.
  437. * @retval None
  438. */
  439. static void FLASH_FlushCaches(void)
  440. {
  441. /* Flush instruction cache */
  442. if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) == FLASH_ACR_ICEN)
  443. {
  444. /* Disable instruction cache */
  445. __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
  446. /* Reset instruction cache */
  447. __HAL_FLASH_INSTRUCTION_CACHE_RESET();
  448. /* Enable instruction cache */
  449. __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
  450. }
  451. /* Flush data cache */
  452. if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) == FLASH_ACR_DCEN)
  453. {
  454. /* Disable data cache */
  455. __HAL_FLASH_DATA_CACHE_DISABLE();
  456. /* Reset data cache */
  457. __HAL_FLASH_DATA_CACHE_RESET();
  458. /* Enable data cache */
  459. __HAL_FLASH_DATA_CACHE_ENABLE();
  460. }
  461. }
  462. /**
  463. * @brief Acknlowldge the page erase operation.
  464. * @retval None
  465. */
  466. static void FLASH_AcknowledgePageErase(void)
  467. {
  468. CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
  469. }
  470. /**
  471. * @brief Configure the write protection of the desired pages.
  472. * @note When WRP is active in a zone, it cannot be erased or programmed.
  473. * Consequently, a software mass erase cannot be performed if one zone
  474. * is write-protected.
  475. * @note When the memory read protection level is selected (RDP level = 1),
  476. * it is not possible to program or erase Flash memory if the CPU debug
  477. * features are connected (JTAG or single wire) or boot code is being
  478. * executed from RAM or System flash, even if WRP is not activated.
  479. * @note To configure the WRP options, the option lock bit OPTLOCK must be
  480. * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
  481. * @note To validate the WRP options, the option bytes must be reloaded
  482. * through the call of the @ref HAL_FLASH_OB_Launch() function.
  483. * @param WRPArea Specifies the area to be configured.
  484. * This parameter can be one of the following values:
  485. * @arg @ref OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A
  486. * @arg @ref OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B
  487. * @param WRPStartOffset Specifies the start page of the write protected area
  488. * This parameter can be page number between 0 and (max number of pages in the Flash - 1)
  489. * @param WRDPEndOffset Specifies the end page of the write protected area
  490. * This parameter can be page number between WRPStartOffset and (max number of pages in the Flash - 1)
  491. * @retval None
  492. */
  493. static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
  494. {
  495. /* Check the parameters */
  496. assert_param(IS_OB_WRPAREA(WRPArea));
  497. assert_param(IS_FLASH_PAGE(WRPStartOffset));
  498. assert_param(IS_FLASH_PAGE(WRDPEndOffset));
  499. /* Configure the write protected area */
  500. if (WRPArea == OB_WRPAREA_BANK1_AREAA)
  501. {
  502. MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
  503. (WRPStartOffset | (WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos)));
  504. }
  505. else /* OB_WRPAREA_BANK1_AREAB */
  506. {
  507. MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
  508. (WRPStartOffset | (WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos)));
  509. }
  510. }
  511. /**
  512. * @brief Set user & RDP configuration
  513. * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
  514. * to go back to level 1 or 0 !!!
  515. * @param UserType The FLASH User Option Bytes to be modified
  516. * This parameter can be a combination of all the following values:
  517. * @arg @ref OB_USER_BOR_LEV or @ref OB_USER_nRST_STOP or @ref OB_USER_nRST_STDBY or
  518. * @arg @ref OB_USER_nRST_SHDW or @ref OB_USER_IWDG_SW or @ref OB_USER_IWDG_STOP or
  519. * @arg @ref OB_USER_IWDG_STDBY or @ref OB_USER_WWDG_SW or @ref OB_USER_nBOOT1 or
  520. * @arg @ref OB_USER_SRAM2PE or @ref OB_USER_SRAM2RST or @ref OB_USER_nSWBOOT0 or
  521. * @arg @ref OB_USER_nBOOT0 or @ref OB_USER_AGC_TRIM or @ref OB_USER_ALL
  522. * @param UserConfig The FLASH User Option Bytes values.
  523. * This parameter can be a combination of all the following values:
  524. * @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4
  525. * @arg @ref OB_STOP_RST or @ref OB_STOP_NORST
  526. * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
  527. * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
  528. * @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*)
  529. * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
  530. * @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
  531. * @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
  532. * @arg @ref OB_WWDG_SW or @ref OB_WWDG_HW
  533. * @arg @ref OB_BOOT1_SRAM or @ref OB_BOOT1_SYSTEM
  534. * @arg @ref OB_SRAM2_PARITY_ENABLE or @ref OB_SRAM2_PARITY_DISABLE
  535. * @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
  536. * @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
  537. * @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
  538. * @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*)
  539. * @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
  540. * @param RDPLevel: specifies the read protection level.
  541. * This parameter can be one of the following values:
  542. * @arg @ref OB_RDP_LEVEL_0 No protection
  543. * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
  544. * @arg @ref OB_RDP_LEVEL_2 Full chip protection
  545. * @retval None
  546. */
  547. static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel)
  548. {
  549. uint32_t optr;
  550. /* Check the parameters */
  551. assert_param(IS_OB_USER_TYPE(UserType));
  552. assert_param(IS_OB_USER_CONFIG(UserType, UserConfig));
  553. assert_param(IS_OB_RDP_LEVEL(RDPLevel));
  554. /* Configure the RDP level in the option bytes register */
  555. optr = FLASH->OPTR;
  556. optr &= ~(UserType | FLASH_OPTR_RDP);
  557. FLASH->OPTR = (optr | UserConfig | RDPLevel);
  558. }
  559. /**
  560. * @brief Configure the Zone 1A Proprietary code readout protection of the desired addresses,
  561. * and erase configuration on RDP regression.
  562. * @note To configure the PCROP options, the option lock bit OPTLOCK must be
  563. * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
  564. * @note To validate the PCROP options, the option bytes must be reloaded
  565. * through the call of the @ref HAL_FLASH_OB_Launch() function.
  566. * @param PCROPConfig: specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE)
  567. * on RDP level 1 regression.
  568. * @param PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection
  569. * This parameter can be an address between begin and end of the flash
  570. * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection
  571. * This parameter can be an address between PCROP1AStartAddr and end of the flash
  572. * @retval None
  573. */
  574. static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
  575. {
  576. uint32_t startoffset;
  577. uint32_t endoffset;
  578. uint32_t pcrop1aend;
  579. /* Check the parameters */
  580. assert_param(IS_OB_PCROP_CONFIG(PCROPConfig));
  581. assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AStartAddr));
  582. assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AEndAddr));
  583. /* get pcrop 1A end register */
  584. pcrop1aend = FLASH->PCROP1AER;
  585. /* Configure the Proprietary code readout protection offset */
  586. if ((PCROPConfig & OB_PCROP_ZONE_A) != 0U)
  587. {
  588. /* Compute offset depending on pcrop granularity */
  589. startoffset = ((PCROP1AStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
  590. endoffset = ((PCROP1AEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
  591. /* Set Zone A start offset */
  592. WRITE_REG(FLASH->PCROP1ASR, startoffset);
  593. /* Set Zone A end offset */
  594. pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END;
  595. pcrop1aend |= endoffset;
  596. }
  597. /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */
  598. if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0U)
  599. {
  600. pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP;
  601. }
  602. /* set 1A End register */
  603. WRITE_REG(FLASH->PCROP1AER, pcrop1aend);
  604. }
  605. /**
  606. * @brief Configure the Zone 1B Proprietary code readout protection of the desired addresses.
  607. * @note To configure the PCROP options, the option lock bit OPTLOCK must be
  608. * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
  609. * @note To validate the PCROP options, the option bytes must be reloaded
  610. * through the call of the @ref HAL_FLASH_OB_Launch() function.
  611. * @param PCROP1BStartAddr Specifies the Zone 1BStart address of the Proprietary code readout protection
  612. * This parameter can be an address between begin and end of the flash
  613. * @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection
  614. * This parameter can be an address between PCROP1BStartAddr and end of the flash
  615. * @retval None
  616. */
  617. static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
  618. {
  619. uint32_t startoffset;
  620. uint32_t endoffset;
  621. /* Check the parameters */
  622. assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BStartAddr));
  623. assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BEndAddr));
  624. /* Compute offset depending on pcrop granularity */
  625. startoffset = ((PCROP1BStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
  626. endoffset = ((PCROP1BEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
  627. /* Configure the Proprietary code readout protection start address */
  628. WRITE_REG(FLASH->PCROP1BSR, startoffset);
  629. /* Configure the Proprietary code readout protection end address */
  630. WRITE_REG(FLASH->PCROP1BER, endoffset);
  631. }
  632. /**
  633. * @brief Program the FLASH IPCC data buffer address.
  634. * @note To configure the extra user option bytes, the option lock bit OPTLOCK must
  635. * be cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
  636. * @note To validate the extra user option bytes, the option bytes must be reloaded
  637. * through the call of the @ref HAL_FLASH_OB_Launch() function.
  638. * @param IPCCDataBufAddr IPCC data buffer start address area in SRAM2
  639. * This parameter must be the double-word aligned
  640. * @retval None
  641. */
  642. static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr)
  643. {
  644. assert_param(IS_OB_IPCC_BUF_ADDR(IPCCDataBufAddr));
  645. /* Configure the option bytes register */
  646. WRITE_REG(FLASH->IPCCBR, (uint32_t)((IPCCDataBufAddr - SRAM2A_BASE) >> 4));
  647. }
  648. /**
  649. * @brief Configure the secure start address of the different memories (FLASH and SRAM2),
  650. * the secure mode and the CPU2 Secure Boot reset vector
  651. * @note To configure the PCROP options, the option lock bit OPTLOCK must be
  652. * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
  653. * @param pOBParam Pointer to an @ref FLASH_OBProgramInitTypeDef structure that
  654. * contains the configuration information for the programming
  655. * @retval void
  656. */
  657. static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam)
  658. {
  659. uint32_t sfr_reg_val = READ_REG(FLASH->SFR);
  660. uint32_t srrvr_reg_val = READ_REG(FLASH->SRRVR);
  661. if ((pOBParam->OptionType & OPTIONBYTE_SECURE_MODE) != 0U)
  662. {
  663. assert_param(IS_OB_SFSA_START_ADDR(pOBParam->SecureFlashStartAddr));
  664. assert_param(IS_OB_SBRSA_START_ADDR(pOBParam->SecureRAM2aStartAddr));
  665. assert_param(IS_OB_SNBRSA_START_ADDR(pOBParam->SecureRAM2bStartAddr));
  666. assert_param(IS_OB_SECURE_MODE(pOBParam->SecureMode));
  667. /* Configure SFR register content with start PAGE index to secure */
  668. MODIFY_REG(sfr_reg_val, FLASH_SFR_SFSA, (((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_SFSA_Pos));
  669. /* Configure SRRVR register */
  670. #if defined(FLASH_SRRVR_SBRSA_A)
  671. MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA_A | FLASH_SRRVR_SBRSA_B), \
  672. (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_A_Pos)) | \
  673. ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_B_Pos))));
  674. #else
  675. MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \
  676. (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \
  677. ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos))));
  678. #endif
  679. /* If Full System Secure mode is requested, clear all the corresponding bit */
  680. /* Else set the corresponding bit */
  681. if (pOBParam->SecureMode == SYSTEM_IN_SECURE_MODE)
  682. {
  683. CLEAR_BIT(sfr_reg_val, FLASH_SFR_FSD);
  684. #if defined(FLASH_SRRVR_BRSD_A)
  685. CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B));
  686. #else
  687. CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
  688. #endif
  689. }
  690. else
  691. {
  692. SET_BIT(sfr_reg_val, FLASH_SFR_FSD);
  693. #if defined(FLASH_SRRVR_BRSD_A)
  694. SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B));
  695. #else
  696. SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
  697. #endif
  698. }
  699. /* Update Flash registers */
  700. WRITE_REG(FLASH->SFR, sfr_reg_val);
  701. }
  702. /* Boot vector */
  703. if ((pOBParam->OptionType & OPTIONBYTE_C2_BOOT_VECT) != 0U)
  704. {
  705. /* Check the parameters */
  706. assert_param(IS_OB_BOOT_VECTOR_ADDR(pOBParam->C2SecureBootVectAddr));
  707. assert_param(IS_OB_BOOT_REGION(pOBParam->C2BootRegion));
  708. /* Set the boot vector */
  709. if (pOBParam->C2BootRegion == OB_C2_BOOT_FROM_FLASH)
  710. {
  711. MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (((pOBParam->C2SecureBootVectAddr - FLASH_BASE) >> 2) | pOBParam->C2BootRegion));
  712. }
  713. else
  714. {
  715. MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (((pOBParam->C2SecureBootVectAddr - SRAM1_BASE) >> 2) | pOBParam->C2BootRegion));
  716. }
  717. }
  718. /* Update Flash registers */
  719. WRITE_REG(FLASH->SRRVR, srrvr_reg_val);
  720. }
  721. /**
  722. * @brief Return the FLASH Write Protection Option Bytes value.
  723. * @param[in] WRPArea Specifies the area to be returned.
  724. * This parameter can be one of the following values:
  725. * @arg @ref OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A
  726. * @arg @ref OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B
  727. * @param[out] WRPStartOffset Specifies the address where to copied the start page
  728. * of the write protected area
  729. * @param[out] WRDPEndOffset Specifies the address where to copied the end page of
  730. * the write protected area
  731. * @retval None
  732. */
  733. static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
  734. {
  735. /* Check the parameters */
  736. assert_param(IS_OB_WRPAREA(WRPArea));
  737. /* Get the configuration of the write protected area */
  738. if (WRPArea == OB_WRPAREA_BANK1_AREAA)
  739. {
  740. *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
  741. *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos);
  742. }
  743. else /* OB_WRPAREA_BANK1_AREAB */
  744. {
  745. *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
  746. *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos);
  747. }
  748. }
  749. /**
  750. * @brief Return the FLASH Read Protection level.
  751. * @retval FLASH ReadOut Protection Status:
  752. * This return value can be one of the following values:
  753. * @arg @ref OB_RDP_LEVEL_0 No protection
  754. * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
  755. * @arg @ref OB_RDP_LEVEL_2 Full chip protection
  756. */
  757. static uint32_t FLASH_OB_GetRDP(void)
  758. {
  759. uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
  760. if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2))
  761. {
  762. return (OB_RDP_LEVEL_1);
  763. }
  764. else
  765. {
  766. return rdplvl;
  767. }
  768. }
  769. /**
  770. * @brief Return the FLASH User Option Byte value.
  771. * @retval This return value can be a combination of all the following values:
  772. * @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4
  773. * @arg @ref OB_STOP_RST or @ref OB_STOP_RST
  774. * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
  775. * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
  776. * @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*)
  777. * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
  778. * @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
  779. * @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
  780. * @arg @ref OB_WWDG_SW or @ref OB_WWDG_HW
  781. * @arg @ref OB_BOOT1_SRAM or @ref OB_BOOT1_SYSTEM
  782. * @arg @ref OB_SRAM2_PARITY_ENABLE or @ref OB_SRAM2_PARITY_DISABLE
  783. * @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
  784. * @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
  785. * @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
  786. * @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*)
  787. * @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
  788. */
  789. static uint32_t FLASH_OB_GetUser(void)
  790. {
  791. uint32_t user_config = (READ_REG(FLASH->OPTR) & OB_USER_ALL);
  792. CLEAR_BIT(user_config, (FLASH_OPTR_RDP | FLASH_OPTR_ESE));
  793. return user_config;
  794. }
  795. /**
  796. * @brief Return the FLASH Write Protection Option Bytes value.
  797. * @param PCROPConfig [out] Specifies the address where to copied the configuration of PCROP_RDP option
  798. * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address
  799. * of the Zone 1A Proprietary code readout protection
  800. * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of
  801. * the Zone 1A Proprietary code readout protection
  802. * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address
  803. * of the Zone 1B Proprietary code readout protection
  804. * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of
  805. * the Zone 1B Proprietary code readout protection
  806. * @retval None
  807. */
  808. static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr)
  809. {
  810. uint32_t pcrop;
  811. pcrop = (READ_BIT(FLASH->PCROP1BSR, FLASH_PCROP1BSR_PCROP1B_STRT));
  812. *PCROP1BStartAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
  813. pcrop = (READ_BIT(FLASH->PCROP1BER, FLASH_PCROP1BER_PCROP1B_END));
  814. *PCROP1BEndAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
  815. pcrop = (READ_BIT(FLASH->PCROP1ASR, FLASH_PCROP1ASR_PCROP1A_STRT));
  816. *PCROP1AStartAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
  817. pcrop = (READ_BIT(FLASH->PCROP1AER, FLASH_PCROP1AER_PCROP1A_END));
  818. *PCROP1AEndAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
  819. *PCROPConfig = (READ_REG(FLASH->PCROP1AER) & FLASH_PCROP1AER_PCROP_RDP);
  820. }
  821. /**
  822. * @brief Return the FLASH IPCC data buffer base address Option Byte value.
  823. * @retval Returned value is the IPCC data buffer start address area in SRAM2.
  824. */
  825. static uint32_t FLASH_OB_GetIPCCBufferAddr(void)
  826. {
  827. return (uint32_t)((READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA) << 4) + SRAM2A_BASE);
  828. }
  829. /**
  830. * @brief Return the Secure Flash start address, Secure Backup RAM2a start address, Secure non-Backup RAM2b start address and the SecureMode
  831. * @param SecureFlashStartAddr Specifies the address where to copied the Secure Flash start address
  832. * @param SecureRAM2aStartAddr Specifies the address where to copied the Secure Backup RAM2a start address
  833. * @param SecureRAM2bStartAddr Specifies the address where to copied the Secure non-Backup RAM2b start address
  834. * @param SecureMode Specifies the address where to copied the Secure Mode.
  835. * This return value can be one of the following values:
  836. * @arg @ref SYSTEM_IN_SECURE_MODE : Security enabled
  837. * @arg @ref SYSTEM_NOT_IN_SECURE_MODE : Security disabled
  838. * @retval None
  839. */
  840. static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode)
  841. {
  842. uint32_t sfr_reg_val = READ_REG(FLASH->SFR);
  843. uint32_t srrvr_reg_val = READ_REG(FLASH->SRRVR);
  844. /* Get Secure Flash start address */
  845. uint32_t user_config = (READ_BIT(sfr_reg_val, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos);
  846. *SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE);
  847. /* Get Secure SRAM2a start address */
  848. #if defined(FLASH_SRRVR_SBRSA_A)
  849. user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_A) >> FLASH_SRRVR_SBRSA_A_Pos);
  850. #else
  851. user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos);
  852. #endif
  853. *SecureRAM2aStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2A_BASE);
  854. /* Get Secure SRAM2b start address */
  855. #if defined(FLASH_SRRVR_SBRSA_B)
  856. user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_B) >> FLASH_SRRVR_SBRSA_B_Pos);
  857. #else
  858. user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos);
  859. #endif
  860. *SecureRAM2bStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2B_BASE);
  861. /* Get Secure Area mode */
  862. *SecureMode = (READ_BIT(FLASH->OPTR, FLASH_OPTR_ESE));
  863. }
  864. /**
  865. * @brief Return the CPU2 Secure Boot reset vector address and the CPU2 Secure Boot Region
  866. * @param C2BootResetVectAddr Specifies the address where to copied the CPU2 Secure Boot reset vector address
  867. * @param C2BootResetRegion Specifies the Secure Boot reset memory region
  868. * @retval None
  869. */
  870. static void FLASH_OB_GetC2BootResetConfig(uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion)
  871. {
  872. *C2BootResetRegion = (READ_BIT(FLASH->SRRVR, FLASH_SRRVR_C2OPT));
  873. if (*C2BootResetRegion == OB_C2_BOOT_FROM_FLASH)
  874. {
  875. *C2BootResetVectAddr = (uint32_t)((READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV) << 2) + FLASH_BASE);
  876. }
  877. else
  878. {
  879. *C2BootResetVectAddr = (uint32_t)((READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV) << 2) + SRAM1_BASE);
  880. }
  881. }
  882. /**
  883. * @brief Proceed the OB Write Operation.
  884. * @retval HAL Status
  885. */
  886. static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void)
  887. {
  888. HAL_StatusTypeDef status;
  889. /* Verify that next operation can be proceed */
  890. status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  891. if (status == HAL_OK)
  892. {
  893. /* Set OPTSTRT Bit */
  894. SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
  895. /* Wait for last operation to be completed */
  896. status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  897. }
  898. return status;
  899. }
  900. /**
  901. * @}
  902. */
  903. /**
  904. * @}
  905. */
  906. #endif /* HAL_FLASH_MODULE_ENABLED */
  907. /**
  908. * @}
  909. */
  910. /**
  911. * @}
  912. */
  913. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/