jmg
/
stm32lib
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
23 Commits
1 Branch
14 MiB
 
 
 
Tree: 31732e0e7e
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '31732e0e7e'
${ noResults }
stm32lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h

5994 lines
273 KiB
Raw Blame History 

  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32h7xx_ll_bus.h

  4.   * @author  MCD Application Team

  5.   * @version $VERSION$

  6.   * @date    $DATE$

  7.   * @brief   Header file of BUS LL module.

  8. 

  9.   @verbatim

  10.                       ##### RCC Limitations #####

  11.   ==============================================================================

  12.     [..]

  13.       A delay between an RCC peripheral clock enable and the effective peripheral

  14.       enabling should be taken into account in order to manage the peripheral read/write

  15.       from/to registers.

  16.       (+) This delay depends on the peripheral mapping.

  17.         (++) AHB & APB peripherals, 1 dummy read is necessary

  18. 

  19.     [..]

  20.       Workarounds:

  21.       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been

  22.           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

  23. 

  24.   @endverbatim

  25.   ******************************************************************************

  26.   * @attention

  27.   *

  28.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

  29.   * All rights reserved.</center></h2>

  30.   *

  31.   * This software component is licensed by ST under BSD 3-Clause license,

  32.   * the "License"; You may not use this file except in compliance with the

  33.   * License. You may obtain a copy of the License at:

  34.   *                        opensource.org/licenses/BSD-3-Clause

  35.   *

  36.   ******************************************************************************

  37.   */

  38. 

  39. /* Define to prevent recursive inclusion -------------------------------------*/

  40. #ifndef STM32H7xx_LL_BUS_H

  41. #define STM32H7xx_LL_BUS_H

  42. 

  43. #ifdef __cplusplus

  44. extern "C" {

  45. #endif

  46. 

  47. /* Includes ------------------------------------------------------------------*/

  48. #include "stm32h7xx.h"

  49. 

  50. /** @addtogroup STM32H7xx_LL_Driver

  51.   * @{

  52.   */

  53. 

  54. #if defined(RCC)

  55. 

  56. /** @defgroup BUS_LL BUS

  57.   * @{

  58.   */

  59. 

  60. /* Private variables ---------------------------------------------------------*/

  61. 

  62. /* Private constants ---------------------------------------------------------*/

  63. 

  64. /* Private macros ------------------------------------------------------------*/

  65. 

  66. /* Exported types ------------------------------------------------------------*/

  67. 

  68. /* Exported constants --------------------------------------------------------*/

  69. /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants

  70.   * @{

  71.   */

  72. 

  73. /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH

  74.   * @{

  75.   */

  76. #define LL_AHB3_GRP1_PERIPH_MDMA           RCC_AHB3ENR_MDMAEN

  77. #define LL_AHB3_GRP1_PERIPH_DMA2D          RCC_AHB3ENR_DMA2DEN

  78. 

  79. #if defined(JPEG)

  80. #define LL_AHB3_GRP1_PERIPH_JPGDEC         RCC_AHB3ENR_JPGDECEN

  81. #endif /* JPEG */

  82. 

  83. #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN

  84. #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN

  85. #define LL_AHB3_GRP1_PERIPH_SDMMC1         RCC_AHB3ENR_SDMMC1EN

  86. #define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3LPENR_FLASHLPEN

  87. #define LL_AHB3_GRP1_PERIPH_DTCM1          RCC_AHB3LPENR_DTCM1LPEN

  88. #define LL_AHB3_GRP1_PERIPH_DTCM2          RCC_AHB3LPENR_DTCM2LPEN

  89. #define LL_AHB3_GRP1_PERIPH_ITCM           RCC_AHB3LPENR_ITCMLPEN

  90. #define LL_AHB3_GRP1_PERIPH_AXISRAM        RCC_AHB3LPENR_AXISRAMLPEN

  91. /**

  92.   * @}

  93.   */

  94. 

  95. 

  96. /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH

  97.   * @{

  98.   */

  99. #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN

  100. #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN

  101. #define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHB1ENR_ADC12EN

  102. #if defined(DUAL_CORE)

  103. #define LL_AHB1_GRP1_PERIPH_ART            RCC_AHB1ENR_ARTEN

  104. #endif /* DUAL_CORE */

  105. #define LL_AHB1_GRP1_PERIPH_ETH1MAC        RCC_AHB1ENR_ETH1MACEN

  106. #define LL_AHB1_GRP1_PERIPH_ETH1TX         RCC_AHB1ENR_ETH1TXEN

  107. #define LL_AHB1_GRP1_PERIPH_ETH1RX         RCC_AHB1ENR_ETH1RXEN

  108. #define LL_AHB1_GRP1_PERIPH_USB1OTGHS      RCC_AHB1ENR_USB1OTGHSEN

  109. #define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI  RCC_AHB1ENR_USB1OTGHSULPIEN

  110. #define LL_AHB1_GRP1_PERIPH_USB2OTGHS      RCC_AHB1ENR_USB2OTGHSEN

  111. #define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  RCC_AHB1ENR_USB2OTGHSULPIEN

  112. /**

  113.   * @}

  114.   */

  115. 

  116. 

  117. /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH

  118.   * @{

  119.   */

  120. #define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN

  121. #if defined(CRYP)

  122. #define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN

  123. #endif /* CRYP */

  124. #if defined(HASH)

  125. #define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN

  126. #endif /* HASH */

  127. #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN

  128. #define LL_AHB2_GRP1_PERIPH_SDMMC2         RCC_AHB2ENR_SDMMC2EN

  129. #define LL_AHB2_GRP1_PERIPH_D2SRAM1        RCC_AHB2ENR_D2SRAM1EN

  130. #define LL_AHB2_GRP1_PERIPH_D2SRAM2        RCC_AHB2ENR_D2SRAM2EN

  131. #define LL_AHB2_GRP1_PERIPH_D2SRAM3        RCC_AHB2ENR_D2SRAM3EN

  132. /**

  133.   * @}

  134.   */

  135. 

  136. 

  137. /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH  AHB4 GRP1 PERIPH

  138.   * @{

  139.   */

  140. #define LL_AHB4_GRP1_PERIPH_GPIOA          RCC_AHB4ENR_GPIOAEN

  141. #define LL_AHB4_GRP1_PERIPH_GPIOB          RCC_AHB4ENR_GPIOBEN

  142. #define LL_AHB4_GRP1_PERIPH_GPIOC          RCC_AHB4ENR_GPIOCEN

  143. #define LL_AHB4_GRP1_PERIPH_GPIOD          RCC_AHB4ENR_GPIODEN

  144. #define LL_AHB4_GRP1_PERIPH_GPIOE          RCC_AHB4ENR_GPIOEEN

  145. #define LL_AHB4_GRP1_PERIPH_GPIOF          RCC_AHB4ENR_GPIOFEN

  146. #define LL_AHB4_GRP1_PERIPH_GPIOG          RCC_AHB4ENR_GPIOGEN

  147. #define LL_AHB4_GRP1_PERIPH_GPIOH          RCC_AHB4ENR_GPIOHEN

  148. #define LL_AHB4_GRP1_PERIPH_GPIOI          RCC_AHB4ENR_GPIOIEN

  149. #define LL_AHB4_GRP1_PERIPH_GPIOJ          RCC_AHB4ENR_GPIOJEN

  150. #define LL_AHB4_GRP1_PERIPH_GPIOK          RCC_AHB4ENR_GPIOKEN

  151. #define LL_AHB4_GRP1_PERIPH_CRC            RCC_AHB4ENR_CRCEN

  152. #define LL_AHB4_GRP1_PERIPH_BDMA           RCC_AHB4ENR_BDMAEN

  153. #define LL_AHB4_GRP1_PERIPH_ADC3           RCC_AHB4ENR_ADC3EN

  154. #if defined(HSEM)

  155. #define LL_AHB4_GRP1_PERIPH_HSEM           RCC_AHB4ENR_HSEMEN

  156. #endif /* HSEM */

  157. #define LL_AHB4_GRP1_PERIPH_BKPRAM         RCC_AHB4ENR_BKPRAMEN

  158. #define LL_AHB4_GRP1_PERIPH_D3SRAM1        RCC_AHB4ENR_D3SRAM1EN

  159. /**

  160.   * @}

  161.   */

  162. 

  163. 

  164. /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH

  165.   * @{

  166.   */

  167. #if defined(LTDC)

  168. #define LL_APB3_GRP1_PERIPH_LTDC           RCC_APB3ENR_LTDCEN

  169. #endif /* LTDC */

  170. #if defined(DSI)

  171. #define LL_APB3_GRP1_PERIPH_DSI            RCC_APB3ENR_DSIEN

  172. #endif /* DSI */

  173. #define LL_APB3_GRP1_PERIPH_WWDG1          RCC_APB3ENR_WWDG1EN

  174. /**

  175.   * @}

  176.   */

  177. 

  178. 

  179. /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH

  180.   * @{

  181.   */

  182. #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1LENR_TIM2EN

  183. #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1LENR_TIM3EN

  184. #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1LENR_TIM4EN

  185. #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1LENR_TIM5EN

  186. #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1LENR_TIM6EN

  187. #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1LENR_TIM7EN

  188. #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1LENR_TIM12EN

  189. #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1LENR_TIM13EN

  190. #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1LENR_TIM14EN

  191. #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1LENR_LPTIM1EN

  192. #if defined(DUAL_CORE)

  193. #define LL_APB1_GRP1_PERIPH_WWDG2          RCC_APB1LENR_WWDG2EN

  194. #endif /*DUAL_CORE*/

  195. #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1LENR_SPI2EN

  196. #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1LENR_SPI3EN

  197. #define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1LENR_SPDIFRXEN

  198. #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1LENR_USART2EN

  199. #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1LENR_USART3EN

  200. #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1LENR_UART4EN

  201. #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1LENR_UART5EN

  202. #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1LENR_I2C1EN

  203. #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1LENR_I2C2EN

  204. #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1LENR_I2C3EN

  205. #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1LENR_CECEN

  206. #define LL_APB1_GRP1_PERIPH_DAC12          RCC_APB1LENR_DAC12EN

  207. #define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1LENR_UART7EN

  208. #define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1LENR_UART8EN

  209. /**

  210.   * @}

  211.   */

  212. 

  213. 

  214. /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH

  215.   * @{

  216.   */

  217. #define LL_APB1_GRP2_PERIPH_CRS            RCC_APB1HENR_CRSEN

  218. #define LL_APB1_GRP2_PERIPH_SWPMI1          RCC_APB1HENR_SWPMIEN

  219. #define LL_APB1_GRP2_PERIPH_OPAMP          RCC_APB1HENR_OPAMPEN

  220. #define LL_APB1_GRP2_PERIPH_MDIOS          RCC_APB1HENR_MDIOSEN

  221. #define LL_APB1_GRP2_PERIPH_FDCAN          RCC_APB1HENR_FDCANEN

  222. /**

  223.   * @}

  224.   */

  225. 

  226. 

  227. /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH

  228.   * @{

  229.   */

  230. #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN

  231. #define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN

  232. #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN

  233. #define LL_APB2_GRP1_PERIPH_USART6         RCC_APB2ENR_USART6EN

  234. #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN

  235. #define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN

  236. #define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN

  237. #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN

  238. #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN

  239. #define LL_APB2_GRP1_PERIPH_SPI5           RCC_APB2ENR_SPI5EN

  240. #define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN

  241. #define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN

  242. #define LL_APB2_GRP1_PERIPH_SAI3           RCC_APB2ENR_SAI3EN

  243. #define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN

  244. #define LL_APB2_GRP1_PERIPH_HRTIM          RCC_APB2ENR_HRTIMEN

  245. /**

  246.   * @}

  247.   */

  248. 

  249. 

  250. /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH  APB4 GRP1 PERIPH

  251.   * @{

  252.   */

  253. #define LL_APB4_GRP1_PERIPH_SYSCFG         RCC_APB4ENR_SYSCFGEN

  254. #define LL_APB4_GRP1_PERIPH_LPUART1        RCC_APB4ENR_LPUART1EN

  255. #define LL_APB4_GRP1_PERIPH_SPI6           RCC_APB4ENR_SPI6EN

  256. #define LL_APB4_GRP1_PERIPH_I2C4           RCC_APB4ENR_I2C4EN

  257. #define LL_APB4_GRP1_PERIPH_LPTIM2         RCC_APB4ENR_LPTIM2EN

  258. #define LL_APB4_GRP1_PERIPH_LPTIM3         RCC_APB4ENR_LPTIM3EN

  259. #define LL_APB4_GRP1_PERIPH_LPTIM4         RCC_APB4ENR_LPTIM4EN

  260. #define LL_APB4_GRP1_PERIPH_LPTIM5         RCC_APB4ENR_LPTIM5EN

  261. #define LL_APB4_GRP1_PERIPH_COMP12         RCC_APB4ENR_COMP12EN

  262. #define LL_APB4_GRP1_PERIPH_VREF           RCC_APB4ENR_VREFEN

  263. #define LL_APB4_GRP1_PERIPH_RTCAPB         RCC_APB4ENR_RTCAPBEN

  264. #define LL_APB4_GRP1_PERIPH_SAI4           RCC_APB4ENR_SAI4EN

  265. /**

  266.   * @}

  267.   */

  268. 

  269. /** @defgroup BUS_LL_EC_CLKAM_PERIPH  CLKAM PERIPH

  270.   * @{

  271.   */

  272. #define LL_CLKAM_PERIPH_BDMA          RCC_D3AMR_BDMAAMEN

  273. #define LL_CLKAM_PERIPH_LPUART1       RCC_D3AMR_LPUART1AMEN

  274. #define LL_CLKAM_PERIPH_SPI6          RCC_D3AMR_SPI6AMEN

  275. #define LL_CLKAM_PERIPH_I2C4          RCC_D3AMR_I2C4AMEN

  276. #define LL_CLKAM_PERIPH_LPTIM2        RCC_D3AMR_LPTIM2AMEN

  277. #define LL_CLKAM_PERIPH_LPTIM3        RCC_D3AMR_LPTIM3AMEN

  278. #define LL_CLKAM_PERIPH_LPTIM4        RCC_D3AMR_LPTIM4AMEN

  279. #define LL_CLKAM_PERIPH_LPTIM5        RCC_D3AMR_LPTIM5AMEN

  280. #define LL_CLKAM_PERIPH_COMP12        RCC_D3AMR_COMP12AMEN

  281. #define LL_CLKAM_PERIPH_VREF          RCC_D3AMR_VREFAMEN

  282. #define LL_CLKAM_PERIPH_RTC           RCC_D3AMR_RTCAMEN

  283. #define LL_CLKAM_PERIPH_CRC           RCC_D3AMR_CRCAMEN

  284. #define LL_CLKAM_PERIPH_SAI4          RCC_D3AMR_SAI4AMEN

  285. #define LL_CLKAM_PERIPH_ADC3          RCC_D3AMR_ADC3AMEN

  286. #define LL_CLKAM_PERIPH_BKPRAM        RCC_D3AMR_BKPRAMAMEN

  287. #define LL_CLKAM_PERIPH_SRAM4         RCC_D3AMR_SRAM4AMEN

  288. /**

  289.   * @}

  290.   */

  291. 

  292. /**

  293.   * @}

  294.   */

  295. 

  296. /* Exported macro ------------------------------------------------------------*/

  297. 

  298. /* Exported functions --------------------------------------------------------*/

  299. 

  300. /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions

  301.   * @{

  302.   */

  303. 

  304. /** @defgroup BUS_LL_EF_AHB3 AHB3

  305.   * @{

  306.   */

  307. 

  308. /**

  309.   * @brief  Enable AHB3 peripherals clock.

  310.   * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_EnableClock\n

  311.   *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_EnableClock\n

  312.   *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_EnableClock\n

  313.   *         AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n

  314.   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n

  315.   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_EnableClock\n

  316.   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock\n

  317.   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_EnableClock\n

  318.   *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_EnableClock\n

  319.   *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_EnableClock\n

  320.   *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_EnableClock

  321.   * @param  Periphs This parameter can be a combination of the following values:

  322.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  323.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  324.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

  325.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  326.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  327.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  328.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)

  329.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)

  330.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)

  331.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)

  332.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)

  333.   *

  334.   *         (*) value not defined in all devices.

  335.   * @retval None

  336. */

  337. __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)

  338. {

  339.   __IO uint32_t tmpreg;

  340.   SET_BIT(RCC->AHB3ENR, Periphs);

  341.   /* Delay after an RCC peripheral clock enabling */

  342.   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);

  343.   (void)tmpreg;

  344. }

  345. 

  346. /**

  347.   * @brief  Check if AHB3 peripheral clock is enabled or not

  348.   * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_IsEnabledClock\n

  349.   *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_IsEnabledClock\n

  350.   *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_IsEnabledClock\n

  351.   *         AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n

  352.   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n

  353.   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_IsEnabledClock\n

  354.   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock\n

  355.   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_IsEnabledClock\n

  356.   *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_IsEnabledClock\n

  357.   *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_IsEnabledClock\n

  358.   *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_IsEnabledClock

  359.   * @param  Periphs This parameter can be a combination of the following values:

  360.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  361.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  362.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

  363.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  364.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  365.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  366.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)

  367.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)

  368.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)

  369.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)

  370.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)

  371.   *

  372.   *         (*) value not defined in all devices.

  373.   * @retval uint32_t

  374. */

  375. __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)

  376. {

  377.   return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);

  378. }

  379. 

  380. /**

  381.   * @brief  Disable AHB3 peripherals clock.

  382.   * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_DisableClock\n

  383.   *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_DisableClock\n

  384.   *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_DisableClock\n

  385.   *         AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n

  386.   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n

  387.   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_DisableClock\n

  388.   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock\n

  389.   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_DisableClock\n

  390.   *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_DisableClock\n

  391.   *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_DisableClock\n

  392.   *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_DisableClock

  393.   * @param  Periphs This parameter can be a combination of the following values:

  394.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  395.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  396.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

  397.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  398.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  399.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  400.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)

  401.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)

  402.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)

  403.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)

  404.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)

  405.   *

  406.   *         (*) value not defined in all devices.

  407.   * @retval None

  408. */

  409. __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)

  410. {

  411.   CLEAR_BIT(RCC->AHB3ENR, Periphs);

  412. }

  413. 

  414. /**

  415.   * @brief  Force AHB3 peripherals reset.

  416.   * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ForceReset\n

  417.   *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ForceReset\n

  418.   *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ForceReset\n

  419.   *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n

  420.   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n

  421.   *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ForceReset

  422.   * @param  Periphs This parameter can be a combination of the following values:

  423.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  424.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  425.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

  426.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  427.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  428.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  429.   *

  430.   *         (*) value not defined in all devices.

  431.   * @retval None

  432. */

  433. __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)

  434. {

  435.   SET_BIT(RCC->AHB3RSTR, Periphs);

  436. }

  437. 

  438. /**

  439.   * @brief  Release AHB3 peripherals reset.

  440.   * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ReleaseReset\n

  441.   *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ReleaseReset\n

  442.   *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ReleaseReset\n

  443.   *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n

  444.   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n

  445.   *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ReleaseReset

  446.   * @param  Periphs This parameter can be a combination of the following values:

  447.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  448.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  449.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

  450.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  451.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  452.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  453.   *

  454.   *         (*) value not defined in all devices.

  455.   * @retval None

  456. */

  457. __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)

  458. {

  459.   CLEAR_BIT(RCC->AHB3RSTR, Periphs);

  460. }

  461. 

  462. /**

  463.   * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.

  464.   * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_EnableClockSleep\n

  465.   *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_EnableClockSleep\n

  466.   *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_EnableClockSleep\n

  467.   *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockSleep\n

  468.   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockSleep\n

  469.   *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_EnableClockSleep\n

  470.   *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_EnableClockSleep\n

  471.   *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_EnableClockSleep\n

  472.   *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_EnableClockSleep\n

  473.   *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_EnableClockSleep\n

  474.   *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_EnableClockSleep

  475.   * @param  Periphs This parameter can be a combination of the following values:

  476.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  477.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

  478.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  479.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  480.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  481.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  482.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  483.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  484.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  485.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  486.   *

  487.   *         (*) value not defined in all devices.

  488.   * @retval None

  489. */

  490. __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)

  491. {

  492.   __IO uint32_t tmpreg;

  493.   SET_BIT(RCC->AHB3LPENR, Periphs);

  494.   /* Delay after an RCC peripheral clock enabling */

  495.   tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);

  496.   (void)tmpreg;

  497. }

  498. 

  499. /**

  500.   * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.

  501.   * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_DisableClockSleep\n

  502.   *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_DisableClockSleep\n

  503.   *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_DisableClockSleep\n

  504.   *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockSleep\n

  505.   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockSleep\n

  506.   *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_DisableClockSleep\n

  507.   *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_DisableClockSleep\n

  508.   *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_DisableClockSleep\n

  509.   *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_DisableClockSleep\n

  510.   *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_DisableClockSleep\n

  511.   *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_DisableClockSleep

  512.   * @param  Periphs This parameter can be a combination of the following values:

  513.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  514.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

  515.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  516.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  517.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  518.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  519.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  520.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  521.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  522.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  523.   *

  524.   *         (*) value not defined in all devices.

  525.   * @retval None

  526. */

  527. __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)

  528. {

  529.   CLEAR_BIT(RCC->AHB3LPENR, Periphs);

  530. }

  531. 

  532. /**

  533.   * @}

  534.   */

  535. 

  536. /** @defgroup BUS_LL_EF_AHB1 AHB1

  537.   * @{

  538.   */

  539. 

  540. /**

  541.   * @brief  Enable AHB1 peripherals clock.

  542.   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n

  543.   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n

  544.   *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_EnableClock\n

  545.   *         AHB1ENR      ARTEN         LL_AHB1_GRP1_EnableClock\n

  546.   *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_EnableClock\n

  547.   *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_EnableClock\n

  548.   *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_EnableClock\n

  549.   *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_EnableClock\n

  550.   *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_EnableClock\n

  551.   *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_EnableClock\n

  552.   *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_EnableClock

  553.   * @param  Periphs This parameter can be a combination of the following values:

  554.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  555.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  556.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  557.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

  558.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  559.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  560.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  561.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  562.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  563.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  564.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  565.   *

  566.   *         (*) value not defined in all devices.

  567.   * @retval None

  568. */

  569. __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)

  570. {

  571.   __IO uint32_t tmpreg;

  572.   SET_BIT(RCC->AHB1ENR, Periphs);

  573.   /* Delay after an RCC peripheral clock enabling */

  574.   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);

  575.   (void)tmpreg;

  576. }

  577. 

  578. /**

  579.   * @brief  Check if AHB1 peripheral clock is enabled or not

  580.   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n

  581.   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n

  582.   *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_IsEnabledClock\n

  583.   *         AHB1ENR      ARTEN         LL_AHB1_GRP1_IsEnabledClock\n

  584.   *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_IsEnabledClock\n

  585.   *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_IsEnabledClock\n

  586.   *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_IsEnabledClock\n

  587.   *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n

  588.   *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock\n

  589.   *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n

  590.   *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock

  591.   * @param  Periphs This parameter can be a combination of the following values:

  592.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  593.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  594.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  595.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

  596.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  597.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  598.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  599.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  600.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  601.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  602.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  603.   *

  604.   *         (*) value not defined in all devices.

  605.   * @retval uint32_t

  606. */

  607. __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

  608. {

  609.   return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);

  610. }

  611. 

  612. /**

  613.   * @brief  Disable AHB1 peripherals clock.

  614.   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n

  615.   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n

  616.   *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_DisableClock\n

  617.   *         AHB1ENR      ARTEN         LL_AHB1_GRP1_DisableClock\n

  618.   *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_DisableClock\n

  619.   *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_DisableClock\n

  620.   *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_DisableClock\n

  621.   *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_DisableClock\n

  622.   *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_DisableClock\n

  623.   *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_DisableClock\n

  624.   *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_DisableClock

  625.   * @param  Periphs This parameter can be a combination of the following values:

  626.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  627.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  628.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  629.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

  630.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  631.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  632.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  633.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  634.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  635.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  636.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  637.   *

  638.   *         (*) value not defined in all devices.

  639.   * @retval None

  640. */

  641. __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)

  642. {

  643.   CLEAR_BIT(RCC->AHB1ENR, Periphs);

  644. }

  645. 

  646. /**

  647.   * @brief  Force AHB1 peripherals reset.

  648.   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n

  649.   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n

  650.   *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ForceReset\n

  651.   *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ForceReset\n

  652.   *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ForceReset\n

  653.   *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ForceReset\n

  654.   *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ForceReset

  655.   * @param  Periphs This parameter can be a combination of the following values:

  656.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  657.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  658.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  659.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

  660.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  661.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  662.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  663.   *

  664.   *         (*) value not defined in all devices.

  665.   * @retval None

  666. */

  667. __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)

  668. {

  669.   SET_BIT(RCC->AHB1RSTR, Periphs);

  670. }

  671. 

  672. /**

  673.   * @brief  Release AHB1 peripherals reset.

  674.   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n

  675.   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n

  676.   *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ReleaseReset\n

  677.   *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ReleaseReset\n

  678.   *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ReleaseReset\n

  679.   *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ReleaseReset\n

  680.   *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ReleaseReset

  681.   * @param  Periphs This parameter can be a combination of the following values:

  682.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  683.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  684.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  685.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

  686.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  687.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  688.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  689.   *

  690.   *         (*) value not defined in all devices.

  691.   * @retval None

  692. */

  693. __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)

  694. {

  695.   CLEAR_BIT(RCC->AHB1RSTR, Periphs);

  696. }

  697. 

  698. /**

  699.   * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.

  700.   * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_EnableClockSleep\n

  701.   *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_EnableClockSleep\n

  702.   *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_EnableClockSleep\n

  703.   *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_EnableClockSleep\n

  704.   *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_EnableClockSleep\n

  705.   *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_EnableClockSleep\n

  706.   *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_EnableClockSleep\n

  707.   *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n

  708.   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep\n

  709.   *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n

  710.   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep

  711.   * @param  Periphs This parameter can be a combination of the following values:

  712.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  713.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  714.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  715.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

  716.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  717.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  718.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  719.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  720.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  721.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  722.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  723.   *

  724.   *         (*) value not defined in all devices.

  725.   * @retval None

  726. */

  727. __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

  728. {

  729.   __IO uint32_t tmpreg;

  730.   SET_BIT(RCC->AHB1LPENR, Periphs);

  731.   /* Delay after an RCC peripheral clock enabling */

  732.   tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);

  733.   (void)tmpreg;

  734. }

  735. 

  736. /**

  737.   * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.

  738.   * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_DisableClockSleep\n

  739.   *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_DisableClockSleep\n

  740.   *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_DisableClockSleep\n

  741.   *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_DisableClockSleep\n

  742.   *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_DisableClockSleep\n

  743.   *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_DisableClockSleep\n

  744.   *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_DisableClockSleep\n

  745.   *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n

  746.   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep\n

  747.   *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n

  748.   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep

  749.   * @param  Periphs This parameter can be a combination of the following values:

  750.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  751.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  752.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  753.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

  754.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  755.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  756.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  757.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  758.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  759.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  760.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  761.   *

  762.   *         (*) value not defined in all devices.

  763.   * @retval None

  764. */

  765. __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

  766. {

  767.   CLEAR_BIT(RCC->AHB1LPENR, Periphs);

  768. }

  769. 

  770. /**

  771.   * @}

  772.   */

  773. 

  774. /** @defgroup BUS_LL_EF_AHB2 AHB2

  775.   * @{

  776.   */

  777. 

  778. /**

  779.   * @brief  Enable AHB2 peripherals clock.

  780.   * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\n

  781.   *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_EnableClock\n

  782.   *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\n

  783.   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock\n

  784.   *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_EnableClock\n

  785.   *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_EnableClock\n

  786.   *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_EnableClock\n

  787.   *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_EnableClock

  788.   * @param  Periphs This parameter can be a combination of the following values:

  789.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  790.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  791.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  792.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  793.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  794.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  795.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  796.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  797.   *

  798.   *         (*) value not defined in all devices.

  799.   * @retval None

  800. */

  801. __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)

  802. {

  803.   __IO uint32_t tmpreg;

  804.   SET_BIT(RCC->AHB2ENR, Periphs);

  805.   /* Delay after an RCC peripheral clock enabling */

  806.   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);

  807.   (void)tmpreg;

  808. }

  809. 

  810. /**

  811.   * @brief  Check if AHB2 peripheral clock is enabled or not

  812.   * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\n

  813.   *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_IsEnabledClock\n

  814.   *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\n

  815.   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock\n

  816.   *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_IsEnabledClock\n

  817.   *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_IsEnabledClock\n

  818.   *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_IsEnabledClock\n

  819.   *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_IsEnabledClock

  820.   * @param  Periphs This parameter can be a combination of the following values:

  821.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  822.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  823.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  824.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  825.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  826.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  827.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  828.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  829.   *

  830.   *         (*) value not defined in all devices.

  831.   * @retval uint32_t

  832. */

  833. __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)

  834. {

  835.   return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);

  836. }

  837. 

  838. /**

  839.   * @brief  Disable AHB2 peripherals clock.

  840.   * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\n

  841.   *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_DisableClock\n

  842.   *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\n

  843.   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock\n

  844.   *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_DisableClock\n

  845.   *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_DisableClock\n

  846.   *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_DisableClock\n

  847.   *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_DisableClock

  848.   * @param  Periphs This parameter can be a combination of the following values:

  849.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  850.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  851.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  852.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  853.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  854.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  855.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  856.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  857.   *

  858.   *         (*) value not defined in all devices.

  859.   * @retval None

  860. */

  861. __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)

  862. {

  863.   CLEAR_BIT(RCC->AHB2ENR, Periphs);

  864. }

  865. 

  866. /**

  867.   * @brief  Force AHB2 peripherals reset.

  868.   * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\n

  869.   *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ForceReset\n

  870.   *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n

  871.   *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\n

  872.   *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ForceReset

  873.   * @param  Periphs This parameter can be a combination of the following values:

  874.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  875.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  876.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  877.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  878.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  879.   *

  880.   *         (*) value not defined in all devices.

  881.   * @retval None

  882. */

  883. __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)

  884. {

  885.   SET_BIT(RCC->AHB2RSTR, Periphs);

  886. }

  887. 

  888. /**

  889.   * @brief  Release AHB2 peripherals reset.

  890.   * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\n

  891.   *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ReleaseReset\n

  892.   *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n

  893.   *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\n

  894.   *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ReleaseReset

  895.   * @param  Periphs This parameter can be a combination of the following values:

  896.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  897.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  898.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  899.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  900.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  901.   *

  902.   *         (*) value not defined in all devices.

  903.   * @retval None

  904. */

  905. __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)

  906. {

  907.   CLEAR_BIT(RCC->AHB2RSTR, Periphs);

  908. }

  909. 

  910. /**

  911.   * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.

  912.   * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_EnableClockSleep\n

  913.   *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_EnableClockSleep\n

  914.   *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_EnableClockSleep\n

  915.   *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_EnableClockSleep\n

  916.   *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_EnableClockSleep\n

  917.   *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_EnableClockSleep\n

  918.   *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_EnableClockSleep\n

  919.   *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_EnableClockSleep

  920.   * @param  Periphs This parameter can be a combination of the following values:

  921.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  922.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  923.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  924.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  925.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  926.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  927.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  928.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  929.   *

  930.   *         (*) value not defined in all devices.

  931.   * @retval None

  932. */

  933. __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)

  934. {

  935.   __IO uint32_t tmpreg;

  936.   SET_BIT(RCC->AHB2LPENR, Periphs);

  937.   /* Delay after an RCC peripheral clock enabling */

  938.   tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);

  939.   (void)tmpreg;

  940. }

  941. 

  942. /**

  943.   * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.

  944.   * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_DisableClockSleep\n

  945.   *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_DisableClockSleep\n

  946.   *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_DisableClockSleep\n

  947.   *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_DisableClockSleep\n

  948.   *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_DisableClockSleep\n

  949.   *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_DisableClockSleep\n

  950.   *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_DisableClockSleep\n

  951.   *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_DisableClockSleep

  952.   * @param  Periphs This parameter can be a combination of the following values:

  953.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  954.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  955.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  956.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  957.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  958.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  959.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  960.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  961.   *

  962.   *         (*) value not defined in all devices.

  963.   * @retval None

  964. */

  965. __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)

  966. {

  967.   CLEAR_BIT(RCC->AHB2LPENR, Periphs);

  968. }

  969. 

  970. /**

  971.   * @}

  972.   */

  973. 

  974. /** @defgroup BUS_LL_EF_AHB4 AHB4

  975.   * @{

  976.   */

  977. 

  978. /**

  979.   * @brief  Enable AHB4 peripherals clock.

  980.   * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_EnableClock\n

  981.   *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_EnableClock\n

  982.   *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_EnableClock\n

  983.   *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_EnableClock\n

  984.   *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_EnableClock\n

  985.   *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_EnableClock\n

  986.   *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_EnableClock\n

  987.   *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_EnableClock\n

  988.   *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_EnableClock\n

  989.   *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_EnableClock\n

  990.   *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_EnableClock\n

  991.   *         AHB4ENR      CRCEN         LL_AHB4_GRP1_EnableClock\n

  992.   *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_EnableClock\n

  993.   *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_EnableClock\n

  994.   *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_EnableClock\n

  995.   *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_EnableClock\n

  996.   *         AHB4ENR      D3SRAM1EN     LL_AHB4_GRP1_EnableClock

  997.   * @param  Periphs This parameter can be a combination of the following values:

  998.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  999.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  1000.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  1001.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  1002.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  1003.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  1004.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  1005.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  1006.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  1007.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  1008.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  1009.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  1010.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  1011.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  1012.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  1013.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  1014.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  1015.   *

  1016.   *         (*) value not defined in all devices.

  1017.   * @retval None

  1018. */

  1019. __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)

  1020. {

  1021.   __IO uint32_t tmpreg;

  1022.   SET_BIT(RCC->AHB4ENR, Periphs);

  1023.   /* Delay after an RCC peripheral clock enabling */

  1024.   tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);

  1025.   (void)tmpreg;

  1026. }

  1027. 

  1028. /**

  1029.   * @brief  Check if AHB4 peripheral clock is enabled or not

  1030.   * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_IsEnabledClock\n

  1031.   *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_IsEnabledClock\n

  1032.   *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_IsEnabledClock\n

  1033.   *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_IsEnabledClock\n

  1034.   *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_IsEnabledClock\n

  1035.   *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_IsEnabledClock\n

  1036.   *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_IsEnabledClock\n

  1037.   *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_IsEnabledClock\n

  1038.   *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_IsEnabledClock\n

  1039.   *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_IsEnabledClock\n

  1040.   *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_IsEnabledClock\n

  1041.   *         AHB4ENR      CRCEN         LL_AHB4_GRP1_IsEnabledClock\n

  1042.   *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_IsEnabledClock\n

  1043.   *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_IsEnabledClock\n

  1044.   *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_IsEnabledClock\n

  1045.   *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_IsEnabledClock\n

  1046.   *         AHB4ENR      D3SRAM1EN     LL_AHB4_GRP1_IsEnabledClock

  1047.   * @param  Periphs This parameter can be a combination of the following values:

  1048.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  1049.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  1050.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  1051.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  1052.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  1053.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  1054.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  1055.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  1056.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  1057.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  1058.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  1059.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  1060.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  1061.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  1062.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  1063.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  1064.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  1065.   *

  1066.   *         (*) value not defined in all devices.

  1067.   * @retval uint32_t

  1068. */

  1069. __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)

  1070. {

  1071.   return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);

  1072. }

  1073. 

  1074. /**

  1075.   * @brief  Disable AHB4 peripherals clock.

  1076.   * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_DisableClock\n

  1077.   *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_DisableClock\n

  1078.   *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_DisableClock\n

  1079.   *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_DisableClock\n

  1080.   *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_DisableClock\n

  1081.   *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_DisableClock\n

  1082.   *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_DisableClock\n

  1083.   *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_DisableClock\n

  1084.   *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_DisableClock\n

  1085.   *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_DisableClock\n

  1086.   *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_DisableClock\n

  1087.   *         AHB4ENR      CRCEN         LL_AHB4_GRP1_DisableClock\n

  1088.   *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_DisableClock\n

  1089.   *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_DisableClock\n

  1090.   *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_DisableClock\n

  1091.   *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_DisableClock\n

  1092.   *         AHB4ENR      D3SRAM1EN     LL_AHB4_GRP1_DisableClock

  1093.   * @param  Periphs This parameter can be a combination of the following values:

  1094.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  1095.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  1096.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  1097.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  1098.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  1099.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  1100.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  1101.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  1102.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  1103.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  1104.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  1105.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  1106.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  1107.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  1108.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  1109.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  1110.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  1111.   *

  1112.   *         (*) value not defined in all devices.

  1113.   * @retval None

  1114. */

  1115. __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)

  1116. {

  1117.   CLEAR_BIT(RCC->AHB4ENR, Periphs);

  1118. }

  1119. 

  1120. /**

  1121.   * @brief  Force AHB4 peripherals reset.

  1122.   * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ForceReset\n

  1123.   *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ForceReset\n

  1124.   *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ForceReset\n

  1125.   *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ForceReset\n

  1126.   *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ForceReset\n

  1127.   *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ForceReset\n

  1128.   *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ForceReset\n

  1129.   *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ForceReset\n

  1130.   *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ForceReset\n

  1131.   *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ForceReset\n

  1132.   *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ForceReset\n

  1133.   *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ForceReset\n

  1134.   *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ForceReset\n

  1135.   *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ForceReset\n

  1136.   *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ForceReset

  1137.   * @param  Periphs This parameter can be a combination of the following values:

  1138.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  1139.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  1140.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  1141.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  1142.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  1143.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  1144.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  1145.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  1146.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  1147.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  1148.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  1149.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  1150.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  1151.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  1152.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  1153.   *

  1154.   *         (*) value not defined in all devices.

  1155.   * @retval None

  1156. */

  1157. __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)

  1158. {

  1159.   SET_BIT(RCC->AHB4RSTR, Periphs);

  1160. }

  1161. 

  1162. /**

  1163.   * @brief  Release AHB4 peripherals reset.

  1164.   * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ReleaseReset\n

  1165.   *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ReleaseReset\n

  1166.   *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ReleaseReset\n

  1167.   *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ReleaseReset\n

  1168.   *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ReleaseReset\n

  1169.   *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ReleaseReset\n

  1170.   *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ReleaseReset\n

  1171.   *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ReleaseReset\n

  1172.   *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ReleaseReset\n

  1173.   *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ReleaseReset\n

  1174.   *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ReleaseReset\n

  1175.   *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ReleaseReset\n

  1176.   *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ReleaseReset\n

  1177.   *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ReleaseReset\n

  1178.   *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ReleaseReset

  1179.   * @param  Periphs This parameter can be a combination of the following values:

  1180.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  1181.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  1182.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  1183.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  1184.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  1185.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  1186.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  1187.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  1188.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  1189.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  1190.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  1191.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  1192.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  1193.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  1194.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  1195.   *

  1196.   *         (*) value not defined in all devices.

  1197.   * @retval None

  1198. */

  1199. __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)

  1200. {

  1201.   CLEAR_BIT(RCC->AHB4RSTR, Periphs);

  1202. }

  1203. 

  1204. /**

  1205.   * @brief  Enable AHB4 peripherals clock during Low Power (Sleep) mode.

  1206.   * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1207.   *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1208.   *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1209.   *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1210.   *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1211.   *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1212.   *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1213.   *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1214.   *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1215.   *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1216.   *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_EnableClockSleep\n

  1217.   *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_EnableClockSleep\n

  1218.   *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_EnableClockSleep\n

  1219.   *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_EnableClockSleep\n

  1220.   *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_EnableClockSleep\n

  1221.   *         AHB4LPENR    D3SRAM1LPEN   LL_AHB4_GRP1_EnableClockSleep

  1222.   * @param  Periphs This parameter can be a combination of the following values:

  1223.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  1224.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  1225.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  1226.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  1227.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  1228.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  1229.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  1230.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  1231.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  1232.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  1233.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  1234.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  1235.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  1236.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  1237.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  1238.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  1239.   * @retval None

  1240. */

  1241. __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)

  1242. {

  1243.   __IO uint32_t tmpreg;

  1244.   SET_BIT(RCC->AHB4LPENR, Periphs);

  1245.   /* Delay after an RCC peripheral clock enabling */

  1246.   tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);

  1247.   (void)tmpreg;

  1248. }

  1249. 

  1250. /**

  1251.   * @brief  Disable AHB4 peripherals clock during Low Power (Sleep) mode.

  1252.   * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1253.   *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1254.   *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1255.   *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1256.   *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1257.   *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1258.   *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1259.   *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1260.   *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1261.   *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1262.   *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_DisableClockSleep\n

  1263.   *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_DisableClockSleep\n

  1264.   *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_DisableClockSleep\n

  1265.   *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_DisableClockSleep\n

  1266.   *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_DisableClockSleep\n

  1267.   *         AHB4LPENR    D3SRAM1LPEN   LL_AHB4_GRP1_DisableClockSleep

  1268.   * @param  Periphs This parameter can be a combination of the following values:

  1269.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  1270.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  1271.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  1272.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  1273.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  1274.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  1275.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  1276.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  1277.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  1278.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  1279.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  1280.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  1281.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  1282.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  1283.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  1284.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  1285.   * @retval None

  1286. */

  1287. __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)

  1288. {

  1289.   CLEAR_BIT(RCC->AHB4LPENR, Periphs);

  1290. }

  1291. 

  1292. /**

  1293.   * @}

  1294.   */

  1295. 

  1296. /** @defgroup BUS_LL_EF_APB3 APB3

  1297.   * @{

  1298.   */

  1299. 

  1300. /**

  1301.   * @brief  Enable APB3 peripherals clock.

  1302.   * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_EnableClock\n

  1303.   *         APB3ENR      DSIEN         LL_APB3_GRP1_EnableClock\n

  1304.   *         APB3ENR      WWDG1EN       LL_APB3_GRP1_EnableClock

  1305.   * @param  Periphs This parameter can be a combination of the following values:

  1306.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

  1307.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  1308.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  1309.   *

  1310.   *         (*) value not defined in all devices.

  1311.   * @retval None

  1312. */

  1313. __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)

  1314. {

  1315.   __IO uint32_t tmpreg;

  1316.   SET_BIT(RCC->APB3ENR, Periphs);

  1317.   /* Delay after an RCC peripheral clock enabling */

  1318.   tmpreg = READ_BIT(RCC->APB3ENR, Periphs);

  1319.   (void)tmpreg;

  1320. }

  1321. 

  1322. /**

  1323.   * @brief  Check if APB3 peripheral clock is enabled or not

  1324.   * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_IsEnabledClock\n

  1325.   *         APB3ENR      DSIEN         LL_APB3_GRP1_IsEnabledClock\n

  1326.   *         APB3ENR      WWDG1EN       LL_APB3_GRP1_IsEnabledClock

  1327.   * @param  Periphs This parameter can be a combination of the following values:

  1328.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

  1329.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  1330.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  1331.   *

  1332.   *         (*) value not defined in all devices.

  1333.   * @retval uint32_t

  1334. */

  1335. __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)

  1336. {

  1337.   return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);

  1338. }

  1339. 

  1340. /**

  1341.   * @brief  Disable APB3 peripherals clock.

  1342.   * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_DisableClock\n

  1343.   *         APB3ENR      DSIEN         LL_APB3_GRP1_DisableClock\n

  1344.   *         APB3ENR      WWDG1EN       LL_APB3_GRP1_DisableClock

  1345.   * @param  Periphs This parameter can be a combination of the following values:

  1346.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

  1347.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  1348.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  1349.   *

  1350.   *         (*) value not defined in all devices.

  1351.   * @retval None

  1352. */

  1353. __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)

  1354. {

  1355.   CLEAR_BIT(RCC->APB3ENR, Periphs);

  1356. }

  1357. 

  1358. /**

  1359.   * @brief  Force APB3 peripherals reset.

  1360.   * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ForceReset\n

  1361.   *         APB3RSTR     DSIRST        LL_APB3_GRP1_ForceReset

  1362.   * @param  Periphs This parameter can be a combination of the following values:

  1363.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

  1364.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  1365.   *

  1366.   *         (*) value not defined in all devices.

  1367.   * @retval None

  1368. */

  1369. __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)

  1370. {

  1371.   SET_BIT(RCC->APB3RSTR, Periphs);

  1372. }

  1373. 

  1374. /**

  1375.   * @brief  Release APB3 peripherals reset.

  1376.   * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ReleaseReset\n

  1377.   *         APB3RSTR     DSIRST        LL_APB3_GRP1_ReleaseReset

  1378.   * @param  Periphs This parameter can be a combination of the following values:

  1379.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

  1380.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  1381.   *

  1382.   *         (*) value not defined in all devices.

  1383.   * @retval None

  1384. */

  1385. __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)

  1386. {

  1387.   CLEAR_BIT(RCC->APB3RSTR, Periphs);

  1388. }

  1389. 

  1390. /**

  1391.   * @brief  Enable APB3 peripherals clock during Low Power (Sleep) mode.

  1392.   * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_EnableClockSleep\n

  1393.   *         APB3LPENR    DSILPEN       LL_APB3_GRP1_EnableClockSleep\n

  1394.   *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_EnableClockSleep

  1395.   * @param  Periphs This parameter can be a combination of the following values:

  1396.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

  1397.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  1398.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  1399.   *

  1400.   *         (*) value not defined in all devices.

  1401.   * @retval None

  1402. */

  1403. __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)

  1404. {

  1405.   __IO uint32_t tmpreg;

  1406.   SET_BIT(RCC->APB3LPENR, Periphs);

  1407.   /* Delay after an RCC peripheral clock enabling */

  1408.   tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);

  1409.   (void)tmpreg;

  1410. }

  1411. 

  1412. /**

  1413.   * @brief  Disable APB3 peripherals clock during Low Power (Sleep) mode.

  1414.   * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_DisableClockSleep\n

  1415.   *         APB3LPENR    DSILPEN       LL_APB3_GRP1_DisableClockSleep\n

  1416.   *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_DisableClockSleep

  1417.   * @param  Periphs This parameter can be a combination of the following values:

  1418.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

  1419.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  1420.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  1421.   *

  1422.   *         (*) value not defined in all devices.

  1423.   * @retval None

  1424. */

  1425. __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)

  1426. {

  1427.   CLEAR_BIT(RCC->APB3LPENR, Periphs);

  1428. }

  1429. 

  1430. /**

  1431.   * @}

  1432.   */

  1433. 

  1434. /** @defgroup BUS_LL_EF_APB1 APB1

  1435.   * @{

  1436.   */

  1437. 

  1438. /**

  1439.   * @brief  Enable APB1 peripherals clock.

  1440.   * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_EnableClock\n

  1441.   *         APB1LENR     TIM3EN        LL_APB1_GRP1_EnableClock\n

  1442.   *         APB1LENR     TIM4EN        LL_APB1_GRP1_EnableClock\n

  1443.   *         APB1LENR     TIM5EN        LL_APB1_GRP1_EnableClock\n

  1444.   *         APB1LENR     TIM6EN        LL_APB1_GRP1_EnableClock\n

  1445.   *         APB1LENR     TIM7EN        LL_APB1_GRP1_EnableClock\n

  1446.   *         APB1LENR     TIM12EN       LL_APB1_GRP1_EnableClock\n

  1447.   *         APB1LENR     TIM13EN       LL_APB1_GRP1_EnableClock\n

  1448.   *         APB1LENR     TIM14EN       LL_APB1_GRP1_EnableClock\n

  1449.   *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n

  1450.   *         APB1LENR     WWDG2EN       LL_APB1_GRP1_EnableClock\n

  1451.   *         APB1LENR     SPI2EN        LL_APB1_GRP1_EnableClock\n

  1452.   *         APB1LENR     SPI3EN        LL_APB1_GRP1_EnableClock\n

  1453.   *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n

  1454.   *         APB1LENR     USART2EN      LL_APB1_GRP1_EnableClock\n

  1455.   *         APB1LENR     USART3EN      LL_APB1_GRP1_EnableClock\n

  1456.   *         APB1LENR     UART4EN       LL_APB1_GRP1_EnableClock\n

  1457.   *         APB1LENR     UART5EN       LL_APB1_GRP1_EnableClock\n

  1458.   *         APB1LENR     I2C1EN        LL_APB1_GRP1_EnableClock\n

  1459.   *         APB1LENR     I2C2EN        LL_APB1_GRP1_EnableClock\n

  1460.   *         APB1LENR     I2C3EN        LL_APB1_GRP1_EnableClock\n

  1461.   *         APB1LENR     CECEN         LL_APB1_GRP1_EnableClock\n

  1462.   *         APB1LENR     DAC12EN       LL_APB1_GRP1_EnableClock\n

  1463.   *         APB1LENR     UART7EN       LL_APB1_GRP1_EnableClock\n

  1464.   *         APB1LENR     UART8EN       LL_APB1_GRP1_EnableClock

  1465.   * @param  Periphs This parameter can be a combination of the following values:

  1466.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1467.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  1468.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  1469.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  1470.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  1471.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  1472.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  1473.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  1474.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  1475.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1476.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

  1477.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  1478.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  1479.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  1480.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  1481.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  1482.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  1483.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  1484.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1485.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  1486.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  1487.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  1488.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  1489.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  1490.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  1491.   *

  1492.   *         (*) value not defined in all devices.

  1493.   * @retval None

  1494. */

  1495. __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)

  1496. {

  1497.   __IO uint32_t tmpreg;

  1498.   SET_BIT(RCC->APB1LENR, Periphs);

  1499.   /* Delay after an RCC peripheral clock enabling */

  1500.   tmpreg = READ_BIT(RCC->APB1LENR, Periphs);

  1501.   (void)tmpreg;

  1502. }

  1503. 

  1504. /**

  1505.   * @brief  Check if APB1 peripheral clock is enabled or not

  1506.   * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n

  1507.   *         APB1LENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n

  1508.   *         APB1LENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n

  1509.   *         APB1LENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n

  1510.   *         APB1LENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n

  1511.   *         APB1LENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n

  1512.   *         APB1LENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n

  1513.   *         APB1LENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n

  1514.   *         APB1LENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n

  1515.   *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n

  1516.   *         APB1LENR     WWDG2EN       LL_APB1_GRP1_IsEnabledClock\n

  1517.   *         APB1LENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n

  1518.   *         APB1LENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n

  1519.   *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n

  1520.   *         APB1LENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n

  1521.   *         APB1LENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n

  1522.   *         APB1LENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n

  1523.   *         APB1LENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n

  1524.   *         APB1LENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n

  1525.   *         APB1LENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n

  1526.   *         APB1LENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n

  1527.   *         APB1LENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n

  1528.   *         APB1LENR     DAC12EN       LL_APB1_GRP1_IsEnabledClock\n

  1529.   *         APB1LENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n

  1530.   *         APB1LENR     UART8EN       LL_APB1_GRP1_IsEnabledClock

  1531.   * @param  Periphs This parameter can be a combination of the following values:

  1532.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1533.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  1534.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  1535.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  1536.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  1537.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  1538.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  1539.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  1540.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  1541.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1542.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

  1543.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  1544.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  1545.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  1546.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  1547.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  1548.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  1549.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  1550.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1551.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  1552.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  1553.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  1554.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  1555.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  1556.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  1557.   *

  1558.   *         (*) value not defined in all devices.

  1559.   * @retval uint32_t

  1560. */

  1561. __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

  1562. {

  1563.   return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);

  1564. }

  1565. 

  1566. /**

  1567.   * @brief  Disable APB1 peripherals clock.

  1568.   * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_DisableClock\n

  1569.   *         APB1LENR     TIM3EN        LL_APB1_GRP1_DisableClock\n

  1570.   *         APB1LENR     TIM4EN        LL_APB1_GRP1_DisableClock\n

  1571.   *         APB1LENR     TIM5EN        LL_APB1_GRP1_DisableClock\n

  1572.   *         APB1LENR     TIM6EN        LL_APB1_GRP1_DisableClock\n

  1573.   *         APB1LENR     TIM7EN        LL_APB1_GRP1_DisableClock\n

  1574.   *         APB1LENR     TIM12EN       LL_APB1_GRP1_DisableClock\n

  1575.   *         APB1LENR     TIM13EN       LL_APB1_GRP1_DisableClock\n

  1576.   *         APB1LENR     TIM14EN       LL_APB1_GRP1_DisableClock\n

  1577.   *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n

  1578.   *         APB1LENR     WWDG2EN       LL_APB1_GRP1_DisableClock\n

  1579.   *         APB1LENR     SPI2EN        LL_APB1_GRP1_DisableClock\n

  1580.   *         APB1LENR     SPI3EN        LL_APB1_GRP1_DisableClock\n

  1581.   *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n

  1582.   *         APB1LENR     USART2EN      LL_APB1_GRP1_DisableClock\n

  1583.   *         APB1LENR     USART3EN      LL_APB1_GRP1_DisableClock\n

  1584.   *         APB1LENR     UART4EN       LL_APB1_GRP1_DisableClock\n

  1585.   *         APB1LENR     UART5EN       LL_APB1_GRP1_DisableClock\n

  1586.   *         APB1LENR     I2C1EN        LL_APB1_GRP1_DisableClock\n

  1587.   *         APB1LENR     I2C2EN        LL_APB1_GRP1_DisableClock\n

  1588.   *         APB1LENR     I2C3EN        LL_APB1_GRP1_DisableClock\n

  1589.   *         APB1LENR     CECEN         LL_APB1_GRP1_DisableClock\n

  1590.   *         APB1LENR     DAC12EN       LL_APB1_GRP1_DisableClock\n

  1591.   *         APB1LENR     UART7EN       LL_APB1_GRP1_DisableClock\n

  1592.   *         APB1LENR     UART8EN       LL_APB1_GRP1_DisableClock

  1593.   * @param  Periphs This parameter can be a combination of the following values:

  1594.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1595.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  1596.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  1597.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  1598.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  1599.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  1600.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  1601.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  1602.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  1603.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1604.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

  1605.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  1606.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  1607.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  1608.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  1609.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  1610.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  1611.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  1612.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1613.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  1614.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  1615.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  1616.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  1617.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  1618.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  1619.   *

  1620.   *         (*) value not defined in all devices.

  1621.   * @retval None

  1622. */

  1623. __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)

  1624. {

  1625.   CLEAR_BIT(RCC->APB1LENR, Periphs);

  1626. }

  1627. 

  1628. /**

  1629.   * @brief  Force APB1 peripherals reset.

  1630.   * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ForceReset\n

  1631.   *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ForceReset\n

  1632.   *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ForceReset\n

  1633.   *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ForceReset\n

  1634.   *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ForceReset\n

  1635.   *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ForceReset\n

  1636.   *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ForceReset\n

  1637.   *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ForceReset\n

  1638.   *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ForceReset\n

  1639.   *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ForceReset\n

  1640.   *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ForceReset\n

  1641.   *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ForceReset\n

  1642.   *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ForceReset\n

  1643.   *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ForceReset\n

  1644.   *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ForceReset\n

  1645.   *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ForceReset\n

  1646.   *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ForceReset\n

  1647.   *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ForceReset\n

  1648.   *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ForceReset\n

  1649.   *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ForceReset\n

  1650.   *         APB1LRSTR    CECRST        LL_APB1_GRP1_ForceReset\n

  1651.   *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ForceReset\n

  1652.   *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ForceReset\n

  1653.   *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ForceReset

  1654.   * @param  Periphs This parameter can be a combination of the following values:

  1655.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1656.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  1657.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  1658.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  1659.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  1660.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  1661.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  1662.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  1663.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  1664.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1665.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  1666.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  1667.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  1668.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  1669.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  1670.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  1671.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  1672.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1673.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  1674.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  1675.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  1676.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  1677.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  1678.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  1679.   * @retval None

  1680. */

  1681. __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)

  1682. {

  1683.   SET_BIT(RCC->APB1LRSTR, Periphs);

  1684. }

  1685. 

  1686. /**

  1687.   * @brief  Release APB1 peripherals reset.

  1688.   * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ReleaseReset\n

  1689.   *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ReleaseReset\n

  1690.   *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ReleaseReset\n

  1691.   *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ReleaseReset\n

  1692.   *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ReleaseReset\n

  1693.   *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ReleaseReset\n

  1694.   *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ReleaseReset\n

  1695.   *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ReleaseReset\n

  1696.   *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ReleaseReset\n

  1697.   *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ReleaseReset\n

  1698.   *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ReleaseReset\n

  1699.   *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ReleaseReset\n

  1700.   *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ReleaseReset\n

  1701.   *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ReleaseReset\n

  1702.   *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ReleaseReset\n

  1703.   *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ReleaseReset\n

  1704.   *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ReleaseReset\n

  1705.   *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ReleaseReset\n

  1706.   *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ReleaseReset\n

  1707.   *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ReleaseReset\n

  1708.   *         APB1LRSTR    CECRST        LL_APB1_GRP1_ReleaseReset\n

  1709.   *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ReleaseReset\n

  1710.   *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ReleaseReset\n

  1711.   *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ReleaseReset

  1712.   * @param  Periphs This parameter can be a combination of the following values:

  1713.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1714.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  1715.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  1716.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  1717.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  1718.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  1719.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  1720.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  1721.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  1722.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1723.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  1724.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  1725.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  1726.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  1727.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  1728.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  1729.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  1730.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1731.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  1732.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  1733.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  1734.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  1735.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  1736.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  1737.   * @retval None

  1738. */

  1739. __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)

  1740. {

  1741.   CLEAR_BIT(RCC->APB1LRSTR, Periphs);

  1742. }

  1743. 

  1744. /**

  1745.   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.

  1746.   * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1747.   *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1748.   *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1749.   *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1750.   *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1751.   *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1752.   *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_EnableClockSleep\n

  1753.   *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_EnableClockSleep\n

  1754.   *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_EnableClockSleep\n

  1755.   *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_EnableClockSleep\n

  1756.   *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_EnableClockSleep\n

  1757.   *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1758.   *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1759.   *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_EnableClockSleep\n

  1760.   *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_EnableClockSleep\n

  1761.   *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_EnableClockSleep\n

  1762.   *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_EnableClockSleep\n

  1763.   *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_EnableClockSleep\n

  1764.   *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1765.   *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1766.   *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_EnableClockSleep\n

  1767.   *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_EnableClockSleep\n

  1768.   *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_EnableClockSleep\n

  1769.   *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_EnableClockSleep\n

  1770.   *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_EnableClockSleep

  1771.   * @param  Periphs This parameter can be a combination of the following values:

  1772.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1773.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  1774.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  1775.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  1776.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  1777.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  1778.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  1779.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  1780.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  1781.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1782.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

  1783.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  1784.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  1785.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  1786.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  1787.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  1788.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  1789.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  1790.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1791.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  1792.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  1793.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  1794.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  1795.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  1796.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  1797.   *

  1798.   *         (*) value not defined in all devices.

  1799.   * @retval None

  1800. */

  1801. __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

  1802. {

  1803.   __IO uint32_t tmpreg;

  1804.   SET_BIT(RCC->APB1LLPENR, Periphs);

  1805.   /* Delay after an RCC peripheral clock enabling */

  1806.   tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);

  1807.   (void)tmpreg;

  1808. }

  1809. 

  1810. /**

  1811.   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.

  1812.   * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1813.   *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1814.   *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1815.   *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1816.   *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1817.   *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1818.   *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_DisableClockSleep\n

  1819.   *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_DisableClockSleep\n

  1820.   *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_DisableClockSleep\n

  1821.   *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_DisableClockSleep\n

  1822.   *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_DisableClockSleep\n

  1823.   *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1824.   *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1825.   *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_DisableClockSleep\n

  1826.   *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_DisableClockSleep\n

  1827.   *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_DisableClockSleep\n

  1828.   *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_DisableClockSleep\n

  1829.   *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_DisableClockSleep\n

  1830.   *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1831.   *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1832.   *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_DisableClockSleep\n

  1833.   *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_DisableClockSleep\n

  1834.   *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_DisableClockSleep\n

  1835.   *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_DisableClockSleep\n

  1836.   *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_DisableClockSleep

  1837.   * @param  Periphs This parameter can be a combination of the following values:

  1838.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  1839.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  1840.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  1841.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  1842.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  1843.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  1844.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  1845.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  1846.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  1847.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  1848.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

  1849.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  1850.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  1851.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  1852.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  1853.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  1854.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  1855.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  1856.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  1857.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  1858.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  1859.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  1860.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  1861.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  1862.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  1863.   *

  1864.   *         (*) value not defined in all devices.

  1865.   * @retval None

  1866. */

  1867. __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

  1868. {

  1869.   CLEAR_BIT(RCC->APB1LLPENR, Periphs);

  1870. }

  1871. 

  1872. /**

  1873.   * @brief  Enable APB1 peripherals clock.

  1874.   * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_EnableClock\n

  1875.   *         APB1HENR     SWPMIEN       LL_APB1_GRP2_EnableClock\n

  1876.   *         APB1HENR     OPAMPEN       LL_APB1_GRP2_EnableClock\n

  1877.   *         APB1HENR     MDIOSEN       LL_APB1_GRP2_EnableClock\n

  1878.   *         APB1HENR     FDCANEN       LL_APB1_GRP2_EnableClock

  1879.   * @param  Periphs This parameter can be a combination of the following values:

  1880.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  1881.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  1882.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  1883.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  1884.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  1885.   * @retval None

  1886. */

  1887. __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)

  1888. {

  1889.   __IO uint32_t tmpreg;

  1890.   SET_BIT(RCC->APB1HENR, Periphs);

  1891.   /* Delay after an RCC peripheral clock enabling */

  1892.   tmpreg = READ_BIT(RCC->APB1HENR, Periphs);

  1893.   (void)tmpreg;

  1894. }

  1895. 

  1896. /**

  1897.   * @brief  Check if APB1 peripheral clock is enabled or not

  1898.   * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_IsEnabledClock\n

  1899.   *         APB1HENR     SWPMIEN       LL_APB1_GRP2_IsEnabledClock\n

  1900.   *         APB1HENR     OPAMPEN       LL_APB1_GRP2_IsEnabledClock\n

  1901.   *         APB1HENR     MDIOSEN       LL_APB1_GRP2_IsEnabledClock\n

  1902.   *         APB1HENR     FDCANEN       LL_APB1_GRP2_IsEnabledClock

  1903.   * @param  Periphs This parameter can be a combination of the following values:

  1904.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  1905.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  1906.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  1907.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  1908.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  1909.   * @retval uint32_t

  1910. */

  1911. __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)

  1912. {

  1913.   return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);

  1914. }

  1915. 

  1916. /**

  1917.   * @brief  Disable APB1 peripherals clock.

  1918.   * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_DisableClock\n

  1919.   *         APB1HENR     SWPMIEN       LL_APB1_GRP2_DisableClock\n

  1920.   *         APB1HENR     OPAMPEN       LL_APB1_GRP2_DisableClock\n

  1921.   *         APB1HENR     MDIOSEN       LL_APB1_GRP2_DisableClock\n

  1922.   *         APB1HENR     FDCANEN       LL_APB1_GRP2_DisableClock

  1923.   * @param  Periphs This parameter can be a combination of the following values:

  1924.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  1925.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  1926.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  1927.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  1928.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  1929.   * @retval None

  1930. */

  1931. __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)

  1932. {

  1933.   CLEAR_BIT(RCC->APB1HENR, Periphs);

  1934. }

  1935. 

  1936. /**

  1937.   * @brief  Force APB1 peripherals reset.

  1938.   * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ForceReset\n

  1939.   *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ForceReset\n

  1940.   *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ForceReset\n

  1941.   *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ForceReset\n

  1942.   *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ForceReset

  1943.   * @param  Periphs This parameter can be a combination of the following values:

  1944.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  1945.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  1946.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  1947.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  1948.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  1949.   * @retval None

  1950. */

  1951. __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)

  1952. {

  1953.   SET_BIT(RCC->APB1HRSTR, Periphs);

  1954. }

  1955. 

  1956. /**

  1957.   * @brief  Release APB1 peripherals reset.

  1958.   * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ReleaseReset\n

  1959.   *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ReleaseReset\n

  1960.   *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ReleaseReset\n

  1961.   *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ReleaseReset\n

  1962.   *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ReleaseReset

  1963.   * @param  Periphs This parameter can be a combination of the following values:

  1964.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  1965.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  1966.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  1967.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  1968.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  1969.   * @retval None

  1970. */

  1971. __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)

  1972. {

  1973.   CLEAR_BIT(RCC->APB1HRSTR, Periphs);

  1974. }

  1975. 

  1976. /**

  1977.   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.

  1978.   * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_EnableClockSleep\n

  1979.   *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_EnableClockSleep\n

  1980.   *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_EnableClockSleep\n

  1981.   *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_EnableClockSleep\n

  1982.   *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_EnableClockSleep

  1983.   * @param  Periphs This parameter can be a combination of the following values:

  1984.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  1985.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  1986.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  1987.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  1988.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  1989.   * @retval None

  1990. */

  1991. __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)

  1992. {

  1993.   __IO uint32_t tmpreg;

  1994.   SET_BIT(RCC->APB1HLPENR, Periphs);

  1995.   /* Delay after an RCC peripheral clock enabling */

  1996.   tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);

  1997.   (void)tmpreg;

  1998. }

  1999. 

  2000. /**

  2001.   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.

  2002.   * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_DisableClockSleep\n

  2003.   *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_DisableClockSleep\n

  2004.   *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_DisableClockSleep\n

  2005.   *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_DisableClockSleep\n

  2006.   *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_DisableClockSleep

  2007.   * @param  Periphs This parameter can be a combination of the following values:

  2008.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  2009.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  2010.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  2011.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  2012.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  2013.   * @retval None

  2014. */

  2015. __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)

  2016. {

  2017.   CLEAR_BIT(RCC->APB1HLPENR, Periphs);

  2018. }

  2019. 

  2020. /**

  2021.   * @}

  2022.   */

  2023. 

  2024. /** @defgroup BUS_LL_EF_APB2 APB2

  2025.   * @{

  2026.   */

  2027. 

  2028. /**

  2029.   * @brief  Enable APB2 peripherals clock.

  2030.   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n

  2031.   *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n

  2032.   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n

  2033.   *         APB2ENR      USART6EN      LL_APB2_GRP1_EnableClock\n

  2034.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n

  2035.   *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n

  2036.   *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n

  2037.   *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n

  2038.   *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n

  2039.   *         APB2ENR      SPI5EN        LL_APB2_GRP1_EnableClock\n

  2040.   *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n

  2041.   *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n

  2042.   *         APB2ENR      SAI3EN        LL_APB2_GRP1_EnableClock\n

  2043.   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock\n

  2044.   *         APB2ENR      HRTIMEN       LL_APB2_GRP1_EnableClock

  2045.   * @param  Periphs This parameter can be a combination of the following values:

  2046.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  2047.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  2048.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  2049.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  2050.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  2051.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  2052.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  2053.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  2054.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  2055.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  2056.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  2057.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  2058.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  2059.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  2060.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  2061.   * @retval None

  2062. */

  2063. __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)

  2064. {

  2065.   __IO uint32_t tmpreg;

  2066.   SET_BIT(RCC->APB2ENR, Periphs);

  2067.   /* Delay after an RCC peripheral clock enabling */

  2068.   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);

  2069.   (void)tmpreg;

  2070. }

  2071. 

  2072. /**

  2073.   * @brief  Check if APB2 peripheral clock is enabled or not

  2074.   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n

  2075.   *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n

  2076.   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n

  2077.   *         APB2ENR      USART6EN      LL_APB2_GRP1_IsEnabledClock\n

  2078.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n

  2079.   *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n

  2080.   *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n

  2081.   *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n

  2082.   *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n

  2083.   *         APB2ENR      SPI5EN        LL_APB2_GRP1_IsEnabledClock\n

  2084.   *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n

  2085.   *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n

  2086.   *         APB2ENR      SAI3EN        LL_APB2_GRP1_IsEnabledClock\n

  2087.   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n

  2088.   *         APB2ENR      HRTIMEN       LL_APB2_GRP1_IsEnabledClock

  2089.   * @param  Periphs This parameter can be a combination of the following values:

  2090.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  2091.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  2092.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  2093.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  2094.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  2095.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  2096.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  2097.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  2098.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  2099.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  2100.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  2101.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  2102.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  2103.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  2104.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  2105.   * @retval uint32_t

  2106. */

  2107. __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

  2108. {

  2109.   return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);

  2110. }

  2111. 

  2112. /**

  2113.   * @brief  Disable APB2 peripherals clock.

  2114.   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n

  2115.   *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n

  2116.   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n

  2117.   *         APB2ENR      USART6EN      LL_APB2_GRP1_DisableClock\n

  2118.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n

  2119.   *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n

  2120.   *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n

  2121.   *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n

  2122.   *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n

  2123.   *         APB2ENR      SPI5EN        LL_APB2_GRP1_DisableClock\n

  2124.   *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n

  2125.   *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n

  2126.   *         APB2ENR      SAI3EN        LL_APB2_GRP1_DisableClock\n

  2127.   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock\n

  2128.   *         APB2ENR      HRTIMEN       LL_APB2_GRP1_DisableClock

  2129.   * @param  Periphs This parameter can be a combination of the following values:

  2130.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  2131.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  2132.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  2133.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  2134.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  2135.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  2136.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  2137.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  2138.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  2139.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  2140.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  2141.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  2142.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  2143.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  2144.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  2145.   * @retval None

  2146. */

  2147. __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)

  2148. {

  2149.   CLEAR_BIT(RCC->APB2ENR, Periphs);

  2150. }

  2151. 

  2152. /**

  2153.   * @brief  Force APB2 peripherals reset.

  2154.   * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n

  2155.   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n

  2156.   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n

  2157.   *         APB2RSTR     USART6RST     LL_APB2_GRP1_ForceReset\n

  2158.   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n

  2159.   *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ForceReset\n

  2160.   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n

  2161.   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n

  2162.   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n

  2163.   *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ForceReset\n

  2164.   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n

  2165.   *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n

  2166.   *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ForceReset\n

  2167.   *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset\n

  2168.   *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ForceReset

  2169.   * @param  Periphs This parameter can be a combination of the following values:

  2170.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  2171.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  2172.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  2173.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  2174.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  2175.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  2176.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  2177.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  2178.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  2179.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  2180.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  2181.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  2182.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  2183.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  2184.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  2185.   * @retval None

  2186. */

  2187. __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)

  2188. {

  2189.   SET_BIT(RCC->APB2RSTR, Periphs);

  2190. }

  2191. 

  2192. /**

  2193.   * @brief  Release APB2 peripherals reset.

  2194.   * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n

  2195.   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n

  2196.   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n

  2197.   *         APB2RSTR     USART6RST     LL_APB2_GRP1_ReleaseReset\n

  2198.   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n

  2199.   *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ReleaseReset\n

  2200.   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n

  2201.   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n

  2202.   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n

  2203.   *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ReleaseReset\n

  2204.   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n

  2205.   *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n

  2206.   *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ReleaseReset\n

  2207.   *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset\n

  2208.   *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ReleaseReset

  2209.   * @param  Periphs This parameter can be a combination of the following values:

  2210.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  2211.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  2212.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  2213.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  2214.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  2215.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  2216.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  2217.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  2218.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  2219.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  2220.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  2221.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  2222.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  2223.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  2224.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  2225.   * @retval None

  2226. */

  2227. __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)

  2228. {

  2229.   CLEAR_BIT(RCC->APB2RSTR, Periphs);

  2230. }

  2231. 

  2232. /**

  2233.   * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.

  2234.   * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_EnableClockSleep\n

  2235.   *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_EnableClockSleep\n

  2236.   *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_EnableClockSleep\n

  2237.   *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_EnableClockSleep\n

  2238.   *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_EnableClockSleep\n

  2239.   *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_EnableClockSleep\n

  2240.   *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_EnableClockSleep\n

  2241.   *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_EnableClockSleep\n

  2242.   *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_EnableClockSleep\n

  2243.   *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_EnableClockSleep\n

  2244.   *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_EnableClockSleep\n

  2245.   *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_EnableClockSleep\n

  2246.   *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_EnableClockSleep\n

  2247.   *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_EnableClockSleep\n

  2248.   *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_EnableClockSleep

  2249.   * @param  Periphs This parameter can be a combination of the following values:

  2250.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  2251.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  2252.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  2253.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  2254.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  2255.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  2256.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  2257.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  2258.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  2259.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  2260.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  2261.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  2262.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  2263.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  2264.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  2265.   * @retval None

  2266. */

  2267. __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

  2268. {

  2269.   __IO uint32_t tmpreg;

  2270.   SET_BIT(RCC->APB2LPENR, Periphs);

  2271.   /* Delay after an RCC peripheral clock enabling */

  2272.   tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);

  2273.   (void)tmpreg;

  2274. }

  2275. 

  2276. /**

  2277.   * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.

  2278.   * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_DisableClockSleep\n

  2279.   *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_DisableClockSleep\n

  2280.   *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_DisableClockSleep\n

  2281.   *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_DisableClockSleep\n

  2282.   *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_DisableClockSleep\n

  2283.   *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_DisableClockSleep\n

  2284.   *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_DisableClockSleep\n

  2285.   *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_DisableClockSleep\n

  2286.   *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_DisableClockSleep\n

  2287.   *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_DisableClockSleep\n

  2288.   *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_DisableClockSleep\n

  2289.   *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_DisableClockSleep\n

  2290.   *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_DisableClockSleep\n

  2291.   *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_DisableClockSleep\n

  2292.   *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_DisableClockSleep

  2293.   * @param  Periphs This parameter can be a combination of the following values:

  2294.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  2295.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  2296.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  2297.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  2298.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  2299.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  2300.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  2301.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  2302.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  2303.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  2304.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  2305.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  2306.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  2307.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  2308.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  2309.   * @retval None

  2310. */

  2311. __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

  2312. {

  2313.   CLEAR_BIT(RCC->APB2LPENR, Periphs);

  2314. }

  2315. 

  2316. /**

  2317.   * @}

  2318.   */

  2319. 

  2320. /** @defgroup BUS_LL_EF_APB4 APB4

  2321.   * @{

  2322.   */

  2323. 

  2324. /**

  2325.   * @brief  Enable APB4 peripherals clock.

  2326.   * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_EnableClock\n

  2327.   *         APB4ENR      LPUART1EN     LL_APB4_GRP1_EnableClock\n

  2328.   *         APB4ENR      SPI6EN        LL_APB4_GRP1_EnableClock\n

  2329.   *         APB4ENR      I2C4EN        LL_APB4_GRP1_EnableClock\n

  2330.   *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_EnableClock\n

  2331.   *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_EnableClock\n

  2332.   *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_EnableClock\n

  2333.   *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_EnableClock\n

  2334.   *         APB4ENR      COMP12EN      LL_APB4_GRP1_EnableClock\n

  2335.   *         APB4ENR      VREFEN        LL_APB4_GRP1_EnableClock\n

  2336.   *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_EnableClock\n

  2337.   *         APB4ENR      SAI4EN        LL_APB4_GRP1_EnableClock

  2338.   * @param  Periphs This parameter can be a combination of the following values:

  2339.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  2340.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  2341.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  2342.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  2343.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  2344.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  2345.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  2346.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  2347.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  2348.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  2349.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  2350.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  2351.   * @retval None

  2352. */

  2353. __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)

  2354. {

  2355.   __IO uint32_t tmpreg;

  2356.   SET_BIT(RCC->APB4ENR, Periphs);

  2357.   /* Delay after an RCC peripheral clock enabling */

  2358.   tmpreg = READ_BIT(RCC->APB4ENR, Periphs);

  2359.   (void)tmpreg;

  2360. }

  2361. 

  2362. /**

  2363.   * @brief  Check if APB4 peripheral clock is enabled or not

  2364.   * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_IsEnabledClock\n

  2365.   *         APB4ENR      LPUART1EN     LL_APB4_GRP1_IsEnabledClock\n

  2366.   *         APB4ENR      SPI6EN        LL_APB4_GRP1_IsEnabledClock\n

  2367.   *         APB4ENR      I2C4EN        LL_APB4_GRP1_IsEnabledClock\n

  2368.   *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_IsEnabledClock\n

  2369.   *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_IsEnabledClock\n

  2370.   *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_IsEnabledClock\n

  2371.   *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_IsEnabledClock\n

  2372.   *         APB4ENR      COMP12EN      LL_APB4_GRP1_IsEnabledClock\n

  2373.   *         APB4ENR      VREFEN        LL_APB4_GRP1_IsEnabledClock\n

  2374.   *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_IsEnabledClock\n

  2375.   *         APB4ENR      SAI4EN        LL_APB4_GRP1_IsEnabledClock

  2376.   * @param  Periphs This parameter can be a combination of the following values:

  2377.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  2378.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  2379.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  2380.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  2381.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  2382.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  2383.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  2384.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  2385.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  2386.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  2387.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  2388.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  2389.   * @retval uint32_t

  2390. */

  2391. __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)

  2392. {

  2393.   return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);

  2394. }

  2395. 

  2396. /**

  2397.   * @brief  Disable APB4 peripherals clock.

  2398.   * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_DisableClock\n

  2399.   *         APB4ENR      LPUART1EN     LL_APB4_GRP1_DisableClock\n

  2400.   *         APB4ENR      SPI6EN        LL_APB4_GRP1_DisableClock\n

  2401.   *         APB4ENR      I2C4EN        LL_APB4_GRP1_DisableClock\n

  2402.   *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_DisableClock\n

  2403.   *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_DisableClock\n

  2404.   *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_DisableClock\n

  2405.   *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_DisableClock\n

  2406.   *         APB4ENR      COMP12EN      LL_APB4_GRP1_DisableClock\n

  2407.   *         APB4ENR      VREFEN        LL_APB4_GRP1_DisableClock\n

  2408.   *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_DisableClock\n

  2409.   *         APB4ENR      SAI4EN        LL_APB4_GRP1_DisableClock

  2410.   * @param  Periphs This parameter can be a combination of the following values:

  2411.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  2412.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  2413.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  2414.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  2415.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  2416.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  2417.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  2418.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  2419.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  2420.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  2421.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  2422.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  2423.   * @retval None

  2424. */

  2425. __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)

  2426. {

  2427.   CLEAR_BIT(RCC->APB4ENR, Periphs);

  2428. }

  2429. 

  2430. /**

  2431.   * @brief  Force APB4 peripherals reset.

  2432.   * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ForceReset\n

  2433.   *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ForceReset\n

  2434.   *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ForceReset\n

  2435.   *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ForceReset\n

  2436.   *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ForceReset\n

  2437.   *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ForceReset\n

  2438.   *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ForceReset\n

  2439.   *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ForceReset\n

  2440.   *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ForceReset\n

  2441.   *         APB4RSTR     VREFRST       LL_APB4_GRP1_ForceReset\n

  2442.   *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ForceReset

  2443.   * @param  Periphs This parameter can be a combination of the following values:

  2444.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  2445.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  2446.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  2447.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  2448.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  2449.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  2450.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  2451.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  2452.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  2453.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  2454.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  2455.   * @retval None

  2456. */

  2457. __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)

  2458. {

  2459.   SET_BIT(RCC->APB4RSTR, Periphs);

  2460. }

  2461. 

  2462. /**

  2463.   * @brief  Release APB4 peripherals reset.

  2464.   * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ReleaseReset\n

  2465.   *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ReleaseReset\n

  2466.   *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ReleaseReset\n

  2467.   *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ReleaseReset\n

  2468.   *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ReleaseReset\n

  2469.   *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ReleaseReset\n

  2470.   *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ReleaseReset\n

  2471.   *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ReleaseReset\n

  2472.   *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ReleaseReset\n

  2473.   *         APB4RSTR     VREFRST       LL_APB4_GRP1_ReleaseReset\n

  2474.   *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ReleaseReset

  2475.   * @param  Periphs This parameter can be a combination of the following values:

  2476.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  2477.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  2478.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  2479.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  2480.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  2481.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  2482.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  2483.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  2484.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  2485.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  2486.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  2487.   * @retval None

  2488. */

  2489. __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)

  2490. {

  2491.   CLEAR_BIT(RCC->APB4RSTR, Periphs);

  2492. }

  2493. 

  2494. /**

  2495.   * @brief  Enable APB4 peripherals clock during Low Power (Sleep) mode.

  2496.   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_EnableClockSleep\n

  2497.   *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_EnableClockSleep\n

  2498.   *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_EnableClockSleep\n

  2499.   *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_EnableClockSleep\n

  2500.   *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_EnableClockSleep\n

  2501.   *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_EnableClockSleep\n

  2502.   *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_EnableClockSleep\n

  2503.   *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_EnableClockSleep\n

  2504.   *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_EnableClockSleep\n

  2505.   *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_EnableClockSleep\n

  2506.   *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_EnableClockSleep\n

  2507.   *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_EnableClockSleep

  2508.   * @param  Periphs This parameter can be a combination of the following values:

  2509.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  2510.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  2511.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  2512.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  2513.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  2514.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  2515.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  2516.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  2517.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  2518.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  2519.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  2520.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  2521.   * @retval None

  2522. */

  2523. __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)

  2524. {

  2525.   __IO uint32_t tmpreg;

  2526.   SET_BIT(RCC->APB4LPENR, Periphs);

  2527.   /* Delay after an RCC peripheral clock enabling */

  2528.   tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);

  2529.   (void)tmpreg;

  2530. }

  2531. 

  2532. /**

  2533.   * @brief  Disable APB4 peripherals clock during Low Power (Sleep) mode.

  2534.   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_DisableClockSleep\n

  2535.   *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_DisableClockSleep\n

  2536.   *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_DisableClockSleep\n

  2537.   *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_DisableClockSleep\n

  2538.   *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_DisableClockSleep\n

  2539.   *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_DisableClockSleep\n

  2540.   *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_DisableClockSleep\n

  2541.   *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_DisableClockSleep\n

  2542.   *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_DisableClockSleep\n

  2543.   *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_DisableClockSleep\n

  2544.   *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_DisableClockSleep\n

  2545.   *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_DisableClockSleep

  2546.   * @param  Periphs This parameter can be a combination of the following values:

  2547.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  2548.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  2549.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  2550.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  2551.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  2552.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  2553.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  2554.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  2555.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  2556.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  2557.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  2558.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  2559.   * @retval None

  2560. */

  2561. __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)

  2562. {

  2563.   CLEAR_BIT(RCC->APB4LPENR, Periphs);

  2564. }

  2565. 

  2566. /**

  2567.   * @}

  2568.   */

  2569. 

  2570. /** @defgroup BUS_LL_EF_CLKAM BUS_LL_EF_CLKAM

  2571.   * @{

  2572.   */

  2573. 

  2574. /**

  2575.   * @brief  Enable peripherals clock for CLKAM Mode.

  2576.   * @rmtoll D3AMR        BDMA          LL_CLKAM_Enable\n

  2577.   *         D3AMR        LPUART1       LL_CLKAM_Enable\n

  2578.   *         D3AMR        SPI6          LL_CLKAM_Enable\n

  2579.   *         D3AMR        I2C4          LL_CLKAM_Enable\n

  2580.   *         D3AMR        LPTIM2        LL_CLKAM_Enable\n

  2581.   *         D3AMR        LPTIM3        LL_CLKAM_Enable\n

  2582.   *         D3AMR        LPTIM4        LL_CLKAM_Enable\n

  2583.   *         D3AMR        LPTIM5        LL_CLKAM_Enable\n

  2584.   *         D3AMR        COMP12        LL_CLKAM_Enable\n

  2585.   *         D3AMR        VREF          LL_CLKAM_Enable\n

  2586.   *         D3AMR        RTC           LL_CLKAM_Enable\n

  2587.   *         D3AMR        CRC           LL_CLKAM_Enable\n

  2588.   *         D3AMR        SAI4          LL_CLKAM_Enable\n

  2589.   *         D3AMR        ADC3          LL_CLKAM_Enable\n

  2590.   *         D3AMR        BKPRAM        LL_CLKAM_Enable\n

  2591.   *         D3AMR        SRAM4         LL_CLKAM_Enable

  2592.   * @param  Periphs This parameter can be a combination of the following values:

  2593.   *         @arg @ref LL_CLKAM_PERIPH_BDMA

  2594.   *         @arg @ref LL_CLKAM_PERIPH_LPUART1

  2595.   *         @arg @ref LL_CLKAM_PERIPH_SPI6

  2596.   *         @arg @ref LL_CLKAM_PERIPH_I2C4

  2597.   *         @arg @ref LL_CLKAM_PERIPH_LPTIM2

  2598.   *         @arg @ref LL_CLKAM_PERIPH_LPTIM3

  2599.   *         @arg @ref LL_CLKAM_PERIPH_LPTIM4

  2600.   *         @arg @ref LL_CLKAM_PERIPH_LPTIM5

  2601.   *         @arg @ref LL_CLKAM_PERIPH_COMP12

  2602.   *         @arg @ref LL_CLKAM_PERIPH_VREF

  2603.   *         @arg @ref LL_CLKAM_PERIPH_RTC

  2604.   *         @arg @ref LL_CLKAM_PERIPH_CRC

  2605.   *         @arg @ref LL_CLKAM_PERIPH_SAI4

  2606.   *         @arg @ref LL_CLKAM_PERIPH_ADC3

  2607.   *         @arg @ref LL_CLKAM_PERIPH_BKPRAM

  2608.   *         @arg @ref LL_CLKAM_PERIPH_SRAM4

  2609.   * @retval None

  2610. */

  2611. __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)

  2612. {

  2613.   __IO uint32_t tmpreg;

  2614.   SET_BIT(RCC->D3AMR, Periphs);

  2615.   /* Delay after an RCC peripheral clock enabling */

  2616.   tmpreg = READ_BIT(RCC->D3AMR, Periphs);

  2617.   (void)tmpreg;

  2618. }

  2619. 

  2620. /**

  2621.   * @brief  Disable peripherals clock for CLKAM Mode.

  2622.   * @rmtoll D3AMR        BDMA          LL_CLKAM_Disable\n

  2623.   *         D3AMR        LPUART1       LL_CLKAM_Disable\n

  2624.   *         D3AMR        SPI6          LL_CLKAM_Disable\n

  2625.   *         D3AMR        I2C4          LL_CLKAM_Disable\n

  2626.   *         D3AMR        LPTIM2        LL_CLKAM_Disable\n

  2627.   *         D3AMR        LPTIM3        LL_CLKAM_Disable\n

  2628.   *         D3AMR        LPTIM4        LL_CLKAM_Disable\n

  2629.   *         D3AMR        LPTIM5        LL_CLKAM_Disable\n

  2630.   *         D3AMR        COMP12        LL_CLKAM_Disable\n

  2631.   *         D3AMR        VREF          LL_CLKAM_Disable\n

  2632.   *         D3AMR        RTC           LL_CLKAM_Disable\n

  2633.   *         D3AMR        CRC           LL_CLKAM_Disable\n

  2634.   *         D3AMR        SAI4          LL_CLKAM_Disable\n

  2635.   *         D3AMR        ADC3          LL_CLKAM_Disable\n

  2636.   *         D3AMR        BKPRAM        LL_CLKAM_Disable\n

  2637.   *         D3AMR        SRAM4         LL_CLKAM_Disable

  2638.   * @param  Periphs This parameter can be a combination of the following values:

  2639.   *         @arg @ref LL_CLKAM_PERIPH_BDMA

  2640.   *         @arg @ref LL_CLKAM_PERIPH_LPUART1

  2641.   *         @arg @ref LL_CLKAM_PERIPH_SPI6

  2642.   *         @arg @ref LL_CLKAM_PERIPH_I2C4

  2643.   *         @arg @ref LL_CLKAM_PERIPH_LPTIM2

  2644.   *         @arg @ref LL_CLKAM_PERIPH_LPTIM3

  2645.   *         @arg @ref LL_CLKAM_PERIPH_LPTIM4

  2646.   *         @arg @ref LL_CLKAM_PERIPH_LPTIM5

  2647.   *         @arg @ref LL_CLKAM_PERIPH_COMP12

  2648.   *         @arg @ref LL_CLKAM_PERIPH_VREF

  2649.   *         @arg @ref LL_CLKAM_PERIPH_RTC

  2650.   *         @arg @ref LL_CLKAM_PERIPH_CRC

  2651.   *         @arg @ref LL_CLKAM_PERIPH_SAI4

  2652.   *         @arg @ref LL_CLKAM_PERIPH_ADC3

  2653.   *         @arg @ref LL_CLKAM_PERIPH_BKPRAM

  2654.   *         @arg @ref LL_CLKAM_PERIPH_SRAM4

  2655.   * @retval None

  2656. */

  2657. __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)

  2658. {

  2659.   CLEAR_BIT(RCC->D3AMR, Periphs);

  2660. }

  2661. 

  2662. /**

  2663.   * @}

  2664.   */

  2665. 

  2666. #if defined(DUAL_CORE)

  2667. /** @defgroup BUS_LL_EF_AHB3 AHB3

  2668.   * @{

  2669.   */

  2670. 

  2671. /**

  2672.   * @brief  Enable C1 AHB3 peripherals clock.

  2673.   * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_EnableClock\n

  2674.   *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_EnableClock\n

  2675.   *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_EnableClock\n

  2676.   *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_EnableClock\n

  2677.   *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_EnableClock\n

  2678.   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_EnableClock

  2679.   * @param  Periphs This parameter can be a combination of the following values:

  2680.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  2681.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  2682.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  2683.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  2684.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  2685.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  2686.   * @retval None

  2687. */

  2688. __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)

  2689. {

  2690.   __IO uint32_t tmpreg;

  2691.   SET_BIT(RCC_C1->AHB3ENR, Periphs);

  2692.   /* Delay after an RCC peripheral clock enabling */

  2693.   tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);

  2694.   (void)tmpreg;

  2695. }

  2696. 

  2697. /**

  2698.   * @brief  Check if C1 AHB3 peripheral clock is enabled or not

  2699.   * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_IsEnabledClock\n

  2700.   *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_IsEnabledClock\n

  2701.   *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_IsEnabledClock\n

  2702.   *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_IsEnabledClock\n

  2703.   *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_IsEnabledClock\n

  2704.   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_IsEnabledClock

  2705.   * @param  Periphs This parameter can be a combination of the following values:

  2706.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  2707.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  2708.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  2709.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  2710.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  2711.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  2712.   * @retval uint32_t

  2713. */

  2714. __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)

  2715. {

  2716.   return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);

  2717. }

  2718. 

  2719. /**

  2720.   * @brief  Disable C1 AHB3 peripherals clock.

  2721.   * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_DisableClock\n

  2722.   *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_DisableClock\n

  2723.   *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_DisableClock\n

  2724.   *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_DisableClock\n

  2725.   *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_DisableClock\n

  2726.   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_DisableClock

  2727.   * @param  Periphs This parameter can be a combination of the following values:

  2728.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  2729.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  2730.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  2731.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  2732.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  2733.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  2734.   * @retval None

  2735. */

  2736. __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)

  2737. {

  2738.   CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);

  2739. }

  2740. 

  2741. /**

  2742.   * @brief  Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.

  2743.   * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n

  2744.   *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n

  2745.   *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n

  2746.   *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_EnableClockSleep\n

  2747.   *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n

  2748.   *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n

  2749.   *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n

  2750.   *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n

  2751.   *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n

  2752.   *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n

  2753.   *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_EnableClockSleep

  2754.   * @param  Periphs This parameter can be a combination of the following values:

  2755.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  2756.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  2757.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  2758.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  2759.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  2760.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  2761.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  2762.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  2763.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  2764.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  2765.   * @retval None

  2766. */

  2767. __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)

  2768. {

  2769.   __IO uint32_t tmpreg;

  2770.   SET_BIT(RCC_C1->AHB3LPENR, Periphs);

  2771.   /* Delay after an RCC peripheral clock enabling */

  2772.   tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);

  2773.   (void)tmpreg;

  2774. }

  2775. 

  2776. /**

  2777.   * @brief  Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.

  2778.   * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n

  2779.   *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n

  2780.   *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n

  2781.   *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_DisableClockSleep\n

  2782.   *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n

  2783.   *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n

  2784.   *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n

  2785.   *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n

  2786.   *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n

  2787.   *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n

  2788.   *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_DisableClockSleep

  2789.   * @param  Periphs This parameter can be a combination of the following values:

  2790.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  2791.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  2792.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  2793.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  2794.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  2795.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  2796.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  2797.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  2798.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  2799.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  2800.   * @retval None

  2801. */

  2802. __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)

  2803. {

  2804.   CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);

  2805. }

  2806. 

  2807. /**

  2808.   * @}

  2809.   */

  2810. 

  2811. /** @defgroup BUS_LL_EF_AHB1 AHB1

  2812.   * @{

  2813.   */

  2814. 

  2815. /**

  2816.   * @brief  Enable C1 AHB1 peripherals clock.

  2817.   * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_EnableClock\n

  2818.   *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_EnableClock\n

  2819.   *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_EnableClock\n

  2820.   *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_EnableClock\n

  2821.   *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_EnableClock\n

  2822.   *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_EnableClock\n

  2823.   *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_EnableClock\n

  2824.   *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n

  2825.   *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock\n

  2826.   *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n

  2827.   *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock

  2828.   * @param  Periphs This parameter can be a combination of the following values:

  2829.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  2830.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  2831.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  2832.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  2833.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  2834.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  2835.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  2836.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  2837.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  2838.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  2839.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  2840.   * @retval None

  2841. */

  2842. __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)

  2843. {

  2844.   __IO uint32_t tmpreg;

  2845.   SET_BIT(RCC_C1->AHB1ENR, Periphs);

  2846.   /* Delay after an RCC peripheral clock enabling */

  2847.   tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);

  2848.   (void)tmpreg;

  2849. }

  2850. 

  2851. /**

  2852.   * @brief  Check if C1 AHB1 peripheral clock is enabled or not

  2853.   * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_IsEnabledClock\n

  2854.   *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_IsEnabledClock\n

  2855.   *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_IsEnabledClock\n

  2856.   *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_IsEnabledClock\n

  2857.   *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_IsEnabledClock\n

  2858.   *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n

  2859.   *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n

  2860.   *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n

  2861.   *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock\n

  2862.   *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n

  2863.   *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock

  2864.   * @param  Periphs This parameter can be a combination of the following values:

  2865.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  2866.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  2867.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  2868.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  2869.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  2870.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  2871.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  2872.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  2873.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  2874.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  2875.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  2876.   * @retval uint32_t

  2877. */

  2878. __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

  2879. {

  2880.   return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);

  2881. }

  2882. 

  2883. /**

  2884.   * @brief  Disable C1 AHB1 peripherals clock.

  2885.   * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_DisableClock\n

  2886.   *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_DisableClock\n

  2887.   *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_DisableClock\n

  2888.   *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_DisableClock\n

  2889.   *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_DisableClock\n

  2890.   *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_DisableClock\n

  2891.   *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_DisableClock\n

  2892.   *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n

  2893.   *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock\n

  2894.   *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n

  2895.   *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock

  2896.   * @param  Periphs This parameter can be a combination of the following values:

  2897.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  2898.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  2899.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  2900.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  2901.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  2902.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  2903.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  2904.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  2905.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  2906.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  2907.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  2908.   * @retval None

  2909. */

  2910. __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)

  2911. {

  2912.   CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);

  2913. }

  2914. 

  2915. /**

  2916.   * @brief  Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.

  2917.   * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n

  2918.   *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n

  2919.   *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_EnableClockSleep\n

  2920.   *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n

  2921.   *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_EnableClockSleep\n

  2922.   *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n

  2923.   *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n

  2924.   *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n

  2925.   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n

  2926.   *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n

  2927.   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep

  2928.   * @param  Periphs This parameter can be a combination of the following values:

  2929.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  2930.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  2931.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  2932.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  2933.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  2934.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  2935.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  2936.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  2937.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  2938.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  2939.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  2940.   * @retval None

  2941. */

  2942. __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

  2943. {

  2944.   __IO uint32_t tmpreg;

  2945.   SET_BIT(RCC_C1->AHB1LPENR, Periphs);

  2946.   /* Delay after an RCC peripheral clock enabling */

  2947.   tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);

  2948.   (void)tmpreg;

  2949. }

  2950. 

  2951. /**

  2952.   * @brief  Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.

  2953.   * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n

  2954.   *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n

  2955.   *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_DisableClockSleep\n

  2956.   *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n

  2957.   *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_DisableClockSleep\n

  2958.   *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n

  2959.   *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n

  2960.   *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n

  2961.   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n

  2962.   *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n

  2963.   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep

  2964.   * @param  Periphs This parameter can be a combination of the following values:

  2965.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  2966.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  2967.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  2968.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  2969.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  2970.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  2971.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  2972.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  2973.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  2974.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  2975.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  2976.   * @retval None

  2977. */

  2978. __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

  2979. {

  2980.   CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);

  2981. }

  2982. 

  2983. /**

  2984.   * @}

  2985.   */

  2986. 

  2987. /** @defgroup BUS_LL_EF_AHB2 AHB2

  2988.   * @{

  2989.   */

  2990. 

  2991. /**

  2992.   * @brief  Enable C1 AHB2 peripherals clock.

  2993.   * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_EnableClock\n

  2994.   *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_EnableClock\n

  2995.   *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_EnableClock\n

  2996.   *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_EnableClock\n

  2997.   *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_EnableClock\n

  2998.   *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_EnableClock\n

  2999.   *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_EnableClock\n

  3000.   *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_EnableClock

  3001.   * @param  Periphs This parameter can be a combination of the following values:

  3002.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  3003.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  3004.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  3005.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  3006.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  3007.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  3008.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  3009.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  3010.   *

  3011.   *         (*) value not defined in all devices.

  3012.   * @retval None

  3013. */

  3014. __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)

  3015. {

  3016.   __IO uint32_t tmpreg;

  3017.   SET_BIT(RCC_C1->AHB2ENR, Periphs);

  3018.   /* Delay after an RCC peripheral clock enabling */

  3019.   tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);

  3020.   (void)tmpreg;

  3021. }

  3022. 

  3023. /**

  3024.   * @brief  Check if C1 AHB2 peripheral clock is enabled or not

  3025.   * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_IsEnabledClock\n

  3026.   *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_IsEnabledClock\n

  3027.   *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_IsEnabledClock\n

  3028.   *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_IsEnabledClock\n

  3029.   *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_IsEnabledClock\n

  3030.   *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_IsEnabledClock\n

  3031.   *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_IsEnabledClock\n

  3032.   *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_IsEnabledClock

  3033.   * @param  Periphs This parameter can be a combination of the following values:

  3034.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  3035.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  3036.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  3037.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  3038.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  3039.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  3040.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  3041.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  3042.   *

  3043.   *         (*) value not defined in all devices.

  3044.   * @retval uint32_t

  3045. */

  3046. __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)

  3047. {

  3048.   return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);

  3049. }

  3050. 

  3051. /**

  3052.   * @brief  Disable C1 AHB2 peripherals clock.

  3053.   * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_DisableClock\n

  3054.   *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_DisableClock\n

  3055.   *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_DisableClock\n

  3056.   *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_DisableClock\n

  3057.   *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_DisableClock\n

  3058.   *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_DisableClock\n

  3059.   *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_DisableClock\n

  3060.   *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_DisableClock

  3061.   * @param  Periphs This parameter can be a combination of the following values:

  3062.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  3063.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  3064.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  3065.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  3066.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  3067.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  3068.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  3069.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  3070.   *

  3071.   *         (*) value not defined in all devices.

  3072.   * @retval None

  3073. */

  3074. __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)

  3075. {

  3076.   CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);

  3077. }

  3078. 

  3079. /**

  3080.   * @brief  Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.

  3081.   * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n

  3082.   *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n

  3083.   *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n

  3084.   *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_EnableClockSleep\n

  3085.   *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n

  3086.   *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n

  3087.   *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n

  3088.   *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_EnableClockSleep

  3089.   * @param  Periphs This parameter can be a combination of the following values:

  3090.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  3091.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  3092.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  3093.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  3094.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  3095.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  3096.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  3097.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  3098.   *

  3099.   *         (*) value not defined in all devices.

  3100.   * @retval None

  3101. */

  3102. __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)

  3103. {

  3104.   __IO uint32_t tmpreg;

  3105.   SET_BIT(RCC_C1->AHB2LPENR, Periphs);

  3106.   /* Delay after an RCC peripheral clock enabling */

  3107.   tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);

  3108.   (void)tmpreg;

  3109. }

  3110. 

  3111. /**

  3112.   * @brief  Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.

  3113.   * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n

  3114.   *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n

  3115.   *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n

  3116.   *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_DisableClockSleep\n

  3117.   *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_DisableClockSleep\n

  3118.   *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n

  3119.   *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n

  3120.   *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_DisableClockSleep

  3121.   * @param  Periphs This parameter can be a combination of the following values:

  3122.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  3123.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  3124.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  3125.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  3126.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  3127.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  3128.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  3129.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  3130.   *

  3131.   *         (*) value not defined in all devices.

  3132.   * @retval None

  3133. */

  3134. __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)

  3135. {

  3136.   CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);

  3137. }

  3138. 

  3139. /**

  3140.   * @}

  3141.   */

  3142. 

  3143. /** @defgroup BUS_LL_EF_AHB4 AHB4

  3144.   * @{

  3145.   */

  3146. 

  3147. /**

  3148.   * @brief  Enable C1 AHB4 peripherals clock.

  3149.   * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_EnableClock\n

  3150.   *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_EnableClock\n

  3151.   *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_EnableClock\n

  3152.   *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_EnableClock\n

  3153.   *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_EnableClock\n

  3154.   *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_EnableClock\n

  3155.   *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_EnableClock\n

  3156.   *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_EnableClock\n

  3157.   *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_EnableClock\n

  3158.   *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_EnableClock\n

  3159.   *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_EnableClock\n

  3160.   *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_EnableClock\n

  3161.   *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_EnableClock\n

  3162.   *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_EnableClock\n

  3163.   *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_EnableClock\n

  3164.   *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_EnableClock\n

  3165.   *         AHB4ENR      D3SRAM1EN     LL_C1_AHB4_GRP1_EnableClock

  3166.   * @param  Periphs This parameter can be a combination of the following values:

  3167.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  3168.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  3169.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  3170.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  3171.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  3172.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  3173.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  3174.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  3175.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  3176.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  3177.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  3178.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  3179.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  3180.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  3181.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  3182.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  3183.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  3184.   *

  3185.   *         (*) value not defined in all devices.

  3186.   * @retval None

  3187. */

  3188. __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)

  3189. {

  3190.   __IO uint32_t tmpreg;

  3191.   SET_BIT(RCC_C1->AHB4ENR, Periphs);

  3192.   /* Delay after an RCC peripheral clock enabling */

  3193.   tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);

  3194.   (void)tmpreg;

  3195. }

  3196. 

  3197. /**

  3198.   * @brief  Check if C1 AHB4 peripheral clock is enabled or not

  3199.   * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3200.   *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3201.   *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3202.   *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3203.   *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3204.   *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3205.   *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3206.   *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3207.   *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3208.   *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3209.   *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

  3210.   *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_IsEnabledClock\n

  3211.   *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_IsEnabledClock\n

  3212.   *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_IsEnabledClock\n

  3213.   *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_IsEnabledClock\n

  3214.   *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_IsEnabledClock\n

  3215.   *         AHB4ENR      D3SRAM1EN     LL_C1_AHB4_GRP1_IsEnabledClock

  3216.   * @param  Periphs This parameter can be a combination of the following values:

  3217.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  3218.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  3219.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  3220.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  3221.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  3222.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  3223.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  3224.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  3225.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  3226.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  3227.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  3228.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  3229.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  3230.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  3231.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  3232.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  3233.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  3234.   *

  3235.   *         (*) value not defined in all devices.

  3236.   * @retval uint32_t

  3237. */

  3238. __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)

  3239. {

  3240.   return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);

  3241. }

  3242. 

  3243. /**

  3244.   * @brief  Disable C1 AHB4 peripherals clock.

  3245.   * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_DisableClock\n

  3246.   *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_DisableClock\n

  3247.   *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_DisableClock\n

  3248.   *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_DisableClock\n

  3249.   *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_DisableClock\n

  3250.   *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_DisableClock\n

  3251.   *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_DisableClock\n

  3252.   *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_DisableClock\n

  3253.   *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_DisableClock\n

  3254.   *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_DisableClock\n

  3255.   *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_DisableClock\n

  3256.   *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_DisableClock\n

  3257.   *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_DisableClock\n

  3258.   *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_DisableClock\n

  3259.   *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_DisableClock\n

  3260.   *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_DisableClock\n

  3261.   *         AHB4ENR      D3SRAM1EN     LL_C1_AHB4_GRP1_DisableClock

  3262.   * @param  Periphs This parameter can be a combination of the following values:

  3263.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  3264.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  3265.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  3266.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  3267.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  3268.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  3269.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  3270.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  3271.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  3272.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  3273.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  3274.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  3275.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  3276.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  3277.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  3278.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  3279.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  3280.   *

  3281.   *         (*) value not defined in all devices.

  3282.   * @retval None

  3283. */

  3284. __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)

  3285. {

  3286.   CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);

  3287. }

  3288. 

  3289. /**

  3290.   * @brief  Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.

  3291.   * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3292.   *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3293.   *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3294.   *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3295.   *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3296.   *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3297.   *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3298.   *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3299.   *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3300.   *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3301.   *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

  3302.   *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_EnableClockSleep\n

  3303.   *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n

  3304.   *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n

  3305.   *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_EnableClockSleep\n

  3306.   *         AHB4LPENR    D3SRAM1LPEN   LL_C1_AHB4_GRP1_EnableClockSleep

  3307.   * @param  Periphs This parameter can be a combination of the following values:

  3308.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  3309.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  3310.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  3311.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  3312.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  3313.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  3314.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  3315.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  3316.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  3317.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  3318.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  3319.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  3320.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  3321.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  3322.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  3323.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  3324.   * @retval None

  3325. */

  3326. __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)

  3327. {

  3328.   __IO uint32_t tmpreg;

  3329.   SET_BIT(RCC_C1->AHB4LPENR, Periphs);

  3330.   /* Delay after an RCC peripheral clock enabling */

  3331.   tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);

  3332.   (void)tmpreg;

  3333. }

  3334. 

  3335. /**

  3336.   * @brief  Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.

  3337.   * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3338.   *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3339.   *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3340.   *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3341.   *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3342.   *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3343.   *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3344.   *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3345.   *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3346.   *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3347.   *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

  3348.   *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_DisableClockSleep\n

  3349.   *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n

  3350.   *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n

  3351.   *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_DisableClockSleep\n

  3352.   *         AHB4LPENR    D3SRAM1LPEN   LL_C1_AHB4_GRP1_DisableClockSleep

  3353.   * @param  Periphs This parameter can be a combination of the following values:

  3354.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  3355.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  3356.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  3357.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  3358.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  3359.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  3360.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  3361.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  3362.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  3363.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  3364.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  3365.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  3366.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  3367.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  3368.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  3369.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  3370.   * @retval None

  3371. */

  3372. __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)

  3373. {

  3374.   CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);

  3375. }

  3376. 

  3377. /**

  3378.   * @}

  3379.   */

  3380. 

  3381. /** @defgroup BUS_LL_EF_APB3 APB3

  3382.   * @{

  3383.   */

  3384. 

  3385. /**

  3386.   * @brief  Enable C1 APB3 peripherals clock.

  3387.   * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_EnableClock\n

  3388.   *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_EnableClock\n

  3389.   *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_EnableClock

  3390.   * @param  Periphs This parameter can be a combination of the following values:

  3391.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  3392.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  3393.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  3394.   *

  3395.   *         (*) value not defined in all devices.

  3396.   * @retval None

  3397. */

  3398. __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)

  3399. {

  3400.   __IO uint32_t tmpreg;

  3401.   SET_BIT(RCC_C1->APB3ENR, Periphs);

  3402.   /* Delay after an RCC peripheral clock enabling */

  3403.   tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);

  3404.   (void)tmpreg;

  3405. }

  3406. 

  3407. /**

  3408.   * @brief  Check if C1 APB3 peripheral clock is enabled or not

  3409.   * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_IsEnabledClock\n

  3410.   *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_IsEnabledClock\n

  3411.   *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_IsEnabledClock

  3412.   * @param  Periphs This parameter can be a combination of the following values:

  3413.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  3414.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  3415.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  3416.   *

  3417.   *         (*) value not defined in all devices.

  3418.   * @retval uint32_t

  3419. */

  3420. __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)

  3421. {

  3422.   return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);

  3423. }

  3424. 

  3425. /**

  3426.   * @brief  Disable C1 APB3 peripherals clock.

  3427.   * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_DisableClock\n

  3428.   *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_DisableClock\n

  3429.   *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_DisableClock

  3430.   * @param  Periphs This parameter can be a combination of the following values:

  3431.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  3432.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  3433.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  3434.   *

  3435.   *         (*) value not defined in all devices.

  3436.   * @retval None

  3437. */

  3438. __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)

  3439. {

  3440.   CLEAR_BIT(RCC_C1->APB3ENR, Periphs);

  3441. }

  3442. 

  3443. /**

  3444.   * @brief  Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.

  3445.   * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_EnableClockSleep\n

  3446.   *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_EnableClockSleep\n

  3447.   *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_EnableClockSleep

  3448.   * @param  Periphs This parameter can be a combination of the following values:

  3449.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  3450.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  3451.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  3452.   *

  3453.   *         (*) value not defined in all devices.

  3454.   * @retval None

  3455. */

  3456. __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)

  3457. {

  3458.   __IO uint32_t tmpreg;

  3459.   SET_BIT(RCC_C1->APB3LPENR, Periphs);

  3460.   /* Delay after an RCC peripheral clock enabling */

  3461.   tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);

  3462.   (void)tmpreg;

  3463. }

  3464. 

  3465. /**

  3466.   * @brief  Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.

  3467.   * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_DisableClockSleep\n

  3468.   *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_DisableClockSleep\n

  3469.   *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_DisableClockSleep

  3470.   * @param  Periphs This parameter can be a combination of the following values:

  3471.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  3472.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  3473.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  3474.   *

  3475.   *         (*) value not defined in all devices.

  3476.   * @retval None

  3477. */

  3478. __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)

  3479. {

  3480.   CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);

  3481. }

  3482. 

  3483. /**

  3484.   * @}

  3485.   */

  3486. 

  3487. /** @defgroup BUS_LL_EF_APB1 APB1

  3488.   * @{

  3489.   */

  3490. 

  3491. /**

  3492.   * @brief  Enable C1 APB1 peripherals clock.

  3493.   * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_EnableClock\n

  3494.   *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_EnableClock\n

  3495.   *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_EnableClock\n

  3496.   *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_EnableClock\n

  3497.   *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_EnableClock\n

  3498.   *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_EnableClock\n

  3499.   *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_EnableClock\n

  3500.   *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_EnableClock\n

  3501.   *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_EnableClock\n

  3502.   *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_EnableClock\n

  3503.   *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_EnableClock\n

  3504.   *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_EnableClock\n

  3505.   *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_EnableClock\n

  3506.   *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_EnableClock\n

  3507.   *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_EnableClock\n

  3508.   *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_EnableClock\n

  3509.   *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_EnableClock\n

  3510.   *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_EnableClock\n

  3511.   *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_EnableClock\n

  3512.   *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_EnableClock\n

  3513.   *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_EnableClock\n

  3514.   *         APB1LENR     CECEN         LL_C1_APB1_GRP1_EnableClock\n

  3515.   *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_EnableClock\n

  3516.   *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_EnableClock\n

  3517.   *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_EnableClock

  3518.   * @param  Periphs This parameter can be a combination of the following values:

  3519.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  3520.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  3521.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  3522.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  3523.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  3524.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  3525.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  3526.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  3527.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  3528.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  3529.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  3530.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  3531.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  3532.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  3533.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  3534.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  3535.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  3536.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  3537.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  3538.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  3539.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  3540.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  3541.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  3542.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  3543.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  3544.   * @retval None

  3545. */

  3546. __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)

  3547. {

  3548.   __IO uint32_t tmpreg;

  3549.   SET_BIT(RCC_C1->APB1LENR, Periphs);

  3550.   /* Delay after an RCC peripheral clock enabling */

  3551.   tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);

  3552.   (void)tmpreg;

  3553. }

  3554. 

  3555. /**

  3556.   * @brief  Check if C1 APB1 peripheral clock is enabled or not

  3557.   * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3558.   *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3559.   *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3560.   *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3561.   *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3562.   *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3563.   *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_IsEnabledClock\n

  3564.   *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_IsEnabledClock\n

  3565.   *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_IsEnabledClock\n

  3566.   *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_IsEnabledClock\n

  3567.   *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_IsEnabledClock\n

  3568.   *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3569.   *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3570.   *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_IsEnabledClock\n

  3571.   *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_IsEnabledClock\n

  3572.   *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_IsEnabledClock\n

  3573.   *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_IsEnabledClock\n

  3574.   *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_IsEnabledClock\n

  3575.   *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3576.   *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3577.   *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_IsEnabledClock\n

  3578.   *         APB1LENR     CECEN         LL_C1_APB1_GRP1_IsEnabledClock\n

  3579.   *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_IsEnabledClock\n

  3580.   *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_IsEnabledClock\n

  3581.   *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_IsEnabledClock

  3582.   * @param  Periphs This parameter can be a combination of the following values:

  3583.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  3584.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  3585.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  3586.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  3587.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  3588.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  3589.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  3590.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  3591.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  3592.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  3593.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  3594.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  3595.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  3596.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  3597.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  3598.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  3599.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  3600.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  3601.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  3602.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  3603.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  3604.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  3605.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  3606.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  3607.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  3608.   * @retval uint32_t

  3609. */

  3610. __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

  3611. {

  3612.   return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);

  3613. }

  3614. 

  3615. /**

  3616.   * @brief  Disable C1 APB1 peripherals clock.

  3617.   * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_DisableClock\n

  3618.   *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_DisableClock\n

  3619.   *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_DisableClock\n

  3620.   *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_DisableClock\n

  3621.   *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_DisableClock\n

  3622.   *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_DisableClock\n

  3623.   *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_DisableClock\n

  3624.   *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_DisableClock\n

  3625.   *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_DisableClock\n

  3626.   *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_DisableClock\n

  3627.   *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_DisableClock\n

  3628.   *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_DisableClock\n

  3629.   *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_DisableClock\n

  3630.   *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_DisableClock\n

  3631.   *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_DisableClock\n

  3632.   *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_DisableClock\n

  3633.   *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_DisableClock\n

  3634.   *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_DisableClock\n

  3635.   *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_DisableClock\n

  3636.   *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_DisableClock\n

  3637.   *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_DisableClock\n

  3638.   *         APB1LENR     CECEN         LL_C1_APB1_GRP1_DisableClock\n

  3639.   *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_DisableClock\n

  3640.   *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_DisableClock\n

  3641.   *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_DisableClock

  3642.   * @param  Periphs This parameter can be a combination of the following values:

  3643.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  3644.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  3645.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  3646.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  3647.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  3648.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  3649.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  3650.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  3651.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  3652.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  3653.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  3654.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  3655.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  3656.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  3657.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  3658.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  3659.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  3660.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  3661.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  3662.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  3663.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  3664.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  3665.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  3666.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  3667.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  3668.   * @retval None

  3669. */

  3670. __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)

  3671. {

  3672.   CLEAR_BIT(RCC_C1->APB1LENR, Periphs);

  3673. }

  3674. 

  3675. /**

  3676.   * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.

  3677.   * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3678.   *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3679.   *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3680.   *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3681.   *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3682.   *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3683.   *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

  3684.   *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

  3685.   *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

  3686.   *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n

  3687.   *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

  3688.   *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3689.   *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3690.   *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_EnableClockSleep\n

  3691.   *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n

  3692.   *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n

  3693.   *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

  3694.   *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

  3695.   *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3696.   *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3697.   *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

  3698.   *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_EnableClockSleep\n

  3699.   *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

  3700.   *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

  3701.   *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_EnableClockSleep

  3702.   * @param  Periphs This parameter can be a combination of the following values:

  3703.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  3704.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  3705.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  3706.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  3707.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  3708.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  3709.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  3710.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  3711.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  3712.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  3713.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  3714.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  3715.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  3716.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  3717.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  3718.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  3719.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  3720.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  3721.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  3722.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  3723.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  3724.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  3725.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  3726.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  3727.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  3728.   * @retval None

  3729. */

  3730. __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

  3731. {

  3732.   __IO uint32_t tmpreg;

  3733.   SET_BIT(RCC_C1->APB1LLPENR, Periphs);

  3734.   /* Delay after an RCC peripheral clock enabling */

  3735.   tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);

  3736.   (void)tmpreg;

  3737. }

  3738. 

  3739. /**

  3740.   * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.

  3741.   * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3742.   *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3743.   *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3744.   *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3745.   *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3746.   *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3747.   *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

  3748.   *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

  3749.   *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

  3750.   *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n

  3751.   *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

  3752.   *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3753.   *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3754.   *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_DisableClockSleep\n

  3755.   *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n

  3756.   *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n

  3757.   *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

  3758.   *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

  3759.   *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3760.   *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3761.   *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

  3762.   *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_DisableClockSleep\n

  3763.   *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

  3764.   *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

  3765.   *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_DisableClockSleep

  3766.   * @param  Periphs This parameter can be a combination of the following values:

  3767.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  3768.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  3769.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  3770.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  3771.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  3772.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  3773.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  3774.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  3775.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  3776.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  3777.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  3778.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  3779.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  3780.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  3781.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  3782.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  3783.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  3784.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  3785.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  3786.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  3787.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  3788.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  3789.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  3790.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  3791.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  3792.   * @retval None

  3793. */

  3794. __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

  3795. {

  3796.   CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);

  3797. }

  3798. 

  3799. /**

  3800.   * @brief  Enable C1 APB1 peripherals clock.

  3801.   * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_EnableClock\n

  3802.   *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_EnableClock\n

  3803.   *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_EnableClock\n

  3804.   *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_EnableClock\n

  3805.   *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_EnableClock

  3806.   * @param  Periphs This parameter can be a combination of the following values:

  3807.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  3808.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  3809.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  3810.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  3811.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  3812.   * @retval None

  3813. */

  3814. __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)

  3815. {

  3816.   __IO uint32_t tmpreg;

  3817.   SET_BIT(RCC_C1->APB1HENR, Periphs);

  3818.   /* Delay after an RCC peripheral clock enabling */

  3819.   tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);

  3820.   (void)tmpreg;

  3821. }

  3822. 

  3823. /**

  3824.   * @brief  Check if C1 APB1 peripheral clock is enabled or not

  3825.   * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_IsEnabledClock\n

  3826.   *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_IsEnabledClock\n

  3827.   *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_IsEnabledClock\n

  3828.   *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_IsEnabledClock\n

  3829.   *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_IsEnabledClock

  3830.   * @param  Periphs This parameter can be a combination of the following values:

  3831.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  3832.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  3833.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  3834.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  3835.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  3836.   * @retval uint32_t

  3837. */

  3838. __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)

  3839. {

  3840.   return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);

  3841. }

  3842. 

  3843. /**

  3844.   * @brief  Disable C1 APB1 peripherals clock.

  3845.   * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_DisableClock\n

  3846.   *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_DisableClock\n

  3847.   *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_DisableClock\n

  3848.   *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_DisableClock\n

  3849.   *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_DisableClock

  3850.   * @param  Periphs This parameter can be a combination of the following values:

  3851.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  3852.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  3853.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  3854.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  3855.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  3856.   * @retval None

  3857. */

  3858. __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)

  3859. {

  3860.   CLEAR_BIT(RCC_C1->APB1HENR, Periphs);

  3861. }

  3862. 

  3863. /**

  3864.   * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.

  3865.   * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_EnableClockSleep\n

  3866.   *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_EnableClockSleep\n

  3867.   *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n

  3868.   *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n

  3869.   *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_EnableClockSleep

  3870.   * @param  Periphs This parameter can be a combination of the following values:

  3871.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  3872.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  3873.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  3874.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  3875.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  3876.   * @retval None

  3877. */

  3878. __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)

  3879. {

  3880.   __IO uint32_t tmpreg;

  3881.   SET_BIT(RCC_C1->APB1HLPENR, Periphs);

  3882.   /* Delay after an RCC peripheral clock enabling */

  3883.   tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);

  3884.   (void)tmpreg;

  3885. }

  3886. 

  3887. /**

  3888.   * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.

  3889.   * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_DisableClockSleep\n

  3890.   *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_DisableClockSleep\n

  3891.   *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n

  3892.   *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n

  3893.   *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_DisableClockSleep

  3894.   * @param  Periphs This parameter can be a combination of the following values:

  3895.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  3896.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  3897.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  3898.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  3899.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  3900.   * @retval None

  3901. */

  3902. __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)

  3903. {

  3904.   CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);

  3905. }

  3906. 

  3907. /**

  3908.   * @}

  3909.   */

  3910. 

  3911. /** @defgroup BUS_LL_EF_APB2 APB2

  3912.   * @{

  3913.   */

  3914. 

  3915. /**

  3916.   * @brief  Enable C1 APB2 peripherals clock.

  3917.   * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_EnableClock\n

  3918.   *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_EnableClock\n

  3919.   *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_EnableClock\n

  3920.   *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_EnableClock\n

  3921.   *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_EnableClock\n

  3922.   *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_EnableClock\n

  3923.   *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_EnableClock\n

  3924.   *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_EnableClock\n

  3925.   *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_EnableClock\n

  3926.   *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_EnableClock\n

  3927.   *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_EnableClock\n

  3928.   *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_EnableClock\n

  3929.   *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_EnableClock\n

  3930.   *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_EnableClock\n

  3931.   *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_EnableClock

  3932.   * @param  Periphs This parameter can be a combination of the following values:

  3933.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  3934.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  3935.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  3936.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  3937.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  3938.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  3939.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  3940.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  3941.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  3942.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  3943.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  3944.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  3945.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  3946.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  3947.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  3948.   * @retval None

  3949. */

  3950. __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)

  3951. {

  3952.   __IO uint32_t tmpreg;

  3953.   SET_BIT(RCC_C1->APB2ENR, Periphs);

  3954.   /* Delay after an RCC peripheral clock enabling */

  3955.   tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);

  3956.   (void)tmpreg;

  3957. }

  3958. 

  3959. /**

  3960.   * @brief  Check if C1 APB2 peripheral clock is enabled or not

  3961.   * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_IsEnabledClock\n

  3962.   *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_IsEnabledClock\n

  3963.   *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_IsEnabledClock\n

  3964.   *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_IsEnabledClock\n

  3965.   *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n

  3966.   *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_IsEnabledClock\n

  3967.   *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_IsEnabledClock\n

  3968.   *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_IsEnabledClock\n

  3969.   *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_IsEnabledClock\n

  3970.   *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_IsEnabledClock\n

  3971.   *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n

  3972.   *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_IsEnabledClock\n

  3973.   *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_IsEnabledClock\n

  3974.   *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_IsEnabledClock\n

  3975.   *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_IsEnabledClock

  3976.   * @param  Periphs This parameter can be a combination of the following values:

  3977.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  3978.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  3979.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  3980.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  3981.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  3982.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  3983.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  3984.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  3985.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  3986.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  3987.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  3988.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  3989.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  3990.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  3991.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  3992.   * @retval uint32_t

  3993. */

  3994. __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

  3995. {

  3996.   return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);

  3997. }

  3998. 

  3999. /**

  4000.   * @brief  Disable C1 APB2 peripherals clock.

  4001.   * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_DisableClock\n

  4002.   *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_DisableClock\n

  4003.   *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_DisableClock\n

  4004.   *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_DisableClock\n

  4005.   *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_DisableClock\n

  4006.   *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_DisableClock\n

  4007.   *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_DisableClock\n

  4008.   *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_DisableClock\n

  4009.   *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_DisableClock\n

  4010.   *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_DisableClock\n

  4011.   *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_DisableClock\n

  4012.   *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_DisableClock\n

  4013.   *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_DisableClock\n

  4014.   *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_DisableClock\n

  4015.   *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_DisableClock

  4016.   * @param  Periphs This parameter can be a combination of the following values:

  4017.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  4018.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  4019.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  4020.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  4021.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  4022.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  4023.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  4024.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  4025.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  4026.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  4027.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  4028.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  4029.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  4030.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  4031.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  4032.   * @retval None

  4033. */

  4034. __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)

  4035. {

  4036.   CLEAR_BIT(RCC_C1->APB2ENR, Periphs);

  4037. }

  4038. 

  4039. /**

  4040.   * @brief  Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.

  4041.   * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

  4042.   *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

  4043.   *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n

  4044.   *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n

  4045.   *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

  4046.   *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

  4047.   *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n

  4048.   *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n

  4049.   *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n

  4050.   *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

  4051.   *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

  4052.   *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

  4053.   *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

  4054.   *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n

  4055.   *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_EnableClockSleep

  4056.   * @param  Periphs This parameter can be a combination of the following values:

  4057.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  4058.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  4059.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  4060.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  4061.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  4062.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  4063.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  4064.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  4065.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  4066.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  4067.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  4068.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  4069.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  4070.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  4071.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  4072.   * @retval None

  4073. */

  4074. __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

  4075. {

  4076.   __IO uint32_t tmpreg;

  4077.   SET_BIT(RCC_C1->APB2LPENR, Periphs);

  4078.   /* Delay after an RCC peripheral clock enabling */

  4079.   tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);

  4080.   (void)tmpreg;

  4081. }

  4082. 

  4083. /**

  4084.   * @brief  Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.

  4085.   * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

  4086.   *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

  4087.   *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n

  4088.   *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n

  4089.   *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

  4090.   *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

  4091.   *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n

  4092.   *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n

  4093.   *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n

  4094.   *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

  4095.   *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

  4096.   *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

  4097.   *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

  4098.   *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n

  4099.   *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_DisableClockSleep

  4100.   * @param  Periphs This parameter can be a combination of the following values:

  4101.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  4102.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  4103.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  4104.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  4105.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  4106.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  4107.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  4108.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  4109.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  4110.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  4111.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  4112.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  4113.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  4114.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  4115.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  4116.   * @retval None

  4117. */

  4118. __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

  4119. {

  4120.   CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);

  4121. }

  4122. 

  4123. /**

  4124.   * @}

  4125.   */

  4126. 

  4127. /** @defgroup BUS_LL_EF_APB4 APB4

  4128.   * @{

  4129.   */

  4130. 

  4131. /**

  4132.   * @brief  Enable C1 APB4 peripherals clock.

  4133.   * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_EnableClock\n

  4134.   *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_EnableClock\n

  4135.   *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_EnableClock\n

  4136.   *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_EnableClock\n

  4137.   *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_EnableClock\n

  4138.   *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_EnableClock\n

  4139.   *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_EnableClock\n

  4140.   *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_EnableClock\n

  4141.   *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_EnableClock\n

  4142.   *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_EnableClock\n

  4143.   *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_EnableClock\n

  4144.   *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClock

  4145.   * @param  Periphs This parameter can be a combination of the following values:

  4146.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  4147.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  4148.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  4149.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  4150.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  4151.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  4152.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  4153.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  4154.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  4155.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  4156.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  4157.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  4158.   * @retval None

  4159. */

  4160. __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)

  4161. {

  4162.   __IO uint32_t tmpreg;

  4163.   SET_BIT(RCC_C1->APB4ENR, Periphs);

  4164.   /* Delay after an RCC peripheral clock enabling */

  4165.   tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);

  4166.   (void)tmpreg;

  4167. }

  4168. 

  4169. /**

  4170.   * @brief  Check if C1 APB4 peripheral clock is enabled or not

  4171.   * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_IsEnabledClock\n

  4172.   *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_IsEnabledClock\n

  4173.   *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_IsEnabledClock\n

  4174.   *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_IsEnabledClock\n

  4175.   *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_IsEnabledClock\n

  4176.   *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_IsEnabledClock\n

  4177.   *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_IsEnabledClock\n

  4178.   *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_IsEnabledClock\n

  4179.   *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_IsEnabledClock\n

  4180.   *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_IsEnabledClock\n

  4181.   *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_IsEnabledClock\n

  4182.   *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_IsEnabledClock

  4183.   * @param  Periphs This parameter can be a combination of the following values:

  4184.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  4185.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  4186.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  4187.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  4188.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  4189.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  4190.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  4191.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  4192.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  4193.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  4194.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  4195.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  4196.   * @retval uint32_t

  4197. */

  4198. __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)

  4199. {

  4200.   return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);

  4201. }

  4202. 

  4203. /**

  4204.   * @brief  Disable C1 APB4 peripherals clock.

  4205.   * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_DisableClock\n

  4206.   *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_DisableClock\n

  4207.   *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_DisableClock\n

  4208.   *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_DisableClock\n

  4209.   *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_DisableClock\n

  4210.   *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_DisableClock\n

  4211.   *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_DisableClock\n

  4212.   *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_DisableClock\n

  4213.   *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_DisableClock\n

  4214.   *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_DisableClock\n

  4215.   *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_DisableClock\n

  4216.   *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClock

  4217.   * @param  Periphs This parameter can be a combination of the following values:

  4218.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  4219.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  4220.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  4221.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  4222.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  4223.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  4224.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  4225.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  4226.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  4227.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  4228.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  4229.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  4230.   * @retval None

  4231. */

  4232. __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)

  4233. {

  4234.   CLEAR_BIT(RCC_C1->APB4ENR, Periphs);

  4235. }

  4236. 

  4237. /**

  4238.   * @brief  Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.

  4239.   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

  4240.   *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_EnableClockSleep\n

  4241.   *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n

  4242.   *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n

  4243.   *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

  4244.   *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

  4245.   *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

  4246.   *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

  4247.   *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

  4248.   *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_EnableClockSleep\n

  4249.   *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

  4250.   *         APB4LPENR    SAI4LPEN      LL_C1_APB4_GRP1_EnableClockSleep

  4251.   * @param  Periphs This parameter can be a combination of the following values:

  4252.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  4253.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  4254.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  4255.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  4256.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  4257.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  4258.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  4259.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  4260.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  4261.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  4262.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  4263.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  4264.   * @retval None

  4265. */

  4266. __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)

  4267. {

  4268.   __IO uint32_t tmpreg;

  4269.   SET_BIT(RCC_C1->APB4LPENR, Periphs);

  4270.   /* Delay after an RCC peripheral clock enabling */

  4271.   tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);

  4272.   (void)tmpreg;

  4273. }

  4274. 

  4275. /**

  4276.   * @brief  Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.

  4277.   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

  4278.   *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_DisableClockSleep\n

  4279.   *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n

  4280.   *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n

  4281.   *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

  4282.   *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

  4283.   *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

  4284.   *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

  4285.   *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

  4286.   *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_DisableClockSleep\n

  4287.   *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

  4288.   *         APB4LPENR    SAI4LPEN      LL_C1_APB4_GRP1_DisableClockSleep

  4289.   * @param  Periphs This parameter can be a combination of the following values:

  4290.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  4291.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  4292.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  4293.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  4294.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  4295.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  4296.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  4297.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  4298.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  4299.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  4300.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  4301.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  4302.   * @retval None

  4303. */

  4304. __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)

  4305. {

  4306.   CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);

  4307. }

  4308. 

  4309. /**

  4310.   * @}

  4311.   */

  4312. 

  4313. /** @defgroup BUS_LL_EF_AHB3 AHB3

  4314.   * @{

  4315.   */

  4316. 

  4317. /**

  4318.   * @brief  Enable C2 AHB3 peripherals clock.

  4319.   * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_EnableClock\n

  4320.   *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_EnableClock\n

  4321.   *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_EnableClock\n

  4322.   *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_EnableClock\n

  4323.   *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_EnableClock\n

  4324.   *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_EnableClock\n

  4325.   *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_EnableClock\n

  4326.   *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_EnableClock\n

  4327.   *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_EnableClock\n

  4328.   *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_EnableClock\n

  4329.   *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_EnableClock

  4330.   * @param  Periphs This parameter can be a combination of the following values:

  4331.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  4332.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  4333.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  4334.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  4335.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  4336.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  4337.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  4338.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  4339.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  4340.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  4341.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  4342.   * @retval None

  4343. */

  4344. __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)

  4345. {

  4346.   __IO uint32_t tmpreg;

  4347.   SET_BIT(RCC_C2->AHB3ENR, Periphs);

  4348.   /* Delay after an RCC peripheral clock enabling */

  4349.   tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);

  4350.   (void)tmpreg;

  4351. }

  4352. 

  4353. /**

  4354.   * @brief  Check if C2 AHB3 peripheral clock is enabled or not

  4355.   * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_IsEnabledClock\n

  4356.   *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_IsEnabledClock\n

  4357.   *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_IsEnabledClock\n

  4358.   *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_IsEnabledClock\n

  4359.   *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_IsEnabledClock\n

  4360.   *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_IsEnabledClock\n

  4361.   *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock\n

  4362.   *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_IsEnabledClock\n

  4363.   *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_IsEnabledClock\n

  4364.   *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n

  4365.   *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_IsEnabledClock

  4366.   * @param  Periphs This parameter can be a combination of the following values:

  4367.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  4368.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  4369.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  4370.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  4371.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  4372.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  4373.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  4374.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  4375.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  4376.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  4377.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  4378.   * @retval uint32_t

  4379. */

  4380. __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)

  4381. {

  4382.   return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);

  4383. }

  4384. 

  4385. /**

  4386.   * @brief  Disable C2 AHB3 peripherals clock.

  4387.   * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_DisableClock\n

  4388.   *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_DisableClock\n

  4389.   *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_DisableClock\n

  4390.   *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_DisableClock\n

  4391.   *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_DisableClock\n

  4392.   *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_DisableClock\n

  4393.   *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_DisableClock\n

  4394.   *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_DisableClock\n

  4395.   *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_DisableClock\n

  4396.   *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_DisableClock\n

  4397.   *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_DisableClock

  4398.   * @param  Periphs This parameter can be a combination of the following values:

  4399.   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

  4400.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  4401.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  4402.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  4403.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  4404.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  4405.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  4406.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  4407.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  4408.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  4409.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  4410.   * @retval None

  4411. */

  4412. __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)

  4413. {

  4414.   CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);

  4415. }

  4416. 

  4417. /**

  4418.   * @brief  Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.

  4419.   * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n

  4420.   *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

  4421.   *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n

  4422.   *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_EnableClockSleep\n

  4423.   *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n

  4424.   *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n

  4425.   *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

  4426.   *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

  4427.   *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

  4428.   *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n

  4429.   *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_EnableClockSleep

  4430.   * @param  Periphs This parameter can be a combination of the following values:

  4431.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  4432.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  4433.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  4434.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  4435.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  4436.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  4437.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  4438.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  4439.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  4440.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  4441.   * @retval None

  4442. */

  4443. __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)

  4444. {

  4445.   __IO uint32_t tmpreg;

  4446.   SET_BIT(RCC_C2->AHB3LPENR, Periphs);

  4447.   /* Delay after an RCC peripheral clock enabling */

  4448.   tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);

  4449.   (void)tmpreg;

  4450. }

  4451. 

  4452. /**

  4453.   * @brief  Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.

  4454.   * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n

  4455.   *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

  4456.   *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n

  4457.   *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_DisableClockSleep\n

  4458.   *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n

  4459.   *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n

  4460.   *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

  4461.   *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

  4462.   *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

  4463.   *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n

  4464.   *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_DisableClockSleep

  4465.   * @param  Periphs This parameter can be a combination of the following values:

  4466.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

  4467.   *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

  4468.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

  4469.   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

  4470.   *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

  4471.   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

  4472.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

  4473.   *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

  4474.   *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

  4475.   *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

  4476.   * @retval None

  4477. */

  4478. __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)

  4479. {

  4480.   CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);

  4481. }

  4482. 

  4483. /**

  4484.   * @}

  4485.   */

  4486. 

  4487. /** @defgroup BUS_LL_EF_AHB1 AHB1

  4488.   * @{

  4489.   */

  4490. 

  4491. /**

  4492.   * @brief  Enable C2 AHB1 peripherals clock.

  4493.   * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n

  4494.   *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n

  4495.   *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_EnableClock\n

  4496.   *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_EnableClock\n

  4497.   *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_EnableClock\n

  4498.   *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_EnableClock\n

  4499.   *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_EnableClock\n

  4500.   *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n

  4501.   *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock\n

  4502.   *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n

  4503.   *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock

  4504.   * @param  Periphs This parameter can be a combination of the following values:

  4505.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  4506.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  4507.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  4508.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  4509.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  4510.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  4511.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  4512.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  4513.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  4514.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  4515.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  4516.   * @retval None

  4517. */

  4518. __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)

  4519. {

  4520.   __IO uint32_t tmpreg;

  4521.   SET_BIT(RCC_C2->AHB1ENR, Periphs);

  4522.   /* Delay after an RCC peripheral clock enabling */

  4523.   tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);

  4524.   (void)tmpreg;

  4525. }

  4526. 

  4527. /**

  4528.   * @brief  Check if C2 AHB1 peripheral clock is enabled or not

  4529.   * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n

  4530.   *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n

  4531.   *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_IsEnabledClock\n

  4532.   *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_IsEnabledClock\n

  4533.   *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_IsEnabledClock\n

  4534.   *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n

  4535.   *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n

  4536.   *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n

  4537.   *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock\n

  4538.   *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n

  4539.   *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock

  4540.   * @param  Periphs This parameter can be a combination of the following values:

  4541.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  4542.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  4543.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  4544.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  4545.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  4546.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  4547.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  4548.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  4549.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  4550.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  4551.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  4552.   * @retval uint32_t

  4553. */

  4554. __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

  4555. {

  4556.   return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);

  4557. }

  4558. 

  4559. /**

  4560.   * @brief  Disable C2 AHB1 peripherals clock.

  4561.   * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n

  4562.   *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n

  4563.   *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_DisableClock\n

  4564.   *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_DisableClock\n

  4565.   *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_DisableClock\n

  4566.   *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_DisableClock\n

  4567.   *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_DisableClock\n

  4568.   *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n

  4569.   *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock\n

  4570.   *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n

  4571.   *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock

  4572.   * @param  Periphs This parameter can be a combination of the following values:

  4573.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  4574.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  4575.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  4576.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  4577.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  4578.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  4579.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  4580.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  4581.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  4582.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  4583.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  4584.   * @retval None

  4585. */

  4586. __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)

  4587. {

  4588.   CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);

  4589. }

  4590. 

  4591. /**

  4592.   * @brief  Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.

  4593.   * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n

  4594.   *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n

  4595.   *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_EnableClockSleep\n

  4596.   *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_EnableClockSleep\n

  4597.   *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_EnableClockSleep\n

  4598.   *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n

  4599.   *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n

  4600.   *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n

  4601.   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n

  4602.   *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n

  4603.   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep

  4604.   * @param  Periphs This parameter can be a combination of the following values:

  4605.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  4606.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  4607.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  4608.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  4609.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  4610.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  4611.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  4612.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  4613.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  4614.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  4615.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  4616.   * @retval None

  4617. */

  4618. __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

  4619. {

  4620.   __IO uint32_t tmpreg;

  4621.   SET_BIT(RCC_C2->AHB1LPENR, Periphs);

  4622.   /* Delay after an RCC peripheral clock enabling */

  4623.   tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);

  4624.   (void)tmpreg;

  4625. }

  4626. 

  4627. /**

  4628.   * @brief  Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.

  4629.   * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n

  4630.   *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n

  4631.   *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_DisableClockSleep\n

  4632.   *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_DisableClockSleep\n

  4633.   *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_DisableClockSleep\n

  4634.   *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n

  4635.   *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n

  4636.   *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n

  4637.   *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n

  4638.   *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n

  4639.   *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep

  4640.   * @param  Periphs This parameter can be a combination of the following values:

  4641.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  4642.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

  4643.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

  4644.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

  4645.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

  4646.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

  4647.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

  4648.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

  4649.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

  4650.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

  4651.   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

  4652.   * @retval None

  4653. */

  4654. __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

  4655. {

  4656.   CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);

  4657. }

  4658. 

  4659. /**

  4660.   * @}

  4661.   */

  4662. 

  4663. /** @defgroup BUS_LL_EF_AHB2 AHB2

  4664.   * @{

  4665.   */

  4666. 

  4667. /**

  4668.   * @brief  Enable C2 AHB2 peripherals clock.

  4669.   * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_EnableClock\n

  4670.   *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_EnableClock\n

  4671.   *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_EnableClock\n

  4672.   *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_EnableClock\n

  4673.   *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_EnableClock

  4674.   * @param  Periphs This parameter can be a combination of the following values:

  4675.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  4676.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  4677.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  4678.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  4679.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  4680.   *

  4681.   *         (*) value not defined in all devices.

  4682.   * @retval None

  4683. */

  4684. __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)

  4685. {

  4686.   __IO uint32_t tmpreg;

  4687.   SET_BIT(RCC_C2->AHB2ENR, Periphs);

  4688.   /* Delay after an RCC peripheral clock enabling */

  4689.   tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);

  4690.   (void)tmpreg;

  4691. }

  4692. 

  4693. /**

  4694.   * @brief  Check if C2 AHB2 peripheral clock is enabled or not

  4695.   * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_IsEnabledClock\n

  4696.   *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_IsEnabledClock\n

  4697.   *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_IsEnabledClock\n

  4698.   *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_IsEnabledClock\n

  4699.   *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_IsEnabledClock

  4700.   * @param  Periphs This parameter can be a combination of the following values:

  4701.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  4702.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  4703.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  4704.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  4705.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  4706.   *

  4707.   *         (*) value not defined in all devices.

  4708.   * @retval uint32_t

  4709. */

  4710. __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)

  4711. {

  4712.   return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);

  4713. }

  4714. 

  4715. /**

  4716.   * @brief  Disable C2 AHB2 peripherals clock.

  4717.   * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_DisableClock\n

  4718.   *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_DisableClock\n

  4719.   *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_DisableClock\n

  4720.   *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_DisableClock\n

  4721.   *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_DisableClock

  4722.   * @param  Periphs This parameter can be a combination of the following values:

  4723.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  4724.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  4725.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  4726.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  4727.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  4728.   *

  4729.   *         (*) value not defined in all devices.

  4730.   * @retval None

  4731. */

  4732. __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)

  4733. {

  4734.   CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);

  4735. }

  4736. 

  4737. /**

  4738.   * @brief  Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.

  4739.   * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n

  4740.   *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n

  4741.   *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n

  4742.   *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_EnableClockSleep\n

  4743.   *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_EnableClockSleep\n

  4744.   *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n

  4745.   *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n

  4746.   *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_EnableClockSleep

  4747.   * @param  Periphs This parameter can be a combination of the following values:

  4748.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  4749.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  4750.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  4751.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  4752.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  4753.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  4754.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  4755.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  4756.   *

  4757.   *         (*) value not defined in all devices.

  4758.   * @retval None

  4759. */

  4760. __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)

  4761. {

  4762.   __IO uint32_t tmpreg;

  4763.   SET_BIT(RCC_C2->AHB2LPENR, Periphs);

  4764.   /* Delay after an RCC peripheral clock enabling */

  4765.   tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);

  4766.   (void)tmpreg;

  4767. }

  4768. 

  4769. /**

  4770.   * @brief  Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.

  4771.   * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n

  4772.   *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n

  4773.   *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n

  4774.   *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_DisableClockSleep\n

  4775.   *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_DisableClockSleep\n

  4776.   *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n

  4777.   *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n

  4778.   *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_DisableClockSleep

  4779.   * @param  Periphs This parameter can be a combination of the following values:

  4780.   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

  4781.   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

  4782.   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

  4783.   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

  4784.   *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

  4785.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

  4786.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

  4787.   *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

  4788.   *

  4789.   *         (*) value not defined in all devices.

  4790.   * @retval None

  4791. */

  4792. __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)

  4793. {

  4794.   CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);

  4795. }

  4796. 

  4797. /**

  4798.   * @}

  4799.   */

  4800. 

  4801. /** @defgroup BUS_LL_EF_AHB4 AHB4

  4802.   * @{

  4803.   */

  4804. 

  4805. /**

  4806.   * @brief  Enable C2 AHB4 peripherals clock.

  4807.   * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_EnableClock\n

  4808.   *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_EnableClock\n

  4809.   *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_EnableClock\n

  4810.   *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_EnableClock\n

  4811.   *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_EnableClock\n

  4812.   *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_EnableClock\n

  4813.   *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_EnableClock\n

  4814.   *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_EnableClock\n

  4815.   *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_EnableClock\n

  4816.   *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_EnableClock\n

  4817.   *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_EnableClock\n

  4818.   *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_EnableClock\n

  4819.   *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_EnableClock\n

  4820.   *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_EnableClock\n

  4821.   *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_EnableClock\n

  4822.   *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_EnableClock\n

  4823.   *         AHB4ENR      D3SRAM1EN     LL_C2_AHB4_GRP1_EnableClock

  4824.   * @param  Periphs This parameter can be a combination of the following values:

  4825.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  4826.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  4827.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  4828.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  4829.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  4830.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  4831.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  4832.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  4833.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  4834.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  4835.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  4836.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  4837.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  4838.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  4839.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  4840.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  4841.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  4842.   *

  4843.   *         (*) value not defined in all devices.

  4844.   * @retval None

  4845. */

  4846. __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)

  4847. {

  4848.   __IO uint32_t tmpreg;

  4849.   SET_BIT(RCC_C2->AHB4ENR, Periphs);

  4850.   /* Delay after an RCC peripheral clock enabling */

  4851.   tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);

  4852.   (void)tmpreg;

  4853. }

  4854. 

  4855. /**

  4856.   * @brief  Check if C2 AHB4 peripheral clock is enabled or not

  4857.   * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4858.   *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4859.   *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4860.   *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4861.   *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4862.   *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4863.   *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4864.   *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4865.   *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4866.   *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4867.   *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

  4868.   *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_IsEnabledClock\n

  4869.   *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_IsEnabledClock\n

  4870.   *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_IsEnabledClock\n

  4871.   *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_IsEnabledClock\n

  4872.   *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_IsEnabledClock\n

  4873.   *         AHB4ENR      D3SRAM1EN     LL_C2_AHB4_GRP1_IsEnabledClock

  4874.   * @param  Periphs This parameter can be a combination of the following values:

  4875.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  4876.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  4877.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  4878.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  4879.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  4880.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  4881.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  4882.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  4883.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  4884.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  4885.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  4886.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  4887.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  4888.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  4889.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  4890.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  4891.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  4892.   *

  4893.   *         (*) value not defined in all devices.

  4894.   * @retval uint32_t

  4895. */

  4896. __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)

  4897. {

  4898.   return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);

  4899. }

  4900. 

  4901. /**

  4902.   * @brief  Disable C2 AHB4 peripherals clock.

  4903.   * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_DisableClock\n

  4904.   *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_DisableClock\n

  4905.   *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_DisableClock\n

  4906.   *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_DisableClock\n

  4907.   *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_DisableClock\n

  4908.   *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_DisableClock\n

  4909.   *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_DisableClock\n

  4910.   *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_DisableClock\n

  4911.   *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_DisableClock\n

  4912.   *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_DisableClock\n

  4913.   *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_DisableClock\n

  4914.   *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_DisableClock\n

  4915.   *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_DisableClock\n

  4916.   *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_DisableClock\n

  4917.   *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_DisableClock\n

  4918.   *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_DisableClock\n

  4919.   *         AHB4ENR      D3SRAM1EN     LL_C2_AHB4_GRP1_DisableClock

  4920.   * @param  Periphs This parameter can be a combination of the following values:

  4921.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  4922.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  4923.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  4924.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  4925.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  4926.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  4927.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  4928.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  4929.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  4930.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  4931.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  4932.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  4933.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  4934.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  4935.   *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

  4936.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  4937.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  4938.   *

  4939.   *         (*) value not defined in all devices.

  4940.   * @retval None

  4941. */

  4942. __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)

  4943. {

  4944.   CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);

  4945. }

  4946. 

  4947. /**

  4948.   * @brief  Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.

  4949.   * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4950.   *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4951.   *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4952.   *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4953.   *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4954.   *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4955.   *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4956.   *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4957.   *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4958.   *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4959.   *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

  4960.   *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_EnableClockSleep\n

  4961.   *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n

  4962.   *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n

  4963.   *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_EnableClockSleep\n

  4964.   *         AHB4LPENR    D3SRAM1LPEN   LL_C2_AHB4_GRP1_EnableClockSleep

  4965.   * @param  Periphs This parameter can be a combination of the following values:

  4966.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  4967.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  4968.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  4969.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  4970.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  4971.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  4972.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  4973.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  4974.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  4975.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  4976.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  4977.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  4978.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  4979.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  4980.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  4981.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  4982.   * @retval None

  4983. */

  4984. __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)

  4985. {

  4986.   __IO uint32_t tmpreg;

  4987.   SET_BIT(RCC_C2->AHB4LPENR, Periphs);

  4988.   /* Delay after an RCC peripheral clock enabling */

  4989.   tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);

  4990.   (void)tmpreg;

  4991. }

  4992. 

  4993. /**

  4994.   * @brief  Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.

  4995.   * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  4996.   *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  4997.   *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  4998.   *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  4999.   *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  5000.   *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  5001.   *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  5002.   *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  5003.   *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  5004.   *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  5005.   *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

  5006.   *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_DisableClockSleep\n

  5007.   *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n

  5008.   *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n

  5009.   *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_DisableClockSleep\n

  5010.   *         AHB4LPENR    D3SRAM1LPEN   LL_C2_AHB4_GRP1_DisableClockSleep

  5011.   * @param  Periphs This parameter can be a combination of the following values:

  5012.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

  5013.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

  5014.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

  5015.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

  5016.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

  5017.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

  5018.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

  5019.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

  5020.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

  5021.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

  5022.   *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

  5023.   *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

  5024.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

  5025.   *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

  5026.   *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

  5027.   *         @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1

  5028.   * @retval None

  5029. */

  5030. __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)

  5031. {

  5032.   CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);

  5033. }

  5034. 

  5035. /**

  5036.   * @}

  5037.   */

  5038. 

  5039. /** @defgroup BUS_LL_EF_APB3 APB3

  5040.   * @{

  5041.   */

  5042. 

  5043. /**

  5044.   * @brief  Enable C2 APB3 peripherals clock.

  5045.   * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_EnableClock\n

  5046.   *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_EnableClock\n

  5047.   *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_EnableClock

  5048.   * @param  Periphs This parameter can be a combination of the following values:

  5049.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  5050.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  5051.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  5052.   *

  5053.   *         (*) value not defined in all devices.

  5054.   * @retval None

  5055. */

  5056. __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)

  5057. {

  5058.   __IO uint32_t tmpreg;

  5059.   SET_BIT(RCC_C2->APB3ENR, Periphs);

  5060.   /* Delay after an RCC peripheral clock enabling */

  5061.   tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);

  5062.   (void)tmpreg;

  5063. }

  5064. 

  5065. /**

  5066.   * @brief  Check if C2 APB3 peripheral clock is enabled or not

  5067.   * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_IsEnabledClock\n

  5068.   *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_IsEnabledClock\n

  5069.   *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_IsEnabledClock

  5070.   * @param  Periphs This parameter can be a combination of the following values:

  5071.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  5072.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  5073.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  5074.   *

  5075.   *         (*) value not defined in all devices.

  5076.   * @retval uint32_t

  5077. */

  5078. __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)

  5079. {

  5080.   return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);

  5081. }

  5082. 

  5083. /**

  5084.   * @brief  Disable C2 APB3 peripherals clock.

  5085.   * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_DisableClock\n

  5086.   *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_DisableClock\n

  5087.   *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_DisableClock

  5088.   * @param  Periphs This parameter can be a combination of the following values:

  5089.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  5090.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  5091.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  5092.   *

  5093.   *         (*) value not defined in all devices.

  5094.   * @retval None

  5095. */

  5096. __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)

  5097. {

  5098.   CLEAR_BIT(RCC_C2->APB3ENR, Periphs);

  5099. }

  5100. 

  5101. /**

  5102.   * @brief  Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.

  5103.   * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_EnableClockSleep\n

  5104.   *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_EnableClockSleep\n

  5105.   *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_EnableClockSleep

  5106.   * @param  Periphs This parameter can be a combination of the following values:

  5107.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  5108.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  5109.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  5110.   *

  5111.   *         (*) value not defined in all devices.

  5112.   * @retval None

  5113. */

  5114. __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)

  5115. {

  5116.   __IO uint32_t tmpreg;

  5117.   SET_BIT(RCC_C2->APB3LPENR, Periphs);

  5118.   /* Delay after an RCC peripheral clock enabling */

  5119.   tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);

  5120.   (void)tmpreg;

  5121. }

  5122. 

  5123. /**

  5124.   * @brief  Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.

  5125.   * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_DisableClockSleep\n

  5126.   *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_DisableClockSleep\n

  5127.   *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_DisableClockSleep

  5128.   * @param  Periphs This parameter can be a combination of the following values:

  5129.   *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

  5130.   *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

  5131.   *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

  5132.   *

  5133.   *         (*) value not defined in all devices.

  5134.   * @retval None

  5135. */

  5136. __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)

  5137. {

  5138.   CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);

  5139. }

  5140. 

  5141. /**

  5142.   * @}

  5143.   */

  5144. 

  5145. /** @defgroup BUS_LL_EF_APB1 APB1

  5146.   * @{

  5147.   */

  5148. 

  5149. /**

  5150.   * @brief  Enable C2 APB1 peripherals clock.

  5151.   * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_EnableClock\n

  5152.   *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_EnableClock\n

  5153.   *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_EnableClock\n

  5154.   *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_EnableClock\n

  5155.   *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_EnableClock\n

  5156.   *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_EnableClock\n

  5157.   *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_EnableClock\n

  5158.   *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_EnableClock\n

  5159.   *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_EnableClock\n

  5160.   *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_EnableClock\n

  5161.   *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_EnableClock\n

  5162.   *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_EnableClock\n

  5163.   *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_EnableClock\n

  5164.   *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_EnableClock\n

  5165.   *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_EnableClock\n

  5166.   *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_EnableClock\n

  5167.   *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_EnableClock\n

  5168.   *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_EnableClock\n

  5169.   *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_EnableClock\n

  5170.   *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_EnableClock\n

  5171.   *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_EnableClock\n

  5172.   *         APB1LENR     CECEN         LL_C2_APB1_GRP1_EnableClock\n

  5173.   *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_EnableClock\n

  5174.   *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_EnableClock\n

  5175.   *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_EnableClock

  5176.   * @param  Periphs This parameter can be a combination of the following values:

  5177.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  5178.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  5179.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  5180.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  5181.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  5182.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  5183.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  5184.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  5185.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  5186.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  5187.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  5188.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  5189.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  5190.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  5191.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  5192.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  5193.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  5194.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  5195.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  5196.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  5197.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  5198.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  5199.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  5200.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  5201.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  5202.   * @retval None

  5203. */

  5204. __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)

  5205. {

  5206.   __IO uint32_t tmpreg;

  5207.   SET_BIT(RCC_C2->APB1LENR, Periphs);

  5208.   /* Delay after an RCC peripheral clock enabling */

  5209.   tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);

  5210.   (void)tmpreg;

  5211. }

  5212. 

  5213. /**

  5214.   * @brief  Check if C2 APB1 peripheral clock is enabled or not

  5215.   * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5216.   *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5217.   *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5218.   *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5219.   *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5220.   *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5221.   *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_IsEnabledClock\n

  5222.   *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_IsEnabledClock\n

  5223.   *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_IsEnabledClock\n

  5224.   *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock\n

  5225.   *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_IsEnabledClock\n

  5226.   *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5227.   *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5228.   *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_IsEnabledClock\n

  5229.   *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_IsEnabledClock\n

  5230.   *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_IsEnabledClock\n

  5231.   *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_IsEnabledClock\n

  5232.   *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_IsEnabledClock\n

  5233.   *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5234.   *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5235.   *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n

  5236.   *         APB1LENR     CECEN         LL_C2_APB1_GRP1_IsEnabledClock\n

  5237.   *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_IsEnabledClock\n

  5238.   *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_IsEnabledClock\n

  5239.   *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_IsEnabledClock

  5240.   * @param  Periphs This parameter can be a combination of the following values:

  5241.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  5242.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  5243.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  5244.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  5245.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  5246.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  5247.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  5248.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  5249.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  5250.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  5251.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  5252.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  5253.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  5254.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  5255.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  5256.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  5257.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  5258.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  5259.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  5260.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  5261.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  5262.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  5263.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  5264.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  5265.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  5266.   * @retval uint32_t

  5267. */

  5268. __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

  5269. {

  5270.   return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);

  5271. }

  5272. 

  5273. /**

  5274.   * @brief  Disable C2 APB1 peripherals clock.

  5275.   * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_DisableClock\n

  5276.   *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_DisableClock\n

  5277.   *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_DisableClock\n

  5278.   *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_DisableClock\n

  5279.   *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_DisableClock\n

  5280.   *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_DisableClock\n

  5281.   *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_DisableClock\n

  5282.   *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_DisableClock\n

  5283.   *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_DisableClock\n

  5284.   *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_DisableClock\n

  5285.   *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_DisableClock\n

  5286.   *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_DisableClock\n

  5287.   *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_DisableClock\n

  5288.   *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_DisableClock\n

  5289.   *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_DisableClock\n

  5290.   *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_DisableClock\n

  5291.   *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_DisableClock\n

  5292.   *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_DisableClock\n

  5293.   *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_DisableClock\n

  5294.   *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_DisableClock\n

  5295.   *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_DisableClock\n

  5296.   *         APB1LENR     CECEN         LL_C2_APB1_GRP1_DisableClock\n

  5297.   *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_DisableClock\n

  5298.   *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_DisableClock\n

  5299.   *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_DisableClock

  5300.   * @param  Periphs This parameter can be a combination of the following values:

  5301.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  5302.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  5303.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  5304.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  5305.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  5306.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  5307.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  5308.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  5309.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  5310.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  5311.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  5312.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  5313.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  5314.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  5315.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  5316.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  5317.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  5318.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  5319.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  5320.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  5321.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  5322.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  5323.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  5324.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  5325.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  5326.   * @retval None

  5327. */

  5328. __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)

  5329. {

  5330.   CLEAR_BIT(RCC_C2->APB1LENR, Periphs);

  5331. }

  5332. 

  5333. /**

  5334.   * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.

  5335.   * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5336.   *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5337.   *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5338.   *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5339.   *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5340.   *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5341.   *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

  5342.   *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

  5343.   *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

  5344.   *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n

  5345.   *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

  5346.   *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5347.   *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5348.   *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_EnableClockSleep\n

  5349.   *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n

  5350.   *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n

  5351.   *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

  5352.   *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

  5353.   *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5354.   *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5355.   *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

  5356.   *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_EnableClockSleep\n

  5357.   *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

  5358.   *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

  5359.   *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_EnableClockSleep

  5360.   * @param  Periphs This parameter can be a combination of the following values:

  5361.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  5362.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  5363.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  5364.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  5365.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  5366.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  5367.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  5368.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  5369.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  5370.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  5371.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  5372.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  5373.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  5374.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  5375.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  5376.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  5377.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  5378.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  5379.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  5380.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  5381.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  5382.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  5383.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  5384.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  5385.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  5386.   * @retval None

  5387. */

  5388. __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

  5389. {

  5390.   __IO uint32_t tmpreg;

  5391.   SET_BIT(RCC_C2->APB1LLPENR, Periphs);

  5392.   /* Delay after an RCC peripheral clock enabling */

  5393.   tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);

  5394.   (void)tmpreg;

  5395. }

  5396. 

  5397. /**

  5398.   * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.

  5399.   * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5400.   *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5401.   *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5402.   *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5403.   *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5404.   *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5405.   *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

  5406.   *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

  5407.   *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

  5408.   *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n

  5409.   *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

  5410.   *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5411.   *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5412.   *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_DisableClockSleep\n

  5413.   *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n

  5414.   *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n

  5415.   *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

  5416.   *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

  5417.   *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5418.   *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5419.   *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

  5420.   *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_DisableClockSleep\n

  5421.   *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

  5422.   *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

  5423.   *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_DisableClockSleep

  5424.   * @param  Periphs This parameter can be a combination of the following values:

  5425.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  5426.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

  5427.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

  5428.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

  5429.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

  5430.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

  5431.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

  5432.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

  5433.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

  5434.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  5435.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

  5436.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

  5437.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

  5438.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

  5439.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  5440.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

  5441.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

  5442.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

  5443.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  5444.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

  5445.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

  5446.   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

  5447.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

  5448.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

  5449.   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

  5450.   * @retval None

  5451. */

  5452. __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

  5453. {

  5454.   CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);

  5455. }

  5456. 

  5457. /**

  5458.   * @brief  Enable C2 APB1 peripherals clock.

  5459.   * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_EnableClock\n

  5460.   *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_EnableClock\n

  5461.   *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_EnableClock\n

  5462.   *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_EnableClock\n

  5463.   *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_EnableClock

  5464.   * @param  Periphs This parameter can be a combination of the following values:

  5465.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  5466.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  5467.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  5468.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  5469.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  5470.   * @retval None

  5471. */

  5472. __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)

  5473. {

  5474.   __IO uint32_t tmpreg;

  5475.   SET_BIT(RCC_C2->APB1HENR, Periphs);

  5476.   /* Delay after an RCC peripheral clock enabling */

  5477.   tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);

  5478.   (void)tmpreg;

  5479. }

  5480. 

  5481. /**

  5482.   * @brief  Check if C2 APB1 peripheral clock is enabled or not

  5483.   * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_IsEnabledClock\n

  5484.   *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_IsEnabledClock\n

  5485.   *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_IsEnabledClock\n

  5486.   *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_IsEnabledClock\n

  5487.   *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_IsEnabledClock

  5488.   * @param  Periphs This parameter can be a combination of the following values:

  5489.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  5490.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  5491.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  5492.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  5493.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  5494.   * @retval uint32_t

  5495. */

  5496. __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)

  5497. {

  5498.   return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);

  5499. }

  5500. 

  5501. /**

  5502.   * @brief  Disable C2 APB1 peripherals clock.

  5503.   * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_DisableClock\n

  5504.   *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_DisableClock\n

  5505.   *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_DisableClock\n

  5506.   *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_DisableClock\n

  5507.   *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_DisableClock

  5508.   * @param  Periphs This parameter can be a combination of the following values:

  5509.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  5510.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  5511.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  5512.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  5513.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  5514.   * @retval None

  5515. */

  5516. __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)

  5517. {

  5518.   CLEAR_BIT(RCC_C2->APB1HENR, Periphs);

  5519. }

  5520. 

  5521. /**

  5522.   * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.

  5523.   * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_EnableClockSleep\n

  5524.   *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_EnableClockSleep\n

  5525.   *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n

  5526.   *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n

  5527.   *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_EnableClockSleep

  5528.   * @param  Periphs This parameter can be a combination of the following values:

  5529.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  5530.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  5531.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  5532.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  5533.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  5534.   * @retval None

  5535. */

  5536. __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)

  5537. {

  5538.   __IO uint32_t tmpreg;

  5539.   SET_BIT(RCC_C2->APB1HLPENR, Periphs);

  5540.   /* Delay after an RCC peripheral clock enabling */

  5541.   tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);

  5542.   (void)tmpreg;

  5543. }

  5544. 

  5545. /**

  5546.   * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.

  5547.   * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_DisableClockSleep\n

  5548.   *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_DisableClockSleep\n

  5549.   *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n

  5550.   *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n

  5551.   *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_DisableClockSleep

  5552.   * @param  Periphs This parameter can be a combination of the following values:

  5553.   *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

  5554.   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

  5555.   *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

  5556.   *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

  5557.   *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

  5558.   * @retval None

  5559. */

  5560. __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)

  5561. {

  5562.   CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);

  5563. }

  5564. 

  5565. /**

  5566.   * @}

  5567.   */

  5568. 

  5569. /** @defgroup BUS_LL_EF_APB2 APB2

  5570.   * @{

  5571.   */

  5572. 

  5573. /**

  5574.   * @brief  Enable C2 APB2 peripherals clock.

  5575.   * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_EnableClock\n

  5576.   *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_EnableClock\n

  5577.   *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_EnableClock\n

  5578.   *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_EnableClock\n

  5579.   *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_EnableClock\n

  5580.   *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_EnableClock\n

  5581.   *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_EnableClock\n

  5582.   *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_EnableClock\n

  5583.   *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_EnableClock\n

  5584.   *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_EnableClock\n

  5585.   *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_EnableClock\n

  5586.   *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_EnableClock\n

  5587.   *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_EnableClock\n

  5588.   *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_EnableClock\n

  5589.   *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_EnableClock

  5590.   * @param  Periphs This parameter can be a combination of the following values:

  5591.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  5592.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  5593.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  5594.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  5595.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  5596.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  5597.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  5598.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  5599.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  5600.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  5601.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  5602.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  5603.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  5604.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  5605.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  5606.   * @retval None

  5607. */

  5608. __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)

  5609. {

  5610.   __IO uint32_t tmpreg;

  5611.   SET_BIT(RCC_C2->APB2ENR, Periphs);

  5612.   /* Delay after an RCC peripheral clock enabling */

  5613.   tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);

  5614.   (void)tmpreg;

  5615. }

  5616. 

  5617. /**

  5618.   * @brief  Check if C2 APB2 peripheral clock is enabled or not

  5619.   * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  5620.   *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  5621.   *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n

  5622.   *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_IsEnabledClock\n

  5623.   *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  5624.   *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  5625.   *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_IsEnabledClock\n

  5626.   *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n

  5627.   *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n

  5628.   *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  5629.   *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  5630.   *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  5631.   *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_IsEnabledClock\n

  5632.   *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_IsEnabledClock\n

  5633.   *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_IsEnabledClock

  5634.   * @param  Periphs This parameter can be a combination of the following values:

  5635.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  5636.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  5637.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  5638.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  5639.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  5640.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  5641.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  5642.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  5643.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  5644.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  5645.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  5646.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  5647.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  5648.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  5649.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  5650.   * @retval uint32_t

  5651. */

  5652. __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

  5653. {

  5654.   return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);

  5655. }

  5656. 

  5657. /**

  5658.   * @brief  Disable C2 APB2 peripherals clock.

  5659.   * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_DisableClock\n

  5660.   *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_DisableClock\n

  5661.   *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_DisableClock\n

  5662.   *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_DisableClock\n

  5663.   *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_DisableClock\n

  5664.   *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_DisableClock\n

  5665.   *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_DisableClock\n

  5666.   *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_DisableClock\n

  5667.   *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_DisableClock\n

  5668.   *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_DisableClock\n

  5669.   *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_DisableClock\n

  5670.   *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_DisableClock\n

  5671.   *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_DisableClock\n

  5672.   *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_DisableClock\n

  5673.   *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_DisableClock

  5674.   * @param  Periphs This parameter can be a combination of the following values:

  5675.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  5676.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  5677.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  5678.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  5679.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  5680.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  5681.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  5682.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  5683.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  5684.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  5685.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  5686.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  5687.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  5688.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  5689.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  5690.   * @retval None

  5691. */

  5692. __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)

  5693. {

  5694.   CLEAR_BIT(RCC_C2->APB2ENR, Periphs);

  5695. }

  5696. 

  5697. /**

  5698.   * @brief  Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.

  5699.   * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  5700.   *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  5701.   *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n

  5702.   *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n

  5703.   *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  5704.   *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  5705.   *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n

  5706.   *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n

  5707.   *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n

  5708.   *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  5709.   *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  5710.   *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  5711.   *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

  5712.   *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n

  5713.   *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_EnableClockSleep

  5714.   * @param  Periphs This parameter can be a combination of the following values:

  5715.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  5716.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  5717.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  5718.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  5719.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  5720.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  5721.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  5722.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  5723.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  5724.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  5725.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  5726.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  5727.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  5728.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  5729.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  5730.   * @retval None

  5731. */

  5732. __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

  5733. {

  5734.   __IO uint32_t tmpreg;

  5735.   SET_BIT(RCC_C2->APB2LPENR, Periphs);

  5736.   /* Delay after an RCC peripheral clock enabling */

  5737.   tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);

  5738.   (void)tmpreg;

  5739. }

  5740. 

  5741. /**

  5742.   * @brief  Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.

  5743.   * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  5744.   *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  5745.   *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n

  5746.   *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n

  5747.   *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  5748.   *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  5749.   *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n

  5750.   *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n

  5751.   *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n

  5752.   *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  5753.   *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  5754.   *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  5755.   *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

  5756.   *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n

  5757.   *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_DisableClockSleep

  5758.   * @param  Periphs This parameter can be a combination of the following values:

  5759.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

  5760.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

  5761.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

  5762.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

  5763.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  5764.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

  5765.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

  5766.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

  5767.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

  5768.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

  5769.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

  5770.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

  5771.   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

  5772.   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

  5773.   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

  5774.   * @retval None

  5775. */

  5776. __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

  5777. {

  5778.   CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);

  5779. }

  5780. 

  5781. /**

  5782.   * @}

  5783.   */

  5784. 

  5785. /** @defgroup BUS_LL_EF_APB4 APB4

  5786.   * @{

  5787.   */

  5788. 

  5789. /**

  5790.   * @brief  Enable C2 APB4 peripherals clock.

  5791.   * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_EnableClock\n

  5792.   *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_EnableClock\n

  5793.   *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_EnableClock\n

  5794.   *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_EnableClock\n

  5795.   *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_EnableClock\n

  5796.   *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_EnableClock\n

  5797.   *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_EnableClock\n

  5798.   *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_EnableClock\n

  5799.   *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_EnableClock\n

  5800.   *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_EnableClock\n

  5801.   *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_EnableClock\n

  5802.   *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_EnableClock

  5803.   * @param  Periphs This parameter can be a combination of the following values:

  5804.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  5805.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  5806.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  5807.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  5808.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  5809.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  5810.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  5811.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  5812.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  5813.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  5814.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  5815.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  5816.   * @retval None

  5817. */

  5818. __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)

  5819. {

  5820.   __IO uint32_t tmpreg;

  5821.   SET_BIT(RCC_C2->APB4ENR, Periphs);

  5822.   /* Delay after an RCC peripheral clock enabling */

  5823.   tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);

  5824.   (void)tmpreg;

  5825. }

  5826. 

  5827. /**

  5828.   * @brief  Check if C2 APB4 peripheral clock is enabled or not

  5829.   * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_IsEnabledClock\n

  5830.   *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_IsEnabledClock\n

  5831.   *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_IsEnabledClock\n

  5832.   *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_IsEnabledClock\n

  5833.   *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_IsEnabledClock\n

  5834.   *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_IsEnabledClock\n

  5835.   *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_IsEnabledClock\n

  5836.   *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_IsEnabledClock\n

  5837.   *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_IsEnabledClock\n

  5838.   *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_IsEnabledClock\n

  5839.   *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_IsEnabledClock\n

  5840.   *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_IsEnabledClock

  5841.   * @param  Periphs This parameter can be a combination of the following values:

  5842.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  5843.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  5844.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  5845.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  5846.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  5847.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  5848.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  5849.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  5850.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  5851.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  5852.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  5853.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  5854.   * @retval uint32_t

  5855. */

  5856. __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)

  5857. {

  5858.   return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);

  5859. }

  5860. 

  5861. /**

  5862.   * @brief  Disable C2 APB4 peripherals clock.

  5863.   * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_DisableClock\n

  5864.   *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_DisableClock\n

  5865.   *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_DisableClock\n

  5866.   *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_DisableClock\n

  5867.   *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_DisableClock\n

  5868.   *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_DisableClock\n

  5869.   *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_DisableClock\n

  5870.   *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_DisableClock\n

  5871.   *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_DisableClock\n

  5872.   *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_DisableClock\n

  5873.   *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_DisableClock\n

  5874.   *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_DisableClock

  5875.   * @param  Periphs This parameter can be a combination of the following values:

  5876.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  5877.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  5878.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  5879.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  5880.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  5881.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  5882.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  5883.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  5884.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  5885.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  5886.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  5887.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  5888.   * @retval None

  5889. */

  5890. __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)

  5891. {

  5892.   CLEAR_BIT(RCC_C2->APB4ENR, Periphs);

  5893. }

  5894. 

  5895. /**

  5896.   * @brief  Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.

  5897.   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

  5898.   *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_EnableClockSleep\n

  5899.   *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n

  5900.   *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n

  5901.   *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

  5902.   *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

  5903.   *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

  5904.   *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

  5905.   *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

  5906.   *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_EnableClockSleep\n

  5907.   *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

  5908.   *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_EnableClockSleep

  5909.   * @param  Periphs This parameter can be a combination of the following values:

  5910.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  5911.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  5912.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  5913.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  5914.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  5915.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  5916.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  5917.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  5918.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  5919.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  5920.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  5921.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  5922.   * @retval None

  5923. */

  5924. __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)

  5925. {

  5926.   __IO uint32_t tmpreg;

  5927.   SET_BIT(RCC_C2->APB4LPENR, Periphs);

  5928.   /* Delay after an RCC peripheral clock enabling */

  5929.   tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);

  5930.   (void)tmpreg;

  5931. }

  5932. 

  5933. /**

  5934.   * @brief  Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.

  5935.   * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

  5936.   *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_DisableClockSleep\n

  5937.   *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n

  5938.   *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n

  5939.   *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

  5940.   *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

  5941.   *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

  5942.   *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

  5943.   *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

  5944.   *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_DisableClockSleep\n

  5945.   *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

  5946.   *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_DisableClockSleep

  5947.   * @param  Periphs This parameter can be a combination of the following values:

  5948.   *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

  5949.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

  5950.   *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

  5951.   *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

  5952.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

  5953.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

  5954.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

  5955.   *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

  5956.   *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

  5957.   *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

  5958.   *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

  5959.   *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

  5960.   * @retval None

  5961. */

  5962. __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)

  5963. {

  5964.   CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);

  5965. }

  5966. 

  5967. /**

  5968.   * @}

  5969.   */

  5970. 

  5971. #endif /*DUAL_CORE*/

  5972. 

  5973. /**

  5974.   * @}

  5975.   */

  5976. 

  5977. /**

  5978.   * @}

  5979.   */

  5980. 

  5981. #endif /* defined(RCC) */

  5982. 

  5983. /**

  5984.   * @}

  5985.   */

  5986. 

  5987. #ifdef __cplusplus

  5988. }

  5989. #endif

  5990. 

  5991. #endif /* STM32H7xx_LL_BUS_H */

  5992. 

  5993. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/