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  1. /**
  2. ******************************************************************************
  3. * @file stm32f7xx_hal_flash_ex.c
  4. * @author MCD Application Team
  5. * @version V1.0.1
  6. * @date 25-June-2015
  7. * @brief Extended FLASH HAL module driver.
  8. * This file provides firmware functions to manage the following
  9. * functionalities of the FLASH extension peripheral:
  10. * + Extended programming operations functions
  11. *
  12. @verbatim
  13. ==============================================================================
  14. ##### Flash Extension features #####
  15. ==============================================================================
  16. [..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and
  17. devices contains the following additional features
  18. (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
  19. capability (RWW)
  20. (+) Dual bank memory organization
  21. (+) PCROP protection for all banks
  22. ##### How to use this driver #####
  23. ==============================================================================
  24. [..] This driver provides functions to configure and program the FLASH memory
  25. of all STM32F7xx devices. It includes
  26. (#) FLASH Memory Erase functions:
  27. (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
  28. HAL_FLASH_Lock() functions
  29. (++) Erase function: Erase sector, erase all sectors
  30. (++) There are two modes of erase :
  31. (+++) Polling Mode using HAL_FLASHEx_Erase()
  32. (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
  33. (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
  34. (++) Set/Reset the write protection
  35. (++) Set the Read protection Level
  36. (++) Set the BOR level
  37. (++) Program the user Option Bytes
  38. (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
  39. (++) Extended space (bank 2) erase function
  40. (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
  41. (++) Dual Boot activation
  42. (++) Write protection configuration for bank 2
  43. (++) PCROP protection configuration and control for both banks
  44. @endverbatim
  45. ******************************************************************************
  46. * @attention
  47. *
  48. * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  49. *
  50. * Redistribution and use in source and binary forms, with or without modification,
  51. * are permitted provided that the following conditions are met:
  52. * 1. Redistributions of source code must retain the above copyright notice,
  53. * this list of conditions and the following disclaimer.
  54. * 2. Redistributions in binary form must reproduce the above copyright notice,
  55. * this list of conditions and the following disclaimer in the documentation
  56. * and/or other materials provided with the distribution.
  57. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  58. * may be used to endorse or promote products derived from this software
  59. * without specific prior written permission.
  60. *
  61. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  62. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  63. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  64. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  65. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  66. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  67. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  68. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  69. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  70. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  71. *
  72. ******************************************************************************
  73. */
  74. /* Includes ------------------------------------------------------------------*/
  75. #include "stm32f7xx_hal.h"
  76. /** @addtogroup STM32F7xx_HAL_Driver
  77. * @{
  78. */
  79. /** @defgroup FLASHEx FLASHEx
  80. * @brief FLASH HAL Extension module driver
  81. * @{
  82. */
  83. #ifdef HAL_FLASH_MODULE_ENABLED
  84. /* Private typedef -----------------------------------------------------------*/
  85. /* Private define ------------------------------------------------------------*/
  86. /** @addtogroup FLASHEx_Private_Constants
  87. * @{
  88. */
  89. #define SECTOR_MASK ((uint32_t)0xFFFFFF07)
  90. #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
  91. /**
  92. * @}
  93. */
  94. /* Private macro -------------------------------------------------------------*/
  95. /* Private variables ---------------------------------------------------------*/
  96. /** @addtogroup FLASHEx_Private_Variables
  97. * @{
  98. */
  99. extern FLASH_ProcessTypeDef pFlash;
  100. /**
  101. * @}
  102. */
  103. /* Private function prototypes -----------------------------------------------*/
  104. /** @addtogroup FLASHEx_Private_Functions
  105. * @{
  106. */
  107. /* Option bytes control */
  108. static void FLASH_MassErase(uint8_t VoltageRange);
  109. static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
  110. static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
  111. static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level);
  112. static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
  113. static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
  114. static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
  115. static uint32_t FLASH_OB_GetUser(void);
  116. static uint32_t FLASH_OB_GetWRP(void);
  117. static uint8_t FLASH_OB_GetRDP(void);
  118. static uint32_t FLASH_OB_GetBOR(void);
  119. static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
  120. extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
  121. /**
  122. * @}
  123. */
  124. /* Exported functions --------------------------------------------------------*/
  125. /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
  126. * @{
  127. */
  128. /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
  129. * @brief Extended IO operation functions
  130. *
  131. @verbatim
  132. ===============================================================================
  133. ##### Extended programming operation functions #####
  134. ===============================================================================
  135. [..]
  136. This subsection provides a set of functions allowing to manage the Extension FLASH
  137. programming operations Operations.
  138. @endverbatim
  139. * @{
  140. */
  141. /**
  142. * @brief Perform a mass erase or erase the specified FLASH memory sectors
  143. * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
  144. * contains the configuration information for the erasing.
  145. *
  146. * @param[out] SectorError: pointer to variable that
  147. * contains the configuration information on faulty sector in case of error
  148. * (0xFFFFFFFF means that all the sectors have been correctly erased)
  149. *
  150. * @retval HAL Status
  151. */
  152. HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
  153. {
  154. HAL_StatusTypeDef status = HAL_ERROR;
  155. uint32_t index = 0;
  156. /* Process Locked */
  157. __HAL_LOCK(&pFlash);
  158. /* Check the parameters */
  159. assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
  160. /* Wait for last operation to be completed */
  161. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  162. if(status == HAL_OK)
  163. {
  164. /*Initialization of SectorError variable*/
  165. *SectorError = 0xFFFFFFFF;
  166. if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
  167. {
  168. /*Mass erase to be done*/
  169. FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
  170. /* Wait for last operation to be completed */
  171. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  172. /* if the erase operation is completed, disable the MER Bit */
  173. FLASH->CR &= (~FLASH_MER_BIT);
  174. }
  175. else
  176. {
  177. /* Check the parameters */
  178. assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
  179. /* Erase by sector by sector to be done*/
  180. for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
  181. {
  182. FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
  183. /* Wait for last operation to be completed */
  184. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  185. /* If the erase operation is completed, disable the SER Bit */
  186. FLASH->CR &= (~FLASH_CR_SER);
  187. FLASH->CR &= SECTOR_MASK;
  188. if(status != HAL_OK)
  189. {
  190. /* In case of error, stop erase procedure and return the faulty sector*/
  191. *SectorError = index;
  192. break;
  193. }
  194. }
  195. }
  196. }
  197. /* Process Unlocked */
  198. __HAL_UNLOCK(&pFlash);
  199. return status;
  200. }
  201. /**
  202. * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
  203. * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
  204. * contains the configuration information for the erasing.
  205. *
  206. * @retval HAL Status
  207. */
  208. HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
  209. {
  210. HAL_StatusTypeDef status = HAL_OK;
  211. /* Process Locked */
  212. __HAL_LOCK(&pFlash);
  213. /* Check the parameters */
  214. assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
  215. /* Enable End of FLASH Operation interrupt */
  216. __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
  217. /* Enable Error source interrupt */
  218. __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
  219. /* Clear pending flags (if any) */
  220. __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
  221. FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
  222. if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
  223. {
  224. /*Mass erase to be done*/
  225. pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
  226. FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
  227. }
  228. else
  229. {
  230. /* Erase by sector to be done*/
  231. /* Check the parameters */
  232. assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
  233. pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
  234. pFlash.NbSectorsToErase = pEraseInit->NbSectors;
  235. pFlash.Sector = pEraseInit->Sector;
  236. pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
  237. /*Erase 1st sector and wait for IT*/
  238. FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
  239. }
  240. return status;
  241. }
  242. /**
  243. * @brief Program option bytes
  244. * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
  245. * contains the configuration information for the programming.
  246. *
  247. * @retval HAL Status
  248. */
  249. HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
  250. {
  251. HAL_StatusTypeDef status = HAL_ERROR;
  252. /* Process Locked */
  253. __HAL_LOCK(&pFlash);
  254. /* Check the parameters */
  255. assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
  256. /* Write protection configuration */
  257. if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
  258. {
  259. assert_param(IS_WRPSTATE(pOBInit->WRPState));
  260. if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
  261. {
  262. /*Enable of Write protection on the selected Sector*/
  263. status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
  264. }
  265. else
  266. {
  267. /*Disable of Write protection on the selected Sector*/
  268. status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
  269. }
  270. }
  271. /* Read protection configuration */
  272. if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
  273. {
  274. status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
  275. }
  276. /* USER configuration */
  277. if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
  278. {
  279. status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
  280. pOBInit->USERConfig & OB_IWDG_SW,
  281. pOBInit->USERConfig & OB_STOP_NO_RST,
  282. pOBInit->USERConfig & OB_STDBY_NO_RST,
  283. pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
  284. pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
  285. }
  286. /* BOR Level configuration */
  287. if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
  288. {
  289. status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
  290. }
  291. /* Boot 0 Address configuration */
  292. if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
  293. {
  294. status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
  295. }
  296. /* Boot 1 Address configuration */
  297. if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
  298. {
  299. status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
  300. }
  301. /* Process Unlocked */
  302. __HAL_UNLOCK(&pFlash);
  303. return status;
  304. }
  305. /**
  306. * @brief Get the Option byte configuration
  307. * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
  308. * contains the configuration information for the programming.
  309. *
  310. * @retval None
  311. */
  312. void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
  313. {
  314. pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
  315. OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
  316. /*Get WRP*/
  317. pOBInit->WRPSector = FLASH_OB_GetWRP();
  318. /*Get RDP Level*/
  319. pOBInit->RDPLevel = FLASH_OB_GetRDP();
  320. /*Get USER*/
  321. pOBInit->USERConfig = FLASH_OB_GetUser();
  322. /*Get BOR Level*/
  323. pOBInit->BORLevel = FLASH_OB_GetBOR();
  324. /*Get Boot Address when Boot pin = 0 */
  325. pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
  326. /*Get Boot Address when Boot pin = 1 */
  327. pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
  328. }
  329. /**
  330. * @}
  331. */
  332. /**
  333. * @brief Full erase of FLASH memory sectors
  334. * @param VoltageRange: The device voltage range which defines the erase parallelism.
  335. * This parameter can be one of the following values:
  336. * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
  337. * the operation will be done by byte (8-bit)
  338. * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
  339. * the operation will be done by half word (16-bit)
  340. * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
  341. * the operation will be done by word (32-bit)
  342. * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
  343. * the operation will be done by double word (64-bit)
  344. *
  345. * @retval HAL Status
  346. */
  347. static void FLASH_MassErase(uint8_t VoltageRange)
  348. {
  349. uint32_t tmp_psize = 0;
  350. /* Check the parameters */
  351. assert_param(IS_VOLTAGERANGE(VoltageRange));
  352. /* if the previous operation is completed, proceed to erase all sectors */
  353. FLASH->CR &= CR_PSIZE_MASK;
  354. FLASH->CR |= tmp_psize;
  355. FLASH->CR |= FLASH_CR_MER;
  356. FLASH->CR |= FLASH_CR_STRT;
  357. /* Data synchronous Barrier (DSB) Just after the write operation
  358. This will force the CPU to respect the sequence of instruction (no optimization).*/
  359. __DSB();
  360. }
  361. /**
  362. * @brief Erase the specified FLASH memory sector
  363. * @param Sector: FLASH sector to erase
  364. * The value of this parameter depend on device used within the same series
  365. * @param VoltageRange: The device voltage range which defines the erase parallelism.
  366. * This parameter can be one of the following values:
  367. * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
  368. * the operation will be done by byte (8-bit)
  369. * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
  370. * the operation will be done by half word (16-bit)
  371. * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
  372. * the operation will be done by word (32-bit)
  373. * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
  374. * the operation will be done by double word (64-bit)
  375. *
  376. * @retval None
  377. */
  378. void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
  379. {
  380. uint32_t tmp_psize = 0;
  381. /* Check the parameters */
  382. assert_param(IS_FLASH_SECTOR(Sector));
  383. assert_param(IS_VOLTAGERANGE(VoltageRange));
  384. if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
  385. {
  386. tmp_psize = FLASH_PSIZE_BYTE;
  387. }
  388. else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
  389. {
  390. tmp_psize = FLASH_PSIZE_HALF_WORD;
  391. }
  392. else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
  393. {
  394. tmp_psize = FLASH_PSIZE_WORD;
  395. }
  396. else
  397. {
  398. tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
  399. }
  400. /* If the previous operation is completed, proceed to erase the sector */
  401. FLASH->CR &= CR_PSIZE_MASK;
  402. FLASH->CR |= tmp_psize;
  403. FLASH->CR &= SECTOR_MASK;
  404. FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
  405. FLASH->CR |= FLASH_CR_STRT;
  406. /* Data synchronous Barrier (DSB) Just after the write operation
  407. This will force the CPU to respect the sequence of instruction (no optimization).*/
  408. __DSB();
  409. }
  410. /**
  411. * @brief Enable the write protection of the desired bank1 or bank 2 sectors
  412. *
  413. * @note When the memory read protection level is selected (RDP level = 1),
  414. * it is not possible to program or erase the flash sector i if CortexM4
  415. * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
  416. * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
  417. *
  418. * @param WRPSector: specifies the sector(s) to be write protected.
  419. * This parameter can be one of the following values:
  420. * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
  421. * @arg OB_WRP_SECTOR_All
  422. *
  423. * @retval HAL FLASH State
  424. */
  425. static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
  426. {
  427. HAL_StatusTypeDef status = HAL_OK;
  428. /* Check the parameters */
  429. assert_param(IS_OB_WRP_SECTOR(WRPSector));
  430. /* Wait for last operation to be completed */
  431. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  432. if(status == HAL_OK)
  433. {
  434. /*Write protection enabled on sectors */
  435. FLASH->OPTCR &= (~WRPSector);
  436. }
  437. return status;
  438. }
  439. /**
  440. * @brief Disable the write protection of the desired bank1 or bank 2 sectors
  441. *
  442. * @note When the memory read protection level is selected (RDP level = 1),
  443. * it is not possible to program or erase the flash sector i if CortexM4
  444. * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
  445. *
  446. * @param WRPSector: specifies the sector(s) to be write protected.
  447. * This parameter can be one of the following values:
  448. * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
  449. * @arg OB_WRP_Sector_All
  450. *
  451. *
  452. * @retval HAL Status
  453. */
  454. static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
  455. {
  456. HAL_StatusTypeDef status = HAL_OK;
  457. /* Check the parameters */
  458. assert_param(IS_OB_WRP_SECTOR(WRPSector));
  459. /* Wait for last operation to be completed */
  460. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  461. if(status == HAL_OK)
  462. {
  463. /* Write protection disabled on sectors */
  464. FLASH->OPTCR |= (WRPSector);
  465. }
  466. return status;
  467. }
  468. /**
  469. * @brief Set the read protection level.
  470. * @param Level: specifies the read protection level.
  471. * This parameter can be one of the following values:
  472. * @arg OB_RDP_LEVEL_0: No protection
  473. * @arg OB_RDP_LEVEL_1: Read protection of the memory
  474. * @arg OB_RDP_LEVEL_2: Full chip protection
  475. *
  476. * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
  477. *
  478. * @retval HAL Status
  479. */
  480. static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
  481. {
  482. HAL_StatusTypeDef status = HAL_OK;
  483. /* Check the parameters */
  484. assert_param(IS_OB_RDP_LEVEL(Level));
  485. /* Wait for last operation to be completed */
  486. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  487. if(status == HAL_OK)
  488. {
  489. MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_RDP, Level);
  490. }
  491. return status;
  492. }
  493. /**
  494. * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
  495. * @param Wwdg: Selects the IWDG mode
  496. * This parameter can be one of the following values:
  497. * @arg OB_WWDG_SW: Software WWDG selected
  498. * @arg OB_WWDG_HW: Hardware WWDG selected
  499. * @param Iwdg: Selects the WWDG mode
  500. * This parameter can be one of the following values:
  501. * @arg OB_IWDG_SW: Software IWDG selected
  502. * @arg OB_IWDG_HW: Hardware IWDG selected
  503. * @param Stop: Reset event when entering STOP mode.
  504. * This parameter can be one of the following values:
  505. * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
  506. * @arg OB_STOP_RST: Reset generated when entering in STOP
  507. * @param Stdby: Reset event when entering Standby mode.
  508. * This parameter can be one of the following values:
  509. * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
  510. * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
  511. * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.
  512. * This parameter can be one of the following values:
  513. * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
  514. * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
  515. * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.
  516. * This parameter can be one of the following values:
  517. * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
  518. * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
  519. * @retval HAL Status
  520. */
  521. static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby )
  522. {
  523. uint32_t useroptionmask = 0x00;
  524. uint32_t useroptionvalue = 0x00;
  525. HAL_StatusTypeDef status = HAL_OK;
  526. /* Check the parameters */
  527. assert_param(IS_OB_WWDG_SOURCE(Wwdg));
  528. assert_param(IS_OB_IWDG_SOURCE(Iwdg));
  529. assert_param(IS_OB_STOP_SOURCE(Stop));
  530. assert_param(IS_OB_STDBY_SOURCE(Stdby));
  531. assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
  532. assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
  533. /* Wait for last operation to be completed */
  534. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  535. if(status == HAL_OK)
  536. {
  537. useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
  538. FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
  539. useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
  540. /* Update User Option Byte */
  541. MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
  542. }
  543. return status;
  544. }
  545. /**
  546. * @brief Set the BOR Level.
  547. * @param Level: specifies the Option Bytes BOR Reset Level.
  548. * This parameter can be one of the following values:
  549. * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
  550. * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
  551. * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
  552. * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
  553. * @retval HAL Status
  554. */
  555. static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
  556. {
  557. /* Check the parameters */
  558. assert_param(IS_OB_BOR_LEVEL(Level));
  559. /* Set the BOR Level */
  560. MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
  561. return HAL_OK;
  562. }
  563. /**
  564. * @brief Configure Boot base address.
  565. *
  566. * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
  567. * This parameter can be one of the following values:
  568. * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
  569. * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
  570. * @param Address: specifies Boot base address
  571. * This parameter can be one of the following values:
  572. * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
  573. * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
  574. * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
  575. * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
  576. * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
  577. * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
  578. * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
  579. *
  580. * @retval HAL Status
  581. */
  582. static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
  583. {
  584. HAL_StatusTypeDef status = HAL_OK;
  585. /* Check the parameters */
  586. assert_param(IS_OB_BOOT_ADDRESS(Address));
  587. /* Wait for last operation to be completed */
  588. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  589. if(status == HAL_OK)
  590. {
  591. if(BootOption == OPTIONBYTE_BOOTADDR_0)
  592. {
  593. MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
  594. }
  595. else
  596. {
  597. MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
  598. }
  599. }
  600. return status;
  601. }
  602. /**
  603. * @brief Return the FLASH User Option Byte value.
  604. * @retval uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
  605. * and RST_STDBY(Bit2).
  606. */
  607. static uint32_t FLASH_OB_GetUser(void)
  608. {
  609. /* Return the User Option Byte */
  610. return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
  611. }
  612. /**
  613. * @brief Return the FLASH Write Protection Option Bytes value.
  614. * @retval uint32_t FLASH Write Protection Option Bytes value
  615. */
  616. static uint32_t FLASH_OB_GetWRP(void)
  617. {
  618. /* Return the FLASH write protection Register value */
  619. return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
  620. }
  621. /**
  622. * @brief Returns the FLASH Read Protection level.
  623. * @retval FlagStatus FLASH ReadOut Protection Status:
  624. * This parameter can be one of the following values:
  625. * @arg OB_RDP_LEVEL_0: No protection
  626. * @arg OB_RDP_LEVEL_1: Read protection of the memory
  627. * @arg OB_RDP_LEVEL_2: Full chip protection
  628. */
  629. static uint8_t FLASH_OB_GetRDP(void)
  630. {
  631. uint8_t readstatus = OB_RDP_LEVEL_0;
  632. if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_0)
  633. {
  634. readstatus = OB_RDP_LEVEL_0;
  635. }
  636. else if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_2)
  637. {
  638. readstatus = OB_RDP_LEVEL_2;
  639. }
  640. else
  641. {
  642. readstatus = OB_RDP_LEVEL_1;
  643. }
  644. return readstatus;
  645. }
  646. /**
  647. * @brief Returns the FLASH BOR level.
  648. * @retval uint32_t The FLASH BOR level:
  649. * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
  650. * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
  651. * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
  652. * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
  653. */
  654. static uint32_t FLASH_OB_GetBOR(void)
  655. {
  656. /* Return the FLASH BOR level */
  657. return ((uint32_t)(FLASH->OPTCR & 0x0C));
  658. }
  659. /**
  660. * @brief Configure Boot base address.
  661. *
  662. * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
  663. * This parameter can be one of the following values:
  664. * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
  665. * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
  666. *
  667. * @retval uint32_t Boot Base Address:
  668. * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
  669. * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
  670. * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
  671. * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
  672. * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
  673. * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
  674. * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
  675. */
  676. static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
  677. {
  678. uint32_t Address = 0;
  679. /* Return the Boot base Address */
  680. if(BootOption == OPTIONBYTE_BOOTADDR_0)
  681. {
  682. Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
  683. }
  684. else
  685. {
  686. Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
  687. }
  688. return Address;
  689. }
  690. /**
  691. * @}
  692. */
  693. #endif /* HAL_FLASH_MODULE_ENABLED */
  694. /**
  695. * @}
  696. */
  697. /**
  698. * @}
  699. */
  700. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/