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stm32lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32h7xx_ll_adc.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of ADC LL module.

  6.   ******************************************************************************

  7.   * @attention

  8.   *

  9.   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

  10.   * All rights reserved.</center></h2>

  11.   *

  12.   * This software component is licensed by ST under BSD 3-Clause license,

  13.   * the "License"; You may not use this file except in compliance with the

  14.   * License. You may obtain a copy of the License at:

  15.   *                        opensource.org/licenses/BSD-3-Clause

  16.   *

  17.   ******************************************************************************

  18.   */

  19. 

  20. /* Define to prevent recursive inclusion -------------------------------------*/

  21. #ifndef STM32H7xx_LL_ADC_H

  22. #define STM32H7xx_LL_ADC_H

  23. 

  24. #ifdef __cplusplus

  25. extern "C" {

  26. #endif

  27. 

  28. /* Includes ------------------------------------------------------------------*/

  29. #include "stm32h7xx.h"

  30. 

  31. /** @addtogroup STM32H7xx_LL_Driver

  32.   * @{

  33.   */

  34. 

  35. #if defined (ADC1) || defined (ADC2) || defined (ADC3)

  36. 

  37. /** @defgroup ADC_LL ADC

  38.   * @{

  39.   */

  40. 

  41. /* Private types -------------------------------------------------------------*/

  42. /* Private variables ---------------------------------------------------------*/

  43. 

  44. /* Private constants ---------------------------------------------------------*/

  45. /** @defgroup ADC_LL_Private_Constants ADC Private Constants

  46.   * @{

  47.   */

  48. 

  49. /* Internal mask for ADC calibration:                                         */

  50. /* Internal register offset for ADC calibration factors configuration */

  51. 

  52. /* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ...   */

  53. /* the relevant bits for:                                                     */

  54. /* (concatenation of multiple bits used in different registers)               */

  55. /* - ADC calibration configuration: configuration before calibration start    */

  56. /* - ADC calibration factors: register offset                                 */

  57. #define ADC_CALIB_FACTOR_OFFSET_REGOFFSET    (0x00000000UL) /* Register CALFACT defined as reference register */

  58. #define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */

  59. #define ADC_CALIB_FACTOR_REGOFFSET_MASK      (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)

  60. #define ADC_CALIB_MODE_MASK                  (ADC_CR_ADCALLIN)

  61. #define ADC_CALIB_MODE_BINARY_MASK           (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */

  62. 

  63. 

  64. /* Internal mask for ADC group regular sequencer:                             */

  65. /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */

  66. /* - sequencer register offset                                                */

  67. /* - sequencer rank bits position into the selected register                  */

  68. 

  69. /* Internal register offset for ADC group regular sequencer configuration */

  70. /* (offset placed into a spare area of literal definition) */

  71. #define ADC_SQR1_REGOFFSET                 (0x00000000UL)

  72. #define ADC_SQR2_REGOFFSET                 (0x00000100UL)

  73. #define ADC_SQR3_REGOFFSET                 (0x00000200UL)

  74. #define ADC_SQR4_REGOFFSET                 (0x00000300UL)

  75. 

  76. #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

  77. #define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */

  78. #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  79. 

  80. /* Definition of ADC group regular sequencer bits information to be inserted  */

  81. /* into ADC group regular sequencer ranks literals definition.                */

  82. #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */

  83. #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */

  84. #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */

  85. #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */

  86. #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */

  87. #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */

  88. #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */

  89. #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */

  90. #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */

  91. #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */

  92. #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */

  93. #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */

  94. #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */

  95. #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */

  96. #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */

  97. #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */

  98. 

  99. 

  100. 

  101. /* Internal mask for ADC group injected sequencer:                            */

  102. /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */

  103. /* - data register offset                                                     */

  104. /* - sequencer rank bits position into the selected register                  */

  105. 

  106. /* Internal register offset for ADC group injected data register */

  107. /* (offset placed into a spare area of literal definition) */

  108. #define ADC_JDR1_REGOFFSET                 (0x00000000UL)

  109. #define ADC_JDR2_REGOFFSET                 (0x00000100UL)

  110. #define ADC_JDR3_REGOFFSET                 (0x00000200UL)

  111. #define ADC_JDR4_REGOFFSET                 (0x00000300UL)

  112. 

  113. #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

  114. #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  115. #define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */

  116. 

  117. /* Definition of ADC group injected sequencer bits information to be inserted */

  118. /* into ADC group injected sequencer ranks literals definition.               */

  119. #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)

  120. #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)

  121. #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)

  122. #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)

  123. 

  124. 

  125. 

  126. /* Internal mask for ADC group regular trigger:                               */

  127. /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */

  128. /* - regular trigger source                                                   */

  129. /* - regular trigger edge                                                     */

  130. #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  131. 

  132. /* Mask containing trigger source masks for each of possible                  */

  133. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  134. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  135. #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \

  136.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \

  137.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \

  138.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )

  139. 

  140. /* Mask containing trigger edge masks for each of possible                    */

  141. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  142. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  143. #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \

  144.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \

  145.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \

  146.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )

  147. 

  148. /* Definition of ADC group regular trigger bits information.                  */

  149. #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */

  150. #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */

  151. 

  152. 

  153. 

  154. /* Internal mask for ADC group injected trigger:                              */

  155. /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */

  156. /* - injected trigger source                                                  */

  157. /* - injected trigger edge                                                    */

  158. #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  159. 

  160. /* Mask containing trigger source masks for each of possible                  */

  161. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  162. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  163. #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \

  164.                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \

  165.                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \

  166.                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )

  167. 

  168. /* Mask containing trigger edge masks for each of possible                    */

  169. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  170. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  171. #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \

  172.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \

  173.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \

  174.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

  175. 

  176. /* Definition of ADC group injected trigger bits information.                 */

  177. #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */

  178. #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */

  179. 

  180. 

  181. 

  182. 

  183. 

  184. 

  185. /* Internal mask for ADC channel:                                             */

  186. /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */

  187. /* - channel identifier defined by number                                     */

  188. /* - channel identifier defined by bitfield                                   */

  189. /* - channel differentiation between external channels (connected to          */

  190. /*   GPIO pins) and internal channels (connected to internal paths)           */

  191. /* - channel sampling time defined by SMPRx register offset                   */

  192. /*   and SMPx bits positions into SMPRx register                              */

  193. #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)

  194. #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)

  195. #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */

  196. #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  197. /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */

  198. #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

  199. 

  200. /* Channel differentiation between external and internal channels */

  201. #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */

  202. #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)

  203. 

  204. /* Internal register offset for ADC channel sampling time configuration */

  205. /* (offset placed into a spare area of literal definition) */

  206. #define ADC_SMPR1_REGOFFSET                (0x00000000UL)

  207. #define ADC_SMPR2_REGOFFSET                (0x02000000UL)

  208. #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

  209. #define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */

  210. 

  211. #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)

  212. #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */

  213. 

  214. /* Definition of channels ID number information to be inserted into           */

  215. /* channels literals definition.                                              */

  216. #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)

  217. #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)

  218. #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )

  219. #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  220. #define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )

  221. #define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)

  222. #define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )

  223. #define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  224. #define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )

  225. #define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)

  226. #define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )

  227. #define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  228. #define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )

  229. #define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)

  230. #define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )

  231. #define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  232. #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )

  233. #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)

  234. #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )

  235. #define ADC_CHANNEL_19_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  236. 

  237. /* Definition of channels ID bitfield information to be inserted into         */

  238. /* channels literals definition.                                              */

  239. #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)

  240. #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)

  241. #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)

  242. #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)

  243. #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)

  244. #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)

  245. #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)

  246. #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)

  247. #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)

  248. #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)

  249. #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)

  250. #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)

  251. #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)

  252. #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)

  253. #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)

  254. #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)

  255. #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)

  256. #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)

  257. #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)

  258. #define ADC_CHANNEL_19_BITFIELD            (ADC_AWD2CR_AWD2CH_19)

  259. 

  260. /* Definition of channels sampling time information to be inserted into       */

  261. /* channels literals definition.                                              */

  262. #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */

  263. #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */

  264. #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */

  265. #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */

  266. #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */

  267. #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */

  268. #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */

  269. #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */

  270. #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */

  271. #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */

  272. #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */

  273. #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */

  274. #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */

  275. #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */

  276. #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */

  277. #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */

  278. #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */

  279. #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */

  280. #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */

  281. #define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */

  282. 

  283. 

  284. /* Internal mask for ADC mode single or differential ended:                   */

  285. /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */

  286. /* the relevant bits for:                                                     */

  287. /* (concatenation of multiple bits used in different registers)               */

  288. /* - ADC calibration: calibration start, calibration factor get or set        */

  289. /* - ADC channels: set each ADC channel ending mode                           */

  290. #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)

  291. #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

  292. #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

  293. #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */

  294. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection of 1 bit to discriminate differential mode: mask of bit */

  295. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection of 1 bit to discriminate differential mode: position of bit */

  296. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */

  297. 

  298. /* Internal mask for ADC analog watchdog:                                     */

  299. /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */

  300. /* (concatenation of multiple bits used in different analog watchdogs,        */

  301. /* (feature of several watchdogs not available on all STM32 families)).       */

  302. /* - analog watchdog 1: monitored channel defined by number,                  */

  303. /*   selection of ADC group (ADC groups regular and-or injected).             */

  304. /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */

  305. /*   selection on groups.                                                     */

  306. 

  307. /* Internal register offset for ADC analog watchdog channel configuration */

  308. #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)

  309. #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)

  310. #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)

  311. 

  312. /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */

  313. /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */

  314. #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)

  315. #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)

  316. 

  317. #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

  318. 

  319. #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

  320. #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)

  321. #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

  322. 

  323. #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

  324. 

  325. /* Internal register offset for ADC analog watchdog threshold configuration */

  326. #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)

  327. #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)

  328. #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)

  329. #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

  330. #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */

  331. 

  332. /* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */

  333. /* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */

  334. #define ADC_AWD_TR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)

  335. #define ADC_AWD_TR12_REGOFFSETGAP_VAL      (0x00000022UL)

  336. 

  337. /* Legacy literals */

  338. #define LL_ADC_AWD1_TR                      LL_ADC_AWD1

  339. #define LL_ADC_AWD2_TR                      LL_ADC_AWD2

  340. #define LL_ADC_AWD3_TR                      LL_ADC_AWD3

  341. 

  342. /* Internal mask for ADC offset:                                              */

  343. /* Internal register offset for ADC offset number configuration */

  344. #define ADC_OFR1_REGOFFSET                 (0x00000000UL)

  345. #define ADC_OFR2_REGOFFSET                 (0x00000001UL)

  346. #define ADC_OFR3_REGOFFSET                 (0x00000002UL)

  347. #define ADC_OFR4_REGOFFSET                 (0x00000003UL)

  348. #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

  349. 

  350. 

  351. /* ADC registers bits positions */

  352. #define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)

  353. #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)

  354. #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)

  355. #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)

  356. 

  357. 

  358. /* ADC registers bits groups */

  359. #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

  360. 

  361. 

  362. /* ADC internal channels related definitions */

  363. /* Internal voltage reference VrefInt */

  364. #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  365. #define VREFINT_CAL_VREF                   (3300UL)                     /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

  366. /* Temperature sensor */

  367. #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  368. #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  369. #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  370. #define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  371. #define TEMPSENSOR_CAL_VREFANALOG          (3300UL)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

  372. 

  373. 

  374. /**

  375.   * @}

  376.   */

  377. 

  378. 

  379. /* Private macros ------------------------------------------------------------*/

  380. /** @defgroup ADC_LL_Private_Macros ADC Private Macros

  381.   * @{

  382.   */

  383. 

  384. /**

  385.   * @brief  Driver macro reserved for internal use: set a pointer to

  386.   *         a register from a register basis from which an offset

  387.   *         is applied.

  388.   * @param  __REG__ Register basis from which the offset is applied.

  389.   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).

  390.   * @retval Pointer to register address

  391.   */

  392. #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \

  393.  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

  394. 

  395. /**

  396.   * @}

  397.   */

  398. 

  399. 

  400. /* Exported types ------------------------------------------------------------*/

  401. #if defined(USE_FULL_LL_DRIVER)

  402. /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure

  403.   * @{

  404.   */

  405. 

  406. /**

  407.   * @brief  Structure definition of some features of ADC common parameters

  408.   *         and multimode

  409.   *         (all ADC instances belonging to the same ADC common instance).

  410.   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()

  411.   *         is conditioned to ADC instances state (all ADC instances

  412.   *         sharing the same ADC common instance):

  413.   *         All ADC instances sharing the same ADC common instance must be

  414.   *         disabled.

  415.   */

  416. typedef struct

  417. {

  418.   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.

  419.                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE

  420.                                              @note On this STM32 serie, if ADC group injected is used, some

  421.                                                    clock ratio constraints between ADC clock and AHB clock

  422.                                                    must be respected. Refer to reference manual.

  423. 

  424.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */

  425. 

  426.   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

  427.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE

  428. 

  429.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */

  430. 

  431.   uint32_t MultiDMATransfer;            /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.

  432.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER

  433. 

  434.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */

  435. 

  436.   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.

  437.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY

  438. 

  439.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */

  440. 

  441. } LL_ADC_CommonInitTypeDef;

  442. 

  443. /**

  444.   * @brief  Structure definition of some features of ADC instance.

  445.   * @note   These parameters have an impact on ADC scope: ADC instance.

  446.   *         Affects both group regular and group injected (availability

  447.   *         of ADC group injected depends on STM32 families).

  448.   *         Refer to corresponding unitary functions into

  449.   *         @ref ADC_LL_EF_Configuration_ADC_Instance .

  450.   * @note   The setting of these parameters by function @ref LL_ADC_Init()

  451.   *         is conditioned to ADC state:

  452.   *         ADC instance must be disabled.

  453.   *         This condition is applied to all ADC features, for efficiency

  454.   *         and compatibility over all STM32 families. However, the different

  455.   *         features can be set under different ADC state conditions

  456.   *         (setting possible with ADC enabled without conversion on going,

  457.   *         ADC enabled with conversion on going, ...)

  458.   *         Each feature can be updated afterwards with a unitary function

  459.   *         and potentially with ADC in a different state than disabled,

  460.   *         refer to description of each function for setting

  461.   *         conditioned to ADC state.

  462.   */

  463. typedef struct

  464. {

  465.   uint32_t Resolution;                  /*!< Set ADC resolution.

  466.                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION

  467. 

  468.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */

  469. 

  470.   uint32_t LeftBitShift;                /*!< Configures the left shifting applied to the final result with or without oversampling.

  471.                                              This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */

  472. 

  473.   uint32_t LowPowerMode;                /*!< Set ADC low power mode.

  474.                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE

  475. 

  476.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */

  477. 

  478. } LL_ADC_InitTypeDef;

  479. 

  480. /**

  481.   * @brief  Structure definition of some features of ADC group regular.

  482.   * @note   These parameters have an impact on ADC scope: ADC group regular.

  483.   *         Refer to corresponding unitary functions into

  484.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  485.   *         (functions with prefix "REG").

  486.   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()

  487.   *         is conditioned to ADC state:

  488.   *         ADC instance must be disabled.

  489.   *         This condition is applied to all ADC features, for efficiency

  490.   *         and compatibility over all STM32 families. However, the different

  491.   *         features can be set under different ADC state conditions

  492.   *         (setting possible with ADC enabled without conversion on going,

  493.   *         ADC enabled with conversion on going, ...)

  494.   *         Each feature can be updated afterwards with a unitary function

  495.   *         and potentially with ADC in a different state than disabled,

  496.   *         refer to description of each function for setting

  497.   *         conditioned to ADC state.

  498.   */

  499. typedef struct

  500. {

  501.   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

  502.                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE

  503.                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge

  504.                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).

  505.                                                    In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().

  506. 

  507.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */

  508. 

  509.   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.

  510.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH

  511. 

  512.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */

  513. 

  514.   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  515.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE

  516.                                              @note This parameter has an effect only if group regular sequencer is enabled

  517.                                                    (scan length of 2 ranks or more).

  518. 

  519.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */

  520. 

  521.   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).

  522.                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE

  523.                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

  524. 

  525.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */

  526. 

  527.   uint32_t DataTransferMode;            /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.

  528.                                              This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE

  529. 

  530.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */

  531. 

  532.   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:

  533.                                              data preserved or overwritten.

  534.                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR

  535. 

  536.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */

  537. 

  538. } LL_ADC_REG_InitTypeDef;

  539. 

  540. /**

  541.   * @brief  Structure definition of some features of ADC group injected.

  542.   * @note   These parameters have an impact on ADC scope: ADC group injected.

  543.   *         Refer to corresponding unitary functions into

  544.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  545.   *         (functions with prefix "INJ").

  546.   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()

  547.   *         is conditioned to ADC state:

  548.   *         ADC instance must be disabled.

  549.   *         This condition is applied to all ADC features, for efficiency

  550.   *         and compatibility over all STM32 families. However, the different

  551.   *         features can be set under different ADC state conditions

  552.   *         (setting possible with ADC enabled without conversion on going,

  553.   *         ADC enabled with conversion on going, ...)

  554.   *         Each feature can be updated afterwards with a unitary function

  555.   *         and potentially with ADC in a different state than disabled,

  556.   *         refer to description of each function for setting

  557.   *         conditioned to ADC state.

  558.   */

  559. typedef struct

  560. {

  561.   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

  562.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE

  563.                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge

  564.                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).

  565.                                                    In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().

  566. 

  567.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */

  568. 

  569.   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.

  570.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH

  571. 

  572.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */

  573. 

  574.   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  575.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE

  576.                                              @note This parameter has an effect only if group injected sequencer is enabled

  577.                                                    (scan length of 2 ranks or more).

  578. 

  579.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */

  580. 

  581.   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.

  582.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO

  583.                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

  584. 

  585.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */

  586. 

  587. } LL_ADC_INJ_InitTypeDef;

  588. 

  589. /**

  590.   * @}

  591.   */

  592. #endif /* USE_FULL_LL_DRIVER */

  593. 

  594. /* Exported constants --------------------------------------------------------*/

  595. /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants

  596.   * @{

  597.   */

  598. 

  599. /** @defgroup ADC_LL_EC_FLAG ADC flags

  600.   * @brief    Flags defines which can be used with LL_ADC_ReadReg function

  601.   * @{

  602.   */

  603. #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */

  604. #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */

  605. #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */

  606. #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */

  607. #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */

  608. #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */

  609. #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */

  610. #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */

  611. #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */

  612. #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */

  613. #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */

  614. #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */

  615. #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */

  616. #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */

  617. #define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */

  618. #define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */

  619. #define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */

  620. #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */

  621. #define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */

  622. #define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */

  623. #define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */

  624. #define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */

  625. #define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */

  626. #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */

  627. #define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */

  628. #define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */

  629. #define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */

  630. #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */

  631. #define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */

  632. #define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */

  633. #define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */

  634. #define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */

  635. #define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */

  636. /**

  637.   * @}

  638.   */

  639. 

  640. /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)

  641.   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions

  642.   * @{

  643.   */

  644. #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */

  645. #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */

  646. #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */

  647. #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */

  648. #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */

  649. #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */

  650. #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */

  651. #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */

  652. #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */

  653. #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */

  654. #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */

  655. /**

  656.   * @}

  657.   */

  658. 

  659. /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose

  660.   * @{

  661.   */

  662. /* List of ADC registers intended to be used (most commonly) with             */

  663. /* DMA transfer.                                                              */

  664. /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */

  665. #define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

  666. #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

  667. /**

  668.   * @}

  669.   */

  670. 

  671. /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source

  672.   * @{

  673.   */

  674. #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */

  675. #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */

  676. #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */

  677. #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */

  678. #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */

  679. #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */

  680. #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */

  681. #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */

  682. #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */

  683. #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */

  684. #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */

  685. #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */

  686. #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */

  687. #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */

  688. #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */

  689. /**

  690.   * @}

  691.   */

  692. 

  693. /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels

  694.   * @{

  695.   */

  696. /* Note: Other measurement paths to internal channels may be available        */

  697. /*       (connections to other peripherals).                                  */

  698. /*       If they are not listed below, they do not require any specific       */

  699. /*       path enable. In this case, Access to measurement path is done        */

  700. /*       only by selecting the corresponding ADC internal channel.            */

  701. #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement pathes all disabled */

  702. #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */

  703. #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */

  704. #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */

  705. /**

  706.   * @}

  707.   */

  708. 

  709. /** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode

  710.   * @{

  711.   */

  712. #define LL_ADC_BOOST_MODE_6MHZ25   (0x00000000UL)                                            /*!< Boost mode is configured for frequency <= 6.25Mhz           */

  713. #define LL_ADC_BOOST_MODE_12MHZ5   (                                        ADC_CR_BOOST_0)  /*!< Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz */

  714. #define LL_ADC_BOOST_MODE_20MHZ    (                       ADC_CR_BOOST_1                 )  /*!< Boost mode is configured for 12.5Mhz < frequency <= 20Mhz   */

  715. #define LL_ADC_BOOST_MODE_25MHZ    ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1                 )  /*!< Boost mode is configured for 20Mhz   < frequency <= 25Mhz   */

  716. #define LL_ADC_BOOST_MODE_50MHZ    ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)  /*!< Boost mode is configured for frequency > 25Mhz              */

  717. /**

  718.   * @}

  719.   */

  720. 

  721. /** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY  ADC instance - Calibration mode for offset and linearity

  722.   * @{

  723.   */

  724. #define LL_ADC_CALIB_OFFSET                (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)                      /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */

  725. #define LL_ADC_CALIB_LINEARITY             (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)                   /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */

  726. #define LL_ADC_CALIB_OFFSET_LINEARITY      (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */

  727. /**

  728.   * @}

  729.   */

  730. 

  731. /** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD  ADC instance - Calibration linearity words

  732.   * @{

  733.   */

  734. #define LL_ADC_CALIB_LINEARITY_WORD1       (ADC_CR_LINCALRDYW1)    /*!< ADC calibration linearity word 1 */

  735. #define LL_ADC_CALIB_LINEARITY_WORD2       (ADC_CR_LINCALRDYW2)    /*!< ADC calibration linearity word 2 */

  736. #define LL_ADC_CALIB_LINEARITY_WORD3       (ADC_CR_LINCALRDYW3)    /*!< ADC calibration linearity word 3 */

  737. #define LL_ADC_CALIB_LINEARITY_WORD4       (ADC_CR_LINCALRDYW4)    /*!< ADC calibration linearity word 4 */

  738. #define LL_ADC_CALIB_LINEARITY_WORD5       (ADC_CR_LINCALRDYW5)    /*!< ADC calibration linearity word 5 */

  739. #define LL_ADC_CALIB_LINEARITY_WORD6       (ADC_CR_LINCALRDYW6)    /*!< ADC calibration linearity word 6 */

  740. /**

  741.   * @}

  742.   */

  743. 

  744. /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution

  745.   * @{

  746.   */

  747. #define LL_ADC_RESOLUTION_16B              (0x00000000UL)                                   /*!< ADC resolution 16 bits */

  748. #define LL_ADC_RESOLUTION_14B              (                                ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */

  749. #define LL_ADC_RESOLUTION_12B              (               ADC_CFGR_RES_1                 ) /*!< ADC resolution 12 bits */

  750. #define LL_ADC_RESOLUTION_10B              (               ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */

  751. #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_2                                ) /*!< ADC resolution  8 bits */

  752. /**

  753.   * @}

  754.   */

  755. 

  756. /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT   ADC left Shift

  757.   * @{

  758.   */

  759. #define LL_ADC_LEFT_BIT_SHIFT_NONE  (0x00000000UL)                                                                       /*!< ADC no bit shift left applied on the final ADC convesion data */

  760. #define LL_ADC_LEFT_BIT_SHIFT_1     (ADC_CFGR2_LSHIFT_0)                                                                 /*!< ADC 1 bit shift left applied on the final ADC convesion data */

  761. #define LL_ADC_LEFT_BIT_SHIFT_2     (ADC_CFGR2_LSHIFT_1)                                                                 /*!< ADC 2 bits shift left applied on the final ADC convesion data */

  762. #define LL_ADC_LEFT_BIT_SHIFT_3     (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 3 bits shift left applied on the final ADC convesion data */

  763. #define LL_ADC_LEFT_BIT_SHIFT_4     (ADC_CFGR2_LSHIFT_2)                                                                 /*!< ADC 4 bits shift left applied on the final ADC convesion data */

  764. #define LL_ADC_LEFT_BIT_SHIFT_5     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 5 bits shift left applied on the final ADC convesion data */

  765. #define LL_ADC_LEFT_BIT_SHIFT_6     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 6 bits shift left applied on the final ADC convesion data */

  766. #define LL_ADC_LEFT_BIT_SHIFT_7     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 7 bits shift left applied on the final ADC convesion data */

  767. #define LL_ADC_LEFT_BIT_SHIFT_8     (ADC_CFGR2_LSHIFT_3)                                                                 /*!< ADC 8 bits shift left applied on the final ADC convesion data */

  768. #define LL_ADC_LEFT_BIT_SHIFT_9     (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 9 bits shift left applied on the final ADC convesion data */

  769. #define LL_ADC_LEFT_BIT_SHIFT_10    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 10 bits shift left applied on the final ADC convesion data */

  770. #define LL_ADC_LEFT_BIT_SHIFT_11    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 11 bits shift left applied on the final ADC convesion data */

  771. #define LL_ADC_LEFT_BIT_SHIFT_12    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)                                            /*!< ADC 12 bits shift left applied on the final ADC convesion data */

  772. #define LL_ADC_LEFT_BIT_SHIFT_13    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 13 bits shift left applied on the final ADC convesion data */

  773. #define LL_ADC_LEFT_BIT_SHIFT_14    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                       /*!< ADC 14 bits shift left applied on the final ADC convesion data */

  774. #define LL_ADC_LEFT_BIT_SHIFT_15    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)  /*!< ADC 15 bits shift left applied on the final ADC convesion data */

  775. /**

  776.   * @}

  777.   */

  778. 

  779. /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode

  780.   * @{

  781.   */

  782. #define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low power mode activated */

  783. #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */

  784. /**

  785.   * @}

  786.   */

  787. 

  788. /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number

  789.   * @{

  790.   */

  791. #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  792. #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  793. #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  794. #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  795. /**

  796.   * @}

  797.   */

  798. 

  799. /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode

  800.   * @{

  801.   */

  802. #define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE   (0x00000000UL)   /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */

  803. #define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE    (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */

  804. /**

  805.   * @}

  806.   */

  807. 

  808. /** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift

  809.   * @{

  810.   */

  811. #define LL_ADC_OFFSET_RSHIFT_DISABLE   (0x00000000UL)      /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */

  812. #define LL_ADC_OFFSET_RSHIFT_ENABLE    (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */

  813. /**

  814.   * @}

  815.   */

  816. /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups

  817.   * @{

  818.   */

  819. #define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */

  820. #define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/

  821. #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected */

  822. /**

  823.   * @}

  824.   */

  825. 

  826. /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number

  827.   * @{

  828.   */

  829. #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */

  830. #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */

  831. #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */

  832. #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */

  833. #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */

  834. #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */

  835. #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */

  836. #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */

  837. #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */

  838. #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */

  839. #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */

  840. #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */

  841. #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */

  842. #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */

  843. #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */

  844. #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */

  845. #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */

  846. #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */

  847. #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */

  848. #define LL_ADC_CHANNEL_19                  (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */

  849. /*!< ADC3 is defined only in the case of STM32H7XX */

  850. #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */

  851. #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */

  852. #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */

  853. #define LL_ADC_CHANNEL_DAC1CH1_ADC2        (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */

  854. #define LL_ADC_CHANNEL_DAC1CH2_ADC2        (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */

  855. /**

  856.   * @}

  857.   */

  858. 

  859. /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source

  860.   * @{

  861.   */

  862. #define LL_ADC_REG_TRIG_SOFTWARE          (0x00000000UL)                                                                                                    /*!< ADC group regular conversion trigger internal: SW start. */

  863. #define LL_ADC_REG_TRIG_EXT_TIM1_CH1      (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                   /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  864. #define LL_ADC_REG_TRIG_EXT_TIM1_CH2      (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  865. #define LL_ADC_REG_TRIG_EXT_TIM1_CH3      (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  866. #define LL_ADC_REG_TRIG_EXT_TIM2_CH2      (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  867. #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO     (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */

  868. #define LL_ADC_REG_TRIG_EXT_TIM4_CH4      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  869. #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */

  870. #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */

  871. #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2    (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */

  872. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */

  873. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */

  874. #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */

  875. #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */

  876. #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */

  877. #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */

  878. #define LL_ADC_REG_TRIG_EXT_TIM3_CH4      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  879. #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1    (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */

  880. #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */

  881. #define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */

  882. #define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */

  883. #define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */

  884. /**

  885.   * @}

  886.   */

  887. 

  888. /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge

  889.   * @{

  890.   */

  891. #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */

  892. #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */

  893. #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */

  894. /**

  895.   * @}

  896.   */

  897. 

  898. /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode

  899. * @{

  900. */

  901. #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are performed in single mode: one conversion per trigger */

  902. #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */

  903. /**

  904.   * @}

  905.   */

  906. 

  907. /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE  ADC group regular - Data transfer mode of ADC conversion data

  908.   * @{

  909.   */

  910. #define LL_ADC_REG_DR_TRANSFER             (0x00000000UL)                        /*!< ADC conversions are transferred to DR rigister */

  911. #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                   ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */

  912. #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */

  913. #define LL_ADC_REG_DFSDM_TRANSFER          (ADC_CFGR_DMNGT_1                   ) /*!< ADC conversion data are transferred to DFSDM */

  914. /**

  915.   * @}

  916.   */

  917. 

  918. /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data

  919. * @{

  920. */

  921. #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior in case of overrun: data preserved */

  922. #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */

  923. /**

  924.   * @}

  925.   */

  926. 

  927. /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length

  928.   * @{

  929.   */

  930. #define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                              /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  931. #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */

  932. #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */

  933. #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */

  934. #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */

  935. #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */

  936. #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */

  937. #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */

  938. #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */

  939. #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */

  940. #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */

  941. #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */

  942. #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */

  943. #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */

  944. #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */

  945. #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */

  946. /**

  947.   * @}

  948.   */

  949. 

  950. /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode

  951.   * @{

  952.   */

  953. #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                                               /*!< ADC group regular sequencer discontinuous mode disable */

  954. #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */

  955. #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */

  956. #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */

  957. #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */

  958. #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */

  959. #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */

  960. #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */

  961. #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */

  962. /**

  963.   * @}

  964.   */

  965. 

  966. /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks

  967.   * @{

  968.   */

  969. #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */

  970. #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */

  971. #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */

  972. #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */

  973. #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */

  974. #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */

  975. #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */

  976. #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */

  977. #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */

  978. #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */

  979. #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */

  980. #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */

  981. #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */

  982. #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */

  983. #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */

  984. #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */

  985. /**

  986.   * @}

  987.   */

  988. 

  989. /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source

  990.   * @{

  991.   */

  992. #define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                                                                                         /*!< ADC group injected conversion trigger internal: SW start. */

  993. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                        /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */

  994. #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  995. #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */

  996. #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  997. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  998. #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */

  999. #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */

  1000. #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1001. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */

  1002. #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */

  1003. #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */

  1004. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1005. #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                            /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */

  1006. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1007. #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */

  1008. #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */

  1009. #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                                   /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */

  1010. #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */

  1011. #define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */

  1012. #define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */

  1013. #define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1014. /**

  1015.   * @}

  1016.   */

  1017. 

  1018. /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge

  1019.   * @{

  1020.   */

  1021. #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */

  1022. #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */

  1023. #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */

  1024. /**

  1025.   * @}

  1026.   */

  1027. 

  1028. /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode

  1029. * @{

  1030. */

  1031. #define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */

  1032. #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */

  1033. /**

  1034.   * @}

  1035.   */

  1036. 

  1037. /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode

  1038.   * @{

  1039.   */

  1040. #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */

  1041. #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */

  1042. #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

  1043. /**

  1044.   * @}

  1045.   */

  1046. 

  1047. /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length

  1048.   * @{

  1049.   */

  1050. #define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  1051. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */

  1052. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */

  1053. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */

  1054. /**

  1055.   * @}

  1056.   */

  1057. 

  1058. /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode

  1059.   * @{

  1060.   */

  1061. #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer discontinuous mode disable */

  1062. #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */

  1063. /**

  1064.   * @}

  1065.   */

  1066. 

  1067. /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks

  1068.   * @{

  1069.   */

  1070. #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */

  1071. #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */

  1072. #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */

  1073. #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */

  1074. /**

  1075.   * @}

  1076.   */

  1077. 

  1078. /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time

  1079.   * @{

  1080.   */

  1081. #define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000UL)                                              /*!< Sampling time 1.5 ADC clock cycles */

  1082. #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */

  1083. #define LL_ADC_SAMPLINGTIME_8CYCLES_5      (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 8.5 ADC clock cycles */

  1084. #define LL_ADC_SAMPLINGTIME_16CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */

  1085. #define LL_ADC_SAMPLINGTIME_32CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 32.5 ADC clock cycles */

  1086. #define LL_ADC_SAMPLINGTIME_64CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */

  1087. #define LL_ADC_SAMPLINGTIME_387CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 387.5 ADC clock cycles */

  1088. #define LL_ADC_SAMPLINGTIME_810CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */

  1089. /**

  1090.   * @}

  1091.   */

  1092. 

  1093. /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending

  1094.   * @{

  1095.   */

  1096. #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */

  1097. #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */

  1098. #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */

  1099. /**

  1100.   * @}

  1101.   */

  1102. 

  1103. /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number

  1104.   * @{

  1105.   */

  1106. #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */

  1107. #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */

  1108. #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */

  1109. /**

  1110.   * @}

  1111.   */

  1112. 

  1113. /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels

  1114.   * @{

  1115.   */

  1116. #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                                      /*!< ADC analog watchdog monitoring disabled */

  1117. #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */

  1118. #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */

  1119. #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */

  1120. #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */

  1121. #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */

  1122. #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */

  1123. #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */

  1124. #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */

  1125. #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */

  1126. #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */

  1127. #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */

  1128. #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */

  1129. #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */

  1130. #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */

  1131. #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */

  1132. #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */

  1133. #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */

  1134. #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */

  1135. #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */

  1136. #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */

  1137. #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */

  1138. #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */

  1139. #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */

  1140. #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */

  1141. #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */

  1142. #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */

  1143. #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */

  1144. #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */

  1145. #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */

  1146. #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */

  1147. #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */

  1148. #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */

  1149. #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */

  1150. #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */

  1151. #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */

  1152. #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */

  1153. #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */

  1154. #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */

  1155. #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */

  1156. #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */

  1157. #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */

  1158. #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */

  1159. #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */

  1160. #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */

  1161. #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */

  1162. #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */

  1163. #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */

  1164. #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */

  1165. #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */

  1166. #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */

  1167. #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */

  1168. #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */

  1169. #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */

  1170. #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */

  1171. #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */

  1172. #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */

  1173. #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */

  1174. #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */

  1175. #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */

  1176. #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */

  1177. #define LL_ADC_AWD_CHANNEL_19_REG          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */

  1178. #define LL_ADC_AWD_CHANNEL_19_INJ          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */

  1179. #define LL_ADC_AWD_CHANNEL_19_REG_INJ      ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */

  1180. #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */

  1181. #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */

  1182. #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */

  1183. #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */

  1184. #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */

  1185. #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */

  1186. #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */

  1187. #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */

  1188. #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */

  1189. #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */

  1190. #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */

  1191. #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */

  1192. #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */

  1193. #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */

  1194. #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */

  1195. /**

  1196.   * @}

  1197.   */

  1198. 

  1199. /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds

  1200.   * @{

  1201.   */

  1202. #define LL_ADC_AWD_THRESHOLD_HIGH          (0x1UL)                     /*!< ADC analog watchdog threshold high */

  1203. #define LL_ADC_AWD_THRESHOLD_LOW           (0x0UL)                     /*!< ADC analog watchdog threshold low */

  1204. /**

  1205.   * @}

  1206.   */

  1207. 

  1208. /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope

  1209.   * @{

  1210.   */

  1211. #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */

  1212. #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */

  1213. #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */

  1214. #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */

  1215. #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */

  1216. /**

  1217.   * @}

  1218.   */

  1219. 

  1220. /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode

  1221.   * @{

  1222.   */

  1223. #define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */

  1224. #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */

  1225. /**

  1226.   * @}

  1227.   */

  1228. 

  1229. /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift

  1230.   * @{

  1231.   */

  1232. #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                                              /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */

  1233. #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */

  1234. #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */

  1235. #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */

  1236. #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */

  1237. #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */

  1238. #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */

  1239. #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */

  1240. #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */

  1241. #define LL_ADC_OVS_SHIFT_RIGHT_9           (ADC_CFGR2_OVSS_3                                       | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */

  1242. #define LL_ADC_OVS_SHIFT_RIGHT_10          (ADC_CFGR2_OVSS_3                    | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */

  1243. #define LL_ADC_OVS_SHIFT_RIGHT_11          (ADC_CFGR2_OVSS_3                    | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */

  1244. /**

  1245.   * @}

  1246.   */

  1247. 

  1248. /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode

  1249.   * @{

  1250.   */

  1251. #define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                                                      /*!< ADC dual mode disabled (ADC independent mode) */

  1252. #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */

  1253. #define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */

  1254. #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */

  1255. #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */

  1256. #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */

  1257. #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */

  1258. #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */

  1259. /**

  1260.   * @}

  1261.   */

  1262. 

  1263. /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer

  1264.   * @{

  1265.   */

  1266. #define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                      /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */

  1267. #define LL_ADC_MULTI_REG_DMA_RES_32_10B      (ADC_CCR_DAMDF_1                  ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */

  1268. #define LL_ADC_MULTI_REG_DMA_RES_8B          (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */

  1269. /**

  1270.   * @}

  1271.   */

  1272. 

  1273. /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases

  1274.   * @{

  1275.   */

  1276. #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5           (0x00000000UL)                                                          /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution                    */

  1277. #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5          (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution                   */

  1278. #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5          (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution                   */

  1279. #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5          (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */

  1280. #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS   (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles  for 8 bits resolution               */

  1281. #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5          (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution       */

  1282. #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution               */

  1283. #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution            */

  1284. #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5          (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution         */

  1285. #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution               */

  1286. #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5          (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution               */

  1287. #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution                 */

  1288. #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution           */

  1289. /**

  1290.   * @}

  1291.   */

  1292. 

  1293. /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave

  1294.   * @{

  1295.   */

  1296. #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */

  1297. #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */

  1298. #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */

  1299. /**

  1300.   * @}

  1301.   */

  1302. 

  1303. 

  1304. 

  1305. /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays

  1306.   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,

  1307.   *         not timeout values.

  1308.   *         For details on delays values, refer to descriptions in source code

  1309.   *         above each literal definition.

  1310.   * @{

  1311.   */

  1312. 

  1313. /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */

  1314. /*       not timeout values.                                                  */

  1315. /*       Timeout values for ADC operations are dependent to device clock      */

  1316. /*       configuration (system clock versus ADC clock),                       */

  1317. /*       and therefore must be defined in user application.                   */

  1318. /*       Indications for estimation of ADC timeout delays, for this           */

  1319. /*       STM32 serie:                                                         */

  1320. /*       - ADC calibration time: maximum delay is 16384/fADC.                   */

  1321. /*         (refer to device datasheet, parameter "tCAL")                      */

  1322. /*       - ADC enable time: maximum delay is 1 conversion cycle.              */

  1323. /*         (refer to device datasheet, parameter "tSTAB")                     */

  1324. /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */

  1325. /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */

  1326. /*         cycles                                                             */

  1327. /*       - ADC conversion time: duration depending on ADC clock and ADC       */

  1328. /*         configuration.                                                     */

  1329. /*         (refer to device reference manual, section "Timing")               */

  1330. 

  1331. /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */

  1332. /* Delay set to maximum value (refer to device datasheet,                     */

  1333. /* parameter "tADCVREG_STUP").                                                */

  1334. /* Unit: us                                                                   */

  1335. #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */

  1336. 

  1337. /* Delay for internal voltage reference stabilization time.                   */

  1338. /* Delay set to maximum value (refer to device datasheet,                     */

  1339. /* parameter "ts_vrefint").                                                   */

  1340. /* Unit: us                                                                   */

  1341. #define LL_ADC_DELAY_VREFINT_STAB_US       (5UL)  /*!< Delay for internal voltage reference stabilization time */

  1342. 

  1343. /* Delay for temperature sensor stabilization time.                           */

  1344. /* Literal set to maximum value (refer to device datasheet,                   */

  1345. /* parameter "tSTART_RUN").                                                   */

  1346. /* Unit: us                                                                   */

  1347. #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ( 26UL)  /*!< Delay for temperature sensor stabilization time */

  1348. 

  1349. /* Delay required between ADC end of calibration and ADC enable.              */

  1350. /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */

  1351. /*       are required between ADC end of calibration and ADC enable.          */

  1352. /*       Wait time can be computed in user application by waiting for the     */

  1353. /*       equivalent number of CPU cycles, by taking into account              */

  1354. /*       ratio of CPU clock versus ADC clock prescalers.                      */

  1355. /* Unit: ADC clock cycles.                                                    */

  1356. #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (  4UL)  /*!< Delay required between ADC end of calibration and ADC enable */

  1357. 

  1358. /* Fixed timeout value for ADC linearity word bit set/clear delay.                         */

  1359. /* Values defined to be higher than worst cases: low clock frequency,                      */

  1360. /* maximum prescalers.                                                                     */

  1361. /* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value                         */

  1362. /* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB  */

  1363. /*           6 / 4577 = 1,311ms                                                            */

  1364. /* At maximum CPU speed (400 MHz), this means                                              */

  1365. /*    3.58 * 400 MHz = 524400 CPU cycles                                                   */

  1366. #define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT         (524400UL)      /*!< ADC linearity set/clear bit delay */

  1367. 

  1368. /**

  1369.   * @}

  1370.   */

  1371. 

  1372. /**

  1373.   * @}

  1374.   */

  1375. 

  1376. 

  1377. /* Exported macro ------------------------------------------------------------*/

  1378. /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros

  1379.   * @{

  1380.   */

  1381. 

  1382. /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros

  1383.   * @{

  1384.   */

  1385. 

  1386. /**

  1387.   * @brief  Write a value in ADC register

  1388.   * @param  __INSTANCE__ ADC Instance

  1389.   * @param  __REG__ Register to be written

  1390.   * @param  __VALUE__ Value to be written in the register

  1391.   * @retval None

  1392.   */

  1393. #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

  1394. 

  1395. /**

  1396.   * @brief  Read a value in ADC register

  1397.   * @param  __INSTANCE__ ADC Instance

  1398.   * @param  __REG__ Register to be read

  1399.   * @retval Register value

  1400.   */

  1401. #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

  1402. /**

  1403.   * @}

  1404.   */

  1405. 

  1406. /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro

  1407.   * @{

  1408.   */

  1409. 

  1410. /**

  1411.   * @brief  Helper macro to get ADC channel number in decimal format

  1412.   *         from literals LL_ADC_CHANNEL_x.

  1413.   * @note   Example:

  1414.   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)

  1415.   *           will return decimal number "4".

  1416.   * @note   The input can be a value from functions where a channel

  1417.   *         number is returned, either defined with number

  1418.   *         or with bitfield (only one bit must be set).

  1419.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1420.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1421.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1422.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1423.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1424.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1425.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1426.   *         @arg @ref LL_ADC_CHANNEL_6

  1427.   *         @arg @ref LL_ADC_CHANNEL_7

  1428.   *         @arg @ref LL_ADC_CHANNEL_8

  1429.   *         @arg @ref LL_ADC_CHANNEL_9

  1430.   *         @arg @ref LL_ADC_CHANNEL_10

  1431.   *         @arg @ref LL_ADC_CHANNEL_11

  1432.   *         @arg @ref LL_ADC_CHANNEL_12

  1433.   *         @arg @ref LL_ADC_CHANNEL_13

  1434.   *         @arg @ref LL_ADC_CHANNEL_14

  1435.   *         @arg @ref LL_ADC_CHANNEL_15

  1436.   *         @arg @ref LL_ADC_CHANNEL_16

  1437.   *         @arg @ref LL_ADC_CHANNEL_17

  1438.   *         @arg @ref LL_ADC_CHANNEL_18

  1439.   *         @arg @ref LL_ADC_CHANNEL_19

  1440.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1441.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1442.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1443.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1444.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1445.   *

  1446.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1447.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1448.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1449.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  1450.   * @retval Value between Min_Data=0 and Max_Data=18

  1451.   */

  1452. #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \

  1453.   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL)                                 \

  1454.     ? (                                                                                    \

  1455.        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \

  1456.       )                                                                                    \

  1457.       :                                                                                    \

  1458.       (                                                                                    \

  1459.        (uint32_t)POSITION_VAL((__CHANNEL__))                                               \

  1460.       )                                                                                    \

  1461.   )

  1462. 

  1463. /**

  1464.   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x

  1465.   *         from number in decimal format.

  1466.   * @note   Example:

  1467.   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)

  1468.   *           will return a data equivalent to "LL_ADC_CHANNEL_4".

  1469.   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18

  1470.   * @retval Returned value can be one of the following values:

  1471.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1472.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1473.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1474.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1475.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1476.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1477.   *         @arg @ref LL_ADC_CHANNEL_6

  1478.   *         @arg @ref LL_ADC_CHANNEL_7

  1479.   *         @arg @ref LL_ADC_CHANNEL_8

  1480.   *         @arg @ref LL_ADC_CHANNEL_9

  1481.   *         @arg @ref LL_ADC_CHANNEL_10

  1482.   *         @arg @ref LL_ADC_CHANNEL_11

  1483.   *         @arg @ref LL_ADC_CHANNEL_12

  1484.   *         @arg @ref LL_ADC_CHANNEL_13

  1485.   *         @arg @ref LL_ADC_CHANNEL_14

  1486.   *         @arg @ref LL_ADC_CHANNEL_15

  1487.   *         @arg @ref LL_ADC_CHANNEL_16

  1488.   *         @arg @ref LL_ADC_CHANNEL_17

  1489.   *         @arg @ref LL_ADC_CHANNEL_18

  1490.   *         @arg @ref LL_ADC_CHANNEL_19

  1491.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1492.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1493.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1494.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1495.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1496.   *

  1497.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1498.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1499.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1500.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  1501.   *         (1, 2) For ADC channel read back from ADC register,

  1502.   *                comparison with internal channel parameter to be done

  1503.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1504.   */

  1505. #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \

  1506.   (((__DECIMAL_NB__) <= 9UL)                                                                            \

  1507.     ? (                                                                                                 \

  1508.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \

  1509.        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \

  1510.        (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \

  1511.       )                                                                                                 \

  1512.       :                                                                                                 \

  1513.       (                                                                                                 \

  1514.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \

  1515.        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \

  1516.        (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \

  1517.       )                                                                                                 \

  1518.   )

  1519. 

  1520. /**

  1521.   * @brief  Helper macro to determine whether the selected channel

  1522.   *         corresponds to literal definitions of driver.

  1523.   * @note   The different literal definitions of ADC channels are:

  1524.   *         - ADC internal channel:

  1525.   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...

  1526.   *         - ADC external channel (channel connected to a GPIO pin):

  1527.   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...

  1528.   * @note   The channel parameter must be a value defined from literal

  1529.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1530.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1531.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),

  1532.   *         must not be a value from functions where a channel number is

  1533.   *         returned from ADC registers,

  1534.   *         because internal and external channels share the same channel

  1535.   *         number in ADC registers. The differentiation is made only with

  1536.   *         parameters definitions of driver.

  1537.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1538.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1539.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1540.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1541.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1542.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1543.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1544.   *         @arg @ref LL_ADC_CHANNEL_6

  1545.   *         @arg @ref LL_ADC_CHANNEL_7

  1546.   *         @arg @ref LL_ADC_CHANNEL_8

  1547.   *         @arg @ref LL_ADC_CHANNEL_9

  1548.   *         @arg @ref LL_ADC_CHANNEL_10

  1549.   *         @arg @ref LL_ADC_CHANNEL_11

  1550.   *         @arg @ref LL_ADC_CHANNEL_12

  1551.   *         @arg @ref LL_ADC_CHANNEL_13

  1552.   *         @arg @ref LL_ADC_CHANNEL_14

  1553.   *         @arg @ref LL_ADC_CHANNEL_15

  1554.   *         @arg @ref LL_ADC_CHANNEL_16

  1555.   *         @arg @ref LL_ADC_CHANNEL_17

  1556.   *         @arg @ref LL_ADC_CHANNEL_18

  1557.   *         @arg @ref LL_ADC_CHANNEL_19

  1558.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1559.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1560.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1561.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1562.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1563.   *

  1564.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1565.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1566.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1567.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  1568.   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).

  1569.   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

  1570.   */

  1571. #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \

  1572.   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)

  1573. 

  1574. /**

  1575.   * @brief  Helper macro to convert a channel defined from parameter

  1576.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1577.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1578.   *         to its equivalent parameter definition of a ADC external channel

  1579.   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

  1580.   * @note   The channel parameter can be, additionally to a value

  1581.   *         defined from parameter definition of a ADC internal channel

  1582.   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1583.   *         a value defined from parameter definition of

  1584.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1585.   *         or a value from functions where a channel number is returned

  1586.   *         from ADC registers.

  1587.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1588.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1589.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1590.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1591.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1592.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1593.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1594.   *         @arg @ref LL_ADC_CHANNEL_6

  1595.   *         @arg @ref LL_ADC_CHANNEL_7

  1596.   *         @arg @ref LL_ADC_CHANNEL_8

  1597.   *         @arg @ref LL_ADC_CHANNEL_9

  1598.   *         @arg @ref LL_ADC_CHANNEL_10

  1599.   *         @arg @ref LL_ADC_CHANNEL_11

  1600.   *         @arg @ref LL_ADC_CHANNEL_12

  1601.   *         @arg @ref LL_ADC_CHANNEL_13

  1602.   *         @arg @ref LL_ADC_CHANNEL_14

  1603.   *         @arg @ref LL_ADC_CHANNEL_15

  1604.   *         @arg @ref LL_ADC_CHANNEL_16

  1605.   *         @arg @ref LL_ADC_CHANNEL_17

  1606.   *         @arg @ref LL_ADC_CHANNEL_18

  1607.   *         @arg @ref LL_ADC_CHANNEL_19

  1608.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1609.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1610.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1611.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1612.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1613.   *

  1614.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1615.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1616.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1617.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  1618.   * @retval Returned value can be one of the following values:

  1619.   *         @arg @ref LL_ADC_CHANNEL_0

  1620.   *         @arg @ref LL_ADC_CHANNEL_1

  1621.   *         @arg @ref LL_ADC_CHANNEL_2

  1622.   *         @arg @ref LL_ADC_CHANNEL_3

  1623.   *         @arg @ref LL_ADC_CHANNEL_4

  1624.   *         @arg @ref LL_ADC_CHANNEL_5

  1625.   *         @arg @ref LL_ADC_CHANNEL_6

  1626.   *         @arg @ref LL_ADC_CHANNEL_7

  1627.   *         @arg @ref LL_ADC_CHANNEL_8

  1628.   *         @arg @ref LL_ADC_CHANNEL_9

  1629.   *         @arg @ref LL_ADC_CHANNEL_10

  1630.   *         @arg @ref LL_ADC_CHANNEL_11

  1631.   *         @arg @ref LL_ADC_CHANNEL_12

  1632.   *         @arg @ref LL_ADC_CHANNEL_13

  1633.   *         @arg @ref LL_ADC_CHANNEL_14

  1634.   *         @arg @ref LL_ADC_CHANNEL_15

  1635.   *         @arg @ref LL_ADC_CHANNEL_16

  1636.   *         @arg @ref LL_ADC_CHANNEL_17

  1637.   *         @arg @ref LL_ADC_CHANNEL_18

  1638.   *         @arg @ref LL_ADC_CHANNEL_19

  1639.   */

  1640. #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \

  1641.   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  1642. 

  1643. /**

  1644.   * @brief  Helper macro to determine whether the internal channel

  1645.   *         selected is available on the ADC instance selected.

  1646.   * @note   The channel parameter must be a value defined from parameter

  1647.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1648.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1649.   *         must not be a value defined from parameter definition of

  1650.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1651.   *         or a value from functions where a channel number is

  1652.   *         returned from ADC registers,

  1653.   *         because internal and external channels share the same channel

  1654.   *         number in ADC registers. The differentiation is made only with

  1655.   *         parameters definitions of driver.

  1656.   * @param  __ADC_INSTANCE__ ADC instance

  1657.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1658.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1659.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1660.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1661.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1662.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1663.   *

  1664.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1665.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

  1666.   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.

  1667.   *         Value "1" if the internal channel selected is available on the ADC instance selected.

  1668.   */

  1669. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

  1670.   ((((__ADC_INSTANCE__) == ADC2)                                               \

  1671.     &&(                                                                        \

  1672.        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                       \

  1673.        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                          \

  1674.       )                                                                        \

  1675.    )                                                                           \

  1676.    ||                                                                          \

  1677.    (((__ADC_INSTANCE__) == ADC3)                                               \

  1678.     &&(                                                                        \

  1679.        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                       \

  1680.        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                       \

  1681.        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \

  1682.       )                                                                        \

  1683.    )                                                                           \

  1684.   )

  1685. /**

  1686.   * @brief  Helper macro to define ADC analog watchdog parameter:

  1687.   *         define a single channel to monitor with analog watchdog

  1688.   *         from sequencer channel and groups definition.

  1689.   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().

  1690.   *         Example:

  1691.   *           LL_ADC_SetAnalogWDMonitChannels(

  1692.   *             ADC1, LL_ADC_AWD1,

  1693.   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))

  1694.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1695.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1696.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1697.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1698.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1699.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1700.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1701.   *         @arg @ref LL_ADC_CHANNEL_6

  1702.   *         @arg @ref LL_ADC_CHANNEL_7

  1703.   *         @arg @ref LL_ADC_CHANNEL_8

  1704.   *         @arg @ref LL_ADC_CHANNEL_9

  1705.   *         @arg @ref LL_ADC_CHANNEL_10

  1706.   *         @arg @ref LL_ADC_CHANNEL_11

  1707.   *         @arg @ref LL_ADC_CHANNEL_12

  1708.   *         @arg @ref LL_ADC_CHANNEL_13

  1709.   *         @arg @ref LL_ADC_CHANNEL_14

  1710.   *         @arg @ref LL_ADC_CHANNEL_15

  1711.   *         @arg @ref LL_ADC_CHANNEL_16

  1712.   *         @arg @ref LL_ADC_CHANNEL_17

  1713.   *         @arg @ref LL_ADC_CHANNEL_18

  1714.   *         @arg @ref LL_ADC_CHANNEL_19

  1715.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1716.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1717.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1718.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1719.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1720.   *

  1721.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1722.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1723.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1724.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  1725.   *         (1, 2) For ADC channel read back from ADC register,

  1726.   *                comparison with internal channel parameter to be done

  1727.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1728.   * @param  __GROUP__ This parameter can be one of the following values:

  1729.   *         @arg @ref LL_ADC_GROUP_REGULAR

  1730.   *         @arg @ref LL_ADC_GROUP_INJECTED

  1731.   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED

  1732.   * @retval Returned value can be one of the following values:

  1733.   *         @arg @ref LL_ADC_AWD_DISABLE

  1734.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  1735.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

  1736.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  1737.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  1738.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

  1739.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  1740.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  1741.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

  1742.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  1743.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  1744.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

  1745.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  1746.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  1747.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

  1748.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  1749.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  1750.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

  1751.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  1752.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  1753.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

  1754.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  1755.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  1756.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

  1757.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  1758.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  1759.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

  1760.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  1761.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  1762.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

  1763.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  1764.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  1765.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

  1766.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  1767.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  1768.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

  1769.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  1770.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  1771.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

  1772.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  1773.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  1774.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

  1775.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  1776.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  1777.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

  1778.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  1779.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  1780.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

  1781.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  1782.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  1783.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

  1784.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  1785.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  1786.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

  1787.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  1788.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  1789.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

  1790.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  1791.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  1792.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

  1793.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  1794.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

  1795.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

  1796.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

  1797.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)

  1798.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)

  1799.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)

  1800.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)

  1801.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)

  1802.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)

  1803.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)

  1804.   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)

  1805.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)

  1806.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)

  1807.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)

  1808.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)

  1809.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)

  1810.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)

  1811.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)

  1812.   *

  1813.   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n

  1814.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1815.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

  1816.   */

  1817. #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \

  1818.   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \

  1819.     ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                        \

  1820.       :                                                                                                   \

  1821.       ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \

  1822.        ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    \

  1823.          :                                                                                                \

  1824.          (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  \

  1825.   )

  1826. 

  1827. /**

  1828.   * @brief  Helper macro to set the value of ADC analog watchdog threshold high

  1829.   *         or low in function of ADC resolution, when ADC resolution is

  1830.   *         different of 16 bits.

  1831.   * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().

  1832.   *         Example, with a ADC resolution of 8 bits, to set the value of

  1833.   *         analog watchdog threshold high (on 18 bits):

  1834.   *           LL_ADC_SetAnalogWDThresholds

  1835.   *            (< ADCx param >,

  1836.   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)

  1837.   *            );

  1838.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1839.   *         @arg @ref LL_ADC_RESOLUTION_16B

  1840.   *         @arg @ref LL_ADC_RESOLUTION_14B

  1841.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1842.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1843.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1844.   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

  1845.   * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

  1846.   */

  1847. #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \

  1848.   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

  1849. 

  1850. /**

  1851.   * @brief  Helper macro to get the value of ADC analog watchdog threshold high

  1852.   *         or low in function of ADC resolution, when ADC resolution is

  1853.   *         different of 16 bits.

  1854.   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().

  1855.   *         Example, with a ADC resolution of 8 bits, to get the value of

  1856.   *         analog watchdog threshold high (on 18 bits):

  1857.   *           < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION

  1858.   *            (LL_ADC_RESOLUTION_8B,

  1859.   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)

  1860.   *            );

  1861.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1862.   *         @arg @ref LL_ADC_RESOLUTION_16B

  1863.   *         @arg @ref LL_ADC_RESOLUTION_14B

  1864.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1865.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1866.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1867.   * @param  __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

  1868.   * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

  1869.   */

  1870. #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \

  1871.   ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

  1872. 

  1873. /**

  1874.   * @brief  Helper macro to set the ADC calibration value with both single ended

  1875.   *         and differential modes calibration factors concatenated.

  1876.   * @note   To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().

  1877.   *         Example, to set calibration factors single ended to 0x55

  1878.   *         and differential ended to 0x2A:

  1879.   *           LL_ADC_SetCalibrationOffsetFactor(

  1880.   *             ADC1,

  1881.   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))

  1882.   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F

  1883.   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F

  1884.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  1885.   */

  1886. #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \

  1887.   (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))

  1888. 

  1889. /**

  1890.   * @brief  Helper macro to get the ADC multimode conversion data of ADC master

  1891.   *         or ADC slave from raw value with both ADC conversion data concatenated.

  1892.   * @note   This macro is intended to be used when multimode transfer by DMA

  1893.   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().

  1894.   *         In this case the transferred data need to processed with this macro

  1895.   *         to separate the conversion data of ADC master and ADC slave.

  1896.   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:

  1897.   *         @arg @ref LL_ADC_MULTI_MASTER

  1898.   *         @arg @ref LL_ADC_MULTI_SLAVE

  1899.   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF

  1900.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  1901.   */

  1902. #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \

  1903.   (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)

  1904. 

  1905. /**

  1906.   * @brief  Helper macro to select, from a ADC instance, to which ADC instance

  1907.   *         it has a dependence in multimode (ADC master of the corresponding

  1908.   *         ADC common instance).

  1909.   * @note   In case of device with multimode available and a mix of

  1910.   *         ADC instances compliant and not compliant with multimode feature,

  1911.   *         ADC instances not compliant with multimode feature are

  1912.   *         considered as master instances (do not depend to

  1913.   *         any other ADC instance).

  1914.   * @param  __ADCx__ ADC instance

  1915.   * @retval __ADCx__ ADC instance master of the corresponding ADC common instance

  1916.   */

  1917. #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \

  1918.   ( ( ((__ADCx__) == ADC2)                                                     \

  1919.     )?                                                                         \

  1920.      (ADC1)                                                                    \

  1921.      :                                                                         \

  1922.      (__ADCx__)                                                                \

  1923.   )

  1924. 

  1925. /**

  1926.   * @brief  Helper macro to select the ADC common instance

  1927.   *         to which is belonging the selected ADC instance.

  1928.   * @note   ADC common register instance can be used for:

  1929.   *         - Set parameters common to several ADC instances

  1930.   *         - Multimode (for devices with several ADC instances)

  1931.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  1932.   * @param  __ADCx__ ADC instance

  1933.   * @retval ADC common register instance

  1934.   */

  1935. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  1936.   ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \

  1937.     ? (                                                                        \

  1938.        (ADC12_COMMON)                                                          \

  1939.       )                                                                        \

  1940.       :                                                                        \

  1941.       (                                                                        \

  1942.        (ADC3_COMMON)                                                           \

  1943.       )                                                                        \

  1944.   )

  1945. 

  1946. /**

  1947.   * @brief  Helper macro to check if all ADC instances sharing the same

  1948.   *         ADC common instance are disabled.

  1949.   * @note   This check is required by functions with setting conditioned to

  1950.   *         ADC state:

  1951.   *         All ADC instances of the ADC common group must be disabled.

  1952.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  1953.   * @note   On devices with only 1 ADC common instance, parameter of this macro

  1954.   *         is useless and can be ignored (parameter kept for compatibility

  1955.   *         with devices featuring several ADC common instances).

  1956.   * @param  __ADCXY_COMMON__ ADC common instance

  1957.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  1958.   * @retval Value "0" if all ADC instances sharing the same ADC common instance

  1959.   *         are disabled.

  1960.   *         Value "1" if at least one ADC instance sharing the same ADC common instance

  1961.   *         is enabled.

  1962.   */

  1963. #if defined(ADC3_COMMON)

  1964. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  1965.   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \

  1966.     ? (                                                                        \

  1967.        (LL_ADC_IsEnabled(ADC1) |                                               \

  1968.         LL_ADC_IsEnabled(ADC2)  )                                              \

  1969.       )                                                                        \

  1970.       :                                                                        \

  1971.       (                                                                        \

  1972.        (LL_ADC_IsEnabled(ADC3))                                                \

  1973.       )                                                                        \

  1974.   )

  1975. #else

  1976. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  1977.                         (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))

  1978. #endif

  1979. 

  1980. /**

  1981.   * @brief  Helper macro to define the ADC conversion data full-scale digital

  1982.   *         value corresponding to the selected ADC resolution.

  1983.   * @note   ADC conversion data full-scale corresponds to voltage range

  1984.   *         determined by analog voltage references Vref+ and Vref-

  1985.   *         (refer to reference manual).

  1986.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1987.   *         @arg @ref LL_ADC_RESOLUTION_16B

  1988.   *         @arg @ref LL_ADC_RESOLUTION_14B

  1989.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1990.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1991.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1992.   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)

  1993.   */

  1994. #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \

  1995.   (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))

  1996. 

  1997. /**

  1998.   * @brief  Helper macro to convert the ADC conversion data from

  1999.   *         a resolution to another resolution.

  2000.   * @param  __DATA__ ADC conversion data to be converted

  2001.   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted

  2002.   *         This parameter can be one of the following values:

  2003.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2004.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2005.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2006.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2007.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2008.   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion

  2009.   *         This parameter can be one of the following values:

  2010.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2011.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2012.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2013.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2014.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2015.   * @retval ADC conversion data to the requested resolution

  2016.   */

  2017. #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\

  2018.                                          __ADC_RESOLUTION_CURRENT__,\

  2019.                                          __ADC_RESOLUTION_TARGET__)            \

  2020.   (((__DATA__)                                                                 \

  2021.     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \

  2022.    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \

  2023.   )

  2024. 

  2025. /**

  2026.   * @brief  Helper macro to calculate the voltage (unit: mVolt)

  2027.   *         corresponding to a ADC conversion data (unit: digital value).

  2028.   * @note   Analog reference voltage (Vref+) must be either known from

  2029.   *         user board environment or can be calculated using ADC measurement

  2030.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2031.   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)

  2032.   * @param  __ADC_DATA__ ADC conversion data (resolution 16 bits)

  2033.   *                       (unit: digital value).

  2034.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  2035.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2036.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2037.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2038.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2039.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2040.   * @retval ADC conversion data equivalent voltage value (unit: mVolt)

  2041.   */

  2042. #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\

  2043.                                       __ADC_DATA__,\

  2044.                                       __ADC_RESOLUTION__)                      \

  2045.   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \

  2046.    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \

  2047.   )

  2048. 

  2049. /**

  2050.   * @brief  Helper macro to calculate analog reference voltage (Vref+)

  2051.   *         (unit: mVolt) from ADC conversion data of internal voltage

  2052.   *         reference VrefInt.

  2053.   * @note   Computation is using VrefInt calibration value

  2054.   *         stored in system memory for each device during production.

  2055.   * @note   This voltage depends on user board environment: voltage level

  2056.   *         connected to pin Vref+.

  2057.   *         On devices with small package, the pin Vref+ is not present

  2058.   *         and internally bonded to pin Vdda.

  2059.   * @note   On this STM32 serie, calibration data of internal voltage reference

  2060.   *         VrefInt corresponds to a resolution of 16 bits,

  2061.   *         this is the recommended ADC resolution to convert voltage of

  2062.   *         internal voltage reference VrefInt.

  2063.   *         Otherwise, this macro performs the processing to scale

  2064.   *         ADC conversion data to 16 bits.

  2065.   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)

  2066.   *         of internal voltage reference VrefInt (unit: digital value).

  2067.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  2068.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2069.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2070.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2071.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2072.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2073.   * @retval Analog reference voltage (unit: mV)

  2074.   */

  2075. #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\

  2076.                                          __ADC_RESOLUTION__)                   \

  2077.   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \

  2078.     / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \

  2079.                                        (__ADC_RESOLUTION__),                   \

  2080.                                        LL_ADC_RESOLUTION_16B)                  \

  2081.   )

  2082. 

  2083. /**

  2084.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  2085.   *         from ADC conversion data of internal temperature sensor.

  2086.   * @note   Computation is using temperature sensor calibration values

  2087.   *         stored in system memory for each device during production.

  2088.   * @note   Calculation formula:

  2089.   *           Temperature = ((TS_ADC_DATA - TS_CAL1)

  2090.   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))

  2091.   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP

  2092.   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC

  2093.   *                Avg_Slope = (TS_CAL2 - TS_CAL1)

  2094.   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)

  2095.   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature

  2096.   *                            TEMP_DEGC_CAL1 (calibrated in factory)

  2097.   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature

  2098.   *                            TEMP_DEGC_CAL2 (calibrated in factory)

  2099.   *         Caution: Calculation relevancy under reserve that calibration

  2100.   *                  parameters are correct (address and data).

  2101.   *                  To calculate temperature using temperature sensor

  2102.   *                  datasheet typical values (generic values less, therefore

  2103.   *                  less accurate than calibrated values),

  2104.   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().

  2105.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  2106.   *         defined as it impacts the ADC LSB equivalent voltage.

  2107.   * @note   Analog reference voltage (Vref+) must be either known from

  2108.   *         user board environment or can be calculated using ADC measurement

  2109.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2110.   * @note   On this STM32 serie, calibration data of temperature sensor

  2111.   *         corresponds to a resolution of 16 bits,

  2112.   *         this is the recommended ADC resolution to convert voltage of

  2113.   *         temperature sensor.

  2114.   *         Otherwise, this macro performs the processing to scale

  2115.   *         ADC conversion data to 16 bits.

  2116.   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)

  2117.   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal

  2118.   *                                 temperature sensor (unit: digital value).

  2119.   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature

  2120.   *                                 sensor voltage has been measured.

  2121.   *         This parameter can be one of the following values:

  2122.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2123.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2124.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2125.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2126.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2127.   * @retval Temperature (unit: degree Celsius)

  2128.   */

  2129. #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\

  2130.                                   __TEMPSENSOR_ADC_DATA__,\

  2131.                                   __ADC_RESOLUTION__)                              \

  2132.   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \

  2133.                                                     (__ADC_RESOLUTION__),          \

  2134.                                                     LL_ADC_RESOLUTION_16B)         \

  2135.                    * (__VREFANALOG_VOLTAGE__))                                     \

  2136.                   / TEMPSENSOR_CAL_VREFANALOG)                                     \

  2137.         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \

  2138.      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \

  2139.     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \

  2140.    ) + TEMPSENSOR_CAL1_TEMP                                                        \

  2141.   )

  2142. 

  2143. /**

  2144.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  2145.   *         from ADC conversion data of internal temperature sensor.

  2146.   * @note   Computation is using temperature sensor typical values

  2147.   *         (refer to device datasheet).

  2148.   * @note   Calculation formula:

  2149.   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)

  2150.   *                         / Avg_Slope + CALx_TEMP

  2151.   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC

  2152.   *                                   (unit: digital value)

  2153.   *                Avg_Slope        = temperature sensor slope

  2154.   *                                   (unit: uV/Degree Celsius)

  2155.   *                TS_TYP_CALx_VOLT = temperature sensor digital value at

  2156.   *                                   temperature CALx_TEMP (unit: mV)

  2157.   *         Caution: Calculation relevancy under reserve the temperature sensor

  2158.   *                  of the current device has characteristics in line with

  2159.   *                  datasheet typical values.

  2160.   *                  If temperature sensor calibration values are available on

  2161.   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),

  2162.   *                  temperature calculation will be more accurate using

  2163.   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().

  2164.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  2165.   *         defined as it impacts the ADC LSB equivalent voltage.

  2166.   * @note   Analog reference voltage (Vref+) must be either known from

  2167.   *         user board environment or can be calculated using ADC measurement

  2168.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2169.   * @note   ADC measurement data must correspond to a resolution of 16 bits

  2170.   *         (full scale digital value 4095). If not the case, the data must be

  2171.   *         preliminarily rescaled to an equivalent resolution of 16 bits.

  2172.   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).

  2173.   *                                       On STM32H7, refer to device datasheet parameter "Avg_Slope".

  2174.   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).

  2175.   *                                       On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).

  2176.   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)

  2177.   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)

  2178.   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).

  2179.   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.

  2180.   *         This parameter can be one of the following values:

  2181.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2182.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2183.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2184.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2185.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2186.   * @retval Temperature (unit: degree Celsius)

  2187.   */

  2188. #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\

  2189.                                              __TEMPSENSOR_TYP_CALX_V__,\

  2190.                                              __TEMPSENSOR_CALX_TEMP__,\

  2191.                                              __VREFANALOG_VOLTAGE__,\

  2192.                                              __TEMPSENSOR_ADC_DATA__,\

  2193.                                              __ADC_RESOLUTION__)               \

  2194.   ((( (                                                                        \

  2195.        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \

  2196.                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \

  2197.                  * 1000UL)                                                     \

  2198.        -                                                                       \

  2199.        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \

  2200.                  * 1000UL)                                                     \

  2201.       )                                                                        \

  2202.     ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                 \

  2203.    ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                     \

  2204.   )

  2205. 

  2206. /**

  2207.   * @}

  2208.   */

  2209. 

  2210. /**

  2211.   * @}

  2212.   */

  2213. 

  2214. 

  2215. /* Exported functions --------------------------------------------------------*/

  2216. /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions

  2217.   * @{

  2218.   */

  2219. 

  2220. /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management

  2221.   * @{

  2222.   */

  2223. 

  2224. /**

  2225.   * @brief  Function to help to configure DMA transfer from ADC: retrieve the

  2226.   *         ADC register address from ADC instance and a list of ADC registers

  2227.   *         intended to be used (most commonly) with DMA transfer.

  2228.   * @note   These ADC registers are data registers:

  2229.   *         when ADC conversion data is available in ADC data registers,

  2230.   *         ADC generates a DMA transfer request.

  2231.   * @note   This macro is intended to be used with LL DMA driver, refer to

  2232.   *         function "LL_DMA_ConfigAddresses()".

  2233.   *         Example:

  2234.   *           LL_DMA_ConfigAddresses(DMA1,

  2235.   *                                  LL_DMA_CHANNEL_1,

  2236.   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),

  2237.   *                                  (uint32_t)&< array or variable >,

  2238.   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

  2239.   * @note   For devices with several ADC: in multimode, some devices

  2240.   *         use a different data register outside of ADC instance scope

  2241.   *         (common data register). This macro manages this register difference,

  2242.   *         only ADC instance has to be set as parameter.

  2243.   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n

  2244.   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n

  2245.   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr

  2246.   * @param  ADCx ADC instance

  2247.   * @param  Register This parameter can be one of the following values:

  2248.   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA

  2249.   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)

  2250.   *

  2251.   *         (1) Available on devices with several ADC instances.

  2252.   * @retval ADC register address

  2253.   */

  2254. __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)

  2255. {

  2256.   register uint32_t data_reg_addr;

  2257. 

  2258.   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)

  2259.   {

  2260.     /* Retrieve address of register DR */

  2261.     data_reg_addr = (uint32_t)&(ADCx->DR);

  2262.   }

  2263.   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */

  2264.   {

  2265.     /* Retrieve address of register CDR */

  2266.     data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);

  2267.   }

  2268. 

  2269.   return data_reg_addr;

  2270. }

  2271. 

  2272. /**

  2273.   * @}

  2274.   */

  2275. 

  2276. /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances

  2277.   * @{

  2278.   */

  2279. 

  2280. /**

  2281.   * @brief  Set parameter common to several ADC: Clock source and prescaler.

  2282.   * @note   On this STM32 serie, if ADC group injected is used, some

  2283.   *         clock ratio constraints between ADC clock and AHB clock

  2284.   *         must be respected.

  2285.   *         Refer to reference manual.

  2286.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2287.   *         ADC state:

  2288.   *         All ADC instances of the ADC common group must be disabled.

  2289.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  2290.   *         ADC instance or by using helper macro helper macro

  2291.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  2292.   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n

  2293.   *         CCR      PRESC          LL_ADC_SetCommonClock

  2294.   * @param  ADCxy_COMMON ADC common instance

  2295.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2296.   * @param  CommonClock This parameter can be one of the following values:

  2297.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1

  2298.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

  2299.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

  2300.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

  2301.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

  2302.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

  2303.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6

  2304.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8

  2305.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10

  2306.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12

  2307.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16

  2308.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32

  2309.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64

  2310.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128

  2311.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256

  2312.   * @retval None

  2313.   */

  2314. __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)

  2315. {

  2316.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);

  2317. }

  2318. 

  2319. /**

  2320.   * @brief  Get parameter common to several ADC: Clock source and prescaler.

  2321.   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n

  2322.   *         CCR      PRESC          LL_ADC_GetCommonClock

  2323.   * @param  ADCxy_COMMON ADC common instance

  2324.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2325.   * @retval Returned value can be one of the following values:

  2326.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1

  2327.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

  2328.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

  2329.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

  2330.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

  2331.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

  2332.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6

  2333.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8

  2334.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10

  2335.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12

  2336.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16

  2337.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32

  2338.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64

  2339.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128

  2340.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256

  2341.   */

  2342. __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)

  2343. {

  2344.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));

  2345. }

  2346. 

  2347. /**

  2348.   * @brief  Set parameter common to several ADC: measurement path to internal

  2349.   *         channels (VrefInt, temperature sensor, ...).

  2350.   * @note   One or several values can be selected.

  2351.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2352.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2353.   * @note   Stabilization time of measurement path to internal channel:

  2354.   *         After enabling internal paths, before starting ADC conversion,

  2355.   *         a delay is required for internal voltage reference and

  2356.   *         temperature sensor stabilization time.

  2357.   *         Refer to device datasheet.

  2358.   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.

  2359.   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.

  2360.   * @note   ADC internal channel sampling time constraint:

  2361.   *         For ADC conversion of internal channels,

  2362.   *         a sampling time minimum value is required.

  2363.   *         Refer to device datasheet.

  2364.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2365.   *         ADC state:

  2366.   *         All ADC instances of the ADC common group must be disabled.

  2367.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  2368.   *         ADC instance or by using helper macro helper macro

  2369.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  2370.   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n

  2371.   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n

  2372.   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh

  2373.   * @param  ADCxy_COMMON ADC common instance

  2374.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2375.   * @param  PathInternal This parameter can be a combination of the following values:

  2376.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2377.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2378.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2379.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  2380.   * @retval None

  2381.   */

  2382. __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)

  2383. {

  2384.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);

  2385. }

  2386. 

  2387. /**

  2388.   * @brief  Get parameter common to several ADC: measurement path to internal

  2389.   *         channels (VrefInt, temperature sensor, ...).

  2390.   * @note   One or several values can be selected.

  2391.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2392.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2393.   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n

  2394.   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n

  2395.   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh

  2396.   * @param  ADCxy_COMMON ADC common instance

  2397.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2398.   * @retval Returned value can be a combination of the following values:

  2399.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2400.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2401.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2402.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  2403.   */

  2404. __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)

  2405. {

  2406.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));

  2407. }

  2408. 

  2409. /**

  2410.   * @}

  2411.   */

  2412. 

  2413. /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance

  2414.   * @{

  2415.   */

  2416. 

  2417. /**

  2418.   * @brief  Set ADC calibration factor in the mode single-ended

  2419.   *         or differential (for devices with differential mode available).

  2420.   * @note   This function is intended to set calibration parameters

  2421.   *         without having to perform a new calibration using

  2422.   *         @ref LL_ADC_StartCalibration().

  2423.   * @note   For devices with differential mode available:

  2424.   *         Calibration of offset is specific to each of

  2425.   *         single-ended and differential modes

  2426.   *         (calibration factor must be specified for each of these

  2427.   *         differential modes, if used afterwards and if the application

  2428.   *         requires their calibration).

  2429.   *         Calibration of linearity is common to both

  2430.   *         single-ended and differential modes

  2431.   *         (calibration factor can be specified only once).

  2432.   * @note   In case of setting calibration factors of both modes single ended

  2433.   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):

  2434.   *         both calibration factors must be concatenated.

  2435.   *         To perform this processing, use helper macro

  2436.   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().

  2437.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2438.   *         ADC state:

  2439.   *         ADC must be enabled, without calibration on going, without conversion

  2440.   *         on going on group regular.

  2441.   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationOffsetFactor\n

  2442.   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationOffsetFactor

  2443.   * @param  ADCx ADC instance

  2444.   * @param  SingleDiff This parameter can be one of the following values:

  2445.   *         @arg @ref LL_ADC_SINGLE_ENDED

  2446.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  2447.   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED

  2448.   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F

  2449.   * @retval None

  2450.   */

  2451. __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)

  2452. {

  2453.   MODIFY_REG(ADCx->CALFACT,

  2454.              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,

  2455.              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));

  2456. }

  2457. 

  2458. /**

  2459.   * @brief  Get ADC calibration factor in the mode single-ended

  2460.   *         or differential (for devices with differential mode available).

  2461.   * @note   Calibration factors are set by hardware after performing

  2462.   *         a calibration run using function @ref LL_ADC_StartCalibration().

  2463.   * @note   For devices with differential mode available:

  2464.   *         Calibration of offset is specific to each of

  2465.   *         single-ended and differential modes

  2466.   *         Calibration of linearity is common to both

  2467.   *         single-ended and differential modes

  2468.   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationOffsetFactor\n

  2469.   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationOffsetFactor

  2470.   * @param  ADCx ADC instance

  2471.   * @param  SingleDiff This parameter can be one of the following values:

  2472.   *         @arg @ref LL_ADC_SINGLE_ENDED

  2473.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  2474.   * @retval Value between Min_Data=0x00 and Max_Data=0x7F

  2475.   */

  2476. __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)

  2477. {

  2478.   /* Retrieve bits with position in register depending on parameter           */

  2479.   /* "SingleDiff".                                                            */

  2480.   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */

  2481.   /* containing other bits reserved for other purpose.                        */

  2482.   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));

  2483. }

  2484. 

  2485. /**

  2486.   * @brief  Set ADC Linear calibration factor in the mode single-ended.

  2487.   * @note   This function is intended to set linear calibration parameters

  2488.   *         without having to perform a new calibration using

  2489.   *         @ref LL_ADC_StartCalibration().

  2490.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2491.   *         ADC state:

  2492.   *         ADC must be enabled, without calibration on going, without conversion

  2493.   *         on going on group regular.

  2494.   * @rmtoll CALFACT2  LINCALFACT      LL_ADC_SetCalibrationLinearFactor\n

  2495.   *         CALFACT2  LINCALFACT      LL_ADC_SetCalibrationLinearFactor

  2496.   * @param  ADCx ADC instance

  2497.   * @param  LinearityWord This parameter can be one of the following values:

  2498.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD1

  2499.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD2

  2500.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD3

  2501.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD4

  2502.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD5

  2503.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD6

  2504.   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF

  2505.   * @retval None

  2506.   */

  2507. __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)

  2508. {

  2509.   register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;

  2510.   MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);

  2511.   MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);

  2512.   while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))

  2513.   {

  2514.     timeout_cpu_cycles--;

  2515.   }

  2516. }

  2517. 

  2518. /**

  2519.   * @brief  Get ADC Linear calibration factor in the mode single-ended.

  2520.   * @note   Calibration factors are set by hardware after performing

  2521.   *         a calibration run using function @ref LL_ADC_StartCalibration().

  2522.   * @rmtoll CALFACT2  LINCALFACT      LL_ADC_GetCalibrationLinearFactor\n

  2523.   *         CALFACT2  LINCALFACT      LL_ADC_GetCalibrationLinearFactor

  2524.   * @param  ADCx ADC instance

  2525.   * @param  LinearityWord This parameter can be one of the following values:

  2526.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD1

  2527.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD2

  2528.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD3

  2529.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD4

  2530.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD5

  2531.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD6

  2532.   * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF

  2533.   */

  2534. __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)

  2535. {

  2536.   register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;

  2537.   CLEAR_BIT(ADCx->CR, LinearityWord);

  2538.   while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))

  2539.   {

  2540.     timeout_cpu_cycles--;

  2541.   }

  2542.   return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));

  2543. }

  2544. /**

  2545.   * @brief  Set ADC resolution.

  2546.   *         Refer to reference manual for alignments formats

  2547.   *         dependencies to ADC resolutions.

  2548.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2549.   *         ADC state:

  2550.   *         ADC must be disabled or enabled without conversion on going

  2551.   *         on either groups regular or injected.

  2552.   * @rmtoll CFGR     RES            LL_ADC_SetResolution

  2553.   * @param  ADCx ADC instance

  2554.   * @param  Resolution This parameter can be one of the following values:

  2555.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2556.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2557.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2558.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2559.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2560.   * @retval None

  2561.   */

  2562. __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)

  2563. {

  2564.   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */

  2565.   {

  2566.     MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

  2567.   }

  2568.   else /* rev.V */

  2569.   {

  2570.     if(LL_ADC_RESOLUTION_8B == Resolution)

  2571.     {

  2572.       MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);

  2573.     }

  2574.     else

  2575.     {

  2576.       MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

  2577.     }

  2578.   }

  2579. }

  2580. 

  2581. /**

  2582.   * @brief  Get ADC resolution.

  2583.   *         Refer to reference manual for alignments formats

  2584.   *         dependencies to ADC resolutions.

  2585.   * @rmtoll CFGR     RES            LL_ADC_GetResolution

  2586.   * @param  ADCx ADC instance

  2587.   * @retval Returned value can be one of the following values:

  2588.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2589.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2590.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2591.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2592.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2593.   */

  2594. __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)

  2595. {

  2596.   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */

  2597.   {

  2598.     return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

  2599.   }

  2600.   else

  2601.   {

  2602.     if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)

  2603.     {

  2604.       return (LL_ADC_RESOLUTION_8B);

  2605.     }

  2606.     else

  2607.     {

  2608.       return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

  2609.     }

  2610.   }

  2611. }

  2612. 

  2613. /**

  2614.   * @brief  Set ADC low power mode.

  2615.   * @note   Description of ADC low power modes:

  2616.   *         - ADC low power mode "auto wait": Dynamic low power mode,

  2617.   *           ADC conversions occurrences are limited to the minimum necessary

  2618.   *           in order to reduce power consumption.

  2619.   *           New ADC conversion starts only when the previous

  2620.   *           unitary conversion data (for ADC group regular)

  2621.   *           or previous sequence conversions data (for ADC group injected)

  2622.   *           has been retrieved by user software.

  2623.   *           In the meantime, ADC remains idle: does not performs any

  2624.   *           other conversion.

  2625.   *           This mode allows to automatically adapt the ADC conversions

  2626.   *           triggers to the speed of the software that reads the data.

  2627.   *           Moreover, this avoids risk of overrun for low frequency

  2628.   *           applications.

  2629.   *           How to use this low power mode:

  2630.   *           - Do not use with interruption or DMA since these modes

  2631.   *             have to clear immediately the EOC flag to free the

  2632.   *             IRQ vector sequencer.

  2633.   *           - Do use with polling: 1. Start conversion,

  2634.   *             2. Later on, when conversion data is needed: poll for end of

  2635.   *             conversion  to ensure that conversion is completed and

  2636.   *             retrieve ADC conversion data. This will trig another

  2637.   *             ADC conversion start.

  2638.   *         - ADC low power mode "auto power-off" (feature available on

  2639.   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):

  2640.   *           the ADC automatically powers-off after a conversion and

  2641.   *           automatically wakes up when a new conversion is triggered

  2642.   *           (with startup time between trigger and start of sampling).

  2643.   *           This feature can be combined with low power mode "auto wait".

  2644.   * @note   With ADC low power mode "auto wait", the ADC conversion data read

  2645.   *         is corresponding to previous ADC conversion start, independently

  2646.   *         of delay during which ADC was idle.

  2647.   *         Therefore, the ADC conversion data may be outdated: does not

  2648.   *         correspond to the current voltage level on the selected

  2649.   *         ADC channel.

  2650.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2651.   *         ADC state:

  2652.   *         ADC must be disabled or enabled without conversion on going

  2653.   *         on either groups regular or injected.

  2654.   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode

  2655.   * @param  ADCx ADC instance

  2656.   * @param  LowPowerMode This parameter can be one of the following values:

  2657.   *         @arg @ref LL_ADC_LP_MODE_NONE

  2658.   *         @arg @ref LL_ADC_LP_AUTOWAIT

  2659.   * @retval None

  2660.   */

  2661. __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)

  2662. {

  2663.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);

  2664. }

  2665. 

  2666. /**

  2667.   * @brief  Get ADC low power mode:

  2668.   * @note   Description of ADC low power modes:

  2669.   *         - ADC low power mode "auto wait": Dynamic low power mode,

  2670.   *           ADC conversions occurrences are limited to the minimum necessary

  2671.   *           in order to reduce power consumption.

  2672.   *           New ADC conversion starts only when the previous

  2673.   *           unitary conversion data (for ADC group regular)

  2674.   *           or previous sequence conversions data (for ADC group injected)

  2675.   *           has been retrieved by user software.

  2676.   *           In the meantime, ADC remains idle: does not performs any

  2677.   *           other conversion.

  2678.   *           This mode allows to automatically adapt the ADC conversions

  2679.   *           triggers to the speed of the software that reads the data.

  2680.   *           Moreover, this avoids risk of overrun for low frequency

  2681.   *           applications.

  2682.   *           How to use this low power mode:

  2683.   *           - Do not use with interruption or DMA since these modes

  2684.   *             have to clear immediately the EOC flag to free the

  2685.   *             IRQ vector sequencer.

  2686.   *           - Do use with polling: 1. Start conversion,

  2687.   *             2. Later on, when conversion data is needed: poll for end of

  2688.   *             conversion  to ensure that conversion is completed and

  2689.   *             retrieve ADC conversion data. This will trig another

  2690.   *             ADC conversion start.

  2691.   *         - ADC low power mode "auto power-off" (feature available on

  2692.   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):

  2693.   *           the ADC automatically powers-off after a conversion and

  2694.   *           automatically wakes up when a new conversion is triggered

  2695.   *           (with startup time between trigger and start of sampling).

  2696.   *           This feature can be combined with low power mode "auto wait".

  2697.   * @note   With ADC low power mode "auto wait", the ADC conversion data read

  2698.   *         is corresponding to previous ADC conversion start, independently

  2699.   *         of delay during which ADC was idle.

  2700.   *         Therefore, the ADC conversion data may be outdated: does not

  2701.   *         correspond to the current voltage level on the selected

  2702.   *         ADC channel.

  2703.   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode

  2704.   * @param  ADCx ADC instance

  2705.   * @retval Returned value can be one of the following values:

  2706.   *         @arg @ref LL_ADC_LP_MODE_NONE

  2707.   *         @arg @ref LL_ADC_LP_AUTOWAIT

  2708.   */

  2709. __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)

  2710. {

  2711.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));

  2712. }

  2713. 

  2714. /**

  2715.   * @brief  Set ADC selected offset number 1, 2, 3 or 4.

  2716.   * @note   This function set the 2 items of offset configuration:

  2717.   *         - ADC channel to which the offset programmed will be applied

  2718.   *           (independently of channel mapped on ADC group regular

  2719.   *           or group injected)

  2720.   *         - Offset level (offset to be subtracted from the raw

  2721.   *           converted data).

  2722.   * @note   Caution: Offset format is dependent to ADC resolution:

  2723.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  2724.   *         are set to 0.

  2725.   * @note   This function enables the offset, by default. It can be forced

  2726.   *         to disable state using function LL_ADC_SetOffsetState().

  2727.   * @note   If a channel is mapped on several offsets numbers, only the offset

  2728.   *         with the lowest value is considered for the subtraction.

  2729.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2730.   *         ADC state:

  2731.   *         ADC must be disabled or enabled without conversion on going

  2732.   *         on either groups regular or injected.

  2733.   * @note   On STM32H7, some fast channels are available: fast analog inputs

  2734.   *         coming from GPIO pads (ADC_IN0..5).

  2735.   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n

  2736.   *         OFR1     OFFSET1        LL_ADC_SetOffset\n

  2737.   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n

  2738.   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n

  2739.   *         OFR2     OFFSET2        LL_ADC_SetOffset\n

  2740.   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n

  2741.   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n

  2742.   *         OFR3     OFFSET3        LL_ADC_SetOffset\n

  2743.   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n

  2744.   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n

  2745.   *         OFR4     OFFSET4        LL_ADC_SetOffset\n

  2746.   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset

  2747.   * @param  ADCx ADC instance

  2748.   * @param  Offsety This parameter can be one of the following values:

  2749.   *         @arg @ref LL_ADC_OFFSET_1

  2750.   *         @arg @ref LL_ADC_OFFSET_2

  2751.   *         @arg @ref LL_ADC_OFFSET_3

  2752.   *         @arg @ref LL_ADC_OFFSET_4

  2753.   * @param  Channel This parameter can be one of the following values:

  2754.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  2755.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  2756.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  2757.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  2758.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  2759.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  2760.   *         @arg @ref LL_ADC_CHANNEL_6

  2761.   *         @arg @ref LL_ADC_CHANNEL_7

  2762.   *         @arg @ref LL_ADC_CHANNEL_8

  2763.   *         @arg @ref LL_ADC_CHANNEL_9

  2764.   *         @arg @ref LL_ADC_CHANNEL_10

  2765.   *         @arg @ref LL_ADC_CHANNEL_11

  2766.   *         @arg @ref LL_ADC_CHANNEL_12

  2767.   *         @arg @ref LL_ADC_CHANNEL_13

  2768.   *         @arg @ref LL_ADC_CHANNEL_14

  2769.   *         @arg @ref LL_ADC_CHANNEL_15

  2770.   *         @arg @ref LL_ADC_CHANNEL_16

  2771.   *         @arg @ref LL_ADC_CHANNEL_17

  2772.   *         @arg @ref LL_ADC_CHANNEL_18

  2773.   *         @arg @ref LL_ADC_CHANNEL_19

  2774.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  2775.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  2776.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  2777.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  2778.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  2779.   *

  2780.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  2781.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  2782.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  2783.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  2784.   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF

  2785.   * @retval None

  2786.   */

  2787. __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)

  2788. {

  2789.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  2790. 

  2791.   MODIFY_REG(*preg,

  2792.              ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,

  2793.              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);

  2794. }

  2795. 

  2796. /**

  2797.   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

  2798.   *         Channel to which the offset programmed will be applied

  2799.   *         (independently of channel mapped on ADC group regular

  2800.   *         or group injected)

  2801.   * @note   Usage of the returned channel number:

  2802.   *         - To reinject this channel into another function LL_ADC_xxx:

  2803.   *           the returned channel number is only partly formatted on definition

  2804.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  2805.   *           with parts of literals LL_ADC_CHANNEL_x or using

  2806.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  2807.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  2808.   *           as parameter for another function.

  2809.   *         - To get the channel number in decimal format:

  2810.   *           process the returned value with the helper macro

  2811.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  2812.   * @note   On STM32H7, some fast channels are available: fast analog inputs

  2813.   *         coming from GPIO pads (ADC_IN0..5).

  2814.   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n

  2815.   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n

  2816.   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n

  2817.   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel

  2818.   * @param  ADCx ADC instance

  2819.   * @param  Offsety This parameter can be one of the following values:

  2820.   *         @arg @ref LL_ADC_OFFSET_1

  2821.   *         @arg @ref LL_ADC_OFFSET_2

  2822.   *         @arg @ref LL_ADC_OFFSET_3

  2823.   *         @arg @ref LL_ADC_OFFSET_4

  2824.   * @retval Returned value can be one of the following values:

  2825.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  2826.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  2827.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  2828.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  2829.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  2830.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  2831.   *         @arg @ref LL_ADC_CHANNEL_6

  2832.   *         @arg @ref LL_ADC_CHANNEL_7

  2833.   *         @arg @ref LL_ADC_CHANNEL_8

  2834.   *         @arg @ref LL_ADC_CHANNEL_9

  2835.   *         @arg @ref LL_ADC_CHANNEL_10

  2836.   *         @arg @ref LL_ADC_CHANNEL_11

  2837.   *         @arg @ref LL_ADC_CHANNEL_12

  2838.   *         @arg @ref LL_ADC_CHANNEL_13

  2839.   *         @arg @ref LL_ADC_CHANNEL_14

  2840.   *         @arg @ref LL_ADC_CHANNEL_15

  2841.   *         @arg @ref LL_ADC_CHANNEL_16

  2842.   *         @arg @ref LL_ADC_CHANNEL_17

  2843.   *         @arg @ref LL_ADC_CHANNEL_18

  2844.   *         @arg @ref LL_ADC_CHANNEL_19

  2845.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  2846.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  2847.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  2848.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  2849.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  2850.   *

  2851.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  2852.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  2853.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  2854.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  2855.   *         (1, 2) For ADC channel read back from ADC register,

  2856.   *                comparison with internal channel parameter to be done

  2857.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  2858.   */

  2859. __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)

  2860. {

  2861.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  2862. 

  2863.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);

  2864. }

  2865. 

  2866. /**

  2867.   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

  2868.   *         Offset level (offset to be subtracted from the raw

  2869.   *         converted data).

  2870.   * @note   Caution: Offset format is dependent to ADC resolution:

  2871.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  2872.   *         are set to 0.

  2873.   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n

  2874.   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n

  2875.   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n

  2876.   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel

  2877.   * @param  ADCx ADC instance

  2878.   * @param  Offsety This parameter can be one of the following values:

  2879.   *         @arg @ref LL_ADC_OFFSET_1

  2880.   *         @arg @ref LL_ADC_OFFSET_2

  2881.   *         @arg @ref LL_ADC_OFFSET_3

  2882.   *         @arg @ref LL_ADC_OFFSET_4

  2883.   * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF

  2884.   */

  2885. __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)

  2886. {

  2887.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  2888. 

  2889.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);

  2890. }

  2891. 

  2892. 

  2893. /**

  2894.   * @brief  Set data right shift for the ADC selected offset number 1, 2, 3 or 4:

  2895.   *         signed offset saturation if enabled or disabled.

  2896.   * @rmtoll CFGR2    RSHIFT          LL_ADC_SetDataRightShift\n

  2897.   * @param  ADCx ADC instance

  2898.   * @param  Offsety This parameter can be one of the following values:

  2899.   *         @arg @ref LL_ADC_OFFSET_1

  2900.   *         @arg @ref LL_ADC_OFFSET_2

  2901.   *         @arg @ref LL_ADC_OFFSET_3

  2902.   *         @arg @ref LL_ADC_OFFSET_4

  2903.   * @param  RigthShift This parameter can be one of the following values:

  2904.   *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE

  2905.   *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE

  2906.   * @retval Returned None

  2907.   */

  2908. __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)

  2909. {

  2910.   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));

  2911. }

  2912. 

  2913. /**

  2914.   * @brief  Get data right shift for the ADC selected offset number 1, 2, 3 or 4:

  2915.   *         signed offset saturation if enabled or disabled.

  2916.   * @rmtoll CFGR2    RSHIFT          LL_ADC_GetDataRightShift\n

  2917.   * @param  ADCx ADC instance

  2918.   * @param  Offsety This parameter can be one of the following values:

  2919.   *         @arg @ref LL_ADC_OFFSET_1

  2920.   *         @arg @ref LL_ADC_OFFSET_2

  2921.   *         @arg @ref LL_ADC_OFFSET_3

  2922.   *         @arg @ref LL_ADC_OFFSET_4

  2923.   * @retval Returned value can be one of the following values:

  2924.   *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE

  2925.   *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE

  2926.   */

  2927. __STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)

  2928. {

  2929.   return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));

  2930. }

  2931. 

  2932. /**

  2933.   * @brief  Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:

  2934.   *         signed offset saturation if enabled or disabled.

  2935.   * @rmtoll OFR1     SSATE          LL_ADC_SetOffsetSignedSaturation\n

  2936.   *         OFR2     SSATE          LL_ADC_SetOffsetSignedSaturation\n

  2937.   *         OFR3     SSATE          LL_ADC_SetOffsetSignedSaturation\n

  2938.   *         OFR4     SSATE          LL_ADC_SetOffsetSignedSaturation

  2939.   * @param  ADCx ADC instance

  2940.   * @param  Offsety This parameter can be one of the following values:

  2941.   *         @arg @ref LL_ADC_OFFSET_1

  2942.   *         @arg @ref LL_ADC_OFFSET_2

  2943.   *         @arg @ref LL_ADC_OFFSET_3

  2944.   *         @arg @ref LL_ADC_OFFSET_4

  2945.   * @param  OffsetSignedSaturation This parameter can be one of the following values:

  2946.   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE

  2947.   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE

  2948.   * @retval Returned None

  2949.   */

  2950. __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)

  2951. {

  2952.    register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  2953.    MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);

  2954. }

  2955. 

  2956. /**

  2957.   * @brief  Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:

  2958.   *         signed offset saturation if enabled or disabled.

  2959.   * @rmtoll OFR1     SSATE          LL_ADC_GetOffsetSignedSaturation\n

  2960.   *         OFR2     SSATE          LL_ADC_GetOffsetSignedSaturation\n

  2961.   *         OFR3     SSATE          LL_ADC_GetOffsetSignedSaturation\n

  2962.   *         OFR4     SSATE          LL_ADC_GetOffsetSignedSaturation

  2963.   * @param  ADCx ADC instance

  2964.   * @param  Offsety This parameter can be one of the following values:

  2965.   *         @arg @ref LL_ADC_OFFSET_1

  2966.   *         @arg @ref LL_ADC_OFFSET_2

  2967.   *         @arg @ref LL_ADC_OFFSET_3

  2968.   *         @arg @ref LL_ADC_OFFSET_4

  2969.   * @retval Returned value can be one of the following values:

  2970.   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE

  2971.   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE

  2972.   */

  2973. __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)

  2974. {

  2975.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  2976.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);

  2977. }

  2978. 

  2979. /**

  2980.   * @}

  2981.   */

  2982. 

  2983. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular

  2984.   * @{

  2985.   */

  2986. 

  2987. /**

  2988.   * @brief  Set ADC group regular conversion trigger source:

  2989.   *         internal (SW start) or from external peripheral (timer event,

  2990.   *         external interrupt line).

  2991.   * @note   On this STM32 serie, setting trigger source to external trigger

  2992.   *         also set trigger polarity to rising edge

  2993.   *         (default setting for compatibility with some ADC on other

  2994.   *         STM32 families having this setting set by HW default value).

  2995.   *         In case of need to modify trigger edge, use

  2996.   *         function @ref LL_ADC_REG_SetTriggerEdge().

  2997.   * @note   Availability of parameters of trigger sources from timer

  2998.   *         depends on timers availability on the selected device.

  2999.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3000.   *         ADC state:

  3001.   *         ADC must be disabled or enabled without conversion on going

  3002.   *         on group regular.

  3003.   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n

  3004.   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource

  3005.   * @param  ADCx ADC instance

  3006.   * @param  TriggerSource This parameter can be one of the following values:

  3007.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  3008.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1

  3009.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2

  3010.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3

  3011.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  3012.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO

  3013.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

  3014.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  3015.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO

  3016.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2

  3017.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO

  3018.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

  3019.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  3020.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

  3021.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

  3022.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO

  3023.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4

  3024.   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1

  3025.   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3

  3026.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT

  3027.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT

  3028.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT

  3029.   * @retval None

  3030.   */

  3031. __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  3032. {

  3033.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);

  3034. }

  3035. 

  3036. /**

  3037.   * @brief  Get ADC group regular conversion trigger source:

  3038.   *         internal (SW start) or from external peripheral (timer event,

  3039.   *         external interrupt line).

  3040.   * @note   To determine whether group regular trigger source is

  3041.   *         internal (SW start) or external, without detail

  3042.   *         of which peripheral is selected as external trigger,

  3043.   *         (equivalent to

  3044.   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")

  3045.   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.

  3046.   * @note   Availability of parameters of trigger sources from timer

  3047.   *         depends on timers availability on the selected device.

  3048.   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n

  3049.   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource

  3050.   * @param  ADCx ADC instance

  3051.   * @retval Returned value can be one of the following values:

  3052.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  3053.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1

  3054.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2

  3055.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3

  3056.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  3057.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO

  3058.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

  3059.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  3060.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO

  3061.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2

  3062.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO

  3063.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

  3064.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  3065.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

  3066.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

  3067.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO

  3068.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4

  3069.   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1

  3070.   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3

  3071.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT

  3072.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT

  3073.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT

  3074.   */

  3075. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)

  3076. {

  3077.   register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);

  3078. 

  3079.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  3080.   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */

  3081.   register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));

  3082. 

  3083.   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */

  3084.   /* to match with triggers literals definition.                              */

  3085.   return ((TriggerSource

  3086.            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)

  3087.           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)

  3088.          );

  3089. }

  3090. 

  3091. /**

  3092.   * @brief  Get ADC group regular conversion trigger source internal (SW start)

  3093.   *         or external.

  3094.   * @note   In case of group regular trigger source set to external trigger,

  3095.   *         to determine which peripheral is selected as external trigger,

  3096.   *         use function @ref LL_ADC_REG_GetTriggerSource().

  3097.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart

  3098.   * @param  ADCx ADC instance

  3099.   * @retval Value "0" if trigger source external trigger

  3100.   *         Value "1" if trigger source SW start.

  3101.   */

  3102. __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  3103. {

  3104.   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);

  3105. }

  3106. 

  3107. /**

  3108.   * @brief  Set ADC group regular conversion trigger polarity.

  3109.   * @note   Applicable only for trigger source set to external trigger.

  3110.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3111.   *         ADC state:

  3112.   *         ADC must be disabled or enabled without conversion on going

  3113.   *         on group regular.

  3114.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge

  3115.   * @param  ADCx ADC instance

  3116.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  3117.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  3118.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  3119.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  3120.   * @retval None

  3121.   */

  3122. __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  3123. {

  3124.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);

  3125. }

  3126. 

  3127. /**

  3128.   * @brief  Get ADC group regular conversion trigger polarity.

  3129.   * @note   Applicable only for trigger source set to external trigger.

  3130.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge

  3131.   * @param  ADCx ADC instance

  3132.   * @retval Returned value can be one of the following values:

  3133.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  3134.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  3135.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  3136.   */

  3137. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)

  3138. {

  3139.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));

  3140. }

  3141. 

  3142. /**

  3143.   * @brief  Set ADC group regular sequencer length and scan direction.

  3144.   * @note   Description of ADC group regular sequencer features:

  3145.   *         - For devices with sequencer fully configurable

  3146.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  3147.   *           sequencer length and each rank affectation to a channel

  3148.   *           are configurable.

  3149.   *           This function performs configuration of:

  3150.   *           - Sequence length: Number of ranks in the scan sequence.

  3151.   *           - Sequence direction: Unless specified in parameters, sequencer

  3152.   *             scan direction is forward (from rank 1 to rank n).

  3153.   *           Sequencer ranks are selected using

  3154.   *           function "LL_ADC_REG_SetSequencerRanks()".

  3155.   *         - For devices with sequencer not fully configurable

  3156.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  3157.   *           sequencer length and each rank affectation to a channel

  3158.   *           are defined by channel number.

  3159.   *           This function performs configuration of:

  3160.   *           - Sequence length: Number of ranks in the scan sequence is

  3161.   *             defined by number of channels set in the sequence,

  3162.   *             rank of each channel is fixed by channel HW number.

  3163.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  3164.   *           - Sequence direction: Unless specified in parameters, sequencer

  3165.   *             scan direction is forward (from lowest channel number to

  3166.   *             highest channel number).

  3167.   *           Sequencer ranks are selected using

  3168.   *           function "LL_ADC_REG_SetSequencerChannels()".

  3169.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3170.   *         ADC conversion on only 1 channel.

  3171.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3172.   *         ADC state:

  3173.   *         ADC must be disabled or enabled without conversion on going

  3174.   *         on group regular.

  3175.   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength

  3176.   * @param  ADCx ADC instance

  3177.   * @param  SequencerNbRanks This parameter can be one of the following values:

  3178.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  3179.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  3180.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  3181.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  3182.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  3183.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  3184.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  3185.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  3186.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

  3187.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

  3188.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

  3189.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

  3190.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

  3191.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

  3192.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

  3193.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  3194.   * @retval None

  3195.   */

  3196. __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  3197. {

  3198.   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);

  3199. }

  3200. 

  3201. /**

  3202.   * @brief  Get ADC group regular sequencer length and scan direction.

  3203.   * @note   Description of ADC group regular sequencer features:

  3204.   *         - For devices with sequencer fully configurable

  3205.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  3206.   *           sequencer length and each rank affectation to a channel

  3207.   *           are configurable.

  3208.   *           This function retrieves:

  3209.   *           - Sequence length: Number of ranks in the scan sequence.

  3210.   *           - Sequence direction: Unless specified in parameters, sequencer

  3211.   *             scan direction is forward (from rank 1 to rank n).

  3212.   *           Sequencer ranks are selected using

  3213.   *           function "LL_ADC_REG_SetSequencerRanks()".

  3214.   *         - For devices with sequencer not fully configurable

  3215.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  3216.   *           sequencer length and each rank affectation to a channel

  3217.   *           are defined by channel number.

  3218.   *           This function retrieves:

  3219.   *           - Sequence length: Number of ranks in the scan sequence is

  3220.   *             defined by number of channels set in the sequence,

  3221.   *             rank of each channel is fixed by channel HW number.

  3222.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  3223.   *           - Sequence direction: Unless specified in parameters, sequencer

  3224.   *             scan direction is forward (from lowest channel number to

  3225.   *             highest channel number).

  3226.   *           Sequencer ranks are selected using

  3227.   *           function "LL_ADC_REG_SetSequencerChannels()".

  3228.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3229.   *         ADC conversion on only 1 channel.

  3230.   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength

  3231.   * @param  ADCx ADC instance

  3232.   * @retval Returned value can be one of the following values:

  3233.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  3234.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  3235.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  3236.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  3237.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  3238.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  3239.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  3240.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  3241.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

  3242.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

  3243.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

  3244.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

  3245.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

  3246.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

  3247.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

  3248.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  3249.   */

  3250. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)

  3251. {

  3252.   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));

  3253. }

  3254. 

  3255. /**

  3256.   * @brief  Set ADC group regular sequencer discontinuous mode:

  3257.   *         sequence subdivided and scan conversions interrupted every selected

  3258.   *         number of ranks.

  3259.   * @note   It is not possible to enable both ADC group regular

  3260.   *         continuous mode and sequencer discontinuous mode.

  3261.   * @note   It is not possible to enable both ADC auto-injected mode

  3262.   *         and ADC group regular sequencer discontinuous mode.

  3263.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3264.   *         ADC state:

  3265.   *         ADC must be disabled or enabled without conversion on going

  3266.   *         on group regular.

  3267.   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n

  3268.   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont

  3269.   * @param  ADCx ADC instance

  3270.   * @param  SeqDiscont This parameter can be one of the following values:

  3271.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  3272.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  3273.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

  3274.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

  3275.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

  3276.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

  3277.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

  3278.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

  3279.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

  3280.   * @retval None

  3281.   */

  3282. __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  3283. {

  3284.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);

  3285. }

  3286. 

  3287. /**

  3288.   * @brief  Get ADC group regular sequencer discontinuous mode:

  3289.   *         sequence subdivided and scan conversions interrupted every selected

  3290.   *         number of ranks.

  3291.   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n

  3292.   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont

  3293.   * @param  ADCx ADC instance

  3294.   * @retval Returned value can be one of the following values:

  3295.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  3296.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  3297.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

  3298.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

  3299.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

  3300.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

  3301.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

  3302.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

  3303.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

  3304.   */

  3305. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)

  3306. {

  3307.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));

  3308. }

  3309. 

  3310. /**

  3311.   * @brief  Set ADC group regular sequence: channel on the selected

  3312.   *         scan sequence rank.

  3313.   * @note   This function performs configuration of:

  3314.   *         - Channels ordering into each rank of scan sequence:

  3315.   *           whatever channel can be placed into whatever rank.

  3316.   * @note   On this STM32 serie, ADC group regular sequencer is

  3317.   *         fully configurable: sequencer length and each rank

  3318.   *         affectation to a channel are configurable.

  3319.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  3320.   * @note   Depending on devices and packages, some channels may not be available.

  3321.   *         Refer to device datasheet for channels availability.

  3322.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  3323.   *         TempSensor, ...), measurement paths to internal channels must be

  3324.   *         enabled separately.

  3325.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  3326.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3327.   *         ADC state:

  3328.   *         ADC must be disabled or enabled without conversion on going

  3329.   *         on group regular.

  3330.   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n

  3331.   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n

  3332.   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n

  3333.   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n

  3334.   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n

  3335.   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n

  3336.   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n

  3337.   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n

  3338.   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n

  3339.   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n

  3340.   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n

  3341.   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n

  3342.   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n

  3343.   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n

  3344.   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n

  3345.   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks

  3346.   * @param  ADCx ADC instance

  3347.   * @param  Rank This parameter can be one of the following values:

  3348.   *         @arg @ref LL_ADC_REG_RANK_1

  3349.   *         @arg @ref LL_ADC_REG_RANK_2

  3350.   *         @arg @ref LL_ADC_REG_RANK_3

  3351.   *         @arg @ref LL_ADC_REG_RANK_4

  3352.   *         @arg @ref LL_ADC_REG_RANK_5

  3353.   *         @arg @ref LL_ADC_REG_RANK_6

  3354.   *         @arg @ref LL_ADC_REG_RANK_7

  3355.   *         @arg @ref LL_ADC_REG_RANK_8

  3356.   *         @arg @ref LL_ADC_REG_RANK_9

  3357.   *         @arg @ref LL_ADC_REG_RANK_10

  3358.   *         @arg @ref LL_ADC_REG_RANK_11

  3359.   *         @arg @ref LL_ADC_REG_RANK_12

  3360.   *         @arg @ref LL_ADC_REG_RANK_13

  3361.   *         @arg @ref LL_ADC_REG_RANK_14

  3362.   *         @arg @ref LL_ADC_REG_RANK_15

  3363.   *         @arg @ref LL_ADC_REG_RANK_16

  3364.   * @param  Channel This parameter can be one of the following values:

  3365.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  3366.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  3367.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  3368.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  3369.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  3370.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  3371.   *         @arg @ref LL_ADC_CHANNEL_6

  3372.   *         @arg @ref LL_ADC_CHANNEL_7

  3373.   *         @arg @ref LL_ADC_CHANNEL_8

  3374.   *         @arg @ref LL_ADC_CHANNEL_9

  3375.   *         @arg @ref LL_ADC_CHANNEL_10

  3376.   *         @arg @ref LL_ADC_CHANNEL_11

  3377.   *         @arg @ref LL_ADC_CHANNEL_12

  3378.   *         @arg @ref LL_ADC_CHANNEL_13

  3379.   *         @arg @ref LL_ADC_CHANNEL_14

  3380.   *         @arg @ref LL_ADC_CHANNEL_15

  3381.   *         @arg @ref LL_ADC_CHANNEL_16

  3382.   *         @arg @ref LL_ADC_CHANNEL_17

  3383.   *         @arg @ref LL_ADC_CHANNEL_18

  3384.   *         @arg @ref LL_ADC_CHANNEL_19

  3385.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3386.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  3387.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3388.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  3389.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  3390.   *

  3391.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  3392.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  3393.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  3394.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  3395.   * @retval None

  3396.   */

  3397. __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  3398. {

  3399.   /* Set bits with content of parameter "Channel" with bits position          */

  3400.   /* in register and register position depending on parameter "Rank".         */

  3401.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  3402.   /* other bits reserved for other purpose.                                   */

  3403.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));

  3404. 

  3405.   MODIFY_REG(*preg,

  3406.              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),

  3407.              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));

  3408. }

  3409. 

  3410. /**

  3411.   * @brief  Get ADC group regular sequence: channel on the selected

  3412.   *         scan sequence rank.

  3413.   * @note   On this STM32 serie, ADC group regular sequencer is

  3414.   *         fully configurable: sequencer length and each rank

  3415.   *         affectation to a channel are configurable.

  3416.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  3417.   * @note   Depending on devices and packages, some channels may not be available.

  3418.   *         Refer to device datasheet for channels availability.

  3419.   * @note   Usage of the returned channel number:

  3420.   *         - To reinject this channel into another function LL_ADC_xxx:

  3421.   *           the returned channel number is only partly formatted on definition

  3422.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  3423.   *           with parts of literals LL_ADC_CHANNEL_x or using

  3424.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3425.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3426.   *           as parameter for another function.

  3427.   *         - To get the channel number in decimal format:

  3428.   *           process the returned value with the helper macro

  3429.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3430.   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n

  3431.   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n

  3432.   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n

  3433.   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n

  3434.   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n

  3435.   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n

  3436.   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n

  3437.   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n

  3438.   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n

  3439.   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n

  3440.   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n

  3441.   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n

  3442.   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n

  3443.   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n

  3444.   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n

  3445.   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks

  3446.   * @param  ADCx ADC instance

  3447.   * @param  Rank This parameter can be one of the following values:

  3448.   *         @arg @ref LL_ADC_REG_RANK_1

  3449.   *         @arg @ref LL_ADC_REG_RANK_2

  3450.   *         @arg @ref LL_ADC_REG_RANK_3

  3451.   *         @arg @ref LL_ADC_REG_RANK_4

  3452.   *         @arg @ref LL_ADC_REG_RANK_5

  3453.   *         @arg @ref LL_ADC_REG_RANK_6

  3454.   *         @arg @ref LL_ADC_REG_RANK_7

  3455.   *         @arg @ref LL_ADC_REG_RANK_8

  3456.   *         @arg @ref LL_ADC_REG_RANK_9

  3457.   *         @arg @ref LL_ADC_REG_RANK_10

  3458.   *         @arg @ref LL_ADC_REG_RANK_11

  3459.   *         @arg @ref LL_ADC_REG_RANK_12

  3460.   *         @arg @ref LL_ADC_REG_RANK_13

  3461.   *         @arg @ref LL_ADC_REG_RANK_14

  3462.   *         @arg @ref LL_ADC_REG_RANK_15

  3463.   *         @arg @ref LL_ADC_REG_RANK_16

  3464.   * @retval Returned value can be one of the following values:

  3465.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  3466.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  3467.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  3468.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  3469.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  3470.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  3471.   *         @arg @ref LL_ADC_CHANNEL_6

  3472.   *         @arg @ref LL_ADC_CHANNEL_7

  3473.   *         @arg @ref LL_ADC_CHANNEL_8

  3474.   *         @arg @ref LL_ADC_CHANNEL_9

  3475.   *         @arg @ref LL_ADC_CHANNEL_10

  3476.   *         @arg @ref LL_ADC_CHANNEL_11

  3477.   *         @arg @ref LL_ADC_CHANNEL_12

  3478.   *         @arg @ref LL_ADC_CHANNEL_13

  3479.   *         @arg @ref LL_ADC_CHANNEL_14

  3480.   *         @arg @ref LL_ADC_CHANNEL_15

  3481.   *         @arg @ref LL_ADC_CHANNEL_16

  3482.   *         @arg @ref LL_ADC_CHANNEL_17

  3483.   *         @arg @ref LL_ADC_CHANNEL_18

  3484.   *         @arg @ref LL_ADC_CHANNEL_19

  3485.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3486.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  3487.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3488.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  3489.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  3490.   *

  3491.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  3492.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  3493.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  3494.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  3495.   *         (1, 2) For ADC channel read back from ADC register,

  3496.   *                comparison with internal channel parameter to be done

  3497.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  3498.   */

  3499. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  3500. {

  3501.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));

  3502. 

  3503.   return (uint32_t) ((READ_BIT(*preg,

  3504.                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))

  3505.                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

  3506.                     );

  3507. }

  3508. 

  3509. /**

  3510.   * @brief  Set ADC continuous conversion mode on ADC group regular.

  3511.   * @note   Description of ADC continuous conversion mode:

  3512.   *         - single mode: one conversion per trigger

  3513.   *         - continuous mode: after the first trigger, following

  3514.   *           conversions launched successively automatically.

  3515.   * @note   It is not possible to enable both ADC group regular

  3516.   *         continuous mode and sequencer discontinuous mode.

  3517.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3518.   *         ADC state:

  3519.   *         ADC must be disabled or enabled without conversion on going

  3520.   *         on group regular.

  3521.   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode

  3522.   * @param  ADCx ADC instance

  3523.   * @param  Continuous This parameter can be one of the following values:

  3524.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  3525.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  3526.   * @retval None

  3527.   */

  3528. __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)

  3529. {

  3530.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);

  3531. }

  3532. 

  3533. /**

  3534.   * @brief  Get ADC continuous conversion mode on ADC group regular.

  3535.   * @note   Description of ADC continuous conversion mode:

  3536.   *         - single mode: one conversion per trigger

  3537.   *         - continuous mode: after the first trigger, following

  3538.   *           conversions launched successively automatically.

  3539.   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode

  3540.   * @param  ADCx ADC instance

  3541.   * @retval Returned value can be one of the following values:

  3542.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  3543.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  3544.   */

  3545. __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)

  3546. {

  3547.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));

  3548. }

  3549. /**

  3550.   * @brief  Set ADC data transfer mode

  3551.   * @note   Conversion data can be either:

  3552.   *            - Available in Data Register

  3553.   *            - Transfered by DMA in one shot mode

  3554.   *            - Transfered by DMA in circular mode

  3555.   *            - Transfered to DFSDM data register

  3556.   * @rmtoll CFGR     DMNGT           LL_ADC_REG_SetDataTransferMode

  3557.   * @param  ADCx ADC instance

  3558.   * @param  DataTransferMode Select Data Management configuration

  3559.   * @retval None

  3560.   */

  3561. __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)

  3562. {

  3563.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);

  3564. }

  3565. 

  3566. 

  3567. /**

  3568.   * @brief  Get ADC data transfer mode

  3569.   * @note   Conversion data can be either:

  3570.   *            - Available in Data Register

  3571.   *            - Transfered by DMA in one shot mode

  3572.   *            - Transfered by DMA in circular mode

  3573.   *            - Transfered to DFSDM data register

  3574.   * @rmtoll CFGR     DMNGT           LL_ADC_REG_GetDataTransferMode

  3575.   * @param  ADCx ADC instance

  3576.   * @retval Returned value can be one of the following values:

  3577.   *         @arg @ref LL_ADC_REG_DR_TRANSFER

  3578.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  3579.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  3580.   *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER

  3581.   */

  3582. __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)

  3583. {

  3584.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));

  3585. }

  3586. 

  3587. 

  3588. /**

  3589.   * @brief  Set ADC group regular behavior in case of overrun:

  3590.   *         data preserved or overwritten.

  3591.   * @note   Compatibility with devices without feature overrun:

  3592.   *         other devices without this feature have a behavior

  3593.   *         equivalent to data overwritten.

  3594.   *         The default setting of overrun is data preserved.

  3595.   *         Therefore, for compatibility with all devices, parameter

  3596.   *         overrun should be set to data overwritten.

  3597.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3598.   *         ADC state:

  3599.   *         ADC must be disabled or enabled without conversion on going

  3600.   *         on group regular.

  3601.   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun

  3602.   * @param  ADCx ADC instance

  3603.   * @param  Overrun This parameter can be one of the following values:

  3604.   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED

  3605.   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN

  3606.   * @retval None

  3607.   */

  3608. __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)

  3609. {

  3610.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);

  3611. }

  3612. 

  3613. /**

  3614.   * @brief  Get ADC group regular behavior in case of overrun:

  3615.   *         data preserved or overwritten.

  3616.   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun

  3617.   * @param  ADCx ADC instance

  3618.   * @retval Returned value can be one of the following values:

  3619.   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED

  3620.   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN

  3621.   */

  3622. __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)

  3623. {

  3624.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));

  3625. }

  3626. 

  3627. /**

  3628.   * @}

  3629.   */

  3630. 

  3631. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected

  3632.   * @{

  3633.   */

  3634. 

  3635. /**

  3636.   * @brief  Set ADC group injected conversion trigger source:

  3637.   *         internal (SW start) or from external peripheral (timer event,

  3638.   *         external interrupt line).

  3639.   * @note   On this STM32 serie, setting trigger source to external trigger

  3640.   *         also set trigger polarity to rising edge

  3641.   *         (default setting for compatibility with some ADC on other

  3642.   *         STM32 families having this setting set by HW default value).

  3643.   *         In case of need to modify trigger edge, use

  3644.   *         function @ref LL_ADC_INJ_SetTriggerEdge().

  3645.   * @note   Availability of parameters of trigger sources from timer

  3646.   *         depends on timers availability on the selected device.

  3647.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3648.   *         ADC state:

  3649.   *         ADC must not be disabled. Can be enabled with or without conversion

  3650.   *         on going on either groups regular or injected.

  3651.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n

  3652.   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource

  3653.   * @param  ADCx ADC instance

  3654.   * @param  TriggerSource This parameter can be one of the following values:

  3655.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  3656.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  3657.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  3658.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  3659.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  3660.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  3661.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  3662.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  3663.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

  3664.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  3665.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

  3666.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

  3667.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

  3668.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

  3669.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

  3670.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

  3671.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

  3672.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

  3673.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

  3674.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

  3675.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

  3676.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

  3677.   * @retval None

  3678.   */

  3679. __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  3680. {

  3681.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);

  3682. }

  3683. 

  3684. /**

  3685.   * @brief  Get ADC group injected conversion trigger source:

  3686.   *         internal (SW start) or from external peripheral (timer event,

  3687.   *         external interrupt line).

  3688.   * @note   To determine whether group injected trigger source is

  3689.   *         internal (SW start) or external, without detail

  3690.   *         of which peripheral is selected as external trigger,

  3691.   *         (equivalent to

  3692.   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")

  3693.   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.

  3694.   * @note   Availability of parameters of trigger sources from timer

  3695.   *         depends on timers availability on the selected device.

  3696.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n

  3697.   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource

  3698.   * @param  ADCx ADC instance

  3699.   * @retval Returned value can be one of the following values:

  3700.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  3701.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  3702.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  3703.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  3704.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  3705.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  3706.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  3707.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  3708.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

  3709.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  3710.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

  3711.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

  3712.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

  3713.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

  3714.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

  3715.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

  3716.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

  3717.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

  3718.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

  3719.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

  3720.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

  3721.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

  3722.   */

  3723. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)

  3724. {

  3725.   register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);

  3726. 

  3727.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  3728.   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */

  3729.   register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));

  3730. 

  3731.   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */

  3732.   /* to match with triggers literals definition.                              */

  3733.   return ((TriggerSource

  3734.            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)

  3735.           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)

  3736.          );

  3737. }

  3738. 

  3739. /**

  3740.   * @brief  Get ADC group injected conversion trigger source internal (SW start)

  3741.             or external

  3742.   * @note   In case of group injected trigger source set to external trigger,

  3743.   *         to determine which peripheral is selected as external trigger,

  3744.   *         use function @ref LL_ADC_INJ_GetTriggerSource.

  3745.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart

  3746.   * @param  ADCx ADC instance

  3747.   * @retval Value "0" if trigger source external trigger

  3748.   *         Value "1" if trigger source SW start.

  3749.   */

  3750. __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  3751. {

  3752.   return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);

  3753. }

  3754. 

  3755. /**

  3756.   * @brief  Set ADC group injected conversion trigger polarity.

  3757.   *         Applicable only for trigger source set to external trigger.

  3758.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3759.   *         ADC state:

  3760.   *         ADC must not be disabled. Can be enabled with or without conversion

  3761.   *         on going on either groups regular or injected.

  3762.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge

  3763.   * @param  ADCx ADC instance

  3764.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  3765.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  3766.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  3767.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  3768.   * @retval None

  3769.   */

  3770. __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  3771. {

  3772.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);

  3773. }

  3774. 

  3775. /**

  3776.   * @brief  Get ADC group injected conversion trigger polarity.

  3777.   *         Applicable only for trigger source set to external trigger.

  3778.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge

  3779.   * @param  ADCx ADC instance

  3780.   * @retval Returned value can be one of the following values:

  3781.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  3782.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  3783.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  3784.   */

  3785. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)

  3786. {

  3787.   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));

  3788. }

  3789. 

  3790. /**

  3791.   * @brief  Set ADC group injected sequencer length and scan direction.

  3792.   * @note   This function performs configuration of:

  3793.   *         - Sequence length: Number of ranks in the scan sequence.

  3794.   *         - Sequence direction: Unless specified in parameters, sequencer

  3795.   *           scan direction is forward (from rank 1 to rank n).

  3796.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3797.   *         ADC conversion on only 1 channel.

  3798.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3799.   *         ADC state:

  3800.   *         ADC must not be disabled. Can be enabled with or without conversion

  3801.   *         on going on either groups regular or injected.

  3802.   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength

  3803.   * @param  ADCx ADC instance

  3804.   * @param  SequencerNbRanks This parameter can be one of the following values:

  3805.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  3806.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  3807.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  3808.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  3809.   * @retval None

  3810.   */

  3811. __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  3812. {

  3813.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);

  3814. }

  3815. 

  3816. /**

  3817.   * @brief  Get ADC group injected sequencer length and scan direction.

  3818.   * @note   This function retrieves:

  3819.   *         - Sequence length: Number of ranks in the scan sequence.

  3820.   *         - Sequence direction: Unless specified in parameters, sequencer

  3821.   *           scan direction is forward (from rank 1 to rank n).

  3822.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3823.   *         ADC conversion on only 1 channel.

  3824.   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength

  3825.   * @param  ADCx ADC instance

  3826.   * @retval Returned value can be one of the following values:

  3827.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  3828.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  3829.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  3830.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  3831.   */

  3832. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)

  3833. {

  3834.   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));

  3835. }

  3836. 

  3837. /**

  3838.   * @brief  Set ADC group injected sequencer discontinuous mode:

  3839.   *         sequence subdivided and scan conversions interrupted every selected

  3840.   *         number of ranks.

  3841.   * @note   It is not possible to enable both ADC group injected

  3842.   *         auto-injected mode and sequencer discontinuous mode.

  3843.   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont

  3844.   * @param  ADCx ADC instance

  3845.   * @param  SeqDiscont This parameter can be one of the following values:

  3846.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  3847.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  3848.   * @retval None

  3849.   */

  3850. __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  3851. {

  3852.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);

  3853. }

  3854. 

  3855. /**

  3856.   * @brief  Get ADC group injected sequencer discontinuous mode:

  3857.   *         sequence subdivided and scan conversions interrupted every selected

  3858.   *         number of ranks.

  3859.   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont

  3860.   * @param  ADCx ADC instance

  3861.   * @retval Returned value can be one of the following values:

  3862.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  3863.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  3864.   */

  3865. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)

  3866. {

  3867.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));

  3868. }

  3869. 

  3870. /**

  3871.   * @brief  Set ADC group injected sequence: channel on the selected

  3872.   *         sequence rank.

  3873.   * @note   Depending on devices and packages, some channels may not be available.

  3874.   *         Refer to device datasheet for channels availability.

  3875.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  3876.   *         TempSensor, ...), measurement paths to internal channels must be

  3877.   *         enabled separately.

  3878.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  3879.   * @note   On STM32H7, some fast channels are available: fast analog inputs

  3880.   *         coming from GPIO pads (ADC_IN0..5).

  3881.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3882.   *         ADC state:

  3883.   *         ADC must not be disabled. Can be enabled with or without conversion

  3884.   *         on going on either groups regular or injected.

  3885.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n

  3886.   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n

  3887.   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n

  3888.   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks

  3889.   * @param  ADCx ADC instance

  3890.   * @param  Rank This parameter can be one of the following values:

  3891.   *         @arg @ref LL_ADC_INJ_RANK_1

  3892.   *         @arg @ref LL_ADC_INJ_RANK_2

  3893.   *         @arg @ref LL_ADC_INJ_RANK_3

  3894.   *         @arg @ref LL_ADC_INJ_RANK_4

  3895.   * @param  Channel This parameter can be one of the following values:

  3896.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  3897.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  3898.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  3899.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  3900.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  3901.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  3902.   *         @arg @ref LL_ADC_CHANNEL_6

  3903.   *         @arg @ref LL_ADC_CHANNEL_7

  3904.   *         @arg @ref LL_ADC_CHANNEL_8

  3905.   *         @arg @ref LL_ADC_CHANNEL_9

  3906.   *         @arg @ref LL_ADC_CHANNEL_10

  3907.   *         @arg @ref LL_ADC_CHANNEL_11

  3908.   *         @arg @ref LL_ADC_CHANNEL_12

  3909.   *         @arg @ref LL_ADC_CHANNEL_13

  3910.   *         @arg @ref LL_ADC_CHANNEL_14

  3911.   *         @arg @ref LL_ADC_CHANNEL_15

  3912.   *         @arg @ref LL_ADC_CHANNEL_16

  3913.   *         @arg @ref LL_ADC_CHANNEL_17

  3914.   *         @arg @ref LL_ADC_CHANNEL_18

  3915.   *         @arg @ref LL_ADC_CHANNEL_19

  3916.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3917.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  3918.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3919.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  3920.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  3921.   *

  3922.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  3923.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  3924.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  3925.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  3926.   * @retval None

  3927.   */

  3928. __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  3929. {

  3930.   /* Set bits with content of parameter "Channel" with bits position          */

  3931.   /* in register depending on parameter "Rank".                               */

  3932.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  3933.   /* other bits reserved for other purpose.                                   */

  3934.   MODIFY_REG(ADCx->JSQR,

  3935.              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),

  3936.              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));

  3937. }

  3938. 

  3939. /**

  3940.   * @brief  Get ADC group injected sequence: channel on the selected

  3941.   *         sequence rank.

  3942.   * @note   Depending on devices and packages, some channels may not be available.

  3943.   *         Refer to device datasheet for channels availability.

  3944.   * @note   Usage of the returned channel number:

  3945.   *         - To reinject this channel into another function LL_ADC_xxx:

  3946.   *           the returned channel number is only partly formatted on definition

  3947.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  3948.   *           with parts of literals LL_ADC_CHANNEL_x or using

  3949.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3950.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3951.   *           as parameter for another function.

  3952.   *         - To get the channel number in decimal format:

  3953.   *           process the returned value with the helper macro

  3954.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3955.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n

  3956.   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n

  3957.   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n

  3958.   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks

  3959.   * @param  ADCx ADC instance

  3960.   * @param  Rank This parameter can be one of the following values:

  3961.   *         @arg @ref LL_ADC_INJ_RANK_1

  3962.   *         @arg @ref LL_ADC_INJ_RANK_2

  3963.   *         @arg @ref LL_ADC_INJ_RANK_3

  3964.   *         @arg @ref LL_ADC_INJ_RANK_4

  3965.   * @retval Returned value can be one of the following values:

  3966.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  3967.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  3968.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  3969.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  3970.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  3971.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  3972.   *         @arg @ref LL_ADC_CHANNEL_6

  3973.   *         @arg @ref LL_ADC_CHANNEL_7

  3974.   *         @arg @ref LL_ADC_CHANNEL_8

  3975.   *         @arg @ref LL_ADC_CHANNEL_9

  3976.   *         @arg @ref LL_ADC_CHANNEL_10

  3977.   *         @arg @ref LL_ADC_CHANNEL_11

  3978.   *         @arg @ref LL_ADC_CHANNEL_12

  3979.   *         @arg @ref LL_ADC_CHANNEL_13

  3980.   *         @arg @ref LL_ADC_CHANNEL_14

  3981.   *         @arg @ref LL_ADC_CHANNEL_15

  3982.   *         @arg @ref LL_ADC_CHANNEL_16

  3983.   *         @arg @ref LL_ADC_CHANNEL_17

  3984.   *         @arg @ref LL_ADC_CHANNEL_18

  3985.   *         @arg @ref LL_ADC_CHANNEL_19

  3986.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3987.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  3988.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3989.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  3990.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  3991.   *

  3992.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  3993.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  3994.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  3995.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  3996.   *         (1, 2) For ADC channel read back from ADC register,

  3997.   *                comparison with internal channel parameter to be done

  3998.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  3999.   */

  4000. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  4001. {

  4002.   return (uint32_t)((READ_BIT(ADCx->JSQR,

  4003.                              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))

  4004.                     >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

  4005.                    );

  4006. }

  4007. 

  4008. /**

  4009.   * @brief  Set ADC group injected conversion trigger:

  4010.   *         independent or from ADC group regular.

  4011.   * @note   This mode can be used to extend number of data registers

  4012.   *         updated after one ADC conversion trigger and with data

  4013.   *         permanently kept (not erased by successive conversions of scan of

  4014.   *         ADC sequencer ranks), up to 5 data registers:

  4015.   *         1 data register on ADC group regular, 4 data registers

  4016.   *         on ADC group injected.

  4017.   * @note   If ADC group injected injected trigger source is set to an

  4018.   *         external trigger, this feature must be must be set to

  4019.   *         independent trigger.

  4020.   *         ADC group injected automatic trigger is compliant only with

  4021.   *         group injected trigger source set to SW start, without any

  4022.   *         further action on  ADC group injected conversion start or stop:

  4023.   *         in this case, ADC group injected is controlled only

  4024.   *         from ADC group regular.

  4025.   * @note   It is not possible to enable both ADC group injected

  4026.   *         auto-injected mode and sequencer discontinuous mode.

  4027.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4028.   *         ADC state:

  4029.   *         ADC must be disabled or enabled without conversion on going

  4030.   *         on either groups regular or injected.

  4031.   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto

  4032.   * @param  ADCx ADC instance

  4033.   * @param  TrigAuto This parameter can be one of the following values:

  4034.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  4035.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  4036.   * @retval None

  4037.   */

  4038. __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)

  4039. {

  4040.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);

  4041. }

  4042. 

  4043. /**

  4044.   * @brief  Get ADC group injected conversion trigger:

  4045.   *         independent or from ADC group regular.

  4046.   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto

  4047.   * @param  ADCx ADC instance

  4048.   * @retval Returned value can be one of the following values:

  4049.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  4050.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  4051.   */

  4052. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)

  4053. {

  4054.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));

  4055. }

  4056. 

  4057. /**

  4058.   * @brief  Set ADC group injected contexts queue mode.

  4059.   * @note   A context is a setting of group injected sequencer:

  4060.   *         - group injected trigger

  4061.   *         - sequencer length

  4062.   *         - sequencer ranks

  4063.   *         If contexts queue is disabled:

  4064.   *         - only 1 sequence can be configured

  4065.   *           and is active perpetually.

  4066.   *         If contexts queue is enabled:

  4067.   *         - up to 2 contexts can be queued

  4068.   *           and are checked in and out as a FIFO stack (first-in, first-out).

  4069.   *         - If a new context is set when queues is full, error is triggered

  4070.   *           by interruption "Injected Queue Overflow".

  4071.   *         - Two behaviors are possible when all contexts have been processed:

  4072.   *           the contexts queue can maintain the last context active perpetually

  4073.   *           or can be empty and injected group triggers are disabled.

  4074.   *         - Triggers can be only external (not internal SW start)

  4075.   *         - Caution: The sequence must be fully configured in one time

  4076.   *           (one write of register JSQR makes a check-in of a new context

  4077.   *           into the queue).

  4078.   *           Therefore functions to set separately injected trigger and

  4079.   *           sequencer channels cannot be used, register JSQR must be set

  4080.   *           using function @ref LL_ADC_INJ_ConfigQueueContext().

  4081.   * @note   This parameter can be modified only when no conversion is on going

  4082.   *         on either groups regular or injected.

  4083.   * @note   A modification of the context mode (bit JQDIS) causes the contexts

  4084.   *         queue to be flushed and the register JSQR is cleared.

  4085.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4086.   *         ADC state:

  4087.   *         ADC must be disabled or enabled without conversion on going

  4088.   *         on either groups regular or injected.

  4089.   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n

  4090.   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode

  4091.   * @param  ADCx ADC instance

  4092.   * @param  QueueMode This parameter can be one of the following values:

  4093.   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE

  4094.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE

  4095.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

  4096.   * @retval None

  4097.   */

  4098. __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)

  4099. {

  4100.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);

  4101. }

  4102. 

  4103. /**

  4104.   * @brief  Get ADC group injected context queue mode.

  4105.   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n

  4106.   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode

  4107.   * @param  ADCx ADC instance

  4108.   * @retval Returned value can be one of the following values:

  4109.   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE

  4110.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE

  4111.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

  4112.   */

  4113. __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)

  4114. {

  4115.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));

  4116. }

  4117. 

  4118. /**

  4119.   * @brief  Set one context on ADC group injected that will be checked in

  4120.   *         contexts queue.

  4121.   * @note   A context is a setting of group injected sequencer:

  4122.   *         - group injected trigger

  4123.   *         - sequencer length

  4124.   *         - sequencer ranks

  4125.   *         This function is intended to be used when contexts queue is enabled,

  4126.   *         because the sequence must be fully configured in one time

  4127.   *         (functions to set separately injected trigger and sequencer channels

  4128.   *         cannot be used):

  4129.   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().

  4130.   * @note   In the contexts queue, only the active context can be read.

  4131.   *         The parameters of this function can be read using functions:

  4132.   *         @arg @ref LL_ADC_INJ_GetTriggerSource()

  4133.   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()

  4134.   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()

  4135.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  4136.   *         TempSensor, ...), measurement paths to internal channels must be

  4137.   *         enabled separately.

  4138.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  4139.   * @note   On STM32H7, some fast channels are available: fast analog inputs

  4140.   *         coming from GPIO pads (ADC_IN0..5).

  4141.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4142.   *         ADC state:

  4143.   *         ADC must not be disabled. Can be enabled with or without conversion

  4144.   *         on going on either groups regular or injected.

  4145.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n

  4146.   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n

  4147.   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n

  4148.   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n

  4149.   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n

  4150.   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n

  4151.   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext

  4152.   * @param  ADCx ADC instance

  4153.   * @param  TriggerSource This parameter can be one of the following values:

  4154.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  4155.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  4156.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  4157.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  4158.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  4159.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  4160.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  4161.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  4162.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

  4163.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  4164.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

  4165.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

  4166.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

  4167.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

  4168.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

  4169.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

  4170.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

  4171.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

  4172.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

  4173.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

  4174.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

  4175.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

  4176.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  4177.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  4178.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  4179.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  4180.   *

  4181.   *         Note: This parameter is discarded in case of SW start:

  4182.   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".

  4183.   * @param  SequencerNbRanks This parameter can be one of the following values:

  4184.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  4185.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  4186.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  4187.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  4188.   * @param  Rank1_Channel This parameter can be one of the following values:

  4189.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4190.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4191.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4192.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4193.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4194.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4195.   *         @arg @ref LL_ADC_CHANNEL_6

  4196.   *         @arg @ref LL_ADC_CHANNEL_7

  4197.   *         @arg @ref LL_ADC_CHANNEL_8

  4198.   *         @arg @ref LL_ADC_CHANNEL_9

  4199.   *         @arg @ref LL_ADC_CHANNEL_10

  4200.   *         @arg @ref LL_ADC_CHANNEL_11

  4201.   *         @arg @ref LL_ADC_CHANNEL_12

  4202.   *         @arg @ref LL_ADC_CHANNEL_13

  4203.   *         @arg @ref LL_ADC_CHANNEL_14

  4204.   *         @arg @ref LL_ADC_CHANNEL_15

  4205.   *         @arg @ref LL_ADC_CHANNEL_16

  4206.   *         @arg @ref LL_ADC_CHANNEL_17

  4207.   *         @arg @ref LL_ADC_CHANNEL_18

  4208.   *         @arg @ref LL_ADC_CHANNEL_19

  4209.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4210.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4211.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4212.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4213.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4214.   *

  4215.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4216.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4217.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4218.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4219.   * @param  Rank2_Channel This parameter can be one of the following values:

  4220.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4221.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4222.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4223.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4224.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4225.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4226.   *         @arg @ref LL_ADC_CHANNEL_6

  4227.   *         @arg @ref LL_ADC_CHANNEL_7

  4228.   *         @arg @ref LL_ADC_CHANNEL_8

  4229.   *         @arg @ref LL_ADC_CHANNEL_9

  4230.   *         @arg @ref LL_ADC_CHANNEL_10

  4231.   *         @arg @ref LL_ADC_CHANNEL_11

  4232.   *         @arg @ref LL_ADC_CHANNEL_12

  4233.   *         @arg @ref LL_ADC_CHANNEL_13

  4234.   *         @arg @ref LL_ADC_CHANNEL_14

  4235.   *         @arg @ref LL_ADC_CHANNEL_15

  4236.   *         @arg @ref LL_ADC_CHANNEL_16

  4237.   *         @arg @ref LL_ADC_CHANNEL_17

  4238.   *         @arg @ref LL_ADC_CHANNEL_18

  4239.   *         @arg @ref LL_ADC_CHANNEL_19

  4240.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4241.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4242.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4243.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4244.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4245.   *

  4246.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4247.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4248.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4249.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4250.   * @param  Rank3_Channel This parameter can be one of the following values:

  4251.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4252.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4253.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4254.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4255.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4256.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4257.   *         @arg @ref LL_ADC_CHANNEL_6

  4258.   *         @arg @ref LL_ADC_CHANNEL_7

  4259.   *         @arg @ref LL_ADC_CHANNEL_8

  4260.   *         @arg @ref LL_ADC_CHANNEL_9

  4261.   *         @arg @ref LL_ADC_CHANNEL_10

  4262.   *         @arg @ref LL_ADC_CHANNEL_11

  4263.   *         @arg @ref LL_ADC_CHANNEL_12

  4264.   *         @arg @ref LL_ADC_CHANNEL_13

  4265.   *         @arg @ref LL_ADC_CHANNEL_14

  4266.   *         @arg @ref LL_ADC_CHANNEL_15

  4267.   *         @arg @ref LL_ADC_CHANNEL_16

  4268.   *         @arg @ref LL_ADC_CHANNEL_17

  4269.   *         @arg @ref LL_ADC_CHANNEL_18

  4270.   *         @arg @ref LL_ADC_CHANNEL_19

  4271.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4272.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4273.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4274.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4275.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4276.   *

  4277.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4278.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4279.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4280.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4281.   * @param  Rank4_Channel This parameter can be one of the following values:

  4282.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4283.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4284.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4285.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4286.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4287.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4288.   *         @arg @ref LL_ADC_CHANNEL_6

  4289.   *         @arg @ref LL_ADC_CHANNEL_7

  4290.   *         @arg @ref LL_ADC_CHANNEL_8

  4291.   *         @arg @ref LL_ADC_CHANNEL_9

  4292.   *         @arg @ref LL_ADC_CHANNEL_10

  4293.   *         @arg @ref LL_ADC_CHANNEL_11

  4294.   *         @arg @ref LL_ADC_CHANNEL_12

  4295.   *         @arg @ref LL_ADC_CHANNEL_13

  4296.   *         @arg @ref LL_ADC_CHANNEL_14

  4297.   *         @arg @ref LL_ADC_CHANNEL_15

  4298.   *         @arg @ref LL_ADC_CHANNEL_16

  4299.   *         @arg @ref LL_ADC_CHANNEL_17

  4300.   *         @arg @ref LL_ADC_CHANNEL_18

  4301.   *         @arg @ref LL_ADC_CHANNEL_19

  4302.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4303.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4304.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4305.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4306.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4307.   *

  4308.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4309.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4310.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4311.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4312.   * @retval None

  4313.   */

  4314. __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,

  4315.                                                    uint32_t TriggerSource,

  4316.                                                    uint32_t ExternalTriggerEdge,

  4317.                                                    uint32_t SequencerNbRanks,

  4318.                                                    uint32_t Rank1_Channel,

  4319.                                                    uint32_t Rank2_Channel,

  4320.                                                    uint32_t Rank3_Channel,

  4321.                                                    uint32_t Rank4_Channel)

  4322. {

  4323.   /* Set bits with content of parameter "Rankx_Channel" with bits position    */

  4324.   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */

  4325.   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */

  4326.   /* because containing other bits reserved for other purpose.                */

  4327.   /* If parameter "TriggerSource" is set to SW start, then parameter          */

  4328.   /* "ExternalTriggerEdge" is discarded.                                      */

  4329.   register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);

  4330.   MODIFY_REG(ADCx->JSQR           ,

  4331.              ADC_JSQR_JEXTSEL |

  4332.              ADC_JSQR_JEXTEN  |

  4333.              ADC_JSQR_JSQ4    |

  4334.              ADC_JSQR_JSQ3    |

  4335.              ADC_JSQR_JSQ2    |

  4336.              ADC_JSQR_JSQ1    |

  4337.              ADC_JSQR_JL          ,

  4338.              TriggerSource       |

  4339.              (ExternalTriggerEdge * (is_trigger_not_sw)) |

  4340.              (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  4341.              (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  4342.              (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  4343.              (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  4344.              SequencerNbRanks

  4345.             );

  4346. }

  4347. 

  4348. /**

  4349.   * @}

  4350.   */

  4351. 

  4352. /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels

  4353.   * @{

  4354.   */

  4355. 

  4356. /**

  4357.   * @brief  Set sampling time of the selected ADC channel

  4358.   *         Unit: ADC clock cycles.

  4359.   * @note   On this device, sampling time is on channel scope: independently

  4360.   *         of channel mapped on ADC group regular or injected.

  4361.   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be

  4362.   *         converted:

  4363.   *         sampling time constraints must be respected (sampling time can be

  4364.   *         adjusted in function of ADC clock frequency and sampling time

  4365.   *         setting).

  4366.   *         Refer to device datasheet for timings values (parameters TS_vrefint,

  4367.   *         TS_temp, ...).

  4368.   * @note   Conversion time is the addition of sampling time and processing time.

  4369.   *         On this STM32 serie, ADC processing time is:

  4370.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  4371.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  4372.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  4373.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  4374.   * @note   In case of ADC conversion of internal channel (VrefInt,

  4375.   *         temperature sensor, ...), a sampling time minimum value

  4376.   *         is required.

  4377.   *         Refer to device datasheet.

  4378.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4379.   *         ADC state:

  4380.   *         ADC must be disabled or enabled without conversion on going

  4381.   *         on either groups regular or injected.

  4382.   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n

  4383.   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n

  4384.   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n

  4385.   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n

  4386.   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n

  4387.   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n

  4388.   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n

  4389.   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n

  4390.   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n

  4391.   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n

  4392.   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n

  4393.   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n

  4394.   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n

  4395.   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n

  4396.   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n

  4397.   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n

  4398.   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n

  4399.   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n

  4400.   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime

  4401.   * @param  ADCx ADC instance

  4402.   * @param  Channel This parameter can be one of the following values:

  4403.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4404.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4405.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4406.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4407.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4408.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4409.   *         @arg @ref LL_ADC_CHANNEL_6

  4410.   *         @arg @ref LL_ADC_CHANNEL_7

  4411.   *         @arg @ref LL_ADC_CHANNEL_8

  4412.   *         @arg @ref LL_ADC_CHANNEL_9

  4413.   *         @arg @ref LL_ADC_CHANNEL_10

  4414.   *         @arg @ref LL_ADC_CHANNEL_11

  4415.   *         @arg @ref LL_ADC_CHANNEL_12

  4416.   *         @arg @ref LL_ADC_CHANNEL_13

  4417.   *         @arg @ref LL_ADC_CHANNEL_14

  4418.   *         @arg @ref LL_ADC_CHANNEL_15

  4419.   *         @arg @ref LL_ADC_CHANNEL_16

  4420.   *         @arg @ref LL_ADC_CHANNEL_17

  4421.   *         @arg @ref LL_ADC_CHANNEL_18

  4422.   *         @arg @ref LL_ADC_CHANNEL_19

  4423.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4424.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4425.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4426.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4427.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4428.   *

  4429.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4430.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4431.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4432.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4433.   * @param  SamplingTime This parameter can be one of the following values:

  4434.   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5

  4435.   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5

  4436.   *         @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5

  4437.   *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5

  4438.   *         @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5

  4439.   *         @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5

  4440.   *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5

  4441.   *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5

  4442.   * @retval None

  4443.   */

  4444. __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)

  4445. {

  4446.   /* Set bits with content of parameter "SamplingTime" with bits position     */

  4447.   /* in register and register position depending on parameter "Channel".      */

  4448.   /* Parameter "Channel" is used with masks because containing                */

  4449.   /* other bits reserved for other purpose.                                   */

  4450.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));

  4451. 

  4452.   MODIFY_REG(*preg,

  4453.              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),

  4454.              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));

  4455. }

  4456. 

  4457. /**

  4458.   * @brief  Get sampling time of the selected ADC channel

  4459.   *         Unit: ADC clock cycles.

  4460.   * @note   On this device, sampling time is on channel scope: independently

  4461.   *         of channel mapped on ADC group regular or injected.

  4462.   * @note   Conversion time is the addition of sampling time and processing time.

  4463.   *         On this STM32 serie, ADC processing time is:

  4464.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  4465.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  4466.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  4467.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  4468.   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n

  4469.   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n

  4470.   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n

  4471.   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n

  4472.   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n

  4473.   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n

  4474.   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n

  4475.   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n

  4476.   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n

  4477.   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n

  4478.   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n

  4479.   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n

  4480.   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n

  4481.   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n

  4482.   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n

  4483.   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n

  4484.   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n

  4485.   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n

  4486.   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime

  4487.   * @param  ADCx ADC instance

  4488.   * @param  Channel This parameter can be one of the following values:

  4489.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4490.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4491.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4492.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4493.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4494.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4495.   *         @arg @ref LL_ADC_CHANNEL_6

  4496.   *         @arg @ref LL_ADC_CHANNEL_7

  4497.   *         @arg @ref LL_ADC_CHANNEL_8

  4498.   *         @arg @ref LL_ADC_CHANNEL_9

  4499.   *         @arg @ref LL_ADC_CHANNEL_10

  4500.   *         @arg @ref LL_ADC_CHANNEL_11

  4501.   *         @arg @ref LL_ADC_CHANNEL_12

  4502.   *         @arg @ref LL_ADC_CHANNEL_13

  4503.   *         @arg @ref LL_ADC_CHANNEL_14

  4504.   *         @arg @ref LL_ADC_CHANNEL_15

  4505.   *         @arg @ref LL_ADC_CHANNEL_16

  4506.   *         @arg @ref LL_ADC_CHANNEL_17

  4507.   *         @arg @ref LL_ADC_CHANNEL_18

  4508.   *         @arg @ref LL_ADC_CHANNEL_19

  4509.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4510.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4511.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4512.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4513.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4514.   *

  4515.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4516.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4517.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4518.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4519.   * @retval Returned value can be one of the following values:

  4520.   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5

  4521.   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5

  4522.   *         @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5

  4523.   *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5

  4524.   *         @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5

  4525.   *         @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5

  4526.   *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5

  4527.   *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5

  4528.   */

  4529. __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)

  4530. {

  4531.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));

  4532. 

  4533.   return (uint32_t)(READ_BIT(*preg,

  4534.                              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))

  4535.                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)

  4536.                    );

  4537. }

  4538. 

  4539. /**

  4540.   * @brief  Set mode single-ended or differential input of the selected

  4541.   *         ADC channel.

  4542.   * @note   Channel ending is on channel scope: independently of channel mapped

  4543.   *         on ADC group regular or injected.

  4544.   *         In differential mode: Differential measurement is carried out

  4545.   *         between the selected channel 'i' (positive input) and

  4546.   *         channel 'i+1' (negative input). Only channel 'i' has to be

  4547.   *         configured, channel 'i+1' is configured automatically.

  4548.   * @note   Refer to Reference Manual to ensure the selected channel is

  4549.   *         available in differential mode.

  4550.   *         For example, internal channels (VrefInt, TempSensor, ...) are

  4551.   *         not available in differential mode.

  4552.   * @note   When configuring a channel 'i' in differential mode,

  4553.   *         the channel 'i+1' is not usable separately.

  4554.   * @note   On STM32H7, some channels are internally fixed to single-ended inputs

  4555.   *         configuration:

  4556.   *         - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19

  4557.   *         - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19

  4558.   *         - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19

  4559.   * @note   For ADC channels configured in differential mode, both inputs

  4560.   *         should be biased at (Vref+)/2 +/-200mV.

  4561.   *         (Vref+ is the analog voltage reference)

  4562.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4563.   *         ADC state:

  4564.   *         ADC must be ADC disabled.

  4565.   * @note   One or several values can be selected.

  4566.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  4567.   * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff

  4568.   * @param  ADCx ADC instance

  4569.   * @param  Channel This parameter can be one of the following values:

  4570.   *         @arg @ref LL_ADC_CHANNEL_1

  4571.   *         @arg @ref LL_ADC_CHANNEL_2

  4572.   *         @arg @ref LL_ADC_CHANNEL_3

  4573.   *         @arg @ref LL_ADC_CHANNEL_4

  4574.   *         @arg @ref LL_ADC_CHANNEL_5

  4575.   *         @arg @ref LL_ADC_CHANNEL_10

  4576.   *         @arg @ref LL_ADC_CHANNEL_11

  4577.   *         @arg @ref LL_ADC_CHANNEL_12

  4578.   *         @arg @ref LL_ADC_CHANNEL_13

  4579.   *         @arg @ref LL_ADC_CHANNEL_14

  4580.   *         @arg @ref LL_ADC_CHANNEL_15

  4581.   *         @arg @ref LL_ADC_CHANNEL_16

  4582.   *         @arg @ref LL_ADC_CHANNEL_17

  4583.   *         @arg @ref LL_ADC_CHANNEL_18

  4584.   *         @arg @ref LL_ADC_CHANNEL_19

  4585.   * @param  SingleDiff This parameter can be a combination of the following values:

  4586.   *         @arg @ref LL_ADC_SINGLE_ENDED

  4587.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  4588.   * @retval None

  4589.   */

  4590. __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)

  4591. {

  4592.   /* Bits of channels in single or differential mode are set only for         */

  4593.   /* differential mode (for single mode, mask of bits allowed to be set is    */

  4594.   /* shifted out of range of bits of channels in single or differential mode. */

  4595.   MODIFY_REG(ADCx->DIFSEL,

  4596.              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,

  4597.              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));

  4598. }

  4599. 

  4600. /**

  4601.   * @brief  Get mode single-ended or differential input of the selected

  4602.   *         ADC channel.

  4603.   * @note   When configuring a channel 'i' in differential mode,

  4604.   *         the channel 'i+1' is not usable separately.

  4605.   *         Therefore, to ensure a channel is configured in single-ended mode,

  4606.   *         the configuration of channel itself and the channel 'i-1' must be

  4607.   *         read back (to ensure that the selected channel channel has not been

  4608.   *         configured in differential mode by the previous channel).

  4609.   * @note   Refer to Reference Manual to ensure the selected channel is

  4610.   *         available in differential mode.

  4611.   *         For example, internal channels (VrefInt, TempSensor, ...) are

  4612.   *         not available in differential mode.

  4613.   * @note   When configuring a channel 'i' in differential mode,

  4614.   *         the channel 'i+1' is not usable separately.

  4615.   * @note   On STM32H7, some channels are internally fixed to single-ended inputs

  4616.   *         configuration:

  4617.   *         - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19

  4618.   *         - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19

  4619.   *         - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19

  4620.   * @note   One or several values can be selected. In this case, the value

  4621.   *         returned is null if all channels are in single ended-mode.

  4622.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  4623.   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff

  4624.   * @param  ADCx ADC instance

  4625.   * @param  Channel This parameter can be a combination of the following values:

  4626.   *         @arg @ref LL_ADC_CHANNEL_1

  4627.   *         @arg @ref LL_ADC_CHANNEL_2

  4628.   *         @arg @ref LL_ADC_CHANNEL_3

  4629.   *         @arg @ref LL_ADC_CHANNEL_4

  4630.   *         @arg @ref LL_ADC_CHANNEL_5

  4631.   *         @arg @ref LL_ADC_CHANNEL_10

  4632.   *         @arg @ref LL_ADC_CHANNEL_11

  4633.   *         @arg @ref LL_ADC_CHANNEL_12

  4634.   *         @arg @ref LL_ADC_CHANNEL_13

  4635.   *         @arg @ref LL_ADC_CHANNEL_14

  4636.   *         @arg @ref LL_ADC_CHANNEL_15

  4637.   *         @arg @ref LL_ADC_CHANNEL_16

  4638.   *         @arg @ref LL_ADC_CHANNEL_17

  4639.   *         @arg @ref LL_ADC_CHANNEL_18

  4640.   *         @arg @ref LL_ADC_CHANNEL_19

  4641.   * @retval 0: channel in single-ended mode, else: channel in differential mode

  4642.   */

  4643. __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)

  4644. {

  4645.   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));

  4646. }

  4647. 

  4648. /**

  4649.   * @}

  4650.   */

  4651. 

  4652. /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog

  4653.   * @{

  4654.   */

  4655. 

  4656. /**

  4657.   * @brief  Set ADC analog watchdog monitored channels:

  4658.   *         a single channel, multiple channels or all channels,

  4659.   *         on ADC groups regular and-or injected.

  4660.   * @note   Once monitored channels are selected, analog watchdog

  4661.   *         is enabled.

  4662.   * @note   In case of need to define a single channel to monitor

  4663.   *         with analog watchdog from sequencer channel definition,

  4664.   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().

  4665.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  4666.   *         instance:

  4667.   *         - AWD standard (instance AWD1):

  4668.   *           - channels monitored: can monitor 1 channel or all channels.

  4669.   *           - groups monitored: ADC groups regular and-or injected.

  4670.   *           - resolution: resolution is not limited (corresponds to

  4671.   *             ADC resolution configured).

  4672.   *         - AWD flexible (instances AWD2, AWD3):

  4673.   *           - channels monitored: flexible on channels monitored, selection is

  4674.   *             channel wise, from from 1 to all channels.

  4675.   *             Specificity of this analog watchdog: Multiple channels can

  4676.   *             be selected. For example:

  4677.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  4678.   *           - groups monitored: not selection possible (monitoring on both

  4679.   *             groups regular and injected).

  4680.   *             Channels selected are monitored on groups regular and injected:

  4681.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  4682.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  4683.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  4684.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  4685.   *             the 2 LSB are ignored.

  4686.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4687.   *         ADC state:

  4688.   *         ADC must be disabled or enabled without conversion on going

  4689.   *         on either groups regular or injected.

  4690.   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n

  4691.   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n

  4692.   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n

  4693.   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n

  4694.   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n

  4695.   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels

  4696.   * @param  ADCx ADC instance

  4697.   * @param  AWDy This parameter can be one of the following values:

  4698.   *         @arg @ref LL_ADC_AWD1

  4699.   *         @arg @ref LL_ADC_AWD2

  4700.   *         @arg @ref LL_ADC_AWD3

  4701.   * @param  AWDChannelGroup This parameter can be one of the following values:

  4702.   *         @arg @ref LL_ADC_AWD_DISABLE

  4703.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  4704.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

  4705.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  4706.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  4707.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

  4708.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  4709.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  4710.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

  4711.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  4712.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  4713.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

  4714.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  4715.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  4716.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

  4717.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  4718.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  4719.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

  4720.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  4721.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  4722.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

  4723.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  4724.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  4725.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

  4726.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  4727.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  4728.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

  4729.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  4730.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  4731.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

  4732.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  4733.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  4734.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

  4735.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  4736.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  4737.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

  4738.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  4739.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  4740.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

  4741.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  4742.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  4743.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

  4744.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  4745.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  4746.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

  4747.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  4748.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  4749.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

  4750.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  4751.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  4752.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

  4753.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  4754.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  4755.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

  4756.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  4757.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  4758.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

  4759.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  4760.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  4761.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

  4762.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  4763.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

  4764.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

  4765.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

  4766.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)

  4767.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)

  4768.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)

  4769.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)

  4770.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)

  4771.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)

  4772.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)

  4773.   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)

  4774.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)

  4775.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)

  4776.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)

  4777.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)

  4778.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)

  4779.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)

  4780.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)

  4781.   *

  4782.   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n

  4783.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4784.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

  4785.   * @retval None

  4786.   */

  4787. __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)

  4788. {

  4789.   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */

  4790.   /* in register and register position depending on parameter "AWDy".         */

  4791.   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */

  4792.   /* containing other bits reserved for other purpose.                        */

  4793.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)

  4794.                                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));

  4795. 

  4796.   MODIFY_REG(*preg,

  4797.              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),

  4798.              AWDChannelGroup & AWDy);

  4799. }

  4800. 

  4801. /**

  4802.   * @brief  Get ADC analog watchdog monitored channel.

  4803.   * @note   Usage of the returned channel number:

  4804.   *         - To reinject this channel into another function LL_ADC_xxx:

  4805.   *           the returned channel number is only partly formatted on definition

  4806.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  4807.   *           with parts of literals LL_ADC_CHANNEL_x or using

  4808.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4809.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  4810.   *           as parameter for another function.

  4811.   *         - To get the channel number in decimal format:

  4812.   *           process the returned value with the helper macro

  4813.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4814.   *           Applicable only when the analog watchdog is set to monitor

  4815.   *           one channel.

  4816.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  4817.   *         instance:

  4818.   *         - AWD standard (instance AWD1):

  4819.   *           - channels monitored: can monitor 1 channel or all channels.

  4820.   *           - groups monitored: ADC groups regular and-or injected.

  4821.   *           - resolution: resolution is not limited (corresponds to

  4822.   *             ADC resolution configured).

  4823.   *         - AWD flexible (instances AWD2, AWD3):

  4824.   *           - channels monitored: flexible on channels monitored, selection is

  4825.   *             channel wise, from from 1 to all channels.

  4826.   *             Specificity of this analog watchdog: Multiple channels can

  4827.   *             be selected. For example:

  4828.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  4829.   *           - groups monitored: not selection possible (monitoring on both

  4830.   *             groups regular and injected).

  4831.   *             Channels selected are monitored on groups regular and injected:

  4832.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  4833.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  4834.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  4835.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  4836.   *             the 2 LSB are ignored.

  4837.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4838.   *         ADC state:

  4839.   *         ADC must be disabled or enabled without conversion on going

  4840.   *         on either groups regular or injected.

  4841.   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n

  4842.   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n

  4843.   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n

  4844.   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n

  4845.   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n

  4846.   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels

  4847.   * @param  ADCx ADC instance

  4848.   * @param  AWDy This parameter can be one of the following values:

  4849.   *         @arg @ref LL_ADC_AWD1

  4850.   *         @arg @ref LL_ADC_AWD2 (1)

  4851.   *         @arg @ref LL_ADC_AWD3 (1)

  4852.   *

  4853.   *         (1) On this AWD number, monitored channel can be retrieved

  4854.   *             if only 1 channel is programmed (or none or all channels).

  4855.   *             This function cannot retrieve monitored channel if

  4856.   *             multiple channels are programmed simultaneously

  4857.   *             by bitfield.

  4858.   * @retval Returned value can be one of the following values:

  4859.   *         @arg @ref LL_ADC_AWD_DISABLE

  4860.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  4861.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

  4862.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  4863.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  4864.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

  4865.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  4866.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  4867.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

  4868.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  4869.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  4870.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

  4871.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  4872.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  4873.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

  4874.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  4875.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  4876.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

  4877.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  4878.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  4879.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

  4880.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  4881.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  4882.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

  4883.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  4884.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  4885.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

  4886.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  4887.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  4888.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

  4889.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  4890.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  4891.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

  4892.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  4893.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  4894.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

  4895.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  4896.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  4897.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

  4898.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  4899.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  4900.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

  4901.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  4902.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  4903.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

  4904.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  4905.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  4906.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

  4907.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  4908.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  4909.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

  4910.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  4911.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  4912.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

  4913.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  4914.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  4915.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

  4916.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  4917.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  4918.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

  4919.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  4920.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

  4921.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

  4922.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

  4923.   *

  4924.   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.

  4925.   */

  4926. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)

  4927. {

  4928.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)

  4929.                                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));

  4930. 

  4931.   register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);

  4932. 

  4933.   /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */

  4934.   /* (parameter value LL_ADC_AWD_DISABLE).                                    */

  4935.   /* Else, the selected AWD is enabled and is monitoring a group of channels  */

  4936.   /* or a single channel.                                                     */

  4937.   if(AnalogWDMonitChannels != 0UL)

  4938.   {

  4939.     if(AWDy == LL_ADC_AWD1)

  4940.     {

  4941.       if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)

  4942.       {

  4943.         /* AWD monitoring a group of channels */

  4944.         AnalogWDMonitChannels = ((  AnalogWDMonitChannels

  4945.                                   | (ADC_AWD_CR23_CHANNEL_MASK)

  4946.                                  )

  4947.                                  & (~(ADC_CFGR_AWD1CH))

  4948.                                 );

  4949.       }

  4950.       else

  4951.       {

  4952.         /* AWD monitoring a single channel */

  4953.         AnalogWDMonitChannels = (AnalogWDMonitChannels

  4954.                                  | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))

  4955.                                 );

  4956.       }

  4957.     }

  4958.     else

  4959.     {

  4960.       if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)

  4961.       {

  4962.         /* AWD monitoring a group of channels */

  4963.         AnalogWDMonitChannels = (  ADC_AWD_CR23_CHANNEL_MASK

  4964.                                  | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))

  4965.                                 );

  4966.       }

  4967.       else

  4968.       {

  4969.         /* AWD monitoring a single channel */

  4970.         /* AWD monitoring a group of channels */

  4971.         AnalogWDMonitChannels = (  AnalogWDMonitChannels

  4972.                                  | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

  4973.                                  | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)

  4974.                                 );

  4975.       }

  4976.     }

  4977.   }

  4978. 

  4979.   return AnalogWDMonitChannels;

  4980. }

  4981. 

  4982. /**

  4983.   * @brief  Set ADC analog watchdog threshold value of threshold

  4984.   *         high or low.

  4985.   * @note   In case of ADC resolution different of 12 bits,

  4986.   *         analog watchdog thresholds data require a specific shift.

  4987.   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().

  4988.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  4989.   *         instance:

  4990.   *         - AWD standard (instance AWD1):

  4991.   *           - channels monitored: can monitor 1 channel or all channels.

  4992.   *           - groups monitored: ADC groups regular and-or injected.

  4993.   *           - resolution: resolution is not limited (corresponds to

  4994.   *             ADC resolution configured).

  4995.   *         - AWD flexible (instances AWD2, AWD3):

  4996.   *           - channels monitored: flexible on channels monitored, selection is

  4997.   *             channel wise, from from 1 to all channels.

  4998.   *             Specificity of this analog watchdog: Multiple channels can

  4999.   *             be selected. For example:

  5000.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  5001.   *           - groups monitored: not selection possible (monitoring on both

  5002.   *             groups regular and injected).

  5003.   *             Channels selected are monitored on groups regular and injected:

  5004.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  5005.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  5006.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  5007.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  5008.   *             the 2 LSB are ignored.

  5009.   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are

  5010.   *         impacted: the comparison of analog watchdog thresholds is done

  5011.   *         on oversampling intermediate computation (after ratio, before shift

  5012.   *         application): intermediate register bitfield [32:7]

  5013.   *         (26 most significant bits).

  5014.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5015.   *         ADC state:

  5016.   *         ADC must be disabled or enabled without conversion on going

  5017.   *         on either ADC groups regular or injected.

  5018.   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n

  5019.   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n

  5020.   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n

  5021.   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n

  5022.   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n

  5023.   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds

  5024.   * @param  ADCx ADC instance

  5025.   * @param  AWDy This parameter can be one of the following values:

  5026.   *         @arg @ref LL_ADC_AWD1

  5027.   *         @arg @ref LL_ADC_AWD2

  5028.   *         @arg @ref LL_ADC_AWD3

  5029.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  5030.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  5031.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  5032.   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF

  5033.   * @retval None

  5034.   */

  5035. __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)

  5036. {

  5037.   /* Set bits with content of parameter "AWDThresholdValue" with bits         */

  5038.   /* position in register and register position depending on parameters       */

  5039.   /* "AWDThresholdsHighLow" and "AWDy".                                       */

  5040.   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */

  5041.   /* containing other bits reserved for other purpose.                        */

  5042.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)

  5043.                                                              + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)

  5044.                                                              + (AWDThresholdsHighLow));

  5045. 

  5046.   MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);

  5047. }

  5048. 

  5049. /**

  5050.   * @brief  Get ADC analog watchdog threshold value of threshold high,

  5051.   *         threshold low or raw data with ADC thresholds high and low

  5052.   *         concatenated.

  5053.   * @note   In case of ADC resolution different of 12 bits,

  5054.   *         analog watchdog thresholds data require a specific shift.

  5055.   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().

  5056.   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n

  5057.   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n

  5058.   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n

  5059.   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n

  5060.   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n

  5061.   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds

  5062.   * @param  ADCx ADC instance

  5063.   * @param  AWDy This parameter can be one of the following values:

  5064.   *         @arg @ref LL_ADC_AWD1

  5065.   *         @arg @ref LL_ADC_AWD2

  5066.   *         @arg @ref LL_ADC_AWD3

  5067.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  5068.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  5069.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  5070.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF

  5071. */

  5072. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)

  5073. {

  5074.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)

  5075.                                                                    + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)

  5076.                                                                    + (AWDThresholdsHighLow));

  5077. 

  5078.   return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));

  5079. }

  5080. 

  5081. /**

  5082.   * @}

  5083.   */

  5084. 

  5085. /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling

  5086.   * @{

  5087.   */

  5088. 

  5089. /**

  5090.   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected

  5091.   *         (availability of ADC group injected depends on STM32 families).

  5092.   * @note   If both groups regular and injected are selected,

  5093.   *         specify behavior of ADC group injected interrupting

  5094.   *         group regular: when ADC group injected is triggered,

  5095.   *         the oversampling on ADC group regular is either

  5096.   *         temporary stopped and continued, or resumed from start

  5097.   *         (oversampler buffer reset).

  5098.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5099.   *         ADC state:

  5100.   *         ADC must be disabled or enabled without conversion on going

  5101.   *         on either groups regular or injected.

  5102.   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n

  5103.   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n

  5104.   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope

  5105.   * @param  ADCx ADC instance

  5106.   * @param  OvsScope This parameter can be one of the following values:

  5107.   *         @arg @ref LL_ADC_OVS_DISABLE

  5108.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED

  5109.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED

  5110.   *         @arg @ref LL_ADC_OVS_GRP_INJECTED

  5111.   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED

  5112.   * @retval None

  5113.   */

  5114. __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)

  5115. {

  5116.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);

  5117. }

  5118. 

  5119. /**

  5120.   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected

  5121.   *         (availability of ADC group injected depends on STM32 families).

  5122.   * @note   If both groups regular and injected are selected,

  5123.   *         specify behavior of ADC group injected interrupting

  5124.   *         group regular: when ADC group injected is triggered,

  5125.   *         the oversampling on ADC group regular is either

  5126.   *         temporary stopped and continued, or resumed from start

  5127.   *         (oversampler buffer reset).

  5128.   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n

  5129.   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n

  5130.   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope

  5131.   * @param  ADCx ADC instance

  5132.   * @retval Returned value can be one of the following values:

  5133.   *         @arg @ref LL_ADC_OVS_DISABLE

  5134.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED

  5135.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED

  5136.   *         @arg @ref LL_ADC_OVS_GRP_INJECTED

  5137.   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED

  5138.   */

  5139. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)

  5140. {

  5141.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));

  5142. }

  5143. 

  5144. /**

  5145.   * @brief  Set ADC oversampling discontinuous mode (triggered mode)

  5146.   *         on the selected ADC group.

  5147.   * @note   Number of oversampled conversions are done either in:

  5148.   *         - continuous mode (all conversions of oversampling ratio

  5149.   *           are done from 1 trigger)

  5150.   *         - discontinuous mode (each conversion of oversampling ratio

  5151.   *           needs a trigger)

  5152.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5153.   *         ADC state:

  5154.   *         ADC must be disabled or enabled without conversion on going

  5155.   *         on group regular.

  5156.   * @note   On this STM32 serie, oversampling discontinuous mode

  5157.   *         (triggered mode) can be used only when oversampling is

  5158.   *         set on group regular only and in resumed mode.

  5159.   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont

  5160.   * @param  ADCx ADC instance

  5161.   * @param  OverSamplingDiscont This parameter can be one of the following values:

  5162.   *         @arg @ref LL_ADC_OVS_REG_CONT

  5163.   *         @arg @ref LL_ADC_OVS_REG_DISCONT

  5164.   * @retval None

  5165.   */

  5166. __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)

  5167. {

  5168.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);

  5169. }

  5170. 

  5171. /**

  5172.   * @brief  Get ADC oversampling discontinuous mode (triggered mode)

  5173.   *         on the selected ADC group.

  5174.   * @note   Number of oversampled conversions are done either in:

  5175.   *         - continuous mode (all conversions of oversampling ratio

  5176.   *           are done from 1 trigger)

  5177.   *         - discontinuous mode (each conversion of oversampling ratio

  5178.   *           needs a trigger)

  5179.   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont

  5180.   * @param  ADCx ADC instance

  5181.   * @retval Returned value can be one of the following values:

  5182.   *         @arg @ref LL_ADC_OVS_REG_CONT

  5183.   *         @arg @ref LL_ADC_OVS_REG_DISCONT

  5184.   */

  5185. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)

  5186. {

  5187.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));

  5188. }

  5189. 

  5190. /**

  5191.   * @brief  Set ADC oversampling

  5192.   *         (impacting both ADC groups regular and injected)

  5193.   * @note   This function set the 2 items of oversampling configuration:

  5194.   *         - ratio

  5195.   *         - shift

  5196.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5197.   *         ADC state:

  5198.   *         ADC must be disabled or enabled without conversion on going

  5199.   *         on either groups regular or injected.

  5200.   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n

  5201.   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift

  5202.   * @param  ADCx ADC instance

  5203.   * @param  Ratio This parameter can be in the range from 1 to 1024.

  5204.   * @param  Shift This parameter can be one of the following values:

  5205.   *         @arg @ref LL_ADC_OVS_SHIFT_NONE

  5206.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1

  5207.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2

  5208.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3

  5209.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4

  5210.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5

  5211.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6

  5212.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7

  5213.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8

  5214.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9

  5215.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10

  5216.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11

  5217.   * @retval None

  5218.   */

  5219. __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)

  5220. {

  5221.   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));

  5222. }

  5223. 

  5224. /**

  5225.   * @brief  Get ADC oversampling ratio

  5226.   *        (impacting both ADC groups regular and injected)

  5227.   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio

  5228.   * @param  ADCx ADC instance

  5229.   * @retval Ratio This parameter can be in the from 1 to 1024.

  5230. */

  5231. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)

  5232. {

  5233.   return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR))+(1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);

  5234. }

  5235. 

  5236. /**

  5237.   * @brief  Get ADC oversampling shift

  5238.   *        (impacting both ADC groups regular and injected)

  5239.   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift

  5240.   * @param  ADCx ADC instance

  5241.   * @retval Shift This parameter can be one of the following values:

  5242.   *         @arg @ref LL_ADC_OVS_SHIFT_NONE

  5243.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1

  5244.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2

  5245.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3

  5246.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4

  5247.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5

  5248.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6

  5249.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7

  5250.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8

  5251.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9

  5252.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10

  5253.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11

  5254. */

  5255. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)

  5256. {

  5257.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));

  5258. }

  5259. 

  5260. /**

  5261.   * @}

  5262.   */

  5263. 

  5264. /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode

  5265.   * @{

  5266.   */

  5267. /**

  5268.   * @brief  Set ADC boost mode.

  5269.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5270.   *         ADC state:

  5271.   *         ADC boost must be configured, without calibration on going, without conversion

  5272.   *         on going on group regular.

  5273.   * @rmtoll CR  BOOST      LL_ADC_SetBoostMode

  5274.   * @param  ADCx ADC instance

  5275.   * @param  BoostMode This parameter can be one of the following values:

  5276.   *         @arg @ref LL_ADC_BOOST_MODE_6MHZ25

  5277.   *         @arg @ref LL_ADC_BOOST_MODE_12MHZ5

  5278.   *         @arg @ref LL_ADC_BOOST_MODE_20MHZ

  5279.   *         @arg @ref LL_ADC_BOOST_MODE_25MHZ

  5280.   *         @arg @ref LL_ADC_BOOST_MODE_50MHZ

  5281.   * @retval None

  5282.   */

  5283. __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)

  5284. {

  5285.   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */

  5286.   {

  5287.     MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));

  5288.   }

  5289.   else /* Cut 2.x */

  5290.   {

  5291.     MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));

  5292.   }

  5293. }

  5294. 

  5295. /**

  5296.   * @brief  Get ADC boost mode.

  5297.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5298.   *         ADC state:

  5299.   *         ADC boost must be configured, without calibration on going, without conversion

  5300.   *         on going on group regular.

  5301.   * @rmtoll CR  BOOST      LL_ADC_GetBoostMode

  5302.   * @param  ADCx ADC instance

  5303.   * @retval 0: Boost disabled 1: Boost enabled

  5304.   */

  5305. __STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)

  5306. {

  5307.   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */

  5308.   {

  5309.     return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);

  5310.   }

  5311.   else /* Cut 2.x */

  5312.   {

  5313.     return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);

  5314.   }

  5315. }

  5316. 

  5317. /**

  5318.   * @brief  Set ADC multimode configuration to operate in independent mode

  5319.   *         or multimode (for devices with several ADC instances).

  5320.   * @note   If multimode configuration: the selected ADC instance is

  5321.   *         either master or slave depending on hardware.

  5322.   *         Refer to reference manual.

  5323.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5324.   *         ADC state:

  5325.   *         All ADC instances of the ADC common group must be disabled.

  5326.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  5327.   *         ADC instance or by using helper macro

  5328.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  5329.   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode

  5330.   * @param  ADCxy_COMMON ADC common instance

  5331.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5332.   * @param  Multimode This parameter can be one of the following values:

  5333.   *         @arg @ref LL_ADC_MULTI_INDEPENDENT

  5334.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT

  5335.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL

  5336.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT

  5337.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN

  5338.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM

  5339.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT

  5340.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

  5341.   * @retval None

  5342.   */

  5343. __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)

  5344. {

  5345.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);

  5346. }

  5347. 

  5348. /**

  5349.   * @brief  Get ADC multimode configuration to operate in independent mode

  5350.   *         or multimode (for devices with several ADC instances).

  5351.   * @note   If multimode configuration: the selected ADC instance is

  5352.   *         either master or slave depending on hardware.

  5353.   *         Refer to reference manual.

  5354.   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode

  5355.   * @param  ADCxy_COMMON ADC common instance

  5356.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5357.   * @retval Returned value can be one of the following values:

  5358.   *         @arg @ref LL_ADC_MULTI_INDEPENDENT

  5359.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT

  5360.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL

  5361.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT

  5362.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN

  5363.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM

  5364.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT

  5365.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

  5366.   */

  5367. __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)

  5368. {

  5369.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));

  5370. }

  5371. 

  5372. /**

  5373.   * @brief  Set ADC multimode conversion data transfer: no transfer

  5374.   *         or transfer by DMA.

  5375.   * @note   If ADC multimode transfer by DMA is not selected:

  5376.   *         each ADC uses its own DMA channel, with its individual

  5377.   *         DMA transfer settings.

  5378.   *         If ADC multimode transfer by DMA is selected:

  5379.   *         One DMA channel is used for both ADC (DMA of ADC master)

  5380.   *         Specifies the DMA requests mode:

  5381.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  5382.   *           when number of DMA data transfers (number of

  5383.   *           ADC conversions) is reached.

  5384.   *           This ADC mode is intended to be used with DMA mode non-circular.

  5385.   *         - Unlimited mode: DMA transfer requests are unlimited,

  5386.   *           whatever number of DMA data transfers (number of

  5387.   *           ADC conversions).

  5388.   *           This ADC mode is intended to be used with DMA mode circular.

  5389.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  5390.   *         mode non-circular:

  5391.   *         when DMA transfers size will be reached, DMA will stop transfers of

  5392.   *         ADC conversions data ADC will raise an overrun error

  5393.   *         (overrun flag and interruption if enabled).

  5394.   * @note   How to retrieve multimode conversion data:

  5395.   *         Whatever multimode transfer by DMA setting: using function

  5396.   *         @ref LL_ADC_REG_ReadMultiConversionData32().

  5397.   *         If ADC multimode transfer by DMA is selected: conversion data

  5398.   *         is a raw data with ADC master and slave concatenated.

  5399.   *         A macro is available to get the conversion data of

  5400.   *         ADC master or ADC slave: see helper macro

  5401.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  5402.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5403.   *         ADC state:

  5404.   *         All ADC instances of the ADC common group must be disabled

  5405.   *         or enabled without conversion on going on group regular.

  5406.   * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDMATransfer\n

  5407.   * @param  ADCxy_COMMON ADC common instance

  5408.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5409.   * @param  MultiDMATransfer This parameter can be one of the following values:

  5410.   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC

  5411.   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B

  5412.   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B

  5413.   * @retval None

  5414.   */

  5415. __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)

  5416. {

  5417.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);

  5418. }

  5419. 

  5420. /**

  5421.   * @brief  Get ADC multimode conversion data transfer: no transfer

  5422.   *         or transfer by DMA.

  5423.   * @note   If ADC multimode transfer by DMA is not selected:

  5424.   *         each ADC uses its own DMA channel, with its individual

  5425.   *         DMA transfer settings.

  5426.   *         If ADC multimode transfer by DMA is selected:

  5427.   *         One DMA channel is used for both ADC (DMA of ADC master)

  5428.   *         Specifies the DMA requests mode:

  5429.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  5430.   *           when number of DMA data transfers (number of

  5431.   *           ADC conversions) is reached.

  5432.   *           This ADC mode is intended to be used with DMA mode non-circular.

  5433.   *         - Unlimited mode: DMA transfer requests are unlimited,

  5434.   *           whatever number of DMA data transfers (number of

  5435.   *           ADC conversions).

  5436.   *           This ADC mode is intended to be used with DMA mode circular.

  5437.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  5438.   *         mode non-circular:

  5439.   *         when DMA transfers size will be reached, DMA will stop transfers of

  5440.   *         ADC conversions data ADC will raise an overrun error

  5441.   *         (overrun flag and interruption if enabled).

  5442.   * @note   How to retrieve multimode conversion data:

  5443.   *         Whatever multimode transfer by DMA setting: using function

  5444.   *         @ref LL_ADC_REG_ReadMultiConversionData32().

  5445.   *         If ADC multimode transfer by DMA is selected: conversion data

  5446.   *         is a raw data with ADC master and slave concatenated.

  5447.   *         A macro is available to get the conversion data of

  5448.   *         ADC master or ADC slave: see helper macro

  5449.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  5450.   * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDMATransfer\n

  5451.   * @param  ADCxy_COMMON ADC common instance

  5452.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5453.   * @retval Returned value can be one of the following values:

  5454.   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC

  5455.   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B

  5456.   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B

  5457.   */

  5458. __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)

  5459. {

  5460.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));

  5461. }

  5462. 

  5463. /**

  5464.   * @brief  Set ADC multimode delay between 2 sampling phases.

  5465.   * @note   The sampling delay range depends on ADC resolution:

  5466.   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.

  5467.   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.

  5468.   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.

  5469.   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.

  5470.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5471.   *         ADC state:

  5472.   *         All ADC instances of the ADC common group must be disabled.

  5473.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  5474.   *         ADC instance or by using helper macro helper macro

  5475.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  5476.   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay

  5477.   * @param  ADCxy_COMMON ADC common instance

  5478.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5479.   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:

  5480.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5

  5481.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5

  5482.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5

  5483.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)

  5484.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS

  5485.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)

  5486.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS

  5487.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (3)

  5488.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)

  5489.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS

  5490.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)

  5491.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (6)

  5492.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (7)

  5493.   *

  5494.   *         (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.

  5495.   *         (2) Parameter available only if ADC resolution is 16, 14 or 12  bits.

  5496.   *         (3) Parameter available only if ADC resolution is 10 or 8 bits.

  5497.   *         (4) Parameter available only if ADC resolution is 16 or 14 bits.

  5498.   *         (5) Parameter available only if ADC resolution is 16 bits.

  5499.   *         (6) Parameter available only if ADC resolution is 12 bits.

  5500.   *         (7) Parameter available only if ADC resolution is 16 or 14 bits.

  5501.   * @retval None

  5502.   */

  5503. __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)

  5504. {

  5505.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);

  5506. }

  5507. 

  5508. /**

  5509.   * @brief  Get ADC multimode delay between 2 sampling phases.

  5510.   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay

  5511.   * @param  ADCxy_COMMON ADC common instance

  5512.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5513.   * @retval Returned value can be one of the following values:

  5514.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5

  5515.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5

  5516.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5

  5517.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)

  5518.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS

  5519.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)

  5520.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS

  5521.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (3)

  5522.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)

  5523.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS

  5524.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)

  5525.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (6)

  5526.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (7)

  5527.   *

  5528.   *         (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.

  5529.   *         (2) Parameter available only if ADC resolution is 16, 14 or 12  bits.

  5530.   *         (3) Parameter available only if ADC resolution is 10 or 8 bits.

  5531.   *         (4) Parameter available only if ADC resolution is 16 or 14 bits.

  5532.   *         (5) Parameter available only if ADC resolution is 16 bits.

  5533.   *         (6) Parameter available only if ADC resolution is 12 bits.

  5534.   *         (7) Parameter available only if ADC resolution is 16 or 14 bits.

  5535.   */

  5536. __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)

  5537. {

  5538.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));

  5539. }

  5540. 

  5541. /**

  5542.   * @}

  5543.   */

  5544. /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance

  5545.   * @{

  5546.   */

  5547. 

  5548. /**

  5549.   * @brief  Put ADC instance in deep power down state.

  5550.   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down

  5551.   *         state, the internal analog calibration is lost. After exiting from

  5552.   *         deep power down, calibration must be relaunched or calibration factor

  5553.   *         (preliminarily saved) must be set back into calibration register.

  5554.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5555.   *         ADC state:

  5556.   *         ADC must be ADC disabled.

  5557.   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown

  5558.   * @param  ADCx ADC instance

  5559.   * @retval None

  5560.   */

  5561. __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)

  5562. {

  5563.   /* Note: Write register with some additional bits forced to state reset     */

  5564.   /*       instead of modifying only the selected bit for this function,      */

  5565.   /*       to not interfere with bits with HW property "rs".                  */

  5566.   MODIFY_REG(ADCx->CR,

  5567.              ADC_CR_BITS_PROPERTY_RS,

  5568.              ADC_CR_DEEPPWD);

  5569. }

  5570. 

  5571. /**

  5572.   * @brief  Disable ADC deep power down mode.

  5573.   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down

  5574.   *         state, the internal analog calibration is lost. After exiting from

  5575.   *         deep power down, calibration must be relaunched or calibration factor

  5576.   *         (preliminarily saved) must be set back into calibration register.

  5577.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5578.   *         ADC state:

  5579.   *         ADC must be ADC disabled.

  5580.   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown

  5581.   * @param  ADCx ADC instance

  5582.   * @retval None

  5583.   */

  5584. __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)

  5585. {

  5586.   /* Note: Write register with some additional bits forced to state reset     */

  5587.   /*       instead of modifying only the selected bit for this function,      */

  5588.   /*       to not interfere with bits with HW property "rs".                  */

  5589.   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));

  5590. }

  5591. 

  5592. /**

  5593.   * @brief  Get the selected ADC instance deep power down state.

  5594.   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled

  5595.   * @param  ADCx ADC instance

  5596.   * @retval 0: deep power down is disabled, 1: deep power down is enabled.

  5597.   */

  5598. __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)

  5599. {

  5600.   return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);

  5601. }

  5602. 

  5603. /**

  5604.   * @brief  Enable ADC instance internal voltage regulator.

  5605.   * @note   On this STM32 serie, after ADC internal voltage regulator enable,

  5606.   *         a delay for ADC internal voltage regulator stabilization

  5607.   *         is required before performing a ADC calibration or ADC enable.

  5608.   *         Refer to device datasheet, parameter tADCVREG_STUP.

  5609.   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.

  5610.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5611.   *         ADC state:

  5612.   *         ADC must be ADC disabled.

  5613.   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator

  5614.   * @param  ADCx ADC instance

  5615.   * @retval None

  5616.   */

  5617. __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)

  5618. {

  5619.   /* Note: Write register with some additional bits forced to state reset     */

  5620.   /*       instead of modifying only the selected bit for this function,      */

  5621.   /*       to not interfere with bits with HW property "rs".                  */

  5622.   MODIFY_REG(ADCx->CR,

  5623.              ADC_CR_BITS_PROPERTY_RS,

  5624.              ADC_CR_ADVREGEN);

  5625. }

  5626. 

  5627. /**

  5628.   * @brief  Disable ADC internal voltage regulator.

  5629.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5630.   *         ADC state:

  5631.   *         ADC must be ADC disabled.

  5632.   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator

  5633.   * @param  ADCx ADC instance

  5634.   * @retval None

  5635.   */

  5636. __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)

  5637. {

  5638.   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));

  5639. }

  5640. 

  5641. /**

  5642.   * @brief  Get the selected ADC instance internal voltage regulator state.

  5643.   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled

  5644.   * @param  ADCx ADC instance

  5645.   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.

  5646.   */

  5647. __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)

  5648. {

  5649.   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);

  5650. }

  5651. 

  5652. /**

  5653.   * @brief  Enable the selected ADC instance.

  5654.   * @note   On this STM32 serie, after ADC enable, a delay for

  5655.   *         ADC internal analog stabilization is required before performing a

  5656.   *         ADC conversion start.

  5657.   *         Refer to device datasheet, parameter tSTAB.

  5658.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  5659.   *         is enabled and when conversion clock is active.

  5660.   *         (not only core clock: this ADC has a dual clock domain)

  5661.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5662.   *         ADC state:

  5663.   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.

  5664.   * @rmtoll CR       ADEN           LL_ADC_Enable

  5665.   * @param  ADCx ADC instance

  5666.   * @retval None

  5667.   */

  5668. __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)

  5669. {

  5670.   /* Note: Write register with some additional bits forced to state reset     */

  5671.   /*       instead of modifying only the selected bit for this function,      */

  5672.   /*       to not interfere with bits with HW property "rs".                  */

  5673.   MODIFY_REG(ADCx->CR,

  5674.              ADC_CR_BITS_PROPERTY_RS,

  5675.              ADC_CR_ADEN);

  5676. }

  5677. 

  5678. /**

  5679.   * @brief  Disable the selected ADC instance.

  5680.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5681.   *         ADC state:

  5682.   *         ADC must be not disabled. Must be enabled without conversion on going

  5683.   *         on either groups regular or injected.

  5684.   * @rmtoll CR       ADDIS          LL_ADC_Disable

  5685.   * @param  ADCx ADC instance

  5686.   * @retval None

  5687.   */

  5688. __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)

  5689. {

  5690.   /* Note: Write register with some additional bits forced to state reset     */

  5691.   /*       instead of modifying only the selected bit for this function,      */

  5692.   /*       to not interfere with bits with HW property "rs".                  */

  5693.   MODIFY_REG(ADCx->CR,

  5694.              ADC_CR_BITS_PROPERTY_RS,

  5695.              ADC_CR_ADDIS);

  5696. }

  5697. 

  5698. /**

  5699.   * @brief  Get the selected ADC instance enable state.

  5700.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  5701.   *         is enabled and when conversion clock is active.

  5702.   *         (not only core clock: this ADC has a dual clock domain)

  5703.   * @rmtoll CR       ADEN           LL_ADC_IsEnabled

  5704.   * @param  ADCx ADC instance

  5705.   * @retval 0: ADC is disabled, 1: ADC is enabled.

  5706.   */

  5707. __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)

  5708. {

  5709.   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);

  5710. }

  5711. 

  5712. /**

  5713.   * @brief  Get the selected ADC instance disable state.

  5714.   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing

  5715.   * @param  ADCx ADC instance

  5716.   * @retval 0: no ADC disable command on going.

  5717.   */

  5718. __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)

  5719. {

  5720.   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);

  5721. }

  5722. 

  5723. /**

  5724.   * @brief  Start ADC calibration in the mode single-ended

  5725.   *         or differential (for devices with differential mode available).

  5726.   * @note   On this STM32 serie, a minimum number of ADC clock cycles

  5727.   *         are required between ADC end of calibration and ADC enable.

  5728.   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.

  5729.   * @note   Calibration duration:

  5730.   *         - Calibration of offset: 520 ADC clock cycles

  5731.   *         - Calibration of linearity: 131072 ADC clock cycles

  5732.   * @note   For devices with differential mode available:

  5733.   *         Calibration of offset is specific to each of

  5734.   *         single-ended and differential modes

  5735.   *         (calibration run must be performed for each of these

  5736.   *         differential modes, if used afterwards and if the application

  5737.   *         requires their calibration).

  5738.   *         Calibration of linearity is common to both

  5739.   *         single-ended and differential modes

  5740.   *         (calibration run can be performed only once).

  5741.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5742.   *         ADC state:

  5743.   *         ADC must be ADC disabled.

  5744.   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n

  5745.   *         CR       ADCALDIF       LL_ADC_StartCalibration\n

  5746.   *         CR       ADCALLIN       LL_ADC_StartCalibration

  5747.   * @param  ADCx ADC instance

  5748.   * @param  CalibrationMode This parameter can be one of the following values:

  5749.   *         @arg @ref LL_ADC_CALIB_OFFSET

  5750.   *         @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY

  5751.   * @param  SingleDiff This parameter can be one of the following values:

  5752.   *         @arg @ref LL_ADC_SINGLE_ENDED

  5753.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  5754.   * @retval None

  5755.   */

  5756. __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)

  5757. {

  5758.   /* Note: Write register with some additional bits forced to state reset     */

  5759.   /*       instead of modifying only the selected bit for this function,      */

  5760.   /*       to not interfere with bits with HW property "rs".                  */

  5761.   MODIFY_REG(ADCx->CR,

  5762.              ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,

  5763.              ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));

  5764. }

  5765. 

  5766. /**

  5767.   * @brief  Get ADC calibration state.

  5768.   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing

  5769.   * @param  ADCx ADC instance

  5770.   * @retval 0: calibration complete, 1: calibration in progress.

  5771.   */

  5772. __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)

  5773. {

  5774.   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);

  5775. }

  5776. 

  5777. /**

  5778.   * @}

  5779.   */

  5780. 

  5781. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular

  5782.   * @{

  5783.   */

  5784. 

  5785. /**

  5786.   * @brief  Start ADC group regular conversion.

  5787.   * @note   On this STM32 serie, this function is relevant for both

  5788.   *         internal trigger (SW start) and external trigger:

  5789.   *         - If ADC trigger has been set to software start, ADC conversion

  5790.   *           starts immediately.

  5791.   *         - If ADC trigger has been set to external trigger, ADC conversion

  5792.   *           will start at next trigger event (on the selected trigger edge)

  5793.   *           following the ADC start conversion command.

  5794.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5795.   *         ADC state:

  5796.   *         ADC must be enabled without conversion on going on group regular,

  5797.   *         without conversion stop command on going on group regular,

  5798.   *         without ADC disable command on going.

  5799.   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion

  5800.   * @param  ADCx ADC instance

  5801.   * @retval None

  5802.   */

  5803. __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)

  5804. {

  5805.   /* Note: Write register with some additional bits forced to state reset     */

  5806.   /*       instead of modifying only the selected bit for this function,      */

  5807.   /*       to not interfere with bits with HW property "rs".                  */

  5808.   MODIFY_REG(ADCx->CR,

  5809.              ADC_CR_BITS_PROPERTY_RS,

  5810.              ADC_CR_ADSTART);

  5811. }

  5812. 

  5813. /**

  5814.   * @brief  Stop ADC group regular conversion.

  5815.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5816.   *         ADC state:

  5817.   *         ADC must be enabled with conversion on going on group regular,

  5818.   *         without ADC disable command on going.

  5819.   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion

  5820.   * @param  ADCx ADC instance

  5821.   * @retval None

  5822.   */

  5823. __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)

  5824. {

  5825.   /* Note: Write register with some additional bits forced to state reset     */

  5826.   /*       instead of modifying only the selected bit for this function,      */

  5827.   /*       to not interfere with bits with HW property "rs".                  */

  5828.   MODIFY_REG(ADCx->CR,

  5829.              ADC_CR_BITS_PROPERTY_RS,

  5830.              ADC_CR_ADSTP);

  5831. }

  5832. 

  5833. /**

  5834.   * @brief  Get ADC group regular conversion state.

  5835.   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing

  5836.   * @param  ADCx ADC instance

  5837.   * @retval 0: no conversion is on going on ADC group regular.

  5838.   */

  5839. __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)

  5840. {

  5841.   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);

  5842. }

  5843. 

  5844. /**

  5845.   * @brief  Get ADC group regular command of conversion stop state

  5846.   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing

  5847.   * @param  ADCx ADC instance

  5848.   * @retval 0: no command of conversion stop is on going on ADC group regular.

  5849.   */

  5850. __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)

  5851. {

  5852.   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);

  5853. }

  5854. 

  5855. /**

  5856.   * @brief  Get ADC group regular conversion data, range fit for

  5857.   *         all ADC configurations: all ADC resolutions and

  5858.   *         all oversampling increased data width (for devices

  5859.   *         with feature oversampling).

  5860.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32

  5861.   * @param  ADCx ADC instance

  5862.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  5863.   */

  5864. __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)

  5865. {

  5866.   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5867. }

  5868. 

  5869. /**

  5870.   * @brief  Get ADC group regular conversion data, range fit for

  5871.   *         ADC resolution 16 bits.

  5872.   * @note   For devices with feature oversampling: Oversampling

  5873.   *         can increase data width, function for extended range

  5874.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5875.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData16

  5876.   * @param  ADCx ADC instance

  5877.   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF

  5878.   */

  5879. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)

  5880. {

  5881.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5882. }

  5883. 

  5884. /**

  5885.   * @brief  Get ADC group regular conversion data, range fit for

  5886.   *         ADC resolution 14 bits.

  5887.   * @note   For devices with feature oversampling: Oversampling

  5888.   *         can increase data width, function for extended range

  5889.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5890.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData14

  5891.   * @param  ADCx ADC instance

  5892.   * @retval Value between Min_Data=0x00 and Max_Data=0x3FF

  5893.   */

  5894. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)

  5895. {

  5896.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5897. }

  5898. 

  5899. /**

  5900.   * @brief  Get ADC group regular conversion data, range fit for

  5901.   *         ADC resolution 12 bits.

  5902.   * @note   For devices with feature oversampling: Oversampling

  5903.   *         can increase data width, function for extended range

  5904.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5905.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12

  5906.   * @param  ADCx ADC instance

  5907.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  5908.   */

  5909. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)

  5910. {

  5911.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5912. }

  5913. 

  5914. /**

  5915.   * @brief  Get ADC group regular conversion data, range fit for

  5916.   *         ADC resolution 10 bits.

  5917.   * @note   For devices with feature oversampling: Oversampling

  5918.   *         can increase data width, function for extended range

  5919.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5920.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10

  5921.   * @param  ADCx ADC instance

  5922.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  5923.   */

  5924. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)

  5925. {

  5926.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5927. }

  5928. 

  5929. /**

  5930.   * @brief  Get ADC group regular conversion data, range fit for

  5931.   *         ADC resolution 8 bits.

  5932.   * @note   For devices with feature oversampling: Oversampling

  5933.   *         can increase data width, function for extended range

  5934.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5935.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8

  5936.   * @param  ADCx ADC instance

  5937.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  5938.   */

  5939. __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)

  5940. {

  5941.   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5942. }

  5943. /**

  5944.   * @brief  Get ADC multimode conversion data of ADC master, ADC slave

  5945.   *         or raw data with ADC master and slave concatenated.

  5946.   * @note   If raw data with ADC master and slave concatenated is retrieved,

  5947.   *         a macro is available to get the conversion data of

  5948.   *         ADC master or ADC slave: see helper macro

  5949.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  5950.   *         (however this macro is mainly intended for multimode

  5951.   *         transfer by DMA, because this function can do the same

  5952.   *         by getting multimode conversion data of ADC master or ADC slave

  5953.   *         separately).

  5954.   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n

  5955.   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32

  5956.   * @param  ADCxy_COMMON ADC common instance

  5957.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5958.   * @param  ConversionData This parameter can be one of the following values:

  5959.   *         @arg @ref LL_ADC_MULTI_MASTER

  5960.   *         @arg @ref LL_ADC_MULTI_SLAVE

  5961.   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE

  5962.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  5963.   */

  5964. __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)

  5965. {

  5966.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,

  5967.                              ConversionData)

  5968.                     >> (POSITION_VAL(ConversionData) & 0x1FUL)

  5969.                    );

  5970. }

  5971. 

  5972. /**

  5973.   * @}

  5974.   */

  5975. 

  5976. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected

  5977.   * @{

  5978.   */

  5979. 

  5980. /**

  5981.   * @brief  Start ADC group injected conversion.

  5982.   * @note   On this STM32 serie, this function is relevant for both

  5983.   *         internal trigger (SW start) and external trigger:

  5984.   *         - If ADC trigger has been set to software start, ADC conversion

  5985.   *           starts immediately.

  5986.   *         - If ADC trigger has been set to external trigger, ADC conversion

  5987.   *           will start at next trigger event (on the selected trigger edge)

  5988.   *           following the ADC start conversion command.

  5989.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5990.   *         ADC state:

  5991.   *         ADC must be enabled without conversion on going on group injected,

  5992.   *         without conversion stop command on going on group injected,

  5993.   *         without ADC disable command on going.

  5994.   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion

  5995.   * @param  ADCx ADC instance

  5996.   * @retval None

  5997.   */

  5998. __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)

  5999. {

  6000.   /* Note: Write register with some additional bits forced to state reset     */

  6001.   /*       instead of modifying only the selected bit for this function,      */

  6002.   /*       to not interfere with bits with HW property "rs".                  */

  6003.   MODIFY_REG(ADCx->CR,

  6004.              ADC_CR_BITS_PROPERTY_RS,

  6005.              ADC_CR_JADSTART);

  6006. }

  6007. 

  6008. /**

  6009.   * @brief  Stop ADC group injected conversion.

  6010.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6011.   *         ADC state:

  6012.   *         ADC must be enabled with conversion on going on group injected,

  6013.   *         without ADC disable command on going.

  6014.   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion

  6015.   * @param  ADCx ADC instance

  6016.   * @retval None

  6017.   */

  6018. __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)

  6019. {

  6020.   /* Note: Write register with some additional bits forced to state reset     */

  6021.   /*       instead of modifying only the selected bit for this function,      */

  6022.   /*       to not interfere with bits with HW property "rs".                  */

  6023.   MODIFY_REG(ADCx->CR,

  6024.              ADC_CR_BITS_PROPERTY_RS,

  6025.              ADC_CR_JADSTP);

  6026. }

  6027. 

  6028. /**

  6029.   * @brief  Get ADC group injected conversion state.

  6030.   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing

  6031.   * @param  ADCx ADC instance

  6032.   * @retval 0: no conversion is on going on ADC group injected.

  6033.   */

  6034. __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)

  6035. {

  6036.   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);

  6037. }

  6038. 

  6039. /**

  6040.   * @brief  Get ADC group injected command of conversion stop state

  6041.   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing

  6042.   * @param  ADCx ADC instance

  6043.   * @retval 0: no command of conversion stop is on going on ADC group injected.

  6044.   */

  6045. __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)

  6046. {

  6047.   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);

  6048. }

  6049. 

  6050. /**

  6051.   * @brief  Get ADC group regular conversion data, range fit for

  6052.   *         all ADC configurations: all ADC resolutions and

  6053.   *         all oversampling increased data width (for devices

  6054.   *         with feature oversampling).

  6055.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n

  6056.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n

  6057.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n

  6058.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32

  6059.   * @param  ADCx ADC instance

  6060.   * @param  Rank This parameter can be one of the following values:

  6061.   *         @arg @ref LL_ADC_INJ_RANK_1

  6062.   *         @arg @ref LL_ADC_INJ_RANK_2

  6063.   *         @arg @ref LL_ADC_INJ_RANK_3

  6064.   *         @arg @ref LL_ADC_INJ_RANK_4

  6065.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  6066.   */

  6067. __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)

  6068. {

  6069.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6070. 

  6071.   return (uint32_t)(READ_BIT(*preg,

  6072.                              ADC_JDR1_JDATA)

  6073.                    );

  6074. }

  6075. 

  6076. /**

  6077.   * @brief  Get ADC group injected conversion data, range fit for

  6078.   *         ADC resolution 16 bits.

  6079.   * @note   For devices with feature oversampling: Oversampling

  6080.   *         can increase data width, function for extended range

  6081.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6082.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData16\n

  6083.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData16\n

  6084.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData16\n

  6085.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData16

  6086.   * @param  ADCx ADC instance

  6087.   * @param  Rank This parameter can be one of the following values:

  6088.   *         @arg @ref LL_ADC_INJ_RANK_1

  6089.   *         @arg @ref LL_ADC_INJ_RANK_2

  6090.   *         @arg @ref LL_ADC_INJ_RANK_3

  6091.   *         @arg @ref LL_ADC_INJ_RANK_4

  6092.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF

  6093.   */

  6094. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)

  6095. {

  6096.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6097. 

  6098.   return (uint16_t)(READ_BIT(*preg,

  6099.                              ADC_JDR1_JDATA)

  6100.                    );

  6101. }

  6102. 

  6103. /**

  6104.   * @brief  Get ADC group injected conversion data, range fit for

  6105.   *         ADC resolution 14 bits.

  6106.   * @note   For devices with feature oversampling: Oversampling

  6107.   *         can increase data width, function for extended range

  6108.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6109.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData14\n

  6110.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData14\n

  6111.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData14\n

  6112.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData14

  6113.   * @param  ADCx ADC instance

  6114.   * @param  Rank This parameter can be one of the following values:

  6115.   *         @arg @ref LL_ADC_INJ_RANK_1

  6116.   *         @arg @ref LL_ADC_INJ_RANK_2

  6117.   *         @arg @ref LL_ADC_INJ_RANK_3

  6118.   *         @arg @ref LL_ADC_INJ_RANK_4

  6119.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF

  6120.   */

  6121. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)

  6122. {

  6123.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6124. 

  6125.   return (uint16_t)(READ_BIT(*preg,

  6126.                              ADC_JDR1_JDATA)

  6127.                    );

  6128. }

  6129. 

  6130. /**

  6131.   * @brief  Get ADC group injected conversion data, range fit for

  6132.   *         ADC resolution 12 bits.

  6133.   * @note   For devices with feature oversampling: Oversampling

  6134.   *         can increase data width, function for extended range

  6135.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6136.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n

  6137.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n

  6138.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n

  6139.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12

  6140.   * @param  ADCx ADC instance

  6141.   * @param  Rank This parameter can be one of the following values:

  6142.   *         @arg @ref LL_ADC_INJ_RANK_1

  6143.   *         @arg @ref LL_ADC_INJ_RANK_2

  6144.   *         @arg @ref LL_ADC_INJ_RANK_3

  6145.   *         @arg @ref LL_ADC_INJ_RANK_4

  6146.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  6147.   */

  6148. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)

  6149. {

  6150.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6151. 

  6152.   return (uint16_t)(READ_BIT(*preg,

  6153.                              ADC_JDR1_JDATA)

  6154.                    );

  6155. }

  6156. 

  6157. /**

  6158.   * @brief  Get ADC group injected conversion data, range fit for

  6159.   *         ADC resolution 10 bits.

  6160.   * @note   For devices with feature oversampling: Oversampling

  6161.   *         can increase data width, function for extended range

  6162.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6163.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n

  6164.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n

  6165.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n

  6166.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10

  6167.   * @param  ADCx ADC instance

  6168.   * @param  Rank This parameter can be one of the following values:

  6169.   *         @arg @ref LL_ADC_INJ_RANK_1

  6170.   *         @arg @ref LL_ADC_INJ_RANK_2

  6171.   *         @arg @ref LL_ADC_INJ_RANK_3

  6172.   *         @arg @ref LL_ADC_INJ_RANK_4

  6173.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  6174.   */

  6175. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)

  6176. {

  6177.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6178. 

  6179.   return (uint16_t)(READ_BIT(*preg,

  6180.                              ADC_JDR1_JDATA)

  6181.                    );

  6182. }

  6183. 

  6184. /**

  6185.   * @brief  Get ADC group injected conversion data, range fit for

  6186.   *         ADC resolution 8 bits.

  6187.   * @note   For devices with feature oversampling: Oversampling

  6188.   *         can increase data width, function for extended range

  6189.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6190.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n

  6191.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n

  6192.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n

  6193.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8

  6194.   * @param  ADCx ADC instance

  6195.   * @param  Rank This parameter can be one of the following values:

  6196.   *         @arg @ref LL_ADC_INJ_RANK_1

  6197.   *         @arg @ref LL_ADC_INJ_RANK_2

  6198.   *         @arg @ref LL_ADC_INJ_RANK_3

  6199.   *         @arg @ref LL_ADC_INJ_RANK_4

  6200.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  6201.   */

  6202. __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)

  6203. {

  6204.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6205. 

  6206.   return (uint8_t)(READ_BIT(*preg,

  6207.                             ADC_JDR1_JDATA)

  6208.                   );

  6209. }

  6210. 

  6211. /**

  6212.   * @}

  6213.   */

  6214. 

  6215. /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management

  6216.   * @{

  6217.   */

  6218. 

  6219. /**

  6220.   * @brief  Get flag ADC ready.

  6221.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  6222.   *         is enabled and when conversion clock is active.

  6223.   *         (not only core clock: this ADC has a dual clock domain)

  6224.   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY

  6225.   * @param  ADCx ADC instance

  6226.   * @retval State of bit (1 or 0).

  6227.   */

  6228. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)

  6229. {

  6230.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);

  6231. }

  6232. 

  6233. /**

  6234.   * @brief  Get flag ADC group regular end of unitary conversion.

  6235.   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC

  6236.   * @param  ADCx ADC instance

  6237.   * @retval State of bit (1 or 0).

  6238.   */

  6239. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)

  6240. {

  6241.   return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);

  6242. }

  6243. 

  6244. /**

  6245.   * @brief  Get flag ADC group regular end of sequence conversions.

  6246.   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS

  6247.   * @param  ADCx ADC instance

  6248.   * @retval State of bit (1 or 0).

  6249.   */

  6250. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)

  6251. {

  6252.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);

  6253. }

  6254. 

  6255. /**

  6256.   * @brief  Get flag ADC group regular overrun.

  6257.   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR

  6258.   * @param  ADCx ADC instance

  6259.   * @retval State of bit (1 or 0).

  6260.   */

  6261. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)

  6262. {

  6263.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);

  6264. }

  6265. 

  6266. /**

  6267.   * @brief  Get flag ADC group regular end of sampling phase.

  6268.   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP

  6269.   * @param  ADCx ADC instance

  6270.   * @retval State of bit (1 or 0).

  6271.   */

  6272. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)

  6273. {

  6274.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);

  6275. }

  6276. 

  6277. /**

  6278.   * @brief  Get flag ADC group injected end of unitary conversion.

  6279.   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC

  6280.   * @param  ADCx ADC instance

  6281.   * @retval State of bit (1 or 0).

  6282.   */

  6283. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)

  6284. {

  6285.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);

  6286. }

  6287. 

  6288. /**

  6289.   * @brief  Get flag ADC group injected end of sequence conversions.

  6290.   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS

  6291.   * @param  ADCx ADC instance

  6292.   * @retval State of bit (1 or 0).

  6293.   */

  6294. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)

  6295. {

  6296.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);

  6297. }

  6298. 

  6299. /**

  6300.   * @brief  Get flag ADC group injected contexts queue overflow.

  6301.   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF

  6302.   * @param  ADCx ADC instance

  6303.   * @retval State of bit (1 or 0).

  6304.   */

  6305. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)

  6306. {

  6307.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);

  6308. }

  6309. 

  6310. /**

  6311.   * @brief  Get flag ADC analog watchdog 1 flag

  6312.   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1

  6313.   * @param  ADCx ADC instance

  6314.   * @retval State of bit (1 or 0).

  6315.   */

  6316. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)

  6317. {

  6318.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);

  6319. }

  6320. 

  6321. /**

  6322.   * @brief  Get flag ADC analog watchdog 2.

  6323.   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2

  6324.   * @param  ADCx ADC instance

  6325.   * @retval State of bit (1 or 0).

  6326.   */

  6327. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)

  6328. {

  6329.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);

  6330. }

  6331. 

  6332. /**

  6333.   * @brief  Get flag ADC analog watchdog 3.

  6334.   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3

  6335.   * @param  ADCx ADC instance

  6336.   * @retval State of bit (1 or 0).

  6337.   */

  6338. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)

  6339. {

  6340.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);

  6341. }

  6342. 

  6343. /**

  6344.   * @brief  Clear flag ADC ready.

  6345.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  6346.   *         is enabled and when conversion clock is active.

  6347.   *         (not only core clock: this ADC has a dual clock domain)

  6348.   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY

  6349.   * @param  ADCx ADC instance

  6350.   * @retval None

  6351.   */

  6352. __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)

  6353. {

  6354.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);

  6355. }

  6356. 

  6357. /**

  6358.   * @brief  Clear flag ADC group regular end of unitary conversion.

  6359.   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC

  6360.   * @param  ADCx ADC instance

  6361.   * @retval None

  6362.   */

  6363. __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)

  6364. {

  6365.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);

  6366. }

  6367. 

  6368. /**

  6369.   * @brief  Clear flag ADC group regular end of sequence conversions.

  6370.   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS

  6371.   * @param  ADCx ADC instance

  6372.   * @retval None

  6373.   */

  6374. __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)

  6375. {

  6376.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);

  6377. }

  6378. 

  6379. /**

  6380.   * @brief  Clear flag ADC group regular overrun.

  6381.   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR

  6382.   * @param  ADCx ADC instance

  6383.   * @retval None

  6384.   */

  6385. __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)

  6386. {

  6387.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);

  6388. }

  6389. 

  6390. /**

  6391.   * @brief  Clear flag ADC group regular end of sampling phase.

  6392.   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP

  6393.   * @param  ADCx ADC instance

  6394.   * @retval None

  6395.   */

  6396. __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)

  6397. {

  6398.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);

  6399. }

  6400. 

  6401. /**

  6402.   * @brief  Clear flag ADC group injected end of unitary conversion.

  6403.   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC

  6404.   * @param  ADCx ADC instance

  6405.   * @retval None

  6406.   */

  6407. __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)

  6408. {

  6409.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);

  6410. }

  6411. 

  6412. /**

  6413.   * @brief  Clear flag ADC group injected end of sequence conversions.

  6414.   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS

  6415.   * @param  ADCx ADC instance

  6416.   * @retval None

  6417.   */

  6418. __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)

  6419. {

  6420.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);

  6421. }

  6422. 

  6423. /**

  6424.   * @brief  Clear flag ADC group injected contexts queue overflow.

  6425.   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF

  6426.   * @param  ADCx ADC instance

  6427.   * @retval None

  6428.   */

  6429. __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)

  6430. {

  6431.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);

  6432. }

  6433. 

  6434. /**

  6435.   * @brief  Clear flag ADC analog watchdog 1.

  6436.   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1

  6437.   * @param  ADCx ADC instance

  6438.   * @retval None

  6439.   */

  6440. __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)

  6441. {

  6442.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);

  6443. }

  6444. 

  6445. /**

  6446.   * @brief  Clear flag ADC analog watchdog 2.

  6447.   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2

  6448.   * @param  ADCx ADC instance

  6449.   * @retval None

  6450.   */

  6451. __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)

  6452. {

  6453.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);

  6454. }

  6455. 

  6456. /**

  6457.   * @brief  Clear flag ADC analog watchdog 3.

  6458.   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3

  6459.   * @param  ADCx ADC instance

  6460.   * @retval None

  6461.   */

  6462. __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)

  6463. {

  6464.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);

  6465. }

  6466. 

  6467. /**

  6468.   * @brief  Get flag multimode ADC ready of the ADC master.

  6469.   * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY

  6470.   * @param  ADCxy_COMMON ADC common instance

  6471.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6472.   * @retval State of bit (1 or 0).

  6473.   */

  6474. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)

  6475. {

  6476.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);

  6477. }

  6478. 

  6479. /**

  6480.   * @brief  Get flag multimode ADC ready of the ADC slave.

  6481.   * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY

  6482.   * @param  ADCxy_COMMON ADC common instance

  6483.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6484.   * @retval State of bit (1 or 0).

  6485.   */

  6486. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)

  6487. {

  6488.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);

  6489. }

  6490. 

  6491. /**

  6492.   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.

  6493.   * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC

  6494.   * @param  ADCxy_COMMON ADC common instance

  6495.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6496.   * @retval State of bit (1 or 0).

  6497.   */

  6498. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)

  6499. {

  6500.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);

  6501. }

  6502. 

  6503. /**

  6504.   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.

  6505.   * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC

  6506.   * @param  ADCxy_COMMON ADC common instance

  6507.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6508.   * @retval State of bit (1 or 0).

  6509.   */

  6510. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)

  6511. {

  6512.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);

  6513. }

  6514. 

  6515. /**

  6516.   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.

  6517.   * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS

  6518.   * @param  ADCxy_COMMON ADC common instance

  6519.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6520.   * @retval State of bit (1 or 0).

  6521.   */

  6522. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)

  6523. {

  6524.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);

  6525. }

  6526. 

  6527. /**

  6528.   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.

  6529.   * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS

  6530.   * @param  ADCxy_COMMON ADC common instance

  6531.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6532.   * @retval State of bit (1 or 0).

  6533.   */

  6534. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)

  6535. {

  6536.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);

  6537. }

  6538. 

  6539. /**

  6540.   * @brief  Get flag multimode ADC group regular overrun of the ADC master.

  6541.   * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR

  6542.   * @param  ADCxy_COMMON ADC common instance

  6543.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6544.   * @retval State of bit (1 or 0).

  6545.   */

  6546. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

  6547. {

  6548.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);

  6549. }

  6550. 

  6551. /**

  6552.   * @brief  Get flag multimode ADC group regular overrun of the ADC slave.

  6553.   * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR

  6554.   * @param  ADCxy_COMMON ADC common instance

  6555.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6556.   * @retval State of bit (1 or 0).

  6557.   */

  6558. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

  6559. {

  6560.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);

  6561. }

  6562. 

  6563. /**

  6564.   * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.

  6565.   * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP

  6566.   * @param  ADCxy_COMMON ADC common instance

  6567.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6568.   * @retval State of bit (1 or 0).

  6569.   */

  6570. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)

  6571. {

  6572.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);

  6573. }

  6574. 

  6575. /**

  6576.   * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.

  6577.   * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP

  6578.   * @param  ADCxy_COMMON ADC common instance

  6579.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6580.   * @retval State of bit (1 or 0).

  6581.   */

  6582. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)

  6583. {

  6584.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);

  6585. }

  6586. 

  6587. /**

  6588.   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.

  6589.   * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC

  6590.   * @param  ADCxy_COMMON ADC common instance

  6591.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6592.   * @retval State of bit (1 or 0).

  6593.   */

  6594. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)

  6595. {

  6596.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);

  6597. }

  6598. 

  6599. /**

  6600.   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.

  6601.   * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC

  6602.   * @param  ADCxy_COMMON ADC common instance

  6603.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6604.   * @retval State of bit (1 or 0).

  6605.   */

  6606. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)

  6607. {

  6608.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);

  6609. }

  6610. 

  6611. /**

  6612.   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.

  6613.   * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS

  6614.   * @param  ADCxy_COMMON ADC common instance

  6615.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6616.   * @retval State of bit (1 or 0).

  6617.   */

  6618. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

  6619. {

  6620.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);

  6621. }

  6622. 

  6623. /**

  6624.   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.

  6625.   * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS

  6626.   * @param  ADCxy_COMMON ADC common instance

  6627.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6628.   * @retval State of bit (1 or 0).

  6629.   */

  6630. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

  6631. {

  6632.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);

  6633. }

  6634. 

  6635. /**

  6636.   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.

  6637.   * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF

  6638.   * @param  ADCxy_COMMON ADC common instance

  6639.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6640.   * @retval State of bit (1 or 0).

  6641.   */

  6642. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)

  6643. {

  6644.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);

  6645. }

  6646. 

  6647. /**

  6648.   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.

  6649.   * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF

  6650.   * @param  ADCxy_COMMON ADC common instance

  6651.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6652.   * @retval State of bit (1 or 0).

  6653.   */

  6654. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)

  6655. {

  6656.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);

  6657. }

  6658. 

  6659. /**

  6660.   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.

  6661.   * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1

  6662.   * @param  ADCxy_COMMON ADC common instance

  6663.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6664.   * @retval State of bit (1 or 0).

  6665.   */

  6666. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

  6667. {

  6668.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);

  6669. }

  6670. 

  6671. /**

  6672.   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.

  6673.   * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1

  6674.   * @param  ADCxy_COMMON ADC common instance

  6675.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6676.   * @retval State of bit (1 or 0).

  6677.   */

  6678. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

  6679. {

  6680.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);

  6681. }

  6682. 

  6683. /**

  6684.   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.

  6685.   * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2

  6686.   * @param  ADCxy_COMMON ADC common instance

  6687.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6688.   * @retval State of bit (1 or 0).

  6689.   */

  6690. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)

  6691. {

  6692.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);

  6693. }

  6694. 

  6695. /**

  6696.   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.

  6697.   * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2

  6698.   * @param  ADCxy_COMMON ADC common instance

  6699.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6700.   * @retval State of bit (1 or 0).

  6701.   */

  6702. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)

  6703. {

  6704.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);

  6705. }

  6706. 

  6707. /**

  6708.   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.

  6709.   * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3

  6710.   * @param  ADCxy_COMMON ADC common instance

  6711.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6712.   * @retval State of bit (1 or 0).

  6713.   */

  6714. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)

  6715. {

  6716.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);

  6717. }

  6718. 

  6719. /**

  6720.   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.

  6721.   * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3

  6722.   * @param  ADCxy_COMMON ADC common instance

  6723.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6724.   * @retval State of bit (1 or 0).

  6725.   */

  6726. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)

  6727. {

  6728.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);

  6729. }

  6730. 

  6731. /**

  6732.   * @}

  6733.   */

  6734. 

  6735. /** @defgroup ADC_LL_EF_IT_Management ADC IT management

  6736.   * @{

  6737.   */

  6738. 

  6739. /**

  6740.   * @brief  Enable ADC ready.

  6741.   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY

  6742.   * @param  ADCx ADC instance

  6743.   * @retval None

  6744.   */

  6745. __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)

  6746. {

  6747.   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);

  6748. }

  6749. 

  6750. /**

  6751.   * @brief  Enable interruption ADC group regular end of unitary conversion.

  6752.   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC

  6753.   * @param  ADCx ADC instance

  6754.   * @retval None

  6755.   */

  6756. __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)

  6757. {

  6758.   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);

  6759. }

  6760. 

  6761. /**

  6762.   * @brief  Enable interruption ADC group regular end of sequence conversions.

  6763.   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS

  6764.   * @param  ADCx ADC instance

  6765.   * @retval None

  6766.   */

  6767. __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)

  6768. {

  6769.   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);

  6770. }

  6771. 

  6772. /**

  6773.   * @brief  Enable ADC group regular interruption overrun.

  6774.   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR

  6775.   * @param  ADCx ADC instance

  6776.   * @retval None

  6777.   */

  6778. __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)

  6779. {

  6780.   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);

  6781. }

  6782. 

  6783. /**

  6784.   * @brief  Enable interruption ADC group regular end of sampling.

  6785.   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP

  6786.   * @param  ADCx ADC instance

  6787.   * @retval None

  6788.   */

  6789. __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)

  6790. {

  6791.   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);

  6792. }

  6793. 

  6794. /**

  6795.   * @brief  Enable interruption ADC group injected end of unitary conversion.

  6796.   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC

  6797.   * @param  ADCx ADC instance

  6798.   * @retval None

  6799.   */

  6800. __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)

  6801. {

  6802.   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);

  6803. }

  6804. 

  6805. /**

  6806.   * @brief  Enable interruption ADC group injected end of sequence conversions.

  6807.   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS

  6808.   * @param  ADCx ADC instance

  6809.   * @retval None

  6810.   */

  6811. __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)

  6812. {

  6813.   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);

  6814. }

  6815. 

  6816. /**

  6817.   * @brief  Enable interruption ADC group injected context queue overflow.

  6818.   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF

  6819.   * @param  ADCx ADC instance

  6820.   * @retval None

  6821.   */

  6822. __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)

  6823. {

  6824.   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);

  6825. }

  6826. 

  6827. /**

  6828.   * @brief  Enable interruption ADC analog watchdog 1.

  6829.   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1

  6830.   * @param  ADCx ADC instance

  6831.   * @retval None

  6832.   */

  6833. __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)

  6834. {

  6835.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);

  6836. }

  6837. 

  6838. /**

  6839.   * @brief  Enable interruption ADC analog watchdog 2.

  6840.   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2

  6841.   * @param  ADCx ADC instance

  6842.   * @retval None

  6843.   */

  6844. __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)

  6845. {

  6846.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);

  6847. }

  6848. 

  6849. /**

  6850.   * @brief  Enable interruption ADC analog watchdog 3.

  6851.   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3

  6852.   * @param  ADCx ADC instance

  6853.   * @retval None

  6854.   */

  6855. __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)

  6856. {

  6857.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);

  6858. }

  6859. 

  6860. /**

  6861.   * @brief  Disable interruption ADC ready.

  6862.   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY

  6863.   * @param  ADCx ADC instance

  6864.   * @retval None

  6865.   */

  6866. __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)

  6867. {

  6868.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);

  6869. }

  6870. 

  6871. /**

  6872.   * @brief  Disable interruption ADC group regular end of unitary conversion.

  6873.   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC

  6874.   * @param  ADCx ADC instance

  6875.   * @retval None

  6876.   */

  6877. __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)

  6878. {

  6879.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);

  6880. }

  6881. 

  6882. /**

  6883.   * @brief  Disable interruption ADC group regular end of sequence conversions.

  6884.   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS

  6885.   * @param  ADCx ADC instance

  6886.   * @retval None

  6887.   */

  6888. __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)

  6889. {

  6890.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);

  6891. }

  6892. 

  6893. /**

  6894.   * @brief  Disable interruption ADC group regular overrun.

  6895.   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR

  6896.   * @param  ADCx ADC instance

  6897.   * @retval None

  6898.   */

  6899. __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)

  6900. {

  6901.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);

  6902. }

  6903. 

  6904. /**

  6905.   * @brief  Disable interruption ADC group regular end of sampling.

  6906.   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP

  6907.   * @param  ADCx ADC instance

  6908.   * @retval None

  6909.   */

  6910. __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)

  6911. {

  6912.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);

  6913. }

  6914. 

  6915. /**

  6916.   * @brief  Disable interruption ADC group regular end of unitary conversion.

  6917.   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC

  6918.   * @param  ADCx ADC instance

  6919.   * @retval None

  6920.   */

  6921. __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)

  6922. {

  6923.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);

  6924. }

  6925. 

  6926. /**

  6927.   * @brief  Disable interruption ADC group injected end of sequence conversions.

  6928.   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS

  6929.   * @param  ADCx ADC instance

  6930.   * @retval None

  6931.   */

  6932. __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)

  6933. {

  6934.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);

  6935. }

  6936. 

  6937. /**

  6938.   * @brief  Disable interruption ADC group injected context queue overflow.

  6939.   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF

  6940.   * @param  ADCx ADC instance

  6941.   * @retval None

  6942.   */

  6943. __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)

  6944. {

  6945.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);

  6946. }

  6947. 

  6948. /**

  6949.   * @brief  Disable interruption ADC analog watchdog 1.

  6950.   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1

  6951.   * @param  ADCx ADC instance

  6952.   * @retval None

  6953.   */

  6954. __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)

  6955. {

  6956.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);

  6957. }

  6958. 

  6959. /**

  6960.   * @brief  Disable interruption ADC analog watchdog 2.

  6961.   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2

  6962.   * @param  ADCx ADC instance

  6963.   * @retval None

  6964.   */

  6965. __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)

  6966. {

  6967.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);

  6968. }

  6969. 

  6970. /**

  6971.   * @brief  Disable interruption ADC analog watchdog 3.

  6972.   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3

  6973.   * @param  ADCx ADC instance

  6974.   * @retval None

  6975.   */

  6976. __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)

  6977. {

  6978.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);

  6979. }

  6980. 

  6981. /**

  6982.   * @brief  Get state of interruption ADC ready

  6983.   *         (0: interrupt disabled, 1: interrupt enabled).

  6984.   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY

  6985.   * @param  ADCx ADC instance

  6986.   * @retval State of bit (1 or 0).

  6987.   */

  6988. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)

  6989. {

  6990.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);

  6991. }

  6992. 

  6993. /**

  6994.   * @brief  Get state of interruption ADC group regular end of unitary conversion

  6995.   *         (0: interrupt disabled, 1: interrupt enabled).

  6996.   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC

  6997.   * @param  ADCx ADC instance

  6998.   * @retval State of bit (1 or 0).

  6999.   */

  7000. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)

  7001. {

  7002.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);

  7003. }

  7004. 

  7005. /**

  7006.   * @brief  Get state of interruption ADC group regular end of sequence conversions

  7007.   *         (0: interrupt disabled, 1: interrupt enabled).

  7008.   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS

  7009.   * @param  ADCx ADC instance

  7010.   * @retval State of bit (1 or 0).

  7011.   */

  7012. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)

  7013. {

  7014.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);

  7015. }

  7016. 

  7017. /**

  7018.   * @brief  Get state of interruption ADC group regular overrun

  7019.   *         (0: interrupt disabled, 1: interrupt enabled).

  7020.   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR

  7021.   * @param  ADCx ADC instance

  7022.   * @retval State of bit (1 or 0).

  7023.   */

  7024. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)

  7025. {

  7026.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);

  7027. }

  7028. 

  7029. /**

  7030.   * @brief  Get state of interruption ADC group regular end of sampling

  7031.   *         (0: interrupt disabled, 1: interrupt enabled).

  7032.   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP

  7033.   * @param  ADCx ADC instance

  7034.   * @retval State of bit (1 or 0).

  7035.   */

  7036. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)

  7037. {

  7038.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);

  7039. }

  7040. 

  7041. /**

  7042.   * @brief  Get state of interruption ADC group injected end of unitary conversion

  7043.   *         (0: interrupt disabled, 1: interrupt enabled).

  7044.   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC

  7045.   * @param  ADCx ADC instance

  7046.   * @retval State of bit (1 or 0).

  7047.   */

  7048. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)

  7049. {

  7050.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);

  7051. }

  7052. 

  7053. /**

  7054.   * @brief  Get state of interruption ADC group injected end of sequence conversions

  7055.   *         (0: interrupt disabled, 1: interrupt enabled).

  7056.   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS

  7057.   * @param  ADCx ADC instance

  7058.   * @retval State of bit (1 or 0).

  7059.   */

  7060. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)

  7061. {

  7062.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);

  7063. }

  7064. 

  7065. /**

  7066.   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state

  7067.   *         (0: interrupt disabled, 1: interrupt enabled).

  7068.   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF

  7069.   * @param  ADCx ADC instance

  7070.   * @retval State of bit (1 or 0).

  7071.   */

  7072. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)

  7073. {

  7074.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);

  7075. }

  7076. 

  7077. /**

  7078.   * @brief  Get state of interruption ADC analog watchdog 1

  7079.   *         (0: interrupt disabled, 1: interrupt enabled).

  7080.   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1

  7081.   * @param  ADCx ADC instance

  7082.   * @retval State of bit (1 or 0).

  7083.   */

  7084. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)

  7085. {

  7086.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);

  7087. }

  7088. 

  7089. /**

  7090.   * @brief  Get state of interruption Get ADC analog watchdog 2

  7091.   *         (0: interrupt disabled, 1: interrupt enabled).

  7092.   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2

  7093.   * @param  ADCx ADC instance

  7094.   * @retval State of bit (1 or 0).

  7095.   */

  7096. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)

  7097. {

  7098.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);

  7099. }

  7100. 

  7101. /**

  7102.   * @brief  Get state of interruption Get ADC analog watchdog 3

  7103.   *         (0: interrupt disabled, 1: interrupt enabled).

  7104.   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3

  7105.   * @param  ADCx ADC instance

  7106.   * @retval State of bit (1 or 0).

  7107.   */

  7108. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)

  7109. {

  7110.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);

  7111. }

  7112. 

  7113. /**

  7114.   * @}

  7115.   */

  7116. 

  7117. #if defined(USE_FULL_LL_DRIVER)

  7118. /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions

  7119.   * @{

  7120.   */

  7121. 

  7122. /* Initialization of some features of ADC common parameters and multimode */

  7123. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);

  7124. ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  7125. void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  7126. 

  7127. /* De-initialization of ADC instance, ADC group regular and ADC group injected */

  7128. /* (availability of ADC group injected depends on STM32 families) */

  7129. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);

  7130. 

  7131. /* Initialization of some features of ADC instance */

  7132. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);

  7133. void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);

  7134. 

  7135. /* Initialization of some features of ADC instance and ADC group regular */

  7136. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  7137. void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  7138. 

  7139. /* Initialization of some features of ADC instance and ADC group injected */

  7140. ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  7141. void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  7142. 

  7143. /**

  7144.   * @}

  7145.   */

  7146. #endif /* USE_FULL_LL_DRIVER */

  7147. 

  7148. /**

  7149.   * @}

  7150.   */

  7151. 

  7152. /**

  7153.   * @}

  7154.   */

  7155. 

  7156. #endif /* ADC1 || ADC2 || ADC3 */

  7157. 

  7158. /**

  7159.   * @}

  7160.   */

  7161. 

  7162. #ifdef __cplusplus

  7163. }

  7164. #endif

  7165. 

  7166. #endif /* STM32H7xx_LL_ADC_H */

  7167. 

  7168. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/