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  1. ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
  2. ;* File Name : startup_stm32l061xx.s
  3. ;* Author : MCD Application Team
  4. ;* Description : STM32l061xx Devices vector table for MDK-ARM toolchain.
  5. ;* This module performs:
  6. ;* - Set the initial SP
  7. ;* - Set the initial PC == Reset_Handler
  8. ;* - Set the vector table entries with the exceptions ISR address
  9. ;* - Branches to __main in the C library (which eventually
  10. ;* calls main()).
  11. ;* After Reset the Cortex-M0+ processor is in Thread mode,
  12. ;* priority is Privileged, and the Stack is set to Main.
  13. ;*******************************************************************************
  14. ;*
  15. ;* Redistribution and use in source and binary forms, with or without modification,
  16. ;* are permitted provided that the following conditions are met:
  17. ;* 1. Redistributions of source code must retain the above copyright notice,
  18. ;* this list of conditions and the following disclaimer.
  19. ;* 2. Redistributions in binary form must reproduce the above copyright notice,
  20. ;* this list of conditions and the following disclaimer in the documentation
  21. ;* and/or other materials provided with the distribution.
  22. ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
  23. ;* may be used to endorse or promote products derived from this software
  24. ;* without specific prior written permission.
  25. ;*
  26. ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  27. ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28. ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29. ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  30. ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31. ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  32. ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  33. ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  34. ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35. ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. ;*
  37. ;*******************************************************************************
  38. ;
  39. ; Amount of memory (in bytes) allocated for Stack
  40. ; Tailor this value to your application needs
  41. ; <h> Stack Configuration
  42. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  43. ; </h>
  44. Stack_Size EQU 0x00000400
  45. AREA STACK, NOINIT, READWRITE, ALIGN=3
  46. Stack_Mem SPACE Stack_Size
  47. __initial_sp
  48. ; <h> Heap Configuration
  49. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  50. ; </h>
  51. Heap_Size EQU 0x00000200
  52. AREA HEAP, NOINIT, READWRITE, ALIGN=3
  53. __heap_base
  54. Heap_Mem SPACE Heap_Size
  55. __heap_limit
  56. PRESERVE8
  57. THUMB
  58. ; Vector Table Mapped to Address 0 at Reset
  59. AREA RESET, DATA, READONLY
  60. EXPORT __Vectors
  61. EXPORT __Vectors_End
  62. EXPORT __Vectors_Size
  63. __Vectors DCD __initial_sp ; Top of Stack
  64. DCD Reset_Handler ; Reset Handler
  65. DCD NMI_Handler ; NMI Handler
  66. DCD HardFault_Handler ; Hard Fault Handler
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD 0 ; Reserved
  71. DCD 0 ; Reserved
  72. DCD 0 ; Reserved
  73. DCD 0 ; Reserved
  74. DCD SVC_Handler ; SVCall Handler
  75. DCD 0 ; Reserved
  76. DCD 0 ; Reserved
  77. DCD PendSV_Handler ; PendSV Handler
  78. DCD SysTick_Handler ; SysTick Handler
  79. ; External Interrupts
  80. DCD WWDG_IRQHandler ; Window Watchdog
  81. DCD PVD_IRQHandler ; PVD through EXTI Line detect
  82. DCD RTC_IRQHandler ; RTC through EXTI Line
  83. DCD FLASH_IRQHandler ; FLASH
  84. DCD RCC_IRQHandler ; RCC
  85. DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
  86. DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
  87. DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
  88. DCD 0 ; Reserved
  89. DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
  90. DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
  91. DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
  92. DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
  93. DCD LPTIM1_IRQHandler ; LPTIM1
  94. DCD 0 ; Reserved
  95. DCD TIM2_IRQHandler ; TIM2
  96. DCD 0 ; Reserved
  97. DCD TIM6_IRQHandler ; TIM6
  98. DCD 0 ; Reserved
  99. DCD 0 ; Reserved
  100. DCD TIM21_IRQHandler ; TIM21
  101. DCD 0 ; Reserved
  102. DCD TIM22_IRQHandler ; TIM22
  103. DCD I2C1_IRQHandler ; I2C1
  104. DCD I2C2_IRQHandler ; I2C2
  105. DCD SPI1_IRQHandler ; SPI1
  106. DCD SPI2_IRQHandler ; SPI2
  107. DCD USART1_IRQHandler ; USART1
  108. DCD USART2_IRQHandler ; USART2
  109. DCD AES_LPUART1_IRQHandler ; AES and LPUART1
  110. DCD 0 ; Reserved
  111. DCD 0 ; Reserved
  112. __Vectors_End
  113. __Vectors_Size EQU __Vectors_End - __Vectors
  114. AREA |.text|, CODE, READONLY
  115. ; Reset handler routine
  116. Reset_Handler PROC
  117. EXPORT Reset_Handler [WEAK]
  118. IMPORT __main
  119. IMPORT SystemInit
  120. LDR R0, =SystemInit
  121. BLX R0
  122. LDR R0, =__main
  123. BX R0
  124. ENDP
  125. ; Dummy Exception Handlers (infinite loops which can be modified)
  126. NMI_Handler PROC
  127. EXPORT NMI_Handler [WEAK]
  128. B .
  129. ENDP
  130. HardFault_Handler\
  131. PROC
  132. EXPORT HardFault_Handler [WEAK]
  133. B .
  134. ENDP
  135. SVC_Handler PROC
  136. EXPORT SVC_Handler [WEAK]
  137. B .
  138. ENDP
  139. PendSV_Handler PROC
  140. EXPORT PendSV_Handler [WEAK]
  141. B .
  142. ENDP
  143. SysTick_Handler PROC
  144. EXPORT SysTick_Handler [WEAK]
  145. B .
  146. ENDP
  147. Default_Handler PROC
  148. EXPORT WWDG_IRQHandler [WEAK]
  149. EXPORT PVD_IRQHandler [WEAK]
  150. EXPORT RTC_IRQHandler [WEAK]
  151. EXPORT FLASH_IRQHandler [WEAK]
  152. EXPORT RCC_IRQHandler [WEAK]
  153. EXPORT EXTI0_1_IRQHandler [WEAK]
  154. EXPORT EXTI2_3_IRQHandler [WEAK]
  155. EXPORT EXTI4_15_IRQHandler [WEAK]
  156. EXPORT DMA1_Channel1_IRQHandler [WEAK]
  157. EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
  158. EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
  159. EXPORT ADC1_COMP_IRQHandler [WEAK]
  160. EXPORT LPTIM1_IRQHandler [WEAK]
  161. EXPORT TIM2_IRQHandler [WEAK]
  162. EXPORT TIM6_IRQHandler [WEAK]
  163. EXPORT TIM21_IRQHandler [WEAK]
  164. EXPORT TIM22_IRQHandler [WEAK]
  165. EXPORT I2C1_IRQHandler [WEAK]
  166. EXPORT I2C2_IRQHandler [WEAK]
  167. EXPORT SPI1_IRQHandler [WEAK]
  168. EXPORT SPI2_IRQHandler [WEAK]
  169. EXPORT USART1_IRQHandler [WEAK]
  170. EXPORT USART2_IRQHandler [WEAK]
  171. EXPORT AES_LPUART1_IRQHandler [WEAK]
  172. WWDG_IRQHandler
  173. PVD_IRQHandler
  174. RTC_IRQHandler
  175. FLASH_IRQHandler
  176. RCC_IRQHandler
  177. EXTI0_1_IRQHandler
  178. EXTI2_3_IRQHandler
  179. EXTI4_15_IRQHandler
  180. DMA1_Channel1_IRQHandler
  181. DMA1_Channel2_3_IRQHandler
  182. DMA1_Channel4_5_6_7_IRQHandler
  183. ADC1_COMP_IRQHandler
  184. LPTIM1_IRQHandler
  185. TIM2_IRQHandler
  186. TIM6_IRQHandler
  187. TIM21_IRQHandler
  188. TIM22_IRQHandler
  189. I2C1_IRQHandler
  190. I2C2_IRQHandler
  191. SPI1_IRQHandler
  192. SPI2_IRQHandler
  193. USART1_IRQHandler
  194. USART2_IRQHandler
  195. AES_LPUART1_IRQHandler
  196. B .
  197. ENDP
  198. ALIGN
  199. ;*******************************************************************************
  200. ; User Stack and Heap initialization
  201. ;*******************************************************************************
  202. IF :DEF:__MICROLIB
  203. EXPORT __initial_sp
  204. EXPORT __heap_base
  205. EXPORT __heap_limit
  206. ELSE
  207. IMPORT __use_two_region_memory
  208. EXPORT __user_initial_stackheap
  209. __user_initial_stackheap
  210. LDR R0, = Heap_Mem
  211. LDR R1, =(Stack_Mem + Stack_Size)
  212. LDR R2, = (Heap_Mem + Heap_Size)
  213. LDR R3, = Stack_Mem
  214. BX LR
  215. ALIGN
  216. ENDIF
  217. END
  218. ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****