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  1. /**
  2. ******************************************************************************
  3. * @file startup_stm32l010x6.s
  4. * @author MCD Application Team
  5. * @brief STM32L010x6 Devices vector table for GCC toolchain.
  6. * This module performs:
  7. * - Set the initial SP
  8. * - Set the initial PC == Reset_Handler,
  9. * - Set the vector table entries with the exceptions ISR address
  10. * - Branches to main in the C library (which eventually
  11. * calls main()).
  12. * After Reset the Cortex-M0+ processor is in Thread mode,
  13. * priority is Privileged, and the Stack is set to Main.
  14. ******************************************************************************
  15. *
  16. * Redistribution and use in source and binary forms, with or without modification,
  17. * are permitted provided that the following conditions are met:
  18. * 1. Redistributions of source code must retain the above copyright notice,
  19. * this list of conditions and the following disclaimer.
  20. * 2. Redistributions in binary form must reproduce the above copyright notice,
  21. * this list of conditions and the following disclaimer in the documentation
  22. * and/or other materials provided with the distribution.
  23. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  24. * may be used to endorse or promote products derived from this software
  25. * without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  28. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  29. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  30. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  31. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  33. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  34. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  35. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. *
  38. ******************************************************************************
  39. */
  40. .syntax unified
  41. .cpu cortex-m0plus
  42. .fpu softvfp
  43. .thumb
  44. .global g_pfnVectors
  45. .global Default_Handler
  46. /* start address for the initialization values of the .data section.
  47. defined in linker script */
  48. .word _sidata
  49. /* start address for the .data section. defined in linker script */
  50. .word _sdata
  51. /* end address for the .data section. defined in linker script */
  52. .word _edata
  53. /* start address for the .bss section. defined in linker script */
  54. .word _sbss
  55. /* end address for the .bss section. defined in linker script */
  56. .word _ebss
  57. .section .text.Reset_Handler
  58. .weak Reset_Handler
  59. .type Reset_Handler, %function
  60. Reset_Handler:
  61. ldr r0, =_estack
  62. mov sp, r0 /* set stack pointer */
  63. /*Check if boot space corresponds to system memory*/
  64. LDR R0,=0x00000004
  65. LDR R1, [R0]
  66. LSRS R1, R1, #24
  67. LDR R2,=0x1F
  68. CMP R1, R2
  69. BNE ApplicationStart
  70. /*SYSCFG clock enable*/
  71. LDR R0,=0x40021034
  72. LDR R1,=0x00000001
  73. STR R1, [R0]
  74. /*Set CFGR1 register with flash memory remap at address 0*/
  75. LDR R0,=0x40010000
  76. LDR R1,=0x00000000
  77. STR R1, [R0]
  78. ApplicationStart:
  79. /* Copy the data segment initializers from flash to SRAM */
  80. movs r1, #0
  81. b LoopCopyDataInit
  82. CopyDataInit:
  83. ldr r3, =_sidata
  84. ldr r3, [r3, r1]
  85. str r3, [r0, r1]
  86. adds r1, r1, #4
  87. LoopCopyDataInit:
  88. ldr r0, =_sdata
  89. ldr r3, =_edata
  90. adds r2, r0, r1
  91. cmp r2, r3
  92. bcc CopyDataInit
  93. ldr r2, =_sbss
  94. b LoopFillZerobss
  95. /* Zero fill the bss segment. */
  96. FillZerobss:
  97. movs r3, #0
  98. str r3, [r2]
  99. adds r2, r2, #4
  100. LoopFillZerobss:
  101. ldr r3, = _ebss
  102. cmp r2, r3
  103. bcc FillZerobss
  104. /* Call the clock system intitialization function.*/
  105. bl SystemInit
  106. /* Call static constructors */
  107. bl __libc_init_array
  108. /* Call the application's entry point.*/
  109. bl main
  110. LoopForever:
  111. b LoopForever
  112. .size Reset_Handler, .-Reset_Handler
  113. /**
  114. * @brief This is the code that gets called when the processor receives an
  115. * unexpected interrupt. This simply enters an infinite loop, preserving
  116. * the system state for examination by a debugger.
  117. *
  118. * @param None
  119. * @retval : None
  120. */
  121. .section .text.Default_Handler,"ax",%progbits
  122. Default_Handler:
  123. Infinite_Loop:
  124. b Infinite_Loop
  125. .size Default_Handler, .-Default_Handler
  126. /******************************************************************************
  127. *
  128. * The minimal vector table for a Cortex M0. Note that the proper constructs
  129. * must be placed on this to ensure that it ends up at physical address
  130. * 0x0000.0000.
  131. *
  132. ******************************************************************************/
  133. .section .isr_vector,"a",%progbits
  134. .type g_pfnVectors, %object
  135. .size g_pfnVectors, .-g_pfnVectors
  136. g_pfnVectors:
  137. .word _estack
  138. .word Reset_Handler
  139. .word NMI_Handler
  140. .word HardFault_Handler
  141. .word 0
  142. .word 0
  143. .word 0
  144. .word 0
  145. .word 0
  146. .word 0
  147. .word 0
  148. .word SVC_Handler
  149. .word 0
  150. .word 0
  151. .word PendSV_Handler
  152. .word SysTick_Handler
  153. .word WWDG_IRQHandler /* Window WatchDog */
  154. .word 0 /* Reserved */
  155. .word RTC_IRQHandler /* RTC through the EXTI line */
  156. .word FLASH_IRQHandler /* FLASH */
  157. .word RCC_IRQHandler /* RCC */
  158. .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
  159. .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
  160. .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
  161. .word 0 /* Reserved */
  162. .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
  163. .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
  164. .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
  165. .word ADC1_IRQHandler /* ADC1 */
  166. .word LPTIM1_IRQHandler /* LPTIM1 */
  167. .word 0 /* Reserved */
  168. .word TIM2_IRQHandler /* TIM2 */
  169. .word 0 /* Reserved */
  170. .word 0 /* Reserved */
  171. .word 0 /* Reserved */
  172. .word 0 /* Reserved */
  173. .word TIM21_IRQHandler /* TIM21 */
  174. .word 0 /* Reserved */
  175. .word 0 /* Reserved */
  176. .word I2C1_IRQHandler /* I2C1 */
  177. .word 0 /* Reserved */
  178. .word SPI1_IRQHandler /* SPI1 */
  179. .word 0 /* Reserved */
  180. .word 0 /* Reserved */
  181. .word USART2_IRQHandler /* USART2 */
  182. .word LPUART1_IRQHandler /* LPUART1 */
  183. .word 0 /* Reserved */
  184. .word 0 /* Reserved */
  185. /*******************************************************************************
  186. *
  187. * Provide weak aliases for each Exception handler to the Default_Handler.
  188. * As they are weak aliases, any function with the same name will override
  189. * this definition.
  190. *
  191. *******************************************************************************/
  192. .weak NMI_Handler
  193. .thumb_set NMI_Handler,Default_Handler
  194. .weak HardFault_Handler
  195. .thumb_set HardFault_Handler,Default_Handler
  196. .weak SVC_Handler
  197. .thumb_set SVC_Handler,Default_Handler
  198. .weak PendSV_Handler
  199. .thumb_set PendSV_Handler,Default_Handler
  200. .weak SysTick_Handler
  201. .thumb_set SysTick_Handler,Default_Handler
  202. .weak WWDG_IRQHandler
  203. .thumb_set WWDG_IRQHandler,Default_Handler
  204. .weak RTC_IRQHandler
  205. .thumb_set RTC_IRQHandler,Default_Handler
  206. .weak FLASH_IRQHandler
  207. .thumb_set FLASH_IRQHandler,Default_Handler
  208. .weak RCC_IRQHandler
  209. .thumb_set RCC_IRQHandler,Default_Handler
  210. .weak EXTI0_1_IRQHandler
  211. .thumb_set EXTI0_1_IRQHandler,Default_Handler
  212. .weak EXTI2_3_IRQHandler
  213. .thumb_set EXTI2_3_IRQHandler,Default_Handler
  214. .weak EXTI4_15_IRQHandler
  215. .thumb_set EXTI4_15_IRQHandler,Default_Handler
  216. .weak DMA1_Channel1_IRQHandler
  217. .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
  218. .weak DMA1_Channel2_3_IRQHandler
  219. .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
  220. .weak DMA1_Channel4_5_6_7_IRQHandler
  221. .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
  222. .weak ADC1_IRQHandler
  223. .thumb_set ADC1_IRQHandler,Default_Handler
  224. .weak LPTIM1_IRQHandler
  225. .thumb_set LPTIM1_IRQHandler,Default_Handler
  226. .weak TIM2_IRQHandler
  227. .thumb_set TIM2_IRQHandler,Default_Handler
  228. .weak TIM21_IRQHandler
  229. .thumb_set TIM21_IRQHandler,Default_Handler
  230. .weak I2C1_IRQHandler
  231. .thumb_set I2C1_IRQHandler,Default_Handler
  232. .weak SPI1_IRQHandler
  233. .thumb_set SPI1_IRQHandler,Default_Handler
  234. .weak USART2_IRQHandler
  235. .thumb_set USART2_IRQHandler,Default_Handler
  236. .weak LPUART1_IRQHandler
  237. .thumb_set LPUART1_IRQHandler,Default_Handler
  238. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/