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- ;/******************** (C) COPYRIGHT 2018 STMicroelectronics ********************
- ;* File Name : startup_stm32l010xb.s
- ;* Author : MCD Application Team
- ;* Description : STM32L010xB Ultra Low Power Devices vector
- ;* This module performs:
- ;* - Set the initial SP
- ;* - Set the initial PC == _iar_program_start,
- ;* - Set the vector table entries with the exceptions ISR
- ;* address.
- ;* - Configure the system clock
- ;* - Branches to main in the C library (which eventually
- ;* calls main()).
- ;* After Reset the Cortex-M0+ processor is in Thread mode,
- ;* priority is Privileged, and the Stack is set to Main.
- ;********************************************************************************
- ;*
- ;* Redistribution and use in source and binary forms, with or without modification,
- ;* are permitted provided that the following conditions are met:
- ;* 1. Redistributions of source code must retain the above copyright notice,
- ;* this list of conditions and the following disclaimer.
- ;* 2. Redistributions in binary form must reproduce the above copyright notice,
- ;* this list of conditions and the following disclaimer in the documentation
- ;* and/or other materials provided with the distribution.
- ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
- ;* may be used to endorse or promote products derived from this software
- ;* without specific prior written permission.
- ;*
- ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ;*
- ;*******************************************************************************/
- ;
- ;
- ; The modules in this file are included in the libraries, and may be replaced
- ; by any user-defined modules that define the PUBLIC symbol _program_start or
- ; a user defined start symbol.
- ; To override the cstartup defined in the library, simply add your modified
- ; version to the workbench project.
- ;
- ; The vector table is normally located at address 0.
- ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
- ; The name "__vector_table" has special meaning for C-SPY:
- ; it is where the SP start value is found, and the NVIC vector
- ; table register (VTOR) is initialized to this address if != 0.
- ;
- ; Cortex-M version
- ;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
- __vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD 0 ; Reserved
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD 0 ; Reserved
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
- DCD ADC1_IRQHandler ; ADC1
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD 0 ; Reserved
- DCD TIM2_IRQHandler ; TIM2
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM21_IRQHandler ; TIM21
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD I2C1_IRQHandler ; I2C1
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD USART2_IRQHandler ; USART2
- DCD LPUART1_IRQHandler ; LPUART1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ;;
- ;; Default interrupt handlers.
- ;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
- Reset_Handler
- LDR R0, =sfe(CSTACK) ; set stack pointer
- MSR MSP, R0
- ;;Check if boot space corresponds to system memory
- LDR R0,=0x00000004
- LDR R1, [R0]
- LSRS R1, R1, #24
- LDR R2,=0x1F
- CMP R1, R2
- BNE ApplicationStart
- ;; SYSCFG clock enable
- LDR R0,=0x40021034
- LDR R1,=0x00000001
- STR R1, [R0]
- ;; Set CFGR1 register with flash memory remap at address 0
- LDR R0,=0x40010000
- LDR R1,=0x00000000
- STR R1, [R0]
-
- ApplicationStart
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
- NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
- HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
- SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
- PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
- SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- RTC_IRQHandler
- B RTC_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- RCC_IRQHandler
- B RCC_IRQHandler
-
-
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
-
-
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
-
-
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- DMA1_Channel2_3_IRQHandler
- B DMA1_Channel2_3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- DMA1_Channel4_5_6_7_IRQHandler
- B DMA1_Channel4_5_6_7_IRQHandler
-
-
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- ADC1_IRQHandler
- B ADC1_IRQHandler
-
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM21_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- TIM21_IRQHandler
- B TIM21_IRQHandler
-
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- I2C1_IRQHandler
- B I2C1_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- USART2_IRQHandler
- B USART2_IRQHandler
-
-
- PUBWEAK LPUART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
- LPUART1_IRQHandler
- B LPUART1_IRQHandler
-
- END
- ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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