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stm32lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32f0xx_hal.h

  4.   * @author  MCD Application Team

  5.   * @brief   This file contains all the functions prototypes for the HAL

  6.   *          module driver.

  7.   ******************************************************************************

  8.   * @attention

  9.   *

  10.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

  11.   *

  12.   * Redistribution and use in source and binary forms, with or without modification,

  13.   * are permitted provided that the following conditions are met:

  14.   *   1. Redistributions of source code must retain the above copyright notice,

  15.   *      this list of conditions and the following disclaimer.

  16.   *   2. Redistributions in binary form must reproduce the above copyright notice,

  17.   *      this list of conditions and the following disclaimer in the documentation

  18.   *      and/or other materials provided with the distribution.

  19.   *   3. Neither the name of STMicroelectronics nor the names of its contributors

  20.   *      may be used to endorse or promote products derived from this software

  21.   *      without specific prior written permission.

  22.   *

  23.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  24.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  25.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  26.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  27.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  28.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  29.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  30.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  31.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  32.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  33.   *

  34.   ******************************************************************************

  35.   */

  36. 

  37. /* Define to prevent recursive inclusion -------------------------------------*/

  38. #ifndef __STM32F0xx_HAL_H

  39. #define __STM32F0xx_HAL_H

  40. 

  41. #ifdef __cplusplus

  42.  extern "C" {

  43. #endif

  44. 

  45. /* Includes ------------------------------------------------------------------*/

  46. #include "stm32f0xx_hal_conf.h"

  47. 

  48. /** @addtogroup STM32F0xx_HAL_Driver

  49.   * @{

  50.   */

  51. 

  52. /** @addtogroup HAL

  53.   * @{

  54.   */

  55. 

  56. /* Private macros ------------------------------------------------------------*/

  57. /** @addtogroup HAL_Private_Macros

  58.   * @{

  59.   */

  60. #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \

  61.     defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \

  62.     defined(STM32F070xB) || defined(STM32F030x6)

  63. #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9)  == SYSCFG_FASTMODEPLUS_PA9)  || \

  64.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \

  65.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \

  66.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \

  67.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \

  68.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))

  69. #else

  70. #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \

  71.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \

  72.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \

  73.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))

  74. #endif

  75. #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)

  76. #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)

  77. #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */

  78. #if defined(STM32F091xC) || defined(STM32F098xx)

  79. #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \

  80.                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)   || \

  81.                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))

  82. #endif /* STM32F091xC || STM32F098xx */

  83. /**

  84.   * @}

  85.   */

  86. 

  87. /* Exported types ------------------------------------------------------------*/

  88. /* Exported constants --------------------------------------------------------*/

  89. /** @defgroup HAL_Exported_Constants HAL Exported Constants

  90.   * @{

  91.   */

  92. 

  93. #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)

  94. /** @defgroup HAL_Pin_remapping HAL Pin remapping

  95.   * @{

  96.   */

  97. #define HAL_REMAP_PA11_PA12                 (SYSCFG_CFGR1_PA11_PA12_RMP)  /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).

  98.                                                                            0: No remap (pin pair PA9/10 mapped on the pins)

  99.                                                                            1: Remap (pin pair PA11/12 mapped instead of PA9/10) */

  100. 

  101. /**

  102.   * @}

  103.   */

  104. #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */

  105. 

  106. #if defined(STM32F091xC) || defined(STM32F098xx)

  107. /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection

  108.   * @note Applicable on STM32F09x

  109.   * @{

  110.   */

  111. #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16     (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1)    /* 00: Timer16 is selected as IRDA Modulation enveloppe source */

  112. #define HAL_SYSCFG_IRDA_ENV_SEL_USART1    (SYSCFG_CFGR1_IRDA_ENV_SEL_0)  /* 01: USART1 is selected as IRDA Modulation enveloppe source */

  113. #define HAL_SYSCFG_IRDA_ENV_SEL_USART4    (SYSCFG_CFGR1_IRDA_ENV_SEL_1)  /* 10: USART4 is selected as IRDA Modulation enveloppe source */

  114. 

  115. /**

  116.   * @}

  117.   */

  118. #endif /* STM32F091xC || STM32F098xx */

  119. 

  120. 

  121. /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO

  122.   * @{

  123.   */

  124. 

  125. /** @brief  Fast-mode Plus driving capability on a specific GPIO

  126.   */

  127. #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \

  128.     defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \

  129.     defined(STM32F070xB) || defined(STM32F030x6)

  130. #define SYSCFG_FASTMODEPLUS_PA9        SYSCFG_CFGR1_I2C_FMP_PA9  /*!< Enable Fast-mode Plus on PA9  */

  131. #define SYSCFG_FASTMODEPLUS_PA10       SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */

  132. #endif

  133. #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_FMP_PB6  /*!< Enable Fast-mode Plus on PB6  */

  134. #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_FMP_PB7  /*!< Enable Fast-mode Plus on PB7  */

  135. #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_FMP_PB8  /*!< Enable Fast-mode Plus on PB8  */

  136. #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_FMP_PB9  /*!< Enable Fast-mode Plus on PB9  */

  137. 

  138. /**

  139.  * @}

  140.  */

  141. 

  142. 

  143. #if defined(STM32F091xC) || defined (STM32F098xx)

  144. /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper

  145.   * @brief ISR Wrapper

  146.   * @note applicable on STM32F09x

  147.   * @{

  148.   */

  149. #define HAL_SYSCFG_ITLINE0                           ( 0x00000000U) /*!< Internal define for macro handling */

  150. #define HAL_SYSCFG_ITLINE1                           ( 0x00000001U) /*!< Internal define for macro handling */

  151. #define HAL_SYSCFG_ITLINE2                           ( 0x00000002U) /*!< Internal define for macro handling */

  152. #define HAL_SYSCFG_ITLINE3                           ( 0x00000003U) /*!< Internal define for macro handling */

  153. #define HAL_SYSCFG_ITLINE4                           ( 0x00000004U) /*!< Internal define for macro handling */

  154. #define HAL_SYSCFG_ITLINE5                           ( 0x00000005U) /*!< Internal define for macro handling */

  155. #define HAL_SYSCFG_ITLINE6                           ( 0x00000006U) /*!< Internal define for macro handling */

  156. #define HAL_SYSCFG_ITLINE7                           ( 0x00000007U) /*!< Internal define for macro handling */

  157. #define HAL_SYSCFG_ITLINE8                           ( 0x00000008U) /*!< Internal define for macro handling */

  158. #define HAL_SYSCFG_ITLINE9                           ( 0x00000009U) /*!< Internal define for macro handling */

  159. #define HAL_SYSCFG_ITLINE10                          ( 0x0000000AU) /*!< Internal define for macro handling */

  160. #define HAL_SYSCFG_ITLINE11                          ( 0x0000000BU) /*!< Internal define for macro handling */

  161. #define HAL_SYSCFG_ITLINE12                          ( 0x0000000CU) /*!< Internal define for macro handling */

  162. #define HAL_SYSCFG_ITLINE13                          ( 0x0000000DU) /*!< Internal define for macro handling */

  163. #define HAL_SYSCFG_ITLINE14                          ( 0x0000000EU) /*!< Internal define for macro handling */

  164. #define HAL_SYSCFG_ITLINE15                          ( 0x0000000FU) /*!< Internal define for macro handling */

  165. #define HAL_SYSCFG_ITLINE16                          ( 0x00000010U) /*!< Internal define for macro handling */

  166. #define HAL_SYSCFG_ITLINE17                          ( 0x00000011U) /*!< Internal define for macro handling */

  167. #define HAL_SYSCFG_ITLINE18                          ( 0x00000012U) /*!< Internal define for macro handling */

  168. #define HAL_SYSCFG_ITLINE19                          ( 0x00000013U) /*!< Internal define for macro handling */

  169. #define HAL_SYSCFG_ITLINE20                          ( 0x00000014U) /*!< Internal define for macro handling */

  170. #define HAL_SYSCFG_ITLINE21                          ( 0x00000015U) /*!< Internal define for macro handling */

  171. #define HAL_SYSCFG_ITLINE22                          ( 0x00000016U) /*!< Internal define for macro handling */

  172. #define HAL_SYSCFG_ITLINE23                          ( 0x00000017U) /*!< Internal define for macro handling */

  173. #define HAL_SYSCFG_ITLINE24                          ( 0x00000018U) /*!< Internal define for macro handling */

  174. #define HAL_SYSCFG_ITLINE25                          ( 0x00000019U) /*!< Internal define for macro handling */

  175. #define HAL_SYSCFG_ITLINE26                          ( 0x0000001AU) /*!< Internal define for macro handling */

  176. #define HAL_SYSCFG_ITLINE27                          ( 0x0000001BU) /*!< Internal define for macro handling */

  177. #define HAL_SYSCFG_ITLINE28                          ( 0x0000001CU) /*!< Internal define for macro handling */

  178. #define HAL_SYSCFG_ITLINE29                          ( 0x0000001DU) /*!< Internal define for macro handling */

  179. #define HAL_SYSCFG_ITLINE30                          ( 0x0000001EU) /*!< Internal define for macro handling */

  180. #define HAL_SYSCFG_ITLINE31                          ( 0x0000001FU) /*!< Internal define for macro handling */

  181. 

  182. #define HAL_ITLINE_EWDG           ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */

  183. #if defined(STM32F091xC)

  184. #define HAL_ITLINE_PVDOUT         ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */

  185. #endif

  186. #define HAL_ITLINE_VDDIO2         ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */

  187. #define HAL_ITLINE_RTC_WAKEUP     ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */

  188. #define HAL_ITLINE_RTC_TSTAMP     ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */

  189. #define HAL_ITLINE_RTC_ALRA       ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */

  190. #define HAL_ITLINE_FLASH_ITF      ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */

  191. #define HAL_ITLINE_CRS            ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */

  192. #define HAL_ITLINE_CLK_CTRL       ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */

  193. #define HAL_ITLINE_EXTI0          ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */

  194. #define HAL_ITLINE_EXTI1          ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */

  195. #define HAL_ITLINE_EXTI2          ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */

  196. #define HAL_ITLINE_EXTI3          ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */

  197. #define HAL_ITLINE_EXTI4          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */

  198. #define HAL_ITLINE_EXTI5          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */

  199. #define HAL_ITLINE_EXTI6          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */

  200. #define HAL_ITLINE_EXTI7          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */

  201. #define HAL_ITLINE_EXTI8          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */

  202. #define HAL_ITLINE_EXTI9          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */

  203. #define HAL_ITLINE_EXTI10         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */

  204. #define HAL_ITLINE_EXTI11         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */

  205. #define HAL_ITLINE_EXTI12         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */

  206. #define HAL_ITLINE_EXTI13         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */

  207. #define HAL_ITLINE_EXTI14         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */

  208. #define HAL_ITLINE_EXTI15         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */

  209. #define HAL_ITLINE_TSC_EOA        ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */

  210. #define HAL_ITLINE_TSC_MCE        ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */

  211. #define HAL_ITLINE_DMA1_CH1       ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */

  212. #define HAL_ITLINE_DMA1_CH2       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */

  213. #define HAL_ITLINE_DMA1_CH3       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */

  214. #define HAL_ITLINE_DMA2_CH1       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */

  215. #define HAL_ITLINE_DMA2_CH2       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */

  216. #define HAL_ITLINE_DMA1_CH4       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */

  217. #define HAL_ITLINE_DMA1_CH5       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */

  218. #define HAL_ITLINE_DMA1_CH6       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */

  219. #define HAL_ITLINE_DMA1_CH7       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */

  220. #define HAL_ITLINE_DMA2_CH3       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */

  221. #define HAL_ITLINE_DMA2_CH4       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */

  222. #define HAL_ITLINE_DMA2_CH5       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */

  223. #define HAL_ITLINE_ADC            ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */

  224. #define HAL_ITLINE_COMP1          ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */

  225. #define HAL_ITLINE_COMP2          ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */

  226. #define HAL_ITLINE_TIM1_BRK       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */

  227. #define HAL_ITLINE_TIM1_UPD       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */

  228. #define HAL_ITLINE_TIM1_TRG       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */

  229. #define HAL_ITLINE_TIM1_CCU       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */

  230. #define HAL_ITLINE_TIM1_CC        ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */

  231. #define HAL_ITLINE_TIM2           ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */

  232. #define HAL_ITLINE_TIM3           ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */

  233. #define HAL_ITLINE_DAC            ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */

  234. #define HAL_ITLINE_TIM6           ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */

  235. #define HAL_ITLINE_TIM7           ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */

  236. #define HAL_ITLINE_TIM14          ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */

  237. #define HAL_ITLINE_TIM15          ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */

  238. #define HAL_ITLINE_TIM16          ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */

  239. #define HAL_ITLINE_TIM17          ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */

  240. #define HAL_ITLINE_I2C1           ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */

  241. #define HAL_ITLINE_I2C2           ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */

  242. #define HAL_ITLINE_SPI1           ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */

  243. #define HAL_ITLINE_SPI2           ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */

  244. #define HAL_ITLINE_USART1         ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */

  245. #define HAL_ITLINE_USART2         ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */

  246. #define HAL_ITLINE_USART3         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */

  247. #define HAL_ITLINE_USART4         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */

  248. #define HAL_ITLINE_USART5         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */

  249. #define HAL_ITLINE_USART6         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */

  250. #define HAL_ITLINE_USART7         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */

  251. #define HAL_ITLINE_USART8         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */

  252. #define HAL_ITLINE_CAN            ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */

  253. #define HAL_ITLINE_CEC            ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */

  254. /**

  255.   * @}

  256.   */

  257. #endif /* STM32F091xC || STM32F098xx */

  258. 

  259. /**

  260.   * @}

  261.   */

  262. 

  263. /* Exported macros -----------------------------------------------------------*/

  264. /** @defgroup HAL_Exported_Macros HAL Exported Macros

  265.   * @{

  266.   */

  267. 

  268. /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals

  269.   * @brief  Freeze/Unfreeze Peripherals in Debug mode

  270.   * @{

  271.   */

  272. 

  273. #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)

  274. #define __HAL_FREEZE_CAN_DBGMCU()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))

  275. #define __HAL_UNFREEZE_CAN_DBGMCU()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))

  276. #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */

  277. 

  278. #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)

  279. #define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))

  280. #define __HAL_DBGMCU_UNFREEZE_RTC()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))

  281. #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */

  282. 

  283. #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)

  284. #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))

  285. #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))

  286. #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */

  287. 

  288. #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)

  289. #define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))

  290. #define __HAL_DBGMCU_UNFREEZE_IWDG()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))

  291. #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */

  292. 

  293. #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)

  294. #define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))

  295. #define __HAL_DBGMCU_UNFREEZE_WWDG()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))

  296. #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */

  297. 

  298. #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)

  299. #define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))

  300. #define __HAL_DBGMCU_UNFREEZE_TIM2()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))

  301. #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */

  302. 

  303. #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)

  304. #define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))

  305. #define __HAL_DBGMCU_UNFREEZE_TIM3()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))

  306. #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */

  307. 

  308. #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)

  309. #define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))

  310. #define __HAL_DBGMCU_UNFREEZE_TIM6()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))

  311. #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */

  312. 

  313. #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)

  314. #define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))

  315. #define __HAL_DBGMCU_UNFREEZE_TIM7()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))

  316. #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */

  317. 

  318. #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)

  319. #define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))

  320. #define __HAL_DBGMCU_UNFREEZE_TIM14()        (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))

  321. #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */

  322. 

  323. #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)

  324. #define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))

  325. #define __HAL_DBGMCU_UNFREEZE_TIM1()         (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))

  326. #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */

  327. 

  328. #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)

  329. #define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))

  330. #define __HAL_DBGMCU_UNFREEZE_TIM15()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))

  331. #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */

  332. 

  333. #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)

  334. #define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))

  335. #define __HAL_DBGMCU_UNFREEZE_TIM16()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))

  336. #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */

  337. 

  338. #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)

  339. #define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))

  340. #define __HAL_DBGMCU_UNFREEZE_TIM17()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))

  341. #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */

  342. 

  343. /**

  344.   * @}

  345.   */

  346. 

  347. /** @defgroup Memory_Mapping_Selection Memory Mapping Selection

  348.   * @{

  349.   */

  350. #if defined(SYSCFG_CFGR1_MEM_MODE)

  351. /** @brief  Main Flash memory mapped at 0x00000000

  352.   */

  353. #define __HAL_SYSCFG_REMAPMEMORY_FLASH()        (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))

  354. #endif /* SYSCFG_CFGR1_MEM_MODE */

  355. 

  356. #if defined(SYSCFG_CFGR1_MEM_MODE_0)

  357. /** @brief  System Flash memory mapped at 0x00000000

  358.   */

  359. #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()  do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \

  360.                                              SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0;  \

  361.                                             }while(0)

  362. #endif /* SYSCFG_CFGR1_MEM_MODE_0 */

  363. 

  364. #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)

  365. /** @brief  Embedded SRAM mapped at 0x00000000

  366.   */

  367. #define __HAL_SYSCFG_REMAPMEMORY_SRAM()         do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \

  368.                                              SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \

  369.                                             }while(0)

  370. #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */

  371. /**

  372.   * @}

  373.   */

  374. 

  375. 

  376. #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)

  377. /** @defgroup HAL_Pin_remap HAL Pin remap

  378.   * @brief  Pin remapping enable/disable macros

  379.   * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping

  380.   * @{

  381.   */

  382. #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__)          do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__)));                 \

  383.                                                            SYSCFG->CFGR1 |= (__PIN_REMAP__);                                \

  384.                                                          }while(0)

  385. #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__)         do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__)));                 \

  386.                                                            SYSCFG->CFGR1 &= ~(__PIN_REMAP__);                               \

  387.                                                          }while(0)

  388. /**

  389.   * @}

  390.   */

  391. #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */

  392. 

  393. /** @brief  Fast-mode Plus driving capability enable/disable macros

  394.   * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.

  395.   *                          That you can find above these macros.

  396.   */

  397. #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\

  398.                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\

  399.                                                                }while(0)

  400. 

  401. #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\

  402.                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\

  403.                                                                }while(0)

  404. #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)

  405. /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable

  406.   * @{

  407.   */

  408. /** @brief  SYSCFG Break Lockup lock

  409.   *         Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input

  410.   * @note   The selected configuration is locked and can be unlocked by system reset

  411.   */

  412. #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()   do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \

  413.                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \

  414.                                               }while(0)

  415. /**

  416.   * @}

  417.   */

  418. #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */

  419. 

  420. #if defined(SYSCFG_CFGR2_PVD_LOCK)

  421. /** @defgroup PVD_Lock_Enable PVD Lock

  422.   * @{

  423.   */

  424. /** @brief  SYSCFG Break PVD lock

  425.   *         Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register

  426.   * @note   The selected configuration is locked and can be unlocked by system reset

  427.   */

  428. #define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \

  429.                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \

  430.                                               }while(0)

  431. /**

  432.   * @}

  433.   */

  434. #endif /* SYSCFG_CFGR2_PVD_LOCK */

  435. 

  436. #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)

  437. /** @defgroup SRAM_Parity_Lock SRAM Parity Lock

  438.   * @{

  439.   */

  440. /** @brief  SYSCFG Break SRAM PARITY lock

  441.   *         Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17

  442.   * @note   The selected configuration is locked and can be unlocked by system reset

  443.   */

  444. #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \

  445.                                                  SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK;    \

  446.                                                 }while(0)

  447. /**

  448.   * @}

  449.   */

  450. #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */

  451. 

  452. #if defined(SYSCFG_CFGR2_SRAM_PEF)

  453. /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM

  454.   * @brief  Parity check on RAM disable macro

  455.   * @note   Disabling the parity check on RAM locks the configuration bit.

  456.   *         To re-enable the parity check on RAM perform a system reset.

  457.   * @{

  458.   */

  459. #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE()   (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)

  460. /**

  461.   * @}

  462.   */

  463. #endif /* SYSCFG_CFGR2_SRAM_PEF */

  464. 

  465. 

  466. #if defined(STM32F091xC) || defined (STM32F098xx)

  467. /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check

  468.   * @brief  ISR wrapper check

  469.   * @note This feature is applicable on STM32F09x

  470.   * @note Allow to determine interrupt source per line.

  471.   * @{

  472.   */

  473. #define __HAL_GET_PENDING_IT(__SOURCE__)       (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))

  474. /**

  475.   * @}

  476.   */

  477. #endif /* (STM32F091xC) || defined (STM32F098xx)*/

  478. 

  479. #if defined(STM32F091xC) || defined (STM32F098xx)

  480. /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection

  481.   * @brief  selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register

  482.   * @note This feature is applicable on STM32F09x

  483.   * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL

  484.   * @{

  485.   */

  486. #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)  do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \

  487.                                                          SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \

  488.                                                          SYSCFG->CFGR1 |= (__SOURCE__);    \

  489.                                                         }while(0)

  490. 

  491. #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()  ((SYSCFG->CFGR1) & 0x000000C0)

  492. /**

  493.   * @}

  494.   */

  495. #endif /* (STM32F091xC) || defined (STM32F098xx)*/

  496. 

  497. /**

  498.   * @}

  499.   */

  500. 

  501. /* Exported functions --------------------------------------------------------*/

  502. 

  503. /** @addtogroup HAL_Exported_Functions

  504.   * @{

  505.   */

  506. 

  507. /** @addtogroup HAL_Exported_Functions_Group1

  508.   * @{

  509.   */

  510. /* Initialization and de-initialization functions  ******************************/

  511. HAL_StatusTypeDef HAL_Init(void);

  512. HAL_StatusTypeDef HAL_DeInit(void);

  513. void              HAL_MspInit(void);

  514. void              HAL_MspDeInit(void);

  515. HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);

  516. /**

  517.   * @}

  518.   */

  519. 

  520. /** @addtogroup HAL_Exported_Functions_Group2

  521.   * @{

  522.   */

  523. 

  524. /* Peripheral Control functions  ************************************************/

  525. void              HAL_IncTick(void);

  526. void              HAL_Delay(__IO uint32_t Delay);

  527. uint32_t          HAL_GetTick(void);

  528. void              HAL_SuspendTick(void);

  529. void              HAL_ResumeTick(void);

  530. uint32_t          HAL_GetHalVersion(void);

  531. uint32_t          HAL_GetREVID(void);

  532. uint32_t          HAL_GetDEVID(void);

  533. uint32_t          HAL_GetUIDw0(void);

  534. uint32_t          HAL_GetUIDw1(void);

  535. uint32_t          HAL_GetUIDw2(void);

  536. void              HAL_DBGMCU_EnableDBGStopMode(void);

  537. void              HAL_DBGMCU_DisableDBGStopMode(void);

  538. void              HAL_DBGMCU_EnableDBGStandbyMode(void);

  539. void              HAL_DBGMCU_DisableDBGStandbyMode(void);

  540. /**

  541.   * @}

  542.   */

  543. 

  544. /**

  545.   * @}

  546.   */

  547. 

  548. /**

  549.   * @}

  550.   */

  551. 

  552. /**

  553.   * @}

  554.   */

  555. 

  556. #ifdef __cplusplus

  557. }

  558. #endif

  559. 

  560. #endif /* __STM32F0xx_HAL_H */

  561. 

  562. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/