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stm32lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32f0xx_hal_dma_ex.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of DMA HAL Extension module.

  6.   ******************************************************************************

  7.   * @attention

  8.   *

  9.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

  10.   *

  11.   * Redistribution and use in source and binary forms, with or without modification,

  12.   * are permitted provided that the following conditions are met:

  13.   *   1. Redistributions of source code must retain the above copyright notice,

  14.   *      this list of conditions and the following disclaimer.

  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,

  16.   *      this list of conditions and the following disclaimer in the documentation

  17.   *      and/or other materials provided with the distribution.

  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors

  19.   *      may be used to endorse or promote products derived from this software

  20.   *      without specific prior written permission.

  21.   *

  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  32.   *

  33.   ******************************************************************************

  34.   */

  35. 

  36. /* Define to prevent recursive inclusion -------------------------------------*/

  37. #ifndef __STM32F0xx_HAL_DMA_EX_H

  38. #define __STM32F0xx_HAL_DMA_EX_H

  39. 

  40. #ifdef __cplusplus

  41.  extern "C" {

  42. #endif

  43. 

  44. /* Includes ------------------------------------------------------------------*/

  45. #include "stm32f0xx_hal_def.h"

  46. 

  47. /** @addtogroup STM32F0xx_HAL_Driver

  48.   * @{

  49.   */

  50. 

  51. /** @defgroup DMAEx DMAEx

  52.   * @brief DMA HAL module driver

  53.   * @{

  54.   */

  55. 

  56. /* Exported types ------------------------------------------------------------*/

  57. /* Exported constants --------------------------------------------------------*/

  58. #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)

  59. /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants

  60.   * @{

  61.   */

  62. #define DMA1_CHANNEL1_RMP                                     0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */

  63. #define DMA1_CHANNEL2_RMP                                     0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */

  64. #define DMA1_CHANNEL3_RMP                                     0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */

  65. #define DMA1_CHANNEL4_RMP                                     0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */

  66. #define DMA1_CHANNEL5_RMP                                     0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */

  67. #if !defined(STM32F030xC)

  68. #define DMA1_CHANNEL6_RMP                                     0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */

  69. #define DMA1_CHANNEL7_RMP                                     0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */

  70. #define DMA2_CHANNEL1_RMP                                     0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */

  71. #define DMA2_CHANNEL2_RMP                                     0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */

  72. #define DMA2_CHANNEL3_RMP                                     0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */

  73. #define DMA2_CHANNEL4_RMP                                     0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */

  74. #define DMA2_CHANNEL5_RMP                                     0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */

  75. #endif /* !defined(STM32F030xC) */

  76. 

  77. /****************** DMA1 remap bit field definition********************/

  78. /* DMA1 - Channel 1 */

  79. #define HAL_DMA1_CH1_DEFAULT      (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */

  80. #define HAL_DMA1_CH1_ADC          (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC)       /*!< Remap ADC on DMA1 Channel 1*/

  81. #define HAL_DMA1_CH1_TIM17_CH1    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */

  82. #define HAL_DMA1_CH1_TIM17_UP     (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 1 */

  83. #define HAL_DMA1_CH1_USART1_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */

  84. #define HAL_DMA1_CH1_USART2_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */

  85. #define HAL_DMA1_CH1_USART3_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */

  86. #define HAL_DMA1_CH1_USART4_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */

  87. #define HAL_DMA1_CH1_USART5_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */

  88. #define HAL_DMA1_CH1_USART6_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */

  89. #if !defined(STM32F030xC)

  90. #define HAL_DMA1_CH1_USART7_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */

  91. #define HAL_DMA1_CH1_USART8_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */

  92. #endif /* !defined(STM32F030xC) */

  93. 

  94. /* DMA1 - Channel 2 */

  95. #define HAL_DMA1_CH2_DEFAULT      (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */

  96. #define HAL_DMA1_CH2_ADC          (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC)       /*!< Remap ADC on DMA1 channel 2 */

  97. #define HAL_DMA1_CH2_I2C1_TX      (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX)   /*!< Remap I2C1 Tx on DMA1 channel 2 */

  98. #define HAL_DMA1_CH2_SPI1_RX      (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX)   /*!< Remap SPI1 Rx on DMA1 channel 2 */

  99. #define HAL_DMA1_CH2_TIM1_CH1     (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1)  /*!< Remap TIM1 channel 1 on DMA1 channel 2 */

  100. #define HAL_DMA1_CH2_TIM17_CH1    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */

  101. #define HAL_DMA1_CH2_TIM17_UP     (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 2 */

  102. #define HAL_DMA1_CH2_USART1_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */

  103. #define HAL_DMA1_CH2_USART2_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */

  104. #define HAL_DMA1_CH2_USART3_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */

  105. #define HAL_DMA1_CH2_USART4_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */

  106. #define HAL_DMA1_CH2_USART5_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */

  107. #define HAL_DMA1_CH2_USART6_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */

  108. #if !defined(STM32F030xC)

  109. #define HAL_DMA1_CH2_USART7_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */

  110. #define HAL_DMA1_CH2_USART8_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */

  111. #endif /* !defined(STM32F030xC) */

  112. 

  113. /* DMA1 - Channel 3 */

  114. #define HAL_DMA1_CH3_DEFAULT      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */

  115. #define HAL_DMA1_CH3_TIM6_UP      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP)   /*!< Remap TIM6 up on DMA1 channel 3 */

  116. #if !defined(STM32F030xC)

  117. #define HAL_DMA1_CH3_DAC_CH1      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1)   /*!< Remap DAC Channel 1on DMA1 channel 3 */

  118. #endif /* !defined(STM32F030xC) */

  119. #define HAL_DMA1_CH3_I2C1_RX      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX)   /*!< Remap I2C1 Rx on DMA1 channel 3 */

  120. #define HAL_DMA1_CH3_SPI1_TX      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX)   /*!< Remap SPI1 Tx on DMA1 channel 3 */

  121. #define HAL_DMA1_CH3_TIM1_CH2     (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2)  /*!< Remap TIM1 channel 2 on DMA1 channel 3 */

  122. #if !defined(STM32F030xC)

  123. #define HAL_DMA1_CH3_TIM2_CH2     (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2)  /*!< Remap TIM2 channel 2 on DMA1 channel 3 */

  124. #endif /* !defined(STM32F030xC) */

  125. #define HAL_DMA1_CH3_TIM16_CH1    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */

  126. #define HAL_DMA1_CH3_TIM16_UP     (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 3 */

  127. #define HAL_DMA1_CH3_USART1_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */

  128. #define HAL_DMA1_CH3_USART2_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */

  129. #define HAL_DMA1_CH3_USART3_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */

  130. #define HAL_DMA1_CH3_USART4_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */

  131. #define HAL_DMA1_CH3_USART5_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */

  132. #define HAL_DMA1_CH3_USART6_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */

  133. #if !defined(STM32F030xC)

  134. #define HAL_DMA1_CH3_USART7_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */

  135. #define HAL_DMA1_CH3_USART8_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */

  136. #endif /* !defined(STM32F030xC) */

  137. 

  138. /* DMA1 - Channel 4 */

  139. #define HAL_DMA1_CH4_DEFAULT      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */

  140. #define HAL_DMA1_CH4_TIM7_UP      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP)   /*!< Remap TIM7 up on DMA1 channel 4 */

  141. #if !defined(STM32F030xC)

  142. #define HAL_DMA1_CH4_DAC_CH2      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2)   /*!< Remap DAC Channel 2 on DMA1 channel 4 */

  143. #endif /* !defined(STM32F030xC) */

  144. #define HAL_DMA1_CH4_I2C2_TX      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX)   /*!< Remap I2C2 Tx on DMA1 channel 4 */

  145. #define HAL_DMA1_CH4_SPI2_RX      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX)   /*!< Remap SPI2 Rx on DMA1 channel 4 */

  146. #if !defined(STM32F030xC)

  147. #define HAL_DMA1_CH4_TIM2_CH4     (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4)  /*!< Remap TIM2 channel 4 on DMA1 channel 4 */

  148. #endif /* !defined(STM32F030xC) */

  149. #define HAL_DMA1_CH4_TIM3_CH1     (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1)  /*!< Remap TIM3 channel 1 on DMA1 channel 4 */

  150. #define HAL_DMA1_CH4_TIM3_TRIG    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */

  151. #define HAL_DMA1_CH4_TIM16_CH1    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */

  152. #define HAL_DMA1_CH4_TIM16_UP     (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 4 */

  153. #define HAL_DMA1_CH4_USART1_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */

  154. #define HAL_DMA1_CH4_USART2_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */

  155. #define HAL_DMA1_CH4_USART3_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */

  156. #define HAL_DMA1_CH4_USART4_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */

  157. #define HAL_DMA1_CH4_USART5_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */

  158. #define HAL_DMA1_CH4_USART6_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */

  159. #if !defined(STM32F030xC)

  160. #define HAL_DMA1_CH4_USART7_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */

  161. #define HAL_DMA1_CH4_USART8_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */

  162. #endif /* !defined(STM32F030xC) */

  163. 

  164. /* DMA1 - Channel 5 */

  165. #define HAL_DMA1_CH5_DEFAULT      (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */

  166. #define HAL_DMA1_CH5_I2C2_RX      (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX)   /*!< Remap I2C2 Rx on DMA1 channel 5 */

  167. #define HAL_DMA1_CH5_SPI2_TX      (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX)   /*!< Remap SPI1 Tx on DMA1 channel 5 */

  168. #define HAL_DMA1_CH5_TIM1_CH3     (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3)  /*!< Remap TIM1 channel 3 on DMA1 channel 5 */

  169. #define HAL_DMA1_CH5_USART1_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */

  170. #define HAL_DMA1_CH5_USART2_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */

  171. #define HAL_DMA1_CH5_USART3_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */

  172. #define HAL_DMA1_CH5_USART4_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */

  173. #define HAL_DMA1_CH5_USART5_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */

  174. #define HAL_DMA1_CH5_USART6_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */

  175. #if !defined(STM32F030xC)

  176. #define HAL_DMA1_CH5_USART7_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */

  177. #define HAL_DMA1_CH5_USART8_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */

  178. #endif /* !defined(STM32F030xC) */

  179. 

  180. #if !defined(STM32F030xC)

  181. /* DMA1 - Channel 6 */

  182. #define HAL_DMA1_CH6_DEFAULT      (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */

  183. #define HAL_DMA1_CH6_I2C1_TX      (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX)   /*!< Remap I2C1 Tx on DMA1 channel 6 */

  184. #define HAL_DMA1_CH6_SPI2_RX      (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX)   /*!< Remap SPI2 Rx on DMA1 channel 6 */

  185. #define HAL_DMA1_CH6_TIM1_CH1     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1)  /*!< Remap TIM1 channel 1 on DMA1 channel 6 */

  186. #define HAL_DMA1_CH6_TIM1_CH2     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2)  /*!< Remap TIM1 channel 2 on DMA1 channel 6 */

  187. #define HAL_DMA1_CH6_TIM1_CH3     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3)  /*!< Remap TIM1 channel 3 on DMA1 channel 6 */

  188. #define HAL_DMA1_CH6_TIM3_CH1     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1)  /*!< Remap TIM3 channel 1 on DMA1 channel 6 */

  189. #define HAL_DMA1_CH6_TIM3_TRIG    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */

  190. #define HAL_DMA1_CH6_TIM16_CH1    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */

  191. #define HAL_DMA1_CH6_TIM16_UP     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 6 */

  192. #define HAL_DMA1_CH6_USART1_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */

  193. #define HAL_DMA1_CH6_USART2_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */

  194. #define HAL_DMA1_CH6_USART3_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */

  195. #define HAL_DMA1_CH6_USART4_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */

  196. #define HAL_DMA1_CH6_USART5_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */

  197. #define HAL_DMA1_CH6_USART6_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */

  198. #define HAL_DMA1_CH6_USART7_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */

  199. #define HAL_DMA1_CH6_USART8_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */

  200. /* DMA1 - Channel 7 */

  201. #define HAL_DMA1_CH7_DEFAULT      (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */

  202. #define HAL_DMA1_CH7_I2C1_RX      (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX)   /*!< Remap I2C1 Rx on DMA1 channel 7 */

  203. #define HAL_DMA1_CH7_SPI2_TX      (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX)   /*!< Remap SPI2 Tx on DMA1 channel 7 */

  204. #define HAL_DMA1_CH7_TIM2_CH2     (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2)  /*!< Remap TIM2 channel 2 on DMA1 channel 7 */

  205. #define HAL_DMA1_CH7_TIM2_CH4     (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4)  /*!< Remap TIM2 channel 4 on DMA1 channel 7 */

  206. #define HAL_DMA1_CH7_TIM17_CH1    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */

  207. #define HAL_DMA1_CH7_TIM17_UP     (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 7 */

  208. #define HAL_DMA1_CH7_USART1_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */

  209. #define HAL_DMA1_CH7_USART2_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */

  210. #define HAL_DMA1_CH7_USART3_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */

  211. #define HAL_DMA1_CH7_USART4_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */

  212. #define HAL_DMA1_CH7_USART5_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */

  213. #define HAL_DMA1_CH7_USART6_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */

  214. #define HAL_DMA1_CH7_USART7_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */

  215. #define HAL_DMA1_CH7_USART8_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */

  216. 

  217. /****************** DMA2 remap bit field definition********************/

  218. /* DMA2 - Channel 1 */

  219. #define HAL_DMA2_CH1_DEFAULT      (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */

  220. #define HAL_DMA2_CH1_I2C2_TX      (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX)   /*!< Remap I2C2 TX on DMA2 channel 1 */

  221. #define HAL_DMA2_CH1_USART1_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */

  222. #define HAL_DMA2_CH1_USART2_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */

  223. #define HAL_DMA2_CH1_USART3_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */

  224. #define HAL_DMA2_CH1_USART4_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */

  225. #define HAL_DMA2_CH1_USART5_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */

  226. #define HAL_DMA2_CH1_USART6_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */

  227. #define HAL_DMA2_CH1_USART7_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */

  228. #define HAL_DMA2_CH1_USART8_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */

  229. /* DMA2 - Channel 2 */

  230. #define HAL_DMA2_CH2_DEFAULT      (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */

  231. #define HAL_DMA2_CH2_I2C2_RX      (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX)   /*!< Remap I2C2 Rx on DMA2 channel 2 */

  232. #define HAL_DMA2_CH2_USART1_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */

  233. #define HAL_DMA2_CH2_USART2_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */

  234. #define HAL_DMA2_CH2_USART3_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */

  235. #define HAL_DMA2_CH2_USART4_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */

  236. #define HAL_DMA2_CH2_USART5_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */

  237. #define HAL_DMA2_CH2_USART6_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */

  238. #define HAL_DMA2_CH2_USART7_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */

  239. #define HAL_DMA2_CH2_USART8_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */

  240. /* DMA2 - Channel 3 */

  241. #define HAL_DMA2_CH3_DEFAULT      (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */

  242. #define HAL_DMA2_CH3_TIM6_UP      (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP)   /*!< Remap TIM6 up on DMA2 channel 3 */

  243. #define HAL_DMA2_CH3_DAC_CH1      (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1)   /*!< Remap DAC channel 1 on DMA2 channel 3 */

  244. #define HAL_DMA2_CH3_SPI1_RX      (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX)   /*!< Remap SPI1 Rx on DMA2 channel 3 */

  245. #define HAL_DMA2_CH3_USART1_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */

  246. #define HAL_DMA2_CH3_USART2_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */

  247. #define HAL_DMA2_CH3_USART3_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */

  248. #define HAL_DMA2_CH3_USART4_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */

  249. #define HAL_DMA2_CH3_USART5_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */

  250. #define HAL_DMA2_CH3_USART6_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */

  251. #define HAL_DMA2_CH3_USART7_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */

  252. #define HAL_DMA2_CH3_USART8_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */

  253. /* DMA2 - Channel 4 */

  254. #define HAL_DMA2_CH4_DEFAULT      (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */

  255. #define HAL_DMA2_CH4_TIM7_UP      (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP)   /*!< Remap TIM7 up on DMA2 channel 4 */

  256. #define HAL_DMA2_CH4_DAC_CH2      (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2)   /*!< Remap DAC channel 2 on DMA2 channel 4 */

  257. #define HAL_DMA2_CH4_SPI1_TX      (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX)   /*!< Remap SPI1 Tx on DMA2 channel 4 */

  258. #define HAL_DMA2_CH4_USART1_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */

  259. #define HAL_DMA2_CH4_USART2_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */

  260. #define HAL_DMA2_CH4_USART3_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */

  261. #define HAL_DMA2_CH4_USART4_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */

  262. #define HAL_DMA2_CH4_USART5_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */

  263. #define HAL_DMA2_CH4_USART6_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */

  264. #define HAL_DMA2_CH4_USART7_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */

  265. #define HAL_DMA2_CH4_USART8_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */

  266. /* DMA2 - Channel 5 */

  267. #define HAL_DMA2_CH5_DEFAULT      (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */

  268. #define HAL_DMA2_CH5_ADC          (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC)       /*!< Remap ADC on DMA2 channel 5 */

  269. #define HAL_DMA2_CH5_USART1_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */

  270. #define HAL_DMA2_CH5_USART2_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */

  271. #define HAL_DMA2_CH5_USART3_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */

  272. #define HAL_DMA2_CH5_USART4_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */

  273. #define HAL_DMA2_CH5_USART5_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */

  274. #define HAL_DMA2_CH5_USART6_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */

  275. #define HAL_DMA2_CH5_USART7_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */

  276. #define HAL_DMA2_CH5_USART8_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */

  277. #endif /* !defined(STM32F030xC) */

  278. 

  279. #if defined(STM32F091xC) || defined(STM32F098xx)

  280. #define IS_HAL_DMA1_REMAP(REQUEST)  (((REQUEST) == HAL_DMA1_CH1_DEFAULT)  ||\

  281.                                     ((REQUEST) == HAL_DMA1_CH1_ADC)       ||\

  282.                                     ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\

  283.                                     ((REQUEST) == HAL_DMA1_CH1_TIM17_UP)  ||\

  284.                                     ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\

  285.                                     ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\

  286.                                     ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\

  287.                                     ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\

  288.                                     ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\

  289.                                     ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\

  290.                                     ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\

  291.                                     ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\

  292.                                     ((REQUEST) == HAL_DMA1_CH2_DEFAULT)   ||\

  293.                                     ((REQUEST) == HAL_DMA1_CH2_ADC)       ||\

  294.                                     ((REQUEST) == HAL_DMA1_CH2_I2C1_TX)   ||\

  295.                                     ((REQUEST) == HAL_DMA1_CH2_SPI1_RX)   ||\

  296.                                     ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1)  ||\

  297.                                     ((REQUEST) == HAL_DMA1_CH2_I2C1_TX)   ||\

  298.                                     ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\

  299.                                     ((REQUEST) == HAL_DMA1_CH2_TIM17_UP)  ||\

  300.                                     ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\

  301.                                     ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\

  302.                                     ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\

  303.                                     ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\

  304.                                     ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\

  305.                                     ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\

  306.                                     ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\

  307.                                     ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\

  308.                                     ((REQUEST) == HAL_DMA1_CH3_DEFAULT)   ||\

  309.                                     ((REQUEST) == HAL_DMA1_CH3_TIM6_UP)   ||\

  310.                                     ((REQUEST) == HAL_DMA1_CH3_DAC_CH1)   ||\

  311.                                     ((REQUEST) == HAL_DMA1_CH3_I2C1_RX)   ||\

  312.                                     ((REQUEST) == HAL_DMA1_CH3_SPI1_TX)   ||\

  313.                                     ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2)  ||\

  314.                                     ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2)  ||\

  315.                                     ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\

  316.                                     ((REQUEST) == HAL_DMA1_CH3_TIM16_UP)  ||\

  317.                                     ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\

  318.                                     ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\

  319.                                     ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\

  320.                                     ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\

  321.                                     ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\

  322.                                     ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\

  323.                                     ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\

  324.                                     ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\

  325.                                     ((REQUEST) == HAL_DMA1_CH4_DEFAULT)   ||\

  326.                                     ((REQUEST) == HAL_DMA1_CH4_TIM7_UP)   ||\

  327.                                     ((REQUEST) == HAL_DMA1_CH4_DAC_CH2)   ||\

  328.                                     ((REQUEST) == HAL_DMA1_CH4_I2C2_TX)   ||\

  329.                                     ((REQUEST) == HAL_DMA1_CH4_SPI2_RX)   ||\

  330.                                     ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4)  ||\

  331.                                     ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1)  ||\

  332.                                     ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\

  333.                                     ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\

  334.                                     ((REQUEST) == HAL_DMA1_CH4_TIM16_UP)  ||\

  335.                                     ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\

  336.                                     ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\

  337.                                     ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\

  338.                                     ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\

  339.                                     ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\

  340.                                     ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\

  341.                                     ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\

  342.                                     ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\

  343.                                     ((REQUEST) == HAL_DMA1_CH5_DEFAULT)   ||\

  344.                                     ((REQUEST) == HAL_DMA1_CH5_I2C2_RX)   ||\

  345.                                     ((REQUEST) == HAL_DMA1_CH5_SPI2_TX)   ||\

  346.                                     ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3)  ||\

  347.                                     ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\

  348.                                     ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\

  349.                                     ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\

  350.                                     ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\

  351.                                     ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\

  352.                                     ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\

  353.                                     ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\

  354.                                     ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\

  355.                                     ((REQUEST) == HAL_DMA1_CH6_DEFAULT)   ||\

  356.                                     ((REQUEST) == HAL_DMA1_CH6_I2C1_TX)   ||\

  357.                                     ((REQUEST) == HAL_DMA1_CH6_SPI2_RX)   ||\

  358.                                     ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1)  ||\

  359.                                     ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2)  ||\

  360.                                     ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3)  ||\

  361.                                     ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1)  ||\

  362.                                     ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\

  363.                                     ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\

  364.                                     ((REQUEST) == HAL_DMA1_CH6_TIM16_UP)  ||\

  365.                                     ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\

  366.                                     ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\

  367.                                     ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\

  368.                                     ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\

  369.                                     ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\

  370.                                     ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\

  371.                                     ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\

  372.                                     ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\

  373.                                     ((REQUEST) == HAL_DMA1_CH7_DEFAULT)   ||\

  374.                                     ((REQUEST) == HAL_DMA1_CH7_I2C1_RX)   ||\

  375.                                     ((REQUEST) == HAL_DMA1_CH7_SPI2_TX)   ||\

  376.                                     ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2)  ||\

  377.                                     ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4)  ||\

  378.                                     ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\

  379.                                     ((REQUEST) == HAL_DMA1_CH7_TIM17_UP)  ||\

  380.                                     ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\

  381.                                     ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\

  382.                                     ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\

  383.                                     ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\

  384.                                     ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\

  385.                                     ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\

  386.                                     ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\

  387.                                     ((REQUEST) == HAL_DMA1_CH7_USART8_TX))

  388. 

  389. #define IS_HAL_DMA2_REMAP(REQUEST)  (((REQUEST) == HAL_DMA2_CH1_DEFAULT)   ||\

  390.                                     ((REQUEST) == HAL_DMA2_CH1_I2C2_TX)   ||\

  391.                                     ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\

  392.                                     ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\

  393.                                     ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\

  394.                                     ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\

  395.                                     ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\

  396.                                     ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\

  397.                                     ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\

  398.                                     ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\

  399.                                     ((REQUEST) == HAL_DMA2_CH2_DEFAULT)   ||\

  400.                                     ((REQUEST) == HAL_DMA2_CH2_I2C2_RX)   ||\

  401.                                     ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\

  402.                                     ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\

  403.                                     ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\

  404.                                     ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\

  405.                                     ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\

  406.                                     ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\

  407.                                     ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\

  408.                                     ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\

  409.                                     ((REQUEST) == HAL_DMA2_CH3_DEFAULT)   ||\

  410.                                     ((REQUEST) == HAL_DMA2_CH3_TIM6_UP)   ||\

  411.                                     ((REQUEST) == HAL_DMA2_CH3_DAC_CH1)   ||\

  412.                                     ((REQUEST) == HAL_DMA2_CH3_SPI1_RX)   ||\

  413.                                     ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\

  414.                                     ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\

  415.                                     ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\

  416.                                     ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\

  417.                                     ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\

  418.                                     ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\

  419.                                     ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\

  420.                                     ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\

  421.                                     ((REQUEST) == HAL_DMA2_CH4_DEFAULT)   ||\

  422.                                     ((REQUEST) == HAL_DMA2_CH4_TIM7_UP)   ||\

  423.                                     ((REQUEST) == HAL_DMA2_CH4_DAC_CH2)   ||\

  424.                                     ((REQUEST) == HAL_DMA2_CH4_SPI1_TX)   ||\

  425.                                     ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\

  426.                                     ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\

  427.                                     ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\

  428.                                     ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\

  429.                                     ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\

  430.                                     ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\

  431.                                     ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\

  432.                                     ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\

  433.                                     ((REQUEST) == HAL_DMA2_CH5_DEFAULT)   ||\

  434.                                     ((REQUEST) == HAL_DMA2_CH5_ADC)       ||\

  435.                                     ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\

  436.                                     ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\

  437.                                     ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\

  438.                                     ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\

  439.                                     ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\

  440.                                     ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\

  441.                                     ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\

  442.                                     ((REQUEST) == HAL_DMA2_CH5_USART8_TX ))

  443. #endif /* STM32F091xC || STM32F098xx */

  444. 

  445. #if defined(STM32F030xC)

  446. #define IS_HAL_DMA1_REMAP(REQUEST)  (((REQUEST) == HAL_DMA1_CH1_DEFAULT)  ||\

  447.                                     ((REQUEST) == HAL_DMA1_CH1_ADC)       ||\

  448.                                     ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\

  449.                                     ((REQUEST) == HAL_DMA1_CH1_TIM17_UP)  ||\

  450.                                     ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\

  451.                                     ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\

  452.                                     ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\

  453.                                     ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\

  454.                                     ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\

  455.                                     ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\

  456.                                     ((REQUEST) == HAL_DMA1_CH2_DEFAULT)   ||\

  457.                                     ((REQUEST) == HAL_DMA1_CH2_ADC)       ||\

  458.                                     ((REQUEST) == HAL_DMA1_CH2_I2C1_TX)   ||\

  459.                                     ((REQUEST) == HAL_DMA1_CH2_SPI1_RX)   ||\

  460.                                     ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1)  ||\

  461.                                     ((REQUEST) == HAL_DMA1_CH2_I2C1_TX)   ||\

  462.                                     ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\

  463.                                     ((REQUEST) == HAL_DMA1_CH2_TIM17_UP)  ||\

  464.                                     ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\

  465.                                     ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\

  466.                                     ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\

  467.                                     ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\

  468.                                     ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\

  469.                                     ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\

  470.                                     ((REQUEST) == HAL_DMA1_CH3_DEFAULT)   ||\

  471.                                     ((REQUEST) == HAL_DMA1_CH3_TIM6_UP)   ||\

  472.                                     ((REQUEST) == HAL_DMA1_CH3_I2C1_RX)   ||\

  473.                                     ((REQUEST) == HAL_DMA1_CH3_SPI1_TX)   ||\

  474.                                     ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2)  ||\

  475.                                     ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\

  476.                                     ((REQUEST) == HAL_DMA1_CH3_TIM16_UP)  ||\

  477.                                     ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\

  478.                                     ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\

  479.                                     ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\

  480.                                     ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\

  481.                                     ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\

  482.                                     ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\

  483.                                     ((REQUEST) == HAL_DMA1_CH4_DEFAULT)   ||\

  484.                                     ((REQUEST) == HAL_DMA1_CH4_TIM7_UP)   ||\

  485.                                     ((REQUEST) == HAL_DMA1_CH4_I2C2_TX)   ||\

  486.                                     ((REQUEST) == HAL_DMA1_CH4_SPI2_RX)   ||\

  487.                                     ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1)  ||\

  488.                                     ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\

  489.                                     ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\

  490.                                     ((REQUEST) == HAL_DMA1_CH4_TIM16_UP)  ||\

  491.                                     ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\

  492.                                     ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\

  493.                                     ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\

  494.                                     ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\

  495.                                     ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\

  496.                                     ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\

  497.                                     ((REQUEST) == HAL_DMA1_CH5_DEFAULT)   ||\

  498.                                     ((REQUEST) == HAL_DMA1_CH5_I2C2_RX)   ||\

  499.                                     ((REQUEST) == HAL_DMA1_CH5_SPI2_TX)   ||\

  500.                                     ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3)  ||\

  501.                                     ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\

  502.                                     ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\

  503.                                     ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\

  504.                                     ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\

  505.                                     ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\

  506.                                     ((REQUEST) == HAL_DMA1_CH5_USART6_RX))

  507. #endif /* STM32F030xC */

  508. 

  509. /**

  510.   * @}

  511.   */

  512. #endif /* STM32F091xC  || STM32F098xx || STM32F030xC */

  513. 

  514. /* Exported macros -----------------------------------------------------------*/

  515. 

  516. /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros

  517.   * @{

  518.   */

  519. /* Interrupt & Flag management */

  520. 

  521. #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)

  522. /**

  523.   * @brief  Returns the current DMA Channel transfer complete flag.

  524.   * @param  __HANDLE__ DMA handle

  525.   * @retval The specified transfer complete flag index.

  526.   */

  527. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \

  528. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\

  529.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\

  530.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\

  531.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\

  532.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\

  533.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\

  534.    DMA_FLAG_TC7)

  535. 

  536. /**

  537.   * @brief  Returns the current DMA Channel half transfer complete flag.

  538.   * @param  __HANDLE__ DMA handle

  539.   * @retval The specified half transfer complete flag index.

  540.   */

  541. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\

  542. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\

  543.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\

  544.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\

  545.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\

  546.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\

  547.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\

  548.    DMA_FLAG_HT7)

  549. 

  550. /**

  551.   * @brief  Returns the current DMA Channel transfer error flag.

  552.   * @param  __HANDLE__ DMA handle

  553.   * @retval The specified transfer error flag index.

  554.   */

  555. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\

  556. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\

  557.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\

  558.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\

  559.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\

  560.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\

  561.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\

  562.    DMA_FLAG_TE7)

  563. 

  564. /**

  565.   * @brief  Return the current DMA Channel Global interrupt flag.

  566.   * @param  __HANDLE__ DMA handle

  567.   * @retval The specified transfer error flag index.

  568.   */

  569. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\

  570. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\

  571.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\

  572.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\

  573.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\

  574.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\

  575.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\

  576.    DMA_FLAG_GL7)

  577. 

  578. /**

  579.   * @brief  Get the DMA Channel pending flags.

  580.   * @param  __HANDLE__ DMA handle

  581.   * @param  __FLAG__ Get the specified flag.

  582.   *          This parameter can be any combination of the following values:

  583.   *            @arg DMA_FLAG_TCx:  Transfer complete flag

  584.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag

  585.   *            @arg DMA_FLAG_TEx:  Transfer error flag

  586.   *         Where x can be 1_7 to select the DMA Channel flag.

  587.   * @retval The state of FLAG (SET or RESET).

  588.   */

  589. 

  590. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))

  591. 

  592. /**

  593.   * @brief  Clears the DMA Channel pending flags.

  594.   * @param  __HANDLE__ DMA handle

  595.   * @param  __FLAG__ specifies the flag to clear.

  596.   *          This parameter can be any combination of the following values:

  597.   *            @arg DMA_FLAG_TCx:  Transfer complete flag

  598.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag

  599.   *            @arg DMA_FLAG_TEx:  Transfer error flag

  600.   *         Where x can be 1_7 to select the DMA Channel flag.

  601.   * @retval None

  602.   */

  603. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))

  604. 

  605. #elif defined(STM32F091xC) || defined(STM32F098xx)

  606. /**

  607.   * @brief  Returns the current DMA Channel transfer complete flag.

  608.   * @param  __HANDLE__ DMA handle

  609.   * @retval The specified transfer complete flag index.

  610.   */

  611. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \

  612. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\

  613.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\

  614.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\

  615.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\

  616.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\

  617.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\

  618.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\

  619.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\

  620.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\

  621.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\

  622.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\

  623.    DMA_FLAG_TC5)

  624. 

  625. /**

  626.   * @brief  Returns the current DMA Channel half transfer complete flag.

  627.   * @param  __HANDLE__ DMA handle

  628.   * @retval The specified half transfer complete flag index.

  629.   */

  630. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\

  631. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\

  632.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\

  633.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\

  634.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\

  635.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\

  636.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\

  637.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\

  638.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\

  639.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\

  640.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\

  641.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\

  642.    DMA_FLAG_HT5)

  643. 

  644. /**

  645.   * @brief  Returns the current DMA Channel transfer error flag.

  646.   * @param  __HANDLE__ DMA handle

  647.   * @retval The specified transfer error flag index.

  648.   */

  649. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\

  650. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\

  651.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\

  652.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\

  653.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\

  654.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\

  655.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\

  656.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\

  657.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\

  658.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\

  659.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\

  660.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\

  661.    DMA_FLAG_TE5)

  662. 

  663. /**

  664.   * @brief  Return the current DMA Channel Global interrupt flag.

  665.   * @param  __HANDLE__ DMA handle

  666.   * @retval The specified transfer error flag index.

  667.   */

  668. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\

  669. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\

  670.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\

  671.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\

  672.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\

  673.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\

  674.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\

  675.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\

  676.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\

  677.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\

  678.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\

  679.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\

  680.    DMA_FLAG_GL5)

  681. 

  682. /**

  683.   * @brief  Get the DMA Channel pending flags.

  684.   * @param  __HANDLE__ DMA handle

  685.   * @param  __FLAG__ Get the specified flag.

  686.   *          This parameter can be any combination of the following values:

  687.   *            @arg DMA_FLAG_TCx:  Transfer complete flag

  688.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag

  689.   *            @arg DMA_FLAG_TEx:  Transfer error flag

  690.   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.

  691.   * @retval The state of FLAG (SET or RESET).

  692.   */

  693. 

  694. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\

  695. (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\

  696.   (DMA1->ISR & (__FLAG__)))

  697. 

  698. /**

  699.   * @brief  Clears the DMA Channel pending flags.

  700.   * @param  __HANDLE__ DMA handle

  701.   * @param  __FLAG__ specifies the flag to clear.

  702.   *          This parameter can be any combination of the following values:

  703.   *            @arg DMA_FLAG_TCx:  Transfer complete flag

  704.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag

  705.   *            @arg DMA_FLAG_TEx:  Transfer error flag

  706.   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.

  707.   * @retval None

  708.   */

  709. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \

  710. (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\

  711.   (DMA1->IFCR = (__FLAG__)))

  712. 

  713. #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */

  714. /**

  715.   * @brief  Returns the current DMA Channel transfer complete flag.

  716.   * @param  __HANDLE__ DMA handle

  717.   * @retval The specified transfer complete flag index.

  718.   */

  719. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \

  720. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\

  721.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\

  722.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\

  723.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\

  724.    DMA_FLAG_TC5)

  725. 

  726. /**

  727.   * @brief  Returns the current DMA Channel half transfer complete flag.

  728.   * @param  __HANDLE__ DMA handle

  729.   * @retval The specified half transfer complete flag index.

  730.   */

  731. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\

  732. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\

  733.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\

  734.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\

  735.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\

  736.    DMA_FLAG_HT5)

  737. 

  738. /**

  739.   * @brief  Returns the current DMA Channel transfer error flag.

  740.   * @param  __HANDLE__ DMA handle

  741.   * @retval The specified transfer error flag index.

  742.   */

  743. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\

  744. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\

  745.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\

  746.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\

  747.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\

  748.    DMA_FLAG_TE5)

  749. 

  750. /**

  751.   * @brief  Return the current DMA Channel Global interrupt flag.

  752.   * @param  __HANDLE__ DMA handle

  753.   * @retval The specified transfer error flag index.

  754.   */

  755. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\

  756. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\

  757.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\

  758.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\

  759.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\

  760.    DMA_FLAG_GL5)

  761. 

  762. /**

  763.   * @brief  Get the DMA Channel pending flags.

  764.   * @param  __HANDLE__ DMA handle

  765.   * @param  __FLAG__ Get the specified flag.

  766.   *          This parameter can be any combination of the following values:

  767.   *            @arg DMA_FLAG_TCx:  Transfer complete flag

  768.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag

  769.   *            @arg DMA_FLAG_TEx:  Transfer error flag

  770.   *         Where x can be 1_5 to select the DMA Channel flag.

  771.   * @retval The state of FLAG (SET or RESET).

  772.   */

  773. 

  774. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))

  775. 

  776. /**

  777.   * @brief  Clears the DMA Channel pending flags.

  778.   * @param  __HANDLE__ DMA handle

  779.   * @param  __FLAG__ specifies the flag to clear.

  780.   *          This parameter can be any combination of the following values:

  781.   *            @arg DMA_FLAG_TCx:  Transfer complete flag

  782.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag

  783.   *            @arg DMA_FLAG_TEx:  Transfer error flag

  784.   *         Where x can be 1_5 to select the DMA Channel flag.

  785.   * @retval None

  786.   */

  787. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))

  788. 

  789. #endif

  790. 

  791. 

  792. #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)

  793. #define __HAL_DMA1_REMAP(__REQUEST__)                                                              \

  794.          do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__));                                             \

  795.               DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \

  796.               DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU);                                     \

  797.   }while(0)

  798. 

  799. #if defined(STM32F091xC) || defined(STM32F098xx)

  800. #define __HAL_DMA2_REMAP(__REQUEST__)                                                              \

  801.          do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__));                                             \

  802.               DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \

  803.               DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU);                                     \

  804.          }while(0)

  805. #endif /* STM32F091xC || STM32F098xx */

  806. 

  807. #endif /* STM32F091xC || STM32F098xx || STM32F030xC */

  808. 

  809. /**

  810.   * @}

  811.   */

  812. 

  813. /**

  814.   * @}

  815.   */

  816. 

  817. /**

  818.   * @}

  819.   */

  820. 

  821. #ifdef __cplusplus

  822. }

  823. #endif

  824. 

  825. #endif /* __STM32F0xx_HAL_DMA_EX_H */

  826. 

  827. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/