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  1. /**
  2. ******************************************************************************
  3. * @file stm32f0xx_ll_bus.h
  4. * @author MCD Application Team
  5. * @brief Header file of BUS LL module.
  6. @verbatim
  7. ##### RCC Limitations #####
  8. ==============================================================================
  9. [..]
  10. A delay between an RCC peripheral clock enable and the effective peripheral
  11. enabling should be taken into account in order to manage the peripheral read/write
  12. from/to registers.
  13. (+) This delay depends on the peripheral mapping.
  14. (++) AHB & APB peripherals, 1 dummy read is necessary
  15. [..]
  16. Workarounds:
  17. (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
  18. inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
  19. @endverbatim
  20. ******************************************************************************
  21. * @attention
  22. *
  23. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  24. *
  25. * Redistribution and use in source and binary forms, with or without modification,
  26. * are permitted provided that the following conditions are met:
  27. * 1. Redistributions of source code must retain the above copyright notice,
  28. * this list of conditions and the following disclaimer.
  29. * 2. Redistributions in binary form must reproduce the above copyright notice,
  30. * this list of conditions and the following disclaimer in the documentation
  31. * and/or other materials provided with the distribution.
  32. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  33. * may be used to endorse or promote products derived from this software
  34. * without specific prior written permission.
  35. *
  36. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  37. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  38. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  39. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  40. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  41. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  42. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  43. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  44. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46. *
  47. ******************************************************************************
  48. */
  49. /* Define to prevent recursive inclusion -------------------------------------*/
  50. #ifndef __STM32F0xx_LL_BUS_H
  51. #define __STM32F0xx_LL_BUS_H
  52. #ifdef __cplusplus
  53. extern "C" {
  54. #endif
  55. /* Includes ------------------------------------------------------------------*/
  56. #include "stm32f0xx.h"
  57. /** @addtogroup STM32F0xx_LL_Driver
  58. * @{
  59. */
  60. #if defined(RCC)
  61. /** @defgroup BUS_LL BUS
  62. * @{
  63. */
  64. /* Private types -------------------------------------------------------------*/
  65. /* Private variables ---------------------------------------------------------*/
  66. /* Private constants ---------------------------------------------------------*/
  67. /* Private macros ------------------------------------------------------------*/
  68. /* Exported types ------------------------------------------------------------*/
  69. /* Exported constants --------------------------------------------------------*/
  70. /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
  71. * @{
  72. */
  73. /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
  74. * @{
  75. */
  76. #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  77. #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
  78. #if defined(DMA2)
  79. #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
  80. #endif /*DMA2*/
  81. #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
  82. #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
  83. #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
  84. #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
  85. #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
  86. #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
  87. #if defined(GPIOD)
  88. #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
  89. #endif /*GPIOD*/
  90. #if defined(GPIOE)
  91. #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
  92. #endif /*GPIOE*/
  93. #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
  94. #if defined(TSC)
  95. #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
  96. #endif /*TSC*/
  97. /**
  98. * @}
  99. */
  100. /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
  101. * @{
  102. */
  103. #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  104. #if defined(TIM2)
  105. #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
  106. #endif /*TIM2*/
  107. #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
  108. #if defined(TIM6)
  109. #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
  110. #endif /*TIM6*/
  111. #if defined(TIM7)
  112. #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
  113. #endif /*TIM7*/
  114. #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
  115. #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
  116. #if defined(SPI2)
  117. #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
  118. #endif /*SPI2*/
  119. #if defined(USART2)
  120. #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
  121. #endif /* USART2 */
  122. #if defined(USART3)
  123. #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
  124. #endif /* USART3 */
  125. #if defined(USART4)
  126. #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
  127. #endif /* USART4 */
  128. #if defined(USART5)
  129. #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
  130. #endif /* USART5 */
  131. #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
  132. #if defined(I2C2)
  133. #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
  134. #endif /*I2C2*/
  135. #if defined(USB)
  136. #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
  137. #endif /* USB */
  138. #if defined(CAN)
  139. #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
  140. #endif /*CAN*/
  141. #if defined(CRS)
  142. #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
  143. #endif /*CRS*/
  144. #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
  145. #if defined(DAC)
  146. #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
  147. #endif /*DAC*/
  148. #if defined(CEC)
  149. #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
  150. #endif /*CEC*/
  151. /**
  152. * @}
  153. */
  154. /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
  155. * @{
  156. */
  157. #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  158. #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
  159. #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
  160. #if defined(USART8)
  161. #define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN
  162. #endif /*USART8*/
  163. #if defined(USART7)
  164. #define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN
  165. #endif /*USART7*/
  166. #if defined(USART6)
  167. #define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN
  168. #endif /*USART6*/
  169. #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
  170. #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
  171. #define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN
  172. #if defined(TIM15)
  173. #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
  174. #endif /*TIM15*/
  175. #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
  176. #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
  177. #define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN
  178. /**
  179. * @}
  180. */
  181. /**
  182. * @}
  183. */
  184. /* Exported macro ------------------------------------------------------------*/
  185. /* Exported functions --------------------------------------------------------*/
  186. /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
  187. * @{
  188. */
  189. /** @defgroup BUS_LL_EF_AHB1 AHB1
  190. * @{
  191. */
  192. /**
  193. * @brief Enable AHB1 peripherals clock.
  194. * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
  195. * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
  196. * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
  197. * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
  198. * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
  199. * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
  200. * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
  201. * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
  202. * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
  203. * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
  204. * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
  205. * AHBENR TSCEN LL_AHB1_GRP1_EnableClock
  206. * @param Periphs This parameter can be a combination of the following values:
  207. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  208. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  209. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  210. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  211. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  212. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
  213. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
  214. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
  215. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
  216. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
  217. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
  218. * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
  219. *
  220. * (*) value not defined in all devices.
  221. * @retval None
  222. */
  223. __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
  224. {
  225. __IO uint32_t tmpreg;
  226. SET_BIT(RCC->AHBENR, Periphs);
  227. /* Delay after an RCC peripheral clock enabling */
  228. tmpreg = READ_BIT(RCC->AHBENR, Periphs);
  229. (void)tmpreg;
  230. }
  231. /**
  232. * @brief Check if AHB1 peripheral clock is enabled or not
  233. * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
  234. * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
  235. * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
  236. * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
  237. * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
  238. * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
  239. * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
  240. * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
  241. * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
  242. * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
  243. * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
  244. * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
  245. * @param Periphs This parameter can be a combination of the following values:
  246. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  247. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  248. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  249. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  250. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  251. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
  252. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
  253. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
  254. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
  255. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
  256. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
  257. * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
  258. *
  259. * (*) value not defined in all devices.
  260. * @retval State of Periphs (1 or 0).
  261. */
  262. __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
  263. {
  264. return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
  265. }
  266. /**
  267. * @brief Disable AHB1 peripherals clock.
  268. * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
  269. * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
  270. * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
  271. * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
  272. * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
  273. * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
  274. * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
  275. * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
  276. * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
  277. * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
  278. * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
  279. * AHBENR TSCEN LL_AHB1_GRP1_DisableClock
  280. * @param Periphs This parameter can be a combination of the following values:
  281. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  282. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  283. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  284. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  285. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  286. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
  287. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
  288. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
  289. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
  290. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
  291. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
  292. * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
  293. *
  294. * (*) value not defined in all devices.
  295. * @retval None
  296. */
  297. __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
  298. {
  299. CLEAR_BIT(RCC->AHBENR, Periphs);
  300. }
  301. /**
  302. * @brief Force AHB1 peripherals reset.
  303. * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
  304. * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
  305. * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
  306. * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
  307. * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
  308. * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
  309. * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
  310. * @param Periphs This parameter can be a combination of the following values:
  311. * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
  312. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
  313. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
  314. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
  315. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
  316. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
  317. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
  318. * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
  319. *
  320. * (*) value not defined in all devices.
  321. * @retval None
  322. */
  323. __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
  324. {
  325. SET_BIT(RCC->AHBRSTR, Periphs);
  326. }
  327. /**
  328. * @brief Release AHB1 peripherals reset.
  329. * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
  330. * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
  331. * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
  332. * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
  333. * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
  334. * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
  335. * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
  336. * @param Periphs This parameter can be a combination of the following values:
  337. * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
  338. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
  339. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
  340. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
  341. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
  342. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
  343. * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
  344. * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
  345. *
  346. * (*) value not defined in all devices.
  347. * @retval None
  348. */
  349. __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
  350. {
  351. CLEAR_BIT(RCC->AHBRSTR, Periphs);
  352. }
  353. /**
  354. * @}
  355. */
  356. /** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
  357. * @{
  358. */
  359. /**
  360. * @brief Enable APB1 peripherals clock (available in register 1).
  361. * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
  362. * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
  363. * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
  364. * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
  365. * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
  366. * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
  367. * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
  368. * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
  369. * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
  370. * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
  371. * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
  372. * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
  373. * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
  374. * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
  375. * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
  376. * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
  377. * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
  378. * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
  379. * APB1ENR CECEN LL_APB1_GRP1_EnableClock
  380. * @param Periphs This parameter can be a combination of the following values:
  381. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
  382. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  383. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  384. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  385. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
  386. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  387. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  388. * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
  389. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  390. * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
  391. * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
  392. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  393. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  394. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  395. * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
  396. * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
  397. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  398. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  399. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  400. *
  401. * (*) value not defined in all devices.
  402. * @retval None
  403. */
  404. __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
  405. {
  406. __IO uint32_t tmpreg;
  407. SET_BIT(RCC->APB1ENR, Periphs);
  408. /* Delay after an RCC peripheral clock enabling */
  409. tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
  410. (void)tmpreg;
  411. }
  412. /**
  413. * @brief Check if APB1 peripheral clock is enabled or not (available in register 1).
  414. * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
  415. * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
  416. * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
  417. * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
  418. * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
  419. * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
  420. * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
  421. * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
  422. * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
  423. * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
  424. * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
  425. * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
  426. * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
  427. * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
  428. * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
  429. * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
  430. * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
  431. * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
  432. * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
  433. * @param Periphs This parameter can be a combination of the following values:
  434. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
  435. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  436. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  437. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  438. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
  439. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  440. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  441. * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
  442. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  443. * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
  444. * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
  445. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  446. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  447. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  448. * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
  449. * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
  450. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  451. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  452. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  453. *
  454. * (*) value not defined in all devices.
  455. * @retval State of Periphs (1 or 0).
  456. */
  457. __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
  458. {
  459. return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
  460. }
  461. /**
  462. * @brief Disable APB1 peripherals clock (available in register 1).
  463. * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
  464. * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
  465. * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
  466. * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
  467. * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
  468. * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
  469. * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
  470. * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
  471. * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
  472. * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
  473. * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
  474. * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
  475. * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
  476. * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
  477. * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
  478. * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
  479. * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
  480. * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
  481. * APB1ENR CECEN LL_APB1_GRP1_DisableClock
  482. * @param Periphs This parameter can be a combination of the following values:
  483. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
  484. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  485. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  486. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  487. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
  488. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  489. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  490. * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
  491. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  492. * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
  493. * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
  494. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  495. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  496. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  497. * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
  498. * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
  499. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  500. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  501. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  502. *
  503. * (*) value not defined in all devices.
  504. * @retval None
  505. */
  506. __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
  507. {
  508. CLEAR_BIT(RCC->APB1ENR, Periphs);
  509. }
  510. /**
  511. * @brief Force APB1 peripherals reset (available in register 1).
  512. * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
  513. * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
  514. * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
  515. * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
  516. * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
  517. * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
  518. * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
  519. * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
  520. * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
  521. * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
  522. * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
  523. * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
  524. * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
  525. * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
  526. * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
  527. * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
  528. * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
  529. * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
  530. * APB1RSTR CECRST LL_APB1_GRP1_ForceReset
  531. * @param Periphs This parameter can be a combination of the following values:
  532. * @arg @ref LL_APB1_GRP1_PERIPH_ALL
  533. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
  534. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  535. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  536. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  537. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
  538. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  539. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  540. * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
  541. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  542. * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
  543. * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
  544. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  545. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  546. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  547. * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
  548. * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
  549. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  550. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  551. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  552. *
  553. * (*) value not defined in all devices.
  554. * @retval None
  555. */
  556. __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
  557. {
  558. SET_BIT(RCC->APB1RSTR, Periphs);
  559. }
  560. /**
  561. * @brief Release APB1 peripherals reset (available in register 1).
  562. * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
  563. * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
  564. * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
  565. * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
  566. * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
  567. * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
  568. * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
  569. * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
  570. * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
  571. * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
  572. * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
  573. * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
  574. * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
  575. * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
  576. * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
  577. * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
  578. * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
  579. * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
  580. * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
  581. * @param Periphs This parameter can be a combination of the following values:
  582. * @arg @ref LL_APB1_GRP1_PERIPH_ALL
  583. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
  584. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  585. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  586. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  587. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
  588. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  589. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  590. * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
  591. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  592. * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
  593. * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
  594. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  595. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  596. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  597. * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
  598. * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
  599. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  600. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  601. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  602. *
  603. * (*) value not defined in all devices.
  604. * @retval None
  605. */
  606. __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
  607. {
  608. CLEAR_BIT(RCC->APB1RSTR, Periphs);
  609. }
  610. /**
  611. * @}
  612. */
  613. /** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
  614. * @{
  615. */
  616. /**
  617. * @brief Enable APB1 peripherals clock (available in register 2).
  618. * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n
  619. * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n
  620. * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n
  621. * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n
  622. * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n
  623. * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n
  624. * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n
  625. * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n
  626. * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n
  627. * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n
  628. * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n
  629. * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock
  630. * @param Periphs This parameter can be a combination of the following values:
  631. * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
  632. * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
  633. * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
  634. * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
  635. * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
  636. * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
  637. * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
  638. * @arg @ref LL_APB1_GRP2_PERIPH_USART1
  639. * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
  640. * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
  641. * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
  642. * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
  643. *
  644. * (*) value not defined in all devices.
  645. * @retval None
  646. */
  647. __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
  648. {
  649. __IO uint32_t tmpreg;
  650. SET_BIT(RCC->APB2ENR, Periphs);
  651. /* Delay after an RCC peripheral clock enabling */
  652. tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
  653. (void)tmpreg;
  654. }
  655. /**
  656. * @brief Check if APB1 peripheral clock is enabled or not (available in register 2).
  657. * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
  658. * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n
  659. * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n
  660. * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n
  661. * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n
  662. * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n
  663. * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n
  664. * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n
  665. * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n
  666. * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n
  667. * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n
  668. * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock
  669. * @param Periphs This parameter can be a combination of the following values:
  670. * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
  671. * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
  672. * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
  673. * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
  674. * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
  675. * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
  676. * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
  677. * @arg @ref LL_APB1_GRP2_PERIPH_USART1
  678. * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
  679. * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
  680. * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
  681. * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
  682. *
  683. * (*) value not defined in all devices.
  684. * @retval State of Periphs (1 or 0).
  685. */
  686. __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
  687. {
  688. return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
  689. }
  690. /**
  691. * @brief Disable APB1 peripherals clock (available in register 2).
  692. * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n
  693. * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n
  694. * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n
  695. * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n
  696. * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n
  697. * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n
  698. * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n
  699. * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n
  700. * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n
  701. * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n
  702. * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n
  703. * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock
  704. * @param Periphs This parameter can be a combination of the following values:
  705. * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
  706. * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
  707. * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
  708. * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
  709. * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
  710. * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
  711. * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
  712. * @arg @ref LL_APB1_GRP2_PERIPH_USART1
  713. * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
  714. * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
  715. * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
  716. * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
  717. *
  718. * (*) value not defined in all devices.
  719. * @retval None
  720. */
  721. __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
  722. {
  723. CLEAR_BIT(RCC->APB2ENR, Periphs);
  724. }
  725. /**
  726. * @brief Force APB1 peripherals reset (available in register 2).
  727. * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n
  728. * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n
  729. * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n
  730. * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n
  731. * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n
  732. * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n
  733. * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n
  734. * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n
  735. * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n
  736. * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n
  737. * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n
  738. * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset
  739. * @param Periphs This parameter can be a combination of the following values:
  740. * @arg @ref LL_APB1_GRP2_PERIPH_ALL
  741. * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
  742. * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
  743. * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
  744. * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
  745. * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
  746. * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
  747. * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
  748. * @arg @ref LL_APB1_GRP2_PERIPH_USART1
  749. * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
  750. * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
  751. * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
  752. * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
  753. *
  754. * (*) value not defined in all devices.
  755. * @retval None
  756. */
  757. __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
  758. {
  759. SET_BIT(RCC->APB2RSTR, Periphs);
  760. }
  761. /**
  762. * @brief Release APB1 peripherals reset (available in register 2).
  763. * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
  764. * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n
  765. * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n
  766. * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n
  767. * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n
  768. * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n
  769. * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n
  770. * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n
  771. * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n
  772. * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n
  773. * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n
  774. * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset
  775. * @param Periphs This parameter can be a combination of the following values:
  776. * @arg @ref LL_APB1_GRP2_PERIPH_ALL
  777. * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
  778. * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
  779. * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
  780. * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
  781. * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
  782. * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
  783. * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
  784. * @arg @ref LL_APB1_GRP2_PERIPH_USART1
  785. * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
  786. * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
  787. * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
  788. * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
  789. *
  790. * (*) value not defined in all devices.
  791. * @retval None
  792. */
  793. __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
  794. {
  795. CLEAR_BIT(RCC->APB2RSTR, Periphs);
  796. }
  797. /**
  798. * @}
  799. */
  800. /**
  801. * @}
  802. */
  803. /**
  804. * @}
  805. */
  806. #endif /* defined(RCC) */
  807. /**
  808. * @}
  809. */
  810. #ifdef __cplusplus
  811. }
  812. #endif
  813. #endif /* __STM32F0xx_LL_BUS_H */
  814. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/