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  1. /**
  2. ******************************************************************************
  3. * @file stm32f0xx_ll_dac.h
  4. * @author MCD Application Team
  5. * @brief Header file of DAC LL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10. *
  11. * Redistribution and use in source and binary forms, with or without modification,
  12. * are permitted provided that the following conditions are met:
  13. * 1. Redistributions of source code must retain the above copyright notice,
  14. * this list of conditions and the following disclaimer.
  15. * 2. Redistributions in binary form must reproduce the above copyright notice,
  16. * this list of conditions and the following disclaimer in the documentation
  17. * and/or other materials provided with the distribution.
  18. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  19. * may be used to endorse or promote products derived from this software
  20. * without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. ******************************************************************************
  34. */
  35. /* Define to prevent recursive inclusion -------------------------------------*/
  36. #ifndef __STM32F0xx_LL_DAC_H
  37. #define __STM32F0xx_LL_DAC_H
  38. #ifdef __cplusplus
  39. extern "C" {
  40. #endif
  41. /* Includes ------------------------------------------------------------------*/
  42. #include "stm32f0xx.h"
  43. /** @addtogroup STM32F0xx_LL_Driver
  44. * @{
  45. */
  46. #if defined (DAC1)
  47. /** @defgroup DAC_LL DAC
  48. * @{
  49. */
  50. /* Private types -------------------------------------------------------------*/
  51. /* Private variables ---------------------------------------------------------*/
  52. /* Private constants ---------------------------------------------------------*/
  53. /** @defgroup DAC_LL_Private_Constants DAC Private Constants
  54. * @{
  55. */
  56. /* Internal masks for DAC channels definition */
  57. /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
  58. /* - channel bits position into register CR */
  59. /* - channel bits position into register SWTRIG */
  60. /* - channel register offset of data holding register DHRx */
  61. /* - channel register offset of data output register DORx */
  62. #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
  63. #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
  64. #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
  65. #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
  66. #if defined(DAC_CHANNEL2_SUPPORT)
  67. #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
  68. #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
  69. #else
  70. #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
  71. #endif /* DAC_CHANNEL2_SUPPORT */
  72. #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
  73. #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
  74. #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
  75. #if defined(DAC_CHANNEL2_SUPPORT)
  76. #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
  77. #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
  78. #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
  79. #endif /* DAC_CHANNEL2_SUPPORT */
  80. #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
  81. #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
  82. #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
  83. #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
  84. #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
  85. #if defined(DAC_CHANNEL2_SUPPORT)
  86. #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
  87. #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
  88. #else
  89. #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
  90. #endif /* DAC_CHANNEL2_SUPPORT */
  91. #define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
  92. #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
  93. #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
  94. #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
  95. #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
  96. /* DAC registers bits positions */
  97. #if defined(DAC_CHANNEL2_SUPPORT)
  98. #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
  99. #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
  100. #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
  101. #endif /* DAC_CHANNEL2_SUPPORT */
  102. /* Miscellaneous data */
  103. #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
  104. /**
  105. * @}
  106. */
  107. /* Private macros ------------------------------------------------------------*/
  108. /** @defgroup DAC_LL_Private_Macros DAC Private Macros
  109. * @{
  110. */
  111. /**
  112. * @brief Driver macro reserved for internal use: set a pointer to
  113. * a register from a register basis from which an offset
  114. * is applied.
  115. * @param __REG__ Register basis from which the offset is applied.
  116. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
  117. * @retval Pointer to register address
  118. */
  119. #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
  120. ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
  121. /**
  122. * @}
  123. */
  124. /* Exported types ------------------------------------------------------------*/
  125. #if defined(USE_FULL_LL_DRIVER)
  126. /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
  127. * @{
  128. */
  129. /**
  130. * @brief Structure definition of some features of DAC instance.
  131. */
  132. typedef struct
  133. {
  134. uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
  135. This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
  136. This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
  137. #if defined(DAC_CR_WAVE1)
  138. uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
  139. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
  140. This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
  141. uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
  142. If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
  143. If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
  144. @note If waveform automatic generation mode is disabled, this parameter is discarded.
  145. This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
  146. #endif
  147. uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
  148. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
  149. This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
  150. } LL_DAC_InitTypeDef;
  151. /**
  152. * @}
  153. */
  154. #endif /* USE_FULL_LL_DRIVER */
  155. /* Exported constants --------------------------------------------------------*/
  156. /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
  157. * @{
  158. */
  159. /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
  160. * @brief Flags defines which can be used with LL_DAC_ReadReg function
  161. * @{
  162. */
  163. /* DAC channel 1 flags */
  164. #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
  165. #if defined(DAC_CHANNEL2_SUPPORT)
  166. /* DAC channel 2 flags */
  167. #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
  168. #endif /* DAC_CHANNEL2_SUPPORT */
  169. /**
  170. * @}
  171. */
  172. /** @defgroup DAC_LL_EC_IT DAC interruptions
  173. * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
  174. * @{
  175. */
  176. #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
  177. #if defined(DAC_CHANNEL2_SUPPORT)
  178. #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
  179. #endif /* DAC_CHANNEL2_SUPPORT */
  180. /**
  181. * @}
  182. */
  183. /** @defgroup DAC_LL_EC_CHANNEL DAC channels
  184. * @{
  185. */
  186. #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
  187. #if defined(DAC_CHANNEL2_SUPPORT)
  188. #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
  189. #endif /* DAC_CHANNEL2_SUPPORT */
  190. /**
  191. * @}
  192. */
  193. /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
  194. * @{
  195. */
  196. #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
  197. #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
  198. #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
  199. #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
  200. #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
  201. #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
  202. #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
  203. #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
  204. /**
  205. * @}
  206. */
  207. /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
  208. * @{
  209. */
  210. #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
  211. #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
  212. #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
  213. /**
  214. * @}
  215. */
  216. /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
  217. * @{
  218. */
  219. #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
  220. #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
  221. #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
  222. #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
  223. #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
  224. #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
  225. #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
  226. #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
  227. #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
  228. #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
  229. #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
  230. #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
  231. /**
  232. * @}
  233. */
  234. /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
  235. * @{
  236. */
  237. #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
  238. #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
  239. #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
  240. #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
  241. #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
  242. #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
  243. #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
  244. #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
  245. #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
  246. #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
  247. #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
  248. #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
  249. /**
  250. * @}
  251. */
  252. /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
  253. * @{
  254. */
  255. #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
  256. #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
  257. /**
  258. * @}
  259. */
  260. /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
  261. * @{
  262. */
  263. #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
  264. #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
  265. /**
  266. * @}
  267. */
  268. /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
  269. * @{
  270. */
  271. /* List of DAC registers intended to be used (most commonly) with */
  272. /* DMA transfer. */
  273. /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
  274. #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
  275. #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
  276. #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
  277. /**
  278. * @}
  279. */
  280. /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
  281. * @note Only DAC IP HW delays are defined in DAC LL driver driver,
  282. * not timeout values.
  283. * For details on delays values, refer to descriptions in source code
  284. * above each literal definition.
  285. * @{
  286. */
  287. /* Delay for DAC channel voltage settling time from DAC channel startup */
  288. /* (transition from disable to enable). */
  289. /* Note: DAC channel startup time depends on board application environment: */
  290. /* impedance connected to DAC channel output. */
  291. /* The delay below is specified under conditions: */
  292. /* - voltage maximum transition (lowest to highest value) */
  293. /* - until voltage reaches final value +-1LSB */
  294. /* - DAC channel output buffer enabled */
  295. /* - load impedance of 5kOhm (min), 50pF (max) */
  296. /* Literal set to maximum value (refer to device datasheet, */
  297. /* parameter "tWAKEUP"). */
  298. /* Unit: us */
  299. #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
  300. /* Delay for DAC channel voltage settling time. */
  301. /* Note: DAC channel startup time depends on board application environment: */
  302. /* impedance connected to DAC channel output. */
  303. /* The delay below is specified under conditions: */
  304. /* - voltage maximum transition (lowest to highest value) */
  305. /* - until voltage reaches final value +-1LSB */
  306. /* - DAC channel output buffer enabled */
  307. /* - load impedance of 5kOhm min, 50pF max */
  308. /* Literal set to maximum value (refer to device datasheet, */
  309. /* parameter "tSETTLING"). */
  310. /* Unit: us */
  311. #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
  312. /**
  313. * @}
  314. */
  315. /**
  316. * @}
  317. */
  318. /* Exported macro ------------------------------------------------------------*/
  319. /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
  320. * @{
  321. */
  322. /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
  323. * @{
  324. */
  325. /**
  326. * @brief Write a value in DAC register
  327. * @param __INSTANCE__ DAC Instance
  328. * @param __REG__ Register to be written
  329. * @param __VALUE__ Value to be written in the register
  330. * @retval None
  331. */
  332. #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  333. /**
  334. * @brief Read a value in DAC register
  335. * @param __INSTANCE__ DAC Instance
  336. * @param __REG__ Register to be read
  337. * @retval Register value
  338. */
  339. #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  340. /**
  341. * @}
  342. */
  343. /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
  344. * @{
  345. */
  346. /**
  347. * @brief Helper macro to get DAC channel number in decimal format
  348. * from literals LL_DAC_CHANNEL_x.
  349. * Example:
  350. * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
  351. * will return decimal number "1".
  352. * @note The input can be a value from functions where a channel
  353. * number is returned.
  354. * @param __CHANNEL__ This parameter can be one of the following values:
  355. * @arg @ref LL_DAC_CHANNEL_1
  356. * @arg @ref LL_DAC_CHANNEL_2 (1)
  357. *
  358. * (1) On this STM32 serie, parameter not available on all devices.
  359. * Refer to device datasheet for channels availability.
  360. * @retval 1...2 (value "2" depending on DAC channel 2 availability)
  361. */
  362. #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
  363. ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
  364. /**
  365. * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
  366. * from number in decimal format.
  367. * Example:
  368. * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
  369. * will return a data equivalent to "LL_DAC_CHANNEL_1".
  370. * @note If the input parameter does not correspond to a DAC channel,
  371. * this macro returns value '0'.
  372. * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
  373. * @retval Returned value can be one of the following values:
  374. * @arg @ref LL_DAC_CHANNEL_1
  375. * @arg @ref LL_DAC_CHANNEL_2 (1)
  376. *
  377. * (1) On this STM32 serie, parameter not available on all devices.
  378. * Refer to device datasheet for channels availability.
  379. */
  380. #if defined(DAC_CHANNEL2_SUPPORT)
  381. #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
  382. (((__DECIMAL_NB__) == 1U) \
  383. ? ( \
  384. LL_DAC_CHANNEL_1 \
  385. ) \
  386. : \
  387. (((__DECIMAL_NB__) == 2U) \
  388. ? ( \
  389. LL_DAC_CHANNEL_2 \
  390. ) \
  391. : \
  392. ( \
  393. 0 \
  394. ) \
  395. ) \
  396. )
  397. #else
  398. #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
  399. (((__DECIMAL_NB__) == 1U) \
  400. ? ( \
  401. LL_DAC_CHANNEL_1 \
  402. ) \
  403. : \
  404. ( \
  405. 0 \
  406. ) \
  407. )
  408. #endif /* DAC_CHANNEL2_SUPPORT */
  409. /**
  410. * @brief Helper macro to define the DAC conversion data full-scale digital
  411. * value corresponding to the selected DAC resolution.
  412. * @note DAC conversion data full-scale corresponds to voltage range
  413. * determined by analog voltage references Vref+ and Vref-
  414. * (refer to reference manual).
  415. * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
  416. * @arg @ref LL_DAC_RESOLUTION_12B
  417. * @arg @ref LL_DAC_RESOLUTION_8B
  418. * @retval ADC conversion data equivalent voltage value (unit: mVolt)
  419. */
  420. #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
  421. ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
  422. /**
  423. * @brief Helper macro to calculate the DAC conversion data (unit: digital
  424. * value) corresponding to a voltage (unit: mVolt).
  425. * @note This helper macro is intended to provide input data in voltage
  426. * rather than digital value,
  427. * to be used with LL DAC functions such as
  428. * @ref LL_DAC_ConvertData12RightAligned().
  429. * @note Analog reference voltage (Vref+) must be either known from
  430. * user board environment or can be calculated using ADC measurement
  431. * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
  432. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
  433. * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
  434. * (unit: mVolt).
  435. * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
  436. * @arg @ref LL_DAC_RESOLUTION_12B
  437. * @arg @ref LL_DAC_RESOLUTION_8B
  438. * @retval DAC conversion data (unit: digital value)
  439. */
  440. #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
  441. __DAC_VOLTAGE__,\
  442. __DAC_RESOLUTION__) \
  443. ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
  444. / (__VREFANALOG_VOLTAGE__) \
  445. )
  446. /**
  447. * @}
  448. */
  449. /**
  450. * @}
  451. */
  452. /* Exported functions --------------------------------------------------------*/
  453. /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
  454. * @{
  455. */
  456. /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
  457. * @{
  458. */
  459. /**
  460. * @brief Set the conversion trigger source for the selected DAC channel.
  461. * @note For conversion trigger source to be effective, DAC trigger
  462. * must be enabled using function @ref LL_DAC_EnableTrigger().
  463. * @note To set conversion trigger source, DAC channel must be disabled.
  464. * Otherwise, the setting is discarded.
  465. * @note Availability of parameters of trigger sources from timer
  466. * depends on timers availability on the selected device.
  467. * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
  468. * CR TSEL2 LL_DAC_SetTriggerSource
  469. * @param DACx DAC instance
  470. * @param DAC_Channel This parameter can be one of the following values:
  471. * @arg @ref LL_DAC_CHANNEL_1
  472. * @arg @ref LL_DAC_CHANNEL_2 (1)
  473. *
  474. * (1) On this STM32 serie, parameter not available on all devices.
  475. * Refer to device datasheet for channels availability.
  476. * @param TriggerSource This parameter can be one of the following values:
  477. * @arg @ref LL_DAC_TRIG_SOFTWARE
  478. * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
  479. * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
  480. * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
  481. * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
  482. * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
  483. * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
  484. * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
  485. * @retval None
  486. */
  487. __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
  488. {
  489. MODIFY_REG(DACx->CR,
  490. DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  491. TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  492. }
  493. /**
  494. * @brief Get the conversion trigger source for the selected DAC channel.
  495. * @note For conversion trigger source to be effective, DAC trigger
  496. * must be enabled using function @ref LL_DAC_EnableTrigger().
  497. * @note Availability of parameters of trigger sources from timer
  498. * depends on timers availability on the selected device.
  499. * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
  500. * CR TSEL2 LL_DAC_GetTriggerSource
  501. * @param DACx DAC instance
  502. * @param DAC_Channel This parameter can be one of the following values:
  503. * @arg @ref LL_DAC_CHANNEL_1
  504. * @arg @ref LL_DAC_CHANNEL_2 (1)
  505. *
  506. * (1) On this STM32 serie, parameter not available on all devices.
  507. * Refer to device datasheet for channels availability.
  508. * @retval Returned value can be one of the following values:
  509. * @arg @ref LL_DAC_TRIG_SOFTWARE
  510. * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
  511. * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
  512. * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
  513. * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
  514. * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
  515. * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
  516. * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
  517. */
  518. __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  519. {
  520. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  521. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  522. );
  523. }
  524. #if defined(DAC_CR_WAVE1)
  525. /**
  526. * @brief Set the waveform automatic generation mode
  527. * for the selected DAC channel.
  528. * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
  529. * CR WAVE2 LL_DAC_SetWaveAutoGeneration
  530. * @param DACx DAC instance
  531. * @param DAC_Channel This parameter can be one of the following values:
  532. * @arg @ref LL_DAC_CHANNEL_1
  533. * @arg @ref LL_DAC_CHANNEL_2 (1)
  534. *
  535. * (1) On this STM32 serie, parameter not available on all devices.
  536. * Refer to device datasheet for channels availability.
  537. * @param WaveAutoGeneration This parameter can be one of the following values:
  538. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
  539. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
  540. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
  541. * @retval None
  542. */
  543. __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
  544. {
  545. MODIFY_REG(DACx->CR,
  546. DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  547. WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  548. }
  549. /**
  550. * @brief Get the waveform automatic generation mode
  551. * for the selected DAC channel.
  552. * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
  553. * CR WAVE2 LL_DAC_GetWaveAutoGeneration
  554. * @param DACx DAC instance
  555. * @param DAC_Channel This parameter can be one of the following values:
  556. * @arg @ref LL_DAC_CHANNEL_1
  557. * @arg @ref LL_DAC_CHANNEL_2 (1)
  558. *
  559. * (1) On this STM32 serie, parameter not available on all devices.
  560. * Refer to device datasheet for channels availability.
  561. * @retval Returned value can be one of the following values:
  562. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
  563. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
  564. * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
  565. */
  566. __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  567. {
  568. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  569. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  570. );
  571. }
  572. /**
  573. * @brief Set the noise waveform generation for the selected DAC channel:
  574. * Noise mode and parameters LFSR (linear feedback shift register).
  575. * @note For wave generation to be effective, DAC channel
  576. * wave generation mode must be enabled using
  577. * function @ref LL_DAC_SetWaveAutoGeneration().
  578. * @note This setting can be set when the selected DAC channel is disabled
  579. * (otherwise, the setting operation is ignored).
  580. * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
  581. * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
  582. * @param DACx DAC instance
  583. * @param DAC_Channel This parameter can be one of the following values:
  584. * @arg @ref LL_DAC_CHANNEL_1
  585. * @arg @ref LL_DAC_CHANNEL_2 (1)
  586. *
  587. * (1) On this STM32 serie, parameter not available on all devices.
  588. * Refer to device datasheet for channels availability.
  589. * @param NoiseLFSRMask This parameter can be one of the following values:
  590. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
  591. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  592. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  593. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  594. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  595. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  596. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  597. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  598. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  599. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  600. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  601. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
  602. * @retval None
  603. */
  604. __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
  605. {
  606. MODIFY_REG(DACx->CR,
  607. DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  608. NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  609. }
  610. /**
  611. * @brief Set the noise waveform generation for the selected DAC channel:
  612. * Noise mode and parameters LFSR (linear feedback shift register).
  613. * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
  614. * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
  615. * @param DACx DAC instance
  616. * @param DAC_Channel This parameter can be one of the following values:
  617. * @arg @ref LL_DAC_CHANNEL_1
  618. * @arg @ref LL_DAC_CHANNEL_2 (1)
  619. *
  620. * (1) On this STM32 serie, parameter not available on all devices.
  621. * Refer to device datasheet for channels availability.
  622. * @retval Returned value can be one of the following values:
  623. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
  624. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  625. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  626. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  627. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  628. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  629. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  630. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  631. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  632. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  633. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  634. * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
  635. */
  636. __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  637. {
  638. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  639. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  640. );
  641. }
  642. /**
  643. * @brief Set the triangle waveform generation for the selected DAC channel:
  644. * triangle mode and amplitude.
  645. * @note For wave generation to be effective, DAC channel
  646. * wave generation mode must be enabled using
  647. * function @ref LL_DAC_SetWaveAutoGeneration().
  648. * @note This setting can be set when the selected DAC channel is disabled
  649. * (otherwise, the setting operation is ignored).
  650. * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
  651. * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
  652. * @param DACx DAC instance
  653. * @param DAC_Channel This parameter can be one of the following values:
  654. * @arg @ref LL_DAC_CHANNEL_1
  655. * @arg @ref LL_DAC_CHANNEL_2 (1)
  656. *
  657. * (1) On this STM32 serie, parameter not available on all devices.
  658. * Refer to device datasheet for channels availability.
  659. * @param TriangleAmplitude This parameter can be one of the following values:
  660. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
  661. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
  662. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
  663. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
  664. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
  665. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
  666. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
  667. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
  668. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
  669. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
  670. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
  671. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
  672. * @retval None
  673. */
  674. __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
  675. {
  676. MODIFY_REG(DACx->CR,
  677. DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  678. TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  679. }
  680. /**
  681. * @brief Set the triangle waveform generation for the selected DAC channel:
  682. * triangle mode and amplitude.
  683. * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
  684. * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
  685. * @param DACx DAC instance
  686. * @param DAC_Channel This parameter can be one of the following values:
  687. * @arg @ref LL_DAC_CHANNEL_1
  688. * @arg @ref LL_DAC_CHANNEL_2 (1)
  689. *
  690. * (1) On this STM32 serie, parameter not available on all devices.
  691. * Refer to device datasheet for channels availability.
  692. * @retval Returned value can be one of the following values:
  693. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
  694. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
  695. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
  696. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
  697. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
  698. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
  699. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
  700. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
  701. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
  702. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
  703. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
  704. * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
  705. */
  706. __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  707. {
  708. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  709. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  710. );
  711. }
  712. #endif
  713. /**
  714. * @brief Set the output buffer for the selected DAC channel.
  715. * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
  716. * CR BOFF2 LL_DAC_SetOutputBuffer
  717. * @param DACx DAC instance
  718. * @param DAC_Channel This parameter can be one of the following values:
  719. * @arg @ref LL_DAC_CHANNEL_1
  720. * @arg @ref LL_DAC_CHANNEL_2 (1)
  721. *
  722. * (1) On this STM32 serie, parameter not available on all devices.
  723. * Refer to device datasheet for channels availability.
  724. * @param OutputBuffer This parameter can be one of the following values:
  725. * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
  726. * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
  727. * @retval None
  728. */
  729. __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
  730. {
  731. MODIFY_REG(DACx->CR,
  732. DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
  733. OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  734. }
  735. /**
  736. * @brief Get the output buffer state for the selected DAC channel.
  737. * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
  738. * CR BOFF2 LL_DAC_GetOutputBuffer
  739. * @param DACx DAC instance
  740. * @param DAC_Channel This parameter can be one of the following values:
  741. * @arg @ref LL_DAC_CHANNEL_1
  742. * @arg @ref LL_DAC_CHANNEL_2 (1)
  743. *
  744. * (1) On this STM32 serie, parameter not available on all devices.
  745. * Refer to device datasheet for channels availability.
  746. * @retval Returned value can be one of the following values:
  747. * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
  748. * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
  749. */
  750. __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  751. {
  752. return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  753. >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
  754. );
  755. }
  756. /**
  757. * @}
  758. */
  759. /** @defgroup DAC_LL_EF_DMA_Management DMA Management
  760. * @{
  761. */
  762. /**
  763. * @brief Enable DAC DMA transfer request of the selected channel.
  764. * @note To configure DMA source address (peripheral address),
  765. * use function @ref LL_DAC_DMA_GetRegAddr().
  766. * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
  767. * CR DMAEN2 LL_DAC_EnableDMAReq
  768. * @param DACx DAC instance
  769. * @param DAC_Channel This parameter can be one of the following values:
  770. * @arg @ref LL_DAC_CHANNEL_1
  771. * @arg @ref LL_DAC_CHANNEL_2 (1)
  772. *
  773. * (1) On this STM32 serie, parameter not available on all devices.
  774. * Refer to device datasheet for channels availability.
  775. * @retval None
  776. */
  777. __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  778. {
  779. SET_BIT(DACx->CR,
  780. DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  781. }
  782. /**
  783. * @brief Disable DAC DMA transfer request of the selected channel.
  784. * @note To configure DMA source address (peripheral address),
  785. * use function @ref LL_DAC_DMA_GetRegAddr().
  786. * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
  787. * CR DMAEN2 LL_DAC_DisableDMAReq
  788. * @param DACx DAC instance
  789. * @param DAC_Channel This parameter can be one of the following values:
  790. * @arg @ref LL_DAC_CHANNEL_1
  791. * @arg @ref LL_DAC_CHANNEL_2 (1)
  792. *
  793. * (1) On this STM32 serie, parameter not available on all devices.
  794. * Refer to device datasheet for channels availability.
  795. * @retval None
  796. */
  797. __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  798. {
  799. CLEAR_BIT(DACx->CR,
  800. DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  801. }
  802. /**
  803. * @brief Get DAC DMA transfer request state of the selected channel.
  804. * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
  805. * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
  806. * CR DMAEN2 LL_DAC_IsDMAReqEnabled
  807. * @param DACx DAC instance
  808. * @param DAC_Channel This parameter can be one of the following values:
  809. * @arg @ref LL_DAC_CHANNEL_1
  810. * @arg @ref LL_DAC_CHANNEL_2 (1)
  811. *
  812. * (1) On this STM32 serie, parameter not available on all devices.
  813. * Refer to device datasheet for channels availability.
  814. * @retval State of bit (1 or 0).
  815. */
  816. __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  817. {
  818. return (READ_BIT(DACx->CR,
  819. DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  820. == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
  821. }
  822. /**
  823. * @brief Function to help to configure DMA transfer to DAC: retrieve the
  824. * DAC register address from DAC instance and a list of DAC registers
  825. * intended to be used (most commonly) with DMA transfer.
  826. * @note These DAC registers are data holding registers:
  827. * when DAC conversion is requested, DAC generates a DMA transfer
  828. * request to have data available in DAC data holding registers.
  829. * @note This macro is intended to be used with LL DMA driver, refer to
  830. * function "LL_DMA_ConfigAddresses()".
  831. * Example:
  832. * LL_DMA_ConfigAddresses(DMA1,
  833. * LL_DMA_CHANNEL_1,
  834. * (uint32_t)&< array or variable >,
  835. * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
  836. * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
  837. * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
  838. * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
  839. * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
  840. * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
  841. * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
  842. * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
  843. * @param DACx DAC instance
  844. * @param DAC_Channel This parameter can be one of the following values:
  845. * @arg @ref LL_DAC_CHANNEL_1
  846. * @arg @ref LL_DAC_CHANNEL_2 (1)
  847. *
  848. * (1) On this STM32 serie, parameter not available on all devices.
  849. * Refer to device datasheet for channels availability.
  850. * @param Register This parameter can be one of the following values:
  851. * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
  852. * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
  853. * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
  854. * @retval DAC register address
  855. */
  856. __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
  857. {
  858. /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
  859. /* DAC channel selected. */
  860. return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
  861. }
  862. /**
  863. * @}
  864. */
  865. /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
  866. * @{
  867. */
  868. /**
  869. * @brief Enable DAC selected channel.
  870. * @rmtoll CR EN1 LL_DAC_Enable\n
  871. * CR EN2 LL_DAC_Enable
  872. * @note After enable from off state, DAC channel requires a delay
  873. * for output voltage to reach accuracy +/- 1 LSB.
  874. * Refer to device datasheet, parameter "tWAKEUP".
  875. * @param DACx DAC instance
  876. * @param DAC_Channel This parameter can be one of the following values:
  877. * @arg @ref LL_DAC_CHANNEL_1
  878. * @arg @ref LL_DAC_CHANNEL_2 (1)
  879. *
  880. * (1) On this STM32 serie, parameter not available on all devices.
  881. * Refer to device datasheet for channels availability.
  882. * @retval None
  883. */
  884. __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  885. {
  886. SET_BIT(DACx->CR,
  887. DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  888. }
  889. /**
  890. * @brief Disable DAC selected channel.
  891. * @rmtoll CR EN1 LL_DAC_Disable\n
  892. * CR EN2 LL_DAC_Disable
  893. * @param DACx DAC instance
  894. * @param DAC_Channel This parameter can be one of the following values:
  895. * @arg @ref LL_DAC_CHANNEL_1
  896. * @arg @ref LL_DAC_CHANNEL_2 (1)
  897. *
  898. * (1) On this STM32 serie, parameter not available on all devices.
  899. * Refer to device datasheet for channels availability.
  900. * @retval None
  901. */
  902. __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  903. {
  904. CLEAR_BIT(DACx->CR,
  905. DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  906. }
  907. /**
  908. * @brief Get DAC enable state of the selected channel.
  909. * (0: DAC channel is disabled, 1: DAC channel is enabled)
  910. * @rmtoll CR EN1 LL_DAC_IsEnabled\n
  911. * CR EN2 LL_DAC_IsEnabled
  912. * @param DACx DAC instance
  913. * @param DAC_Channel This parameter can be one of the following values:
  914. * @arg @ref LL_DAC_CHANNEL_1
  915. * @arg @ref LL_DAC_CHANNEL_2 (1)
  916. *
  917. * (1) On this STM32 serie, parameter not available on all devices.
  918. * Refer to device datasheet for channels availability.
  919. * @retval State of bit (1 or 0).
  920. */
  921. __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  922. {
  923. return (READ_BIT(DACx->CR,
  924. DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  925. == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
  926. }
  927. /**
  928. * @brief Enable DAC trigger of the selected channel.
  929. * @note - If DAC trigger is disabled, DAC conversion is performed
  930. * automatically once the data holding register is updated,
  931. * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
  932. * @ref LL_DAC_ConvertData12RightAligned(), ...
  933. * - If DAC trigger is enabled, DAC conversion is performed
  934. * only when a hardware of software trigger event is occurring.
  935. * Select trigger source using
  936. * function @ref LL_DAC_SetTriggerSource().
  937. * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
  938. * CR TEN2 LL_DAC_EnableTrigger
  939. * @param DACx DAC instance
  940. * @param DAC_Channel This parameter can be one of the following values:
  941. * @arg @ref LL_DAC_CHANNEL_1
  942. * @arg @ref LL_DAC_CHANNEL_2 (1)
  943. *
  944. * (1) On this STM32 serie, parameter not available on all devices.
  945. * Refer to device datasheet for channels availability.
  946. * @retval None
  947. */
  948. __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  949. {
  950. SET_BIT(DACx->CR,
  951. DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  952. }
  953. /**
  954. * @brief Disable DAC trigger of the selected channel.
  955. * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
  956. * CR TEN2 LL_DAC_DisableTrigger
  957. * @param DACx DAC instance
  958. * @param DAC_Channel This parameter can be one of the following values:
  959. * @arg @ref LL_DAC_CHANNEL_1
  960. * @arg @ref LL_DAC_CHANNEL_2 (1)
  961. *
  962. * (1) On this STM32 serie, parameter not available on all devices.
  963. * Refer to device datasheet for channels availability.
  964. * @retval None
  965. */
  966. __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  967. {
  968. CLEAR_BIT(DACx->CR,
  969. DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
  970. }
  971. /**
  972. * @brief Get DAC trigger state of the selected channel.
  973. * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
  974. * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
  975. * CR TEN2 LL_DAC_IsTriggerEnabled
  976. * @param DACx DAC instance
  977. * @param DAC_Channel This parameter can be one of the following values:
  978. * @arg @ref LL_DAC_CHANNEL_1
  979. * @arg @ref LL_DAC_CHANNEL_2 (1)
  980. *
  981. * (1) On this STM32 serie, parameter not available on all devices.
  982. * Refer to device datasheet for channels availability.
  983. * @retval State of bit (1 or 0).
  984. */
  985. __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  986. {
  987. return (READ_BIT(DACx->CR,
  988. DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
  989. == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
  990. }
  991. /**
  992. * @brief Trig DAC conversion by software for the selected DAC channel.
  993. * @note Preliminarily, DAC trigger must be set to software trigger
  994. * using function @ref LL_DAC_SetTriggerSource()
  995. * with parameter "LL_DAC_TRIGGER_SOFTWARE".
  996. * and DAC trigger must be enabled using
  997. * function @ref LL_DAC_EnableTrigger().
  998. * @note For devices featuring DAC with 2 channels: this function
  999. * can perform a SW start of both DAC channels simultaneously.
  1000. * Two channels can be selected as parameter.
  1001. * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
  1002. * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
  1003. * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
  1004. * @param DACx DAC instance
  1005. * @param DAC_Channel This parameter can a combination of the following values:
  1006. * @arg @ref LL_DAC_CHANNEL_1
  1007. * @arg @ref LL_DAC_CHANNEL_2 (1)
  1008. *
  1009. * (1) On this STM32 serie, parameter not available on all devices.
  1010. * Refer to device datasheet for channels availability.
  1011. * @retval None
  1012. */
  1013. __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  1014. {
  1015. SET_BIT(DACx->SWTRIGR,
  1016. (DAC_Channel & DAC_SWTR_CHX_MASK));
  1017. }
  1018. /**
  1019. * @brief Set the data to be loaded in the data holding register
  1020. * in format 12 bits left alignment (LSB aligned on bit 0),
  1021. * for the selected DAC channel.
  1022. * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
  1023. * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
  1024. * @param DACx DAC instance
  1025. * @param DAC_Channel This parameter can be one of the following values:
  1026. * @arg @ref LL_DAC_CHANNEL_1
  1027. * @arg @ref LL_DAC_CHANNEL_2 (1)
  1028. *
  1029. * (1) On this STM32 serie, parameter not available on all devices.
  1030. * Refer to device datasheet for channels availability.
  1031. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
  1032. * @retval None
  1033. */
  1034. __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
  1035. {
  1036. register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
  1037. MODIFY_REG(*preg,
  1038. DAC_DHR12R1_DACC1DHR,
  1039. Data);
  1040. }
  1041. /**
  1042. * @brief Set the data to be loaded in the data holding register
  1043. * in format 12 bits left alignment (MSB aligned on bit 15),
  1044. * for the selected DAC channel.
  1045. * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
  1046. * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
  1047. * @param DACx DAC instance
  1048. * @param DAC_Channel This parameter can be one of the following values:
  1049. * @arg @ref LL_DAC_CHANNEL_1
  1050. * @arg @ref LL_DAC_CHANNEL_2 (1)
  1051. *
  1052. * (1) On this STM32 serie, parameter not available on all devices.
  1053. * Refer to device datasheet for channels availability.
  1054. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
  1055. * @retval None
  1056. */
  1057. __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
  1058. {
  1059. register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
  1060. MODIFY_REG(*preg,
  1061. DAC_DHR12L1_DACC1DHR,
  1062. Data);
  1063. }
  1064. /**
  1065. * @brief Set the data to be loaded in the data holding register
  1066. * in format 8 bits left alignment (LSB aligned on bit 0),
  1067. * for the selected DAC channel.
  1068. * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
  1069. * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
  1070. * @param DACx DAC instance
  1071. * @param DAC_Channel This parameter can be one of the following values:
  1072. * @arg @ref LL_DAC_CHANNEL_1
  1073. * @arg @ref LL_DAC_CHANNEL_2 (1)
  1074. *
  1075. * (1) On this STM32 serie, parameter not available on all devices.
  1076. * Refer to device datasheet for channels availability.
  1077. * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
  1078. * @retval None
  1079. */
  1080. __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
  1081. {
  1082. register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
  1083. MODIFY_REG(*preg,
  1084. DAC_DHR8R1_DACC1DHR,
  1085. Data);
  1086. }
  1087. #if defined(DAC_CHANNEL2_SUPPORT)
  1088. /**
  1089. * @brief Set the data to be loaded in the data holding register
  1090. * in format 12 bits left alignment (LSB aligned on bit 0),
  1091. * for both DAC channels.
  1092. * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
  1093. * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
  1094. * @param DACx DAC instance
  1095. * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
  1096. * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
  1097. * @retval None
  1098. */
  1099. __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
  1100. {
  1101. MODIFY_REG(DACx->DHR12RD,
  1102. (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
  1103. ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
  1104. }
  1105. /**
  1106. * @brief Set the data to be loaded in the data holding register
  1107. * in format 12 bits left alignment (MSB aligned on bit 15),
  1108. * for both DAC channels.
  1109. * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
  1110. * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
  1111. * @param DACx DAC instance
  1112. * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
  1113. * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
  1114. * @retval None
  1115. */
  1116. __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
  1117. {
  1118. /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
  1119. /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
  1120. /* the 4 LSB must be taken into account for the shift value. */
  1121. MODIFY_REG(DACx->DHR12LD,
  1122. (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
  1123. ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
  1124. }
  1125. /**
  1126. * @brief Set the data to be loaded in the data holding register
  1127. * in format 8 bits left alignment (LSB aligned on bit 0),
  1128. * for both DAC channels.
  1129. * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
  1130. * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
  1131. * @param DACx DAC instance
  1132. * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
  1133. * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
  1134. * @retval None
  1135. */
  1136. __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
  1137. {
  1138. MODIFY_REG(DACx->DHR8RD,
  1139. (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
  1140. ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
  1141. }
  1142. #endif /* DAC_CHANNEL2_SUPPORT */
  1143. /**
  1144. * @brief Retrieve output data currently generated for the selected DAC channel.
  1145. * @note Whatever alignment and resolution settings
  1146. * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
  1147. * @ref LL_DAC_ConvertData12RightAligned(), ...),
  1148. * output data format is 12 bits right aligned (LSB aligned on bit 0).
  1149. * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
  1150. * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
  1151. * @param DACx DAC instance
  1152. * @param DAC_Channel This parameter can be one of the following values:
  1153. * @arg @ref LL_DAC_CHANNEL_1
  1154. * @arg @ref LL_DAC_CHANNEL_2 (1)
  1155. *
  1156. * (1) On this STM32 serie, parameter not available on all devices.
  1157. * Refer to device datasheet for channels availability.
  1158. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  1159. */
  1160. __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
  1161. {
  1162. register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
  1163. return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
  1164. }
  1165. /**
  1166. * @}
  1167. */
  1168. /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
  1169. * @{
  1170. */
  1171. /**
  1172. * @brief Get DAC underrun flag for DAC channel 1
  1173. * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
  1174. * @param DACx DAC instance
  1175. * @retval State of bit (1 or 0).
  1176. */
  1177. __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
  1178. {
  1179. return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
  1180. }
  1181. #if defined(DAC_CHANNEL2_SUPPORT)
  1182. /**
  1183. * @brief Get DAC underrun flag for DAC channel 2
  1184. * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
  1185. * @param DACx DAC instance
  1186. * @retval State of bit (1 or 0).
  1187. */
  1188. __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
  1189. {
  1190. return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
  1191. }
  1192. #endif /* DAC_CHANNEL2_SUPPORT */
  1193. /**
  1194. * @brief Clear DAC underrun flag for DAC channel 1
  1195. * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
  1196. * @param DACx DAC instance
  1197. * @retval None
  1198. */
  1199. __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
  1200. {
  1201. WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
  1202. }
  1203. #if defined(DAC_CHANNEL2_SUPPORT)
  1204. /**
  1205. * @brief Clear DAC underrun flag for DAC channel 2
  1206. * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
  1207. * @param DACx DAC instance
  1208. * @retval None
  1209. */
  1210. __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
  1211. {
  1212. WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
  1213. }
  1214. #endif /* DAC_CHANNEL2_SUPPORT */
  1215. /**
  1216. * @}
  1217. */
  1218. /** @defgroup DAC_LL_EF_IT_Management IT management
  1219. * @{
  1220. */
  1221. /**
  1222. * @brief Enable DMA underrun interrupt for DAC channel 1
  1223. * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
  1224. * @param DACx DAC instance
  1225. * @retval None
  1226. */
  1227. __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
  1228. {
  1229. SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
  1230. }
  1231. #if defined(DAC_CHANNEL2_SUPPORT)
  1232. /**
  1233. * @brief Enable DMA underrun interrupt for DAC channel 2
  1234. * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
  1235. * @param DACx DAC instance
  1236. * @retval None
  1237. */
  1238. __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
  1239. {
  1240. SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
  1241. }
  1242. #endif /* DAC_CHANNEL2_SUPPORT */
  1243. /**
  1244. * @brief Disable DMA underrun interrupt for DAC channel 1
  1245. * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
  1246. * @param DACx DAC instance
  1247. * @retval None
  1248. */
  1249. __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
  1250. {
  1251. CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
  1252. }
  1253. #if defined(DAC_CHANNEL2_SUPPORT)
  1254. /**
  1255. * @brief Disable DMA underrun interrupt for DAC channel 2
  1256. * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
  1257. * @param DACx DAC instance
  1258. * @retval None
  1259. */
  1260. __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
  1261. {
  1262. CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
  1263. }
  1264. #endif /* DAC_CHANNEL2_SUPPORT */
  1265. /**
  1266. * @brief Get DMA underrun interrupt for DAC channel 1
  1267. * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
  1268. * @param DACx DAC instance
  1269. * @retval State of bit (1 or 0).
  1270. */
  1271. __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
  1272. {
  1273. return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
  1274. }
  1275. #if defined(DAC_CHANNEL2_SUPPORT)
  1276. /**
  1277. * @brief Get DMA underrun interrupt for DAC channel 2
  1278. * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
  1279. * @param DACx DAC instance
  1280. * @retval State of bit (1 or 0).
  1281. */
  1282. __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
  1283. {
  1284. return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
  1285. }
  1286. #endif /* DAC_CHANNEL2_SUPPORT */
  1287. /**
  1288. * @}
  1289. */
  1290. #if defined(USE_FULL_LL_DRIVER)
  1291. /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
  1292. * @{
  1293. */
  1294. ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
  1295. ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
  1296. void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
  1297. /**
  1298. * @}
  1299. */
  1300. #endif /* USE_FULL_LL_DRIVER */
  1301. /**
  1302. * @}
  1303. */
  1304. /**
  1305. * @}
  1306. */
  1307. #endif /* DAC1 */
  1308. /**
  1309. * @}
  1310. */
  1311. #ifdef __cplusplus
  1312. }
  1313. #endif
  1314. #endif /* __STM32F0xx_LL_DAC_H */
  1315. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/