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  1. /**
  2. ******************************************************************************
  3. * @file stm32f7xx_hal_dfsdm.h
  4. * @author MCD Application Team
  5. * @version V1.2.2
  6. * @date 14-April-2017
  7. * @brief Header file of DFSDM HAL module.
  8. ******************************************************************************
  9. * @attention
  10. *
  11. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12. *
  13. * Redistribution and use in source and binary forms, with or without modification,
  14. * are permitted provided that the following conditions are met:
  15. * 1. Redistributions of source code must retain the above copyright notice,
  16. * this list of conditions and the following disclaimer.
  17. * 2. Redistributions in binary form must reproduce the above copyright notice,
  18. * this list of conditions and the following disclaimer in the documentation
  19. * and/or other materials provided with the distribution.
  20. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  21. * may be used to endorse or promote products derived from this software
  22. * without specific prior written permission.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. ******************************************************************************
  36. */
  37. /* Define to prevent recursive inclusion -------------------------------------*/
  38. #ifndef __STM32F7xx_HAL_DFSDM_H
  39. #define __STM32F7xx_HAL_DFSDM_H
  40. #ifdef __cplusplus
  41. extern "C" {
  42. #endif
  43. #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
  44. /* Includes ------------------------------------------------------------------*/
  45. #include "stm32f7xx_hal_def.h"
  46. /** @addtogroup STM32F7xx_HAL_Driver
  47. * @{
  48. */
  49. /** @addtogroup DFSDM
  50. * @{
  51. */
  52. /* Exported types ------------------------------------------------------------*/
  53. /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
  54. * @{
  55. */
  56. /**
  57. * @brief HAL DFSDM Channel states definition
  58. */
  59. typedef enum
  60. {
  61. HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
  62. HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
  63. HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
  64. }HAL_DFSDM_Channel_StateTypeDef;
  65. /**
  66. * @brief DFSDM channel output clock structure definition
  67. */
  68. typedef struct
  69. {
  70. FunctionalState Activation; /*!< Output clock enable/disable */
  71. uint32_t Selection; /*!< Output clock is system clock or audio clock.
  72. This parameter can be a value of @ref DFSDM_Channel_OuputClock */
  73. uint32_t Divider; /*!< Output clock divider.
  74. This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
  75. }DFSDM_Channel_OutputClockTypeDef;
  76. /**
  77. * @brief DFSDM channel input structure definition
  78. */
  79. typedef struct
  80. {
  81. uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
  82. This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
  83. uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
  84. This parameter can be a value of @ref DFSDM_Channel_DataPacking */
  85. uint32_t Pins; /*!< Input pins are taken from same or following channel.
  86. This parameter can be a value of @ref DFSDM_Channel_InputPins */
  87. }DFSDM_Channel_InputTypeDef;
  88. /**
  89. * @brief DFSDM channel serial interface structure definition
  90. */
  91. typedef struct
  92. {
  93. uint32_t Type; /*!< SPI or Manchester modes.
  94. This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
  95. uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
  96. This parameter can be a value of @ref DFSDM_Channel_SpiClock */
  97. }DFSDM_Channel_SerialInterfaceTypeDef;
  98. /**
  99. * @brief DFSDM channel analog watchdog structure definition
  100. */
  101. typedef struct
  102. {
  103. uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
  104. This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
  105. uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
  106. This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
  107. }DFSDM_Channel_AwdTypeDef;
  108. /**
  109. * @brief DFSDM channel init structure definition
  110. */
  111. typedef struct
  112. {
  113. DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
  114. DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
  115. DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
  116. DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
  117. int32_t Offset; /*!< DFSDM channel offset.
  118. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
  119. uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
  120. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
  121. }DFSDM_Channel_InitTypeDef;
  122. /**
  123. * @brief DFSDM channel handle structure definition
  124. */
  125. typedef struct
  126. {
  127. DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
  128. DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
  129. HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
  130. }DFSDM_Channel_HandleTypeDef;
  131. /**
  132. * @brief HAL DFSDM Filter states definition
  133. */
  134. typedef enum
  135. {
  136. HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
  137. HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */
  138. HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */
  139. HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
  140. HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
  141. HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
  142. }HAL_DFSDM_Filter_StateTypeDef;
  143. /**
  144. * @brief DFSDM filter regular conversion parameters structure definition
  145. */
  146. typedef struct
  147. {
  148. uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
  149. This parameter can be a value of @ref DFSDM_Filter_Trigger */
  150. FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
  151. FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
  152. }DFSDM_Filter_RegularParamTypeDef;
  153. /**
  154. * @brief DFSDM filter injected conversion parameters structure definition
  155. */
  156. typedef struct
  157. {
  158. uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
  159. This parameter can be a value of @ref DFSDM_Filter_Trigger */
  160. FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
  161. FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
  162. uint32_t ExtTrigger; /*!< External trigger.
  163. This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
  164. uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
  165. This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
  166. }DFSDM_Filter_InjectedParamTypeDef;
  167. /**
  168. * @brief DFSDM filter parameters structure definition
  169. */
  170. typedef struct
  171. {
  172. uint32_t SincOrder; /*!< Sinc filter order.
  173. This parameter can be a value of @ref DFSDM_Filter_SincOrder */
  174. uint32_t Oversampling; /*!< Filter oversampling ratio.
  175. This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
  176. uint32_t IntOversampling; /*!< Integrator oversampling ratio.
  177. This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
  178. }DFSDM_Filter_FilterParamTypeDef;
  179. /**
  180. * @brief DFSDM filter init structure definition
  181. */
  182. typedef struct
  183. {
  184. DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
  185. DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
  186. DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
  187. }DFSDM_Filter_InitTypeDef;
  188. /**
  189. * @brief DFSDM filter handle structure definition
  190. */
  191. typedef struct
  192. {
  193. DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
  194. DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
  195. DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
  196. DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
  197. uint32_t RegularContMode; /*!< Regular conversion continuous mode */
  198. uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
  199. uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
  200. uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
  201. FunctionalState InjectedScanMode; /*!< Injected scanning mode */
  202. uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
  203. uint32_t InjConvRemaining; /*!< Injected conversions remaining */
  204. HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
  205. uint32_t ErrorCode; /*!< DFSDM filter error code */
  206. }DFSDM_Filter_HandleTypeDef;
  207. /**
  208. * @brief DFSDM filter analog watchdog parameters structure definition
  209. */
  210. typedef struct
  211. {
  212. uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
  213. This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
  214. uint32_t Channel; /*!< Analog watchdog channel selection.
  215. This parameter can be a values combination of @ref DFSDM_Channel_Selection */
  216. int32_t HighThreshold; /*!< High threshold for the analog watchdog.
  217. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
  218. int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
  219. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
  220. uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
  221. This parameter can be a values combination of @ref DFSDM_BreakSignals */
  222. uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
  223. This parameter can be a values combination of @ref DFSDM_BreakSignals */
  224. }DFSDM_Filter_AwdParamTypeDef;
  225. /**
  226. * @}
  227. */
  228. /* End of exported types -----------------------------------------------------*/
  229. /* Exported constants --------------------------------------------------------*/
  230. /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
  231. * @{
  232. */
  233. /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
  234. * @{
  235. */
  236. #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
  237. #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
  238. /**
  239. * @}
  240. */
  241. /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
  242. * @{
  243. */
  244. #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
  245. #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
  246. /**
  247. * @}
  248. */
  249. /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
  250. * @{
  251. */
  252. #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */
  253. #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
  254. #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
  255. /**
  256. * @}
  257. */
  258. /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
  259. * @{
  260. */
  261. #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
  262. #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
  263. /**
  264. * @}
  265. */
  266. /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
  267. * @{
  268. */
  269. #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */
  270. #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
  271. #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
  272. #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
  273. /**
  274. * @}
  275. */
  276. /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
  277. * @{
  278. */
  279. #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */
  280. #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
  281. #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
  282. #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
  283. /**
  284. * @}
  285. */
  286. /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
  287. * @{
  288. */
  289. #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
  290. #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
  291. #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
  292. #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
  293. /**
  294. * @}
  295. */
  296. /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
  297. * @{
  298. */
  299. #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */
  300. #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
  301. #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
  302. /**
  303. * @}
  304. */
  305. /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
  306. * @{
  307. */
  308. #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
  309. #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
  310. #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
  311. #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */
  312. #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */
  313. #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
  314. #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
  315. #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \
  316. DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
  317. #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */
  318. #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
  319. #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \
  320. DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
  321. #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
  322. DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
  323. /**
  324. * @}
  325. */
  326. /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
  327. * @{
  328. */
  329. #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
  330. #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
  331. #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
  332. /**
  333. * @}
  334. */
  335. /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
  336. * @{
  337. */
  338. #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
  339. #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
  340. #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
  341. #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
  342. #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
  343. #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
  344. /**
  345. * @}
  346. */
  347. /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
  348. * @{
  349. */
  350. #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */
  351. #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
  352. /**
  353. * @}
  354. */
  355. /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
  356. * @{
  357. */
  358. #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
  359. #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
  360. #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
  361. #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */
  362. /**
  363. * @}
  364. */
  365. /** @defgroup DFSDM_BreakSignals DFSDM break signals
  366. * @{
  367. */
  368. #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
  369. #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */
  370. #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */
  371. #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */
  372. #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */
  373. /**
  374. * @}
  375. */
  376. /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
  377. * @{
  378. */
  379. /* DFSDM Channels ------------------------------------------------------------*/
  380. /* The DFSDM channels are defined as follows:
  381. - in 16-bit LSB the channel mask is set
  382. - in 16-bit MSB the channel number is set
  383. e.g. for channel 5 definition:
  384. - the channel mask is 0x00000020 (bit 5 is set)
  385. - the channel number 5 is 0x00050000
  386. --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
  387. #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
  388. #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
  389. #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
  390. #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
  391. #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
  392. #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
  393. #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
  394. #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
  395. /**
  396. * @}
  397. */
  398. /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
  399. * @{
  400. */
  401. #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
  402. #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */
  403. /**
  404. * @}
  405. */
  406. /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
  407. * @{
  408. */
  409. #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
  410. #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
  411. /**
  412. * @}
  413. */
  414. /**
  415. * @}
  416. */
  417. /* End of exported constants -------------------------------------------------*/
  418. /* Exported macros -----------------------------------------------------------*/
  419. /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
  420. * @{
  421. */
  422. /** @brief Reset DFSDM channel handle state.
  423. * @param __HANDLE__: DFSDM channel handle.
  424. * @retval None
  425. */
  426. #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
  427. /** @brief Reset DFSDM filter handle state.
  428. * @param __HANDLE__: DFSDM filter handle.
  429. * @retval None
  430. */
  431. #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
  432. /**
  433. * @}
  434. */
  435. /* End of exported macros ----------------------------------------------------*/
  436. /* Exported functions --------------------------------------------------------*/
  437. /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
  438. * @{
  439. */
  440. /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
  441. * @{
  442. */
  443. /* Channel initialization and de-initialization functions *********************/
  444. HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  445. HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  446. void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  447. void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  448. /**
  449. * @}
  450. */
  451. /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
  452. * @{
  453. */
  454. /* Channel operation functions ************************************************/
  455. HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  456. HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  457. HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  458. HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  459. HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
  460. HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
  461. HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  462. HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  463. int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  464. HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
  465. HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
  466. HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
  467. void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  468. void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  469. /**
  470. * @}
  471. */
  472. /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
  473. * @{
  474. */
  475. /* Channel state function *****************************************************/
  476. HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
  477. /**
  478. * @}
  479. */
  480. /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
  481. * @{
  482. */
  483. /* Filter initialization and de-initialization functions *********************/
  484. HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  485. HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  486. void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  487. void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  488. /**
  489. * @}
  490. */
  491. /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
  492. * @{
  493. */
  494. /* Filter control functions *********************/
  495. HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
  496. uint32_t Channel,
  497. uint32_t ContinuousMode);
  498. HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
  499. uint32_t Channel);
  500. /**
  501. * @}
  502. */
  503. /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
  504. * @{
  505. */
  506. /* Filter operation functions *********************/
  507. HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  508. HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  509. HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
  510. HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
  511. HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  512. HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  513. HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  514. HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  515. HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  516. HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
  517. HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
  518. HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  519. HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  520. HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  521. HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
  522. DFSDM_Filter_AwdParamTypeDef* awdParam);
  523. HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  524. HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
  525. HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  526. int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
  527. int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
  528. int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
  529. int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
  530. uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  531. void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  532. HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
  533. HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
  534. void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  535. void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  536. void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  537. void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  538. void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
  539. void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  540. /**
  541. * @}
  542. */
  543. /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
  544. * @{
  545. */
  546. /* Filter state functions *****************************************************/
  547. HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  548. uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
  549. /**
  550. * @}
  551. */
  552. /**
  553. * @}
  554. */
  555. /* End of exported functions -------------------------------------------------*/
  556. /* Private macros ------------------------------------------------------------*/
  557. /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
  558. * @{
  559. */
  560. #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
  561. ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
  562. #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
  563. #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
  564. ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
  565. #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
  566. ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
  567. ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
  568. #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
  569. ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
  570. #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
  571. ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
  572. ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
  573. ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
  574. #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
  575. ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
  576. ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
  577. ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
  578. #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
  579. ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
  580. ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
  581. ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
  582. #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
  583. #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
  584. #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
  585. #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
  586. #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
  587. ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
  588. #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
  589. ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
  590. ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
  591. #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
  592. ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \
  593. ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
  594. ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \
  595. ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
  596. ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
  597. ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
  598. ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
  599. ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
  600. ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
  601. ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\
  602. ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
  603. #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
  604. ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
  605. ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
  606. #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
  607. ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
  608. ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
  609. ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
  610. ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
  611. ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
  612. #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
  613. #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
  614. #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
  615. ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
  616. #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
  617. #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
  618. #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
  619. ((CHANNEL) == DFSDM_CHANNEL_1) || \
  620. ((CHANNEL) == DFSDM_CHANNEL_2) || \
  621. ((CHANNEL) == DFSDM_CHANNEL_3) || \
  622. ((CHANNEL) == DFSDM_CHANNEL_4) || \
  623. ((CHANNEL) == DFSDM_CHANNEL_5) || \
  624. ((CHANNEL) == DFSDM_CHANNEL_6) || \
  625. ((CHANNEL) == DFSDM_CHANNEL_7))
  626. #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
  627. #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
  628. ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
  629. /**
  630. * @}
  631. */
  632. /* End of private macros -----------------------------------------------------*/
  633. /**
  634. * @}
  635. */
  636. /**
  637. * @}
  638. */
  639. #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
  640. #ifdef __cplusplus
  641. }
  642. #endif
  643. #endif /* __STM32F7xx_HAL_DFSDM_H */
  644. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/