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  1. /**
  2. ******************************************************************************
  3. * @file stm32f7xx_hal_dsi.c
  4. * @author MCD Application Team
  5. * @version V1.2.2
  6. * @date 14-April-2017
  7. * @brief DSI HAL module driver.
  8. * This file provides firmware functions to manage the following
  9. * functionalities of the DSI peripheral:
  10. * + Initialization and de-initialization functions
  11. * + IO operation functions
  12. * + Peripheral Control functions
  13. * + Peripheral State and Errors functions
  14. ******************************************************************************
  15. * @attention
  16. *
  17. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  18. *
  19. * Redistribution and use in source and binary forms, with or without modification,
  20. * are permitted provided that the following conditions are met:
  21. * 1. Redistributions of source code must retain the above copyright notice,
  22. * this list of conditions and the following disclaimer.
  23. * 2. Redistributions in binary form must reproduce the above copyright notice,
  24. * this list of conditions and the following disclaimer in the documentation
  25. * and/or other materials provided with the distribution.
  26. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  27. * may be used to endorse or promote products derived from this software
  28. * without specific prior written permission.
  29. *
  30. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  31. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  32. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  34. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  36. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  37. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  38. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. *
  41. ******************************************************************************
  42. */
  43. /* Includes ------------------------------------------------------------------*/
  44. #include "stm32f7xx_hal.h"
  45. /** @addtogroup STM32F7xx_HAL_Driver
  46. * @{
  47. */
  48. /** @addtogroup DSI
  49. * @{
  50. */
  51. #ifdef HAL_DSI_MODULE_ENABLED
  52. #if defined (STM32F769xx) || defined (STM32F779xx)
  53. /* Private types -------------------------------------------------------------*/
  54. /* Private defines -----------------------------------------------------------*/
  55. /** @addtogroup DSI_Private_Constants
  56. * @{
  57. */
  58. #define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
  59. #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
  60. DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
  61. DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
  62. DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
  63. #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
  64. #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
  65. #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
  66. #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
  67. #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
  68. #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
  69. #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
  70. #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
  71. #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
  72. /**
  73. * @}
  74. */
  75. /* Private variables ---------------------------------------------------------*/
  76. /* Private constants ---------------------------------------------------------*/
  77. /* Private macros ------------------------------------------------------------*/
  78. /* Private function prototypes -----------------------------------------------*/
  79. static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
  80. /* Private functions ---------------------------------------------------------*/
  81. /**
  82. * @brief Generic DSI packet header configuration
  83. * @param DSIx: Pointer to DSI register base
  84. * @param ChannelID: Virtual channel ID of the header packet
  85. * @param DataType: Packet data type of the header packet
  86. * This parameter can be any value of :
  87. * @ref DSI_SHORT_WRITE_PKT_Data_Type
  88. * or @ref DSI_LONG_WRITE_PKT_Data_Type
  89. * or @ref DSI_SHORT_READ_PKT_Data_Type
  90. * or DSI_MAX_RETURN_PKT_SIZE
  91. * @param Data0: Word count LSB
  92. * @param Data1: Word count MSB
  93. * @retval None
  94. */
  95. static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
  96. uint32_t ChannelID,
  97. uint32_t DataType,
  98. uint32_t Data0,
  99. uint32_t Data1)
  100. {
  101. /* Update the DSI packet header with new information */
  102. DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));
  103. }
  104. /* Exported functions --------------------------------------------------------*/
  105. /** @addtogroup DSI_Exported_Functions
  106. * @{
  107. */
  108. /** @defgroup DSI_Group1 Initialization and Configuration functions
  109. * @brief Initialization and Configuration functions
  110. *
  111. @verbatim
  112. ===============================================================================
  113. ##### Initialization and Configuration functions #####
  114. ===============================================================================
  115. [..] This section provides functions allowing to:
  116. (+) Initialize and configure the DSI
  117. (+) De-initialize the DSI
  118. @endverbatim
  119. * @{
  120. */
  121. /**
  122. * @brief Initializes the DSI according to the specified
  123. * parameters in the DSI_InitTypeDef and create the associated handle.
  124. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  125. * the configuration information for the DSI.
  126. * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
  127. * the PLL Clock structure definition for the DSI.
  128. * @retval HAL status
  129. */
  130. HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
  131. {
  132. uint32_t tickstart = 0;
  133. uint32_t unitIntervalx4 = 0;
  134. uint32_t tempIDF = 0;
  135. /* Check the DSI handle allocation */
  136. if(hdsi == NULL)
  137. {
  138. return HAL_ERROR;
  139. }
  140. /* Check function parameters */
  141. assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
  142. assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
  143. assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
  144. assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
  145. assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
  146. if(hdsi->State == HAL_DSI_STATE_RESET)
  147. {
  148. /* Initialize the low level hardware */
  149. HAL_DSI_MspInit(hdsi);
  150. }
  151. /* Change DSI peripheral state */
  152. hdsi->State = HAL_DSI_STATE_BUSY;
  153. /**************** Turn on the regulator and enable the DSI PLL ****************/
  154. /* Enable the regulator */
  155. __HAL_DSI_REG_ENABLE(hdsi);
  156. /* Get tick */
  157. tickstart = HAL_GetTick();
  158. /* Wait until the regulator is ready */
  159. while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
  160. {
  161. /* Check for the Timeout */
  162. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  163. {
  164. return HAL_TIMEOUT;
  165. }
  166. }
  167. /* Set the PLL division factors */
  168. hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
  169. hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));
  170. /* Enable the DSI PLL */
  171. __HAL_DSI_PLL_ENABLE(hdsi);
  172. /* Get tick */
  173. tickstart = HAL_GetTick();
  174. /* Wait for the lock of the PLL */
  175. while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
  176. {
  177. /* Check for the Timeout */
  178. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  179. {
  180. return HAL_TIMEOUT;
  181. }
  182. }
  183. /*************************** Set the PHY parameters ***************************/
  184. /* D-PHY clock and digital enable*/
  185. hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
  186. /* Clock lane configuration */
  187. hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
  188. hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
  189. /* Configure the number of active data lanes */
  190. hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
  191. hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
  192. /************************ Set the DSI clock parameters ************************/
  193. /* Set the TX escape clock division factor */
  194. hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
  195. hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
  196. /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
  197. /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
  198. /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
  199. tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;
  200. unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);
  201. /* Set the bit period in high-speed mode */
  202. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4;
  203. hdsi->Instance->WPCR[0] |= unitIntervalx4;
  204. /****************************** Error management *****************************/
  205. /* Disable all error interrupts and reset the Error Mask */
  206. hdsi->Instance->IER[0] = 0;
  207. hdsi->Instance->IER[1] = 0;
  208. hdsi->ErrorMsk = 0;
  209. /* Initialise the error code */
  210. hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
  211. /* Initialize the DSI state*/
  212. hdsi->State = HAL_DSI_STATE_READY;
  213. return HAL_OK;
  214. }
  215. /**
  216. * @brief De-initializes the DSI peripheral registers to their default reset
  217. * values.
  218. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  219. * the configuration information for the DSI.
  220. * @retval HAL status
  221. */
  222. HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
  223. {
  224. /* Check the DSI handle allocation */
  225. if(hdsi == NULL)
  226. {
  227. return HAL_ERROR;
  228. }
  229. /* Change DSI peripheral state */
  230. hdsi->State = HAL_DSI_STATE_BUSY;
  231. /* Disable the DSI wrapper */
  232. __HAL_DSI_WRAPPER_DISABLE(hdsi);
  233. /* Disable the DSI host */
  234. __HAL_DSI_DISABLE(hdsi);
  235. /* D-PHY clock and digital disable */
  236. hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
  237. /* Turn off the DSI PLL */
  238. __HAL_DSI_PLL_DISABLE(hdsi);
  239. /* Disable the regulator */
  240. __HAL_DSI_REG_DISABLE(hdsi);
  241. /* DeInit the low level hardware */
  242. HAL_DSI_MspDeInit(hdsi);
  243. /* Initialise the error code */
  244. hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
  245. /* Initialize the DSI state*/
  246. hdsi->State = HAL_DSI_STATE_RESET;
  247. /* Release Lock */
  248. __HAL_UNLOCK(hdsi);
  249. return HAL_OK;
  250. }
  251. /**
  252. * @brief Return the DSI error code
  253. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  254. * the configuration information for the DSI.
  255. * @retval DSI Error Code
  256. */
  257. uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
  258. {
  259. /* Get the error code */
  260. return hdsi->ErrorCode;
  261. }
  262. /**
  263. * @brief Enable the error monitor flags
  264. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  265. * the configuration information for the DSI.
  266. * @param ActiveErrors: indicates which error interrupts will be enabled.
  267. * This parameter can be any combination of @ref DSI_Error_Data_Type.
  268. * @retval HAL status
  269. */
  270. HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
  271. {
  272. /* Process locked */
  273. __HAL_LOCK(hdsi);
  274. hdsi->Instance->IER[0] = 0;
  275. hdsi->Instance->IER[1] = 0;
  276. /* Store active errors to the handle */
  277. hdsi->ErrorMsk = ActiveErrors;
  278. if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
  279. {
  280. /* Enable the interrupt generation on selected errors */
  281. hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK;
  282. }
  283. if((ActiveErrors & HAL_DSI_ERROR_PHY ) != RESET)
  284. {
  285. /* Enable the interrupt generation on selected errors */
  286. hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK;
  287. }
  288. if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
  289. {
  290. /* Enable the interrupt generation on selected errors */
  291. hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK;
  292. }
  293. if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
  294. {
  295. /* Enable the interrupt generation on selected errors */
  296. hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK;
  297. }
  298. if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
  299. {
  300. /* Enable the interrupt generation on selected errors */
  301. hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK;
  302. }
  303. if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
  304. {
  305. /* Enable the interrupt generation on selected errors */
  306. hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK;
  307. }
  308. if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
  309. {
  310. /* Enable the interrupt generation on selected errors */
  311. hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK;
  312. }
  313. if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
  314. {
  315. /* Enable the interrupt generation on selected errors */
  316. hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK;
  317. }
  318. if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
  319. {
  320. /* Enable the interrupt generation on selected errors */
  321. hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK;
  322. }
  323. if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
  324. {
  325. /* Enable the interrupt generation on selected errors */
  326. hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK;
  327. }
  328. /* Process Unlocked */
  329. __HAL_UNLOCK(hdsi);
  330. return HAL_OK;
  331. }
  332. /**
  333. * @brief Initializes the DSI MSP.
  334. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  335. * the configuration information for the DSI.
  336. * @retval None
  337. */
  338. __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
  339. {
  340. /* Prevent unused argument(s) compilation warning */
  341. UNUSED(hdsi);
  342. /* NOTE : This function Should not be modified, when the callback is needed,
  343. the HAL_DSI_MspInit could be implemented in the user file
  344. */
  345. }
  346. /**
  347. * @brief De-initializes the DSI MSP.
  348. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  349. * the configuration information for the DSI.
  350. * @retval None
  351. */
  352. __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
  353. {
  354. /* Prevent unused argument(s) compilation warning */
  355. UNUSED(hdsi);
  356. /* NOTE : This function Should not be modified, when the callback is needed,
  357. the HAL_DSI_MspDeInit could be implemented in the user file
  358. */
  359. }
  360. /**
  361. * @}
  362. */
  363. /** @defgroup DSI_Group2 IO operation functions
  364. * @brief IO operation functions
  365. *
  366. @verbatim
  367. ===============================================================================
  368. ##### IO operation functions #####
  369. ===============================================================================
  370. [..] This section provides function allowing to:
  371. (+) Handle DSI interrupt request
  372. @endverbatim
  373. * @{
  374. */
  375. /**
  376. * @brief Handles DSI interrupt request.
  377. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  378. * the configuration information for the DSI.
  379. * @retval HAL status
  380. */
  381. void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
  382. {
  383. uint32_t ErrorStatus0, ErrorStatus1;
  384. /* Tearing Effect Interrupt management ***************************************/
  385. if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
  386. {
  387. if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
  388. {
  389. /* Clear the Tearing Effect Interrupt Flag */
  390. __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
  391. /* Tearing Effect Callback */
  392. HAL_DSI_TearingEffectCallback(hdsi);
  393. }
  394. }
  395. /* End of Refresh Interrupt management ***************************************/
  396. if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
  397. {
  398. if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
  399. {
  400. /* Clear the End of Refresh Interrupt Flag */
  401. __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
  402. /* End of Refresh Callback */
  403. HAL_DSI_EndOfRefreshCallback(hdsi);
  404. }
  405. }
  406. /* Error Interrupts management ***********************************************/
  407. if(hdsi->ErrorMsk != 0)
  408. {
  409. ErrorStatus0 = hdsi->Instance->ISR[0];
  410. ErrorStatus0 &= hdsi->Instance->IER[0];
  411. ErrorStatus1 = hdsi->Instance->ISR[1];
  412. ErrorStatus1 &= hdsi->Instance->IER[1];
  413. if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
  414. {
  415. hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
  416. }
  417. if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
  418. {
  419. hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
  420. }
  421. if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
  422. {
  423. hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
  424. }
  425. if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
  426. {
  427. hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
  428. }
  429. if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
  430. {
  431. hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
  432. }
  433. if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
  434. {
  435. hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
  436. }
  437. if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
  438. {
  439. hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
  440. }
  441. if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
  442. {
  443. hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
  444. }
  445. if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
  446. {
  447. hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
  448. }
  449. if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
  450. {
  451. hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
  452. }
  453. /* Check only selected errors */
  454. if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
  455. {
  456. /* DSI error interrupt user callback */
  457. HAL_DSI_ErrorCallback(hdsi);
  458. }
  459. }
  460. }
  461. /**
  462. * @brief Tearing Effect DSI callback.
  463. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  464. * the configuration information for the DSI.
  465. * @retval None
  466. */
  467. __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
  468. {
  469. /* Prevent unused argument(s) compilation warning */
  470. UNUSED(hdsi);
  471. /* NOTE : This function Should not be modified, when the callback is needed,
  472. the HAL_DSI_TearingEffectCallback could be implemented in the user file
  473. */
  474. }
  475. /**
  476. * @brief End of Refresh DSI callback.
  477. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  478. * the configuration information for the DSI.
  479. * @retval None
  480. */
  481. __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
  482. {
  483. /* Prevent unused argument(s) compilation warning */
  484. UNUSED(hdsi);
  485. /* NOTE : This function Should not be modified, when the callback is needed,
  486. the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
  487. */
  488. }
  489. /**
  490. * @brief Operation Error DSI callback.
  491. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  492. * the configuration information for the DSI.
  493. * @retval None
  494. */
  495. __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
  496. {
  497. /* Prevent unused argument(s) compilation warning */
  498. UNUSED(hdsi);
  499. /* NOTE : This function Should not be modified, when the callback is needed,
  500. the HAL_DSI_ErrorCallback could be implemented in the user file
  501. */
  502. }
  503. /**
  504. * @}
  505. */
  506. /** @defgroup DSI_Group3 Peripheral Control functions
  507. * @brief Peripheral Control functions
  508. *
  509. @verbatim
  510. ===============================================================================
  511. ##### Peripheral Control functions #####
  512. ===============================================================================
  513. @endverbatim
  514. * @{
  515. */
  516. /**
  517. * @brief Configure the Generic interface read-back Virtual Channel ID.
  518. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  519. * the configuration information for the DSI.
  520. * @param VirtualChannelID: Virtual channel ID
  521. * @retval HAL status
  522. */
  523. HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
  524. {
  525. /* Process locked */
  526. __HAL_LOCK(hdsi);
  527. /* Update the GVCID register */
  528. hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
  529. hdsi->Instance->GVCIDR |= VirtualChannelID;
  530. /* Process unlocked */
  531. __HAL_UNLOCK(hdsi);
  532. return HAL_OK;
  533. }
  534. /**
  535. * @brief Select video mode and configure the corresponding parameters
  536. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  537. * the configuration information for the DSI.
  538. * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
  539. * the DSI video mode configuration parameters
  540. * @retval HAL status
  541. */
  542. HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
  543. {
  544. /* Process locked */
  545. __HAL_LOCK(hdsi);
  546. /* Check the parameters */
  547. assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
  548. assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
  549. assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
  550. assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
  551. assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
  552. assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
  553. assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
  554. assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
  555. assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
  556. assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
  557. assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
  558. assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
  559. assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
  560. /* Check the LooselyPacked variant only in 18-bit mode */
  561. if(VidCfg->ColorCoding == DSI_RGB666)
  562. {
  563. assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
  564. }
  565. /* Select video mode by resetting CMDM and DSIM bits */
  566. hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
  567. hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
  568. /* Configure the video mode transmission type */
  569. hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
  570. hdsi->Instance->VMCR |= VidCfg->Mode;
  571. /* Configure the video packet size */
  572. hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
  573. hdsi->Instance->VPCR |= VidCfg->PacketSize;
  574. /* Set the chunks number to be transmitted through the DSI link */
  575. hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
  576. hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
  577. /* Set the size of the null packet */
  578. hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
  579. hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
  580. /* Select the virtual channel for the LTDC interface traffic */
  581. hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
  582. hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
  583. /* Configure the polarity of control signals */
  584. hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
  585. hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
  586. /* Select the color coding for the host */
  587. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
  588. hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
  589. /* Select the color coding for the wrapper */
  590. hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
  591. hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1);
  592. /* Enable/disable the loosely packed variant to 18-bit configuration */
  593. if(VidCfg->ColorCoding == DSI_RGB666)
  594. {
  595. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
  596. hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
  597. }
  598. /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
  599. hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
  600. hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
  601. /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
  602. hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
  603. hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
  604. /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
  605. hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
  606. hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
  607. /* Set the Vertical Synchronization Active (VSA) */
  608. hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
  609. hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
  610. /* Set the Vertical Back Porch (VBP)*/
  611. hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
  612. hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
  613. /* Set the Vertical Front Porch (VFP)*/
  614. hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
  615. hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
  616. /* Set the Vertical Active period*/
  617. hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
  618. hdsi->Instance->VVACR |= VidCfg->VerticalActive;
  619. /* Configure the command transmission mode */
  620. hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
  621. hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
  622. /* Low power largest packet size */
  623. hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
  624. hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);
  625. /* Low power VACT largest packet size */
  626. hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
  627. hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
  628. /* Enable LP transition in HFP period */
  629. hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
  630. hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
  631. /* Enable LP transition in HBP period */
  632. hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
  633. hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
  634. /* Enable LP transition in VACT period */
  635. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
  636. hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
  637. /* Enable LP transition in VFP period */
  638. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
  639. hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
  640. /* Enable LP transition in VBP period */
  641. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
  642. hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
  643. /* Enable LP transition in vertical sync period */
  644. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
  645. hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
  646. /* Enable the request for an acknowledge response at the end of a frame */
  647. hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
  648. hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
  649. /* Process unlocked */
  650. __HAL_UNLOCK(hdsi);
  651. return HAL_OK;
  652. }
  653. /**
  654. * @brief Select adapted command mode and configure the corresponding parameters
  655. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  656. * the configuration information for the DSI.
  657. * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
  658. * the DSI command mode configuration parameters
  659. * @retval HAL status
  660. */
  661. HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
  662. {
  663. /* Process locked */
  664. __HAL_LOCK(hdsi);
  665. /* Check the parameters */
  666. assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
  667. assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
  668. assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
  669. assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
  670. assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
  671. assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
  672. assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
  673. assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
  674. assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
  675. /* Select command mode by setting CMDM and DSIM bits */
  676. hdsi->Instance->MCR |= DSI_MCR_CMDM;
  677. hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
  678. hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
  679. /* Select the virtual channel for the LTDC interface traffic */
  680. hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
  681. hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
  682. /* Configure the polarity of control signals */
  683. hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
  684. hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
  685. /* Select the color coding for the host */
  686. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
  687. hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
  688. /* Select the color coding for the wrapper */
  689. hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
  690. hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1);
  691. /* Configure the maximum allowed size for write memory command */
  692. hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
  693. hdsi->Instance->LCCR |= CmdCfg->CommandSize;
  694. /* Configure the tearing effect source and polarity and select the refresh mode */
  695. hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
  696. hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
  697. /* Configure the tearing effect acknowledge request */
  698. hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
  699. hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
  700. /* Enable the Tearing Effect interrupt */
  701. __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
  702. /* Enable the End of Refresh interrupt */
  703. __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
  704. /* Process unlocked */
  705. __HAL_UNLOCK(hdsi);
  706. return HAL_OK;
  707. }
  708. /**
  709. * @brief Configure command transmission mode: High-speed or Low-power
  710. * and enable/disable acknowledge request after packet transmission
  711. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  712. * the configuration information for the DSI.
  713. * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
  714. * the DSI command transmission mode configuration parameters
  715. * @retval HAL status
  716. */
  717. HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
  718. {
  719. /* Process locked */
  720. __HAL_LOCK(hdsi);
  721. assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
  722. assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
  723. assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
  724. assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
  725. assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
  726. assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
  727. assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
  728. assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
  729. assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
  730. assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
  731. assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
  732. assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
  733. assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
  734. /* Select High-speed or Low-power for command transmission */
  735. hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
  736. DSI_CMCR_GSW1TX |\
  737. DSI_CMCR_GSW2TX |\
  738. DSI_CMCR_GSR0TX |\
  739. DSI_CMCR_GSR1TX |\
  740. DSI_CMCR_GSR2TX |\
  741. DSI_CMCR_GLWTX |\
  742. DSI_CMCR_DSW0TX |\
  743. DSI_CMCR_DSW1TX |\
  744. DSI_CMCR_DSR0TX |\
  745. DSI_CMCR_DLWTX |\
  746. DSI_CMCR_MRDPS);
  747. hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
  748. LPCmd->LPGenShortWriteOneP |\
  749. LPCmd->LPGenShortWriteTwoP |\
  750. LPCmd->LPGenShortReadNoP |\
  751. LPCmd->LPGenShortReadOneP |\
  752. LPCmd->LPGenShortReadTwoP |\
  753. LPCmd->LPGenLongWrite |\
  754. LPCmd->LPDcsShortWriteNoP |\
  755. LPCmd->LPDcsShortWriteOneP |\
  756. LPCmd->LPDcsShortReadNoP |\
  757. LPCmd->LPDcsLongWrite |\
  758. LPCmd->LPMaxReadPacket);
  759. /* Configure the acknowledge request after each packet transmission */
  760. hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
  761. hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
  762. /* Process unlocked */
  763. __HAL_UNLOCK(hdsi);
  764. return HAL_OK;
  765. }
  766. /**
  767. * @brief Configure the flow control parameters
  768. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  769. * the configuration information for the DSI.
  770. * @param FlowControl: flow control feature(s) to be enabled.
  771. * This parameter can be any combination of @ref DSI_FlowControl.
  772. * @retval HAL status
  773. */
  774. HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
  775. {
  776. /* Process locked */
  777. __HAL_LOCK(hdsi);
  778. /* Check the parameters */
  779. assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
  780. /* Set the DSI Host Protocol Configuration Register */
  781. hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
  782. hdsi->Instance->PCR |= FlowControl;
  783. /* Process unlocked */
  784. __HAL_UNLOCK(hdsi);
  785. return HAL_OK;
  786. }
  787. /**
  788. * @brief Configure the DSI PHY timer parameters
  789. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  790. * the configuration information for the DSI.
  791. * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
  792. * the DSI PHY timing parameters
  793. * @retval HAL status
  794. */
  795. HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
  796. {
  797. uint32_t maxTime;
  798. /* Process locked */
  799. __HAL_LOCK(hdsi);
  800. maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
  801. /* Clock lane timer configuration */
  802. /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
  803. High-Speed transmission.
  804. To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
  805. to Low-Power and from Low-Power to High-Speed.
  806. This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
  807. But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
  808. Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
  809. */
  810. hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
  811. hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16));
  812. /* Data lane timer configuration */
  813. hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
  814. hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));
  815. /* Configure the wait period to request HS transmission after a stop state */
  816. hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
  817. hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8);
  818. /* Process unlocked */
  819. __HAL_UNLOCK(hdsi);
  820. return HAL_OK;
  821. }
  822. /**
  823. * @brief Configure the DSI HOST timeout parameters
  824. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  825. * the configuration information for the DSI.
  826. * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
  827. * the DSI host timeout parameters
  828. * @retval HAL status
  829. */
  830. HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
  831. {
  832. /* Process locked */
  833. __HAL_LOCK(hdsi);
  834. /* Set the timeout clock division factor */
  835. hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
  836. hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8);
  837. /* High-speed transmission timeout */
  838. hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;
  839. hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);
  840. /* Low-power reception timeout */
  841. hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;
  842. hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;
  843. /* High-speed read timeout */
  844. hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;
  845. hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;
  846. /* Low-power read timeout */
  847. hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;
  848. hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;
  849. /* High-speed write timeout */
  850. hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;
  851. hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;
  852. /* High-speed write presp mode */
  853. hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM;
  854. hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;
  855. /* Low-speed write timeout */
  856. hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;
  857. hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;
  858. /* BTA timeout */
  859. hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;
  860. hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout;
  861. /* Process unlocked */
  862. __HAL_UNLOCK(hdsi);
  863. return HAL_OK;
  864. }
  865. /**
  866. * @brief Start the DSI module
  867. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  868. * the configuration information for the DSI.
  869. * @retval HAL status
  870. */
  871. HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
  872. {
  873. /* Process locked */
  874. __HAL_LOCK(hdsi);
  875. /* Enable the DSI host */
  876. __HAL_DSI_ENABLE(hdsi);
  877. /* Enable the DSI wrapper */
  878. __HAL_DSI_WRAPPER_ENABLE(hdsi);
  879. /* Process unlocked */
  880. __HAL_UNLOCK(hdsi);
  881. return HAL_OK;
  882. }
  883. /**
  884. * @brief Stop the DSI module
  885. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  886. * the configuration information for the DSI.
  887. * @retval HAL status
  888. */
  889. HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
  890. {
  891. /* Process locked */
  892. __HAL_LOCK(hdsi);
  893. /* Disable the DSI host */
  894. __HAL_DSI_DISABLE(hdsi);
  895. /* Disable the DSI wrapper */
  896. __HAL_DSI_WRAPPER_DISABLE(hdsi);
  897. /* Process unlocked */
  898. __HAL_UNLOCK(hdsi);
  899. return HAL_OK;
  900. }
  901. /**
  902. * @brief Refresh the display in command mode
  903. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  904. * the configuration information for the DSI.
  905. * @retval HAL status
  906. */
  907. HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
  908. {
  909. /* Process locked */
  910. __HAL_LOCK(hdsi);
  911. /* Update the display */
  912. hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
  913. /* Process unlocked */
  914. __HAL_UNLOCK(hdsi);
  915. return HAL_OK;
  916. }
  917. /**
  918. * @brief Controls the display color mode in Video mode
  919. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  920. * the configuration information for the DSI.
  921. * @param ColorMode: Color mode (full or 8-colors).
  922. * This parameter can be any value of @ref DSI_Color_Mode
  923. * @retval HAL status
  924. */
  925. HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
  926. {
  927. /* Process locked */
  928. __HAL_LOCK(hdsi);
  929. /* Check the parameters */
  930. assert_param(IS_DSI_COLOR_MODE(ColorMode));
  931. /* Update the display color mode */
  932. hdsi->Instance->WCR &= ~DSI_WCR_COLM;
  933. hdsi->Instance->WCR |= ColorMode;
  934. /* Process unlocked */
  935. __HAL_UNLOCK(hdsi);
  936. return HAL_OK;
  937. }
  938. /**
  939. * @brief Control the display shutdown in Video mode
  940. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  941. * the configuration information for the DSI.
  942. * @param Shutdown: Shut-down (Display-ON or Display-OFF).
  943. * This parameter can be any value of @ref DSI_ShutDown
  944. * @retval HAL status
  945. */
  946. HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
  947. {
  948. /* Process locked */
  949. __HAL_LOCK(hdsi);
  950. /* Check the parameters */
  951. assert_param(IS_DSI_SHUT_DOWN(Shutdown));
  952. /* Update the display Shutdown */
  953. hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
  954. hdsi->Instance->WCR |= Shutdown;
  955. /* Process unlocked */
  956. __HAL_UNLOCK(hdsi);
  957. return HAL_OK;
  958. }
  959. /**
  960. * @brief DCS or Generic short write command
  961. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  962. * the configuration information for the DSI.
  963. * @param ChannelID: Virtual channel ID.
  964. * @param Mode: DSI short packet data type.
  965. * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
  966. * @param Param1: DSC command or first generic parameter.
  967. * This parameter can be any value of @ref DSI_DCS_Command or a
  968. * generic command code.
  969. * @param Param2: DSC parameter or second generic parameter.
  970. * @retval HAL status
  971. */
  972. HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
  973. uint32_t ChannelID,
  974. uint32_t Mode,
  975. uint32_t Param1,
  976. uint32_t Param2)
  977. {
  978. uint32_t tickstart = 0;
  979. /* Process locked */
  980. __HAL_LOCK(hdsi);
  981. /* Check the parameters */
  982. assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
  983. /* Get tick */
  984. tickstart = HAL_GetTick();
  985. /* Wait for Command FIFO Empty */
  986. while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0)
  987. {
  988. /* Check for the Timeout */
  989. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  990. {
  991. /* Process Unlocked */
  992. __HAL_UNLOCK(hdsi);
  993. return HAL_TIMEOUT;
  994. }
  995. }
  996. /* Configure the packet to send a short DCS command with 0 or 1 parameter */
  997. DSI_ConfigPacketHeader(hdsi->Instance,
  998. ChannelID,
  999. Mode,
  1000. Param1,
  1001. Param2);
  1002. /* Process unlocked */
  1003. __HAL_UNLOCK(hdsi);
  1004. return HAL_OK;
  1005. }
  1006. /**
  1007. * @brief DCS or Generic long write command
  1008. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1009. * the configuration information for the DSI.
  1010. * @param ChannelID: Virtual channel ID.
  1011. * @param Mode: DSI long packet data type.
  1012. * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
  1013. * @param NbParams: Number of parameters.
  1014. * @param Param1: DSC command or first generic parameter.
  1015. * This parameter can be any value of @ref DSI_DCS_Command or a
  1016. * generic command code
  1017. * @param ParametersTable: Pointer to parameter values table.
  1018. * @retval HAL status
  1019. */
  1020. HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
  1021. uint32_t ChannelID,
  1022. uint32_t Mode,
  1023. uint32_t NbParams,
  1024. uint32_t Param1,
  1025. uint8_t* ParametersTable)
  1026. {
  1027. uint32_t uicounter = 0;
  1028. uint32_t tickstart = 0;
  1029. /* Process locked */
  1030. __HAL_LOCK(hdsi);
  1031. /* Check the parameters */
  1032. assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
  1033. /* Get tick */
  1034. tickstart = HAL_GetTick();
  1035. /* Wait for Command FIFO Empty */
  1036. while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
  1037. {
  1038. /* Check for the Timeout */
  1039. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1040. {
  1041. /* Process Unlocked */
  1042. __HAL_UNLOCK(hdsi);
  1043. return HAL_TIMEOUT;
  1044. }
  1045. }
  1046. /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
  1047. while(uicounter < NbParams)
  1048. {
  1049. if(uicounter == 0x00)
  1050. {
  1051. hdsi->Instance->GPDR=(Param1 | \
  1052. ((uint32_t)(*(ParametersTable + uicounter)) << 8) | \
  1053. ((uint32_t)(*(ParametersTable + uicounter+1))<<16) | \
  1054. ((uint32_t)(*(ParametersTable + uicounter+2))<<24));
  1055. uicounter += 3;
  1056. }
  1057. else
  1058. {
  1059. hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) | \
  1060. ((uint32_t)(*(ParametersTable + uicounter+1)) << 8) | \
  1061. ((uint32_t)(*(ParametersTable + uicounter+2)) << 16) | \
  1062. ((uint32_t)(*(ParametersTable + uicounter+3)) << 24));
  1063. uicounter+=4;
  1064. }
  1065. }
  1066. /* Configure the packet to send a long DCS command */
  1067. DSI_ConfigPacketHeader(hdsi->Instance,
  1068. ChannelID,
  1069. Mode,
  1070. ((NbParams+1)&0x00FF),
  1071. (((NbParams+1)&0xFF00)>>8));
  1072. /* Process unlocked */
  1073. __HAL_UNLOCK(hdsi);
  1074. return HAL_OK;
  1075. }
  1076. /**
  1077. * @brief Read command (DCS or generic)
  1078. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1079. * the configuration information for the DSI.
  1080. * @param ChannelNbr: Virtual channel ID
  1081. * @param Array: pointer to a buffer to store the payload of a read back operation.
  1082. * @param Size: Data size to be read (in byte).
  1083. * @param Mode: DSI read packet data type.
  1084. * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
  1085. * @param DCSCmd: DCS get/read command.
  1086. * @param ParametersTable: Pointer to parameter values table.
  1087. * @retval HAL status
  1088. */
  1089. HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
  1090. uint32_t ChannelNbr,
  1091. uint8_t* Array,
  1092. uint32_t Size,
  1093. uint32_t Mode,
  1094. uint32_t DCSCmd,
  1095. uint8_t* ParametersTable)
  1096. {
  1097. uint32_t tickstart = 0;
  1098. /* Process locked */
  1099. __HAL_LOCK(hdsi);
  1100. /* Check the parameters */
  1101. assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
  1102. if(Size > 2)
  1103. {
  1104. /* set max return packet size */
  1105. HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));
  1106. }
  1107. /* Configure the packet to read command */
  1108. if (Mode == DSI_DCS_SHORT_PKT_READ)
  1109. {
  1110. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0);
  1111. }
  1112. else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
  1113. {
  1114. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0);
  1115. }
  1116. else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
  1117. {
  1118. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0);
  1119. }
  1120. else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
  1121. {
  1122. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);
  1123. }
  1124. else
  1125. {
  1126. /* Process Unlocked */
  1127. __HAL_UNLOCK(hdsi);
  1128. return HAL_ERROR;
  1129. }
  1130. /* Get tick */
  1131. tickstart = HAL_GetTick();
  1132. /* Check that the payload read FIFO is not empty */
  1133. while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
  1134. {
  1135. /* Check for the Timeout */
  1136. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1137. {
  1138. /* Process Unlocked */
  1139. __HAL_UNLOCK(hdsi);
  1140. return HAL_TIMEOUT;
  1141. }
  1142. }
  1143. /* Get the first byte */
  1144. *((uint32_t *)Array) = (hdsi->Instance->GPDR);
  1145. if (Size > 4)
  1146. {
  1147. Size -= 4;
  1148. Array += 4;
  1149. }
  1150. else
  1151. {
  1152. /* Process unlocked */
  1153. __HAL_UNLOCK(hdsi);
  1154. return HAL_OK;
  1155. }
  1156. /* Get tick */
  1157. tickstart = HAL_GetTick();
  1158. /* Get the remaining bytes if any */
  1159. while(((int)(Size)) > 0)
  1160. {
  1161. if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0)
  1162. {
  1163. *((uint32_t *)Array) = (hdsi->Instance->GPDR);
  1164. Size -= 4;
  1165. Array += 4;
  1166. }
  1167. /* Check for the Timeout */
  1168. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1169. {
  1170. /* Process Unlocked */
  1171. __HAL_UNLOCK(hdsi);
  1172. return HAL_TIMEOUT;
  1173. }
  1174. }
  1175. /* Process unlocked */
  1176. __HAL_UNLOCK(hdsi);
  1177. return HAL_OK;
  1178. }
  1179. /**
  1180. * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
  1181. * (only data lanes are in ULPM)
  1182. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1183. * the configuration information for the DSI.
  1184. * @retval HAL status
  1185. */
  1186. HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
  1187. {
  1188. uint32_t tickstart = 0;
  1189. /* Process locked */
  1190. __HAL_LOCK(hdsi);
  1191. /* ULPS Request on Data Lanes */
  1192. hdsi->Instance->PUCR |= DSI_PUCR_URDL;
  1193. /* Get tick */
  1194. tickstart = HAL_GetTick();
  1195. /* Wait until the D-PHY active lanes enter into ULPM */
  1196. if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1197. {
  1198. while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
  1199. {
  1200. /* Check for the Timeout */
  1201. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1202. {
  1203. /* Process Unlocked */
  1204. __HAL_UNLOCK(hdsi);
  1205. return HAL_TIMEOUT;
  1206. }
  1207. }
  1208. }
  1209. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1210. {
  1211. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
  1212. {
  1213. /* Check for the Timeout */
  1214. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1215. {
  1216. /* Process Unlocked */
  1217. __HAL_UNLOCK(hdsi);
  1218. return HAL_TIMEOUT;
  1219. }
  1220. }
  1221. }
  1222. /* Process unlocked */
  1223. __HAL_UNLOCK(hdsi);
  1224. return HAL_OK;
  1225. }
  1226. /**
  1227. * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
  1228. * (only data lanes are in ULPM)
  1229. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1230. * the configuration information for the DSI.
  1231. * @retval HAL status
  1232. */
  1233. HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
  1234. {
  1235. uint32_t tickstart = 0;
  1236. /* Process locked */
  1237. __HAL_LOCK(hdsi);
  1238. /* Exit ULPS on Data Lanes */
  1239. hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
  1240. /* Get tick */
  1241. tickstart = HAL_GetTick();
  1242. /* Wait until all active lanes exit ULPM */
  1243. if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1244. {
  1245. while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
  1246. {
  1247. /* Check for the Timeout */
  1248. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1249. {
  1250. /* Process Unlocked */
  1251. __HAL_UNLOCK(hdsi);
  1252. return HAL_TIMEOUT;
  1253. }
  1254. }
  1255. }
  1256. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1257. {
  1258. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
  1259. {
  1260. /* Check for the Timeout */
  1261. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1262. {
  1263. /* Process Unlocked */
  1264. __HAL_UNLOCK(hdsi);
  1265. return HAL_TIMEOUT;
  1266. }
  1267. }
  1268. }
  1269. /* De-assert the ULPM requests and the ULPM exit bits */
  1270. hdsi->Instance->PUCR = 0;
  1271. /* Process unlocked */
  1272. __HAL_UNLOCK(hdsi);
  1273. return HAL_OK;
  1274. }
  1275. /**
  1276. * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
  1277. * (both data and clock lanes are in ULPM)
  1278. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1279. * the configuration information for the DSI.
  1280. * @retval HAL status
  1281. */
  1282. HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
  1283. {
  1284. uint32_t tickstart = 0;
  1285. /* Process locked */
  1286. __HAL_LOCK(hdsi);
  1287. /* Clock lane configuration: no more HS request */
  1288. hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
  1289. /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
  1290. __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
  1291. /* ULPS Request on Clock and Data Lanes */
  1292. hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
  1293. /* Get tick */
  1294. tickstart = HAL_GetTick();
  1295. /* Wait until all active lanes exit ULPM */
  1296. if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1297. {
  1298. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
  1299. {
  1300. /* Check for the Timeout */
  1301. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1302. {
  1303. /* Process Unlocked */
  1304. __HAL_UNLOCK(hdsi);
  1305. return HAL_TIMEOUT;
  1306. }
  1307. }
  1308. }
  1309. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1310. {
  1311. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
  1312. {
  1313. /* Check for the Timeout */
  1314. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1315. {
  1316. /* Process Unlocked */
  1317. __HAL_UNLOCK(hdsi);
  1318. return HAL_TIMEOUT;
  1319. }
  1320. }
  1321. }
  1322. /* Turn off the DSI PLL */
  1323. __HAL_DSI_PLL_DISABLE(hdsi);
  1324. /* Process unlocked */
  1325. __HAL_UNLOCK(hdsi);
  1326. return HAL_OK;
  1327. }
  1328. /**
  1329. * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
  1330. * (both data and clock lanes are in ULPM)
  1331. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1332. * the configuration information for the DSI.
  1333. * @retval HAL status
  1334. */
  1335. HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
  1336. {
  1337. uint32_t tickstart = 0;
  1338. /* Process locked */
  1339. __HAL_LOCK(hdsi);
  1340. /* Turn on the DSI PLL */
  1341. __HAL_DSI_PLL_ENABLE(hdsi);
  1342. /* Get tick */
  1343. tickstart = HAL_GetTick();
  1344. /* Wait for the lock of the PLL */
  1345. while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
  1346. {
  1347. /* Check for the Timeout */
  1348. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1349. {
  1350. /* Process Unlocked */
  1351. __HAL_UNLOCK(hdsi);
  1352. return HAL_TIMEOUT;
  1353. }
  1354. }
  1355. /* Exit ULPS on Clock and Data Lanes */
  1356. hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
  1357. /* Get tick */
  1358. tickstart = HAL_GetTick();
  1359. /* Wait until all active lanes exit ULPM */
  1360. if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1361. {
  1362. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
  1363. {
  1364. /* Check for the Timeout */
  1365. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1366. {
  1367. /* Process Unlocked */
  1368. __HAL_UNLOCK(hdsi);
  1369. return HAL_TIMEOUT;
  1370. }
  1371. }
  1372. }
  1373. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1374. {
  1375. while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
  1376. {
  1377. /* Check for the Timeout */
  1378. if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
  1379. {
  1380. /* Process Unlocked */
  1381. __HAL_UNLOCK(hdsi);
  1382. return HAL_TIMEOUT;
  1383. }
  1384. }
  1385. }
  1386. /* De-assert the ULPM requests and the ULPM exit bits */
  1387. hdsi->Instance->PUCR = 0;
  1388. /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
  1389. __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
  1390. /* Restore clock lane configuration to HS */
  1391. hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
  1392. /* Process unlocked */
  1393. __HAL_UNLOCK(hdsi);
  1394. return HAL_OK;
  1395. }
  1396. /**
  1397. * @brief Start test pattern generation
  1398. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1399. * the configuration information for the DSI.
  1400. * @param Mode: Pattern generator mode
  1401. * This parameter can be one of the following values:
  1402. * 0 : Color bars (horizontal or vertical)
  1403. * 1 : BER pattern (vertical only)
  1404. * @param Orientation: Pattern generator orientation
  1405. * This parameter can be one of the following values:
  1406. * 0 : Vertical color bars
  1407. * 1 : Horizontal color bars
  1408. * @retval HAL status
  1409. */
  1410. HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
  1411. {
  1412. /* Process locked */
  1413. __HAL_LOCK(hdsi);
  1414. /* Configure pattern generator mode and orientation */
  1415. hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
  1416. hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24));
  1417. /* Enable pattern generator by setting PGE bit */
  1418. hdsi->Instance->VMCR |= DSI_VMCR_PGE;
  1419. /* Process unlocked */
  1420. __HAL_UNLOCK(hdsi);
  1421. return HAL_OK;
  1422. }
  1423. /**
  1424. * @brief Stop test pattern generation
  1425. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1426. * the configuration information for the DSI.
  1427. * @retval HAL status
  1428. */
  1429. HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
  1430. {
  1431. /* Process locked */
  1432. __HAL_LOCK(hdsi);
  1433. /* Disable pattern generator by clearing PGE bit */
  1434. hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
  1435. /* Process unlocked */
  1436. __HAL_UNLOCK(hdsi);
  1437. return HAL_OK;
  1438. }
  1439. /**
  1440. * @brief Set Slew-Rate And Delay Tuning
  1441. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1442. * the configuration information for the DSI.
  1443. * @param CommDelay: Communication delay to be adjusted.
  1444. * This parameter can be any value of @ref DSI_Communication_Delay
  1445. * @param Lane: select between clock or data lanes.
  1446. * This parameter can be any value of @ref DSI_Lane_Group
  1447. * @param Value: Custom value of the slew-rate or delay
  1448. * @retval HAL status
  1449. */
  1450. HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
  1451. {
  1452. /* Process locked */
  1453. __HAL_LOCK(hdsi);
  1454. /* Check function parameters */
  1455. assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
  1456. assert_param(IS_DSI_LANE_GROUP(Lane));
  1457. switch(CommDelay)
  1458. {
  1459. case DSI_SLEW_RATE_HSTX:
  1460. if(Lane == DSI_CLOCK_LANE)
  1461. {
  1462. /* High-Speed Transmission Slew Rate Control on Clock Lane */
  1463. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;
  1464. hdsi->Instance->WPCR[1] |= Value<<16;
  1465. }
  1466. else if(Lane == DSI_DATA_LANES)
  1467. {
  1468. /* High-Speed Transmission Slew Rate Control on Data Lanes */
  1469. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;
  1470. hdsi->Instance->WPCR[1] |= Value<<18;
  1471. }
  1472. break;
  1473. case DSI_SLEW_RATE_LPTX:
  1474. if(Lane == DSI_CLOCK_LANE)
  1475. {
  1476. /* Low-Power transmission Slew Rate Compensation on Clock Lane */
  1477. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;
  1478. hdsi->Instance->WPCR[1] |= Value<<6;
  1479. }
  1480. else if(Lane == DSI_DATA_LANES)
  1481. {
  1482. /* Low-Power transmission Slew Rate Compensation on Data Lanes */
  1483. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;
  1484. hdsi->Instance->WPCR[1] |= Value<<8;
  1485. }
  1486. break;
  1487. case DSI_HS_DELAY:
  1488. if(Lane == DSI_CLOCK_LANE)
  1489. {
  1490. /* High-Speed Transmission Delay on Clock Lane */
  1491. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;
  1492. hdsi->Instance->WPCR[1] |= Value;
  1493. }
  1494. else if(Lane == DSI_DATA_LANES)
  1495. {
  1496. /* High-Speed Transmission Delay on Data Lanes */
  1497. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;
  1498. hdsi->Instance->WPCR[1] |= Value<<2;
  1499. }
  1500. break;
  1501. default:
  1502. break;
  1503. }
  1504. /* Process unlocked */
  1505. __HAL_UNLOCK(hdsi);
  1506. return HAL_OK;
  1507. }
  1508. /**
  1509. * @brief Low-Power Reception Filter Tuning
  1510. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1511. * the configuration information for the DSI.
  1512. * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
  1513. * @retval HAL status
  1514. */
  1515. HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
  1516. {
  1517. /* Process locked */
  1518. __HAL_LOCK(hdsi);
  1519. /* Low-Power RX low-pass Filtering Tuning */
  1520. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT;
  1521. hdsi->Instance->WPCR[1] |= Frequency<<25;
  1522. /* Process unlocked */
  1523. __HAL_UNLOCK(hdsi);
  1524. return HAL_OK;
  1525. }
  1526. /**
  1527. * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
  1528. * defined in the MIPI D-PHY specification
  1529. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1530. * the configuration information for the DSI.
  1531. * @param State: ENABLE or DISABLE
  1532. * @retval HAL status
  1533. */
  1534. HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1535. {
  1536. /* Process locked */
  1537. __HAL_LOCK(hdsi);
  1538. /* Check function parameters */
  1539. assert_param(IS_FUNCTIONAL_STATE(State));
  1540. /* Activate/Disactivate additional current path on all lanes */
  1541. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC;
  1542. hdsi->Instance->WPCR[1] |= ((uint32_t)State << 12);
  1543. /* Process unlocked */
  1544. __HAL_UNLOCK(hdsi);
  1545. return HAL_OK;
  1546. }
  1547. /**
  1548. * @brief Custom lane pins configuration
  1549. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1550. * the configuration information for the DSI.
  1551. * @param CustomLane: Function to be applyed on selected lane.
  1552. * This parameter can be any value of @ref DSI_CustomLane
  1553. * @param Lane: select between clock or data lane 0 or data lane 1.
  1554. * This parameter can be any value of @ref DSI_Lane_Select
  1555. * @param State: ENABLE or DISABLE
  1556. * @retval HAL status
  1557. */
  1558. HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
  1559. {
  1560. /* Process locked */
  1561. __HAL_LOCK(hdsi);
  1562. /* Check function parameters */
  1563. assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
  1564. assert_param(IS_DSI_LANE(Lane));
  1565. assert_param(IS_FUNCTIONAL_STATE(State));
  1566. switch(CustomLane)
  1567. {
  1568. case DSI_SWAP_LANE_PINS:
  1569. if(Lane == DSI_CLOCK_LANE)
  1570. {
  1571. /* Swap pins on clock lane */
  1572. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL;
  1573. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 6);
  1574. }
  1575. else if(Lane == DSI_DATA_LANE0)
  1576. {
  1577. /* Swap pins on data lane 0 */
  1578. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0;
  1579. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 7);
  1580. }
  1581. else if(Lane == DSI_DATA_LANE1)
  1582. {
  1583. /* Swap pins on data lane 1 */
  1584. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1;
  1585. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 8);
  1586. }
  1587. break;
  1588. case DSI_INVERT_HS_SIGNAL:
  1589. if(Lane == DSI_CLOCK_LANE)
  1590. {
  1591. /* Invert HS signal on clock lane */
  1592. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL;
  1593. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 9);
  1594. }
  1595. else if(Lane == DSI_DATA_LANE0)
  1596. {
  1597. /* Invert HS signal on data lane 0 */
  1598. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0;
  1599. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 10);
  1600. }
  1601. else if(Lane == DSI_DATA_LANE1)
  1602. {
  1603. /* Invert HS signal on data lane 1 */
  1604. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1;
  1605. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 11);
  1606. }
  1607. break;
  1608. default:
  1609. break;
  1610. }
  1611. /* Process unlocked */
  1612. __HAL_UNLOCK(hdsi);
  1613. return HAL_OK;
  1614. }
  1615. /**
  1616. * @brief Set custom timing for the PHY
  1617. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1618. * the configuration information for the DSI.
  1619. * @param Timing: PHY timing to be adjusted.
  1620. * This parameter can be any value of @ref DSI_PHY_Timing
  1621. * @param State: ENABLE or DISABLE
  1622. * @param Value: Custom value of the timing
  1623. * @retval HAL status
  1624. */
  1625. HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
  1626. {
  1627. /* Process locked */
  1628. __HAL_LOCK(hdsi);
  1629. /* Check function parameters */
  1630. assert_param(IS_DSI_PHY_TIMING(Timing));
  1631. assert_param(IS_FUNCTIONAL_STATE(State));
  1632. switch(Timing)
  1633. {
  1634. case DSI_TCLK_POST:
  1635. /* Enable/Disable custom timing setting */
  1636. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;
  1637. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 27);
  1638. if(State)
  1639. {
  1640. /* Set custom value */
  1641. hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;
  1642. hdsi->Instance->WPCR[4] |= Value & DSI_WPCR4_TCLKPOST;
  1643. }
  1644. break;
  1645. case DSI_TLPX_CLK:
  1646. /* Enable/Disable custom timing setting */
  1647. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;
  1648. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 26);
  1649. if(State)
  1650. {
  1651. /* Set custom value */
  1652. hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC;
  1653. hdsi->Instance->WPCR[3] |= (Value << 24) & DSI_WPCR3_TLPXC;
  1654. }
  1655. break;
  1656. case DSI_THS_EXIT:
  1657. /* Enable/Disable custom timing setting */
  1658. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;
  1659. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 25);
  1660. if(State)
  1661. {
  1662. /* Set custom value */
  1663. hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT;
  1664. hdsi->Instance->WPCR[3] |= (Value << 16) & DSI_WPCR3_THSEXIT;
  1665. }
  1666. break;
  1667. case DSI_TLPX_DATA:
  1668. /* Enable/Disable custom timing setting */
  1669. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;
  1670. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 24);
  1671. if(State)
  1672. {
  1673. /* Set custom value */
  1674. hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD;
  1675. hdsi->Instance->WPCR[3] |= (Value << 8) & DSI_WPCR3_TLPXD;
  1676. }
  1677. break;
  1678. case DSI_THS_ZERO:
  1679. /* Enable/Disable custom timing setting */
  1680. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;
  1681. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 23);
  1682. if(State)
  1683. {
  1684. /* Set custom value */
  1685. hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO;
  1686. hdsi->Instance->WPCR[3] |= Value & DSI_WPCR3_THSZERO;
  1687. }
  1688. break;
  1689. case DSI_THS_TRAIL:
  1690. /* Enable/Disable custom timing setting */
  1691. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;
  1692. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 22);
  1693. if(State)
  1694. {
  1695. /* Set custom value */
  1696. hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;
  1697. hdsi->Instance->WPCR[2] |= (Value << 24) & DSI_WPCR2_THSTRAIL;
  1698. }
  1699. break;
  1700. case DSI_THS_PREPARE:
  1701. /* Enable/Disable custom timing setting */
  1702. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;
  1703. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 21);
  1704. if(State)
  1705. {
  1706. /* Set custom value */
  1707. hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP;
  1708. hdsi->Instance->WPCR[2] |= (Value << 16) & DSI_WPCR2_THSPREP;
  1709. }
  1710. break;
  1711. case DSI_TCLK_ZERO:
  1712. /* Enable/Disable custom timing setting */
  1713. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;
  1714. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 20);
  1715. if(State)
  1716. {
  1717. /* Set custom value */
  1718. hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;
  1719. hdsi->Instance->WPCR[2] |= (Value << 8) & DSI_WPCR2_TCLKZERO;
  1720. }
  1721. break;
  1722. case DSI_TCLK_PREPARE:
  1723. /* Enable/Disable custom timing setting */
  1724. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;
  1725. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 19);
  1726. if(State)
  1727. {
  1728. /* Set custom value */
  1729. hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;
  1730. hdsi->Instance->WPCR[2] |= Value & DSI_WPCR2_TCLKPREP;
  1731. }
  1732. break;
  1733. default:
  1734. break;
  1735. }
  1736. /* Process unlocked */
  1737. __HAL_UNLOCK(hdsi);
  1738. return HAL_OK;
  1739. }
  1740. /**
  1741. * @brief Force the Clock/Data Lane in TX Stop Mode
  1742. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1743. * the configuration information for the DSI.
  1744. * @param Lane: select between clock or data lanes.
  1745. * This parameter can be any value of @ref DSI_Lane_Group
  1746. * @param State: ENABLE or DISABLE
  1747. * @retval HAL status
  1748. */
  1749. HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
  1750. {
  1751. /* Process locked */
  1752. __HAL_LOCK(hdsi);
  1753. /* Check function parameters */
  1754. assert_param(IS_DSI_LANE_GROUP(Lane));
  1755. assert_param(IS_FUNCTIONAL_STATE(State));
  1756. if(Lane == DSI_CLOCK_LANE)
  1757. {
  1758. /* Force/Unforce the Clock Lane in TX Stop Mode */
  1759. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;
  1760. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 12);
  1761. }
  1762. else if(Lane == DSI_DATA_LANES)
  1763. {
  1764. /* Force/Unforce the Data Lanes in TX Stop Mode */
  1765. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;
  1766. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 13);
  1767. }
  1768. /* Process unlocked */
  1769. __HAL_UNLOCK(hdsi);
  1770. return HAL_OK;
  1771. }
  1772. /**
  1773. * @brief Forces LP Receiver in Low-Power Mode
  1774. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1775. * the configuration information for the DSI.
  1776. * @param State: ENABLE or DISABLE
  1777. * @retval HAL status
  1778. */
  1779. HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1780. {
  1781. /* Process locked */
  1782. __HAL_LOCK(hdsi);
  1783. /* Check function parameters */
  1784. assert_param(IS_FUNCTIONAL_STATE(State));
  1785. /* Force/Unforce LP Receiver in Low-Power Mode */
  1786. hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;
  1787. hdsi->Instance->WPCR[1] |= ((uint32_t)State << 22);
  1788. /* Process unlocked */
  1789. __HAL_UNLOCK(hdsi);
  1790. return HAL_OK;
  1791. }
  1792. /**
  1793. * @brief Force Data Lanes in RX Mode after a BTA
  1794. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1795. * the configuration information for the DSI.
  1796. * @param State: ENABLE or DISABLE
  1797. * @retval HAL status
  1798. */
  1799. HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1800. {
  1801. /* Process locked */
  1802. __HAL_LOCK(hdsi);
  1803. /* Check function parameters */
  1804. assert_param(IS_FUNCTIONAL_STATE(State));
  1805. /* Force Data Lanes in RX Mode */
  1806. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL;
  1807. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 16);
  1808. /* Process unlocked */
  1809. __HAL_UNLOCK(hdsi);
  1810. return HAL_OK;
  1811. }
  1812. /**
  1813. * @brief Enable a pull-down on the lanes to prevent from floating states when unused
  1814. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1815. * the configuration information for the DSI.
  1816. * @param State: ENABLE or DISABLE
  1817. * @retval HAL status
  1818. */
  1819. HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1820. {
  1821. /* Process locked */
  1822. __HAL_LOCK(hdsi);
  1823. /* Check function parameters */
  1824. assert_param(IS_FUNCTIONAL_STATE(State));
  1825. /* Enable/Disable pull-down on lanes */
  1826. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN;
  1827. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 18);
  1828. /* Process unlocked */
  1829. __HAL_UNLOCK(hdsi);
  1830. return HAL_OK;
  1831. }
  1832. /**
  1833. * @brief Switch off the contention detection on data lanes
  1834. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1835. * the configuration information for the DSI.
  1836. * @param State: ENABLE or DISABLE
  1837. * @retval HAL status
  1838. */
  1839. HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1840. {
  1841. /* Process locked */
  1842. __HAL_LOCK(hdsi);
  1843. /* Check function parameters */
  1844. assert_param(IS_FUNCTIONAL_STATE(State));
  1845. /* Contention Detection on Data Lanes OFF */
  1846. hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;
  1847. hdsi->Instance->WPCR[0] |= ((uint32_t)State << 14);
  1848. /* Process unlocked */
  1849. __HAL_UNLOCK(hdsi);
  1850. return HAL_OK;
  1851. }
  1852. /**
  1853. * @}
  1854. */
  1855. /** @defgroup DSI_Group4 Peripheral State and Errors functions
  1856. * @brief Peripheral State and Errors functions
  1857. *
  1858. @verbatim
  1859. ===============================================================================
  1860. ##### Peripheral State and Errors functions #####
  1861. ===============================================================================
  1862. [..]
  1863. This subsection provides functions allowing to
  1864. (+) Check the DSI state.
  1865. (+) Get error code.
  1866. @endverbatim
  1867. * @{
  1868. */
  1869. /**
  1870. * @brief Return the DSI state
  1871. * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
  1872. * the configuration information for the DSI.
  1873. * @retval HAL state
  1874. */
  1875. HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
  1876. {
  1877. return hdsi->State;
  1878. }
  1879. /**
  1880. * @}
  1881. */
  1882. /**
  1883. * @}
  1884. */
  1885. #endif /*STM32F769xx | STM32F779xx */
  1886. #endif /* HAL_DSI_MODULE_ENABLED */
  1887. /**
  1888. * @}
  1889. */
  1890. /**
  1891. * @}
  1892. */
  1893. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/