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  1. /**
  2. ******************************************************************************
  3. * @file stm32f7xx_hal_rcc.c
  4. * @author MCD Application Team
  5. * @version V1.2.2
  6. * @date 14-April-2017
  7. * @brief RCC HAL module driver.
  8. * This file provides firmware functions to manage the following
  9. * functionalities of the Reset and Clock Control (RCC) peripheral:
  10. * + Initialization and de-initialization functions
  11. * + Peripheral Control functions
  12. *
  13. @verbatim
  14. ==============================================================================
  15. ##### RCC specific features #####
  16. ==============================================================================
  17. [..]
  18. After reset the device is running from Internal High Speed oscillator
  19. (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
  20. and I-Cache are disabled, and all peripherals are off except internal
  21. SRAM, Flash and JTAG.
  22. (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
  23. all peripherals mapped on these busses are running at HSI speed.
  24. (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
  25. (+) All GPIOs are in input floating state, except the JTAG pins which
  26. are assigned to be used for debug purpose.
  27. [..]
  28. Once the device started from reset, the user application has to:
  29. (+) Configure the clock source to be used to drive the System clock
  30. (if the application needs higher frequency/performance)
  31. (+) Configure the System clock frequency and Flash settings
  32. (+) Configure the AHB and APB busses prescalers
  33. (+) Enable the clock for the peripheral(s) to be used
  34. (+) Configure the clock source(s) for peripherals which clocks are not
  35. derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
  36. ##### RCC Limitations #####
  37. ==============================================================================
  38. [..]
  39. A delay between an RCC peripheral clock enable and the effective peripheral
  40. enabling should be taken into account in order to manage the peripheral read/write
  41. from/to registers.
  42. (+) This delay depends on the peripheral mapping.
  43. (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
  44. after the clock enable bit is set on the hardware register
  45. (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
  46. after the clock enable bit is set on the hardware register
  47. [..]
  48. Implemented Workaround:
  49. (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
  50. inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
  51. @endverbatim
  52. ******************************************************************************
  53. * @attention
  54. *
  55. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  56. *
  57. * Redistribution and use in source and binary forms, with or without modification,
  58. * are permitted provided that the following conditions are met:
  59. * 1. Redistributions of source code must retain the above copyright notice,
  60. * this list of conditions and the following disclaimer.
  61. * 2. Redistributions in binary form must reproduce the above copyright notice,
  62. * this list of conditions and the following disclaimer in the documentation
  63. * and/or other materials provided with the distribution.
  64. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  65. * may be used to endorse or promote products derived from this software
  66. * without specific prior written permission.
  67. *
  68. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  69. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  70. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  71. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  72. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  73. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  74. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  75. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  76. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  77. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  78. *
  79. ******************************************************************************
  80. */
  81. /* Includes ------------------------------------------------------------------*/
  82. #include "stm32f7xx_hal.h"
  83. /** @addtogroup STM32F7xx_HAL_Driver
  84. * @{
  85. */
  86. /** @defgroup RCC RCC
  87. * @brief RCC HAL module driver
  88. * @{
  89. */
  90. #ifdef HAL_RCC_MODULE_ENABLED
  91. /* Private typedef -----------------------------------------------------------*/
  92. /* Private define ------------------------------------------------------------*/
  93. /* Private macro -------------------------------------------------------------*/
  94. /** @defgroup RCC_Private_Macros RCC Private Macros
  95. * @{
  96. */
  97. #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
  98. #define MCO1_GPIO_PORT GPIOA
  99. #define MCO1_PIN GPIO_PIN_8
  100. #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
  101. #define MCO2_GPIO_PORT GPIOC
  102. #define MCO2_PIN GPIO_PIN_9
  103. /**
  104. * @}
  105. */
  106. /* Private variables ---------------------------------------------------------*/
  107. /** @defgroup RCC_Private_Variables RCC Private Variables
  108. * @{
  109. */
  110. /**
  111. * @}
  112. */
  113. /* Private function prototypes -----------------------------------------------*/
  114. /* Exported functions ---------------------------------------------------------*/
  115. /** @defgroup RCC_Exported_Functions RCC Exported Functions
  116. * @{
  117. */
  118. /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
  119. * @brief Initialization and Configuration functions
  120. *
  121. @verbatim
  122. ===============================================================================
  123. ##### Initialization and de-initialization functions #####
  124. ===============================================================================
  125. [..]
  126. This section provides functions allowing to configure the internal/external oscillators
  127. (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
  128. and APB2).
  129. [..] Internal/external clock and PLL configuration
  130. (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
  131. the PLL as System clock source.
  132. (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
  133. clock source.
  134. (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
  135. through the PLL as System clock source. Can be used also as RTC clock source.
  136. (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
  137. (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
  138. (++) The first output is used to generate the high speed system clock (up to 216 MHz)
  139. (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
  140. the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
  141. (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
  142. and if a HSE clock failure occurs(HSE used directly or through PLL as System
  143. clock source), the System clock is automatically switched to HSI and an interrupt
  144. is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
  145. (Non-Maskable Interrupt) exception vector.
  146. (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
  147. clock (through a configurable prescaler) on PA8 pin.
  148. (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
  149. clock (through a configurable prescaler) on PC9 pin.
  150. [..] System, AHB and APB busses clocks configuration
  151. (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
  152. HSE and PLL.
  153. The AHB clock (HCLK) is derived from System clock through configurable
  154. prescaler and used to clock the CPU, memory and peripherals mapped
  155. on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
  156. from AHB clock through configurable prescalers and used to clock
  157. the peripherals mapped on these busses. You can use
  158. "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
  159. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
  160. (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
  161. from an external clock mapped on the I2S_CKIN pin.
  162. You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
  163. (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
  164. from an external clock mapped on the I2S_CKIN pin.
  165. You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
  166. (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
  167. divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
  168. macros to configure this clock.
  169. (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
  170. to work correctly, while the SDIO require a frequency equal or lower than
  171. to 48. This clock is derived of the main PLL through PLLQ divider.
  172. (+@) IWDG clock which is always the LSI clock.
  173. @endverbatim
  174. * @{
  175. */
  176. /**
  177. * @brief Resets the RCC clock configuration to the default reset state.
  178. * @note The default reset state of the clock configuration is given below:
  179. * - HSI ON and used as system clock source
  180. * - HSE, PLL and PLLI2S OFF
  181. * - AHB, APB1 and APB2 prescaler set to 1.
  182. * - CSS, MCO1 and MCO2 OFF
  183. * - All interrupts disabled
  184. * @note This function doesn't modify the configuration of the
  185. * - Peripheral clocks
  186. * - LSI, LSE and RTC clocks
  187. * @retval None
  188. */
  189. void HAL_RCC_DeInit(void)
  190. {
  191. /* Set HSION bit */
  192. SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
  193. /* Reset CFGR register */
  194. CLEAR_REG(RCC->CFGR);
  195. /* Reset HSEON, CSSON, PLLON, PLLI2S */
  196. CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
  197. /* Reset PLLCFGR register */
  198. CLEAR_REG(RCC->PLLCFGR);
  199. SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U));
  200. /* Reset PLLI2SCFGR register */
  201. CLEAR_REG(RCC->PLLI2SCFGR);
  202. SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
  203. /* Reset HSEBYP bit */
  204. CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
  205. /* Disable all interrupts */
  206. CLEAR_REG(RCC->CIR);
  207. /* Update the SystemCoreClock global variable */
  208. SystemCoreClock = HSI_VALUE;
  209. }
  210. /**
  211. * @brief Initializes the RCC Oscillators according to the specified parameters in the
  212. * RCC_OscInitTypeDef.
  213. * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
  214. * contains the configuration information for the RCC Oscillators.
  215. * @note The PLL is not disabled when used as system clock.
  216. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
  217. * supported by this function. User should request a transition to LSE Off
  218. * first and then LSE On or LSE Bypass.
  219. * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
  220. * supported by this function. User should request a transition to HSE Off
  221. * first and then HSE On or HSE Bypass.
  222. * @retval HAL status
  223. */
  224. HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
  225. {
  226. uint32_t tickstart = 0;
  227. FlagStatus pwrclkchanged = RESET;
  228. /* Check the parameters */
  229. assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  230. /*------------------------------- HSE Configuration ------------------------*/
  231. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  232. {
  233. /* Check the parameters */
  234. assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
  235. /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
  236. if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
  237. || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
  238. {
  239. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  240. {
  241. return HAL_ERROR;
  242. }
  243. }
  244. else
  245. {
  246. /* Set the new HSE configuration ---------------------------------------*/
  247. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  248. /* Check the HSE State */
  249. if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
  250. {
  251. /* Get Start Tick*/
  252. tickstart = HAL_GetTick();
  253. /* Wait till HSE is ready */
  254. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  255. {
  256. if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  257. {
  258. return HAL_TIMEOUT;
  259. }
  260. }
  261. }
  262. else
  263. {
  264. /* Get Start Tick*/
  265. tickstart = HAL_GetTick();
  266. /* Wait till HSE is bypassed or disabled */
  267. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
  268. {
  269. if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  270. {
  271. return HAL_TIMEOUT;
  272. }
  273. }
  274. }
  275. }
  276. }
  277. /*----------------------------- HSI Configuration --------------------------*/
  278. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
  279. {
  280. /* Check the parameters */
  281. assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
  282. assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
  283. /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
  284. if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
  285. || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
  286. {
  287. /* When HSI is used as system clock it will not disabled */
  288. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
  289. {
  290. return HAL_ERROR;
  291. }
  292. /* Otherwise, just the calibration is allowed */
  293. else
  294. {
  295. /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  296. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  297. }
  298. }
  299. else
  300. {
  301. /* Check the HSI State */
  302. if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
  303. {
  304. /* Enable the Internal High Speed oscillator (HSI). */
  305. __HAL_RCC_HSI_ENABLE();
  306. /* Get Start Tick*/
  307. tickstart = HAL_GetTick();
  308. /* Wait till HSI is ready */
  309. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  310. {
  311. if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  312. {
  313. return HAL_TIMEOUT;
  314. }
  315. }
  316. /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  317. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  318. }
  319. else
  320. {
  321. /* Disable the Internal High Speed oscillator (HSI). */
  322. __HAL_RCC_HSI_DISABLE();
  323. /* Get Start Tick*/
  324. tickstart = HAL_GetTick();
  325. /* Wait till HSI is ready */
  326. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
  327. {
  328. if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  329. {
  330. return HAL_TIMEOUT;
  331. }
  332. }
  333. }
  334. }
  335. }
  336. /*------------------------------ LSI Configuration -------------------------*/
  337. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  338. {
  339. /* Check the parameters */
  340. assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
  341. /* Check the LSI State */
  342. if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
  343. {
  344. /* Enable the Internal Low Speed oscillator (LSI). */
  345. __HAL_RCC_LSI_ENABLE();
  346. /* Get Start Tick*/
  347. tickstart = HAL_GetTick();
  348. /* Wait till LSI is ready */
  349. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
  350. {
  351. if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  352. {
  353. return HAL_TIMEOUT;
  354. }
  355. }
  356. }
  357. else
  358. {
  359. /* Disable the Internal Low Speed oscillator (LSI). */
  360. __HAL_RCC_LSI_DISABLE();
  361. /* Get Start Tick*/
  362. tickstart = HAL_GetTick();
  363. /* Wait till LSI is ready */
  364. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
  365. {
  366. if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  367. {
  368. return HAL_TIMEOUT;
  369. }
  370. }
  371. }
  372. }
  373. /*------------------------------ LSE Configuration -------------------------*/
  374. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
  375. {
  376. /* Check the parameters */
  377. assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
  378. /* Update LSE configuration in Backup Domain control register */
  379. /* Requires to enable write access to Backup Domain of necessary */
  380. if(__HAL_RCC_PWR_IS_CLK_DISABLED())
  381. {
  382. /* Enable Power Clock*/
  383. __HAL_RCC_PWR_CLK_ENABLE();
  384. pwrclkchanged = SET;
  385. }
  386. if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
  387. {
  388. /* Enable write access to Backup domain */
  389. PWR->CR1 |= PWR_CR1_DBP;
  390. /* Wait for Backup domain Write protection disable */
  391. tickstart = HAL_GetTick();
  392. while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
  393. {
  394. if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
  395. {
  396. return HAL_TIMEOUT;
  397. }
  398. }
  399. }
  400. /* Set the new LSE configuration -----------------------------------------*/
  401. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  402. /* Check the LSE State */
  403. if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
  404. {
  405. /* Get Start Tick*/
  406. tickstart = HAL_GetTick();
  407. /* Wait till LSE is ready */
  408. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
  409. {
  410. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  411. {
  412. return HAL_TIMEOUT;
  413. }
  414. }
  415. }
  416. else
  417. {
  418. /* Get Start Tick*/
  419. tickstart = HAL_GetTick();
  420. /* Wait till LSE is ready */
  421. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
  422. {
  423. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  424. {
  425. return HAL_TIMEOUT;
  426. }
  427. }
  428. }
  429. /* Restore clock configuration if changed */
  430. if(pwrclkchanged == SET)
  431. {
  432. __HAL_RCC_PWR_CLK_DISABLE();
  433. }
  434. }
  435. /*-------------------------------- PLL Configuration -----------------------*/
  436. /* Check the parameters */
  437. assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  438. if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
  439. {
  440. /* Check if the PLL is used as system clock or not */
  441. if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  442. {
  443. if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  444. {
  445. /* Check the parameters */
  446. assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
  447. assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
  448. assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
  449. assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
  450. assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
  451. #if defined (RCC_PLLCFGR_PLLR)
  452. assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
  453. #endif
  454. /* Disable the main PLL. */
  455. __HAL_RCC_PLL_DISABLE();
  456. /* Get Start Tick*/
  457. tickstart = HAL_GetTick();
  458. /* Wait till PLL is ready */
  459. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
  460. {
  461. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  462. {
  463. return HAL_TIMEOUT;
  464. }
  465. }
  466. /* Configure the main PLL clock source, multiplication and division factors. */
  467. #if defined (RCC_PLLCFGR_PLLR)
  468. __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  469. RCC_OscInitStruct->PLL.PLLM,
  470. RCC_OscInitStruct->PLL.PLLN,
  471. RCC_OscInitStruct->PLL.PLLP,
  472. RCC_OscInitStruct->PLL.PLLQ,
  473. RCC_OscInitStruct->PLL.PLLR);
  474. #else
  475. __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  476. RCC_OscInitStruct->PLL.PLLM,
  477. RCC_OscInitStruct->PLL.PLLN,
  478. RCC_OscInitStruct->PLL.PLLP,
  479. RCC_OscInitStruct->PLL.PLLQ);
  480. #endif
  481. /* Enable the main PLL. */
  482. __HAL_RCC_PLL_ENABLE();
  483. /* Get Start Tick*/
  484. tickstart = HAL_GetTick();
  485. /* Wait till PLL is ready */
  486. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
  487. {
  488. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  489. {
  490. return HAL_TIMEOUT;
  491. }
  492. }
  493. }
  494. else
  495. {
  496. /* Disable the main PLL. */
  497. __HAL_RCC_PLL_DISABLE();
  498. /* Get Start Tick*/
  499. tickstart = HAL_GetTick();
  500. /* Wait till PLL is ready */
  501. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
  502. {
  503. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  504. {
  505. return HAL_TIMEOUT;
  506. }
  507. }
  508. }
  509. }
  510. else
  511. {
  512. return HAL_ERROR;
  513. }
  514. }
  515. return HAL_OK;
  516. }
  517. /**
  518. * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
  519. * parameters in the RCC_ClkInitStruct.
  520. * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
  521. * contains the configuration information for the RCC peripheral.
  522. * @param FLatency: FLASH Latency, this parameter depend on device selected
  523. *
  524. * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  525. * and updated by HAL_RCC_GetHCLKFreq() function called within this function
  526. *
  527. * @note The HSI is used (enabled by hardware) as system clock source after
  528. * startup from Reset, wake-up from STOP and STANDBY mode, or in case
  529. * of failure of the HSE used directly or indirectly as system clock
  530. * (if the Clock Security System CSS is enabled).
  531. *
  532. * @note A switch from one clock source to another occurs only if the target
  533. * clock source is ready (clock stable after startup delay or PLL locked).
  534. * If a clock source which is not yet ready is selected, the switch will
  535. * occur when the clock source will be ready.
  536. * You can use HAL_RCC_GetClockConfig() function to know which clock is
  537. * currently used as system clock source.
  538. * @note Depending on the device voltage range, the software has to set correctly
  539. * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  540. * (for more details refer to section above "Initialization/de-initialization functions")
  541. * @retval None
  542. */
  543. HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
  544. {
  545. uint32_t tickstart = 0;
  546. /* Check the parameters */
  547. assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
  548. assert_param(IS_FLASH_LATENCY(FLatency));
  549. /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  550. must be correctly programmed according to the frequency of the CPU clock
  551. (HCLK) and the supply voltage of the device. */
  552. /* Increasing the CPU frequency */
  553. if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
  554. {
  555. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  556. __HAL_FLASH_SET_LATENCY(FLatency);
  557. /* Check that the new number of wait states is taken into account to access the Flash
  558. memory by reading the FLASH_ACR register */
  559. if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
  560. {
  561. return HAL_ERROR;
  562. }
  563. }
  564. /*-------------------------- HCLK Configuration --------------------------*/
  565. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  566. {
  567. assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
  568. MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  569. }
  570. /*------------------------- SYSCLK Configuration ---------------------------*/
  571. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  572. {
  573. assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
  574. /* HSE is selected as System Clock Source */
  575. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  576. {
  577. /* Check the HSE ready flag */
  578. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  579. {
  580. return HAL_ERROR;
  581. }
  582. }
  583. /* PLL is selected as System Clock Source */
  584. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  585. {
  586. /* Check the PLL ready flag */
  587. if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
  588. {
  589. return HAL_ERROR;
  590. }
  591. }
  592. /* HSI is selected as System Clock Source */
  593. else
  594. {
  595. /* Check the HSI ready flag */
  596. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  597. {
  598. return HAL_ERROR;
  599. }
  600. }
  601. __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
  602. /* Get Start Tick*/
  603. tickstart = HAL_GetTick();
  604. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  605. {
  606. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
  607. {
  608. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  609. {
  610. return HAL_TIMEOUT;
  611. }
  612. }
  613. }
  614. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  615. {
  616. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  617. {
  618. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  619. {
  620. return HAL_TIMEOUT;
  621. }
  622. }
  623. }
  624. else
  625. {
  626. while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
  627. {
  628. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  629. {
  630. return HAL_TIMEOUT;
  631. }
  632. }
  633. }
  634. }
  635. /* Decreasing the number of wait states because of lower CPU frequency */
  636. if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
  637. {
  638. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  639. __HAL_FLASH_SET_LATENCY(FLatency);
  640. /* Check that the new number of wait states is taken into account to access the Flash
  641. memory by reading the FLASH_ACR register */
  642. if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
  643. {
  644. return HAL_ERROR;
  645. }
  646. }
  647. /*-------------------------- PCLK1 Configuration ---------------------------*/
  648. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  649. {
  650. assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
  651. MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
  652. }
  653. /*-------------------------- PCLK2 Configuration ---------------------------*/
  654. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  655. {
  656. assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
  657. MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
  658. }
  659. /* Update the SystemCoreClock global variable */
  660. SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
  661. /* Configure the source of time base considering new system clocks settings*/
  662. HAL_InitTick (TICK_INT_PRIORITY);
  663. return HAL_OK;
  664. }
  665. /**
  666. * @}
  667. */
  668. /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
  669. * @brief RCC clocks control functions
  670. *
  671. @verbatim
  672. ===============================================================================
  673. ##### Peripheral Control functions #####
  674. ===============================================================================
  675. [..]
  676. This subsection provides a set of functions allowing to control the RCC Clocks
  677. frequencies.
  678. @endverbatim
  679. * @{
  680. */
  681. /**
  682. * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
  683. * @note PA8/PC9 should be configured in alternate function mode.
  684. * @param RCC_MCOx: specifies the output direction for the clock source.
  685. * This parameter can be one of the following values:
  686. * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
  687. * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
  688. * @param RCC_MCOSource: specifies the clock source to output.
  689. * This parameter can be one of the following values:
  690. * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  691. * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  692. * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  693. * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
  694. * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  695. * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
  696. * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  697. * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
  698. * @param RCC_MCODiv: specifies the MCOx prescaler.
  699. * This parameter can be one of the following values:
  700. * @arg RCC_MCODIV_1: no division applied to MCOx clock
  701. * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
  702. * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
  703. * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
  704. * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
  705. * @retval None
  706. */
  707. void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
  708. {
  709. GPIO_InitTypeDef GPIO_InitStruct;
  710. /* Check the parameters */
  711. assert_param(IS_RCC_MCO(RCC_MCOx));
  712. assert_param(IS_RCC_MCODIV(RCC_MCODiv));
  713. /* RCC_MCO1 */
  714. if(RCC_MCOx == RCC_MCO1)
  715. {
  716. assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
  717. /* MCO1 Clock Enable */
  718. MCO1_CLK_ENABLE();
  719. /* Configure the MCO1 pin in alternate function mode */
  720. GPIO_InitStruct.Pin = MCO1_PIN;
  721. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  722. GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
  723. GPIO_InitStruct.Pull = GPIO_NOPULL;
  724. GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
  725. HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
  726. /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
  727. MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
  728. }
  729. else
  730. {
  731. assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
  732. /* MCO2 Clock Enable */
  733. MCO2_CLK_ENABLE();
  734. /* Configure the MCO2 pin in alternate function mode */
  735. GPIO_InitStruct.Pin = MCO2_PIN;
  736. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  737. GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
  738. GPIO_InitStruct.Pull = GPIO_NOPULL;
  739. GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
  740. HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
  741. /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
  742. MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
  743. }
  744. }
  745. /**
  746. * @brief Enables the Clock Security System.
  747. * @note If a failure is detected on the HSE oscillator clock, this oscillator
  748. * is automatically disabled and an interrupt is generated to inform the
  749. * software about the failure (Clock Security System Interrupt, CSSI),
  750. * allowing the MCU to perform rescue operations. The CSSI is linked to
  751. * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
  752. * @retval None
  753. */
  754. void HAL_RCC_EnableCSS(void)
  755. {
  756. SET_BIT(RCC->CR, RCC_CR_CSSON);
  757. }
  758. /**
  759. * @brief Disables the Clock Security System.
  760. * @retval None
  761. */
  762. void HAL_RCC_DisableCSS(void)
  763. {
  764. CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
  765. }
  766. /**
  767. * @brief Returns the SYSCLK frequency
  768. *
  769. * @note The system frequency computed by this function is not the real
  770. * frequency in the chip. It is calculated based on the predefined
  771. * constant and the selected clock source:
  772. * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
  773. * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
  774. * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
  775. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
  776. * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
  777. * 16 MHz) but the real value may vary depending on the variations
  778. * in voltage and temperature.
  779. * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
  780. * 25 MHz), user has to ensure that HSE_VALUE is same as the real
  781. * frequency of the crystal used. Otherwise, this function may
  782. * have wrong result.
  783. *
  784. * @note The result of this function could be not correct when using fractional
  785. * value for HSE crystal.
  786. *
  787. * @note This function can be used by the user application to compute the
  788. * baudrate for the communication peripherals or configure other parameters.
  789. *
  790. * @note Each time SYSCLK changes, this function must be called to update the
  791. * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  792. *
  793. *
  794. * @retval SYSCLK frequency
  795. */
  796. uint32_t HAL_RCC_GetSysClockFreq(void)
  797. {
  798. uint32_t pllm = 0, pllvco = 0, pllp = 0;
  799. uint32_t sysclockfreq = 0;
  800. /* Get SYSCLK source -------------------------------------------------------*/
  801. switch (RCC->CFGR & RCC_CFGR_SWS)
  802. {
  803. case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
  804. {
  805. sysclockfreq = HSI_VALUE;
  806. break;
  807. }
  808. case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
  809. {
  810. sysclockfreq = HSE_VALUE;
  811. break;
  812. }
  813. case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
  814. {
  815. /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
  816. SYSCLK = PLL_VCO / PLLP */
  817. pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
  818. if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
  819. {
  820. /* HSE used as PLL clock source */
  821. //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
  822. // dpgeorge: Adjust the way the arithmetic is done so it retains
  823. // precision for the case that pllm doesn't evenly divide HSE_VALUE.
  824. // Must be sure not to overflow, so divide by 4 first. HSE_VALUE
  825. // should be a multiple of 4 (being a multiple of 100 is enough).
  826. pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
  827. }
  828. else
  829. {
  830. /* HSI used as PLL clock source */
  831. pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
  832. }
  833. pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
  834. sysclockfreq = pllvco/pllp;
  835. break;
  836. }
  837. default:
  838. {
  839. sysclockfreq = HSI_VALUE;
  840. break;
  841. }
  842. }
  843. return sysclockfreq;
  844. }
  845. /**
  846. * @brief Returns the HCLK frequency
  847. * @note Each time HCLK changes, this function must be called to update the
  848. * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
  849. * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
  850. * @retval HCLK frequency
  851. */
  852. uint32_t HAL_RCC_GetHCLKFreq(void)
  853. {
  854. return SystemCoreClock;
  855. }
  856. /**
  857. * @brief Returns the PCLK1 frequency
  858. * @note Each time PCLK1 changes, this function must be called to update the
  859. * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  860. * @retval PCLK1 frequency
  861. */
  862. uint32_t HAL_RCC_GetPCLK1Freq(void)
  863. {
  864. /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  865. return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
  866. }
  867. /**
  868. * @brief Returns the PCLK2 frequency
  869. * @note Each time PCLK2 changes, this function must be called to update the
  870. * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  871. * @retval PCLK2 frequency
  872. */
  873. uint32_t HAL_RCC_GetPCLK2Freq(void)
  874. {
  875. /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  876. return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
  877. }
  878. /**
  879. * @brief Configures the RCC_OscInitStruct according to the internal
  880. * RCC configuration registers.
  881. * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
  882. * will be configured.
  883. * @retval None
  884. */
  885. void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
  886. {
  887. /* Set all possible values for the Oscillator type parameter ---------------*/
  888. RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
  889. /* Get the HSE configuration -----------------------------------------------*/
  890. if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
  891. {
  892. RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
  893. }
  894. else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
  895. {
  896. RCC_OscInitStruct->HSEState = RCC_HSE_ON;
  897. }
  898. else
  899. {
  900. RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
  901. }
  902. /* Get the HSI configuration -----------------------------------------------*/
  903. if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
  904. {
  905. RCC_OscInitStruct->HSIState = RCC_HSI_ON;
  906. }
  907. else
  908. {
  909. RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
  910. }
  911. RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
  912. /* Get the LSE configuration -----------------------------------------------*/
  913. if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
  914. {
  915. RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
  916. }
  917. else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
  918. {
  919. RCC_OscInitStruct->LSEState = RCC_LSE_ON;
  920. }
  921. else
  922. {
  923. RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
  924. }
  925. /* Get the LSI configuration -----------------------------------------------*/
  926. if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
  927. {
  928. RCC_OscInitStruct->LSIState = RCC_LSI_ON;
  929. }
  930. else
  931. {
  932. RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
  933. }
  934. /* Get the PLL configuration -----------------------------------------------*/
  935. if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
  936. {
  937. RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
  938. }
  939. else
  940. {
  941. RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
  942. }
  943. RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
  944. RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
  945. RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
  946. RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
  947. RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
  948. }
  949. /**
  950. * @brief Configures the RCC_ClkInitStruct according to the internal
  951. * RCC configuration registers.
  952. * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
  953. * will be configured.
  954. * @param pFLatency: Pointer on the Flash Latency.
  955. * @retval None
  956. */
  957. void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
  958. {
  959. /* Set all possible values for the Clock type parameter --------------------*/
  960. RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
  961. /* Get the SYSCLK configuration --------------------------------------------*/
  962. RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
  963. /* Get the HCLK configuration ----------------------------------------------*/
  964. RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
  965. /* Get the APB1 configuration ----------------------------------------------*/
  966. RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
  967. /* Get the APB2 configuration ----------------------------------------------*/
  968. RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
  969. /* Get the Flash Wait State (Latency) configuration ------------------------*/
  970. *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
  971. }
  972. /**
  973. * @brief This function handles the RCC CSS interrupt request.
  974. * @note This API should be called under the NMI_Handler().
  975. * @retval None
  976. */
  977. void HAL_RCC_NMI_IRQHandler(void)
  978. {
  979. /* Check RCC CSSF flag */
  980. if(__HAL_RCC_GET_IT(RCC_IT_CSS))
  981. {
  982. /* RCC Clock Security System interrupt user callback */
  983. HAL_RCC_CSSCallback();
  984. /* Clear RCC CSS pending bit */
  985. __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
  986. }
  987. }
  988. /**
  989. * @brief RCC Clock Security System interrupt callback
  990. * @retval None
  991. */
  992. __weak void HAL_RCC_CSSCallback(void)
  993. {
  994. /* NOTE : This function Should not be modified, when the callback is needed,
  995. the HAL_RCC_CSSCallback could be implemented in the user file
  996. */
  997. }
  998. /**
  999. * @}
  1000. */
  1001. /**
  1002. * @}
  1003. */
  1004. #endif /* HAL_RCC_MODULE_ENABLED */
  1005. /**
  1006. * @}
  1007. */
  1008. /**
  1009. * @}
  1010. */
  1011. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/