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  1. /**
  2. ******************************************************************************
  3. * @file stm32f7xx_ll_utils.c
  4. * @author MCD Application Team
  5. * @version V1.2.2
  6. * @date 14-April-2017
  7. * @brief UTILS LL module driver.
  8. ******************************************************************************
  9. * @attention
  10. *
  11. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12. *
  13. * Redistribution and use in source and binary forms, with or without modification,
  14. * are permitted provided that the following conditions are met:
  15. * 1. Redistributions of source code must retain the above copyright notice,
  16. * this list of conditions and the following disclaimer.
  17. * 2. Redistributions in binary form must reproduce the above copyright notice,
  18. * this list of conditions and the following disclaimer in the documentation
  19. * and/or other materials provided with the distribution.
  20. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  21. * may be used to endorse or promote products derived from this software
  22. * without specific prior written permission.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. ******************************************************************************
  36. */
  37. /* Includes ------------------------------------------------------------------*/
  38. #include "stm32f7xx_ll_utils.h"
  39. #include "stm32f7xx_ll_rcc.h"
  40. #include "stm32f7xx_ll_system.h"
  41. #include "stm32f7xx_ll_pwr.h"
  42. #ifdef USE_FULL_ASSERT
  43. #include "stm32_assert.h"
  44. #else
  45. #define assert_param(expr) ((void)0U)
  46. #endif /* USE_FULL_ASSERT */
  47. /** @addtogroup STM32F7xx_LL_Driver
  48. * @{
  49. */
  50. /** @addtogroup UTILS_LL
  51. * @{
  52. */
  53. /* Private types -------------------------------------------------------------*/
  54. /* Private variables ---------------------------------------------------------*/
  55. /* Private constants ---------------------------------------------------------*/
  56. /** @addtogroup UTILS_LL_Private_Constants
  57. * @{
  58. */
  59. #define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
  60. #define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
  61. #define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
  62. /* Defines used for PLL range */
  63. #define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
  64. #define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
  65. #define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
  66. #define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
  67. /* Defines used for HSE range */
  68. #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
  69. #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
  70. /* Defines used for FLASH latency according to HCLK Frequency */
  71. #define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
  72. #define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
  73. #define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
  74. #define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
  75. #define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
  76. #define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 with over-drive mode */
  77. #define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 with over-drive mode */
  78. #define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
  79. #define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
  80. #define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
  81. #define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
  82. #define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
  83. #define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
  84. #define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
  85. #define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
  86. #define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
  87. /**
  88. * @}
  89. */
  90. /* Private macros ------------------------------------------------------------*/
  91. /** @addtogroup UTILS_LL_Private_Macros
  92. * @{
  93. */
  94. #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
  95. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
  96. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
  97. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
  98. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
  99. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
  100. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
  101. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
  102. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
  103. #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
  104. || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
  105. || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
  106. || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
  107. || ((__VALUE__) == LL_RCC_APB1_DIV_16))
  108. #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
  109. || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
  110. || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
  111. || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
  112. || ((__VALUE__) == LL_RCC_APB2_DIV_16))
  113. #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
  114. || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
  115. || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
  116. || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
  117. || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
  118. || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
  119. || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
  120. || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
  121. || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
  122. || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
  123. || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
  124. || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
  125. || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
  126. || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
  127. || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
  128. || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
  129. || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
  130. || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
  131. || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
  132. || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
  133. || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
  134. || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
  135. || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
  136. || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
  137. || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
  138. || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
  139. || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
  140. || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
  141. || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
  142. || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
  143. || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
  144. || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
  145. || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
  146. || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
  147. || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
  148. || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
  149. || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
  150. || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
  151. || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
  152. || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
  153. || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
  154. || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
  155. || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
  156. || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
  157. || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
  158. || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
  159. || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
  160. || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
  161. || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
  162. || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
  163. || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
  164. || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
  165. || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
  166. || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
  167. || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
  168. || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
  169. || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
  170. || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
  171. || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
  172. || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
  173. || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
  174. || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
  175. #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432))
  176. #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
  177. || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
  178. || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
  179. || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
  180. #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
  181. #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
  182. #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
  183. (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
  184. ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
  185. #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
  186. || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
  187. #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
  188. /**
  189. * @}
  190. */
  191. /* Private function prototypes -----------------------------------------------*/
  192. /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
  193. * @{
  194. */
  195. static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
  196. LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
  197. static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
  198. static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
  199. static ErrorStatus UTILS_PLL_IsBusy(void);
  200. /**
  201. * @}
  202. */
  203. /* Exported functions --------------------------------------------------------*/
  204. /** @addtogroup UTILS_LL_Exported_Functions
  205. * @{
  206. */
  207. /** @addtogroup UTILS_LL_EF_DELAY
  208. * @{
  209. */
  210. /**
  211. * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
  212. * @note When a RTOS is used, it is recommended to avoid changing the Systick
  213. * configuration by calling this function, for a delay use rather osDelay RTOS service.
  214. * @param HCLKFrequency HCLK frequency in Hz
  215. * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
  216. * @retval None
  217. */
  218. void LL_Init1msTick(uint32_t HCLKFrequency)
  219. {
  220. /* Use frequency provided in argument */
  221. LL_InitTick(HCLKFrequency, 1000U);
  222. }
  223. /**
  224. * @brief This function provides accurate delay (in milliseconds) based
  225. * on SysTick counter flag
  226. * @note When a RTOS is used, it is recommended to avoid using blocking delay
  227. * and use rather osDelay service.
  228. * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
  229. * will configure Systick to 1ms
  230. * @param Delay specifies the delay time length, in milliseconds.
  231. * @retval None
  232. */
  233. void LL_mDelay(uint32_t Delay)
  234. {
  235. __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
  236. /* Add this code to indicate that local variable is not used */
  237. ((void)tmp);
  238. /* Add a period to guaranty minimum wait */
  239. if(Delay < LL_MAX_DELAY)
  240. {
  241. Delay++;
  242. }
  243. while (Delay)
  244. {
  245. if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
  246. {
  247. Delay--;
  248. }
  249. }
  250. }
  251. /**
  252. * @}
  253. */
  254. /** @addtogroup UTILS_EF_SYSTEM
  255. * @brief System Configuration functions
  256. *
  257. @verbatim
  258. ===============================================================================
  259. ##### System Configuration functions #####
  260. ===============================================================================
  261. [..]
  262. System, AHB and APB buses clocks configuration
  263. (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz.
  264. @endverbatim
  265. @internal
  266. Depending on the device voltage range, the maximum frequency should be
  267. adapted accordingly:
  268. (++) +------------------------------------------------------------------------------------------------+
  269. (++) | Wait states | HCLK clock frequency (MHz) |
  270. (++) | |-------------------------------------------------------------------------------|
  271. (++) | (Latency) | voltage range | voltage range | voltage range | voltage range |
  272. (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | 1.8V - 2.1V |
  273. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  274. (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | 0 < HCLK <= 20 |
  275. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  276. (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 20 < HCLK <= 44 |
  277. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  278. (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 40 < HCLK <= 60 |
  279. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  280. (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 60 < HCLK <= 80 |
  281. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  282. (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 80 < HCLK <= 100 |
  283. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  284. (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 |
  285. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  286. (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 |
  287. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  288. (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 |
  289. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  290. (++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 |
  291. (++) |----------------|-------------------|-------------------|-------------------|-------------------|
  292. (++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | -- |
  293. (++) +------------------------------------------------------------------------------------------------+
  294. @endinternal
  295. * @{
  296. */
  297. /**
  298. * @brief This function sets directly SystemCoreClock CMSIS variable.
  299. * @note Variable can be calculated also through SystemCoreClockUpdate function.
  300. * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
  301. * @retval None
  302. */
  303. void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
  304. {
  305. /* HCLK clock frequency */
  306. SystemCoreClock = HCLKFrequency;
  307. }
  308. /**
  309. * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
  310. * @note The application need to ensure that PLL is disabled.
  311. * @note Function is based on the following formula:
  312. * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
  313. * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM)
  314. * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  315. * - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP)
  316. * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  317. * the configuration information for the PLL.
  318. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  319. * the configuration information for the BUS prescalers.
  320. * @retval An ErrorStatus enumeration value:
  321. * - SUCCESS: Max frequency configuration done
  322. * - ERROR: Max frequency configuration not done
  323. */
  324. ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
  325. LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  326. {
  327. ErrorStatus status = SUCCESS;
  328. uint32_t pllfreq = 0U;
  329. /* Check if one of the PLL is enabled */
  330. if(UTILS_PLL_IsBusy() == SUCCESS)
  331. {
  332. /* Calculate the new PLL output frequency */
  333. pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
  334. /* Enable HSI if not enabled */
  335. if(LL_RCC_HSI_IsReady() != 1U)
  336. {
  337. LL_RCC_HSI_Enable();
  338. while (LL_RCC_HSI_IsReady() != 1U)
  339. {
  340. /* Wait for HSI ready */
  341. }
  342. }
  343. /* Configure PLL */
  344. LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
  345. UTILS_PLLInitStruct->PLLP);
  346. /* Enable PLL and switch system clock to PLL */
  347. status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  348. }
  349. else
  350. {
  351. /* Current PLL configuration cannot be modified */
  352. status = ERROR;
  353. }
  354. return status;
  355. }
  356. /**
  357. * @brief This function configures system clock with HSE as clock source of the PLL
  358. * @note The application need to ensure that PLL is disabled.
  359. * @note Function is based on the following formula:
  360. * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
  361. * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
  362. * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  363. * - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP)
  364. * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
  365. * @param HSEBypass This parameter can be one of the following values:
  366. * @arg @ref LL_UTILS_HSEBYPASS_ON
  367. * @arg @ref LL_UTILS_HSEBYPASS_OFF
  368. * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  369. * the configuration information for the PLL.
  370. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  371. * the configuration information for the BUS prescalers.
  372. * @retval An ErrorStatus enumeration value:
  373. * - SUCCESS: Max frequency configuration done
  374. * - ERROR: Max frequency configuration not done
  375. */
  376. ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
  377. LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  378. {
  379. ErrorStatus status = SUCCESS;
  380. uint32_t pllfreq = 0U;
  381. /* Check the parameters */
  382. assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
  383. assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
  384. /* Check if one of the PLL is enabled */
  385. if(UTILS_PLL_IsBusy() == SUCCESS)
  386. {
  387. /* Calculate the new PLL output frequency */
  388. pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
  389. /* Enable HSE if not enabled */
  390. if(LL_RCC_HSE_IsReady() != 1U)
  391. {
  392. /* Check if need to enable HSE bypass feature or not */
  393. if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
  394. {
  395. LL_RCC_HSE_EnableBypass();
  396. }
  397. else
  398. {
  399. LL_RCC_HSE_DisableBypass();
  400. }
  401. /* Enable HSE */
  402. LL_RCC_HSE_Enable();
  403. while (LL_RCC_HSE_IsReady() != 1U)
  404. {
  405. /* Wait for HSE ready */
  406. }
  407. }
  408. /* Configure PLL */
  409. LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
  410. UTILS_PLLInitStruct->PLLP);
  411. /* Enable PLL and switch system clock to PLL */
  412. status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  413. }
  414. else
  415. {
  416. /* Current PLL configuration cannot be modified */
  417. status = ERROR;
  418. }
  419. return status;
  420. }
  421. /**
  422. * @}
  423. */
  424. /**
  425. * @}
  426. */
  427. /** @addtogroup UTILS_LL_Private_Functions
  428. * @{
  429. */
  430. /**
  431. * @brief Update number of Flash wait states in line with new frequency and current
  432. voltage range.
  433. * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
  434. * @param HCLK_Frequency HCLK frequency
  435. * @retval An ErrorStatus enumeration value:
  436. * - SUCCESS: Latency has been modified
  437. * - ERROR: Latency cannot be modified
  438. */
  439. static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
  440. {
  441. ErrorStatus status = SUCCESS;
  442. uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
  443. /* Frequency cannot be equal to 0 */
  444. if(HCLK_Frequency == 0U)
  445. {
  446. status = ERROR;
  447. }
  448. else
  449. {
  450. if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
  451. {
  452. if(LL_PWR_IsEnabledOverDriveMode() != 0U)
  453. {
  454. if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
  455. {
  456. /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */
  457. latency = LL_FLASH_LATENCY_7;
  458. }
  459. else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */
  460. {
  461. /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */
  462. latency = LL_FLASH_LATENCY_6;
  463. }
  464. }
  465. if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0))
  466. {
  467. /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */
  468. latency = LL_FLASH_LATENCY_5;
  469. }
  470. else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0))
  471. {
  472. /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
  473. latency = LL_FLASH_LATENCY_4;
  474. }
  475. else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0))
  476. {
  477. /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
  478. latency = LL_FLASH_LATENCY_3;
  479. }
  480. else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0))
  481. {
  482. /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
  483. latency = LL_FLASH_LATENCY_2;
  484. }
  485. else
  486. {
  487. if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0))
  488. {
  489. /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
  490. latency = LL_FLASH_LATENCY_1;
  491. }
  492. /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
  493. }
  494. }
  495. else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
  496. {
  497. if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)
  498. {
  499. /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */
  500. latency = LL_FLASH_LATENCY_5;
  501. }
  502. else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)
  503. {
  504. /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
  505. latency = LL_FLASH_LATENCY_4;
  506. }
  507. else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
  508. {
  509. /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
  510. latency = LL_FLASH_LATENCY_3;
  511. }
  512. else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
  513. {
  514. /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
  515. latency = LL_FLASH_LATENCY_2;
  516. }
  517. else
  518. {
  519. if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
  520. {
  521. /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
  522. latency = LL_FLASH_LATENCY_1;
  523. }
  524. /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
  525. }
  526. }
  527. else /* Scale 3 */
  528. {
  529. if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ)
  530. {
  531. /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */
  532. latency = LL_FLASH_LATENCY_4;
  533. }
  534. else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)
  535. {
  536. /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
  537. latency = LL_FLASH_LATENCY_3;
  538. }
  539. else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)
  540. {
  541. /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
  542. latency = LL_FLASH_LATENCY_2;
  543. }
  544. else
  545. {
  546. if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)
  547. {
  548. /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
  549. latency = LL_FLASH_LATENCY_1;
  550. }
  551. /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */
  552. }
  553. }
  554. LL_FLASH_SetLatency(latency);
  555. /* Check that the new number of wait states is taken into account to access the Flash
  556. memory by reading the FLASH_ACR register */
  557. if(LL_FLASH_GetLatency() != latency)
  558. {
  559. status = ERROR;
  560. }
  561. }
  562. return status;
  563. }
  564. /**
  565. * @brief Function to check that PLL can be modified
  566. * @param PLL_InputFrequency PLL input frequency (in Hz)
  567. * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  568. * the configuration information for the PLL.
  569. * @retval PLL output frequency (in Hz)
  570. */
  571. static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
  572. {
  573. uint32_t pllfreq = 0U;
  574. /* Check the parameters */
  575. assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
  576. assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
  577. assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
  578. /* Check different PLL parameters according to RM */
  579. /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */
  580. pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
  581. assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
  582. /* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/
  583. pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
  584. assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
  585. /* - PLLP: ensure that max frequency at 216000000 Hz is reached */
  586. pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
  587. assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
  588. return pllfreq;
  589. }
  590. /**
  591. * @brief Function to check that PLL can be modified
  592. * @retval An ErrorStatus enumeration value:
  593. * - SUCCESS: PLL modification can be done
  594. * - ERROR: PLL is busy
  595. */
  596. static ErrorStatus UTILS_PLL_IsBusy(void)
  597. {
  598. ErrorStatus status = SUCCESS;
  599. /* Check if PLL is busy*/
  600. if(LL_RCC_PLL_IsReady() != 0U)
  601. {
  602. /* PLL configuration cannot be modified */
  603. status = ERROR;
  604. }
  605. /* Check if PLLSAI is busy*/
  606. if(LL_RCC_PLLSAI_IsReady() != 0U)
  607. {
  608. /* PLLSAI1 configuration cannot be modified */
  609. status = ERROR;
  610. }
  611. /* Check if PLLI2S is busy*/
  612. if(LL_RCC_PLLI2S_IsReady() != 0U)
  613. {
  614. /* PLLI2S configuration cannot be modified */
  615. status = ERROR;
  616. }
  617. return status;
  618. }
  619. /**
  620. * @brief Function to enable PLL and switch system clock to PLL
  621. * @param SYSCLK_Frequency SYSCLK frequency
  622. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  623. * the configuration information for the BUS prescalers.
  624. * @retval An ErrorStatus enumeration value:
  625. * - SUCCESS: No problem to switch system to PLL
  626. * - ERROR: Problem to switch system to PLL
  627. */
  628. static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  629. {
  630. ErrorStatus status = SUCCESS;
  631. uint32_t hclk_frequency = 0U;
  632. assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
  633. assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
  634. assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
  635. /* Calculate HCLK frequency */
  636. hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
  637. /* Increasing the number of wait states because of higher CPU frequency */
  638. if(SystemCoreClock < hclk_frequency)
  639. {
  640. /* Set FLASH latency to highest latency */
  641. status = UTILS_SetFlashLatency(hclk_frequency);
  642. }
  643. /* Update system clock configuration */
  644. if(status == SUCCESS)
  645. {
  646. /* Enable PLL */
  647. LL_RCC_PLL_Enable();
  648. while (LL_RCC_PLL_IsReady() != 1U)
  649. {
  650. /* Wait for PLL ready */
  651. }
  652. /* Sysclk activation on the main PLL */
  653. LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
  654. LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
  655. while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
  656. {
  657. /* Wait for system clock switch to PLL */
  658. }
  659. /* Set APB1 & APB2 prescaler*/
  660. LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
  661. LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
  662. }
  663. /* Decreasing the number of wait states because of lower CPU frequency */
  664. if(SystemCoreClock > hclk_frequency)
  665. {
  666. /* Set FLASH latency to lowest latency */
  667. status = UTILS_SetFlashLatency(hclk_frequency);
  668. }
  669. /* Update SystemCoreClock variable */
  670. if(status == SUCCESS)
  671. {
  672. LL_SetSystemCoreClock(hclk_frequency);
  673. }
  674. return status;
  675. }
  676. /**
  677. * @}
  678. */
  679. /**
  680. * @}
  681. */
  682. /**
  683. * @}
  684. */
  685. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/