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  1. /**
  2. ******************************************************************************
  3. * @file stm32h7xx_hal_spi.h
  4. * @author MCD Application Team
  5. * @brief Header file of SPI HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32H7xx_HAL_SPI_H
  21. #define STM32H7xx_HAL_SPI_H
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32h7xx_hal_def.h"
  27. /** @addtogroup STM32H7xx_HAL_Driver
  28. * @{
  29. */
  30. /** @addtogroup SPI
  31. * @{
  32. */
  33. /* Exported types ------------------------------------------------------------*/
  34. /** @defgroup SPI_Exported_Types SPI Exported Types
  35. * @{
  36. */
  37. /**
  38. * @brief SPI Configuration Structure definition
  39. */
  40. typedef struct
  41. {
  42. uint32_t Mode; /*!< Specifies the SPI operating mode.
  43. This parameter can be a value of @ref SPI_Mode */
  44. uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
  45. This parameter can be a value of @ref SPI_Direction */
  46. uint32_t DataSize; /*!< Specifies the SPI data size.
  47. This parameter can be a value of @ref SPI_Data_Size */
  48. uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
  49. This parameter can be a value of @ref SPI_Clock_Polarity */
  50. uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
  51. This parameter can be a value of @ref SPI_Clock_Phase */
  52. uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
  53. hardware (NSS pin) or by software using the SSI bit.
  54. This parameter can be a value of @ref SPI_Slave_Select_Management */
  55. uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
  56. used to configure the transmit and receive SCK clock.
  57. This parameter can be a value of @ref SPI_BaudRate_Prescaler
  58. @note The communication clock is derived from the master
  59. clock. The slave clock does not need to be set. */
  60. uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
  61. This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
  62. uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
  63. This parameter can be a value of @ref SPI_TI_Mode */
  64. uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
  65. This parameter can be a value of @ref SPI_CRC_Calculation */
  66. uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
  67. This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
  68. uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
  69. This parameter can be a value of @ref SPI_CRC_length */
  70. uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
  71. This parameter can be a value of @ref SPI_NSSP_Mode
  72. This mode is activated by the SSOM bit in the SPIx_CR2 register and
  73. it takes effect only if the SPI interface is configured as Motorola SPI
  74. master (FRF=0). */
  75. uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is
  76. considered as active one.
  77. This parameter can be a value of @ref SPI_NSS_Polarity */
  78. uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
  79. This parameter can be a value of @ref SPI_Fifo_Threshold */
  80. uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
  81. This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
  82. uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
  83. This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
  84. uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
  85. additionally between active edge of SS and first data transaction start in master mode.
  86. This parameter can be a value of @ref SPI_Master_SS_Idleness */
  87. uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
  88. two consecutive data frames in master mode
  89. This parameter can be a value of @ref SPI_Master_InterData_Idleness */
  90. uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management
  91. in order to avoid overrun condition.
  92. This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
  93. uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
  94. This parameter can be a value of @ref SPI_Master_Keep_IO_State */
  95. uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
  96. This parameter can be a value of @ref SPI_IO_Swap */
  97. } SPI_InitTypeDef;
  98. /**
  99. * @brief HAL SPI State structure definition
  100. */
  101. typedef enum
  102. {
  103. HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */
  104. HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */
  105. HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */
  106. HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
  107. HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
  108. HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
  109. HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */
  110. HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */
  111. } HAL_SPI_StateTypeDef;
  112. #if defined(USE_SPI_RELOAD_TRANSFER)
  113. /**
  114. * @brief SPI Reload Structure definition
  115. */
  116. typedef struct
  117. {
  118. uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
  119. uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */
  120. uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
  121. uint16_t RxXferSize; /*!< SPI Rx Transfer size to reload */
  122. uint32_t Requested; /*!< SPI reload request */
  123. } SPI_ReloadTypeDef;
  124. #endif /* USE_HSPI_RELOAD_TRANSFER */
  125. /**
  126. * @brief SPI handle Structure definition
  127. */
  128. typedef struct __SPI_HandleTypeDef
  129. {
  130. SPI_TypeDef *Instance; /*!< SPI registers base address */
  131. SPI_InitTypeDef Init; /*!< SPI communication parameters */
  132. uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
  133. uint16_t TxXferSize; /*!< SPI Tx Transfer size */
  134. __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
  135. uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
  136. uint16_t RxXferSize; /*!< SPI Rx Transfer size */
  137. __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
  138. uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
  139. void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
  140. void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
  141. DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
  142. DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
  143. HAL_LockTypeDef Lock; /*!< Locking object */
  144. __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
  145. __IO uint32_t ErrorCode; /*!< SPI Error code */
  146. #if defined(USE_SPI_RELOAD_TRANSFER)
  147. SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */
  148. #endif /* USE_HSPI_RELOAD_TRANSFER */
  149. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
  150. void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
  151. void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
  152. void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
  153. void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
  154. void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
  155. void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
  156. void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
  157. void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
  158. void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
  159. void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
  160. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  161. } SPI_HandleTypeDef;
  162. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
  163. /**
  164. * @brief HAL SPI Callback ID enumeration definition
  165. */
  166. typedef enum
  167. {
  168. HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */
  169. HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */
  170. HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */
  171. HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */
  172. HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */
  173. HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */
  174. HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */
  175. HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */
  176. HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */
  177. HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */
  178. } HAL_SPI_CallbackIDTypeDef;
  179. /**
  180. * @brief HAL SPI Callback pointer definition
  181. */
  182. typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
  183. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  184. /**
  185. * @}
  186. */
  187. /* Exported constants --------------------------------------------------------*/
  188. /** @defgroup SPI_Exported_Constants SPI Exported Constants
  189. * @{
  190. */
  191. /** @defgroup SPI_FIFO_Type SPI FIFO Type
  192. * @{
  193. */
  194. #define SPI_LOWEND_FIFO_SIZE 8UL
  195. #define SPI_HIGHEND_FIFO_SIZE 16UL
  196. /**
  197. * @}
  198. */
  199. /** @defgroup SPI_Error_Code SPI Error Codes
  200. * @{
  201. */
  202. #define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */
  203. #define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */
  204. #define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */
  205. #define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */
  206. #define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */
  207. #define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */
  208. #define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
  209. #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */
  210. #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */
  211. #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */
  212. #define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknow error */
  213. #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */
  214. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
  215. #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /*!< Invalid Callback error */
  216. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  217. /**
  218. * @}
  219. */
  220. /** @defgroup SPI_Mode SPI Mode
  221. * @{
  222. */
  223. #define SPI_MODE_SLAVE (0x00000000UL)
  224. #define SPI_MODE_MASTER SPI_CFG2_MASTER
  225. /**
  226. * @}
  227. */
  228. /** @defgroup SPI_Direction SPI Direction Mode
  229. * @{
  230. */
  231. #define SPI_DIRECTION_2LINES (0x00000000UL)
  232. #define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
  233. #define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
  234. #define SPI_DIRECTION_1LINE SPI_CFG2_COMM
  235. /**
  236. * @}
  237. */
  238. /** @defgroup SPI_Data_Size SPI Data Size
  239. * @{
  240. */
  241. #define SPI_DATASIZE_4BIT (0x00000003UL)
  242. #define SPI_DATASIZE_5BIT (0x00000004UL)
  243. #define SPI_DATASIZE_6BIT (0x00000005UL)
  244. #define SPI_DATASIZE_7BIT (0x00000006UL)
  245. #define SPI_DATASIZE_8BIT (0x00000007UL)
  246. #define SPI_DATASIZE_9BIT (0x00000008UL)
  247. #define SPI_DATASIZE_10BIT (0x00000009UL)
  248. #define SPI_DATASIZE_11BIT (0x0000000AUL)
  249. #define SPI_DATASIZE_12BIT (0x0000000BUL)
  250. #define SPI_DATASIZE_13BIT (0x0000000CUL)
  251. #define SPI_DATASIZE_14BIT (0x0000000DUL)
  252. #define SPI_DATASIZE_15BIT (0x0000000EUL)
  253. #define SPI_DATASIZE_16BIT (0x0000000FUL)
  254. #define SPI_DATASIZE_17BIT (0x00000010UL)
  255. #define SPI_DATASIZE_18BIT (0x00000011UL)
  256. #define SPI_DATASIZE_19BIT (0x00000012UL)
  257. #define SPI_DATASIZE_20BIT (0x00000013UL)
  258. #define SPI_DATASIZE_21BIT (0x00000014UL)
  259. #define SPI_DATASIZE_22BIT (0x00000015UL)
  260. #define SPI_DATASIZE_23BIT (0x00000016UL)
  261. #define SPI_DATASIZE_24BIT (0x00000017UL)
  262. #define SPI_DATASIZE_25BIT (0x00000018UL)
  263. #define SPI_DATASIZE_26BIT (0x00000019UL)
  264. #define SPI_DATASIZE_27BIT (0x0000001AUL)
  265. #define SPI_DATASIZE_28BIT (0x0000001BUL)
  266. #define SPI_DATASIZE_29BIT (0x0000001CUL)
  267. #define SPI_DATASIZE_30BIT (0x0000001DUL)
  268. #define SPI_DATASIZE_31BIT (0x0000001EUL)
  269. #define SPI_DATASIZE_32BIT (0x0000001FUL)
  270. /**
  271. * @}
  272. */
  273. /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
  274. * @{
  275. */
  276. #define SPI_POLARITY_LOW (0x00000000UL)
  277. #define SPI_POLARITY_HIGH SPI_CFG2_CPOL
  278. /**
  279. * @}
  280. */
  281. /** @defgroup SPI_Clock_Phase SPI Clock Phase
  282. * @{
  283. */
  284. #define SPI_PHASE_1EDGE (0x00000000UL)
  285. #define SPI_PHASE_2EDGE SPI_CFG2_CPHA
  286. /**
  287. * @}
  288. */
  289. /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
  290. * @{
  291. */
  292. #define SPI_NSS_SOFT SPI_CFG2_SSM
  293. #define SPI_NSS_HARD_INPUT (0x00000000UL)
  294. #define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
  295. /**
  296. * @}
  297. */
  298. /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
  299. * @{
  300. */
  301. #define SPI_NSS_PULSE_DISABLE (0x00000000UL)
  302. #define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
  303. /**
  304. * @}
  305. */
  306. /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
  307. * @{
  308. */
  309. #define SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
  310. #define SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
  311. #define SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
  312. #define SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
  313. #define SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
  314. #define SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
  315. #define SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
  316. #define SPI_BAUDRATEPRESCALER_256 (0x70000000UL)
  317. /**
  318. * @}
  319. */
  320. /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
  321. * @{
  322. */
  323. #define SPI_FIRSTBIT_MSB (0x00000000UL)
  324. #define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
  325. /**
  326. * @}
  327. */
  328. /** @defgroup SPI_TI_Mode SPI TI Mode
  329. * @{
  330. */
  331. #define SPI_TIMODE_DISABLE (0x00000000UL)
  332. #define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
  333. /**
  334. * @}
  335. */
  336. /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
  337. * @{
  338. */
  339. #define SPI_CRCCALCULATION_DISABLE (0x00000000UL)
  340. #define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
  341. /**
  342. * @}
  343. */
  344. /** @defgroup SPI_CRC_length SPI CRC Length
  345. * @{
  346. */
  347. #define SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
  348. #define SPI_CRC_LENGTH_4BIT (0x00030000UL)
  349. #define SPI_CRC_LENGTH_5BIT (0x00040000UL)
  350. #define SPI_CRC_LENGTH_6BIT (0x00050000UL)
  351. #define SPI_CRC_LENGTH_7BIT (0x00060000UL)
  352. #define SPI_CRC_LENGTH_8BIT (0x00070000UL)
  353. #define SPI_CRC_LENGTH_9BIT (0x00080000UL)
  354. #define SPI_CRC_LENGTH_10BIT (0x00090000UL)
  355. #define SPI_CRC_LENGTH_11BIT (0x000A0000UL)
  356. #define SPI_CRC_LENGTH_12BIT (0x000B0000UL)
  357. #define SPI_CRC_LENGTH_13BIT (0x000C0000UL)
  358. #define SPI_CRC_LENGTH_14BIT (0x000D0000UL)
  359. #define SPI_CRC_LENGTH_15BIT (0x000E0000UL)
  360. #define SPI_CRC_LENGTH_16BIT (0x000F0000UL)
  361. #define SPI_CRC_LENGTH_17BIT (0x00100000UL)
  362. #define SPI_CRC_LENGTH_18BIT (0x00110000UL)
  363. #define SPI_CRC_LENGTH_19BIT (0x00120000UL)
  364. #define SPI_CRC_LENGTH_20BIT (0x00130000UL)
  365. #define SPI_CRC_LENGTH_21BIT (0x00140000UL)
  366. #define SPI_CRC_LENGTH_22BIT (0x00150000UL)
  367. #define SPI_CRC_LENGTH_23BIT (0x00160000UL)
  368. #define SPI_CRC_LENGTH_24BIT (0x00170000UL)
  369. #define SPI_CRC_LENGTH_25BIT (0x00180000UL)
  370. #define SPI_CRC_LENGTH_26BIT (0x00190000UL)
  371. #define SPI_CRC_LENGTH_27BIT (0x001A0000UL)
  372. #define SPI_CRC_LENGTH_28BIT (0x001B0000UL)
  373. #define SPI_CRC_LENGTH_29BIT (0x001C0000UL)
  374. #define SPI_CRC_LENGTH_30BIT (0x001D0000UL)
  375. #define SPI_CRC_LENGTH_31BIT (0x001E0000UL)
  376. #define SPI_CRC_LENGTH_32BIT (0x001F0000UL)
  377. /**
  378. * @}
  379. */
  380. /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
  381. * @{
  382. */
  383. #define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
  384. #define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
  385. #define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
  386. #define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
  387. #define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
  388. #define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
  389. #define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
  390. #define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
  391. #define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
  392. #define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
  393. #define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
  394. #define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
  395. #define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
  396. #define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
  397. #define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
  398. #define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)
  399. /**
  400. * @}
  401. */
  402. /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
  403. * @{
  404. */
  405. #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
  406. #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)
  407. /**
  408. * @}
  409. */
  410. /** @defgroup SPI_NSS_Polarity SPI NSS Polarity
  411. * @{
  412. */
  413. #define SPI_NSS_POLARITY_LOW (0x00000000UL)
  414. #define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
  415. /**
  416. * @}
  417. */
  418. /** @defgroup SPI_Master_Keep_IO_State Keep IO State
  419. * @{
  420. */
  421. #define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
  422. #define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
  423. /**
  424. * @}
  425. */
  426. /** @defgroup SPI_IO_Swap Control SPI IO Swap
  427. * @{
  428. */
  429. #define SPI_IO_SWAP_DISABLE (0x00000000UL)
  430. #define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
  431. /**
  432. * @}
  433. */
  434. /** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness
  435. * @{
  436. */
  437. #define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
  438. #define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
  439. #define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
  440. #define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
  441. #define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
  442. #define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
  443. #define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
  444. #define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
  445. #define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
  446. #define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
  447. #define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
  448. #define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
  449. #define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
  450. #define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
  451. #define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
  452. #define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)
  453. /**
  454. * @}
  455. */
  456. /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness
  457. * @{
  458. */
  459. #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
  460. #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
  461. #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
  462. #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
  463. #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
  464. #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
  465. #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
  466. #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
  467. #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
  468. #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
  469. #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
  470. #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
  471. #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
  472. #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
  473. #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
  474. #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)
  475. /**
  476. * @}
  477. */
  478. /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
  479. * @{
  480. */
  481. #define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
  482. #define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
  483. /**
  484. * @}
  485. */
  486. /** @defgroup SPI_Underrun_Detection SPI Underrun Detection
  487. * @{
  488. */
  489. #define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
  490. #define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
  491. #define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
  492. /**
  493. * @}
  494. */
  495. /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
  496. * @{
  497. */
  498. #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
  499. #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
  500. #define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
  501. /**
  502. * @}
  503. */
  504. /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
  505. * @{
  506. */
  507. #define SPI_IT_RXP SPI_IER_RXPIE
  508. #define SPI_IT_TXP SPI_IER_TXPIE
  509. #define SPI_IT_DXP SPI_IER_DXPIE
  510. #define SPI_IT_EOT SPI_IER_EOTIE
  511. #define SPI_IT_TXTF SPI_IER_TXTFIE
  512. #define SPI_IT_UDR SPI_IER_UDRIE
  513. #define SPI_IT_OVR SPI_IER_OVRIE
  514. #define SPI_IT_CRCERR SPI_IER_CRCEIE
  515. #define SPI_IT_FRE SPI_IER_TIFREIE
  516. #define SPI_IT_MODF SPI_IER_MODFIE
  517. #define SPI_IT_TSERF SPI_IER_TSERFIE
  518. #define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
  519. /**
  520. * @}
  521. */
  522. /** @defgroup SPI_Flags_definition SPI Flags Definition
  523. * @{
  524. */
  525. #define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
  526. #define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
  527. #define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
  528. #define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
  529. #define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
  530. #define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
  531. #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
  532. #define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
  533. #define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
  534. #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
  535. #define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */
  536. #define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
  537. #define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
  538. #define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
  539. #define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */
  540. /**
  541. * @}
  542. */
  543. /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
  544. * @{
  545. */
  546. #define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
  547. #define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
  548. #define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
  549. #define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
  550. /**
  551. * @}
  552. */
  553. /**
  554. * @}
  555. */
  556. /* Exported macros -----------------------------------------------------------*/
  557. /** @defgroup SPI_Exported_Macros SPI Exported Macros
  558. * @{
  559. */
  560. /** @brief Reset SPI handle state.
  561. * @param __HANDLE__: specifies the SPI Handle.
  562. * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
  563. * @retval None
  564. */
  565. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
  566. #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
  567. (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
  568. (__HANDLE__)->MspInitCallback = NULL; \
  569. (__HANDLE__)->MspDeInitCallback = NULL; \
  570. } while(0)
  571. #else
  572. #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
  573. #endif
  574. /** @brief Enable the specified SPI interrupts.
  575. * @param __HANDLE__: specifies the SPI Handle.
  576. * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
  577. * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
  578. * This parameter can be one of the following values:
  579. * @arg SPI_IT_RXP : Rx-Packet available interrupt
  580. * @arg SPI_IT_TXP : Tx-Packet space available interrupt
  581. * @arg SPI_IT_DXP : Duplex Packet interrupt
  582. * @arg SPI_IT_EOT : End of transfer interrupt
  583. * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
  584. * @arg SPI_IT_UDR : Underrun interrupt
  585. * @arg SPI_IT_OVR : Overrun interrupt
  586. * @arg SPI_IT_CRCERR : CRC error interrupt
  587. * @arg SPI_IT_FRE : TI mode frame format error interrupt
  588. * @arg SPI_IT_MODF : Mode fault interrupt
  589. * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
  590. * @arg SPI_IT_ERR : Error interrupt
  591. * @retval None
  592. */
  593. #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
  594. /** @brief Disable the specified SPI interrupts.
  595. * @param __HANDLE__: specifies the SPI Handle.
  596. * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
  597. * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
  598. * This parameter can be one of the following values:
  599. * @arg SPI_IT_RXP : Rx-Packet available interrupt
  600. * @arg SPI_IT_TXP : Tx-Packet space available interrupt
  601. * @arg SPI_IT_DXP : Duplex Packet interrupt
  602. * @arg SPI_IT_EOT : End of transfer interrupt
  603. * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
  604. * @arg SPI_IT_UDR : Underrun interrupt
  605. * @arg SPI_IT_OVR : Overrun interrupt
  606. * @arg SPI_IT_CRCERR : CRC error interrupt
  607. * @arg SPI_IT_FRE : TI mode frame format error interrupt
  608. * @arg SPI_IT_MODF : Mode fault interrupt
  609. * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
  610. * @arg SPI_IT_ERR : Error interrupt
  611. * @retval None
  612. */
  613. #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
  614. /** @brief Check whether the specified SPI interrupt source is enabled or not.
  615. * @param __HANDLE__: specifies the SPI Handle.
  616. * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
  617. * @param __INTERRUPT__: specifies the SPI interrupt source to check.
  618. * This parameter can be one of the following values:
  619. * @arg SPI_IT_RXP : Rx-Packet available interrupt
  620. * @arg SPI_IT_TXP : Tx-Packet space available interrupt
  621. * @arg SPI_IT_DXP : Duplex Packet interrupt
  622. * @arg SPI_IT_EOT : End of transfer interrupt
  623. * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
  624. * @arg SPI_IT_UDR : Underrun interrupt
  625. * @arg SPI_IT_OVR : Overrun interrupt
  626. * @arg SPI_IT_CRCERR : CRC error interrupt
  627. * @arg SPI_IT_FRE : TI mode frame format error interrupt
  628. * @arg SPI_IT_MODF : Mode fault interrupt
  629. * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
  630. * @arg SPI_IT_ERR : Error interrupt
  631. * @retval The new state of __IT__ (TRUE or FALSE).
  632. */
  633. #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
  634. /** @brief Check whether the specified SPI flag is set or not.
  635. * @param __HANDLE__: specifies the SPI Handle.
  636. * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
  637. * @param __FLAG__: specifies the flag to check.
  638. * This parameter can be one of the following values:
  639. * @arg SPI_FLAG_RXP : Rx-Packet available flag
  640. * @arg SPI_FLAG_TXP : Tx-Packet space available flag
  641. * @arg SPI_FLAG_DXP : Duplex Packet flag
  642. * @arg SPI_FLAG_EOT : End of transfer flag
  643. * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag
  644. * @arg SPI_FLAG_UDR : Underrun flag
  645. * @arg SPI_FLAG_OVR : Overrun flag
  646. * @arg SPI_FLAG_CRCERR : CRC error flag
  647. * @arg SPI_FLAG_FRE : TI mode frame format error flag
  648. * @arg SPI_FLAG_MODF : Mode fault flag
  649. * @arg SPI_FLAG_TSERF : Additional number of data reloaded flag
  650. * @arg SPI_FLAG_SUSP : Transfer suspend complete flag
  651. * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag
  652. * @arg SPI_FLAG_FRLVL : Fifo reception level flag
  653. * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag
  654. * @retval The new state of __FLAG__ (TRUE or FALSE).
  655. */
  656. #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
  657. /** @brief Clear the SPI CRCERR pending flag.
  658. * @param __HANDLE__: specifies the SPI Handle.
  659. * @retval None
  660. */
  661. #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
  662. /** @brief Clear the SPI MODF pending flag.
  663. * @param __HANDLE__: specifies the SPI Handle.
  664. * @retval None
  665. */
  666. #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
  667. /** @brief Clear the SPI OVR pending flag.
  668. * @param __HANDLE__: specifies the SPI Handle.
  669. * @retval None
  670. */
  671. #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
  672. /** @brief Clear the SPI FRE pending flag.
  673. * @param __HANDLE__: specifies the SPI Handle.
  674. * @retval None
  675. */
  676. #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
  677. /** @brief Clear the SPI UDR pending flag.
  678. * @param __HANDLE__: specifies the SPI Handle.
  679. * @retval None
  680. */
  681. #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
  682. /** @brief Clear the SPI EOT pending flag.
  683. * @param __HANDLE__: specifies the SPI Handle.
  684. * @retval None
  685. */
  686. #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
  687. /** @brief Clear the SPI UDR pending flag.
  688. * @param __HANDLE__: specifies the SPI Handle.
  689. * @retval None
  690. */
  691. #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
  692. /** @brief Clear the SPI SUSP pending flag.
  693. * @param __HANDLE__: specifies the SPI Handle.
  694. * @retval None
  695. */
  696. #define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
  697. /** @brief Clear the SPI TSERF pending flag.
  698. * @param __HANDLE__: specifies the SPI Handle.
  699. * @retval None
  700. */
  701. #define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
  702. /** @brief Enable the SPI peripheral.
  703. * @param __HANDLE__: specifies the SPI Handle.
  704. * @retval None
  705. */
  706. #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
  707. /** @brief Disable the SPI peripheral.
  708. * @param __HANDLE__: specifies the SPI Handle.
  709. * @retval None
  710. */
  711. #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
  712. /**
  713. * @}
  714. */
  715. /* Include SPI HAL Extension module */
  716. #include "stm32h7xx_hal_spi_ex.h"
  717. /* Exported functions --------------------------------------------------------*/
  718. /** @addtogroup SPI_Exported_Functions
  719. * @{
  720. */
  721. /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
  722. * @{
  723. */
  724. /* Initialization/de-initialization functions ********************************/
  725. HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
  726. HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
  727. void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
  728. void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
  729. /* Callbacks Register/UnRegister functions ***********************************/
  730. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  731. HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
  732. HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
  733. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  734. /**
  735. * @}
  736. */
  737. /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
  738. * @{
  739. */
  740. /* I/O operation functions ***************************************************/
  741. HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
  742. HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
  743. HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
  744. uint32_t Timeout);
  745. HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
  746. HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
  747. HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
  748. HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
  749. HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
  750. HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
  751. #if defined(USE_SPI_RELOAD_TRANSFER)
  752. HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
  753. HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
  754. HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
  755. #endif /* USE_HSPI_RELOAD_TRANSFER */
  756. HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
  757. HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
  758. HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
  759. /* Transfer Abort functions */
  760. HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
  761. HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
  762. void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
  763. void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
  764. void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
  765. void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
  766. void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
  767. void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
  768. void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
  769. void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
  770. void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
  771. /**
  772. * @}
  773. */
  774. /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
  775. * @{
  776. */
  777. /* Peripheral State and Error functions ***************************************/
  778. HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
  779. uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
  780. /**
  781. * @}
  782. */
  783. /**
  784. * @}
  785. */
  786. /* Private macros ------------------------------------------------------------*/
  787. /** @defgroup SPI_Private_Macros SPI Private Macros
  788. * @{
  789. */
  790. /** @brief Set the SPI transmit-only mode.
  791. * @param __HANDLE__: specifies the SPI Handle.
  792. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
  793. * @retval None
  794. */
  795. #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
  796. /** @brief Set the SPI receive-only mode.
  797. * @param __HANDLE__: specifies the SPI Handle.
  798. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
  799. * @retval None
  800. */
  801. #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
  802. #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
  803. ((MODE) == SPI_MODE_MASTER))
  804. #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
  805. ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
  806. ((MODE) == SPI_DIRECTION_1LINE) || \
  807. ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
  808. #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
  809. #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \
  810. ((MODE) == SPI_DIRECTION_2LINES)|| \
  811. ((MODE) == SPI_DIRECTION_1LINE) || \
  812. ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
  813. #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \
  814. ((MODE) == SPI_DIRECTION_2LINES)|| \
  815. ((MODE) == SPI_DIRECTION_1LINE) || \
  816. ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
  817. #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
  818. ((DATASIZE) == SPI_DATASIZE_31BIT) || \
  819. ((DATASIZE) == SPI_DATASIZE_30BIT) || \
  820. ((DATASIZE) == SPI_DATASIZE_29BIT) || \
  821. ((DATASIZE) == SPI_DATASIZE_28BIT) || \
  822. ((DATASIZE) == SPI_DATASIZE_27BIT) || \
  823. ((DATASIZE) == SPI_DATASIZE_26BIT) || \
  824. ((DATASIZE) == SPI_DATASIZE_25BIT) || \
  825. ((DATASIZE) == SPI_DATASIZE_24BIT) || \
  826. ((DATASIZE) == SPI_DATASIZE_23BIT) || \
  827. ((DATASIZE) == SPI_DATASIZE_22BIT) || \
  828. ((DATASIZE) == SPI_DATASIZE_21BIT) || \
  829. ((DATASIZE) == SPI_DATASIZE_20BIT) || \
  830. ((DATASIZE) == SPI_DATASIZE_22BIT) || \
  831. ((DATASIZE) == SPI_DATASIZE_19BIT) || \
  832. ((DATASIZE) == SPI_DATASIZE_18BIT) || \
  833. ((DATASIZE) == SPI_DATASIZE_17BIT) || \
  834. ((DATASIZE) == SPI_DATASIZE_16BIT) || \
  835. ((DATASIZE) == SPI_DATASIZE_15BIT) || \
  836. ((DATASIZE) == SPI_DATASIZE_14BIT) || \
  837. ((DATASIZE) == SPI_DATASIZE_13BIT) || \
  838. ((DATASIZE) == SPI_DATASIZE_12BIT) || \
  839. ((DATASIZE) == SPI_DATASIZE_11BIT) || \
  840. ((DATASIZE) == SPI_DATASIZE_10BIT) || \
  841. ((DATASIZE) == SPI_DATASIZE_9BIT) || \
  842. ((DATASIZE) == SPI_DATASIZE_8BIT) || \
  843. ((DATASIZE) == SPI_DATASIZE_7BIT) || \
  844. ((DATASIZE) == SPI_DATASIZE_6BIT) || \
  845. ((DATASIZE) == SPI_DATASIZE_5BIT) || \
  846. ((DATASIZE) == SPI_DATASIZE_4BIT))
  847. #define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
  848. ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
  849. ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
  850. ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
  851. ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
  852. ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
  853. ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
  854. ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
  855. ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
  856. ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
  857. ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
  858. ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
  859. ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
  860. ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
  861. ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
  862. ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
  863. #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
  864. ((CPOL) == SPI_POLARITY_HIGH))
  865. #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
  866. ((CPHA) == SPI_PHASE_2EDGE))
  867. #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
  868. ((NSS) == SPI_NSS_HARD_INPUT) || \
  869. ((NSS) == SPI_NSS_HARD_OUTPUT))
  870. #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
  871. ((NSSP) == SPI_NSS_PULSE_DISABLE))
  872. #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
  873. ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
  874. ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
  875. ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
  876. ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
  877. ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
  878. ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
  879. ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
  880. #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
  881. ((BIT) == SPI_FIRSTBIT_LSB))
  882. #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
  883. ((MODE) == SPI_TIMODE_ENABLE))
  884. #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
  885. ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
  886. #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
  887. ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
  888. #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
  889. ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \
  890. ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \
  891. ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \
  892. ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \
  893. ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \
  894. ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \
  895. ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \
  896. ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \
  897. ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \
  898. ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \
  899. ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \
  900. ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \
  901. ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \
  902. ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \
  903. ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \
  904. ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \
  905. ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \
  906. ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \
  907. ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \
  908. ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \
  909. ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \
  910. ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \
  911. ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \
  912. ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \
  913. ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
  914. ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \
  915. ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \
  916. ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
  917. ((LENGTH) == SPI_CRC_LENGTH_4BIT))
  918. #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1UL)
  919. #define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
  920. ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
  921. ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
  922. #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
  923. ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
  924. ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
  925. /**
  926. * @}
  927. */
  928. /**
  929. * @}
  930. */
  931. /**
  932. * @}
  933. */
  934. #ifdef __cplusplus
  935. }
  936. #endif
  937. #endif /* STM32H7xx_HAL_SPI_H */
  938. /**
  939. * @}
  940. */
  941. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/