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stm32lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32h7xx_ll_adc.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of ADC LL module.

  6.   ******************************************************************************

  7.   * @attention

  8.   *

  9.   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

  10.   * All rights reserved.</center></h2>

  11.   *

  12.   * This software component is licensed by ST under BSD 3-Clause license,

  13.   * the "License"; You may not use this file except in compliance with the

  14.   * License. You may obtain a copy of the License at:

  15.   *                        opensource.org/licenses/BSD-3-Clause

  16.   *

  17.   ******************************************************************************

  18.   */

  19. 

  20. /* Define to prevent recursive inclusion -------------------------------------*/

  21. #ifndef STM32H7xx_LL_ADC_H

  22. #define STM32H7xx_LL_ADC_H

  23. 

  24. #ifdef __cplusplus

  25. extern "C" {

  26. #endif

  27. 

  28. /* Includes ------------------------------------------------------------------*/

  29. #include "stm32h7xx.h"

  30. 

  31. /** @addtogroup STM32H7xx_LL_Driver

  32.   * @{

  33.   */

  34. 

  35. #if defined (ADC1) || defined (ADC2) || defined (ADC3)

  36. 

  37. /** @defgroup ADC_LL ADC

  38.   * @{

  39.   */

  40. 

  41. /* Private types -------------------------------------------------------------*/

  42. /* Private variables ---------------------------------------------------------*/

  43. 

  44. /* Private constants ---------------------------------------------------------*/

  45. /** @defgroup ADC_LL_Private_Constants ADC Private Constants

  46.   * @{

  47.   */

  48. 

  49. /* Internal mask for ADC calibration:                                         */

  50. /* Internal register offset for ADC calibration factors configuration */

  51. 

  52. /* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ...   */

  53. /* the relevant bits for:                                                     */

  54. /* (concatenation of multiple bits used in different registers)               */

  55. /* - ADC calibration configuration: configuration before calibration start    */

  56. /* - ADC calibration factors: register offset                                 */

  57. #define ADC_CALIB_FACTOR_OFFSET_REGOFFSET    (0x00000000UL) /* Register CALFACT defined as reference register */

  58. #define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */

  59. #define ADC_CALIB_FACTOR_REGOFFSET_MASK      (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)

  60. #define ADC_CALIB_MODE_MASK                  (ADC_CR_ADCALLIN)

  61. #define ADC_CALIB_MODE_BINARY_MASK           (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */

  62. 

  63. 

  64. /* Internal mask for ADC group regular sequencer:                             */

  65. /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */

  66. /* - sequencer register offset                                                */

  67. /* - sequencer rank bits position into the selected register                  */

  68. 

  69. /* Internal register offset for ADC group regular sequencer configuration */

  70. /* (offset placed into a spare area of literal definition) */

  71. #define ADC_SQR1_REGOFFSET                 (0x00000000UL)

  72. #define ADC_SQR2_REGOFFSET                 (0x00000100UL)

  73. #define ADC_SQR3_REGOFFSET                 (0x00000200UL)

  74. #define ADC_SQR4_REGOFFSET                 (0x00000300UL)

  75. 

  76. #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

  77. #define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */

  78. #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  79. 

  80. /* Definition of ADC group regular sequencer bits information to be inserted  */

  81. /* into ADC group regular sequencer ranks literals definition.                */

  82. #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */

  83. #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */

  84. #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */

  85. #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */

  86. #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */

  87. #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */

  88. #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */

  89. #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */

  90. #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */

  91. #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */

  92. #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */

  93. #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */

  94. #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */

  95. #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */

  96. #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */

  97. #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */

  98. 

  99. 

  100. 

  101. /* Internal mask for ADC group injected sequencer:                            */

  102. /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */

  103. /* - data register offset                                                     */

  104. /* - sequencer rank bits position into the selected register                  */

  105. 

  106. /* Internal register offset for ADC group injected data register */

  107. /* (offset placed into a spare area of literal definition) */

  108. #define ADC_JDR1_REGOFFSET                 (0x00000000UL)

  109. #define ADC_JDR2_REGOFFSET                 (0x00000100UL)

  110. #define ADC_JDR3_REGOFFSET                 (0x00000200UL)

  111. #define ADC_JDR4_REGOFFSET                 (0x00000300UL)

  112. 

  113. #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

  114. #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  115. #define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */

  116. 

  117. /* Definition of ADC group injected sequencer bits information to be inserted */

  118. /* into ADC group injected sequencer ranks literals definition.               */

  119. #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)

  120. #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)

  121. #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)

  122. #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)

  123. 

  124. 

  125. 

  126. /* Internal mask for ADC group regular trigger:                               */

  127. /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */

  128. /* - regular trigger source                                                   */

  129. /* - regular trigger edge                                                     */

  130. #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  131. 

  132. /* Mask containing trigger source masks for each of possible                  */

  133. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  134. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  135. #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \

  136.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \

  137.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \

  138.                                              ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )

  139. 

  140. /* Mask containing trigger edge masks for each of possible                    */

  141. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  142. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  143. #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \

  144.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \

  145.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \

  146.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )

  147. 

  148. /* Definition of ADC group regular trigger bits information.                  */

  149. #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */

  150. #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */

  151. 

  152. 

  153. 

  154. /* Internal mask for ADC group injected trigger:                              */

  155. /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */

  156. /* - injected trigger source                                                  */

  157. /* - injected trigger edge                                                    */

  158. #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  159. 

  160. /* Mask containing trigger source masks for each of possible                  */

  161. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  162. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  163. #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \

  164.                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \

  165.                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \

  166.                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )

  167. 

  168. /* Mask containing trigger edge masks for each of possible                    */

  169. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  170. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  171. #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \

  172.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \

  173.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \

  174.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

  175. 

  176. /* Definition of ADC group injected trigger bits information.                 */

  177. #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */

  178. #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */

  179. 

  180. 

  181. 

  182. 

  183. 

  184. 

  185. /* Internal mask for ADC channel:                                             */

  186. /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */

  187. /* - channel identifier defined by number                                     */

  188. /* - channel identifier defined by bitfield                                   */

  189. /* - channel differentiation between external channels (connected to          */

  190. /*   GPIO pins) and internal channels (connected to internal paths)           */

  191. /* - channel sampling time defined by SMPRx register offset                   */

  192. /*   and SMPx bits positions into SMPRx register                              */

  193. #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)

  194. #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)

  195. #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */

  196. #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  197. /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */

  198. #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

  199. 

  200. /* Channel differentiation between external and internal channels */

  201. #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */

  202. #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)

  203. 

  204. /* Internal register offset for ADC channel sampling time configuration */

  205. /* (offset placed into a spare area of literal definition) */

  206. #define ADC_SMPR1_REGOFFSET                (0x00000000UL)

  207. #define ADC_SMPR2_REGOFFSET                (0x02000000UL)

  208. #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

  209. #define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */

  210. 

  211. #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)

  212. #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */

  213. 

  214. /* Definition of channels ID number information to be inserted into           */

  215. /* channels literals definition.                                              */

  216. #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)

  217. #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)

  218. #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )

  219. #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  220. #define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )

  221. #define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)

  222. #define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )

  223. #define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  224. #define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )

  225. #define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)

  226. #define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )

  227. #define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  228. #define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )

  229. #define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)

  230. #define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )

  231. #define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  232. #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )

  233. #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)

  234. #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )

  235. #define ADC_CHANNEL_19_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

  236. 

  237. /* Definition of channels ID bitfield information to be inserted into         */

  238. /* channels literals definition.                                              */

  239. #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)

  240. #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)

  241. #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)

  242. #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)

  243. #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)

  244. #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)

  245. #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)

  246. #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)

  247. #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)

  248. #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)

  249. #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)

  250. #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)

  251. #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)

  252. #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)

  253. #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)

  254. #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)

  255. #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)

  256. #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)

  257. #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)

  258. #define ADC_CHANNEL_19_BITFIELD            (ADC_AWD2CR_AWD2CH_19)

  259. 

  260. /* Definition of channels sampling time information to be inserted into       */

  261. /* channels literals definition.                                              */

  262. #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */

  263. #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */

  264. #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */

  265. #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */

  266. #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */

  267. #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */

  268. #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */

  269. #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */

  270. #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */

  271. #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */

  272. #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */

  273. #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */

  274. #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */

  275. #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */

  276. #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */

  277. #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */

  278. #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */

  279. #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */

  280. #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */

  281. #define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */

  282. 

  283. 

  284. /* Internal mask for ADC mode single or differential ended:                   */

  285. /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */

  286. /* the relevant bits for:                                                     */

  287. /* (concatenation of multiple bits used in different registers)               */

  288. /* - ADC calibration: calibration start, calibration factor get or set        */

  289. /* - ADC channels: set each ADC channel ending mode                           */

  290. #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)

  291. #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

  292. #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

  293. #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */

  294. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection of 1 bit to discriminate differential mode: mask of bit */

  295. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection of 1 bit to discriminate differential mode: position of bit */

  296. #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */

  297. 

  298. /* Internal mask for ADC analog watchdog:                                     */

  299. /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */

  300. /* (concatenation of multiple bits used in different analog watchdogs,        */

  301. /* (feature of several watchdogs not available on all STM32 families)).       */

  302. /* - analog watchdog 1: monitored channel defined by number,                  */

  303. /*   selection of ADC group (ADC groups regular and-or injected).             */

  304. /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */

  305. /*   selection on groups.                                                     */

  306. 

  307. /* Internal register offset for ADC analog watchdog channel configuration */

  308. #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)

  309. #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)

  310. #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)

  311. 

  312. /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */

  313. /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */

  314. #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)

  315. #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)

  316. 

  317. #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

  318. 

  319. #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

  320. #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)

  321. #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

  322. 

  323. #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

  324. 

  325. /* Internal register offset for ADC analog watchdog threshold configuration */

  326. #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)

  327. #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)

  328. #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)

  329. #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

  330. #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */

  331. 

  332. /* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */

  333. /* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */

  334. #define ADC_AWD_TR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)

  335. #define ADC_AWD_TR12_REGOFFSETGAP_VAL      (0x00000022UL)

  336. 

  337. /* Legacy literals */

  338. #define LL_ADC_AWD1_TR                      LL_ADC_AWD1

  339. #define LL_ADC_AWD2_TR                      LL_ADC_AWD2

  340. #define LL_ADC_AWD3_TR                      LL_ADC_AWD3

  341. 

  342. /* Internal mask for ADC offset:                                              */

  343. /* Internal register offset for ADC offset number configuration */

  344. #define ADC_OFR1_REGOFFSET                 (0x00000000UL)

  345. #define ADC_OFR2_REGOFFSET                 (0x00000001UL)

  346. #define ADC_OFR3_REGOFFSET                 (0x00000002UL)

  347. #define ADC_OFR4_REGOFFSET                 (0x00000003UL)

  348. #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

  349. 

  350. 

  351. /* ADC registers bits positions */

  352. #define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)

  353. #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)

  354. #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)

  355. #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)

  356. 

  357. 

  358. /* ADC registers bits groups */

  359. #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

  360. 

  361. 

  362. /* ADC internal channels related definitions */

  363. /* Internal voltage reference VrefInt */

  364. #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  365. #define VREFINT_CAL_VREF                   (3300UL)                     /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

  366. /* Temperature sensor */

  367. #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  368. #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  369. #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  370. #define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  371. #define TEMPSENSOR_CAL_VREFANALOG          (3300UL)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

  372. 

  373. 

  374. /* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */

  375. #define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))

  376. #define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))

  377. #define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))

  378. #define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))

  379. #define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))

  380. #define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))

  381. #define ADC_LINEAR_CALIB_REG_COUNT  (6UL)

  382. /**

  383.   * @}

  384.   */

  385. 

  386. 

  387. /* Private macros ------------------------------------------------------------*/

  388. /** @defgroup ADC_LL_Private_Macros ADC Private Macros

  389.   * @{

  390.   */

  391. 

  392. /**

  393.   * @brief  Driver macro reserved for internal use: set a pointer to

  394.   *         a register from a register basis from which an offset

  395.   *         is applied.

  396.   * @param  __REG__ Register basis from which the offset is applied.

  397.   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).

  398.   * @retval Pointer to register address

  399.   */

  400. #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \

  401.   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

  402. 

  403. /**

  404.   * @}

  405.   */

  406. 

  407. 

  408. /* Exported types ------------------------------------------------------------*/

  409. #if defined(USE_FULL_LL_DRIVER)

  410. /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure

  411.   * @{

  412.   */

  413. 

  414. /**

  415.   * @brief  Structure definition of some features of ADC common parameters

  416.   *         and multimode

  417.   *         (all ADC instances belonging to the same ADC common instance).

  418.   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()

  419.   *         is conditioned to ADC instances state (all ADC instances

  420.   *         sharing the same ADC common instance):

  421.   *         All ADC instances sharing the same ADC common instance must be

  422.   *         disabled.

  423.   */

  424. typedef struct

  425. {

  426.   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.

  427.                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE

  428.                                              @note On this STM32 serie, if ADC group injected is used, some

  429.                                                    clock ratio constraints between ADC clock and AHB clock

  430.                                                    must be respected. Refer to reference manual.

  431. 

  432.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */

  433. 

  434.   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

  435.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE

  436. 

  437.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */

  438. 

  439.   uint32_t MultiDMATransfer;            /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.

  440.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER

  441. 

  442.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */

  443. 

  444.   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.

  445.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY

  446. 

  447.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */

  448. 

  449. } LL_ADC_CommonInitTypeDef;

  450. 

  451. /**

  452.   * @brief  Structure definition of some features of ADC instance.

  453.   * @note   These parameters have an impact on ADC scope: ADC instance.

  454.   *         Affects both group regular and group injected (availability

  455.   *         of ADC group injected depends on STM32 families).

  456.   *         Refer to corresponding unitary functions into

  457.   *         @ref ADC_LL_EF_Configuration_ADC_Instance .

  458.   * @note   The setting of these parameters by function @ref LL_ADC_Init()

  459.   *         is conditioned to ADC state:

  460.   *         ADC instance must be disabled.

  461.   *         This condition is applied to all ADC features, for efficiency

  462.   *         and compatibility over all STM32 families. However, the different

  463.   *         features can be set under different ADC state conditions

  464.   *         (setting possible with ADC enabled without conversion on going,

  465.   *         ADC enabled with conversion on going, ...)

  466.   *         Each feature can be updated afterwards with a unitary function

  467.   *         and potentially with ADC in a different state than disabled,

  468.   *         refer to description of each function for setting

  469.   *         conditioned to ADC state.

  470.   */

  471. typedef struct

  472. {

  473.   uint32_t Resolution;                  /*!< Set ADC resolution.

  474.                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION

  475. 

  476.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */

  477. 

  478.   uint32_t LeftBitShift;                /*!< Configures the left shifting applied to the final result with or without oversampling.

  479.                                              This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */

  480. 

  481.   uint32_t LowPowerMode;                /*!< Set ADC low power mode.

  482.                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE

  483. 

  484.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */

  485. 

  486. } LL_ADC_InitTypeDef;

  487. 

  488. /**

  489.   * @brief  Structure definition of some features of ADC group regular.

  490.   * @note   These parameters have an impact on ADC scope: ADC group regular.

  491.   *         Refer to corresponding unitary functions into

  492.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  493.   *         (functions with prefix "REG").

  494.   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()

  495.   *         is conditioned to ADC state:

  496.   *         ADC instance must be disabled.

  497.   *         This condition is applied to all ADC features, for efficiency

  498.   *         and compatibility over all STM32 families. However, the different

  499.   *         features can be set under different ADC state conditions

  500.   *         (setting possible with ADC enabled without conversion on going,

  501.   *         ADC enabled with conversion on going, ...)

  502.   *         Each feature can be updated afterwards with a unitary function

  503.   *         and potentially with ADC in a different state than disabled,

  504.   *         refer to description of each function for setting

  505.   *         conditioned to ADC state.

  506.   */

  507. typedef struct

  508. {

  509.   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

  510.                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE

  511.                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge

  512.                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).

  513.                                                    In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().

  514. 

  515.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */

  516. 

  517.   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.

  518.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH

  519. 

  520.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */

  521. 

  522.   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  523.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE

  524.                                              @note This parameter has an effect only if group regular sequencer is enabled

  525.                                                    (scan length of 2 ranks or more).

  526. 

  527.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */

  528. 

  529.   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).

  530.                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE

  531.                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

  532. 

  533.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */

  534. 

  535.   uint32_t DataTransferMode;            /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.

  536.                                              This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE

  537. 

  538.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */

  539. 

  540.   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:

  541.                                              data preserved or overwritten.

  542.                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR

  543. 

  544.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */

  545. 

  546. } LL_ADC_REG_InitTypeDef;

  547. 

  548. /**

  549.   * @brief  Structure definition of some features of ADC group injected.

  550.   * @note   These parameters have an impact on ADC scope: ADC group injected.

  551.   *         Refer to corresponding unitary functions into

  552.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  553.   *         (functions with prefix "INJ").

  554.   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()

  555.   *         is conditioned to ADC state:

  556.   *         ADC instance must be disabled.

  557.   *         This condition is applied to all ADC features, for efficiency

  558.   *         and compatibility over all STM32 families. However, the different

  559.   *         features can be set under different ADC state conditions

  560.   *         (setting possible with ADC enabled without conversion on going,

  561.   *         ADC enabled with conversion on going, ...)

  562.   *         Each feature can be updated afterwards with a unitary function

  563.   *         and potentially with ADC in a different state than disabled,

  564.   *         refer to description of each function for setting

  565.   *         conditioned to ADC state.

  566.   */

  567. typedef struct

  568. {

  569.   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

  570.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE

  571.                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge

  572.                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).

  573.                                                    In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().

  574. 

  575.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */

  576. 

  577.   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.

  578.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH

  579. 

  580.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */

  581. 

  582.   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  583.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE

  584.                                              @note This parameter has an effect only if group injected sequencer is enabled

  585.                                                    (scan length of 2 ranks or more).

  586. 

  587.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */

  588. 

  589.   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.

  590.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO

  591.                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

  592. 

  593.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */

  594. 

  595. } LL_ADC_INJ_InitTypeDef;

  596. 

  597. /**

  598.   * @}

  599.   */

  600. #endif /* USE_FULL_LL_DRIVER */

  601. 

  602. /* Exported constants --------------------------------------------------------*/

  603. /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants

  604.   * @{

  605.   */

  606. 

  607. /** @defgroup ADC_LL_EC_FLAG ADC flags

  608.   * @brief    Flags defines which can be used with LL_ADC_ReadReg function

  609.   * @{

  610.   */

  611. #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */

  612. #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */

  613. #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */

  614. #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */

  615. #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */

  616. #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */

  617. #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */

  618. #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */

  619. #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */

  620. #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */

  621. #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */

  622. #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */

  623. #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */

  624. #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */

  625. #define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */

  626. #define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */

  627. #define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */

  628. #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */

  629. #define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */

  630. #define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */

  631. #define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */

  632. #define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */

  633. #define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */

  634. #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */

  635. #define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */

  636. #define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */

  637. #define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */

  638. #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */

  639. #define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */

  640. #define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */

  641. #define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */

  642. #define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */

  643. #define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */

  644. /**

  645.   * @}

  646.   */

  647. 

  648. /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)

  649.   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions

  650.   * @{

  651.   */

  652. #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */

  653. #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */

  654. #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */

  655. #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */

  656. #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */

  657. #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */

  658. #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */

  659. #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */

  660. #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */

  661. #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */

  662. #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */

  663. /**

  664.   * @}

  665.   */

  666. 

  667. /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose

  668.   * @{

  669.   */

  670. /* List of ADC registers intended to be used (most commonly) with             */

  671. /* DMA transfer.                                                              */

  672. /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */

  673. #define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

  674. #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

  675. /**

  676.   * @}

  677.   */

  678. 

  679. /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source

  680.   * @{

  681.   */

  682. #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */

  683. #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */

  684. #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */

  685. #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */

  686. #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */

  687. #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */

  688. #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */

  689. #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */

  690. #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */

  691. #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */

  692. #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */

  693. #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */

  694. #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */

  695. #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */

  696. #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */

  697. /**

  698.   * @}

  699.   */

  700. 

  701. /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels

  702.   * @{

  703.   */

  704. /* Note: Other measurement paths to internal channels may be available        */

  705. /*       (connections to other peripherals).                                  */

  706. /*       If they are not listed below, they do not require any specific       */

  707. /*       path enable. In this case, Access to measurement path is done        */

  708. /*       only by selecting the corresponding ADC internal channel.            */

  709. #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement pathes all disabled */

  710. #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */

  711. #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */

  712. #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */

  713. /**

  714.   * @}

  715.   */

  716. 

  717. /** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode

  718.   * @{

  719.   */

  720. #define LL_ADC_BOOST_MODE_6MHZ25   (0x00000000UL)                                            /*!< Boost mode is configured for frequency <= 6.25Mhz           */

  721. #define LL_ADC_BOOST_MODE_12MHZ5   (                                        ADC_CR_BOOST_0)  /*!< Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz */

  722. #define LL_ADC_BOOST_MODE_20MHZ    (                       ADC_CR_BOOST_1                 )  /*!< Boost mode is configured for 12.5Mhz < frequency <= 20Mhz   */

  723. #define LL_ADC_BOOST_MODE_25MHZ    ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1                 )  /*!< Boost mode is configured for 20Mhz   < frequency <= 25Mhz   */

  724. #define LL_ADC_BOOST_MODE_50MHZ    ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)  /*!< Boost mode is configured for frequency > 25Mhz              */

  725. /**

  726.   * @}

  727.   */

  728. 

  729. /** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY  ADC instance - Calibration mode for offset and linearity

  730.   * @{

  731.   */

  732. #define LL_ADC_CALIB_OFFSET                (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)                      /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */

  733. #define LL_ADC_CALIB_LINEARITY             (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)                   /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */

  734. #define LL_ADC_CALIB_OFFSET_LINEARITY      (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */

  735. /**

  736.   * @}

  737.   */

  738. 

  739. /** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD  ADC instance - Calibration linearity words

  740.   * @{

  741.   */

  742. #define LL_ADC_CALIB_LINEARITY_WORD1       (ADC_CR_LINCALRDYW1)    /*!< ADC calibration linearity word 1 */

  743. #define LL_ADC_CALIB_LINEARITY_WORD2       (ADC_CR_LINCALRDYW2)    /*!< ADC calibration linearity word 2 */

  744. #define LL_ADC_CALIB_LINEARITY_WORD3       (ADC_CR_LINCALRDYW3)    /*!< ADC calibration linearity word 3 */

  745. #define LL_ADC_CALIB_LINEARITY_WORD4       (ADC_CR_LINCALRDYW4)    /*!< ADC calibration linearity word 4 */

  746. #define LL_ADC_CALIB_LINEARITY_WORD5       (ADC_CR_LINCALRDYW5)    /*!< ADC calibration linearity word 5 */

  747. #define LL_ADC_CALIB_LINEARITY_WORD6       (ADC_CR_LINCALRDYW6)    /*!< ADC calibration linearity word 6 */

  748. /**

  749.   * @}

  750.   */

  751. 

  752. /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution

  753.   * @{

  754.   */

  755. #define LL_ADC_RESOLUTION_16B              (0x00000000UL)                                   /*!< ADC resolution 16 bits */

  756. #define LL_ADC_RESOLUTION_14B              (                                ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */

  757. #define LL_ADC_RESOLUTION_12B              (               ADC_CFGR_RES_1                 ) /*!< ADC resolution 12 bits */

  758. #define LL_ADC_RESOLUTION_10B              (               ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */

  759. #if defined (ADC_VER_V5_3)

  760. #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution  8 bits */

  761. #else

  762. #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_2                                ) /*!< ADC resolution  8 bits */

  763. #endif

  764. /**

  765.   * @}

  766.   */

  767. 

  768. /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT   ADC left Shift

  769.   * @{

  770.   */

  771. #define LL_ADC_LEFT_BIT_SHIFT_NONE  (0x00000000UL)                                                                       /*!< ADC no bit shift left applied on the final ADC convesion data */

  772. #define LL_ADC_LEFT_BIT_SHIFT_1     (ADC_CFGR2_LSHIFT_0)                                                                 /*!< ADC 1 bit shift left applied on the final ADC convesion data */

  773. #define LL_ADC_LEFT_BIT_SHIFT_2     (ADC_CFGR2_LSHIFT_1)                                                                 /*!< ADC 2 bits shift left applied on the final ADC convesion data */

  774. #define LL_ADC_LEFT_BIT_SHIFT_3     (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 3 bits shift left applied on the final ADC convesion data */

  775. #define LL_ADC_LEFT_BIT_SHIFT_4     (ADC_CFGR2_LSHIFT_2)                                                                 /*!< ADC 4 bits shift left applied on the final ADC convesion data */

  776. #define LL_ADC_LEFT_BIT_SHIFT_5     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 5 bits shift left applied on the final ADC convesion data */

  777. #define LL_ADC_LEFT_BIT_SHIFT_6     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 6 bits shift left applied on the final ADC convesion data */

  778. #define LL_ADC_LEFT_BIT_SHIFT_7     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 7 bits shift left applied on the final ADC convesion data */

  779. #define LL_ADC_LEFT_BIT_SHIFT_8     (ADC_CFGR2_LSHIFT_3)                                                                 /*!< ADC 8 bits shift left applied on the final ADC convesion data */

  780. #define LL_ADC_LEFT_BIT_SHIFT_9     (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 9 bits shift left applied on the final ADC convesion data */

  781. #define LL_ADC_LEFT_BIT_SHIFT_10    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 10 bits shift left applied on the final ADC convesion data */

  782. #define LL_ADC_LEFT_BIT_SHIFT_11    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 11 bits shift left applied on the final ADC convesion data */

  783. #define LL_ADC_LEFT_BIT_SHIFT_12    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)                                            /*!< ADC 12 bits shift left applied on the final ADC convesion data */

  784. #define LL_ADC_LEFT_BIT_SHIFT_13    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 13 bits shift left applied on the final ADC convesion data */

  785. #define LL_ADC_LEFT_BIT_SHIFT_14    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                       /*!< ADC 14 bits shift left applied on the final ADC convesion data */

  786. #define LL_ADC_LEFT_BIT_SHIFT_15    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)  /*!< ADC 15 bits shift left applied on the final ADC convesion data */

  787. /**

  788.   * @}

  789.   */

  790. 

  791. /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode

  792.   * @{

  793.   */

  794. #define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low power mode activated */

  795. #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */

  796. /**

  797.   * @}

  798.   */

  799. 

  800. /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number

  801.   * @{

  802.   */

  803. #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  804. #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  805. #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  806. #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

  807. /**

  808.   * @}

  809.   */

  810. 

  811. /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode

  812.   * @{

  813.   */

  814. #define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE   (0x00000000UL)   /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */

  815. #define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE    (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */

  816. /**

  817.   * @}

  818.   */

  819. 

  820. /** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift

  821.   * @{

  822.   */

  823. #define LL_ADC_OFFSET_RSHIFT_DISABLE   (0x00000000UL)      /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */

  824. #define LL_ADC_OFFSET_RSHIFT_ENABLE    (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */

  825. /**

  826.   * @}

  827.   */

  828. /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups

  829.   * @{

  830.   */

  831. #define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */

  832. #define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/

  833. #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected */

  834. /**

  835.   * @}

  836.   */

  837. 

  838. /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number

  839.   * @{

  840.   */

  841. #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */

  842. #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */

  843. #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */

  844. #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */

  845. #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */

  846. #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */

  847. #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */

  848. #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */

  849. #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */

  850. #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */

  851. #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */

  852. #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */

  853. #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */

  854. #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */

  855. #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */

  856. #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */

  857. #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */

  858. #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */

  859. #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */

  860. #define LL_ADC_CHANNEL_19                  (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */

  861. #if defined(ADC3)

  862. /*!< ADC3 is defined only in the case of STM32H7XX */

  863. #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */

  864. #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */

  865. #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */

  866. #else

  867. /*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */

  868. #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2. */

  869. #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC2. */

  870. #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC2. */

  871. #endif

  872. #define LL_ADC_CHANNEL_DAC1CH1_ADC2        (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */

  873. #define LL_ADC_CHANNEL_DAC1CH2_ADC2        (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */

  874. #if defined(DAC2)

  875. /*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */

  876. #define LL_ADC_CHANNEL_DAC2CH1_ADC2        (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */

  877. #endif

  878. /**

  879.   * @}

  880.   */

  881. 

  882. /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source

  883.   * @{

  884.   */

  885. #define LL_ADC_REG_TRIG_SOFTWARE          (0x00000000UL)                                                                                                    /*!< ADC group regular conversion trigger internal: SW start. */

  886. #define LL_ADC_REG_TRIG_EXT_TIM1_CH1      (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                   /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  887. #define LL_ADC_REG_TRIG_EXT_TIM1_CH2      (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  888. #define LL_ADC_REG_TRIG_EXT_TIM1_CH3      (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  889. #define LL_ADC_REG_TRIG_EXT_TIM2_CH2      (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  890. #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO     (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */

  891. #define LL_ADC_REG_TRIG_EXT_TIM4_CH4      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  892. #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */

  893. #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */

  894. #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2    (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */

  895. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */

  896. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */

  897. #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */

  898. #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */

  899. #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */

  900. #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */

  901. #define LL_ADC_REG_TRIG_EXT_TIM3_CH4      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  902. #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1    (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */

  903. #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */

  904. #define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */

  905. #define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */

  906. #define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */

  907. /**

  908.   * @}

  909.   */

  910. 

  911. /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge

  912.   * @{

  913.   */

  914. #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */

  915. #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */

  916. #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */

  917. /**

  918.   * @}

  919.   */

  920. 

  921. /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode

  922.   * @{

  923.   */

  924. #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are performed in single mode: one conversion per trigger */

  925. #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */

  926. /**

  927.   * @}

  928.   */

  929. 

  930. /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE  ADC group regular - Data transfer mode of ADC conversion data

  931.   * @{

  932.   */

  933. #define LL_ADC_REG_DR_TRANSFER             (0x00000000UL)                        /*!< ADC conversions are transferred to DR rigister */

  934. #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                   ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */

  935. #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */

  936. #define LL_ADC_REG_DFSDM_TRANSFER          (ADC_CFGR_DMNGT_1                   ) /*!< ADC conversion data are transferred to DFSDM */

  937. /**

  938.   * @}

  939.   */

  940. 

  941. /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data

  942.   * @{

  943.   */

  944. #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior in case of overrun: data preserved */

  945. #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */

  946. /**

  947.   * @}

  948.   */

  949. 

  950. /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length

  951.   * @{

  952.   */

  953. #define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                              /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  954. #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */

  955. #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */

  956. #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */

  957. #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */

  958. #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */

  959. #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */

  960. #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */

  961. #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */

  962. #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */

  963. #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */

  964. #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */

  965. #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */

  966. #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */

  967. #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */

  968. #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */

  969. /**

  970.   * @}

  971.   */

  972. 

  973. /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode

  974.   * @{

  975.   */

  976. #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                                               /*!< ADC group regular sequencer discontinuous mode disable */

  977. #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */

  978. #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */

  979. #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */

  980. #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */

  981. #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */

  982. #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */

  983. #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */

  984. #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */

  985. /**

  986.   * @}

  987.   */

  988. 

  989. /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks

  990.   * @{

  991.   */

  992. #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */

  993. #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */

  994. #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */

  995. #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */

  996. #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */

  997. #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */

  998. #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */

  999. #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */

  1000. #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */

  1001. #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */

  1002. #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */

  1003. #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */

  1004. #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */

  1005. #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */

  1006. #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */

  1007. #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */

  1008. /**

  1009.   * @}

  1010.   */

  1011. 

  1012. /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source

  1013.   * @{

  1014.   */

  1015. #define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                                                                                         /*!< ADC group injected conversion trigger internal: SW start. */

  1016. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                        /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */

  1017. #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1018. #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */

  1019. #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1020. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1021. #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */

  1022. #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */

  1023. #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1024. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */

  1025. #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */

  1026. #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */

  1027. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1028. #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                            /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */

  1029. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1030. #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */

  1031. #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */

  1032. #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                                   /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */

  1033. #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */

  1034. #define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */

  1035. #define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */

  1036. #define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  1037. /**

  1038.   * @}

  1039.   */

  1040. 

  1041. /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge

  1042.   * @{

  1043.   */

  1044. #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */

  1045. #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */

  1046. #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */

  1047. /**

  1048.   * @}

  1049.   */

  1050. 

  1051. /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode

  1052.   * @{

  1053.   */

  1054. #define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */

  1055. #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */

  1056. /**

  1057.   * @}

  1058.   */

  1059. 

  1060. /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode

  1061.   * @{

  1062.   */

  1063. #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */

  1064. #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */

  1065. #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

  1066. /**

  1067.   * @}

  1068.   */

  1069. 

  1070. /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length

  1071.   * @{

  1072.   */

  1073. #define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  1074. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */

  1075. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */

  1076. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */

  1077. /**

  1078.   * @}

  1079.   */

  1080. 

  1081. /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode

  1082.   * @{

  1083.   */

  1084. #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer discontinuous mode disable */

  1085. #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */

  1086. /**

  1087.   * @}

  1088.   */

  1089. 

  1090. /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks

  1091.   * @{

  1092.   */

  1093. #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */

  1094. #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */

  1095. #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */

  1096. #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */

  1097. /**

  1098.   * @}

  1099.   */

  1100. 

  1101. /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time

  1102.   * @{

  1103.   */

  1104. #define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000UL)                                              /*!< Sampling time 1.5 ADC clock cycles */

  1105. #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */

  1106. #define LL_ADC_SAMPLINGTIME_8CYCLES_5      (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 8.5 ADC clock cycles */

  1107. #define LL_ADC_SAMPLINGTIME_16CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */

  1108. #define LL_ADC_SAMPLINGTIME_32CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 32.5 ADC clock cycles */

  1109. #define LL_ADC_SAMPLINGTIME_64CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */

  1110. #define LL_ADC_SAMPLINGTIME_387CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 387.5 ADC clock cycles */

  1111. #define LL_ADC_SAMPLINGTIME_810CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */

  1112. /**

  1113.   * @}

  1114.   */

  1115. 

  1116. /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending

  1117.   * @{

  1118.   */

  1119. #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */

  1120. #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */

  1121. #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */

  1122. /**

  1123.   * @}

  1124.   */

  1125. 

  1126. /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number

  1127.   * @{

  1128.   */

  1129. #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */

  1130. #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */

  1131. #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */

  1132. /**

  1133.   * @}

  1134.   */

  1135. 

  1136. /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels

  1137.   * @{

  1138.   */

  1139. #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                                      /*!< ADC analog watchdog monitoring disabled */

  1140. #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */

  1141. #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */

  1142. #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */

  1143. #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */

  1144. #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */

  1145. #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */

  1146. #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */

  1147. #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */

  1148. #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */

  1149. #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */

  1150. #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */

  1151. #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */

  1152. #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */

  1153. #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */

  1154. #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */

  1155. #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */

  1156. #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */

  1157. #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */

  1158. #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */

  1159. #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */

  1160. #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */

  1161. #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */

  1162. #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */

  1163. #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */

  1164. #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */

  1165. #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */

  1166. #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */

  1167. #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */

  1168. #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */

  1169. #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */

  1170. #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */

  1171. #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */

  1172. #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */

  1173. #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */

  1174. #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */

  1175. #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */

  1176. #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */

  1177. #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */

  1178. #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */

  1179. #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */

  1180. #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */

  1181. #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */

  1182. #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */

  1183. #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */

  1184. #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */

  1185. #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */

  1186. #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */

  1187. #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */

  1188. #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */

  1189. #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */

  1190. #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */

  1191. #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */

  1192. #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */

  1193. #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */

  1194. #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */

  1195. #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */

  1196. #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */

  1197. #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */

  1198. #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */

  1199. #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */

  1200. #define LL_ADC_AWD_CHANNEL_19_REG          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */

  1201. #define LL_ADC_AWD_CHANNEL_19_INJ          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */

  1202. #define LL_ADC_AWD_CHANNEL_19_REG_INJ      ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */

  1203. #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */

  1204. #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */

  1205. #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */

  1206. #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */

  1207. #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */

  1208. #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */

  1209. #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */

  1210. #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */

  1211. #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */

  1212. #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */

  1213. #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */

  1214. #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */

  1215. #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */

  1216. #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */

  1217. #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */

  1218. /**

  1219.   * @}

  1220.   */

  1221. 

  1222. /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds

  1223.   * @{

  1224.   */

  1225. #define LL_ADC_AWD_THRESHOLD_HIGH          (0x1UL)                     /*!< ADC analog watchdog threshold high */

  1226. #define LL_ADC_AWD_THRESHOLD_LOW           (0x0UL)                     /*!< ADC analog watchdog threshold low */

  1227. /**

  1228.   * @}

  1229.   */

  1230. 

  1231. /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope

  1232.   * @{

  1233.   */

  1234. #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */

  1235. #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */

  1236. #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */

  1237. #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */

  1238. #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */

  1239. /**

  1240.   * @}

  1241.   */

  1242. 

  1243. /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode

  1244.   * @{

  1245.   */

  1246. #define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */

  1247. #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */

  1248. /**

  1249.   * @}

  1250.   */

  1251. 

  1252. /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift

  1253.   * @{

  1254.   */

  1255. #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                                              /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */

  1256. #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */

  1257. #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */

  1258. #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */

  1259. #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */

  1260. #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */

  1261. #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */

  1262. #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */

  1263. #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */

  1264. #define LL_ADC_OVS_SHIFT_RIGHT_9           (ADC_CFGR2_OVSS_3                                       | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */

  1265. #define LL_ADC_OVS_SHIFT_RIGHT_10          (ADC_CFGR2_OVSS_3                    | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */

  1266. #define LL_ADC_OVS_SHIFT_RIGHT_11          (ADC_CFGR2_OVSS_3                    | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */

  1267. /**

  1268.   * @}

  1269.   */

  1270. 

  1271. /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode

  1272.   * @{

  1273.   */

  1274. #define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                                                      /*!< ADC dual mode disabled (ADC independent mode) */

  1275. #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */

  1276. #define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */

  1277. #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */

  1278. #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */

  1279. #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */

  1280. #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */

  1281. #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */

  1282. /**

  1283.   * @}

  1284.   */

  1285. 

  1286. /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer

  1287.   * @{

  1288.   */

  1289. #define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                      /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */

  1290. #define LL_ADC_MULTI_REG_DMA_RES_32_10B      (ADC_CCR_DAMDF_1                  ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */

  1291. #define LL_ADC_MULTI_REG_DMA_RES_8B          (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */

  1292. /**

  1293.   * @}

  1294.   */

  1295. 

  1296. /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases

  1297.   * @{

  1298.   */

  1299. #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5           (0x00000000UL)                                                          /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution                    */

  1300. #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5          (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution                   */

  1301. #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5          (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution                   */

  1302. #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5          (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */

  1303. #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS   (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles  for 8 bits resolution               */

  1304. #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5          (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution       */

  1305. #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution               */

  1306. #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution            */

  1307. #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5          (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution         */

  1308. #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution               */

  1309. #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5          (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution               */

  1310. #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution                 */

  1311. #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution           */

  1312. /**

  1313.   * @}

  1314.   */

  1315. 

  1316. /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave

  1317.   * @{

  1318.   */

  1319. #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */

  1320. #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */

  1321. #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */

  1322. /**

  1323.   * @}

  1324.   */

  1325. 

  1326. 

  1327. 

  1328. /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays

  1329.   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,

  1330.   *         not timeout values.

  1331.   *         For details on delays values, refer to descriptions in source code

  1332.   *         above each literal definition.

  1333.   * @{

  1334.   */

  1335. 

  1336. /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */

  1337. /*       not timeout values.                                                  */

  1338. /*       Timeout values for ADC operations are dependent to device clock      */

  1339. /*       configuration (system clock versus ADC clock),                       */

  1340. /*       and therefore must be defined in user application.                   */

  1341. /*       Indications for estimation of ADC timeout delays, for this           */

  1342. /*       STM32 serie:                                                         */

  1343. /*       - ADC calibration time: maximum delay is 16384/fADC.                   */

  1344. /*         (refer to device datasheet, parameter "tCAL")                      */

  1345. /*       - ADC enable time: maximum delay is 1 conversion cycle.              */

  1346. /*         (refer to device datasheet, parameter "tSTAB")                     */

  1347. /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */

  1348. /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */

  1349. /*         cycles                                                             */

  1350. /*       - ADC conversion time: duration depending on ADC clock and ADC       */

  1351. /*         configuration.                                                     */

  1352. /*         (refer to device reference manual, section "Timing")               */

  1353. 

  1354. /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */

  1355. /* Delay set to maximum value (refer to device datasheet,                     */

  1356. /* parameter "tADCVREG_STUP").                                                */

  1357. /* Unit: us                                                                   */

  1358. #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */

  1359. 

  1360. /* Delay for internal voltage reference stabilization time.                   */

  1361. /* Delay set to maximum value (refer to device datasheet,                     */

  1362. /* parameter "ts_vrefint").                                                   */

  1363. /* Unit: us                                                                   */

  1364. #define LL_ADC_DELAY_VREFINT_STAB_US       (5UL)  /*!< Delay for internal voltage reference stabilization time */

  1365. 

  1366. /* Delay for temperature sensor stabilization time.                           */

  1367. /* Literal set to maximum value (refer to device datasheet,                   */

  1368. /* parameter "tSTART_RUN").                                                   */

  1369. /* Unit: us                                                                   */

  1370. #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ( 26UL)  /*!< Delay for temperature sensor stabilization time */

  1371. 

  1372. /* Delay required between ADC end of calibration and ADC enable.              */

  1373. /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */

  1374. /*       are required between ADC end of calibration and ADC enable.          */

  1375. /*       Wait time can be computed in user application by waiting for the     */

  1376. /*       equivalent number of CPU cycles, by taking into account              */

  1377. /*       ratio of CPU clock versus ADC clock prescalers.                      */

  1378. /* Unit: ADC clock cycles.                                                    */

  1379. #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (  4UL)  /*!< Delay required between ADC end of calibration and ADC enable */

  1380. 

  1381. /* Fixed timeout value for ADC linearity word bit set/clear delay.                         */

  1382. /* Values defined to be higher than worst cases: low clock frequency,                      */

  1383. /* maximum prescalers.                                                                     */

  1384. /* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value                         */

  1385. /* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB  */

  1386. /*           6 / 4577 = 1,311ms                                                            */

  1387. /* At maximum CPU speed (400 MHz), this means                                              */

  1388. /*    3.58 * 400 MHz = 524400 CPU cycles                                                   */

  1389. #define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT         (524400UL)      /*!< ADC linearity set/clear bit delay */

  1390. 

  1391. /**

  1392.   * @}

  1393.   */

  1394. 

  1395. /**

  1396.   * @}

  1397.   */

  1398. 

  1399. 

  1400. /* Exported macro ------------------------------------------------------------*/

  1401. /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros

  1402.   * @{

  1403.   */

  1404. 

  1405. /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros

  1406.   * @{

  1407.   */

  1408. 

  1409. /**

  1410.   * @brief  Write a value in ADC register

  1411.   * @param  __INSTANCE__ ADC Instance

  1412.   * @param  __REG__ Register to be written

  1413.   * @param  __VALUE__ Value to be written in the register

  1414.   * @retval None

  1415.   */

  1416. #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

  1417. 

  1418. /**

  1419.   * @brief  Read a value in ADC register

  1420.   * @param  __INSTANCE__ ADC Instance

  1421.   * @param  __REG__ Register to be read

  1422.   * @retval Register value

  1423.   */

  1424. #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

  1425. /**

  1426.   * @}

  1427.   */

  1428. 

  1429. /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro

  1430.   * @{

  1431.   */

  1432. 

  1433. /**

  1434.   * @brief  Helper macro to get ADC channel number in decimal format

  1435.   *         from literals LL_ADC_CHANNEL_x.

  1436.   * @note   Example:

  1437.   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)

  1438.   *           will return decimal number "4".

  1439.   * @note   The input can be a value from functions where a channel

  1440.   *         number is returned, either defined with number

  1441.   *         or with bitfield (only one bit must be set).

  1442.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1443.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1444.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1445.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1446.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1447.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1448.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1449.   *         @arg @ref LL_ADC_CHANNEL_6

  1450.   *         @arg @ref LL_ADC_CHANNEL_7

  1451.   *         @arg @ref LL_ADC_CHANNEL_8

  1452.   *         @arg @ref LL_ADC_CHANNEL_9

  1453.   *         @arg @ref LL_ADC_CHANNEL_10

  1454.   *         @arg @ref LL_ADC_CHANNEL_11

  1455.   *         @arg @ref LL_ADC_CHANNEL_12

  1456.   *         @arg @ref LL_ADC_CHANNEL_13

  1457.   *         @arg @ref LL_ADC_CHANNEL_14

  1458.   *         @arg @ref LL_ADC_CHANNEL_15

  1459.   *         @arg @ref LL_ADC_CHANNEL_16

  1460.   *         @arg @ref LL_ADC_CHANNEL_17

  1461.   *         @arg @ref LL_ADC_CHANNEL_18

  1462.   *         @arg @ref LL_ADC_CHANNEL_19

  1463.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1464.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1465.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1466.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1467.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1468.   *

  1469.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1470.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1471.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1472.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  1473.   * @retval Value between Min_Data=0 and Max_Data=18

  1474.   */

  1475. #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \

  1476.   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL)                                 \

  1477.    ? (                                                                                     \

  1478.        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \

  1479.      )                                                                                     \

  1480.    :                                                                                       \

  1481.    (                                                                                       \

  1482.        (uint32_t)POSITION_VAL((__CHANNEL__))                                               \

  1483.    )                                                                                       \

  1484.   )

  1485. 

  1486. /**

  1487.   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x

  1488.   *         from number in decimal format.

  1489.   * @note   Example:

  1490.   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)

  1491.   *           will return a data equivalent to "LL_ADC_CHANNEL_4".

  1492.   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18

  1493.   * @retval Returned value can be one of the following values:

  1494.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1495.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1496.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1497.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1498.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1499.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1500.   *         @arg @ref LL_ADC_CHANNEL_6

  1501.   *         @arg @ref LL_ADC_CHANNEL_7

  1502.   *         @arg @ref LL_ADC_CHANNEL_8

  1503.   *         @arg @ref LL_ADC_CHANNEL_9

  1504.   *         @arg @ref LL_ADC_CHANNEL_10

  1505.   *         @arg @ref LL_ADC_CHANNEL_11

  1506.   *         @arg @ref LL_ADC_CHANNEL_12

  1507.   *         @arg @ref LL_ADC_CHANNEL_13

  1508.   *         @arg @ref LL_ADC_CHANNEL_14

  1509.   *         @arg @ref LL_ADC_CHANNEL_15

  1510.   *         @arg @ref LL_ADC_CHANNEL_16

  1511.   *         @arg @ref LL_ADC_CHANNEL_17

  1512.   *         @arg @ref LL_ADC_CHANNEL_18

  1513.   *         @arg @ref LL_ADC_CHANNEL_19

  1514.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1515.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1516.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1517.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1518.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1519.   *

  1520.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1521.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1522.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1523.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  1524.   *         (1, 2) For ADC channel read back from ADC register,

  1525.   *                comparison with internal channel parameter to be done

  1526.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1527.   */

  1528. #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \

  1529.   (((__DECIMAL_NB__) <= 9UL)                                                                            \

  1530.    ? (                                                                                                  \

  1531.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \

  1532.        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \

  1533.        (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \

  1534.      )                                                                                                  \

  1535.    :                                                                                                    \

  1536.    (                                                                                                    \

  1537.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \

  1538.        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \

  1539.        (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \

  1540.    )                                                                                                    \

  1541.   )

  1542. 

  1543. /**

  1544.   * @brief  Helper macro to determine whether the selected channel

  1545.   *         corresponds to literal definitions of driver.

  1546.   * @note   The different literal definitions of ADC channels are:

  1547.   *         - ADC internal channel:

  1548.   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...

  1549.   *         - ADC external channel (channel connected to a GPIO pin):

  1550.   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...

  1551.   * @note   The channel parameter must be a value defined from literal

  1552.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1553.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1554.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),

  1555.   *         must not be a value from functions where a channel number is

  1556.   *         returned from ADC registers,

  1557.   *         because internal and external channels share the same channel

  1558.   *         number in ADC registers. The differentiation is made only with

  1559.   *         parameters definitions of driver.

  1560.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1561.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1562.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1563.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1564.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1565.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1566.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1567.   *         @arg @ref LL_ADC_CHANNEL_6

  1568.   *         @arg @ref LL_ADC_CHANNEL_7

  1569.   *         @arg @ref LL_ADC_CHANNEL_8

  1570.   *         @arg @ref LL_ADC_CHANNEL_9

  1571.   *         @arg @ref LL_ADC_CHANNEL_10

  1572.   *         @arg @ref LL_ADC_CHANNEL_11

  1573.   *         @arg @ref LL_ADC_CHANNEL_12

  1574.   *         @arg @ref LL_ADC_CHANNEL_13

  1575.   *         @arg @ref LL_ADC_CHANNEL_14

  1576.   *         @arg @ref LL_ADC_CHANNEL_15

  1577.   *         @arg @ref LL_ADC_CHANNEL_16

  1578.   *         @arg @ref LL_ADC_CHANNEL_17

  1579.   *         @arg @ref LL_ADC_CHANNEL_18

  1580.   *         @arg @ref LL_ADC_CHANNEL_19

  1581.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1582.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1583.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1584.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1585.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1586.   *

  1587.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1588.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1589.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1590.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  1591.   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).

  1592.   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

  1593.   */

  1594. #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \

  1595.   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)

  1596. 

  1597. /**

  1598.   * @brief  Helper macro to convert a channel defined from parameter

  1599.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1600.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1601.   *         to its equivalent parameter definition of a ADC external channel

  1602.   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

  1603.   * @note   The channel parameter can be, additionally to a value

  1604.   *         defined from parameter definition of a ADC internal channel

  1605.   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1606.   *         a value defined from parameter definition of

  1607.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1608.   *         or a value from functions where a channel number is returned

  1609.   *         from ADC registers.

  1610.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1611.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1612.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1613.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1614.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1615.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1616.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1617.   *         @arg @ref LL_ADC_CHANNEL_6

  1618.   *         @arg @ref LL_ADC_CHANNEL_7

  1619.   *         @arg @ref LL_ADC_CHANNEL_8

  1620.   *         @arg @ref LL_ADC_CHANNEL_9

  1621.   *         @arg @ref LL_ADC_CHANNEL_10

  1622.   *         @arg @ref LL_ADC_CHANNEL_11

  1623.   *         @arg @ref LL_ADC_CHANNEL_12

  1624.   *         @arg @ref LL_ADC_CHANNEL_13

  1625.   *         @arg @ref LL_ADC_CHANNEL_14

  1626.   *         @arg @ref LL_ADC_CHANNEL_15

  1627.   *         @arg @ref LL_ADC_CHANNEL_16

  1628.   *         @arg @ref LL_ADC_CHANNEL_17

  1629.   *         @arg @ref LL_ADC_CHANNEL_18

  1630.   *         @arg @ref LL_ADC_CHANNEL_19

  1631.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1632.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1633.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1634.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1635.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1636.   *

  1637.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1638.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1639.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1640.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  1641.   * @retval Returned value can be one of the following values:

  1642.   *         @arg @ref LL_ADC_CHANNEL_0

  1643.   *         @arg @ref LL_ADC_CHANNEL_1

  1644.   *         @arg @ref LL_ADC_CHANNEL_2

  1645.   *         @arg @ref LL_ADC_CHANNEL_3

  1646.   *         @arg @ref LL_ADC_CHANNEL_4

  1647.   *         @arg @ref LL_ADC_CHANNEL_5

  1648.   *         @arg @ref LL_ADC_CHANNEL_6

  1649.   *         @arg @ref LL_ADC_CHANNEL_7

  1650.   *         @arg @ref LL_ADC_CHANNEL_8

  1651.   *         @arg @ref LL_ADC_CHANNEL_9

  1652.   *         @arg @ref LL_ADC_CHANNEL_10

  1653.   *         @arg @ref LL_ADC_CHANNEL_11

  1654.   *         @arg @ref LL_ADC_CHANNEL_12

  1655.   *         @arg @ref LL_ADC_CHANNEL_13

  1656.   *         @arg @ref LL_ADC_CHANNEL_14

  1657.   *         @arg @ref LL_ADC_CHANNEL_15

  1658.   *         @arg @ref LL_ADC_CHANNEL_16

  1659.   *         @arg @ref LL_ADC_CHANNEL_17

  1660.   *         @arg @ref LL_ADC_CHANNEL_18

  1661.   *         @arg @ref LL_ADC_CHANNEL_19

  1662.   */

  1663. #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \

  1664.   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  1665. 

  1666. /**

  1667.   * @brief  Helper macro to determine whether the internal channel

  1668.   *         selected is available on the ADC instance selected.

  1669.   * @note   The channel parameter must be a value defined from parameter

  1670.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1671.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1672.   *         must not be a value defined from parameter definition of

  1673.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1674.   *         or a value from functions where a channel number is

  1675.   *         returned from ADC registers,

  1676.   *         because internal and external channels share the same channel

  1677.   *         number in ADC registers. The differentiation is made only with

  1678.   *         parameters definitions of driver.

  1679.   * @param  __ADC_INSTANCE__ ADC instance

  1680.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1681.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1682.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1683.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1684.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1685.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1686.   *

  1687.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1688.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

  1689.   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.

  1690.   *         Value "1" if the internal channel selected is available on the ADC instance selected.

  1691.   */

  1692. #if defined(ADC3)

  1693. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

  1694.   ((((__ADC_INSTANCE__) == ADC2)                                               \

  1695.     &&(                                                                        \

  1696.        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                       \

  1697.        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                          \

  1698.       )                                                                        \

  1699.    )                                                                           \

  1700.    ||                                                                          \

  1701.    (((__ADC_INSTANCE__) == ADC3)                                               \

  1702.     &&(                                                                        \

  1703.        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                       \

  1704.        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                       \

  1705.        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \

  1706.       )                                                                        \

  1707.    )                                                                           \

  1708.   )

  1709. #else

  1710. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

  1711.   ((((__ADC_INSTANCE__) == ADC2)                                               \

  1712.     &&(                                                                        \

  1713.        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                       \

  1714.        ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) ||                       \

  1715.        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                       \

  1716.        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                       \

  1717.        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \

  1718.       )                                                                        \

  1719.    )                                                                           \

  1720.   )

  1721. #endif

  1722. 

  1723. /**

  1724.   * @brief  Helper macro to define ADC analog watchdog parameter:

  1725.   *         define a single channel to monitor with analog watchdog

  1726.   *         from sequencer channel and groups definition.

  1727.   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().

  1728.   *         Example:

  1729.   *           LL_ADC_SetAnalogWDMonitChannels(

  1730.   *             ADC1, LL_ADC_AWD1,

  1731.   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))

  1732.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1733.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  1734.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  1735.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  1736.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  1737.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  1738.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  1739.   *         @arg @ref LL_ADC_CHANNEL_6

  1740.   *         @arg @ref LL_ADC_CHANNEL_7

  1741.   *         @arg @ref LL_ADC_CHANNEL_8

  1742.   *         @arg @ref LL_ADC_CHANNEL_9

  1743.   *         @arg @ref LL_ADC_CHANNEL_10

  1744.   *         @arg @ref LL_ADC_CHANNEL_11

  1745.   *         @arg @ref LL_ADC_CHANNEL_12

  1746.   *         @arg @ref LL_ADC_CHANNEL_13

  1747.   *         @arg @ref LL_ADC_CHANNEL_14

  1748.   *         @arg @ref LL_ADC_CHANNEL_15

  1749.   *         @arg @ref LL_ADC_CHANNEL_16

  1750.   *         @arg @ref LL_ADC_CHANNEL_17

  1751.   *         @arg @ref LL_ADC_CHANNEL_18

  1752.   *         @arg @ref LL_ADC_CHANNEL_19

  1753.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1754.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  1755.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1756.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  1757.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  1758.   *

  1759.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1760.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  1761.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  1762.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  1763.   *         (1, 2) For ADC channel read back from ADC register,

  1764.   *                comparison with internal channel parameter to be done

  1765.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1766.   * @param  __GROUP__ This parameter can be one of the following values:

  1767.   *         @arg @ref LL_ADC_GROUP_REGULAR

  1768.   *         @arg @ref LL_ADC_GROUP_INJECTED

  1769.   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED

  1770.   * @retval Returned value can be one of the following values:

  1771.   *         @arg @ref LL_ADC_AWD_DISABLE

  1772.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  1773.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

  1774.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  1775.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  1776.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

  1777.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  1778.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  1779.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

  1780.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  1781.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  1782.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

  1783.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  1784.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  1785.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

  1786.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  1787.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  1788.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

  1789.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  1790.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  1791.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

  1792.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  1793.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  1794.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

  1795.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  1796.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  1797.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

  1798.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  1799.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  1800.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

  1801.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  1802.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  1803.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

  1804.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  1805.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  1806.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

  1807.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  1808.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  1809.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

  1810.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  1811.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  1812.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

  1813.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  1814.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  1815.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

  1816.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  1817.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  1818.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

  1819.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  1820.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  1821.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

  1822.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  1823.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  1824.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

  1825.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  1826.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  1827.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

  1828.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  1829.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  1830.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

  1831.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  1832.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

  1833.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

  1834.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

  1835.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)

  1836.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)

  1837.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)

  1838.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)

  1839.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)

  1840.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)

  1841.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)

  1842.   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)

  1843.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)

  1844.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)

  1845.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)

  1846.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)

  1847.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)

  1848.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)

  1849.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)

  1850.   *

  1851.   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n

  1852.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  1853.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

  1854.   */

  1855. #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \

  1856.   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \

  1857.    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \

  1858.    :                                                                                                      \

  1859.    ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \

  1860.    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \

  1861.    :                                                                                                      \

  1862.    (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \

  1863.   )

  1864. 

  1865. /**

  1866.   * @brief  Helper macro to set the value of ADC analog watchdog threshold high

  1867.   *         or low in function of ADC resolution, when ADC resolution is

  1868.   *         different of 16 bits.

  1869.   * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().

  1870.   *         Example, with a ADC resolution of 8 bits, to set the value of

  1871.   *         analog watchdog threshold high (on 18 bits):

  1872.   *           LL_ADC_SetAnalogWDThresholds

  1873.   *            (< ADCx param >,

  1874.   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)

  1875.   *            );

  1876.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1877.   *         @arg @ref LL_ADC_RESOLUTION_16B

  1878.   *         @arg @ref LL_ADC_RESOLUTION_14B

  1879.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1880.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1881.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1882.   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

  1883.   * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

  1884.   */

  1885. #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \

  1886.   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

  1887. 

  1888. /**

  1889.   * @brief  Helper macro to get the value of ADC analog watchdog threshold high

  1890.   *         or low in function of ADC resolution, when ADC resolution is

  1891.   *         different of 16 bits.

  1892.   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().

  1893.   *         Example, with a ADC resolution of 8 bits, to get the value of

  1894.   *         analog watchdog threshold high (on 18 bits):

  1895.   *           < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION

  1896.   *            (LL_ADC_RESOLUTION_8B,

  1897.   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)

  1898.   *            );

  1899.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1900.   *         @arg @ref LL_ADC_RESOLUTION_16B

  1901.   *         @arg @ref LL_ADC_RESOLUTION_14B

  1902.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1903.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1904.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1905.   * @param  __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

  1906.   * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

  1907.   */

  1908. #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \

  1909.   ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

  1910. 

  1911. /**

  1912.   * @brief  Helper macro to set the ADC calibration value with both single ended

  1913.   *         and differential modes calibration factors concatenated.

  1914.   * @note   To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().

  1915.   *         Example, to set calibration factors single ended to 0x55

  1916.   *         and differential ended to 0x2A:

  1917.   *           LL_ADC_SetCalibrationOffsetFactor(

  1918.   *             ADC1,

  1919.   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))

  1920.   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F

  1921.   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F

  1922.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  1923.   */

  1924. #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \

  1925.   (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))

  1926. 

  1927. /**

  1928.   * @brief  Helper macro to get the ADC multimode conversion data of ADC master

  1929.   *         or ADC slave from raw value with both ADC conversion data concatenated.

  1930.   * @note   This macro is intended to be used when multimode transfer by DMA

  1931.   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().

  1932.   *         In this case the transferred data need to processed with this macro

  1933.   *         to separate the conversion data of ADC master and ADC slave.

  1934.   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:

  1935.   *         @arg @ref LL_ADC_MULTI_MASTER

  1936.   *         @arg @ref LL_ADC_MULTI_SLAVE

  1937.   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF

  1938.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  1939.   */

  1940. #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \

  1941.   (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)

  1942. 

  1943. /**

  1944.   * @brief  Helper macro to select, from a ADC instance, to which ADC instance

  1945.   *         it has a dependence in multimode (ADC master of the corresponding

  1946.   *         ADC common instance).

  1947.   * @note   In case of device with multimode available and a mix of

  1948.   *         ADC instances compliant and not compliant with multimode feature,

  1949.   *         ADC instances not compliant with multimode feature are

  1950.   *         considered as master instances (do not depend to

  1951.   *         any other ADC instance).

  1952.   * @param  __ADCx__ ADC instance

  1953.   * @retval __ADCx__ ADC instance master of the corresponding ADC common instance

  1954.   */

  1955. #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \

  1956.   ( ( ((__ADCx__) == ADC2)                                                     \

  1957.     )?                                                                         \

  1958.      (ADC1)                                                                    \

  1959.      :                                                                         \

  1960.      (__ADCx__)                                                                \

  1961.   )

  1962. 

  1963. /**

  1964.   * @brief  Helper macro to select the ADC common instance

  1965.   *         to which is belonging the selected ADC instance.

  1966.   * @note   ADC common register instance can be used for:

  1967.   *         - Set parameters common to several ADC instances

  1968.   *         - Multimode (for devices with several ADC instances)

  1969.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  1970.   * @param  __ADCx__ ADC instance

  1971.   * @retval ADC common register instance

  1972.   */

  1973. #if defined(ADC3_COMMON)

  1974. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  1975.   ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \

  1976.     ? (                                                                        \

  1977.        (ADC12_COMMON)                                                          \

  1978.       )                                                                        \

  1979.       :                                                                        \

  1980.       (                                                                        \

  1981.        (ADC3_COMMON)                                                           \

  1982.       )                                                                        \

  1983.   )

  1984. #else

  1985. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)   (ADC12_COMMON)

  1986. #endif

  1987. 

  1988. /**

  1989.   * @brief  Helper macro to check if all ADC instances sharing the same

  1990.   *         ADC common instance are disabled.

  1991.   * @note   This check is required by functions with setting conditioned to

  1992.   *         ADC state:

  1993.   *         All ADC instances of the ADC common group must be disabled.

  1994.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  1995.   * @note   On devices with only 1 ADC common instance, parameter of this macro

  1996.   *         is useless and can be ignored (parameter kept for compatibility

  1997.   *         with devices featuring several ADC common instances).

  1998.   * @param  __ADCXY_COMMON__ ADC common instance

  1999.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2000.   * @retval Value "0" if all ADC instances sharing the same ADC common instance

  2001.   *         are disabled.

  2002.   *         Value "1" if at least one ADC instance sharing the same ADC common instance

  2003.   *         is enabled.

  2004.   */

  2005. #if defined(ADC3_COMMON)

  2006. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  2007.   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \

  2008.     ? (                                                                        \

  2009.        (LL_ADC_IsEnabled(ADC1) |                                               \

  2010.         LL_ADC_IsEnabled(ADC2)  )                                              \

  2011.       )                                                                        \

  2012.       :                                                                        \

  2013.       (                                                                        \

  2014.        (LL_ADC_IsEnabled(ADC3))                                                \

  2015.       )                                                                        \

  2016.   )

  2017. #else

  2018. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  2019.                         (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))

  2020. #endif

  2021. 

  2022. /**

  2023.   * @brief  Helper macro to define the ADC conversion data full-scale digital

  2024.   *         value corresponding to the selected ADC resolution.

  2025.   * @note   ADC conversion data full-scale corresponds to voltage range

  2026.   *         determined by analog voltage references Vref+ and Vref-

  2027.   *         (refer to reference manual).

  2028.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  2029.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2030.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2031.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2032.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2033.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2034.   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)

  2035.   */

  2036. #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \

  2037.   (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))

  2038. 

  2039. /**

  2040.   * @brief  Helper macro to convert the ADC conversion data from

  2041.   *         a resolution to another resolution.

  2042.   * @param  __DATA__ ADC conversion data to be converted

  2043.   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted

  2044.   *         This parameter can be one of the following values:

  2045.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2046.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2047.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2048.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2049.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2050.   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion

  2051.   *         This parameter can be one of the following values:

  2052.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2053.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2054.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2055.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2056.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2057.   * @retval ADC conversion data to the requested resolution

  2058.   */

  2059. #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\

  2060.                                          __ADC_RESOLUTION_CURRENT__,\

  2061.                                          __ADC_RESOLUTION_TARGET__)            \

  2062.   (((__DATA__)                                                                 \

  2063.     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \

  2064.    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \

  2065.   )

  2066. 

  2067. /**

  2068.   * @brief  Helper macro to calculate the voltage (unit: mVolt)

  2069.   *         corresponding to a ADC conversion data (unit: digital value).

  2070.   * @note   Analog reference voltage (Vref+) must be either known from

  2071.   *         user board environment or can be calculated using ADC measurement

  2072.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2073.   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)

  2074.   * @param  __ADC_DATA__ ADC conversion data (resolution 16 bits)

  2075.   *                       (unit: digital value).

  2076.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  2077.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2078.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2079.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2080.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2081.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2082.   * @retval ADC conversion data equivalent voltage value (unit: mVolt)

  2083.   */

  2084. #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\

  2085.                                       __ADC_DATA__,\

  2086.                                       __ADC_RESOLUTION__)                      \

  2087.   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \

  2088.    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \

  2089.   )

  2090. 

  2091. /**

  2092.   * @brief  Helper macro to calculate analog reference voltage (Vref+)

  2093.   *         (unit: mVolt) from ADC conversion data of internal voltage

  2094.   *         reference VrefInt.

  2095.   * @note   Computation is using VrefInt calibration value

  2096.   *         stored in system memory for each device during production.

  2097.   * @note   This voltage depends on user board environment: voltage level

  2098.   *         connected to pin Vref+.

  2099.   *         On devices with small package, the pin Vref+ is not present

  2100.   *         and internally bonded to pin Vdda.

  2101.   * @note   On this STM32 serie, calibration data of internal voltage reference

  2102.   *         VrefInt corresponds to a resolution of 16 bits,

  2103.   *         this is the recommended ADC resolution to convert voltage of

  2104.   *         internal voltage reference VrefInt.

  2105.   *         Otherwise, this macro performs the processing to scale

  2106.   *         ADC conversion data to 16 bits.

  2107.   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)

  2108.   *         of internal voltage reference VrefInt (unit: digital value).

  2109.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  2110.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2111.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2112.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2113.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2114.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2115.   * @retval Analog reference voltage (unit: mV)

  2116.   */

  2117. #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\

  2118.                                          __ADC_RESOLUTION__)                   \

  2119.   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \

  2120.    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \

  2121.                                       (__ADC_RESOLUTION__),                    \

  2122.                                       LL_ADC_RESOLUTION_16B))

  2123. 

  2124. /**

  2125.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  2126.   *         from ADC conversion data of internal temperature sensor.

  2127.   * @note   Computation is using temperature sensor calibration values

  2128.   *         stored in system memory for each device during production.

  2129.   * @note   Calculation formula:

  2130.   *           Temperature = ((TS_ADC_DATA - TS_CAL1)

  2131.   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))

  2132.   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP

  2133.   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC

  2134.   *                Avg_Slope = (TS_CAL2 - TS_CAL1)

  2135.   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)

  2136.   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature

  2137.   *                            TEMP_DEGC_CAL1 (calibrated in factory)

  2138.   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature

  2139.   *                            TEMP_DEGC_CAL2 (calibrated in factory)

  2140.   *         Caution: Calculation relevancy under reserve that calibration

  2141.   *                  parameters are correct (address and data).

  2142.   *                  To calculate temperature using temperature sensor

  2143.   *                  datasheet typical values (generic values less, therefore

  2144.   *                  less accurate than calibrated values),

  2145.   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().

  2146.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  2147.   *         defined as it impacts the ADC LSB equivalent voltage.

  2148.   * @note   Analog reference voltage (Vref+) must be either known from

  2149.   *         user board environment or can be calculated using ADC measurement

  2150.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2151.   * @note   On this STM32 serie, calibration data of temperature sensor

  2152.   *         corresponds to a resolution of 16 bits,

  2153.   *         this is the recommended ADC resolution to convert voltage of

  2154.   *         temperature sensor.

  2155.   *         Otherwise, this macro performs the processing to scale

  2156.   *         ADC conversion data to 16 bits.

  2157.   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)

  2158.   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal

  2159.   *                                 temperature sensor (unit: digital value).

  2160.   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature

  2161.   *                                 sensor voltage has been measured.

  2162.   *         This parameter can be one of the following values:

  2163.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2164.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2165.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2166.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2167.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2168.   * @retval Temperature (unit: degree Celsius)

  2169.   */

  2170. #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\

  2171.                                   __TEMPSENSOR_ADC_DATA__,\

  2172.                                   __ADC_RESOLUTION__)                              \

  2173.   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \

  2174.                                                     (__ADC_RESOLUTION__),          \

  2175.                                                     LL_ADC_RESOLUTION_16B)         \

  2176.                    * (__VREFANALOG_VOLTAGE__))                                     \

  2177.                   / TEMPSENSOR_CAL_VREFANALOG)                                     \

  2178.         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \

  2179.      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \

  2180.     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \

  2181.    ) + TEMPSENSOR_CAL1_TEMP                                                        \

  2182.   )

  2183. 

  2184. /**

  2185.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  2186.   *         from ADC conversion data of internal temperature sensor.

  2187.   * @note   Computation is using temperature sensor typical values

  2188.   *         (refer to device datasheet).

  2189.   * @note   Calculation formula:

  2190.   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)

  2191.   *                         / Avg_Slope + CALx_TEMP

  2192.   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC

  2193.   *                                   (unit: digital value)

  2194.   *                Avg_Slope        = temperature sensor slope

  2195.   *                                   (unit: uV/Degree Celsius)

  2196.   *                TS_TYP_CALx_VOLT = temperature sensor digital value at

  2197.   *                                   temperature CALx_TEMP (unit: mV)

  2198.   *         Caution: Calculation relevancy under reserve the temperature sensor

  2199.   *                  of the current device has characteristics in line with

  2200.   *                  datasheet typical values.

  2201.   *                  If temperature sensor calibration values are available on

  2202.   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),

  2203.   *                  temperature calculation will be more accurate using

  2204.   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().

  2205.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  2206.   *         defined as it impacts the ADC LSB equivalent voltage.

  2207.   * @note   Analog reference voltage (Vref+) must be either known from

  2208.   *         user board environment or can be calculated using ADC measurement

  2209.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2210.   * @note   ADC measurement data must correspond to a resolution of 16 bits

  2211.   *         (full scale digital value 4095). If not the case, the data must be

  2212.   *         preliminarily rescaled to an equivalent resolution of 16 bits.

  2213.   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).

  2214.   *                                       On STM32H7, refer to device datasheet parameter "Avg_Slope".

  2215.   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).

  2216.   *                                       On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).

  2217.   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)

  2218.   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)

  2219.   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).

  2220.   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.

  2221.   *         This parameter can be one of the following values:

  2222.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2223.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2224.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2225.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2226.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2227.   * @retval Temperature (unit: degree Celsius)

  2228.   */

  2229. #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\

  2230.                                              __TEMPSENSOR_TYP_CALX_V__,\

  2231.                                              __TEMPSENSOR_CALX_TEMP__,\

  2232.                                              __VREFANALOG_VOLTAGE__,\

  2233.                                              __TEMPSENSOR_ADC_DATA__,\

  2234.                                              __ADC_RESOLUTION__)               \

  2235.   ((( (                                                                        \

  2236.        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \

  2237.                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \

  2238.                  * 1000UL)                                                     \

  2239.        -                                                                       \

  2240.        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \

  2241.                  * 1000UL)                                                     \

  2242.       )                                                                        \

  2243.     ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                 \

  2244.    ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                     \

  2245.   )

  2246. 

  2247. /**

  2248.   * @}

  2249.   */

  2250. 

  2251. /**

  2252.   * @}

  2253.   */

  2254. 

  2255. 

  2256. /* Exported functions --------------------------------------------------------*/

  2257. /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions

  2258.   * @{

  2259.   */

  2260. 

  2261. /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management

  2262.   * @{

  2263.   */

  2264. 

  2265. /**

  2266.   * @brief  Function to help to configure DMA transfer from ADC: retrieve the

  2267.   *         ADC register address from ADC instance and a list of ADC registers

  2268.   *         intended to be used (most commonly) with DMA transfer.

  2269.   * @note   These ADC registers are data registers:

  2270.   *         when ADC conversion data is available in ADC data registers,

  2271.   *         ADC generates a DMA transfer request.

  2272.   * @note   This macro is intended to be used with LL DMA driver, refer to

  2273.   *         function "LL_DMA_ConfigAddresses()".

  2274.   *         Example:

  2275.   *           LL_DMA_ConfigAddresses(DMA1,

  2276.   *                                  LL_DMA_CHANNEL_1,

  2277.   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),

  2278.   *                                  (uint32_t)&< array or variable >,

  2279.   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

  2280.   * @note   For devices with several ADC: in multimode, some devices

  2281.   *         use a different data register outside of ADC instance scope

  2282.   *         (common data register). This macro manages this register difference,

  2283.   *         only ADC instance has to be set as parameter.

  2284.   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n

  2285.   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n

  2286.   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr

  2287.   * @param  ADCx ADC instance

  2288.   * @param  Register This parameter can be one of the following values:

  2289.   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA

  2290.   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)

  2291.   *

  2292.   *         (1) Available on devices with several ADC instances.

  2293.   * @retval ADC register address

  2294.   */

  2295. __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)

  2296. {

  2297.   register uint32_t data_reg_addr;

  2298. 

  2299.   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)

  2300.   {

  2301.     /* Retrieve address of register DR */

  2302.     data_reg_addr = (uint32_t) &(ADCx->DR);

  2303.   }

  2304.   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */

  2305.   {

  2306.     /* Retrieve address of register CDR */

  2307.     data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);

  2308.   }

  2309. 

  2310.   return data_reg_addr;

  2311. }

  2312. 

  2313. /**

  2314.   * @}

  2315.   */

  2316. 

  2317. /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances

  2318.   * @{

  2319.   */

  2320. 

  2321. /**

  2322.   * @brief  Set parameter common to several ADC: Clock source and prescaler.

  2323.   * @note   On this STM32 serie, if ADC group injected is used, some

  2324.   *         clock ratio constraints between ADC clock and AHB clock

  2325.   *         must be respected.

  2326.   *         Refer to reference manual.

  2327.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2328.   *         ADC state:

  2329.   *         All ADC instances of the ADC common group must be disabled.

  2330.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  2331.   *         ADC instance or by using helper macro helper macro

  2332.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  2333.   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n

  2334.   *         CCR      PRESC          LL_ADC_SetCommonClock

  2335.   * @param  ADCxy_COMMON ADC common instance

  2336.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2337.   * @param  CommonClock This parameter can be one of the following values:

  2338.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1

  2339.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

  2340.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

  2341.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

  2342.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

  2343.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

  2344.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6

  2345.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8

  2346.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10

  2347.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12

  2348.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16

  2349.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32

  2350.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64

  2351.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128

  2352.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256

  2353.   * @retval None

  2354.   */

  2355. __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)

  2356. {

  2357.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);

  2358. }

  2359. 

  2360. /**

  2361.   * @brief  Get parameter common to several ADC: Clock source and prescaler.

  2362.   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n

  2363.   *         CCR      PRESC          LL_ADC_GetCommonClock

  2364.   * @param  ADCxy_COMMON ADC common instance

  2365.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2366.   * @retval Returned value can be one of the following values:

  2367.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1

  2368.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

  2369.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

  2370.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

  2371.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

  2372.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

  2373.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6

  2374.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8

  2375.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10

  2376.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12

  2377.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16

  2378.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32

  2379.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64

  2380.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128

  2381.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256

  2382.   */

  2383. __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)

  2384. {

  2385.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));

  2386. }

  2387. 

  2388. /**

  2389.   * @brief  Set parameter common to several ADC: measurement path to internal

  2390.   *         channels (VrefInt, temperature sensor, ...).

  2391.   * @note   One or several values can be selected.

  2392.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2393.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2394.   * @note   Stabilization time of measurement path to internal channel:

  2395.   *         After enabling internal paths, before starting ADC conversion,

  2396.   *         a delay is required for internal voltage reference and

  2397.   *         temperature sensor stabilization time.

  2398.   *         Refer to device datasheet.

  2399.   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.

  2400.   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.

  2401.   * @note   ADC internal channel sampling time constraint:

  2402.   *         For ADC conversion of internal channels,

  2403.   *         a sampling time minimum value is required.

  2404.   *         Refer to device datasheet.

  2405.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2406.   *         ADC state:

  2407.   *         All ADC instances of the ADC common group must be disabled.

  2408.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  2409.   *         ADC instance or by using helper macro helper macro

  2410.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  2411.   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n

  2412.   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n

  2413.   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh

  2414.   * @param  ADCxy_COMMON ADC common instance

  2415.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2416.   * @param  PathInternal This parameter can be a combination of the following values:

  2417.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2418.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2419.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2420.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  2421.   * @retval None

  2422.   */

  2423. __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)

  2424. {

  2425.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);

  2426. }

  2427. 

  2428. /**

  2429.   * @brief  Get parameter common to several ADC: measurement path to internal

  2430.   *         channels (VrefInt, temperature sensor, ...).

  2431.   * @note   One or several values can be selected.

  2432.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2433.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2434.   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n

  2435.   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n

  2436.   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh

  2437.   * @param  ADCxy_COMMON ADC common instance

  2438.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2439.   * @retval Returned value can be a combination of the following values:

  2440.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2441.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2442.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2443.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  2444.   */

  2445. __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)

  2446. {

  2447.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));

  2448. }

  2449. 

  2450. /**

  2451.   * @}

  2452.   */

  2453. 

  2454. /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance

  2455.   * @{

  2456.   */

  2457. 

  2458. /**

  2459.   * @brief  Set ADC calibration factor in the mode single-ended

  2460.   *         or differential (for devices with differential mode available).

  2461.   * @note   This function is intended to set calibration parameters

  2462.   *         without having to perform a new calibration using

  2463.   *         @ref LL_ADC_StartCalibration().

  2464.   * @note   For devices with differential mode available:

  2465.   *         Calibration of offset is specific to each of

  2466.   *         single-ended and differential modes

  2467.   *         (calibration factor must be specified for each of these

  2468.   *         differential modes, if used afterwards and if the application

  2469.   *         requires their calibration).

  2470.   *         Calibration of linearity is common to both

  2471.   *         single-ended and differential modes

  2472.   *         (calibration factor can be specified only once).

  2473.   * @note   In case of setting calibration factors of both modes single ended

  2474.   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):

  2475.   *         both calibration factors must be concatenated.

  2476.   *         To perform this processing, use helper macro

  2477.   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().

  2478.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2479.   *         ADC state:

  2480.   *         ADC must be enabled, without calibration on going, without conversion

  2481.   *         on going on group regular.

  2482.   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationOffsetFactor\n

  2483.   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationOffsetFactor

  2484.   * @param  ADCx ADC instance

  2485.   * @param  SingleDiff This parameter can be one of the following values:

  2486.   *         @arg @ref LL_ADC_SINGLE_ENDED

  2487.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  2488.   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED

  2489.   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F

  2490.   * @retval None

  2491.   */

  2492. __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)

  2493. {

  2494.   MODIFY_REG(ADCx->CALFACT,

  2495.              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,

  2496.              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));

  2497. }

  2498. 

  2499. /**

  2500.   * @brief  Get ADC calibration factor in the mode single-ended

  2501.   *         or differential (for devices with differential mode available).

  2502.   * @note   Calibration factors are set by hardware after performing

  2503.   *         a calibration run using function @ref LL_ADC_StartCalibration().

  2504.   * @note   For devices with differential mode available:

  2505.   *         Calibration of offset is specific to each of

  2506.   *         single-ended and differential modes

  2507.   *         Calibration of linearity is common to both

  2508.   *         single-ended and differential modes

  2509.   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationOffsetFactor\n

  2510.   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationOffsetFactor

  2511.   * @param  ADCx ADC instance

  2512.   * @param  SingleDiff This parameter can be one of the following values:

  2513.   *         @arg @ref LL_ADC_SINGLE_ENDED

  2514.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  2515.   * @retval Value between Min_Data=0x00 and Max_Data=0x7F

  2516.   */

  2517. __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)

  2518. {

  2519.   /* Retrieve bits with position in register depending on parameter           */

  2520.   /* "SingleDiff".                                                            */

  2521.   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */

  2522.   /* containing other bits reserved for other purpose.                        */

  2523.   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));

  2524. }

  2525. 

  2526. /**

  2527.   * @brief  Set ADC Linear calibration factor in the mode single-ended.

  2528.   * @note   This function is intended to set linear calibration parameters

  2529.   *         without having to perform a new calibration using

  2530.   *         @ref LL_ADC_StartCalibration().

  2531.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2532.   *         ADC state:

  2533.   *         ADC must be enabled, without calibration on going, without conversion

  2534.   *         on going on group regular.

  2535.   * @rmtoll CALFACT2  LINCALFACT      LL_ADC_SetCalibrationLinearFactor\n

  2536.   *         CALFACT2  LINCALFACT      LL_ADC_SetCalibrationLinearFactor

  2537.   * @param  ADCx ADC instance

  2538.   * @param  LinearityWord This parameter can be one of the following values:

  2539.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD1

  2540.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD2

  2541.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD3

  2542.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD4

  2543.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD5

  2544.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD6

  2545.   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF

  2546.   * @retval None

  2547.   */

  2548. __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)

  2549. {

  2550.   register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;

  2551.   MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);

  2552.   MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);

  2553.   while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))

  2554.   {

  2555.     timeout_cpu_cycles--;

  2556.   }

  2557. }

  2558. 

  2559. /**

  2560.   * @brief  Get ADC Linear calibration factor in the mode single-ended.

  2561.   * @note   Calibration factors are set by hardware after performing

  2562.   *         a calibration run using function @ref LL_ADC_StartCalibration().

  2563.   * @rmtoll CALFACT2  LINCALFACT      LL_ADC_GetCalibrationLinearFactor\n

  2564.   *         CALFACT2  LINCALFACT      LL_ADC_GetCalibrationLinearFactor

  2565.   * @param  ADCx ADC instance

  2566.   * @param  LinearityWord This parameter can be one of the following values:

  2567.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD1

  2568.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD2

  2569.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD3

  2570.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD4

  2571.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD5

  2572.   *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD6

  2573.   * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF

  2574.   */

  2575. __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)

  2576. {

  2577.   register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;

  2578.   CLEAR_BIT(ADCx->CR, LinearityWord);

  2579.   while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))

  2580.   {

  2581.     timeout_cpu_cycles--;

  2582.   }

  2583.   return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));

  2584. }

  2585. /**

  2586.   * @brief  Set ADC resolution.

  2587.   *         Refer to reference manual for alignments formats

  2588.   *         dependencies to ADC resolutions.

  2589.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2590.   *         ADC state:

  2591.   *         ADC must be disabled or enabled without conversion on going

  2592.   *         on either groups regular or injected.

  2593.   * @rmtoll CFGR     RES            LL_ADC_SetResolution

  2594.   * @param  ADCx ADC instance

  2595.   * @param  Resolution This parameter can be one of the following values:

  2596.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2597.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2598.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2599.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2600.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2601.   * @retval None

  2602.   */

  2603. __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)

  2604. {

  2605. #if defined (ADC_VER_V5_3)

  2606.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

  2607. #else

  2608.   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */

  2609.   {

  2610.     MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

  2611.   }

  2612.   else /* Rev.V */

  2613.   {

  2614.     if(LL_ADC_RESOLUTION_8B == Resolution)

  2615.     {

  2616.       MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);

  2617.     }

  2618.     else

  2619.     {

  2620.       MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

  2621.     }

  2622.   }

  2623. #endif /* ADC_VER_V5_3*/

  2624. }

  2625. 

  2626. /**

  2627.   * @brief  Get ADC resolution.

  2628.   *         Refer to reference manual for alignments formats

  2629.   *         dependencies to ADC resolutions.

  2630.   * @rmtoll CFGR     RES            LL_ADC_GetResolution

  2631.   * @param  ADCx ADC instance

  2632.   * @retval Returned value can be one of the following values:

  2633.   *         @arg @ref LL_ADC_RESOLUTION_16B

  2634.   *         @arg @ref LL_ADC_RESOLUTION_14B

  2635.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2636.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2637.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2638.   */

  2639. __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)

  2640. {

  2641. #if defined (ADC_VER_V5_3)

  2642.     return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

  2643. #else

  2644.   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */

  2645.   {

  2646.     return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

  2647.   }

  2648.   else /* Rev.V */

  2649.   {

  2650.     if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)

  2651.     {

  2652.       return (LL_ADC_RESOLUTION_8B);

  2653.     }

  2654.     else

  2655.     {

  2656.       return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

  2657.     }

  2658.   }

  2659. #endif /* ADC_VER_V5_3 */

  2660. }

  2661. 

  2662. /**

  2663.   * @brief  Set ADC low power mode.

  2664.   * @note   Description of ADC low power modes:

  2665.   *         - ADC low power mode "auto wait": Dynamic low power mode,

  2666.   *           ADC conversions occurrences are limited to the minimum necessary

  2667.   *           in order to reduce power consumption.

  2668.   *           New ADC conversion starts only when the previous

  2669.   *           unitary conversion data (for ADC group regular)

  2670.   *           or previous sequence conversions data (for ADC group injected)

  2671.   *           has been retrieved by user software.

  2672.   *           In the meantime, ADC remains idle: does not performs any

  2673.   *           other conversion.

  2674.   *           This mode allows to automatically adapt the ADC conversions

  2675.   *           triggers to the speed of the software that reads the data.

  2676.   *           Moreover, this avoids risk of overrun for low frequency

  2677.   *           applications.

  2678.   *           How to use this low power mode:

  2679.   *           - Do not use with interruption or DMA since these modes

  2680.   *             have to clear immediately the EOC flag to free the

  2681.   *             IRQ vector sequencer.

  2682.   *           - Do use with polling: 1. Start conversion,

  2683.   *             2. Later on, when conversion data is needed: poll for end of

  2684.   *             conversion  to ensure that conversion is completed and

  2685.   *             retrieve ADC conversion data. This will trig another

  2686.   *             ADC conversion start.

  2687.   *         - ADC low power mode "auto power-off" (feature available on

  2688.   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):

  2689.   *           the ADC automatically powers-off after a conversion and

  2690.   *           automatically wakes up when a new conversion is triggered

  2691.   *           (with startup time between trigger and start of sampling).

  2692.   *           This feature can be combined with low power mode "auto wait".

  2693.   * @note   With ADC low power mode "auto wait", the ADC conversion data read

  2694.   *         is corresponding to previous ADC conversion start, independently

  2695.   *         of delay during which ADC was idle.

  2696.   *         Therefore, the ADC conversion data may be outdated: does not

  2697.   *         correspond to the current voltage level on the selected

  2698.   *         ADC channel.

  2699.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2700.   *         ADC state:

  2701.   *         ADC must be disabled or enabled without conversion on going

  2702.   *         on either groups regular or injected.

  2703.   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode

  2704.   * @param  ADCx ADC instance

  2705.   * @param  LowPowerMode This parameter can be one of the following values:

  2706.   *         @arg @ref LL_ADC_LP_MODE_NONE

  2707.   *         @arg @ref LL_ADC_LP_AUTOWAIT

  2708.   * @retval None

  2709.   */

  2710. __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)

  2711. {

  2712.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);

  2713. }

  2714. 

  2715. /**

  2716.   * @brief  Get ADC low power mode:

  2717.   * @note   Description of ADC low power modes:

  2718.   *         - ADC low power mode "auto wait": Dynamic low power mode,

  2719.   *           ADC conversions occurrences are limited to the minimum necessary

  2720.   *           in order to reduce power consumption.

  2721.   *           New ADC conversion starts only when the previous

  2722.   *           unitary conversion data (for ADC group regular)

  2723.   *           or previous sequence conversions data (for ADC group injected)

  2724.   *           has been retrieved by user software.

  2725.   *           In the meantime, ADC remains idle: does not performs any

  2726.   *           other conversion.

  2727.   *           This mode allows to automatically adapt the ADC conversions

  2728.   *           triggers to the speed of the software that reads the data.

  2729.   *           Moreover, this avoids risk of overrun for low frequency

  2730.   *           applications.

  2731.   *           How to use this low power mode:

  2732.   *           - Do not use with interruption or DMA since these modes

  2733.   *             have to clear immediately the EOC flag to free the

  2734.   *             IRQ vector sequencer.

  2735.   *           - Do use with polling: 1. Start conversion,

  2736.   *             2. Later on, when conversion data is needed: poll for end of

  2737.   *             conversion  to ensure that conversion is completed and

  2738.   *             retrieve ADC conversion data. This will trig another

  2739.   *             ADC conversion start.

  2740.   *         - ADC low power mode "auto power-off" (feature available on

  2741.   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):

  2742.   *           the ADC automatically powers-off after a conversion and

  2743.   *           automatically wakes up when a new conversion is triggered

  2744.   *           (with startup time between trigger and start of sampling).

  2745.   *           This feature can be combined with low power mode "auto wait".

  2746.   * @note   With ADC low power mode "auto wait", the ADC conversion data read

  2747.   *         is corresponding to previous ADC conversion start, independently

  2748.   *         of delay during which ADC was idle.

  2749.   *         Therefore, the ADC conversion data may be outdated: does not

  2750.   *         correspond to the current voltage level on the selected

  2751.   *         ADC channel.

  2752.   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode

  2753.   * @param  ADCx ADC instance

  2754.   * @retval Returned value can be one of the following values:

  2755.   *         @arg @ref LL_ADC_LP_MODE_NONE

  2756.   *         @arg @ref LL_ADC_LP_AUTOWAIT

  2757.   */

  2758. __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)

  2759. {

  2760.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));

  2761. }

  2762. 

  2763. /**

  2764.   * @brief  Set ADC selected offset number 1, 2, 3 or 4.

  2765.   * @note   This function set the 2 items of offset configuration:

  2766.   *         - ADC channel to which the offset programmed will be applied

  2767.   *           (independently of channel mapped on ADC group regular

  2768.   *           or group injected)

  2769.   *         - Offset level (offset to be subtracted from the raw

  2770.   *           converted data).

  2771.   * @note   Caution: Offset format is dependent to ADC resolution:

  2772.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  2773.   *         are set to 0.

  2774.   * @note   This function enables the offset, by default. It can be forced

  2775.   *         to disable state using function LL_ADC_SetOffsetState().

  2776.   * @note   If a channel is mapped on several offsets numbers, only the offset

  2777.   *         with the lowest value is considered for the subtraction.

  2778.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2779.   *         ADC state:

  2780.   *         ADC must be disabled or enabled without conversion on going

  2781.   *         on either groups regular or injected.

  2782.   * @note   On STM32H7, some fast channels are available: fast analog inputs

  2783.   *         coming from GPIO pads (ADC_IN0..5).

  2784.   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n

  2785.   *         OFR1     OFFSET1        LL_ADC_SetOffset\n

  2786.   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n

  2787.   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n

  2788.   *         OFR2     OFFSET2        LL_ADC_SetOffset\n

  2789.   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n

  2790.   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n

  2791.   *         OFR3     OFFSET3        LL_ADC_SetOffset\n

  2792.   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n

  2793.   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n

  2794.   *         OFR4     OFFSET4        LL_ADC_SetOffset\n

  2795.   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset

  2796.   * @param  ADCx ADC instance

  2797.   * @param  Offsety This parameter can be one of the following values:

  2798.   *         @arg @ref LL_ADC_OFFSET_1

  2799.   *         @arg @ref LL_ADC_OFFSET_2

  2800.   *         @arg @ref LL_ADC_OFFSET_3

  2801.   *         @arg @ref LL_ADC_OFFSET_4

  2802.   * @param  Channel This parameter can be one of the following values:

  2803.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  2804.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  2805.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  2806.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  2807.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  2808.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  2809.   *         @arg @ref LL_ADC_CHANNEL_6

  2810.   *         @arg @ref LL_ADC_CHANNEL_7

  2811.   *         @arg @ref LL_ADC_CHANNEL_8

  2812.   *         @arg @ref LL_ADC_CHANNEL_9

  2813.   *         @arg @ref LL_ADC_CHANNEL_10

  2814.   *         @arg @ref LL_ADC_CHANNEL_11

  2815.   *         @arg @ref LL_ADC_CHANNEL_12

  2816.   *         @arg @ref LL_ADC_CHANNEL_13

  2817.   *         @arg @ref LL_ADC_CHANNEL_14

  2818.   *         @arg @ref LL_ADC_CHANNEL_15

  2819.   *         @arg @ref LL_ADC_CHANNEL_16

  2820.   *         @arg @ref LL_ADC_CHANNEL_17

  2821.   *         @arg @ref LL_ADC_CHANNEL_18

  2822.   *         @arg @ref LL_ADC_CHANNEL_19

  2823.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  2824.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  2825.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  2826.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  2827.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  2828.   *

  2829.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  2830.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  2831.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  2832.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  2833.   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF

  2834.   * @retval None

  2835.   */

  2836. __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)

  2837. {

  2838.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  2839. 

  2840.   MODIFY_REG(*preg,

  2841.              ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,

  2842.              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);

  2843. }

  2844. 

  2845. /**

  2846.   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

  2847.   *         Channel to which the offset programmed will be applied

  2848.   *         (independently of channel mapped on ADC group regular

  2849.   *         or group injected)

  2850.   * @note   Usage of the returned channel number:

  2851.   *         - To reinject this channel into another function LL_ADC_xxx:

  2852.   *           the returned channel number is only partly formatted on definition

  2853.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  2854.   *           with parts of literals LL_ADC_CHANNEL_x or using

  2855.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  2856.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  2857.   *           as parameter for another function.

  2858.   *         - To get the channel number in decimal format:

  2859.   *           process the returned value with the helper macro

  2860.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  2861.   * @note   On STM32H7, some fast channels are available: fast analog inputs

  2862.   *         coming from GPIO pads (ADC_IN0..5).

  2863.   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n

  2864.   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n

  2865.   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n

  2866.   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel

  2867.   * @param  ADCx ADC instance

  2868.   * @param  Offsety This parameter can be one of the following values:

  2869.   *         @arg @ref LL_ADC_OFFSET_1

  2870.   *         @arg @ref LL_ADC_OFFSET_2

  2871.   *         @arg @ref LL_ADC_OFFSET_3

  2872.   *         @arg @ref LL_ADC_OFFSET_4

  2873.   * @retval Returned value can be one of the following values:

  2874.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  2875.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  2876.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  2877.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  2878.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  2879.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  2880.   *         @arg @ref LL_ADC_CHANNEL_6

  2881.   *         @arg @ref LL_ADC_CHANNEL_7

  2882.   *         @arg @ref LL_ADC_CHANNEL_8

  2883.   *         @arg @ref LL_ADC_CHANNEL_9

  2884.   *         @arg @ref LL_ADC_CHANNEL_10

  2885.   *         @arg @ref LL_ADC_CHANNEL_11

  2886.   *         @arg @ref LL_ADC_CHANNEL_12

  2887.   *         @arg @ref LL_ADC_CHANNEL_13

  2888.   *         @arg @ref LL_ADC_CHANNEL_14

  2889.   *         @arg @ref LL_ADC_CHANNEL_15

  2890.   *         @arg @ref LL_ADC_CHANNEL_16

  2891.   *         @arg @ref LL_ADC_CHANNEL_17

  2892.   *         @arg @ref LL_ADC_CHANNEL_18

  2893.   *         @arg @ref LL_ADC_CHANNEL_19

  2894.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  2895.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  2896.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  2897.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  2898.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  2899.   *

  2900.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  2901.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  2902.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  2903.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  2904.   *         (1, 2) For ADC channel read back from ADC register,

  2905.   *                comparison with internal channel parameter to be done

  2906.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  2907.   */

  2908. __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)

  2909. {

  2910.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  2911. 

  2912.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);

  2913. }

  2914. 

  2915. /**

  2916.   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

  2917.   *         Offset level (offset to be subtracted from the raw

  2918.   *         converted data).

  2919.   * @note   Caution: Offset format is dependent to ADC resolution:

  2920.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  2921.   *         are set to 0.

  2922.   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n

  2923.   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n

  2924.   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n

  2925.   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel

  2926.   * @param  ADCx ADC instance

  2927.   * @param  Offsety This parameter can be one of the following values:

  2928.   *         @arg @ref LL_ADC_OFFSET_1

  2929.   *         @arg @ref LL_ADC_OFFSET_2

  2930.   *         @arg @ref LL_ADC_OFFSET_3

  2931.   *         @arg @ref LL_ADC_OFFSET_4

  2932.   * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF

  2933.   */

  2934. __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)

  2935. {

  2936.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  2937. 

  2938.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);

  2939. }

  2940. 

  2941. 

  2942. /**

  2943.   * @brief  Set data right shift for the ADC selected offset number 1, 2, 3 or 4:

  2944.   *         signed offset saturation if enabled or disabled.

  2945.   * @rmtoll CFGR2    RSHIFT          LL_ADC_SetDataRightShift\n

  2946.   * @param  ADCx ADC instance

  2947.   * @param  Offsety This parameter can be one of the following values:

  2948.   *         @arg @ref LL_ADC_OFFSET_1

  2949.   *         @arg @ref LL_ADC_OFFSET_2

  2950.   *         @arg @ref LL_ADC_OFFSET_3

  2951.   *         @arg @ref LL_ADC_OFFSET_4

  2952.   * @param  RigthShift This parameter can be one of the following values:

  2953.   *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE

  2954.   *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE

  2955.   * @retval Returned None

  2956.   */

  2957. __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)

  2958. {

  2959.   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));

  2960. }

  2961. 

  2962. /**

  2963.   * @brief  Get data right shift for the ADC selected offset number 1, 2, 3 or 4:

  2964.   *         signed offset saturation if enabled or disabled.

  2965.   * @rmtoll CFGR2    RSHIFT          LL_ADC_GetDataRightShift\n

  2966.   * @param  ADCx ADC instance

  2967.   * @param  Offsety This parameter can be one of the following values:

  2968.   *         @arg @ref LL_ADC_OFFSET_1

  2969.   *         @arg @ref LL_ADC_OFFSET_2

  2970.   *         @arg @ref LL_ADC_OFFSET_3

  2971.   *         @arg @ref LL_ADC_OFFSET_4

  2972.   * @retval Returned value can be one of the following values:

  2973.   *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE

  2974.   *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE

  2975.   */

  2976. __STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)

  2977. {

  2978.   return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));

  2979. }

  2980. 

  2981. /**

  2982.   * @brief  Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:

  2983.   *         signed offset saturation if enabled or disabled.

  2984.   * @rmtoll OFR1     SSATE          LL_ADC_SetOffsetSignedSaturation\n

  2985.   *         OFR2     SSATE          LL_ADC_SetOffsetSignedSaturation\n

  2986.   *         OFR3     SSATE          LL_ADC_SetOffsetSignedSaturation\n

  2987.   *         OFR4     SSATE          LL_ADC_SetOffsetSignedSaturation

  2988.   * @param  ADCx ADC instance

  2989.   * @param  Offsety This parameter can be one of the following values:

  2990.   *         @arg @ref LL_ADC_OFFSET_1

  2991.   *         @arg @ref LL_ADC_OFFSET_2

  2992.   *         @arg @ref LL_ADC_OFFSET_3

  2993.   *         @arg @ref LL_ADC_OFFSET_4

  2994.   * @param  OffsetSignedSaturation This parameter can be one of the following values:

  2995.   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE

  2996.   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE

  2997.   * @retval Returned None

  2998.   */

  2999. __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)

  3000. {

  3001.    register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  3002.    MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);

  3003. }

  3004. 

  3005. /**

  3006.   * @brief  Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:

  3007.   *         signed offset saturation if enabled or disabled.

  3008.   * @rmtoll OFR1     SSATE          LL_ADC_GetOffsetSignedSaturation\n

  3009.   *         OFR2     SSATE          LL_ADC_GetOffsetSignedSaturation\n

  3010.   *         OFR3     SSATE          LL_ADC_GetOffsetSignedSaturation\n

  3011.   *         OFR4     SSATE          LL_ADC_GetOffsetSignedSaturation

  3012.   * @param  ADCx ADC instance

  3013.   * @param  Offsety This parameter can be one of the following values:

  3014.   *         @arg @ref LL_ADC_OFFSET_1

  3015.   *         @arg @ref LL_ADC_OFFSET_2

  3016.   *         @arg @ref LL_ADC_OFFSET_3

  3017.   *         @arg @ref LL_ADC_OFFSET_4

  3018.   * @retval Returned value can be one of the following values:

  3019.   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE

  3020.   *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE

  3021.   */

  3022. __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)

  3023. {

  3024.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

  3025.   return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);

  3026. }

  3027. 

  3028. /**

  3029.   * @}

  3030.   */

  3031. 

  3032. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular

  3033.   * @{

  3034.   */

  3035. 

  3036. /**

  3037.   * @brief  Set ADC group regular conversion trigger source:

  3038.   *         internal (SW start) or from external peripheral (timer event,

  3039.   *         external interrupt line).

  3040.   * @note   On this STM32 serie, setting trigger source to external trigger

  3041.   *         also set trigger polarity to rising edge

  3042.   *         (default setting for compatibility with some ADC on other

  3043.   *         STM32 families having this setting set by HW default value).

  3044.   *         In case of need to modify trigger edge, use

  3045.   *         function @ref LL_ADC_REG_SetTriggerEdge().

  3046.   * @note   Availability of parameters of trigger sources from timer

  3047.   *         depends on timers availability on the selected device.

  3048.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3049.   *         ADC state:

  3050.   *         ADC must be disabled or enabled without conversion on going

  3051.   *         on group regular.

  3052.   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n

  3053.   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource

  3054.   * @param  ADCx ADC instance

  3055.   * @param  TriggerSource This parameter can be one of the following values:

  3056.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  3057.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1

  3058.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2

  3059.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3

  3060.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  3061.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO

  3062.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

  3063.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  3064.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO

  3065.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2

  3066.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO

  3067.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

  3068.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  3069.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

  3070.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

  3071.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO

  3072.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4

  3073.   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1

  3074.   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3

  3075.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT

  3076.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT

  3077.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT

  3078.   * @retval None

  3079.   */

  3080. __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  3081. {

  3082.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);

  3083. }

  3084. 

  3085. /**

  3086.   * @brief  Get ADC group regular conversion trigger source:

  3087.   *         internal (SW start) or from external peripheral (timer event,

  3088.   *         external interrupt line).

  3089.   * @note   To determine whether group regular trigger source is

  3090.   *         internal (SW start) or external, without detail

  3091.   *         of which peripheral is selected as external trigger,

  3092.   *         (equivalent to

  3093.   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")

  3094.   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.

  3095.   * @note   Availability of parameters of trigger sources from timer

  3096.   *         depends on timers availability on the selected device.

  3097.   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n

  3098.   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource

  3099.   * @param  ADCx ADC instance

  3100.   * @retval Returned value can be one of the following values:

  3101.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  3102.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1

  3103.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2

  3104.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3

  3105.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  3106.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO

  3107.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

  3108.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  3109.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO

  3110.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2

  3111.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO

  3112.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

  3113.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  3114.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

  3115.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

  3116.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO

  3117.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4

  3118.   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1

  3119.   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3

  3120.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT

  3121.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT

  3122.   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT

  3123.   */

  3124. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)

  3125. {

  3126.   register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);

  3127. 

  3128.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  3129.   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */

  3130.   register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));

  3131. 

  3132.   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */

  3133.   /* to match with triggers literals definition.                              */

  3134.   return ((TriggerSource

  3135.            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)

  3136.           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)

  3137.          );

  3138. }

  3139. 

  3140. /**

  3141.   * @brief  Get ADC group regular conversion trigger source internal (SW start)

  3142.   *         or external.

  3143.   * @note   In case of group regular trigger source set to external trigger,

  3144.   *         to determine which peripheral is selected as external trigger,

  3145.   *         use function @ref LL_ADC_REG_GetTriggerSource().

  3146.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart

  3147.   * @param  ADCx ADC instance

  3148.   * @retval Value "0" if trigger source external trigger

  3149.   *         Value "1" if trigger source SW start.

  3150.   */

  3151. __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  3152. {

  3153.   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);

  3154. }

  3155. 

  3156. /**

  3157.   * @brief  Set ADC group regular conversion trigger polarity.

  3158.   * @note   Applicable only for trigger source set to external trigger.

  3159.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3160.   *         ADC state:

  3161.   *         ADC must be disabled or enabled without conversion on going

  3162.   *         on group regular.

  3163.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge

  3164.   * @param  ADCx ADC instance

  3165.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  3166.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  3167.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  3168.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  3169.   * @retval None

  3170.   */

  3171. __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  3172. {

  3173.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);

  3174. }

  3175. 

  3176. /**

  3177.   * @brief  Get ADC group regular conversion trigger polarity.

  3178.   * @note   Applicable only for trigger source set to external trigger.

  3179.   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge

  3180.   * @param  ADCx ADC instance

  3181.   * @retval Returned value can be one of the following values:

  3182.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  3183.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  3184.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  3185.   */

  3186. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)

  3187. {

  3188.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));

  3189. }

  3190. 

  3191. /**

  3192.   * @brief  Set ADC group regular sequencer length and scan direction.

  3193.   * @note   Description of ADC group regular sequencer features:

  3194.   *         - For devices with sequencer fully configurable

  3195.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  3196.   *           sequencer length and each rank affectation to a channel

  3197.   *           are configurable.

  3198.   *           This function performs configuration of:

  3199.   *           - Sequence length: Number of ranks in the scan sequence.

  3200.   *           - Sequence direction: Unless specified in parameters, sequencer

  3201.   *             scan direction is forward (from rank 1 to rank n).

  3202.   *           Sequencer ranks are selected using

  3203.   *           function "LL_ADC_REG_SetSequencerRanks()".

  3204.   *         - For devices with sequencer not fully configurable

  3205.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  3206.   *           sequencer length and each rank affectation to a channel

  3207.   *           are defined by channel number.

  3208.   *           This function performs configuration of:

  3209.   *           - Sequence length: Number of ranks in the scan sequence is

  3210.   *             defined by number of channels set in the sequence,

  3211.   *             rank of each channel is fixed by channel HW number.

  3212.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  3213.   *           - Sequence direction: Unless specified in parameters, sequencer

  3214.   *             scan direction is forward (from lowest channel number to

  3215.   *             highest channel number).

  3216.   *           Sequencer ranks are selected using

  3217.   *           function "LL_ADC_REG_SetSequencerChannels()".

  3218.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3219.   *         ADC conversion on only 1 channel.

  3220.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3221.   *         ADC state:

  3222.   *         ADC must be disabled or enabled without conversion on going

  3223.   *         on group regular.

  3224.   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength

  3225.   * @param  ADCx ADC instance

  3226.   * @param  SequencerNbRanks This parameter can be one of the following values:

  3227.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  3228.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  3229.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  3230.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  3231.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  3232.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  3233.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  3234.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  3235.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

  3236.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

  3237.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

  3238.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

  3239.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

  3240.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

  3241.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

  3242.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  3243.   * @retval None

  3244.   */

  3245. __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  3246. {

  3247.   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);

  3248. }

  3249. 

  3250. /**

  3251.   * @brief  Get ADC group regular sequencer length and scan direction.

  3252.   * @note   Description of ADC group regular sequencer features:

  3253.   *         - For devices with sequencer fully configurable

  3254.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  3255.   *           sequencer length and each rank affectation to a channel

  3256.   *           are configurable.

  3257.   *           This function retrieves:

  3258.   *           - Sequence length: Number of ranks in the scan sequence.

  3259.   *           - Sequence direction: Unless specified in parameters, sequencer

  3260.   *             scan direction is forward (from rank 1 to rank n).

  3261.   *           Sequencer ranks are selected using

  3262.   *           function "LL_ADC_REG_SetSequencerRanks()".

  3263.   *         - For devices with sequencer not fully configurable

  3264.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  3265.   *           sequencer length and each rank affectation to a channel

  3266.   *           are defined by channel number.

  3267.   *           This function retrieves:

  3268.   *           - Sequence length: Number of ranks in the scan sequence is

  3269.   *             defined by number of channels set in the sequence,

  3270.   *             rank of each channel is fixed by channel HW number.

  3271.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  3272.   *           - Sequence direction: Unless specified in parameters, sequencer

  3273.   *             scan direction is forward (from lowest channel number to

  3274.   *             highest channel number).

  3275.   *           Sequencer ranks are selected using

  3276.   *           function "LL_ADC_REG_SetSequencerChannels()".

  3277.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3278.   *         ADC conversion on only 1 channel.

  3279.   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength

  3280.   * @param  ADCx ADC instance

  3281.   * @retval Returned value can be one of the following values:

  3282.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  3283.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  3284.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  3285.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  3286.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  3287.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  3288.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  3289.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  3290.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

  3291.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

  3292.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

  3293.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

  3294.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

  3295.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

  3296.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

  3297.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  3298.   */

  3299. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)

  3300. {

  3301.   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));

  3302. }

  3303. 

  3304. /**

  3305.   * @brief  Set ADC group regular sequencer discontinuous mode:

  3306.   *         sequence subdivided and scan conversions interrupted every selected

  3307.   *         number of ranks.

  3308.   * @note   It is not possible to enable both ADC group regular

  3309.   *         continuous mode and sequencer discontinuous mode.

  3310.   * @note   It is not possible to enable both ADC auto-injected mode

  3311.   *         and ADC group regular sequencer discontinuous mode.

  3312.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3313.   *         ADC state:

  3314.   *         ADC must be disabled or enabled without conversion on going

  3315.   *         on group regular.

  3316.   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n

  3317.   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont

  3318.   * @param  ADCx ADC instance

  3319.   * @param  SeqDiscont This parameter can be one of the following values:

  3320.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  3321.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  3322.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

  3323.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

  3324.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

  3325.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

  3326.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

  3327.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

  3328.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

  3329.   * @retval None

  3330.   */

  3331. __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  3332. {

  3333.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);

  3334. }

  3335. 

  3336. /**

  3337.   * @brief  Get ADC group regular sequencer discontinuous mode:

  3338.   *         sequence subdivided and scan conversions interrupted every selected

  3339.   *         number of ranks.

  3340.   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n

  3341.   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont

  3342.   * @param  ADCx ADC instance

  3343.   * @retval Returned value can be one of the following values:

  3344.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  3345.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  3346.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

  3347.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

  3348.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

  3349.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

  3350.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

  3351.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

  3352.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

  3353.   */

  3354. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)

  3355. {

  3356.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));

  3357. }

  3358. 

  3359. /**

  3360.   * @brief  Set ADC group regular sequence: channel on the selected

  3361.   *         scan sequence rank.

  3362.   * @note   This function performs configuration of:

  3363.   *         - Channels ordering into each rank of scan sequence:

  3364.   *           whatever channel can be placed into whatever rank.

  3365.   * @note   On this STM32 serie, ADC group regular sequencer is

  3366.   *         fully configurable: sequencer length and each rank

  3367.   *         affectation to a channel are configurable.

  3368.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  3369.   * @note   Depending on devices and packages, some channels may not be available.

  3370.   *         Refer to device datasheet for channels availability.

  3371.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  3372.   *         TempSensor, ...), measurement paths to internal channels must be

  3373.   *         enabled separately.

  3374.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  3375.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3376.   *         ADC state:

  3377.   *         ADC must be disabled or enabled without conversion on going

  3378.   *         on group regular.

  3379.   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n

  3380.   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n

  3381.   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n

  3382.   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n

  3383.   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n

  3384.   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n

  3385.   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n

  3386.   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n

  3387.   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n

  3388.   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n

  3389.   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n

  3390.   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n

  3391.   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n

  3392.   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n

  3393.   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n

  3394.   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks

  3395.   * @param  ADCx ADC instance

  3396.   * @param  Rank This parameter can be one of the following values:

  3397.   *         @arg @ref LL_ADC_REG_RANK_1

  3398.   *         @arg @ref LL_ADC_REG_RANK_2

  3399.   *         @arg @ref LL_ADC_REG_RANK_3

  3400.   *         @arg @ref LL_ADC_REG_RANK_4

  3401.   *         @arg @ref LL_ADC_REG_RANK_5

  3402.   *         @arg @ref LL_ADC_REG_RANK_6

  3403.   *         @arg @ref LL_ADC_REG_RANK_7

  3404.   *         @arg @ref LL_ADC_REG_RANK_8

  3405.   *         @arg @ref LL_ADC_REG_RANK_9

  3406.   *         @arg @ref LL_ADC_REG_RANK_10

  3407.   *         @arg @ref LL_ADC_REG_RANK_11

  3408.   *         @arg @ref LL_ADC_REG_RANK_12

  3409.   *         @arg @ref LL_ADC_REG_RANK_13

  3410.   *         @arg @ref LL_ADC_REG_RANK_14

  3411.   *         @arg @ref LL_ADC_REG_RANK_15

  3412.   *         @arg @ref LL_ADC_REG_RANK_16

  3413.   * @param  Channel This parameter can be one of the following values:

  3414.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  3415.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  3416.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  3417.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  3418.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  3419.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  3420.   *         @arg @ref LL_ADC_CHANNEL_6

  3421.   *         @arg @ref LL_ADC_CHANNEL_7

  3422.   *         @arg @ref LL_ADC_CHANNEL_8

  3423.   *         @arg @ref LL_ADC_CHANNEL_9

  3424.   *         @arg @ref LL_ADC_CHANNEL_10

  3425.   *         @arg @ref LL_ADC_CHANNEL_11

  3426.   *         @arg @ref LL_ADC_CHANNEL_12

  3427.   *         @arg @ref LL_ADC_CHANNEL_13

  3428.   *         @arg @ref LL_ADC_CHANNEL_14

  3429.   *         @arg @ref LL_ADC_CHANNEL_15

  3430.   *         @arg @ref LL_ADC_CHANNEL_16

  3431.   *         @arg @ref LL_ADC_CHANNEL_17

  3432.   *         @arg @ref LL_ADC_CHANNEL_18

  3433.   *         @arg @ref LL_ADC_CHANNEL_19

  3434.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3435.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  3436.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3437.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  3438.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  3439.   *

  3440.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  3441.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  3442.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  3443.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  3444.   * @retval None

  3445.   */

  3446. __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  3447. {

  3448.   /* Set bits with content of parameter "Channel" with bits position          */

  3449.   /* in register and register position depending on parameter "Rank".         */

  3450.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  3451.   /* other bits reserved for other purpose.                                   */

  3452.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));

  3453. 

  3454.   MODIFY_REG(*preg,

  3455.              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),

  3456.              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));

  3457. }

  3458. 

  3459. /**

  3460.   * @brief  Get ADC group regular sequence: channel on the selected

  3461.   *         scan sequence rank.

  3462.   * @note   On this STM32 serie, ADC group regular sequencer is

  3463.   *         fully configurable: sequencer length and each rank

  3464.   *         affectation to a channel are configurable.

  3465.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  3466.   * @note   Depending on devices and packages, some channels may not be available.

  3467.   *         Refer to device datasheet for channels availability.

  3468.   * @note   Usage of the returned channel number:

  3469.   *         - To reinject this channel into another function LL_ADC_xxx:

  3470.   *           the returned channel number is only partly formatted on definition

  3471.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  3472.   *           with parts of literals LL_ADC_CHANNEL_x or using

  3473.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3474.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3475.   *           as parameter for another function.

  3476.   *         - To get the channel number in decimal format:

  3477.   *           process the returned value with the helper macro

  3478.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3479.   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n

  3480.   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n

  3481.   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n

  3482.   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n

  3483.   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n

  3484.   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n

  3485.   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n

  3486.   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n

  3487.   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n

  3488.   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n

  3489.   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n

  3490.   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n

  3491.   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n

  3492.   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n

  3493.   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n

  3494.   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks

  3495.   * @param  ADCx ADC instance

  3496.   * @param  Rank This parameter can be one of the following values:

  3497.   *         @arg @ref LL_ADC_REG_RANK_1

  3498.   *         @arg @ref LL_ADC_REG_RANK_2

  3499.   *         @arg @ref LL_ADC_REG_RANK_3

  3500.   *         @arg @ref LL_ADC_REG_RANK_4

  3501.   *         @arg @ref LL_ADC_REG_RANK_5

  3502.   *         @arg @ref LL_ADC_REG_RANK_6

  3503.   *         @arg @ref LL_ADC_REG_RANK_7

  3504.   *         @arg @ref LL_ADC_REG_RANK_8

  3505.   *         @arg @ref LL_ADC_REG_RANK_9

  3506.   *         @arg @ref LL_ADC_REG_RANK_10

  3507.   *         @arg @ref LL_ADC_REG_RANK_11

  3508.   *         @arg @ref LL_ADC_REG_RANK_12

  3509.   *         @arg @ref LL_ADC_REG_RANK_13

  3510.   *         @arg @ref LL_ADC_REG_RANK_14

  3511.   *         @arg @ref LL_ADC_REG_RANK_15

  3512.   *         @arg @ref LL_ADC_REG_RANK_16

  3513.   * @retval Returned value can be one of the following values:

  3514.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  3515.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  3516.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  3517.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  3518.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  3519.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  3520.   *         @arg @ref LL_ADC_CHANNEL_6

  3521.   *         @arg @ref LL_ADC_CHANNEL_7

  3522.   *         @arg @ref LL_ADC_CHANNEL_8

  3523.   *         @arg @ref LL_ADC_CHANNEL_9

  3524.   *         @arg @ref LL_ADC_CHANNEL_10

  3525.   *         @arg @ref LL_ADC_CHANNEL_11

  3526.   *         @arg @ref LL_ADC_CHANNEL_12

  3527.   *         @arg @ref LL_ADC_CHANNEL_13

  3528.   *         @arg @ref LL_ADC_CHANNEL_14

  3529.   *         @arg @ref LL_ADC_CHANNEL_15

  3530.   *         @arg @ref LL_ADC_CHANNEL_16

  3531.   *         @arg @ref LL_ADC_CHANNEL_17

  3532.   *         @arg @ref LL_ADC_CHANNEL_18

  3533.   *         @arg @ref LL_ADC_CHANNEL_19

  3534.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3535.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  3536.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3537.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  3538.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  3539.   *

  3540.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  3541.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  3542.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  3543.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  3544.   *         (1, 2) For ADC channel read back from ADC register,

  3545.   *                comparison with internal channel parameter to be done

  3546.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  3547.   */

  3548. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  3549. {

  3550.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));

  3551. 

  3552.   return (uint32_t)((READ_BIT(*preg,

  3553.                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))

  3554.                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

  3555.                    );

  3556. }

  3557. 

  3558. /**

  3559.   * @brief  Set ADC continuous conversion mode on ADC group regular.

  3560.   * @note   Description of ADC continuous conversion mode:

  3561.   *         - single mode: one conversion per trigger

  3562.   *         - continuous mode: after the first trigger, following

  3563.   *           conversions launched successively automatically.

  3564.   * @note   It is not possible to enable both ADC group regular

  3565.   *         continuous mode and sequencer discontinuous mode.

  3566.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3567.   *         ADC state:

  3568.   *         ADC must be disabled or enabled without conversion on going

  3569.   *         on group regular.

  3570.   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode

  3571.   * @param  ADCx ADC instance

  3572.   * @param  Continuous This parameter can be one of the following values:

  3573.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  3574.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  3575.   * @retval None

  3576.   */

  3577. __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)

  3578. {

  3579.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);

  3580. }

  3581. 

  3582. /**

  3583.   * @brief  Get ADC continuous conversion mode on ADC group regular.

  3584.   * @note   Description of ADC continuous conversion mode:

  3585.   *         - single mode: one conversion per trigger

  3586.   *         - continuous mode: after the first trigger, following

  3587.   *           conversions launched successively automatically.

  3588.   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode

  3589.   * @param  ADCx ADC instance

  3590.   * @retval Returned value can be one of the following values:

  3591.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  3592.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  3593.   */

  3594. __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)

  3595. {

  3596.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));

  3597. }

  3598. /**

  3599.   * @brief  Set ADC data transfer mode

  3600.   * @note   Conversion data can be either:

  3601.   *            - Available in Data Register

  3602.   *            - Transfered by DMA in one shot mode

  3603.   *            - Transfered by DMA in circular mode

  3604.   *            - Transfered to DFSDM data register

  3605.   * @rmtoll CFGR     DMNGT           LL_ADC_REG_SetDataTransferMode

  3606.   * @param  ADCx ADC instance

  3607.   * @param  DataTransferMode This parameter can be one of the following values:

  3608.   *         @arg @ref LL_ADC_REG_DR_TRANSFER

  3609.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  3610.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  3611.   *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER

  3612.   * @retval None

  3613.   */

  3614. __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)

  3615. {

  3616.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);

  3617. }

  3618. 

  3619. 

  3620. /**

  3621.   * @brief  Get ADC data transfer mode

  3622.   * @note   Conversion data can be either:

  3623.   *            - Available in Data Register

  3624.   *            - Transfered by DMA in one shot mode

  3625.   *            - Transfered by DMA in circular mode

  3626.   *            - Transfered to DFSDM data register

  3627.   * @rmtoll CFGR     DMNGT           LL_ADC_REG_GetDataTransferMode

  3628.   * @param  ADCx ADC instance

  3629.   * @retval Returned value can be one of the following values:

  3630.   *         @arg @ref LL_ADC_REG_DR_TRANSFER

  3631.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  3632.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  3633.   *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER

  3634.   */

  3635. __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)

  3636. {

  3637.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));

  3638. }

  3639. 

  3640. 

  3641. /**

  3642.   * @brief  Set ADC group regular behavior in case of overrun:

  3643.   *         data preserved or overwritten.

  3644.   * @note   Compatibility with devices without feature overrun:

  3645.   *         other devices without this feature have a behavior

  3646.   *         equivalent to data overwritten.

  3647.   *         The default setting of overrun is data preserved.

  3648.   *         Therefore, for compatibility with all devices, parameter

  3649.   *         overrun should be set to data overwritten.

  3650.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3651.   *         ADC state:

  3652.   *         ADC must be disabled or enabled without conversion on going

  3653.   *         on group regular.

  3654.   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun

  3655.   * @param  ADCx ADC instance

  3656.   * @param  Overrun This parameter can be one of the following values:

  3657.   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED

  3658.   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN

  3659.   * @retval None

  3660.   */

  3661. __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)

  3662. {

  3663.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);

  3664. }

  3665. 

  3666. /**

  3667.   * @brief  Get ADC group regular behavior in case of overrun:

  3668.   *         data preserved or overwritten.

  3669.   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun

  3670.   * @param  ADCx ADC instance

  3671.   * @retval Returned value can be one of the following values:

  3672.   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED

  3673.   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN

  3674.   */

  3675. __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)

  3676. {

  3677.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));

  3678. }

  3679. 

  3680. /**

  3681.   * @}

  3682.   */

  3683. 

  3684. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected

  3685.   * @{

  3686.   */

  3687. 

  3688. /**

  3689.   * @brief  Set ADC group injected conversion trigger source:

  3690.   *         internal (SW start) or from external peripheral (timer event,

  3691.   *         external interrupt line).

  3692.   * @note   On this STM32 serie, setting trigger source to external trigger

  3693.   *         also set trigger polarity to rising edge

  3694.   *         (default setting for compatibility with some ADC on other

  3695.   *         STM32 families having this setting set by HW default value).

  3696.   *         In case of need to modify trigger edge, use

  3697.   *         function @ref LL_ADC_INJ_SetTriggerEdge().

  3698.   * @note   Availability of parameters of trigger sources from timer

  3699.   *         depends on timers availability on the selected device.

  3700.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3701.   *         ADC state:

  3702.   *         ADC must not be disabled. Can be enabled with or without conversion

  3703.   *         on going on either groups regular or injected.

  3704.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n

  3705.   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource

  3706.   * @param  ADCx ADC instance

  3707.   * @param  TriggerSource This parameter can be one of the following values:

  3708.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  3709.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  3710.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  3711.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  3712.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  3713.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  3714.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  3715.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  3716.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

  3717.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  3718.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

  3719.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

  3720.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

  3721.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

  3722.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

  3723.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

  3724.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

  3725.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

  3726.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

  3727.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

  3728.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

  3729.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

  3730.   * @retval None

  3731.   */

  3732. __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  3733. {

  3734.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);

  3735. }

  3736. 

  3737. /**

  3738.   * @brief  Get ADC group injected conversion trigger source:

  3739.   *         internal (SW start) or from external peripheral (timer event,

  3740.   *         external interrupt line).

  3741.   * @note   To determine whether group injected trigger source is

  3742.   *         internal (SW start) or external, without detail

  3743.   *         of which peripheral is selected as external trigger,

  3744.   *         (equivalent to

  3745.   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")

  3746.   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.

  3747.   * @note   Availability of parameters of trigger sources from timer

  3748.   *         depends on timers availability on the selected device.

  3749.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n

  3750.   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource

  3751.   * @param  ADCx ADC instance

  3752.   * @retval Returned value can be one of the following values:

  3753.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  3754.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  3755.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  3756.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  3757.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  3758.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  3759.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  3760.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  3761.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

  3762.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  3763.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

  3764.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

  3765.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

  3766.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

  3767.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

  3768.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

  3769.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

  3770.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

  3771.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

  3772.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

  3773.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

  3774.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

  3775.   */

  3776. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)

  3777. {

  3778.   register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);

  3779. 

  3780.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  3781.   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */

  3782.   register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));

  3783. 

  3784.   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */

  3785.   /* to match with triggers literals definition.                              */

  3786.   return ((TriggerSource

  3787.            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)

  3788.           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)

  3789.          );

  3790. }

  3791. 

  3792. /**

  3793.   * @brief  Get ADC group injected conversion trigger source internal (SW start)

  3794.             or external

  3795.   * @note   In case of group injected trigger source set to external trigger,

  3796.   *         to determine which peripheral is selected as external trigger,

  3797.   *         use function @ref LL_ADC_INJ_GetTriggerSource.

  3798.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart

  3799.   * @param  ADCx ADC instance

  3800.   * @retval Value "0" if trigger source external trigger

  3801.   *         Value "1" if trigger source SW start.

  3802.   */

  3803. __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  3804. {

  3805.   return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);

  3806. }

  3807. 

  3808. /**

  3809.   * @brief  Set ADC group injected conversion trigger polarity.

  3810.   *         Applicable only for trigger source set to external trigger.

  3811.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3812.   *         ADC state:

  3813.   *         ADC must not be disabled. Can be enabled with or without conversion

  3814.   *         on going on either groups regular or injected.

  3815.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge

  3816.   * @param  ADCx ADC instance

  3817.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  3818.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  3819.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  3820.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  3821.   * @retval None

  3822.   */

  3823. __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  3824. {

  3825.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);

  3826. }

  3827. 

  3828. /**

  3829.   * @brief  Get ADC group injected conversion trigger polarity.

  3830.   *         Applicable only for trigger source set to external trigger.

  3831.   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge

  3832.   * @param  ADCx ADC instance

  3833.   * @retval Returned value can be one of the following values:

  3834.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  3835.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  3836.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  3837.   */

  3838. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)

  3839. {

  3840.   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));

  3841. }

  3842. 

  3843. /**

  3844.   * @brief  Set ADC group injected sequencer length and scan direction.

  3845.   * @note   This function performs configuration of:

  3846.   *         - Sequence length: Number of ranks in the scan sequence.

  3847.   *         - Sequence direction: Unless specified in parameters, sequencer

  3848.   *           scan direction is forward (from rank 1 to rank n).

  3849.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3850.   *         ADC conversion on only 1 channel.

  3851.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3852.   *         ADC state:

  3853.   *         ADC must not be disabled. Can be enabled with or without conversion

  3854.   *         on going on either groups regular or injected.

  3855.   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength

  3856.   * @param  ADCx ADC instance

  3857.   * @param  SequencerNbRanks This parameter can be one of the following values:

  3858.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  3859.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  3860.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  3861.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  3862.   * @retval None

  3863.   */

  3864. __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  3865. {

  3866.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);

  3867. }

  3868. 

  3869. /**

  3870.   * @brief  Get ADC group injected sequencer length and scan direction.

  3871.   * @note   This function retrieves:

  3872.   *         - Sequence length: Number of ranks in the scan sequence.

  3873.   *         - Sequence direction: Unless specified in parameters, sequencer

  3874.   *           scan direction is forward (from rank 1 to rank n).

  3875.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3876.   *         ADC conversion on only 1 channel.

  3877.   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength

  3878.   * @param  ADCx ADC instance

  3879.   * @retval Returned value can be one of the following values:

  3880.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  3881.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  3882.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  3883.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  3884.   */

  3885. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)

  3886. {

  3887.   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));

  3888. }

  3889. 

  3890. /**

  3891.   * @brief  Set ADC group injected sequencer discontinuous mode:

  3892.   *         sequence subdivided and scan conversions interrupted every selected

  3893.   *         number of ranks.

  3894.   * @note   It is not possible to enable both ADC group injected

  3895.   *         auto-injected mode and sequencer discontinuous mode.

  3896.   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont

  3897.   * @param  ADCx ADC instance

  3898.   * @param  SeqDiscont This parameter can be one of the following values:

  3899.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  3900.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  3901.   * @retval None

  3902.   */

  3903. __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  3904. {

  3905.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);

  3906. }

  3907. 

  3908. /**

  3909.   * @brief  Get ADC group injected sequencer discontinuous mode:

  3910.   *         sequence subdivided and scan conversions interrupted every selected

  3911.   *         number of ranks.

  3912.   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont

  3913.   * @param  ADCx ADC instance

  3914.   * @retval Returned value can be one of the following values:

  3915.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  3916.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  3917.   */

  3918. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)

  3919. {

  3920.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));

  3921. }

  3922. 

  3923. /**

  3924.   * @brief  Set ADC group injected sequence: channel on the selected

  3925.   *         sequence rank.

  3926.   * @note   Depending on devices and packages, some channels may not be available.

  3927.   *         Refer to device datasheet for channels availability.

  3928.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  3929.   *         TempSensor, ...), measurement paths to internal channels must be

  3930.   *         enabled separately.

  3931.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  3932.   * @note   On STM32H7, some fast channels are available: fast analog inputs

  3933.   *         coming from GPIO pads (ADC_IN0..5).

  3934.   * @note   On this STM32 serie, setting of this feature is conditioned to

  3935.   *         ADC state:

  3936.   *         ADC must not be disabled. Can be enabled with or without conversion

  3937.   *         on going on either groups regular or injected.

  3938.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n

  3939.   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n

  3940.   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n

  3941.   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks

  3942.   * @param  ADCx ADC instance

  3943.   * @param  Rank This parameter can be one of the following values:

  3944.   *         @arg @ref LL_ADC_INJ_RANK_1

  3945.   *         @arg @ref LL_ADC_INJ_RANK_2

  3946.   *         @arg @ref LL_ADC_INJ_RANK_3

  3947.   *         @arg @ref LL_ADC_INJ_RANK_4

  3948.   * @param  Channel This parameter can be one of the following values:

  3949.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  3950.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  3951.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  3952.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  3953.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  3954.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  3955.   *         @arg @ref LL_ADC_CHANNEL_6

  3956.   *         @arg @ref LL_ADC_CHANNEL_7

  3957.   *         @arg @ref LL_ADC_CHANNEL_8

  3958.   *         @arg @ref LL_ADC_CHANNEL_9

  3959.   *         @arg @ref LL_ADC_CHANNEL_10

  3960.   *         @arg @ref LL_ADC_CHANNEL_11

  3961.   *         @arg @ref LL_ADC_CHANNEL_12

  3962.   *         @arg @ref LL_ADC_CHANNEL_13

  3963.   *         @arg @ref LL_ADC_CHANNEL_14

  3964.   *         @arg @ref LL_ADC_CHANNEL_15

  3965.   *         @arg @ref LL_ADC_CHANNEL_16

  3966.   *         @arg @ref LL_ADC_CHANNEL_17

  3967.   *         @arg @ref LL_ADC_CHANNEL_18

  3968.   *         @arg @ref LL_ADC_CHANNEL_19

  3969.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3970.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  3971.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3972.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  3973.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  3974.   *

  3975.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  3976.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  3977.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  3978.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  3979.   * @retval None

  3980.   */

  3981. __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  3982. {

  3983.   /* Set bits with content of parameter "Channel" with bits position          */

  3984.   /* in register depending on parameter "Rank".                               */

  3985.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  3986.   /* other bits reserved for other purpose.                                   */

  3987.   MODIFY_REG(ADCx->JSQR,

  3988.              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),

  3989.              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));

  3990. }

  3991. 

  3992. /**

  3993.   * @brief  Get ADC group injected sequence: channel on the selected

  3994.   *         sequence rank.

  3995.   * @note   Depending on devices and packages, some channels may not be available.

  3996.   *         Refer to device datasheet for channels availability.

  3997.   * @note   Usage of the returned channel number:

  3998.   *         - To reinject this channel into another function LL_ADC_xxx:

  3999.   *           the returned channel number is only partly formatted on definition

  4000.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  4001.   *           with parts of literals LL_ADC_CHANNEL_x or using

  4002.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4003.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  4004.   *           as parameter for another function.

  4005.   *         - To get the channel number in decimal format:

  4006.   *           process the returned value with the helper macro

  4007.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4008.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n

  4009.   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n

  4010.   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n

  4011.   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks

  4012.   * @param  ADCx ADC instance

  4013.   * @param  Rank This parameter can be one of the following values:

  4014.   *         @arg @ref LL_ADC_INJ_RANK_1

  4015.   *         @arg @ref LL_ADC_INJ_RANK_2

  4016.   *         @arg @ref LL_ADC_INJ_RANK_3

  4017.   *         @arg @ref LL_ADC_INJ_RANK_4

  4018.   * @retval Returned value can be one of the following values:

  4019.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4020.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4021.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4022.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4023.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4024.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4025.   *         @arg @ref LL_ADC_CHANNEL_6

  4026.   *         @arg @ref LL_ADC_CHANNEL_7

  4027.   *         @arg @ref LL_ADC_CHANNEL_8

  4028.   *         @arg @ref LL_ADC_CHANNEL_9

  4029.   *         @arg @ref LL_ADC_CHANNEL_10

  4030.   *         @arg @ref LL_ADC_CHANNEL_11

  4031.   *         @arg @ref LL_ADC_CHANNEL_12

  4032.   *         @arg @ref LL_ADC_CHANNEL_13

  4033.   *         @arg @ref LL_ADC_CHANNEL_14

  4034.   *         @arg @ref LL_ADC_CHANNEL_15

  4035.   *         @arg @ref LL_ADC_CHANNEL_16

  4036.   *         @arg @ref LL_ADC_CHANNEL_17

  4037.   *         @arg @ref LL_ADC_CHANNEL_18

  4038.   *         @arg @ref LL_ADC_CHANNEL_19

  4039.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4040.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4041.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4042.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4043.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4044.   *

  4045.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4046.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4047.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4048.   *             Other channels are slow channels (conversion rate: refer to reference manual).\n

  4049.   *         (1, 2) For ADC channel read back from ADC register,

  4050.   *                comparison with internal channel parameter to be done

  4051.   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  4052.   */

  4053. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  4054. {

  4055.   return (uint32_t)((READ_BIT(ADCx->JSQR,

  4056.                               (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))

  4057.                      >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

  4058.                    );

  4059. }

  4060. 

  4061. /**

  4062.   * @brief  Set ADC group injected conversion trigger:

  4063.   *         independent or from ADC group regular.

  4064.   * @note   This mode can be used to extend number of data registers

  4065.   *         updated after one ADC conversion trigger and with data

  4066.   *         permanently kept (not erased by successive conversions of scan of

  4067.   *         ADC sequencer ranks), up to 5 data registers:

  4068.   *         1 data register on ADC group regular, 4 data registers

  4069.   *         on ADC group injected.

  4070.   * @note   If ADC group injected injected trigger source is set to an

  4071.   *         external trigger, this feature must be must be set to

  4072.   *         independent trigger.

  4073.   *         ADC group injected automatic trigger is compliant only with

  4074.   *         group injected trigger source set to SW start, without any

  4075.   *         further action on  ADC group injected conversion start or stop:

  4076.   *         in this case, ADC group injected is controlled only

  4077.   *         from ADC group regular.

  4078.   * @note   It is not possible to enable both ADC group injected

  4079.   *         auto-injected mode and sequencer discontinuous mode.

  4080.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4081.   *         ADC state:

  4082.   *         ADC must be disabled or enabled without conversion on going

  4083.   *         on either groups regular or injected.

  4084.   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto

  4085.   * @param  ADCx ADC instance

  4086.   * @param  TrigAuto This parameter can be one of the following values:

  4087.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  4088.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  4089.   * @retval None

  4090.   */

  4091. __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)

  4092. {

  4093.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);

  4094. }

  4095. 

  4096. /**

  4097.   * @brief  Get ADC group injected conversion trigger:

  4098.   *         independent or from ADC group regular.

  4099.   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto

  4100.   * @param  ADCx ADC instance

  4101.   * @retval Returned value can be one of the following values:

  4102.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  4103.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  4104.   */

  4105. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)

  4106. {

  4107.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));

  4108. }

  4109. 

  4110. /**

  4111.   * @brief  Set ADC group injected contexts queue mode.

  4112.   * @note   A context is a setting of group injected sequencer:

  4113.   *         - group injected trigger

  4114.   *         - sequencer length

  4115.   *         - sequencer ranks

  4116.   *         If contexts queue is disabled:

  4117.   *         - only 1 sequence can be configured

  4118.   *           and is active perpetually.

  4119.   *         If contexts queue is enabled:

  4120.   *         - up to 2 contexts can be queued

  4121.   *           and are checked in and out as a FIFO stack (first-in, first-out).

  4122.   *         - If a new context is set when queues is full, error is triggered

  4123.   *           by interruption "Injected Queue Overflow".

  4124.   *         - Two behaviors are possible when all contexts have been processed:

  4125.   *           the contexts queue can maintain the last context active perpetually

  4126.   *           or can be empty and injected group triggers are disabled.

  4127.   *         - Triggers can be only external (not internal SW start)

  4128.   *         - Caution: The sequence must be fully configured in one time

  4129.   *           (one write of register JSQR makes a check-in of a new context

  4130.   *           into the queue).

  4131.   *           Therefore functions to set separately injected trigger and

  4132.   *           sequencer channels cannot be used, register JSQR must be set

  4133.   *           using function @ref LL_ADC_INJ_ConfigQueueContext().

  4134.   * @note   This parameter can be modified only when no conversion is on going

  4135.   *         on either groups regular or injected.

  4136.   * @note   A modification of the context mode (bit JQDIS) causes the contexts

  4137.   *         queue to be flushed and the register JSQR is cleared.

  4138.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4139.   *         ADC state:

  4140.   *         ADC must be disabled or enabled without conversion on going

  4141.   *         on either groups regular or injected.

  4142.   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n

  4143.   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode

  4144.   * @param  ADCx ADC instance

  4145.   * @param  QueueMode This parameter can be one of the following values:

  4146.   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE

  4147.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE

  4148.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

  4149.   * @retval None

  4150.   */

  4151. __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)

  4152. {

  4153.   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);

  4154. }

  4155. 

  4156. /**

  4157.   * @brief  Get ADC group injected context queue mode.

  4158.   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n

  4159.   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode

  4160.   * @param  ADCx ADC instance

  4161.   * @retval Returned value can be one of the following values:

  4162.   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE

  4163.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE

  4164.   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

  4165.   */

  4166. __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)

  4167. {

  4168.   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));

  4169. }

  4170. 

  4171. /**

  4172.   * @brief  Set one context on ADC group injected that will be checked in

  4173.   *         contexts queue.

  4174.   * @note   A context is a setting of group injected sequencer:

  4175.   *         - group injected trigger

  4176.   *         - sequencer length

  4177.   *         - sequencer ranks

  4178.   *         This function is intended to be used when contexts queue is enabled,

  4179.   *         because the sequence must be fully configured in one time

  4180.   *         (functions to set separately injected trigger and sequencer channels

  4181.   *         cannot be used):

  4182.   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().

  4183.   * @note   In the contexts queue, only the active context can be read.

  4184.   *         The parameters of this function can be read using functions:

  4185.   *         @arg @ref LL_ADC_INJ_GetTriggerSource()

  4186.   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()

  4187.   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()

  4188.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  4189.   *         TempSensor, ...), measurement paths to internal channels must be

  4190.   *         enabled separately.

  4191.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  4192.   * @note   On STM32H7, some fast channels are available: fast analog inputs

  4193.   *         coming from GPIO pads (ADC_IN0..5).

  4194.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4195.   *         ADC state:

  4196.   *         ADC must not be disabled. Can be enabled with or without conversion

  4197.   *         on going on either groups regular or injected.

  4198.   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n

  4199.   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n

  4200.   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n

  4201.   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n

  4202.   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n

  4203.   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n

  4204.   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext

  4205.   * @param  ADCx ADC instance

  4206.   * @param  TriggerSource This parameter can be one of the following values:

  4207.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  4208.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  4209.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  4210.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  4211.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  4212.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  4213.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  4214.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  4215.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

  4216.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  4217.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

  4218.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

  4219.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

  4220.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

  4221.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

  4222.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

  4223.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

  4224.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

  4225.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

  4226.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

  4227.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

  4228.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

  4229.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  4230.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  4231.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  4232.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  4233.   *

  4234.   *         Note: This parameter is discarded in case of SW start:

  4235.   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".

  4236.   * @param  SequencerNbRanks This parameter can be one of the following values:

  4237.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  4238.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  4239.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  4240.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  4241.   * @param  Rank1_Channel This parameter can be one of the following values:

  4242.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4243.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4244.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4245.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4246.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4247.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4248.   *         @arg @ref LL_ADC_CHANNEL_6

  4249.   *         @arg @ref LL_ADC_CHANNEL_7

  4250.   *         @arg @ref LL_ADC_CHANNEL_8

  4251.   *         @arg @ref LL_ADC_CHANNEL_9

  4252.   *         @arg @ref LL_ADC_CHANNEL_10

  4253.   *         @arg @ref LL_ADC_CHANNEL_11

  4254.   *         @arg @ref LL_ADC_CHANNEL_12

  4255.   *         @arg @ref LL_ADC_CHANNEL_13

  4256.   *         @arg @ref LL_ADC_CHANNEL_14

  4257.   *         @arg @ref LL_ADC_CHANNEL_15

  4258.   *         @arg @ref LL_ADC_CHANNEL_16

  4259.   *         @arg @ref LL_ADC_CHANNEL_17

  4260.   *         @arg @ref LL_ADC_CHANNEL_18

  4261.   *         @arg @ref LL_ADC_CHANNEL_19

  4262.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4263.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4264.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4265.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4266.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4267.   *

  4268.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4269.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4270.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4271.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4272.   * @param  Rank2_Channel This parameter can be one of the following values:

  4273.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4274.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4275.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4276.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4277.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4278.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4279.   *         @arg @ref LL_ADC_CHANNEL_6

  4280.   *         @arg @ref LL_ADC_CHANNEL_7

  4281.   *         @arg @ref LL_ADC_CHANNEL_8

  4282.   *         @arg @ref LL_ADC_CHANNEL_9

  4283.   *         @arg @ref LL_ADC_CHANNEL_10

  4284.   *         @arg @ref LL_ADC_CHANNEL_11

  4285.   *         @arg @ref LL_ADC_CHANNEL_12

  4286.   *         @arg @ref LL_ADC_CHANNEL_13

  4287.   *         @arg @ref LL_ADC_CHANNEL_14

  4288.   *         @arg @ref LL_ADC_CHANNEL_15

  4289.   *         @arg @ref LL_ADC_CHANNEL_16

  4290.   *         @arg @ref LL_ADC_CHANNEL_17

  4291.   *         @arg @ref LL_ADC_CHANNEL_18

  4292.   *         @arg @ref LL_ADC_CHANNEL_19

  4293.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4294.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4295.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4296.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4297.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4298.   *

  4299.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4300.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4301.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4302.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4303.   * @param  Rank3_Channel This parameter can be one of the following values:

  4304.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4305.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4306.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4307.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4308.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4309.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4310.   *         @arg @ref LL_ADC_CHANNEL_6

  4311.   *         @arg @ref LL_ADC_CHANNEL_7

  4312.   *         @arg @ref LL_ADC_CHANNEL_8

  4313.   *         @arg @ref LL_ADC_CHANNEL_9

  4314.   *         @arg @ref LL_ADC_CHANNEL_10

  4315.   *         @arg @ref LL_ADC_CHANNEL_11

  4316.   *         @arg @ref LL_ADC_CHANNEL_12

  4317.   *         @arg @ref LL_ADC_CHANNEL_13

  4318.   *         @arg @ref LL_ADC_CHANNEL_14

  4319.   *         @arg @ref LL_ADC_CHANNEL_15

  4320.   *         @arg @ref LL_ADC_CHANNEL_16

  4321.   *         @arg @ref LL_ADC_CHANNEL_17

  4322.   *         @arg @ref LL_ADC_CHANNEL_18

  4323.   *         @arg @ref LL_ADC_CHANNEL_19

  4324.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4325.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4326.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4327.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4328.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4329.   *

  4330.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4331.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4332.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4333.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4334.   * @param  Rank4_Channel This parameter can be one of the following values:

  4335.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4336.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4337.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4338.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4339.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4340.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4341.   *         @arg @ref LL_ADC_CHANNEL_6

  4342.   *         @arg @ref LL_ADC_CHANNEL_7

  4343.   *         @arg @ref LL_ADC_CHANNEL_8

  4344.   *         @arg @ref LL_ADC_CHANNEL_9

  4345.   *         @arg @ref LL_ADC_CHANNEL_10

  4346.   *         @arg @ref LL_ADC_CHANNEL_11

  4347.   *         @arg @ref LL_ADC_CHANNEL_12

  4348.   *         @arg @ref LL_ADC_CHANNEL_13

  4349.   *         @arg @ref LL_ADC_CHANNEL_14

  4350.   *         @arg @ref LL_ADC_CHANNEL_15

  4351.   *         @arg @ref LL_ADC_CHANNEL_16

  4352.   *         @arg @ref LL_ADC_CHANNEL_17

  4353.   *         @arg @ref LL_ADC_CHANNEL_18

  4354.   *         @arg @ref LL_ADC_CHANNEL_19

  4355.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4356.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4357.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4358.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4359.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4360.   *

  4361.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4362.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4363.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4364.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4365.   * @retval None

  4366.   */

  4367. __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,

  4368.                                                    uint32_t TriggerSource,

  4369.                                                    uint32_t ExternalTriggerEdge,

  4370.                                                    uint32_t SequencerNbRanks,

  4371.                                                    uint32_t Rank1_Channel,

  4372.                                                    uint32_t Rank2_Channel,

  4373.                                                    uint32_t Rank3_Channel,

  4374.                                                    uint32_t Rank4_Channel)

  4375. {

  4376.   /* Set bits with content of parameter "Rankx_Channel" with bits position    */

  4377.   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */

  4378.   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */

  4379.   /* because containing other bits reserved for other purpose.                */

  4380.   /* If parameter "TriggerSource" is set to SW start, then parameter          */

  4381.   /* "ExternalTriggerEdge" is discarded.                                      */

  4382.   register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);

  4383.   MODIFY_REG(ADCx->JSQR,

  4384.              ADC_JSQR_JEXTSEL |

  4385.              ADC_JSQR_JEXTEN  |

  4386.              ADC_JSQR_JSQ4    |

  4387.              ADC_JSQR_JSQ3    |

  4388.              ADC_JSQR_JSQ2    |

  4389.              ADC_JSQR_JSQ1    |

  4390.              ADC_JSQR_JL,

  4391.              (TriggerSource & ADC_JSQR_JEXTSEL)          |

  4392.              (ExternalTriggerEdge * (is_trigger_not_sw)) |

  4393.              (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  4394.              (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  4395.              (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  4396.              (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |

  4397.              SequencerNbRanks

  4398.             );

  4399. }

  4400. 

  4401. /**

  4402.   * @}

  4403.   */

  4404. 

  4405. /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels

  4406.   * @{

  4407.   */

  4408. 

  4409. /**

  4410.   * @brief  Set sampling time of the selected ADC channel

  4411.   *         Unit: ADC clock cycles.

  4412.   * @note   On this device, sampling time is on channel scope: independently

  4413.   *         of channel mapped on ADC group regular or injected.

  4414.   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be

  4415.   *         converted:

  4416.   *         sampling time constraints must be respected (sampling time can be

  4417.   *         adjusted in function of ADC clock frequency and sampling time

  4418.   *         setting).

  4419.   *         Refer to device datasheet for timings values (parameters TS_vrefint,

  4420.   *         TS_temp, ...).

  4421.   * @note   Conversion time is the addition of sampling time and processing time.

  4422.   *         On this STM32 serie, ADC processing time is:

  4423.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  4424.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  4425.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  4426.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  4427.   * @note   In case of ADC conversion of internal channel (VrefInt,

  4428.   *         temperature sensor, ...), a sampling time minimum value

  4429.   *         is required.

  4430.   *         Refer to device datasheet.

  4431.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4432.   *         ADC state:

  4433.   *         ADC must be disabled or enabled without conversion on going

  4434.   *         on either groups regular or injected.

  4435.   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n

  4436.   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n

  4437.   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n

  4438.   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n

  4439.   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n

  4440.   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n

  4441.   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n

  4442.   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n

  4443.   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n

  4444.   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n

  4445.   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n

  4446.   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n

  4447.   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n

  4448.   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n

  4449.   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n

  4450.   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n

  4451.   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n

  4452.   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n

  4453.   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime

  4454.   * @param  ADCx ADC instance

  4455.   * @param  Channel This parameter can be one of the following values:

  4456.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4457.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4458.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4459.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4460.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4461.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4462.   *         @arg @ref LL_ADC_CHANNEL_6

  4463.   *         @arg @ref LL_ADC_CHANNEL_7

  4464.   *         @arg @ref LL_ADC_CHANNEL_8

  4465.   *         @arg @ref LL_ADC_CHANNEL_9

  4466.   *         @arg @ref LL_ADC_CHANNEL_10

  4467.   *         @arg @ref LL_ADC_CHANNEL_11

  4468.   *         @arg @ref LL_ADC_CHANNEL_12

  4469.   *         @arg @ref LL_ADC_CHANNEL_13

  4470.   *         @arg @ref LL_ADC_CHANNEL_14

  4471.   *         @arg @ref LL_ADC_CHANNEL_15

  4472.   *         @arg @ref LL_ADC_CHANNEL_16

  4473.   *         @arg @ref LL_ADC_CHANNEL_17

  4474.   *         @arg @ref LL_ADC_CHANNEL_18

  4475.   *         @arg @ref LL_ADC_CHANNEL_19

  4476.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4477.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4478.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4479.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4480.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4481.   *

  4482.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4483.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4484.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4485.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4486.   * @param  SamplingTime This parameter can be one of the following values:

  4487.   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5

  4488.   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5

  4489.   *         @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5

  4490.   *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5

  4491.   *         @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5

  4492.   *         @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5

  4493.   *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5

  4494.   *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5

  4495.   * @retval None

  4496.   */

  4497. __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)

  4498. {

  4499.   /* Set bits with content of parameter "SamplingTime" with bits position     */

  4500.   /* in register and register position depending on parameter "Channel".      */

  4501.   /* Parameter "Channel" is used with masks because containing                */

  4502.   /* other bits reserved for other purpose.                                   */

  4503.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));

  4504. 

  4505.   MODIFY_REG(*preg,

  4506.              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),

  4507.              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));

  4508. }

  4509. 

  4510. /**

  4511.   * @brief  Get sampling time of the selected ADC channel

  4512.   *         Unit: ADC clock cycles.

  4513.   * @note   On this device, sampling time is on channel scope: independently

  4514.   *         of channel mapped on ADC group regular or injected.

  4515.   * @note   Conversion time is the addition of sampling time and processing time.

  4516.   *         On this STM32 serie, ADC processing time is:

  4517.   *         - 12.5 ADC clock cycles at ADC resolution 12 bits

  4518.   *         - 10.5 ADC clock cycles at ADC resolution 10 bits

  4519.   *         - 8.5 ADC clock cycles at ADC resolution 8 bits

  4520.   *         - 6.5 ADC clock cycles at ADC resolution 6 bits

  4521.   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n

  4522.   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n

  4523.   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n

  4524.   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n

  4525.   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n

  4526.   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n

  4527.   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n

  4528.   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n

  4529.   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n

  4530.   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n

  4531.   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n

  4532.   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n

  4533.   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n

  4534.   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n

  4535.   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n

  4536.   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n

  4537.   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n

  4538.   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n

  4539.   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime

  4540.   * @param  ADCx ADC instance

  4541.   * @param  Channel This parameter can be one of the following values:

  4542.   *         @arg @ref LL_ADC_CHANNEL_0           (3)

  4543.   *         @arg @ref LL_ADC_CHANNEL_1           (3)

  4544.   *         @arg @ref LL_ADC_CHANNEL_2           (3)

  4545.   *         @arg @ref LL_ADC_CHANNEL_3           (3)

  4546.   *         @arg @ref LL_ADC_CHANNEL_4           (3)

  4547.   *         @arg @ref LL_ADC_CHANNEL_5           (3)

  4548.   *         @arg @ref LL_ADC_CHANNEL_6

  4549.   *         @arg @ref LL_ADC_CHANNEL_7

  4550.   *         @arg @ref LL_ADC_CHANNEL_8

  4551.   *         @arg @ref LL_ADC_CHANNEL_9

  4552.   *         @arg @ref LL_ADC_CHANNEL_10

  4553.   *         @arg @ref LL_ADC_CHANNEL_11

  4554.   *         @arg @ref LL_ADC_CHANNEL_12

  4555.   *         @arg @ref LL_ADC_CHANNEL_13

  4556.   *         @arg @ref LL_ADC_CHANNEL_14

  4557.   *         @arg @ref LL_ADC_CHANNEL_15

  4558.   *         @arg @ref LL_ADC_CHANNEL_16

  4559.   *         @arg @ref LL_ADC_CHANNEL_17

  4560.   *         @arg @ref LL_ADC_CHANNEL_18

  4561.   *         @arg @ref LL_ADC_CHANNEL_19

  4562.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  4563.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

  4564.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  4565.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

  4566.   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

  4567.   *

  4568.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4569.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

  4570.   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

  4571.   *             Other channels are slow channels (conversion rate: refer to reference manual).

  4572.   * @retval Returned value can be one of the following values:

  4573.   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5

  4574.   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5

  4575.   *         @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5

  4576.   *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5

  4577.   *         @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5

  4578.   *         @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5

  4579.   *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5

  4580.   *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5

  4581.   */

  4582. __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)

  4583. {

  4584.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));

  4585. 

  4586.   return (uint32_t)(READ_BIT(*preg,

  4587.                              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))

  4588.                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)

  4589.                    );

  4590. }

  4591. 

  4592. /**

  4593.   * @brief  Set mode single-ended or differential input of the selected

  4594.   *         ADC channel.

  4595.   * @note   Channel ending is on channel scope: independently of channel mapped

  4596.   *         on ADC group regular or injected.

  4597.   *         In differential mode: Differential measurement is carried out

  4598.   *         between the selected channel 'i' (positive input) and

  4599.   *         channel 'i+1' (negative input). Only channel 'i' has to be

  4600.   *         configured, channel 'i+1' is configured automatically.

  4601.   * @note   Refer to Reference Manual to ensure the selected channel is

  4602.   *         available in differential mode.

  4603.   *         For example, internal channels (VrefInt, TempSensor, ...) are

  4604.   *         not available in differential mode.

  4605.   * @note   When configuring a channel 'i' in differential mode,

  4606.   *         the channel 'i+1' is not usable separately.

  4607.   * @note   On STM32H7, some channels are internally fixed to single-ended inputs

  4608.   *         configuration:

  4609.   *         - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19

  4610.   *         - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19

  4611.   *         - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19

  4612.   * @note   For ADC channels configured in differential mode, both inputs

  4613.   *         should be biased at (Vref+)/2 +/-200mV.

  4614.   *         (Vref+ is the analog voltage reference)

  4615.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4616.   *         ADC state:

  4617.   *         ADC must be ADC disabled.

  4618.   * @note   One or several values can be selected.

  4619.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  4620.   * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff

  4621.   * @param  ADCx ADC instance

  4622.   * @param  Channel This parameter can be one of the following values:

  4623.   *         @arg @ref LL_ADC_CHANNEL_1

  4624.   *         @arg @ref LL_ADC_CHANNEL_2

  4625.   *         @arg @ref LL_ADC_CHANNEL_3

  4626.   *         @arg @ref LL_ADC_CHANNEL_4

  4627.   *         @arg @ref LL_ADC_CHANNEL_5

  4628.   *         @arg @ref LL_ADC_CHANNEL_10

  4629.   *         @arg @ref LL_ADC_CHANNEL_11

  4630.   *         @arg @ref LL_ADC_CHANNEL_12

  4631.   *         @arg @ref LL_ADC_CHANNEL_13

  4632.   *         @arg @ref LL_ADC_CHANNEL_14

  4633.   *         @arg @ref LL_ADC_CHANNEL_15

  4634.   *         @arg @ref LL_ADC_CHANNEL_16

  4635.   *         @arg @ref LL_ADC_CHANNEL_17

  4636.   *         @arg @ref LL_ADC_CHANNEL_18

  4637.   *         @arg @ref LL_ADC_CHANNEL_19

  4638.   * @param  SingleDiff This parameter can be a combination of the following values:

  4639.   *         @arg @ref LL_ADC_SINGLE_ENDED

  4640.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  4641.   * @retval None

  4642.   */

  4643. __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)

  4644. {

  4645.   /* Bits of channels in single or differential mode are set only for         */

  4646.   /* differential mode (for single mode, mask of bits allowed to be set is    */

  4647.   /* shifted out of range of bits of channels in single or differential mode. */

  4648.   MODIFY_REG(ADCx->DIFSEL,

  4649.              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,

  4650.              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));

  4651. }

  4652. 

  4653. /**

  4654.   * @brief  Get mode single-ended or differential input of the selected

  4655.   *         ADC channel.

  4656.   * @note   When configuring a channel 'i' in differential mode,

  4657.   *         the channel 'i+1' is not usable separately.

  4658.   *         Therefore, to ensure a channel is configured in single-ended mode,

  4659.   *         the configuration of channel itself and the channel 'i-1' must be

  4660.   *         read back (to ensure that the selected channel channel has not been

  4661.   *         configured in differential mode by the previous channel).

  4662.   * @note   Refer to Reference Manual to ensure the selected channel is

  4663.   *         available in differential mode.

  4664.   *         For example, internal channels (VrefInt, TempSensor, ...) are

  4665.   *         not available in differential mode.

  4666.   * @note   When configuring a channel 'i' in differential mode,

  4667.   *         the channel 'i+1' is not usable separately.

  4668.   * @note   On STM32H7, some channels are internally fixed to single-ended inputs

  4669.   *         configuration:

  4670.   *         - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19

  4671.   *         - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19

  4672.   *         - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19

  4673.   * @note   One or several values can be selected. In this case, the value

  4674.   *         returned is null if all channels are in single ended-mode.

  4675.   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

  4676.   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff

  4677.   * @param  ADCx ADC instance

  4678.   * @param  Channel This parameter can be a combination of the following values:

  4679.   *         @arg @ref LL_ADC_CHANNEL_1

  4680.   *         @arg @ref LL_ADC_CHANNEL_2

  4681.   *         @arg @ref LL_ADC_CHANNEL_3

  4682.   *         @arg @ref LL_ADC_CHANNEL_4

  4683.   *         @arg @ref LL_ADC_CHANNEL_5

  4684.   *         @arg @ref LL_ADC_CHANNEL_10

  4685.   *         @arg @ref LL_ADC_CHANNEL_11

  4686.   *         @arg @ref LL_ADC_CHANNEL_12

  4687.   *         @arg @ref LL_ADC_CHANNEL_13

  4688.   *         @arg @ref LL_ADC_CHANNEL_14

  4689.   *         @arg @ref LL_ADC_CHANNEL_15

  4690.   *         @arg @ref LL_ADC_CHANNEL_16

  4691.   *         @arg @ref LL_ADC_CHANNEL_17

  4692.   *         @arg @ref LL_ADC_CHANNEL_18

  4693.   *         @arg @ref LL_ADC_CHANNEL_19

  4694.   * @retval 0: channel in single-ended mode, else: channel in differential mode

  4695.   */

  4696. __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)

  4697. {

  4698.   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));

  4699. }

  4700. 

  4701. /**

  4702.   * @}

  4703.   */

  4704. 

  4705. /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog

  4706.   * @{

  4707.   */

  4708. 

  4709. /**

  4710.   * @brief  Set ADC analog watchdog monitored channels:

  4711.   *         a single channel, multiple channels or all channels,

  4712.   *         on ADC groups regular and-or injected.

  4713.   * @note   Once monitored channels are selected, analog watchdog

  4714.   *         is enabled.

  4715.   * @note   In case of need to define a single channel to monitor

  4716.   *         with analog watchdog from sequencer channel definition,

  4717.   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().

  4718.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  4719.   *         instance:

  4720.   *         - AWD standard (instance AWD1):

  4721.   *           - channels monitored: can monitor 1 channel or all channels.

  4722.   *           - groups monitored: ADC groups regular and-or injected.

  4723.   *           - resolution: resolution is not limited (corresponds to

  4724.   *             ADC resolution configured).

  4725.   *         - AWD flexible (instances AWD2, AWD3):

  4726.   *           - channels monitored: flexible on channels monitored, selection is

  4727.   *             channel wise, from from 1 to all channels.

  4728.   *             Specificity of this analog watchdog: Multiple channels can

  4729.   *             be selected. For example:

  4730.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  4731.   *           - groups monitored: not selection possible (monitoring on both

  4732.   *             groups regular and injected).

  4733.   *             Channels selected are monitored on groups regular and injected:

  4734.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  4735.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  4736.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  4737.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  4738.   *             the 2 LSB are ignored.

  4739.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4740.   *         ADC state:

  4741.   *         ADC must be disabled or enabled without conversion on going

  4742.   *         on either groups regular or injected.

  4743.   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n

  4744.   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n

  4745.   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n

  4746.   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n

  4747.   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n

  4748.   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels

  4749.   * @param  ADCx ADC instance

  4750.   * @param  AWDy This parameter can be one of the following values:

  4751.   *         @arg @ref LL_ADC_AWD1

  4752.   *         @arg @ref LL_ADC_AWD2

  4753.   *         @arg @ref LL_ADC_AWD3

  4754.   * @param  AWDChannelGroup This parameter can be one of the following values:

  4755.   *         @arg @ref LL_ADC_AWD_DISABLE

  4756.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  4757.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

  4758.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  4759.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  4760.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

  4761.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  4762.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  4763.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

  4764.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  4765.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  4766.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

  4767.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  4768.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  4769.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

  4770.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  4771.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  4772.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

  4773.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  4774.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  4775.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

  4776.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  4777.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  4778.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

  4779.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  4780.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  4781.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

  4782.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  4783.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  4784.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

  4785.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  4786.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  4787.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

  4788.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  4789.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  4790.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

  4791.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  4792.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  4793.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

  4794.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  4795.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  4796.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

  4797.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  4798.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  4799.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

  4800.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  4801.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  4802.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

  4803.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  4804.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  4805.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

  4806.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  4807.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  4808.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

  4809.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  4810.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  4811.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

  4812.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  4813.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  4814.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

  4815.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  4816.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

  4817.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

  4818.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

  4819.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)

  4820.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)

  4821.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)

  4822.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)

  4823.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)

  4824.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)

  4825.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)

  4826.   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)

  4827.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)

  4828.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)

  4829.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)

  4830.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)

  4831.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)

  4832.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)

  4833.   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)

  4834.   *

  4835.   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n

  4836.   *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

  4837.   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

  4838.   * @retval None

  4839.   */

  4840. __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)

  4841. {

  4842.   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */

  4843.   /* in register and register position depending on parameter "AWDy".         */

  4844.   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */

  4845.   /* containing other bits reserved for other purpose.                        */

  4846.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)

  4847.                                                       + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));

  4848. 

  4849.   MODIFY_REG(*preg,

  4850.              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),

  4851.              AWDChannelGroup & AWDy);

  4852. }

  4853. 

  4854. /**

  4855.   * @brief  Get ADC analog watchdog monitored channel.

  4856.   * @note   Usage of the returned channel number:

  4857.   *         - To reinject this channel into another function LL_ADC_xxx:

  4858.   *           the returned channel number is only partly formatted on definition

  4859.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  4860.   *           with parts of literals LL_ADC_CHANNEL_x or using

  4861.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4862.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  4863.   *           as parameter for another function.

  4864.   *         - To get the channel number in decimal format:

  4865.   *           process the returned value with the helper macro

  4866.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4867.   *           Applicable only when the analog watchdog is set to monitor

  4868.   *           one channel.

  4869.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  4870.   *         instance:

  4871.   *         - AWD standard (instance AWD1):

  4872.   *           - channels monitored: can monitor 1 channel or all channels.

  4873.   *           - groups monitored: ADC groups regular and-or injected.

  4874.   *           - resolution: resolution is not limited (corresponds to

  4875.   *             ADC resolution configured).

  4876.   *         - AWD flexible (instances AWD2, AWD3):

  4877.   *           - channels monitored: flexible on channels monitored, selection is

  4878.   *             channel wise, from from 1 to all channels.

  4879.   *             Specificity of this analog watchdog: Multiple channels can

  4880.   *             be selected. For example:

  4881.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  4882.   *           - groups monitored: not selection possible (monitoring on both

  4883.   *             groups regular and injected).

  4884.   *             Channels selected are monitored on groups regular and injected:

  4885.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  4886.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  4887.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  4888.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  4889.   *             the 2 LSB are ignored.

  4890.   * @note   On this STM32 serie, setting of this feature is conditioned to

  4891.   *         ADC state:

  4892.   *         ADC must be disabled or enabled without conversion on going

  4893.   *         on either groups regular or injected.

  4894.   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n

  4895.   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n

  4896.   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n

  4897.   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n

  4898.   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n

  4899.   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels

  4900.   * @param  ADCx ADC instance

  4901.   * @param  AWDy This parameter can be one of the following values:

  4902.   *         @arg @ref LL_ADC_AWD1

  4903.   *         @arg @ref LL_ADC_AWD2 (1)

  4904.   *         @arg @ref LL_ADC_AWD3 (1)

  4905.   *

  4906.   *         (1) On this AWD number, monitored channel can be retrieved

  4907.   *             if only 1 channel is programmed (or none or all channels).

  4908.   *             This function cannot retrieve monitored channel if

  4909.   *             multiple channels are programmed simultaneously

  4910.   *             by bitfield.

  4911.   * @retval Returned value can be one of the following values:

  4912.   *         @arg @ref LL_ADC_AWD_DISABLE

  4913.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

  4914.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

  4915.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  4916.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

  4917.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

  4918.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  4919.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

  4920.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

  4921.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  4922.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

  4923.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

  4924.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  4925.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

  4926.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

  4927.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  4928.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

  4929.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

  4930.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  4931.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

  4932.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

  4933.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  4934.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

  4935.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

  4936.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  4937.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

  4938.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

  4939.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  4940.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

  4941.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

  4942.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  4943.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

  4944.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

  4945.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  4946.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

  4947.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

  4948.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  4949.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

  4950.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

  4951.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  4952.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

  4953.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

  4954.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  4955.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

  4956.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

  4957.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  4958.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

  4959.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

  4960.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  4961.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

  4962.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

  4963.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  4964.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

  4965.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

  4966.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  4967.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

  4968.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

  4969.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  4970.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

  4971.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

  4972.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  4973.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

  4974.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

  4975.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

  4976.   *

  4977.   *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.

  4978.   */

  4979. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)

  4980. {

  4981.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)

  4982.                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));

  4983. 

  4984.   register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);

  4985. 

  4986.   /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */

  4987.   /* (parameter value LL_ADC_AWD_DISABLE).                                    */

  4988.   /* Else, the selected AWD is enabled and is monitoring a group of channels  */

  4989.   /* or a single channel.                                                     */

  4990.   if (AnalogWDMonitChannels != 0UL)

  4991.   {

  4992.     if (AWDy == LL_ADC_AWD1)

  4993.     {

  4994.       if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)

  4995.       {

  4996.         /* AWD monitoring a group of channels */

  4997.         AnalogWDMonitChannels = ((AnalogWDMonitChannels

  4998.                                   | (ADC_AWD_CR23_CHANNEL_MASK)

  4999.                                  )

  5000.                                  & (~(ADC_CFGR_AWD1CH))

  5001.                                 );

  5002.       }

  5003.       else

  5004.       {

  5005.         /* AWD monitoring a single channel */

  5006.         AnalogWDMonitChannels = (AnalogWDMonitChannels

  5007.                                  | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))

  5008.                                 );

  5009.       }

  5010.     }

  5011.     else

  5012.     {

  5013.       if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)

  5014.       {

  5015.         /* AWD monitoring a group of channels */

  5016.         AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK

  5017.                                  | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))

  5018.                                 );

  5019.       }

  5020.       else

  5021.       {

  5022.         /* AWD monitoring a single channel */

  5023.         /* AWD monitoring a group of channels */

  5024.         AnalogWDMonitChannels = (AnalogWDMonitChannels

  5025.                                  | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

  5026.                                  | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)

  5027.                                 );

  5028.       }

  5029.     }

  5030.   }

  5031. 

  5032.   return AnalogWDMonitChannels;

  5033. }

  5034. 

  5035. /**

  5036.   * @brief  Set ADC analog watchdog threshold value of threshold

  5037.   *         high or low.

  5038.   * @note   In case of ADC resolution different of 12 bits,

  5039.   *         analog watchdog thresholds data require a specific shift.

  5040.   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().

  5041.   * @note   On this STM32 serie, there are 2 kinds of analog watchdog

  5042.   *         instance:

  5043.   *         - AWD standard (instance AWD1):

  5044.   *           - channels monitored: can monitor 1 channel or all channels.

  5045.   *           - groups monitored: ADC groups regular and-or injected.

  5046.   *           - resolution: resolution is not limited (corresponds to

  5047.   *             ADC resolution configured).

  5048.   *         - AWD flexible (instances AWD2, AWD3):

  5049.   *           - channels monitored: flexible on channels monitored, selection is

  5050.   *             channel wise, from from 1 to all channels.

  5051.   *             Specificity of this analog watchdog: Multiple channels can

  5052.   *             be selected. For example:

  5053.   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

  5054.   *           - groups monitored: not selection possible (monitoring on both

  5055.   *             groups regular and injected).

  5056.   *             Channels selected are monitored on groups regular and injected:

  5057.   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

  5058.   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

  5059.   *           - resolution: resolution is limited to 8 bits: if ADC resolution is

  5060.   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

  5061.   *             the 2 LSB are ignored.

  5062.   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are

  5063.   *         impacted: the comparison of analog watchdog thresholds is done

  5064.   *         on oversampling intermediate computation (after ratio, before shift

  5065.   *         application): intermediate register bitfield [32:7]

  5066.   *         (26 most significant bits).

  5067.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5068.   *         ADC state:

  5069.   *         ADC must be disabled or enabled without conversion on going

  5070.   *         on either ADC groups regular or injected.

  5071.   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n

  5072.   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n

  5073.   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n

  5074.   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n

  5075.   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n

  5076.   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds

  5077.   * @param  ADCx ADC instance

  5078.   * @param  AWDy This parameter can be one of the following values:

  5079.   *         @arg @ref LL_ADC_AWD1

  5080.   *         @arg @ref LL_ADC_AWD2

  5081.   *         @arg @ref LL_ADC_AWD3

  5082.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  5083.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  5084.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  5085.   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF

  5086.   * @retval None

  5087.   */

  5088. __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,

  5089.                                                   uint32_t AWDThresholdValue)

  5090. {

  5091.   /* Set bits with content of parameter "AWDThresholdValue" with bits         */

  5092.   /* position in register and register position depending on parameters       */

  5093.   /* "AWDThresholdsHighLow" and "AWDy".                                       */

  5094.   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */

  5095.   /* containing other bits reserved for other purpose.                        */

  5096.   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)

  5097.                                                              + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)

  5098.                                                              + (AWDThresholdsHighLow));

  5099. 

  5100.   MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);

  5101. }

  5102. 

  5103. /**

  5104.   * @brief  Get ADC analog watchdog threshold value of threshold high,

  5105.   *         threshold low or raw data with ADC thresholds high and low

  5106.   *         concatenated.

  5107.   * @note   In case of ADC resolution different of 12 bits,

  5108.   *         analog watchdog thresholds data require a specific shift.

  5109.   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().

  5110.   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n

  5111.   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n

  5112.   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n

  5113.   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n

  5114.   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n

  5115.   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds

  5116.   * @param  ADCx ADC instance

  5117.   * @param  AWDy This parameter can be one of the following values:

  5118.   *         @arg @ref LL_ADC_AWD1

  5119.   *         @arg @ref LL_ADC_AWD2

  5120.   *         @arg @ref LL_ADC_AWD3

  5121.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  5122.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  5123.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  5124.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF

  5125.   */

  5126. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)

  5127. {

  5128.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)

  5129.                                                                    + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)

  5130.                                                                    + (AWDThresholdsHighLow));

  5131. 

  5132.   return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));

  5133. }

  5134. 

  5135. /**

  5136.   * @}

  5137.   */

  5138. 

  5139. /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling

  5140.   * @{

  5141.   */

  5142. 

  5143. /**

  5144.   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected

  5145.   *         (availability of ADC group injected depends on STM32 families).

  5146.   * @note   If both groups regular and injected are selected,

  5147.   *         specify behavior of ADC group injected interrupting

  5148.   *         group regular: when ADC group injected is triggered,

  5149.   *         the oversampling on ADC group regular is either

  5150.   *         temporary stopped and continued, or resumed from start

  5151.   *         (oversampler buffer reset).

  5152.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5153.   *         ADC state:

  5154.   *         ADC must be disabled or enabled without conversion on going

  5155.   *         on either groups regular or injected.

  5156.   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n

  5157.   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n

  5158.   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope

  5159.   * @param  ADCx ADC instance

  5160.   * @param  OvsScope This parameter can be one of the following values:

  5161.   *         @arg @ref LL_ADC_OVS_DISABLE

  5162.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED

  5163.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED

  5164.   *         @arg @ref LL_ADC_OVS_GRP_INJECTED

  5165.   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED

  5166.   * @retval None

  5167.   */

  5168. __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)

  5169. {

  5170.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);

  5171. }

  5172. 

  5173. /**

  5174.   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected

  5175.   *         (availability of ADC group injected depends on STM32 families).

  5176.   * @note   If both groups regular and injected are selected,

  5177.   *         specify behavior of ADC group injected interrupting

  5178.   *         group regular: when ADC group injected is triggered,

  5179.   *         the oversampling on ADC group regular is either

  5180.   *         temporary stopped and continued, or resumed from start

  5181.   *         (oversampler buffer reset).

  5182.   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n

  5183.   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n

  5184.   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope

  5185.   * @param  ADCx ADC instance

  5186.   * @retval Returned value can be one of the following values:

  5187.   *         @arg @ref LL_ADC_OVS_DISABLE

  5188.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED

  5189.   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED

  5190.   *         @arg @ref LL_ADC_OVS_GRP_INJECTED

  5191.   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED

  5192.   */

  5193. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)

  5194. {

  5195.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));

  5196. }

  5197. 

  5198. /**

  5199.   * @brief  Set ADC oversampling discontinuous mode (triggered mode)

  5200.   *         on the selected ADC group.

  5201.   * @note   Number of oversampled conversions are done either in:

  5202.   *         - continuous mode (all conversions of oversampling ratio

  5203.   *           are done from 1 trigger)

  5204.   *         - discontinuous mode (each conversion of oversampling ratio

  5205.   *           needs a trigger)

  5206.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5207.   *         ADC state:

  5208.   *         ADC must be disabled or enabled without conversion on going

  5209.   *         on group regular.

  5210.   * @note   On this STM32 serie, oversampling discontinuous mode

  5211.   *         (triggered mode) can be used only when oversampling is

  5212.   *         set on group regular only and in resumed mode.

  5213.   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont

  5214.   * @param  ADCx ADC instance

  5215.   * @param  OverSamplingDiscont This parameter can be one of the following values:

  5216.   *         @arg @ref LL_ADC_OVS_REG_CONT

  5217.   *         @arg @ref LL_ADC_OVS_REG_DISCONT

  5218.   * @retval None

  5219.   */

  5220. __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)

  5221. {

  5222.   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);

  5223. }

  5224. 

  5225. /**

  5226.   * @brief  Get ADC oversampling discontinuous mode (triggered mode)

  5227.   *         on the selected ADC group.

  5228.   * @note   Number of oversampled conversions are done either in:

  5229.   *         - continuous mode (all conversions of oversampling ratio

  5230.   *           are done from 1 trigger)

  5231.   *         - discontinuous mode (each conversion of oversampling ratio

  5232.   *           needs a trigger)

  5233.   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont

  5234.   * @param  ADCx ADC instance

  5235.   * @retval Returned value can be one of the following values:

  5236.   *         @arg @ref LL_ADC_OVS_REG_CONT

  5237.   *         @arg @ref LL_ADC_OVS_REG_DISCONT

  5238.   */

  5239. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)

  5240. {

  5241.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));

  5242. }

  5243. 

  5244. /**

  5245.   * @brief  Set ADC oversampling

  5246.   *         (impacting both ADC groups regular and injected)

  5247.   * @note   This function set the 2 items of oversampling configuration:

  5248.   *         - ratio

  5249.   *         - shift

  5250.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5251.   *         ADC state:

  5252.   *         ADC must be disabled or enabled without conversion on going

  5253.   *         on either groups regular or injected.

  5254.   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n

  5255.   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift

  5256.   * @param  ADCx ADC instance

  5257.   * @param  Ratio This parameter can be in the range from 1 to 1024.

  5258.   * @param  Shift This parameter can be one of the following values:

  5259.   *         @arg @ref LL_ADC_OVS_SHIFT_NONE

  5260.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1

  5261.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2

  5262.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3

  5263.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4

  5264.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5

  5265.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6

  5266.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7

  5267.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8

  5268.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9

  5269.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10

  5270.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11

  5271.   * @retval None

  5272.   */

  5273. __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)

  5274. {

  5275.   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));

  5276. }

  5277. 

  5278. /**

  5279.   * @brief  Get ADC oversampling ratio

  5280.   *        (impacting both ADC groups regular and injected)

  5281.   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio

  5282.   * @param  ADCx ADC instance

  5283.   * @retval Ratio This parameter can be in the from 1 to 1024.

  5284.   */

  5285. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)

  5286. {

  5287.   return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR))+(1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);

  5288. }

  5289. 

  5290. /**

  5291.   * @brief  Get ADC oversampling shift

  5292.   *        (impacting both ADC groups regular and injected)

  5293.   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift

  5294.   * @param  ADCx ADC instance

  5295.   * @retval Shift This parameter can be one of the following values:

  5296.   *         @arg @ref LL_ADC_OVS_SHIFT_NONE

  5297.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1

  5298.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2

  5299.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3

  5300.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4

  5301.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5

  5302.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6

  5303.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7

  5304.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8

  5305.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9

  5306.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10

  5307.   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11

  5308.   */

  5309. __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)

  5310. {

  5311.   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));

  5312. }

  5313. 

  5314. /**

  5315.   * @}

  5316.   */

  5317. 

  5318. /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode

  5319.   * @{

  5320.   */

  5321. /**

  5322.   * @brief  Set ADC boost mode.

  5323.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5324.   *         ADC state:

  5325.   *         ADC boost must be configured, without calibration on going, without conversion

  5326.   *         on going on group regular.

  5327.   * @rmtoll CR  BOOST      LL_ADC_SetBoostMode

  5328.   * @param  ADCx ADC instance

  5329.   * @param  BoostMode This parameter can be one of the following values:

  5330.   *         @arg @ref LL_ADC_BOOST_MODE_6MHZ25

  5331.   *         @arg @ref LL_ADC_BOOST_MODE_12MHZ5

  5332.   *         @arg @ref LL_ADC_BOOST_MODE_20MHZ

  5333.   *         @arg @ref LL_ADC_BOOST_MODE_25MHZ

  5334.   *         @arg @ref LL_ADC_BOOST_MODE_50MHZ

  5335.   * @retval None

  5336.   */

  5337. __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)

  5338. {

  5339.   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */

  5340.   {

  5341.     MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));

  5342.   }

  5343.   else /* Cut 2.x */

  5344.   {

  5345.     MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));

  5346.   }

  5347. }

  5348. 

  5349. /**

  5350.   * @brief  Get ADC boost mode.

  5351.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5352.   *         ADC state:

  5353.   *         ADC boost must be configured, without calibration on going, without conversion

  5354.   *         on going on group regular.

  5355.   * @rmtoll CR  BOOST      LL_ADC_GetBoostMode

  5356.   * @param  ADCx ADC instance

  5357.   * @retval 0: Boost disabled 1: Boost enabled

  5358.   */

  5359. __STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)

  5360. {

  5361.   if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */

  5362.   {

  5363.     return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);

  5364.   }

  5365.   else /* Cut 2.x */

  5366.   {

  5367.     return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);

  5368.   }

  5369. }

  5370. 

  5371. /**

  5372.   * @brief  Set ADC multimode configuration to operate in independent mode

  5373.   *         or multimode (for devices with several ADC instances).

  5374.   * @note   If multimode configuration: the selected ADC instance is

  5375.   *         either master or slave depending on hardware.

  5376.   *         Refer to reference manual.

  5377.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5378.   *         ADC state:

  5379.   *         All ADC instances of the ADC common group must be disabled.

  5380.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  5381.   *         ADC instance or by using helper macro

  5382.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  5383.   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode

  5384.   * @param  ADCxy_COMMON ADC common instance

  5385.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5386.   * @param  Multimode This parameter can be one of the following values:

  5387.   *         @arg @ref LL_ADC_MULTI_INDEPENDENT

  5388.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT

  5389.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL

  5390.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT

  5391.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN

  5392.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM

  5393.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT

  5394.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

  5395.   * @retval None

  5396.   */

  5397. __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)

  5398. {

  5399.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);

  5400. }

  5401. 

  5402. /**

  5403.   * @brief  Get ADC multimode configuration to operate in independent mode

  5404.   *         or multimode (for devices with several ADC instances).

  5405.   * @note   If multimode configuration: the selected ADC instance is

  5406.   *         either master or slave depending on hardware.

  5407.   *         Refer to reference manual.

  5408.   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode

  5409.   * @param  ADCxy_COMMON ADC common instance

  5410.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5411.   * @retval Returned value can be one of the following values:

  5412.   *         @arg @ref LL_ADC_MULTI_INDEPENDENT

  5413.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT

  5414.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL

  5415.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT

  5416.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN

  5417.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM

  5418.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT

  5419.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

  5420.   */

  5421. __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)

  5422. {

  5423.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));

  5424. }

  5425. 

  5426. /**

  5427.   * @brief  Set ADC multimode conversion data transfer: no transfer

  5428.   *         or transfer by DMA.

  5429.   * @note   If ADC multimode transfer by DMA is not selected:

  5430.   *         each ADC uses its own DMA channel, with its individual

  5431.   *         DMA transfer settings.

  5432.   *         If ADC multimode transfer by DMA is selected:

  5433.   *         One DMA channel is used for both ADC (DMA of ADC master)

  5434.   *         Specifies the DMA requests mode:

  5435.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  5436.   *           when number of DMA data transfers (number of

  5437.   *           ADC conversions) is reached.

  5438.   *           This ADC mode is intended to be used with DMA mode non-circular.

  5439.   *         - Unlimited mode: DMA transfer requests are unlimited,

  5440.   *           whatever number of DMA data transfers (number of

  5441.   *           ADC conversions).

  5442.   *           This ADC mode is intended to be used with DMA mode circular.

  5443.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  5444.   *         mode non-circular:

  5445.   *         when DMA transfers size will be reached, DMA will stop transfers of

  5446.   *         ADC conversions data ADC will raise an overrun error

  5447.   *         (overrun flag and interruption if enabled).

  5448.   * @note   How to retrieve multimode conversion data:

  5449.   *         Whatever multimode transfer by DMA setting: using function

  5450.   *         @ref LL_ADC_REG_ReadMultiConversionData32().

  5451.   *         If ADC multimode transfer by DMA is selected: conversion data

  5452.   *         is a raw data with ADC master and slave concatenated.

  5453.   *         A macro is available to get the conversion data of

  5454.   *         ADC master or ADC slave: see helper macro

  5455.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  5456.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5457.   *         ADC state:

  5458.   *         All ADC instances of the ADC common group must be disabled

  5459.   *         or enabled without conversion on going on group regular.

  5460.   * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDMATransfer\n

  5461.   * @param  ADCxy_COMMON ADC common instance

  5462.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5463.   * @param  MultiDMATransfer This parameter can be one of the following values:

  5464.   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC

  5465.   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B

  5466.   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B

  5467.   * @retval None

  5468.   */

  5469. __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)

  5470. {

  5471.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);

  5472. }

  5473. 

  5474. /**

  5475.   * @brief  Get ADC multimode conversion data transfer: no transfer

  5476.   *         or transfer by DMA.

  5477.   * @note   If ADC multimode transfer by DMA is not selected:

  5478.   *         each ADC uses its own DMA channel, with its individual

  5479.   *         DMA transfer settings.

  5480.   *         If ADC multimode transfer by DMA is selected:

  5481.   *         One DMA channel is used for both ADC (DMA of ADC master)

  5482.   *         Specifies the DMA requests mode:

  5483.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  5484.   *           when number of DMA data transfers (number of

  5485.   *           ADC conversions) is reached.

  5486.   *           This ADC mode is intended to be used with DMA mode non-circular.

  5487.   *         - Unlimited mode: DMA transfer requests are unlimited,

  5488.   *           whatever number of DMA data transfers (number of

  5489.   *           ADC conversions).

  5490.   *           This ADC mode is intended to be used with DMA mode circular.

  5491.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  5492.   *         mode non-circular:

  5493.   *         when DMA transfers size will be reached, DMA will stop transfers of

  5494.   *         ADC conversions data ADC will raise an overrun error

  5495.   *         (overrun flag and interruption if enabled).

  5496.   * @note   How to retrieve multimode conversion data:

  5497.   *         Whatever multimode transfer by DMA setting: using function

  5498.   *         @ref LL_ADC_REG_ReadMultiConversionData32().

  5499.   *         If ADC multimode transfer by DMA is selected: conversion data

  5500.   *         is a raw data with ADC master and slave concatenated.

  5501.   *         A macro is available to get the conversion data of

  5502.   *         ADC master or ADC slave: see helper macro

  5503.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  5504.   * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDMATransfer\n

  5505.   * @param  ADCxy_COMMON ADC common instance

  5506.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5507.   * @retval Returned value can be one of the following values:

  5508.   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC

  5509.   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B

  5510.   *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B

  5511.   */

  5512. __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)

  5513. {

  5514.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));

  5515. }

  5516. 

  5517. /**

  5518.   * @brief  Set ADC multimode delay between 2 sampling phases.

  5519.   * @note   The sampling delay range depends on ADC resolution:

  5520.   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.

  5521.   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.

  5522.   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.

  5523.   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.

  5524.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5525.   *         ADC state:

  5526.   *         All ADC instances of the ADC common group must be disabled.

  5527.   *         This check can be done with function @ref LL_ADC_IsEnabled() for each

  5528.   *         ADC instance or by using helper macro helper macro

  5529.   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

  5530.   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay

  5531.   * @param  ADCxy_COMMON ADC common instance

  5532.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5533.   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:

  5534.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5

  5535.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5

  5536.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5

  5537.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)

  5538.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS

  5539.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)

  5540.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS

  5541.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (3)

  5542.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)

  5543.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS

  5544.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)

  5545.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (6)

  5546.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (7)

  5547.   *

  5548.   *         (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.

  5549.   *         (2) Parameter available only if ADC resolution is 16, 14 or 12  bits.

  5550.   *         (3) Parameter available only if ADC resolution is 10 or 8 bits.

  5551.   *         (4) Parameter available only if ADC resolution is 16 or 14 bits.

  5552.   *         (5) Parameter available only if ADC resolution is 16 bits.

  5553.   *         (6) Parameter available only if ADC resolution is 12 bits.

  5554.   *         (7) Parameter available only if ADC resolution is 16 or 14 bits.

  5555.   * @retval None

  5556.   */

  5557. __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)

  5558. {

  5559.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);

  5560. }

  5561. 

  5562. /**

  5563.   * @brief  Get ADC multimode delay between 2 sampling phases.

  5564.   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay

  5565.   * @param  ADCxy_COMMON ADC common instance

  5566.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  5567.   * @retval Returned value can be one of the following values:

  5568.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5

  5569.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5

  5570.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5

  5571.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)

  5572.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS

  5573.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)

  5574.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS

  5575.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (3)

  5576.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)

  5577.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS

  5578.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)

  5579.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (6)

  5580.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (7)

  5581.   *

  5582.   *         (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.

  5583.   *         (2) Parameter available only if ADC resolution is 16, 14 or 12  bits.

  5584.   *         (3) Parameter available only if ADC resolution is 10 or 8 bits.

  5585.   *         (4) Parameter available only if ADC resolution is 16 or 14 bits.

  5586.   *         (5) Parameter available only if ADC resolution is 16 bits.

  5587.   *         (6) Parameter available only if ADC resolution is 12 bits.

  5588.   *         (7) Parameter available only if ADC resolution is 16 or 14 bits.

  5589.   */

  5590. __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)

  5591. {

  5592.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));

  5593. }

  5594. 

  5595. /**

  5596.   * @}

  5597.   */

  5598. /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance

  5599.   * @{

  5600.   */

  5601. 

  5602. /**

  5603.   * @brief  Put ADC instance in deep power down state.

  5604.   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down

  5605.   *         state, the internal analog calibration is lost. After exiting from

  5606.   *         deep power down, calibration must be relaunched or calibration factor

  5607.   *         (preliminarily saved) must be set back into calibration register.

  5608.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5609.   *         ADC state:

  5610.   *         ADC must be ADC disabled.

  5611.   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown

  5612.   * @param  ADCx ADC instance

  5613.   * @retval None

  5614.   */

  5615. __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)

  5616. {

  5617.   /* Note: Write register with some additional bits forced to state reset     */

  5618.   /*       instead of modifying only the selected bit for this function,      */

  5619.   /*       to not interfere with bits with HW property "rs".                  */

  5620.   MODIFY_REG(ADCx->CR,

  5621.              ADC_CR_BITS_PROPERTY_RS,

  5622.              ADC_CR_DEEPPWD);

  5623. }

  5624. 

  5625. /**

  5626.   * @brief  Disable ADC deep power down mode.

  5627.   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down

  5628.   *         state, the internal analog calibration is lost. After exiting from

  5629.   *         deep power down, calibration must be relaunched or calibration factor

  5630.   *         (preliminarily saved) must be set back into calibration register.

  5631.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5632.   *         ADC state:

  5633.   *         ADC must be ADC disabled.

  5634.   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown

  5635.   * @param  ADCx ADC instance

  5636.   * @retval None

  5637.   */

  5638. __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)

  5639. {

  5640.   /* Note: Write register with some additional bits forced to state reset     */

  5641.   /*       instead of modifying only the selected bit for this function,      */

  5642.   /*       to not interfere with bits with HW property "rs".                  */

  5643.   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));

  5644. }

  5645. 

  5646. /**

  5647.   * @brief  Get the selected ADC instance deep power down state.

  5648.   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled

  5649.   * @param  ADCx ADC instance

  5650.   * @retval 0: deep power down is disabled, 1: deep power down is enabled.

  5651.   */

  5652. __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)

  5653. {

  5654.   return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);

  5655. }

  5656. 

  5657. /**

  5658.   * @brief  Enable ADC instance internal voltage regulator.

  5659.   * @note   On this STM32 serie, after ADC internal voltage regulator enable,

  5660.   *         a delay for ADC internal voltage regulator stabilization

  5661.   *         is required before performing a ADC calibration or ADC enable.

  5662.   *         Refer to device datasheet, parameter tADCVREG_STUP.

  5663.   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.

  5664.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5665.   *         ADC state:

  5666.   *         ADC must be ADC disabled.

  5667.   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator

  5668.   * @param  ADCx ADC instance

  5669.   * @retval None

  5670.   */

  5671. __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)

  5672. {

  5673.   /* Note: Write register with some additional bits forced to state reset     */

  5674.   /*       instead of modifying only the selected bit for this function,      */

  5675.   /*       to not interfere with bits with HW property "rs".                  */

  5676.   MODIFY_REG(ADCx->CR,

  5677.              ADC_CR_BITS_PROPERTY_RS,

  5678.              ADC_CR_ADVREGEN);

  5679. }

  5680. 

  5681. /**

  5682.   * @brief  Disable ADC internal voltage regulator.

  5683.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5684.   *         ADC state:

  5685.   *         ADC must be ADC disabled.

  5686.   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator

  5687.   * @param  ADCx ADC instance

  5688.   * @retval None

  5689.   */

  5690. __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)

  5691. {

  5692.   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));

  5693. }

  5694. 

  5695. /**

  5696.   * @brief  Get the selected ADC instance internal voltage regulator state.

  5697.   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled

  5698.   * @param  ADCx ADC instance

  5699.   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.

  5700.   */

  5701. __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)

  5702. {

  5703.   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);

  5704. }

  5705. 

  5706. /**

  5707.   * @brief  Enable the selected ADC instance.

  5708.   * @note   On this STM32 serie, after ADC enable, a delay for

  5709.   *         ADC internal analog stabilization is required before performing a

  5710.   *         ADC conversion start.

  5711.   *         Refer to device datasheet, parameter tSTAB.

  5712.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  5713.   *         is enabled and when conversion clock is active.

  5714.   *         (not only core clock: this ADC has a dual clock domain)

  5715.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5716.   *         ADC state:

  5717.   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.

  5718.   * @rmtoll CR       ADEN           LL_ADC_Enable

  5719.   * @param  ADCx ADC instance

  5720.   * @retval None

  5721.   */

  5722. __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)

  5723. {

  5724.   /* Note: Write register with some additional bits forced to state reset     */

  5725.   /*       instead of modifying only the selected bit for this function,      */

  5726.   /*       to not interfere with bits with HW property "rs".                  */

  5727.   MODIFY_REG(ADCx->CR,

  5728.              ADC_CR_BITS_PROPERTY_RS,

  5729.              ADC_CR_ADEN);

  5730. }

  5731. 

  5732. /**

  5733.   * @brief  Disable the selected ADC instance.

  5734.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5735.   *         ADC state:

  5736.   *         ADC must be not disabled. Must be enabled without conversion on going

  5737.   *         on either groups regular or injected.

  5738.   * @rmtoll CR       ADDIS          LL_ADC_Disable

  5739.   * @param  ADCx ADC instance

  5740.   * @retval None

  5741.   */

  5742. __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)

  5743. {

  5744.   /* Note: Write register with some additional bits forced to state reset     */

  5745.   /*       instead of modifying only the selected bit for this function,      */

  5746.   /*       to not interfere with bits with HW property "rs".                  */

  5747.   MODIFY_REG(ADCx->CR,

  5748.              ADC_CR_BITS_PROPERTY_RS,

  5749.              ADC_CR_ADDIS);

  5750. }

  5751. 

  5752. /**

  5753.   * @brief  Get the selected ADC instance enable state.

  5754.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  5755.   *         is enabled and when conversion clock is active.

  5756.   *         (not only core clock: this ADC has a dual clock domain)

  5757.   * @rmtoll CR       ADEN           LL_ADC_IsEnabled

  5758.   * @param  ADCx ADC instance

  5759.   * @retval 0: ADC is disabled, 1: ADC is enabled.

  5760.   */

  5761. __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)

  5762. {

  5763.   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);

  5764. }

  5765. 

  5766. /**

  5767.   * @brief  Get the selected ADC instance disable state.

  5768.   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing

  5769.   * @param  ADCx ADC instance

  5770.   * @retval 0: no ADC disable command on going.

  5771.   */

  5772. __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)

  5773. {

  5774.   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);

  5775. }

  5776. 

  5777. /**

  5778.   * @brief  Start ADC calibration in the mode single-ended

  5779.   *         or differential (for devices with differential mode available).

  5780.   * @note   On this STM32 serie, a minimum number of ADC clock cycles

  5781.   *         are required between ADC end of calibration and ADC enable.

  5782.   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.

  5783.   * @note   Calibration duration:

  5784.   *         - Calibration of offset: 520 ADC clock cycles

  5785.   *         - Calibration of linearity: 131072 ADC clock cycles

  5786.   * @note   For devices with differential mode available:

  5787.   *         Calibration of offset is specific to each of

  5788.   *         single-ended and differential modes

  5789.   *         (calibration run must be performed for each of these

  5790.   *         differential modes, if used afterwards and if the application

  5791.   *         requires their calibration).

  5792.   *         Calibration of linearity is common to both

  5793.   *         single-ended and differential modes

  5794.   *         (calibration run can be performed only once).

  5795.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5796.   *         ADC state:

  5797.   *         ADC must be ADC disabled.

  5798.   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n

  5799.   *         CR       ADCALDIF       LL_ADC_StartCalibration\n

  5800.   *         CR       ADCALLIN       LL_ADC_StartCalibration

  5801.   * @param  ADCx ADC instance

  5802.   * @param  CalibrationMode This parameter can be one of the following values:

  5803.   *         @arg @ref LL_ADC_CALIB_OFFSET

  5804.   *         @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY

  5805.   * @param  SingleDiff This parameter can be one of the following values:

  5806.   *         @arg @ref LL_ADC_SINGLE_ENDED

  5807.   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

  5808.   * @retval None

  5809.   */

  5810. __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)

  5811. {

  5812.   /* Note: Write register with some additional bits forced to state reset     */

  5813.   /*       instead of modifying only the selected bit for this function,      */

  5814.   /*       to not interfere with bits with HW property "rs".                  */

  5815.   MODIFY_REG(ADCx->CR,

  5816.              ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,

  5817.              ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));

  5818. }

  5819. 

  5820. /**

  5821.   * @brief  Get ADC calibration state.

  5822.   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing

  5823.   * @param  ADCx ADC instance

  5824.   * @retval 0: calibration complete, 1: calibration in progress.

  5825.   */

  5826. __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)

  5827. {

  5828.   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);

  5829. }

  5830. 

  5831. /**

  5832.   * @}

  5833.   */

  5834. 

  5835. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular

  5836.   * @{

  5837.   */

  5838. 

  5839. /**

  5840.   * @brief  Start ADC group regular conversion.

  5841.   * @note   On this STM32 serie, this function is relevant for both

  5842.   *         internal trigger (SW start) and external trigger:

  5843.   *         - If ADC trigger has been set to software start, ADC conversion

  5844.   *           starts immediately.

  5845.   *         - If ADC trigger has been set to external trigger, ADC conversion

  5846.   *           will start at next trigger event (on the selected trigger edge)

  5847.   *           following the ADC start conversion command.

  5848.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5849.   *         ADC state:

  5850.   *         ADC must be enabled without conversion on going on group regular,

  5851.   *         without conversion stop command on going on group regular,

  5852.   *         without ADC disable command on going.

  5853.   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion

  5854.   * @param  ADCx ADC instance

  5855.   * @retval None

  5856.   */

  5857. __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)

  5858. {

  5859.   /* Note: Write register with some additional bits forced to state reset     */

  5860.   /*       instead of modifying only the selected bit for this function,      */

  5861.   /*       to not interfere with bits with HW property "rs".                  */

  5862.   MODIFY_REG(ADCx->CR,

  5863.              ADC_CR_BITS_PROPERTY_RS,

  5864.              ADC_CR_ADSTART);

  5865. }

  5866. 

  5867. /**

  5868.   * @brief  Stop ADC group regular conversion.

  5869.   * @note   On this STM32 serie, setting of this feature is conditioned to

  5870.   *         ADC state:

  5871.   *         ADC must be enabled with conversion on going on group regular,

  5872.   *         without ADC disable command on going.

  5873.   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion

  5874.   * @param  ADCx ADC instance

  5875.   * @retval None

  5876.   */

  5877. __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)

  5878. {

  5879.   /* Note: Write register with some additional bits forced to state reset     */

  5880.   /*       instead of modifying only the selected bit for this function,      */

  5881.   /*       to not interfere with bits with HW property "rs".                  */

  5882.   MODIFY_REG(ADCx->CR,

  5883.              ADC_CR_BITS_PROPERTY_RS,

  5884.              ADC_CR_ADSTP);

  5885. }

  5886. 

  5887. /**

  5888.   * @brief  Get ADC group regular conversion state.

  5889.   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing

  5890.   * @param  ADCx ADC instance

  5891.   * @retval 0: no conversion is on going on ADC group regular.

  5892.   */

  5893. __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)

  5894. {

  5895.   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);

  5896. }

  5897. 

  5898. /**

  5899.   * @brief  Get ADC group regular command of conversion stop state

  5900.   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing

  5901.   * @param  ADCx ADC instance

  5902.   * @retval 0: no command of conversion stop is on going on ADC group regular.

  5903.   */

  5904. __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)

  5905. {

  5906.   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);

  5907. }

  5908. 

  5909. /**

  5910.   * @brief  Get ADC group regular conversion data, range fit for

  5911.   *         all ADC configurations: all ADC resolutions and

  5912.   *         all oversampling increased data width (for devices

  5913.   *         with feature oversampling).

  5914.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32

  5915.   * @param  ADCx ADC instance

  5916.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  5917.   */

  5918. __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)

  5919. {

  5920.   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5921. }

  5922. 

  5923. /**

  5924.   * @brief  Get ADC group regular conversion data, range fit for

  5925.   *         ADC resolution 16 bits.

  5926.   * @note   For devices with feature oversampling: Oversampling

  5927.   *         can increase data width, function for extended range

  5928.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5929.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData16

  5930.   * @param  ADCx ADC instance

  5931.   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF

  5932.   */

  5933. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)

  5934. {

  5935.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5936. }

  5937. 

  5938. /**

  5939.   * @brief  Get ADC group regular conversion data, range fit for

  5940.   *         ADC resolution 14 bits.

  5941.   * @note   For devices with feature oversampling: Oversampling

  5942.   *         can increase data width, function for extended range

  5943.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5944.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData14

  5945.   * @param  ADCx ADC instance

  5946.   * @retval Value between Min_Data=0x00 and Max_Data=0x3FF

  5947.   */

  5948. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)

  5949. {

  5950.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5951. }

  5952. 

  5953. /**

  5954.   * @brief  Get ADC group regular conversion data, range fit for

  5955.   *         ADC resolution 12 bits.

  5956.   * @note   For devices with feature oversampling: Oversampling

  5957.   *         can increase data width, function for extended range

  5958.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5959.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12

  5960.   * @param  ADCx ADC instance

  5961.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  5962.   */

  5963. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)

  5964. {

  5965.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5966. }

  5967. 

  5968. /**

  5969.   * @brief  Get ADC group regular conversion data, range fit for

  5970.   *         ADC resolution 10 bits.

  5971.   * @note   For devices with feature oversampling: Oversampling

  5972.   *         can increase data width, function for extended range

  5973.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5974.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10

  5975.   * @param  ADCx ADC instance

  5976.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  5977.   */

  5978. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)

  5979. {

  5980.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5981. }

  5982. 

  5983. /**

  5984.   * @brief  Get ADC group regular conversion data, range fit for

  5985.   *         ADC resolution 8 bits.

  5986.   * @note   For devices with feature oversampling: Oversampling

  5987.   *         can increase data width, function for extended range

  5988.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  5989.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8

  5990.   * @param  ADCx ADC instance

  5991.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  5992.   */

  5993. __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)

  5994. {

  5995.   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

  5996. }

  5997. /**

  5998.   * @brief  Get ADC multimode conversion data of ADC master, ADC slave

  5999.   *         or raw data with ADC master and slave concatenated.

  6000.   * @note   If raw data with ADC master and slave concatenated is retrieved,

  6001.   *         a macro is available to get the conversion data of

  6002.   *         ADC master or ADC slave: see helper macro

  6003.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  6004.   *         (however this macro is mainly intended for multimode

  6005.   *         transfer by DMA, because this function can do the same

  6006.   *         by getting multimode conversion data of ADC master or ADC slave

  6007.   *         separately).

  6008.   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n

  6009.   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32

  6010.   * @param  ADCxy_COMMON ADC common instance

  6011.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6012.   * @param  ConversionData This parameter can be one of the following values:

  6013.   *         @arg @ref LL_ADC_MULTI_MASTER

  6014.   *         @arg @ref LL_ADC_MULTI_SLAVE

  6015.   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE

  6016.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  6017.   */

  6018. __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)

  6019. {

  6020.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,

  6021.                              ConversionData)

  6022.                     >> (POSITION_VAL(ConversionData) & 0x1FUL)

  6023.                    );

  6024. }

  6025. 

  6026. /**

  6027.   * @}

  6028.   */

  6029. 

  6030. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected

  6031.   * @{

  6032.   */

  6033. 

  6034. /**

  6035.   * @brief  Start ADC group injected conversion.

  6036.   * @note   On this STM32 serie, this function is relevant for both

  6037.   *         internal trigger (SW start) and external trigger:

  6038.   *         - If ADC trigger has been set to software start, ADC conversion

  6039.   *           starts immediately.

  6040.   *         - If ADC trigger has been set to external trigger, ADC conversion

  6041.   *           will start at next trigger event (on the selected trigger edge)

  6042.   *           following the ADC start conversion command.

  6043.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6044.   *         ADC state:

  6045.   *         ADC must be enabled without conversion on going on group injected,

  6046.   *         without conversion stop command on going on group injected,

  6047.   *         without ADC disable command on going.

  6048.   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion

  6049.   * @param  ADCx ADC instance

  6050.   * @retval None

  6051.   */

  6052. __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)

  6053. {

  6054.   /* Note: Write register with some additional bits forced to state reset     */

  6055.   /*       instead of modifying only the selected bit for this function,      */

  6056.   /*       to not interfere with bits with HW property "rs".                  */

  6057.   MODIFY_REG(ADCx->CR,

  6058.              ADC_CR_BITS_PROPERTY_RS,

  6059.              ADC_CR_JADSTART);

  6060. }

  6061. 

  6062. /**

  6063.   * @brief  Stop ADC group injected conversion.

  6064.   * @note   On this STM32 serie, setting of this feature is conditioned to

  6065.   *         ADC state:

  6066.   *         ADC must be enabled with conversion on going on group injected,

  6067.   *         without ADC disable command on going.

  6068.   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion

  6069.   * @param  ADCx ADC instance

  6070.   * @retval None

  6071.   */

  6072. __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)

  6073. {

  6074.   /* Note: Write register with some additional bits forced to state reset     */

  6075.   /*       instead of modifying only the selected bit for this function,      */

  6076.   /*       to not interfere with bits with HW property "rs".                  */

  6077.   MODIFY_REG(ADCx->CR,

  6078.              ADC_CR_BITS_PROPERTY_RS,

  6079.              ADC_CR_JADSTP);

  6080. }

  6081. 

  6082. /**

  6083.   * @brief  Get ADC group injected conversion state.

  6084.   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing

  6085.   * @param  ADCx ADC instance

  6086.   * @retval 0: no conversion is on going on ADC group injected.

  6087.   */

  6088. __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)

  6089. {

  6090.   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);

  6091. }

  6092. 

  6093. /**

  6094.   * @brief  Get ADC group injected command of conversion stop state

  6095.   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing

  6096.   * @param  ADCx ADC instance

  6097.   * @retval 0: no command of conversion stop is on going on ADC group injected.

  6098.   */

  6099. __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)

  6100. {

  6101.   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);

  6102. }

  6103. 

  6104. /**

  6105.   * @brief  Get ADC group injected conversion data, range fit for

  6106.   *         all ADC configurations: all ADC resolutions and

  6107.   *         all oversampling increased data width (for devices

  6108.   *         with feature oversampling).

  6109.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n

  6110.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n

  6111.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n

  6112.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32

  6113.   * @param  ADCx ADC instance

  6114.   * @param  Rank This parameter can be one of the following values:

  6115.   *         @arg @ref LL_ADC_INJ_RANK_1

  6116.   *         @arg @ref LL_ADC_INJ_RANK_2

  6117.   *         @arg @ref LL_ADC_INJ_RANK_3

  6118.   *         @arg @ref LL_ADC_INJ_RANK_4

  6119.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  6120.   */

  6121. __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)

  6122. {

  6123.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6124. 

  6125.   return (uint32_t)(READ_BIT(*preg,

  6126.                              ADC_JDR1_JDATA)

  6127.                    );

  6128. }

  6129. 

  6130. /**

  6131.   * @brief  Get ADC group injected conversion data, range fit for

  6132.   *         ADC resolution 16 bits.

  6133.   * @note   For devices with feature oversampling: Oversampling

  6134.   *         can increase data width, function for extended range

  6135.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6136.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData16\n

  6137.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData16\n

  6138.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData16\n

  6139.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData16

  6140.   * @param  ADCx ADC instance

  6141.   * @param  Rank This parameter can be one of the following values:

  6142.   *         @arg @ref LL_ADC_INJ_RANK_1

  6143.   *         @arg @ref LL_ADC_INJ_RANK_2

  6144.   *         @arg @ref LL_ADC_INJ_RANK_3

  6145.   *         @arg @ref LL_ADC_INJ_RANK_4

  6146.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF

  6147.   */

  6148. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)

  6149. {

  6150.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6151. 

  6152.   return (uint16_t)(READ_BIT(*preg,

  6153.                              ADC_JDR1_JDATA)

  6154.                    );

  6155. }

  6156. 

  6157. /**

  6158.   * @brief  Get ADC group injected conversion data, range fit for

  6159.   *         ADC resolution 14 bits.

  6160.   * @note   For devices with feature oversampling: Oversampling

  6161.   *         can increase data width, function for extended range

  6162.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6163.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData14\n

  6164.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData14\n

  6165.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData14\n

  6166.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData14

  6167.   * @param  ADCx ADC instance

  6168.   * @param  Rank This parameter can be one of the following values:

  6169.   *         @arg @ref LL_ADC_INJ_RANK_1

  6170.   *         @arg @ref LL_ADC_INJ_RANK_2

  6171.   *         @arg @ref LL_ADC_INJ_RANK_3

  6172.   *         @arg @ref LL_ADC_INJ_RANK_4

  6173.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF

  6174.   */

  6175. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)

  6176. {

  6177.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6178. 

  6179.   return (uint16_t)(READ_BIT(*preg,

  6180.                              ADC_JDR1_JDATA)

  6181.                    );

  6182. }

  6183. 

  6184. /**

  6185.   * @brief  Get ADC group injected conversion data, range fit for

  6186.   *         ADC resolution 12 bits.

  6187.   * @note   For devices with feature oversampling: Oversampling

  6188.   *         can increase data width, function for extended range

  6189.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6190.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n

  6191.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n

  6192.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n

  6193.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12

  6194.   * @param  ADCx ADC instance

  6195.   * @param  Rank This parameter can be one of the following values:

  6196.   *         @arg @ref LL_ADC_INJ_RANK_1

  6197.   *         @arg @ref LL_ADC_INJ_RANK_2

  6198.   *         @arg @ref LL_ADC_INJ_RANK_3

  6199.   *         @arg @ref LL_ADC_INJ_RANK_4

  6200.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  6201.   */

  6202. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)

  6203. {

  6204.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6205. 

  6206.   return (uint16_t)(READ_BIT(*preg,

  6207.                              ADC_JDR1_JDATA)

  6208.                    );

  6209. }

  6210. 

  6211. /**

  6212.   * @brief  Get ADC group injected conversion data, range fit for

  6213.   *         ADC resolution 10 bits.

  6214.   * @note   For devices with feature oversampling: Oversampling

  6215.   *         can increase data width, function for extended range

  6216.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6217.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n

  6218.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n

  6219.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n

  6220.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10

  6221.   * @param  ADCx ADC instance

  6222.   * @param  Rank This parameter can be one of the following values:

  6223.   *         @arg @ref LL_ADC_INJ_RANK_1

  6224.   *         @arg @ref LL_ADC_INJ_RANK_2

  6225.   *         @arg @ref LL_ADC_INJ_RANK_3

  6226.   *         @arg @ref LL_ADC_INJ_RANK_4

  6227.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  6228.   */

  6229. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)

  6230. {

  6231.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6232. 

  6233.   return (uint16_t)(READ_BIT(*preg,

  6234.                              ADC_JDR1_JDATA)

  6235.                    );

  6236. }

  6237. 

  6238. /**

  6239.   * @brief  Get ADC group injected conversion data, range fit for

  6240.   *         ADC resolution 8 bits.

  6241.   * @note   For devices with feature oversampling: Oversampling

  6242.   *         can increase data width, function for extended range

  6243.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  6244.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n

  6245.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n

  6246.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n

  6247.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8

  6248.   * @param  ADCx ADC instance

  6249.   * @param  Rank This parameter can be one of the following values:

  6250.   *         @arg @ref LL_ADC_INJ_RANK_1

  6251.   *         @arg @ref LL_ADC_INJ_RANK_2

  6252.   *         @arg @ref LL_ADC_INJ_RANK_3

  6253.   *         @arg @ref LL_ADC_INJ_RANK_4

  6254.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  6255.   */

  6256. __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)

  6257. {

  6258.   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

  6259. 

  6260.   return (uint8_t)(READ_BIT(*preg,

  6261.                             ADC_JDR1_JDATA)

  6262.                   );

  6263. }

  6264. 

  6265. /**

  6266.   * @}

  6267.   */

  6268. 

  6269. /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management

  6270.   * @{

  6271.   */

  6272. 

  6273. /**

  6274.   * @brief  Get flag ADC ready.

  6275.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  6276.   *         is enabled and when conversion clock is active.

  6277.   *         (not only core clock: this ADC has a dual clock domain)

  6278.   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY

  6279.   * @param  ADCx ADC instance

  6280.   * @retval State of bit (1 or 0).

  6281.   */

  6282. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)

  6283. {

  6284.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);

  6285. }

  6286. 

  6287. /**

  6288.   * @brief  Get flag ADC group regular end of unitary conversion.

  6289.   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC

  6290.   * @param  ADCx ADC instance

  6291.   * @retval State of bit (1 or 0).

  6292.   */

  6293. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)

  6294. {

  6295.   return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);

  6296. }

  6297. 

  6298. /**

  6299.   * @brief  Get flag ADC group regular end of sequence conversions.

  6300.   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS

  6301.   * @param  ADCx ADC instance

  6302.   * @retval State of bit (1 or 0).

  6303.   */

  6304. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)

  6305. {

  6306.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);

  6307. }

  6308. 

  6309. /**

  6310.   * @brief  Get flag ADC group regular overrun.

  6311.   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR

  6312.   * @param  ADCx ADC instance

  6313.   * @retval State of bit (1 or 0).

  6314.   */

  6315. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)

  6316. {

  6317.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);

  6318. }

  6319. 

  6320. /**

  6321.   * @brief  Get flag ADC group regular end of sampling phase.

  6322.   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP

  6323.   * @param  ADCx ADC instance

  6324.   * @retval State of bit (1 or 0).

  6325.   */

  6326. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)

  6327. {

  6328.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);

  6329. }

  6330. 

  6331. /**

  6332.   * @brief  Get flag ADC group injected end of unitary conversion.

  6333.   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC

  6334.   * @param  ADCx ADC instance

  6335.   * @retval State of bit (1 or 0).

  6336.   */

  6337. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)

  6338. {

  6339.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);

  6340. }

  6341. 

  6342. /**

  6343.   * @brief  Get flag ADC group injected end of sequence conversions.

  6344.   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS

  6345.   * @param  ADCx ADC instance

  6346.   * @retval State of bit (1 or 0).

  6347.   */

  6348. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)

  6349. {

  6350.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);

  6351. }

  6352. 

  6353. /**

  6354.   * @brief  Get flag ADC group injected contexts queue overflow.

  6355.   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF

  6356.   * @param  ADCx ADC instance

  6357.   * @retval State of bit (1 or 0).

  6358.   */

  6359. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)

  6360. {

  6361.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);

  6362. }

  6363. 

  6364. /**

  6365.   * @brief  Get flag ADC analog watchdog 1 flag

  6366.   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1

  6367.   * @param  ADCx ADC instance

  6368.   * @retval State of bit (1 or 0).

  6369.   */

  6370. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)

  6371. {

  6372.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);

  6373. }

  6374. 

  6375. /**

  6376.   * @brief  Get flag ADC analog watchdog 2.

  6377.   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2

  6378.   * @param  ADCx ADC instance

  6379.   * @retval State of bit (1 or 0).

  6380.   */

  6381. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)

  6382. {

  6383.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);

  6384. }

  6385. 

  6386. /**

  6387.   * @brief  Get flag ADC analog watchdog 3.

  6388.   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3

  6389.   * @param  ADCx ADC instance

  6390.   * @retval State of bit (1 or 0).

  6391.   */

  6392. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)

  6393. {

  6394.   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);

  6395. }

  6396. 

  6397. /**

  6398.   * @brief  Clear flag ADC ready.

  6399.   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

  6400.   *         is enabled and when conversion clock is active.

  6401.   *         (not only core clock: this ADC has a dual clock domain)

  6402.   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY

  6403.   * @param  ADCx ADC instance

  6404.   * @retval None

  6405.   */

  6406. __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)

  6407. {

  6408.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);

  6409. }

  6410. 

  6411. /**

  6412.   * @brief  Clear flag ADC group regular end of unitary conversion.

  6413.   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC

  6414.   * @param  ADCx ADC instance

  6415.   * @retval None

  6416.   */

  6417. __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)

  6418. {

  6419.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);

  6420. }

  6421. 

  6422. /**

  6423.   * @brief  Clear flag ADC group regular end of sequence conversions.

  6424.   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS

  6425.   * @param  ADCx ADC instance

  6426.   * @retval None

  6427.   */

  6428. __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)

  6429. {

  6430.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);

  6431. }

  6432. 

  6433. /**

  6434.   * @brief  Clear flag ADC group regular overrun.

  6435.   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR

  6436.   * @param  ADCx ADC instance

  6437.   * @retval None

  6438.   */

  6439. __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)

  6440. {

  6441.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);

  6442. }

  6443. 

  6444. /**

  6445.   * @brief  Clear flag ADC group regular end of sampling phase.

  6446.   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP

  6447.   * @param  ADCx ADC instance

  6448.   * @retval None

  6449.   */

  6450. __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)

  6451. {

  6452.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);

  6453. }

  6454. 

  6455. /**

  6456.   * @brief  Clear flag ADC group injected end of unitary conversion.

  6457.   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC

  6458.   * @param  ADCx ADC instance

  6459.   * @retval None

  6460.   */

  6461. __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)

  6462. {

  6463.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);

  6464. }

  6465. 

  6466. /**

  6467.   * @brief  Clear flag ADC group injected end of sequence conversions.

  6468.   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS

  6469.   * @param  ADCx ADC instance

  6470.   * @retval None

  6471.   */

  6472. __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)

  6473. {

  6474.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);

  6475. }

  6476. 

  6477. /**

  6478.   * @brief  Clear flag ADC group injected contexts queue overflow.

  6479.   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF

  6480.   * @param  ADCx ADC instance

  6481.   * @retval None

  6482.   */

  6483. __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)

  6484. {

  6485.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);

  6486. }

  6487. 

  6488. /**

  6489.   * @brief  Clear flag ADC analog watchdog 1.

  6490.   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1

  6491.   * @param  ADCx ADC instance

  6492.   * @retval None

  6493.   */

  6494. __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)

  6495. {

  6496.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);

  6497. }

  6498. 

  6499. /**

  6500.   * @brief  Clear flag ADC analog watchdog 2.

  6501.   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2

  6502.   * @param  ADCx ADC instance

  6503.   * @retval None

  6504.   */

  6505. __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)

  6506. {

  6507.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);

  6508. }

  6509. 

  6510. /**

  6511.   * @brief  Clear flag ADC analog watchdog 3.

  6512.   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3

  6513.   * @param  ADCx ADC instance

  6514.   * @retval None

  6515.   */

  6516. __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)

  6517. {

  6518.   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);

  6519. }

  6520. 

  6521. /**

  6522.   * @brief  Get flag multimode ADC ready of the ADC master.

  6523.   * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY

  6524.   * @param  ADCxy_COMMON ADC common instance

  6525.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6526.   * @retval State of bit (1 or 0).

  6527.   */

  6528. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)

  6529. {

  6530.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);

  6531. }

  6532. 

  6533. /**

  6534.   * @brief  Get flag multimode ADC ready of the ADC slave.

  6535.   * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY

  6536.   * @param  ADCxy_COMMON ADC common instance

  6537.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6538.   * @retval State of bit (1 or 0).

  6539.   */

  6540. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)

  6541. {

  6542.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);

  6543. }

  6544. 

  6545. /**

  6546.   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.

  6547.   * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC

  6548.   * @param  ADCxy_COMMON ADC common instance

  6549.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6550.   * @retval State of bit (1 or 0).

  6551.   */

  6552. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)

  6553. {

  6554.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);

  6555. }

  6556. 

  6557. /**

  6558.   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.

  6559.   * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC

  6560.   * @param  ADCxy_COMMON ADC common instance

  6561.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6562.   * @retval State of bit (1 or 0).

  6563.   */

  6564. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)

  6565. {

  6566.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);

  6567. }

  6568. 

  6569. /**

  6570.   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.

  6571.   * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS

  6572.   * @param  ADCxy_COMMON ADC common instance

  6573.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6574.   * @retval State of bit (1 or 0).

  6575.   */

  6576. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)

  6577. {

  6578.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);

  6579. }

  6580. 

  6581. /**

  6582.   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.

  6583.   * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS

  6584.   * @param  ADCxy_COMMON ADC common instance

  6585.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6586.   * @retval State of bit (1 or 0).

  6587.   */

  6588. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)

  6589. {

  6590.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);

  6591. }

  6592. 

  6593. /**

  6594.   * @brief  Get flag multimode ADC group regular overrun of the ADC master.

  6595.   * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR

  6596.   * @param  ADCxy_COMMON ADC common instance

  6597.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6598.   * @retval State of bit (1 or 0).

  6599.   */

  6600. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

  6601. {

  6602.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);

  6603. }

  6604. 

  6605. /**

  6606.   * @brief  Get flag multimode ADC group regular overrun of the ADC slave.

  6607.   * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR

  6608.   * @param  ADCxy_COMMON ADC common instance

  6609.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6610.   * @retval State of bit (1 or 0).

  6611.   */

  6612. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

  6613. {

  6614.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);

  6615. }

  6616. 

  6617. /**

  6618.   * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.

  6619.   * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP

  6620.   * @param  ADCxy_COMMON ADC common instance

  6621.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6622.   * @retval State of bit (1 or 0).

  6623.   */

  6624. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)

  6625. {

  6626.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);

  6627. }

  6628. 

  6629. /**

  6630.   * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.

  6631.   * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP

  6632.   * @param  ADCxy_COMMON ADC common instance

  6633.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6634.   * @retval State of bit (1 or 0).

  6635.   */

  6636. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)

  6637. {

  6638.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);

  6639. }

  6640. 

  6641. /**

  6642.   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.

  6643.   * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC

  6644.   * @param  ADCxy_COMMON ADC common instance

  6645.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6646.   * @retval State of bit (1 or 0).

  6647.   */

  6648. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)

  6649. {

  6650.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);

  6651. }

  6652. 

  6653. /**

  6654.   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.

  6655.   * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC

  6656.   * @param  ADCxy_COMMON ADC common instance

  6657.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6658.   * @retval State of bit (1 or 0).

  6659.   */

  6660. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)

  6661. {

  6662.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);

  6663. }

  6664. 

  6665. /**

  6666.   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.

  6667.   * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS

  6668.   * @param  ADCxy_COMMON ADC common instance

  6669.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6670.   * @retval State of bit (1 or 0).

  6671.   */

  6672. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

  6673. {

  6674.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);

  6675. }

  6676. 

  6677. /**

  6678.   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.

  6679.   * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS

  6680.   * @param  ADCxy_COMMON ADC common instance

  6681.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6682.   * @retval State of bit (1 or 0).

  6683.   */

  6684. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

  6685. {

  6686.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);

  6687. }

  6688. 

  6689. /**

  6690.   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.

  6691.   * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF

  6692.   * @param  ADCxy_COMMON ADC common instance

  6693.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6694.   * @retval State of bit (1 or 0).

  6695.   */

  6696. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)

  6697. {

  6698.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);

  6699. }

  6700. 

  6701. /**

  6702.   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.

  6703.   * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF

  6704.   * @param  ADCxy_COMMON ADC common instance

  6705.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6706.   * @retval State of bit (1 or 0).

  6707.   */

  6708. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)

  6709. {

  6710.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);

  6711. }

  6712. 

  6713. /**

  6714.   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.

  6715.   * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1

  6716.   * @param  ADCxy_COMMON ADC common instance

  6717.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6718.   * @retval State of bit (1 or 0).

  6719.   */

  6720. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

  6721. {

  6722.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);

  6723. }

  6724. 

  6725. /**

  6726.   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.

  6727.   * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1

  6728.   * @param  ADCxy_COMMON ADC common instance

  6729.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6730.   * @retval State of bit (1 or 0).

  6731.   */

  6732. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

  6733. {

  6734.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);

  6735. }

  6736. 

  6737. /**

  6738.   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.

  6739.   * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2

  6740.   * @param  ADCxy_COMMON ADC common instance

  6741.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6742.   * @retval State of bit (1 or 0).

  6743.   */

  6744. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)

  6745. {

  6746.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);

  6747. }

  6748. 

  6749. /**

  6750.   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.

  6751.   * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2

  6752.   * @param  ADCxy_COMMON ADC common instance

  6753.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6754.   * @retval State of bit (1 or 0).

  6755.   */

  6756. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)

  6757. {

  6758.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);

  6759. }

  6760. 

  6761. /**

  6762.   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.

  6763.   * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3

  6764.   * @param  ADCxy_COMMON ADC common instance

  6765.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6766.   * @retval State of bit (1 or 0).

  6767.   */

  6768. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)

  6769. {

  6770.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);

  6771. }

  6772. 

  6773. /**

  6774.   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.

  6775.   * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3

  6776.   * @param  ADCxy_COMMON ADC common instance

  6777.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  6778.   * @retval State of bit (1 or 0).

  6779.   */

  6780. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)

  6781. {

  6782.   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);

  6783. }

  6784. 

  6785. /**

  6786.   * @}

  6787.   */

  6788. 

  6789. /** @defgroup ADC_LL_EF_IT_Management ADC IT management

  6790.   * @{

  6791.   */

  6792. 

  6793. /**

  6794.   * @brief  Enable ADC ready.

  6795.   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY

  6796.   * @param  ADCx ADC instance

  6797.   * @retval None

  6798.   */

  6799. __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)

  6800. {

  6801.   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);

  6802. }

  6803. 

  6804. /**

  6805.   * @brief  Enable interruption ADC group regular end of unitary conversion.

  6806.   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC

  6807.   * @param  ADCx ADC instance

  6808.   * @retval None

  6809.   */

  6810. __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)

  6811. {

  6812.   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);

  6813. }

  6814. 

  6815. /**

  6816.   * @brief  Enable interruption ADC group regular end of sequence conversions.

  6817.   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS

  6818.   * @param  ADCx ADC instance

  6819.   * @retval None

  6820.   */

  6821. __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)

  6822. {

  6823.   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);

  6824. }

  6825. 

  6826. /**

  6827.   * @brief  Enable ADC group regular interruption overrun.

  6828.   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR

  6829.   * @param  ADCx ADC instance

  6830.   * @retval None

  6831.   */

  6832. __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)

  6833. {

  6834.   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);

  6835. }

  6836. 

  6837. /**

  6838.   * @brief  Enable interruption ADC group regular end of sampling.

  6839.   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP

  6840.   * @param  ADCx ADC instance

  6841.   * @retval None

  6842.   */

  6843. __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)

  6844. {

  6845.   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);

  6846. }

  6847. 

  6848. /**

  6849.   * @brief  Enable interruption ADC group injected end of unitary conversion.

  6850.   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC

  6851.   * @param  ADCx ADC instance

  6852.   * @retval None

  6853.   */

  6854. __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)

  6855. {

  6856.   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);

  6857. }

  6858. 

  6859. /**

  6860.   * @brief  Enable interruption ADC group injected end of sequence conversions.

  6861.   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS

  6862.   * @param  ADCx ADC instance

  6863.   * @retval None

  6864.   */

  6865. __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)

  6866. {

  6867.   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);

  6868. }

  6869. 

  6870. /**

  6871.   * @brief  Enable interruption ADC group injected context queue overflow.

  6872.   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF

  6873.   * @param  ADCx ADC instance

  6874.   * @retval None

  6875.   */

  6876. __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)

  6877. {

  6878.   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);

  6879. }

  6880. 

  6881. /**

  6882.   * @brief  Enable interruption ADC analog watchdog 1.

  6883.   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1

  6884.   * @param  ADCx ADC instance

  6885.   * @retval None

  6886.   */

  6887. __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)

  6888. {

  6889.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);

  6890. }

  6891. 

  6892. /**

  6893.   * @brief  Enable interruption ADC analog watchdog 2.

  6894.   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2

  6895.   * @param  ADCx ADC instance

  6896.   * @retval None

  6897.   */

  6898. __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)

  6899. {

  6900.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);

  6901. }

  6902. 

  6903. /**

  6904.   * @brief  Enable interruption ADC analog watchdog 3.

  6905.   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3

  6906.   * @param  ADCx ADC instance

  6907.   * @retval None

  6908.   */

  6909. __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)

  6910. {

  6911.   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);

  6912. }

  6913. 

  6914. /**

  6915.   * @brief  Disable interruption ADC ready.

  6916.   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY

  6917.   * @param  ADCx ADC instance

  6918.   * @retval None

  6919.   */

  6920. __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)

  6921. {

  6922.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);

  6923. }

  6924. 

  6925. /**

  6926.   * @brief  Disable interruption ADC group regular end of unitary conversion.

  6927.   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC

  6928.   * @param  ADCx ADC instance

  6929.   * @retval None

  6930.   */

  6931. __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)

  6932. {

  6933.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);

  6934. }

  6935. 

  6936. /**

  6937.   * @brief  Disable interruption ADC group regular end of sequence conversions.

  6938.   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS

  6939.   * @param  ADCx ADC instance

  6940.   * @retval None

  6941.   */

  6942. __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)

  6943. {

  6944.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);

  6945. }

  6946. 

  6947. /**

  6948.   * @brief  Disable interruption ADC group regular overrun.

  6949.   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR

  6950.   * @param  ADCx ADC instance

  6951.   * @retval None

  6952.   */

  6953. __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)

  6954. {

  6955.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);

  6956. }

  6957. 

  6958. /**

  6959.   * @brief  Disable interruption ADC group regular end of sampling.

  6960.   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP

  6961.   * @param  ADCx ADC instance

  6962.   * @retval None

  6963.   */

  6964. __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)

  6965. {

  6966.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);

  6967. }

  6968. 

  6969. /**

  6970.   * @brief  Disable interruption ADC group regular end of unitary conversion.

  6971.   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC

  6972.   * @param  ADCx ADC instance

  6973.   * @retval None

  6974.   */

  6975. __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)

  6976. {

  6977.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);

  6978. }

  6979. 

  6980. /**

  6981.   * @brief  Disable interruption ADC group injected end of sequence conversions.

  6982.   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS

  6983.   * @param  ADCx ADC instance

  6984.   * @retval None

  6985.   */

  6986. __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)

  6987. {

  6988.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);

  6989. }

  6990. 

  6991. /**

  6992.   * @brief  Disable interruption ADC group injected context queue overflow.

  6993.   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF

  6994.   * @param  ADCx ADC instance

  6995.   * @retval None

  6996.   */

  6997. __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)

  6998. {

  6999.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);

  7000. }

  7001. 

  7002. /**

  7003.   * @brief  Disable interruption ADC analog watchdog 1.

  7004.   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1

  7005.   * @param  ADCx ADC instance

  7006.   * @retval None

  7007.   */

  7008. __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)

  7009. {

  7010.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);

  7011. }

  7012. 

  7013. /**

  7014.   * @brief  Disable interruption ADC analog watchdog 2.

  7015.   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2

  7016.   * @param  ADCx ADC instance

  7017.   * @retval None

  7018.   */

  7019. __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)

  7020. {

  7021.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);

  7022. }

  7023. 

  7024. /**

  7025.   * @brief  Disable interruption ADC analog watchdog 3.

  7026.   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3

  7027.   * @param  ADCx ADC instance

  7028.   * @retval None

  7029.   */

  7030. __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)

  7031. {

  7032.   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);

  7033. }

  7034. 

  7035. /**

  7036.   * @brief  Get state of interruption ADC ready

  7037.   *         (0: interrupt disabled, 1: interrupt enabled).

  7038.   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY

  7039.   * @param  ADCx ADC instance

  7040.   * @retval State of bit (1 or 0).

  7041.   */

  7042. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)

  7043. {

  7044.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);

  7045. }

  7046. 

  7047. /**

  7048.   * @brief  Get state of interruption ADC group regular end of unitary conversion

  7049.   *         (0: interrupt disabled, 1: interrupt enabled).

  7050.   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC

  7051.   * @param  ADCx ADC instance

  7052.   * @retval State of bit (1 or 0).

  7053.   */

  7054. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)

  7055. {

  7056.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);

  7057. }

  7058. 

  7059. /**

  7060.   * @brief  Get state of interruption ADC group regular end of sequence conversions

  7061.   *         (0: interrupt disabled, 1: interrupt enabled).

  7062.   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS

  7063.   * @param  ADCx ADC instance

  7064.   * @retval State of bit (1 or 0).

  7065.   */

  7066. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)

  7067. {

  7068.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);

  7069. }

  7070. 

  7071. /**

  7072.   * @brief  Get state of interruption ADC group regular overrun

  7073.   *         (0: interrupt disabled, 1: interrupt enabled).

  7074.   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR

  7075.   * @param  ADCx ADC instance

  7076.   * @retval State of bit (1 or 0).

  7077.   */

  7078. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)

  7079. {

  7080.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);

  7081. }

  7082. 

  7083. /**

  7084.   * @brief  Get state of interruption ADC group regular end of sampling

  7085.   *         (0: interrupt disabled, 1: interrupt enabled).

  7086.   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP

  7087.   * @param  ADCx ADC instance

  7088.   * @retval State of bit (1 or 0).

  7089.   */

  7090. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)

  7091. {

  7092.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);

  7093. }

  7094. 

  7095. /**

  7096.   * @brief  Get state of interruption ADC group injected end of unitary conversion

  7097.   *         (0: interrupt disabled, 1: interrupt enabled).

  7098.   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC

  7099.   * @param  ADCx ADC instance

  7100.   * @retval State of bit (1 or 0).

  7101.   */

  7102. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)

  7103. {

  7104.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);

  7105. }

  7106. 

  7107. /**

  7108.   * @brief  Get state of interruption ADC group injected end of sequence conversions

  7109.   *         (0: interrupt disabled, 1: interrupt enabled).

  7110.   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS

  7111.   * @param  ADCx ADC instance

  7112.   * @retval State of bit (1 or 0).

  7113.   */

  7114. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)

  7115. {

  7116.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);

  7117. }

  7118. 

  7119. /**

  7120.   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state

  7121.   *         (0: interrupt disabled, 1: interrupt enabled).

  7122.   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF

  7123.   * @param  ADCx ADC instance

  7124.   * @retval State of bit (1 or 0).

  7125.   */

  7126. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)

  7127. {

  7128.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);

  7129. }

  7130. 

  7131. /**

  7132.   * @brief  Get state of interruption ADC analog watchdog 1

  7133.   *         (0: interrupt disabled, 1: interrupt enabled).

  7134.   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1

  7135.   * @param  ADCx ADC instance

  7136.   * @retval State of bit (1 or 0).

  7137.   */

  7138. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)

  7139. {

  7140.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);

  7141. }

  7142. 

  7143. /**

  7144.   * @brief  Get state of interruption Get ADC analog watchdog 2

  7145.   *         (0: interrupt disabled, 1: interrupt enabled).

  7146.   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2

  7147.   * @param  ADCx ADC instance

  7148.   * @retval State of bit (1 or 0).

  7149.   */

  7150. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)

  7151. {

  7152.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);

  7153. }

  7154. 

  7155. /**

  7156.   * @brief  Get state of interruption Get ADC analog watchdog 3

  7157.   *         (0: interrupt disabled, 1: interrupt enabled).

  7158.   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3

  7159.   * @param  ADCx ADC instance

  7160.   * @retval State of bit (1 or 0).

  7161.   */

  7162. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)

  7163. {

  7164.   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);

  7165. }

  7166. 

  7167. /**

  7168.   * @}

  7169.   */

  7170. 

  7171. #if defined(USE_FULL_LL_DRIVER)

  7172. /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions

  7173.   * @{

  7174.   */

  7175. 

  7176. /* Initialization of some features of ADC common parameters and multimode */

  7177. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);

  7178. ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  7179. void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  7180. 

  7181. /* De-initialization of ADC instance, ADC group regular and ADC group injected */

  7182. /* (availability of ADC group injected depends on STM32 families) */

  7183. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);

  7184. 

  7185. /* Initialization of some features of ADC instance */

  7186. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);

  7187. void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);

  7188. 

  7189. /* Initialization of some features of ADC instance and ADC group regular */

  7190. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  7191. void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  7192. 

  7193. /* Initialization of some features of ADC instance and ADC group injected */

  7194. ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  7195. void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  7196. 

  7197. /**

  7198.   * @}

  7199.   */

  7200. #endif /* USE_FULL_LL_DRIVER */

  7201. 

  7202. /**

  7203.   * @}

  7204.   */

  7205. 

  7206. /**

  7207.   * @}

  7208.   */

  7209. 

  7210. #endif /* ADC1 || ADC2 || ADC3 */

  7211. 

  7212. /**

  7213.   * @}

  7214.   */

  7215. 

  7216. #ifdef __cplusplus

  7217. }

  7218. #endif

  7219. 

  7220. #endif /* STM32H7xx_LL_ADC_H */

  7221. 

  7222. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/