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  1. /**
  2. ******************************************************************************
  3. * @file stm32h7xx_hal_adc.c
  4. * @author MCD Application Team
  5. * @brief This file provides firmware functions to manage the following
  6. * functionalities of the Analog to Digital Convertor (ADC)
  7. * peripheral:
  8. * + Initialization and de-initialization functions
  9. * ++ Initialization and Configuration of ADC
  10. * + Operation functions
  11. * ++ Start, stop, get result of conversions of regular
  12. * group, using 3 possible modes: polling, interruption or DMA.
  13. * + Control functions
  14. * ++ Channels configuration on regular group
  15. * ++ Analog Watchdog configuration
  16. * + State functions
  17. * ++ ADC state machine management
  18. * ++ Interrupts and flags management
  19. * Other functions (extended functions) are available in file
  20. * "stm32h7xx_hal_adc_ex.c".
  21. *
  22. @verbatim
  23. ==============================================================================
  24. ##### ADC peripheral features #####
  25. ==============================================================================
  26. [..]
  27. (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
  28. (+) Interrupt generation at the end of regular conversion and in case of
  29. analog watchdog or overrun events.
  30. (+) Single and continuous conversion modes.
  31. (+) Scan mode for conversion of several channels sequentially.
  32. (+) Data alignment with in-built data coherency.
  33. (+) Programmable sampling time (channel wise)
  34. (+) External trigger (timer or EXTI) with configurable polarity
  35. (+) DMA request generation for transfer of conversions data of regular group.
  36. (+) Configurable delay between conversions in Dual interleaved mode.
  37. (+) ADC channels selectable single/differential input.
  38. (+) ADC offset shared on 4 offset instances.
  39. (+) ADC calibration
  40. (+) ADC conversion of regular group.
  41. (+) ADC supply requirements: 1.62 V to 3.6 V.
  42. (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
  43. Vdda or to an external voltage reference).
  44. ##### How to use this driver #####
  45. ==============================================================================
  46. [..]
  47. *** Configuration of top level parameters related to ADC ***
  48. ============================================================
  49. [..]
  50. (#) Enable the ADC interface
  51. (++) As prerequisite, ADC clock must be configured at RCC top level.
  52. (++) Two clock settings are mandatory:
  53. (+++) ADC clock (core clock, also possibly conversion clock).
  54. (+++) ADC clock (conversions clock).
  55. Two possible clock sources: synchronous clock derived from AHB clock
  56. or asynchronous clock derived from system clock, the PLL2 or the PLL3 running up to 400MHz.
  57. (+++) Example:
  58. Into HAL_ADC_MspInit() (recommended code location) or with
  59. other device clock parameters configuration:
  60. (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
  61. RCC_ADCCLKSOURCE_PLL2 enable: (optional: if asynchronous clock selected)
  62. (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
  63. (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  64. (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
  65. (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
  66. (++) ADC clock source and clock prescaler are configured at ADC level with
  67. parameter "ClockPrescaler" using function HAL_ADC_Init().
  68. (#) ADC pins configuration
  69. (++) Enable the clock for the ADC GPIOs
  70. using macro __HAL_RCC_GPIOx_CLK_ENABLE()
  71. (++) Configure these ADC pins in analog mode
  72. using function HAL_GPIO_Init()
  73. (#) Optionally, in case of usage of ADC with interruptions:
  74. (++) Configure the NVIC for ADC
  75. using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
  76. (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
  77. into the function of corresponding ADC interruption vector
  78. ADCx_IRQHandler().
  79. (#) Optionally, in case of usage of DMA:
  80. (++) Configure the DMA (DMA channel, mode normal or circular, ...)
  81. using function HAL_DMA_Init().
  82. (++) Configure the NVIC for DMA
  83. using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
  84. (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
  85. into the function of corresponding DMA interruption vector
  86. DMAx_Channelx_IRQHandler().
  87. *** Configuration of ADC, group regular, channels parameters ***
  88. ================================================================
  89. [..]
  90. (#) Configure the ADC parameters (resolution, data alignment, ...)
  91. and regular group parameters (conversion trigger, sequencer, ...)
  92. using function HAL_ADC_Init().
  93. (#) Configure the channels for regular group parameters (channel number,
  94. channel rank into sequencer, ..., into regular group)
  95. using function HAL_ADC_ConfigChannel().
  96. (#) Optionally, configure the analog watchdog parameters (channels
  97. monitored, thresholds, ...)
  98. using function HAL_ADC_AnalogWDGConfig().
  99. *** Execution of ADC conversions ***
  100. ====================================
  101. [..]
  102. (#) Optionally, perform an automatic ADC calibration to improve the
  103. conversion accuracy
  104. using function HAL_ADCEx_Calibration_Start().
  105. (#) ADC driver can be used among three modes: polling, interruption,
  106. transfer by DMA.
  107. (++) ADC conversion by polling:
  108. (+++) Activate the ADC peripheral and start conversions
  109. using function HAL_ADC_Start()
  110. (+++) Wait for ADC conversion completion
  111. using function HAL_ADC_PollForConversion()
  112. (+++) Retrieve conversion results
  113. using function HAL_ADC_GetValue()
  114. (+++) Stop conversion and disable the ADC peripheral
  115. using function HAL_ADC_Stop()
  116. (++) ADC conversion by interruption:
  117. (+++) Activate the ADC peripheral and start conversions
  118. using function HAL_ADC_Start_IT()
  119. (+++) Wait for ADC conversion completion by call of function
  120. HAL_ADC_ConvCpltCallback()
  121. (this function must be implemented in user program)
  122. (+++) Retrieve conversion results
  123. using function HAL_ADC_GetValue()
  124. (+++) Stop conversion and disable the ADC peripheral
  125. using function HAL_ADC_Stop_IT()
  126. (++) ADC conversion with transfer by DMA:
  127. (+++) Activate the ADC peripheral and start conversions
  128. using function HAL_ADC_Start_DMA()
  129. (+++) Wait for ADC conversion completion by call of function
  130. HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
  131. (these functions must be implemented in user program)
  132. (+++) Conversion results are automatically transferred by DMA into
  133. destination variable address.
  134. (+++) Stop conversion and disable the ADC peripheral
  135. using function HAL_ADC_Stop_DMA()
  136. [..]
  137. (@) Callback functions must be implemented in user program:
  138. (+@) HAL_ADC_ErrorCallback()
  139. (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
  140. (+@) HAL_ADC_ConvCpltCallback()
  141. (+@) HAL_ADC_ConvHalfCpltCallback
  142. *** Deinitialization of ADC ***
  143. ============================================================
  144. [..]
  145. (#) Disable the ADC interface
  146. (++) ADC clock can be hard reset and disabled at RCC top level.
  147. (++) Hard reset of ADC peripherals
  148. using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
  149. (++) ADC clock disable
  150. using the equivalent macro/functions as configuration step.
  151. (+++) Example:
  152. Into HAL_ADC_MspDeInit() (recommended code location) or with
  153. other device clock parameters configuration:
  154. (+++) __HAL_RCC_ADC_CLK_DISABLE(); (if not used anymore)
  155. RCC_ADCCLKSOURCE_CLKP restore: (optional)
  156. (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
  157. (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  158. (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
  159. (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
  160. (#) ADC pins configuration
  161. (++) Disable the clock for the ADC GPIOs
  162. using macro __HAL_RCC_GPIOx_CLK_DISABLE()
  163. (#) Optionally, in case of usage of ADC with interruptions:
  164. (++) Disable the NVIC for ADC
  165. using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
  166. (#) Optionally, in case of usage of DMA:
  167. (++) Deinitialize the DMA
  168. using function HAL_DMA_Init().
  169. (++) Disable the NVIC for DMA
  170. using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
  171. [..]
  172. *** Callback registration ***
  173. =============================================
  174. [..]
  175. The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
  176. allows the user to configure dynamically the driver callbacks.
  177. Use Functions @ref HAL_ADC_RegisterCallback()
  178. to register an interrupt callback.
  179. [..]
  180. Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
  181. (+) ConvCpltCallback : ADC conversion complete callback
  182. (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
  183. (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
  184. (+) ErrorCallback : ADC error callback
  185. (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
  186. (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
  187. (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
  188. (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
  189. (+) EndOfSamplingCallback : ADC end of sampling callback
  190. (+) MspInitCallback : ADC Msp Init callback
  191. (+) MspDeInitCallback : ADC Msp DeInit callback
  192. This function takes as parameters the HAL peripheral handle, the Callback ID
  193. and a pointer to the user callback function.
  194. [..]
  195. Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
  196. weak function.
  197. [..]
  198. @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
  199. and the Callback ID.
  200. This function allows to reset following callbacks:
  201. (+) ConvCpltCallback : ADC conversion complete callback
  202. (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
  203. (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
  204. (+) ErrorCallback : ADC error callback
  205. (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
  206. (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
  207. (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
  208. (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
  209. (+) EndOfSamplingCallback : ADC end of sampling callback
  210. (+) MspInitCallback : ADC Msp Init callback
  211. (+) MspDeInitCallback : ADC Msp DeInit callback
  212. [..]
  213. By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
  214. all callbacks are set to the corresponding weak functions:
  215. examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
  216. Exception done for MspInit and MspDeInit functions that are
  217. reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
  218. these callbacks are null (not registered beforehand).
  219. [..]
  220. If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
  221. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
  222. [..]
  223. Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
  224. Exception done MspInit/MspDeInit functions that can be registered/unregistered
  225. in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
  226. thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  227. [..]
  228. Then, the user first registers the MspInit/MspDeInit user callbacks
  229. using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
  230. or @ref HAL_ADC_Init() function.
  231. [..]
  232. When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
  233. not defined, the callback registration feature is not available and all callbacks
  234. are set to the corresponding weak functions.
  235. @endverbatim
  236. ******************************************************************************
  237. * @attention
  238. *
  239. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  240. * All rights reserved.</center></h2>
  241. *
  242. * This software component is licensed by ST under BSD 3-Clause license,
  243. * the "License"; You may not use this file except in compliance with the
  244. * License. You may obtain a copy of the License at:
  245. * opensource.org/licenses/BSD-3-Clause
  246. *
  247. ******************************************************************************
  248. */
  249. /* Includes ------------------------------------------------------------------*/
  250. #include "stm32h7xx_hal.h"
  251. /** @addtogroup STM32H7xx_HAL_Driver
  252. * @{
  253. */
  254. /** @defgroup ADC ADC
  255. * @brief ADC HAL module driver
  256. * @{
  257. */
  258. #ifdef HAL_ADC_MODULE_ENABLED
  259. /* Private typedef -----------------------------------------------------------*/
  260. /* Private define ------------------------------------------------------------*/
  261. /** @defgroup ADC_Private_Constants ADC Private Constants
  262. * @{
  263. */
  264. #define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES |\
  265. ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
  266. ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
  267. ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
  268. when no regular conversion is on-going */
  269. #define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\
  270. ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
  271. ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
  272. (neither regular nor injected) is on-going */
  273. /* Timeout values for ADC operations (enable settling time, */
  274. /* disable settling time, ...). */
  275. /* Values defined to be higher than worst cases: low clock frequency, */
  276. /* maximum prescalers. */
  277. #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
  278. #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
  279. /* Timeout to wait for current conversion on going to be completed. */
  280. /* Timeout fixed to worst case, for 1 channel. */
  281. /* - maximum sampling time (830.5 adc_clk) */
  282. /* - ADC resolution (Tsar 16 bits= 16.5 adc_clk) */
  283. /* - ADC clock with prescaler 256 */
  284. /* 823 * 256 = 210688 clock cycles max */
  285. /* Unit: cycles of CPU clock. */
  286. #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688) /*!< ADC conversion completion time-out value */
  287. /**
  288. * @}
  289. */
  290. /* Private macro -------------------------------------------------------------*/
  291. /* Private variables ---------------------------------------------------------*/
  292. /* Private function prototypes -----------------------------------------------*/
  293. /* Exported functions --------------------------------------------------------*/
  294. /** @defgroup ADC_Exported_Functions ADC Exported Functions
  295. * @{
  296. */
  297. /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
  298. * @brief ADC Initialization and Configuration functions
  299. *
  300. @verbatim
  301. ===============================================================================
  302. ##### Initialization and de-initialization functions #####
  303. ===============================================================================
  304. [..] This section provides functions allowing to:
  305. (+) Initialize and configure the ADC.
  306. (+) De-initialize the ADC.
  307. @endverbatim
  308. * @{
  309. */
  310. /**
  311. * @brief Initialize the ADC peripheral and regular group according to
  312. * parameters specified in structure "ADC_InitTypeDef".
  313. * @note As prerequisite, ADC clock must be configured at RCC top level
  314. * (refer to description of RCC configuration for ADC
  315. * in header of this file).
  316. * @note Possibility to update parameters on the fly:
  317. * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
  318. * coming from ADC state reset. Following calls to this function can
  319. * be used to reconfigure some parameters of ADC_InitTypeDef
  320. * structure on the fly, without modifying MSP configuration. If ADC
  321. * MSP has to be modified again, HAL_ADC_DeInit() must be called
  322. * before HAL_ADC_Init().
  323. * The setting of these parameters is conditioned to ADC state.
  324. * For parameters constraints, see comments of structure
  325. * "ADC_InitTypeDef".
  326. * @note This function configures the ADC within 2 scopes: scope of entire
  327. * ADC and scope of regular group. For parameters details, see comments
  328. * of structure "ADC_InitTypeDef".
  329. * @note Parameters related to common ADC registers (ADC clock mode) are set
  330. * only if all ADCs are disabled.
  331. * If this is not the case, these common parameters setting are
  332. * bypassed without error reporting: it can be the intended behaviour in
  333. * case of update of a parameter of ADC_InitTypeDef on the fly,
  334. * without disabling the other ADCs.
  335. * @param hadc ADC handle
  336. * @retval HAL status
  337. */
  338. HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
  339. {
  340. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  341. uint32_t tmpCFGR;
  342. uint32_t tmp_adc_reg_is_conversion_on_going;
  343. __IO uint32_t wait_loop_index = 0UL;
  344. uint32_t tmp_adc_is_conversion_on_going_regular;
  345. uint32_t tmp_adc_is_conversion_on_going_injected;
  346. /* Check ADC handle */
  347. if (hadc == NULL)
  348. {
  349. return HAL_ERROR;
  350. }
  351. /* Check the parameters */
  352. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  353. assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
  354. assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
  355. assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
  356. assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  357. assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
  358. assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
  359. assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
  360. assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
  361. assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
  362. assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
  363. assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
  364. if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
  365. {
  366. assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
  367. assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
  368. if (hadc->Init.DiscontinuousConvMode == ENABLE)
  369. {
  370. assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
  371. }
  372. }
  373. /* DISCEN and CONT bits cannot be set at the same time */
  374. assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
  375. /* Actions performed only if ADC is coming from state reset: */
  376. /* - Initialization of ADC MSP */
  377. if (hadc->State == HAL_ADC_STATE_RESET)
  378. {
  379. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  380. /* Init the ADC Callback settings */
  381. hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
  382. hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
  383. hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
  384. hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
  385. hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
  386. hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
  387. hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
  388. hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
  389. hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
  390. if (hadc->MspInitCallback == NULL)
  391. {
  392. hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
  393. }
  394. /* Init the low level hardware */
  395. hadc->MspInitCallback(hadc);
  396. #else
  397. /* Init the low level hardware */
  398. HAL_ADC_MspInit(hadc);
  399. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  400. /* Set ADC error code to none */
  401. ADC_CLEAR_ERRORCODE(hadc);
  402. /* Initialize Lock */
  403. hadc->Lock = HAL_UNLOCKED;
  404. }
  405. /* - Exit from deep-power-down mode and ADC voltage regulator enable */
  406. if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
  407. {
  408. /* Disable ADC deep power down mode */
  409. LL_ADC_DisableDeepPowerDown(hadc->Instance);
  410. /* System was in deep power down mode, calibration must
  411. be relaunched or a previously saved calibration factor
  412. re-applied once the ADC voltage regulator is enabled */
  413. }
  414. if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
  415. {
  416. /* Enable ADC internal voltage regulator */
  417. LL_ADC_EnableInternalRegulator(hadc->Instance);
  418. /* Note: Variable divided by 2 to compensate partially */
  419. /* CPU processing cycles, scaling in us split to not */
  420. /* exceed 32 bits register capacity and handle low frequency. */
  421. wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
  422. while (wait_loop_index != 0UL)
  423. {
  424. wait_loop_index--;
  425. }
  426. }
  427. /* Verification that ADC voltage regulator is correctly enabled, whether */
  428. /* or not ADC is coming from state reset (if any potential problem of */
  429. /* clocking, voltage regulator would not be enabled). */
  430. if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
  431. {
  432. /* Update ADC state machine to error */
  433. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  434. /* Set ADC error code to ADC peripheral internal error */
  435. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  436. tmp_hal_status = HAL_ERROR;
  437. }
  438. /* Configuration of ADC parameters if previous preliminary actions are */
  439. /* correctly completed and if there is no conversion on going on regular */
  440. /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
  441. /* called to update a parameter on the fly). */
  442. tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
  443. if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
  444. && (tmp_adc_reg_is_conversion_on_going == 0UL)
  445. )
  446. {
  447. /* Set ADC state */
  448. ADC_STATE_CLR_SET(hadc->State,
  449. HAL_ADC_STATE_REG_BUSY,
  450. HAL_ADC_STATE_BUSY_INTERNAL);
  451. /* Configuration of common ADC parameters */
  452. /* Parameters update conditioned to ADC state: */
  453. /* Parameters that can be updated only when ADC is disabled: */
  454. /* - clock configuration */
  455. if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
  456. {
  457. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
  458. {
  459. /* Reset configuration of ADC common register CCR: */
  460. /* */
  461. /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
  462. /* according to adc->Init.ClockPrescaler. It selects the clock */
  463. /* source and sets the clock division factor. */
  464. /* */
  465. /* Some parameters of this register are not reset, since they are set */
  466. /* by other functions and must be kept in case of usage of this */
  467. /* function on the fly (update of a parameter of ADC_InitTypeDef */
  468. /* without needing to reconfigure all other ADC groups/channels */
  469. /* parameters): */
  470. /* - when multimode feature is available, multimode-related */
  471. /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
  472. /* HAL_ADCEx_MultiModeConfigChannel() ) */
  473. /* - internal measurement paths: Vbat, temperature sensor, Vref */
  474. /* (set into HAL_ADC_ConfigChannel() or */
  475. /* HAL_ADCEx_InjectedConfigChannel() ) */
  476. LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
  477. }
  478. }
  479. /* Configuration of ADC: */
  480. /* - resolution Init.Resolution */
  481. /* - external trigger to start conversion Init.ExternalTrigConv */
  482. /* - external trigger polarity Init.ExternalTrigConvEdge */
  483. /* - continuous conversion mode Init.ContinuousConvMode */
  484. /* - overrun Init.Overrun */
  485. /* - discontinuous mode Init.DiscontinuousConvMode */
  486. /* - discontinuous mode channel count Init.NbrOfDiscConversion */
  487. #if defined(ADC_VER_V5_3)
  488. tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
  489. hadc->Init.Overrun |
  490. hadc->Init.Resolution |
  491. ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
  492. #else
  493. if((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
  494. {
  495. /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */
  496. tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
  497. hadc->Init.Overrun |
  498. hadc->Init.Resolution |(ADC_CFGR_RES_1|ADC_CFGR_RES_0) |
  499. ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
  500. }
  501. else
  502. {
  503. tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
  504. hadc->Init.Overrun |
  505. hadc->Init.Resolution |
  506. ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
  507. }
  508. #endif /* ADC_VER_V5_3 */
  509. if (hadc->Init.DiscontinuousConvMode == ENABLE)
  510. {
  511. tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
  512. }
  513. /* Enable external trigger if trigger selection is different of software */
  514. /* start. */
  515. /* Note: This configuration keeps the hardware feature of parameter */
  516. /* ExternalTrigConvEdge "trigger edge none" equivalent to */
  517. /* software start. */
  518. if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
  519. {
  520. tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
  521. | hadc->Init.ExternalTrigConvEdge
  522. );
  523. }
  524. /* Update Configuration Register CFGR */
  525. MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
  526. /* Parameters update conditioned to ADC state: */
  527. /* Parameters that can be updated when ADC is disabled or enabled without */
  528. /* conversion on going on regular and injected groups: */
  529. /* - Conversion data management Init.ConversionDataManagement */
  530. /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
  531. /* - Oversampling parameters Init.Oversampling */
  532. tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
  533. tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
  534. if ((tmp_adc_is_conversion_on_going_regular == 0UL)
  535. && (tmp_adc_is_conversion_on_going_injected == 0UL)
  536. )
  537. {
  538. tmpCFGR = (
  539. ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
  540. ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
  541. MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
  542. if (hadc->Init.OversamplingMode == ENABLE)
  543. {
  544. assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
  545. assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
  546. assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
  547. assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
  548. if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
  549. || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
  550. {
  551. /* Multi trigger is not applicable to software-triggered conversions */
  552. assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
  553. }
  554. /* Configuration of Oversampler: */
  555. /* - Oversampling Ratio */
  556. /* - Right bit shift */
  557. /* - Left bit shift */
  558. /* - Triggered mode */
  559. /* - Oversampling mode (continued/resumed) */
  560. MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
  561. ADC_CFGR2_ROVSE |
  562. ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
  563. hadc->Init.Oversampling.RightBitShift |
  564. hadc->Init.Oversampling.TriggeredMode |
  565. hadc->Init.Oversampling.OversamplingStopReset);
  566. }
  567. else
  568. {
  569. /* Disable ADC oversampling scope on ADC group regular */
  570. CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
  571. }
  572. /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
  573. MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
  574. /* Configure the BOOST Mode */
  575. ADC_ConfigureBoostMode(hadc);
  576. }
  577. /* Configuration of regular group sequencer: */
  578. /* - if scan mode is disabled, regular channels sequence length is set to */
  579. /* 0x00: 1 channel converted (channel on regular rank 1) */
  580. /* Parameter "NbrOfConversion" is discarded. */
  581. /* Note: Scan mode is not present by hardware on this device, but */
  582. /* emulated by software for alignment over all STM32 devices. */
  583. /* - if scan mode is enabled, regular channels sequence length is set to */
  584. /* parameter "NbrOfConversion". */
  585. if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
  586. {
  587. /* Set number of ranks in regular group sequencer */
  588. MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
  589. }
  590. else
  591. {
  592. CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
  593. }
  594. /* Initialize the ADC state */
  595. /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
  596. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
  597. }
  598. else
  599. {
  600. /* Update ADC state machine to error */
  601. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  602. tmp_hal_status = HAL_ERROR;
  603. }
  604. /* Return function status */
  605. return tmp_hal_status;
  606. }
  607. /**
  608. * @brief Deinitialize the ADC peripheral registers to their default reset
  609. * values, with deinitialization of the ADC MSP.
  610. * @note For devices with several ADCs: reset of ADC common registers is done
  611. * only if all ADCs sharing the same common group are disabled.
  612. * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
  613. * all ADC instances use the same core clock at RCC level, disabling
  614. * the core clock reset all ADC instances).
  615. * If this is not the case, reset of these common parameters reset is
  616. * bypassed without error reporting: it can be the intended behavior in
  617. * case of reset of a single ADC while the other ADCs sharing the same
  618. * common group is still running.
  619. * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
  620. * this saves more power by reducing leakage currents
  621. * and is particularly interesting before entering MCU low-power modes.
  622. * @param hadc ADC handle
  623. * @retval HAL status
  624. */
  625. HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
  626. {
  627. HAL_StatusTypeDef tmp_hal_status;
  628. /* Check ADC handle */
  629. if (hadc == NULL)
  630. {
  631. return HAL_ERROR;
  632. }
  633. /* Check the parameters */
  634. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  635. /* Set ADC state */
  636. SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
  637. /* Stop potential conversion on going */
  638. tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
  639. /* Disable ADC peripheral if conversions are effectively stopped */
  640. /* Flush register JSQR: reset the queue sequencer when injected */
  641. /* queue sequencer is enabled and ADC disabled. */
  642. /* The software and hardware triggers of the injected sequence are both */
  643. /* internally disabled just after the completion of the last valid */
  644. /* injected sequence. */
  645. SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
  646. /* Disable ADC peripheral if conversions are effectively stopped */
  647. if (tmp_hal_status == HAL_OK)
  648. {
  649. /* Disable the ADC peripheral */
  650. tmp_hal_status = ADC_Disable(hadc);
  651. /* Check if ADC is effectively disabled */
  652. if (tmp_hal_status == HAL_OK)
  653. {
  654. /* Change ADC state */
  655. hadc->State = HAL_ADC_STATE_READY;
  656. }
  657. }
  658. /* Note: HAL ADC deInit is done independently of ADC conversion stop */
  659. /* and disable return status. In case of status fail, attempt to */
  660. /* perform deinitialization anyway and it is up user code in */
  661. /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
  662. /* system RCC hard reset. */
  663. /* ========== Reset ADC registers ========== */
  664. /* Reset register IER */
  665. __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
  666. ADC_IT_JQOVF | ADC_IT_OVR |
  667. ADC_IT_JEOS | ADC_IT_JEOC |
  668. ADC_IT_EOS | ADC_IT_EOC |
  669. ADC_IT_EOSMP | ADC_IT_RDY));
  670. /* Reset register ISR */
  671. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
  672. ADC_FLAG_JQOVF | ADC_FLAG_OVR |
  673. ADC_FLAG_JEOS | ADC_FLAG_JEOC |
  674. ADC_FLAG_EOS | ADC_FLAG_EOC |
  675. ADC_FLAG_EOSMP | ADC_FLAG_RDY));
  676. /* Reset register CR */
  677. /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
  678. ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
  679. no direct reset applicable.
  680. Update CR register to reset value where doable by software */
  681. CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
  682. SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
  683. /* Reset register CFGR */
  684. CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
  685. ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
  686. ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
  687. ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
  688. ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL |
  689. ADC_CFGR_RES | ADC_CFGR_DMNGT);
  690. SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
  691. /* Reset register CFGR2 */
  692. CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
  693. ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
  694. /* Reset register SMPR1 */
  695. CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
  696. /* Reset register SMPR2 */
  697. CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
  698. ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
  699. ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
  700. /* Reset register LTR1 and HTR1 */
  701. CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR_LT);
  702. CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR_HT);
  703. /* Reset register LTR2 and HTR2*/
  704. CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR_LT);
  705. CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR_HT);
  706. /* Reset register LTR3 and HTR3 */
  707. CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR_LT);
  708. CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR_HT);
  709. /* Reset register SQR1 */
  710. CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
  711. ADC_SQR1_SQ1 | ADC_SQR1_L);
  712. /* Reset register SQR2 */
  713. CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
  714. ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
  715. /* Reset register SQR3 */
  716. CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
  717. ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
  718. /* Reset register SQR4 */
  719. CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
  720. /* Register JSQR was reset when the ADC was disabled */
  721. /* Reset register DR */
  722. /* bits in access mode read only, no direct reset applicable*/
  723. /* Reset register OFR1 */
  724. CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
  725. /* Reset register OFR2 */
  726. CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
  727. /* Reset register OFR3 */
  728. CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
  729. /* Reset register OFR4 */
  730. CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
  731. /* Reset registers JDR1, JDR2, JDR3, JDR4 */
  732. /* bits in access mode read only, no direct reset applicable*/
  733. /* Reset register AWD2CR */
  734. CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
  735. /* Reset register AWD3CR */
  736. CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
  737. /* Reset register DIFSEL */
  738. CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
  739. /* Reset register CALFACT */
  740. CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
  741. /* ========== Reset common ADC registers ========== */
  742. /* Software is allowed to change common parameters only when all the other
  743. ADCs are disabled. */
  744. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
  745. {
  746. /* Reset configuration of ADC common register CCR:
  747. - clock mode: CKMODE, PRESCEN
  748. - multimode related parameters(when this feature is available): DELAY, DUAL
  749. (set into HAL_ADCEx_MultiModeConfigChannel() API)
  750. - internal measurement paths: Vbat, temperature sensor, Vref (set into
  751. HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
  752. */
  753. ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
  754. }
  755. /* DeInit the low level hardware.
  756. For example:
  757. __HAL_RCC_ADC_FORCE_RESET();
  758. __HAL_RCC_ADC_RELEASE_RESET();
  759. __HAL_RCC_ADC_CLK_DISABLE();
  760. Keep in mind that all ADCs use the same clock: disabling
  761. the clock will reset all ADCs.
  762. */
  763. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  764. if (hadc->MspDeInitCallback == NULL)
  765. {
  766. hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
  767. }
  768. /* DeInit the low level hardware: RCC clock, NVIC */
  769. hadc->MspDeInitCallback(hadc);
  770. #else
  771. /* DeInit the low level hardware: RCC clock, NVIC */
  772. HAL_ADC_MspDeInit(hadc);
  773. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  774. /* Set ADC error code to none */
  775. ADC_CLEAR_ERRORCODE(hadc);
  776. /* Reset injected channel configuration parameters */
  777. hadc->InjectionConfig.ContextQueue = 0;
  778. hadc->InjectionConfig.ChannelCount = 0;
  779. /* Set ADC state */
  780. hadc->State = HAL_ADC_STATE_RESET;
  781. /* Process unlocked */
  782. __HAL_UNLOCK(hadc);
  783. /* Return function status */
  784. return tmp_hal_status;
  785. }
  786. /**
  787. * @brief Initialize the ADC MSP.
  788. * @param hadc ADC handle
  789. * @retval None
  790. */
  791. __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
  792. {
  793. /* Prevent unused argument(s) compilation warning */
  794. UNUSED(hadc);
  795. /* NOTE : This function should not be modified. When the callback is needed,
  796. function HAL_ADC_MspInit must be implemented in the user file.
  797. */
  798. }
  799. /**
  800. * @brief DeInitialize the ADC MSP.
  801. * @param hadc ADC handle
  802. * @note All ADC instances use the same core clock at RCC level, disabling
  803. * the core clock reset all ADC instances).
  804. * @retval None
  805. */
  806. __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
  807. {
  808. /* Prevent unused argument(s) compilation warning */
  809. UNUSED(hadc);
  810. /* NOTE : This function should not be modified. When the callback is needed,
  811. function HAL_ADC_MspDeInit must be implemented in the user file.
  812. */
  813. }
  814. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  815. /**
  816. * @brief Register a User ADC Callback
  817. * To be used instead of the weak predefined callback
  818. * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
  819. * the configuration information for the specified ADC.
  820. * @param CallbackID ID of the callback to be registered
  821. * This parameter can be one of the following values:
  822. * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  823. * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  824. * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  825. * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
  826. * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
  827. * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
  828. * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  829. * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  830. * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  831. * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  832. * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
  833. * @param pCallback pointer to the Callback function
  834. * @retval HAL status
  835. */
  836. HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
  837. {
  838. HAL_StatusTypeDef status = HAL_OK;
  839. if (pCallback == NULL)
  840. {
  841. /* Update the error code */
  842. hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
  843. return HAL_ERROR;
  844. }
  845. if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
  846. {
  847. switch (CallbackID)
  848. {
  849. case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
  850. hadc->ConvCpltCallback = pCallback;
  851. break;
  852. case HAL_ADC_CONVERSION_HALF_CB_ID :
  853. hadc->ConvHalfCpltCallback = pCallback;
  854. break;
  855. case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
  856. hadc->LevelOutOfWindowCallback = pCallback;
  857. break;
  858. case HAL_ADC_ERROR_CB_ID :
  859. hadc->ErrorCallback = pCallback;
  860. break;
  861. case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
  862. hadc->InjectedConvCpltCallback = pCallback;
  863. break;
  864. case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
  865. hadc->InjectedQueueOverflowCallback = pCallback;
  866. break;
  867. case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
  868. hadc->LevelOutOfWindow2Callback = pCallback;
  869. break;
  870. case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
  871. hadc->LevelOutOfWindow3Callback = pCallback;
  872. break;
  873. case HAL_ADC_END_OF_SAMPLING_CB_ID :
  874. hadc->EndOfSamplingCallback = pCallback;
  875. break;
  876. case HAL_ADC_MSPINIT_CB_ID :
  877. hadc->MspInitCallback = pCallback;
  878. break;
  879. case HAL_ADC_MSPDEINIT_CB_ID :
  880. hadc->MspDeInitCallback = pCallback;
  881. break;
  882. default :
  883. /* Update the error code */
  884. hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
  885. /* Return error status */
  886. status = HAL_ERROR;
  887. break;
  888. }
  889. }
  890. else if (HAL_ADC_STATE_RESET == hadc->State)
  891. {
  892. switch (CallbackID)
  893. {
  894. case HAL_ADC_MSPINIT_CB_ID :
  895. hadc->MspInitCallback = pCallback;
  896. break;
  897. case HAL_ADC_MSPDEINIT_CB_ID :
  898. hadc->MspDeInitCallback = pCallback;
  899. break;
  900. default :
  901. /* Update the error code */
  902. hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
  903. /* Return error status */
  904. status = HAL_ERROR;
  905. break;
  906. }
  907. }
  908. else
  909. {
  910. /* Update the error code */
  911. hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
  912. /* Return error status */
  913. status = HAL_ERROR;
  914. }
  915. return status;
  916. }
  917. /**
  918. * @brief Unregister a ADC Callback
  919. * ADC callback is redirected to the weak predefined callback
  920. * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
  921. * the configuration information for the specified ADC.
  922. * @param CallbackID ID of the callback to be unregistered
  923. * This parameter can be one of the following values:
  924. * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  925. * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  926. * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  927. * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
  928. * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
  929. * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
  930. * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  931. * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  932. * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  933. * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  934. * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
  935. * @retval HAL status
  936. */
  937. HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
  938. {
  939. HAL_StatusTypeDef status = HAL_OK;
  940. if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
  941. {
  942. switch (CallbackID)
  943. {
  944. case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
  945. hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
  946. break;
  947. case HAL_ADC_CONVERSION_HALF_CB_ID :
  948. hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
  949. break;
  950. case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
  951. hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
  952. break;
  953. case HAL_ADC_ERROR_CB_ID :
  954. hadc->ErrorCallback = HAL_ADC_ErrorCallback;
  955. break;
  956. case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
  957. hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
  958. break;
  959. case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
  960. hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
  961. break;
  962. case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
  963. hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
  964. break;
  965. case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
  966. hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
  967. break;
  968. case HAL_ADC_END_OF_SAMPLING_CB_ID :
  969. hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
  970. break;
  971. case HAL_ADC_MSPINIT_CB_ID :
  972. hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
  973. break;
  974. case HAL_ADC_MSPDEINIT_CB_ID :
  975. hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
  976. break;
  977. default :
  978. /* Update the error code */
  979. hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
  980. /* Return error status */
  981. status = HAL_ERROR;
  982. break;
  983. }
  984. }
  985. else if (HAL_ADC_STATE_RESET == hadc->State)
  986. {
  987. switch (CallbackID)
  988. {
  989. case HAL_ADC_MSPINIT_CB_ID :
  990. hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
  991. break;
  992. case HAL_ADC_MSPDEINIT_CB_ID :
  993. hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
  994. break;
  995. default :
  996. /* Update the error code */
  997. hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
  998. /* Return error status */
  999. status = HAL_ERROR;
  1000. break;
  1001. }
  1002. }
  1003. else
  1004. {
  1005. /* Update the error code */
  1006. hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
  1007. /* Return error status */
  1008. status = HAL_ERROR;
  1009. }
  1010. return status;
  1011. }
  1012. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  1013. /**
  1014. * @}
  1015. */
  1016. /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
  1017. * @brief ADC IO operation functions
  1018. *
  1019. @verbatim
  1020. ===============================================================================
  1021. ##### IO operation functions #####
  1022. ===============================================================================
  1023. [..] This section provides functions allowing to:
  1024. (+) Start conversion of regular group.
  1025. (+) Stop conversion of regular group.
  1026. (+) Poll for conversion complete on regular group.
  1027. (+) Poll for conversion event.
  1028. (+) Get result of regular channel conversion.
  1029. (+) Start conversion of regular group and enable interruptions.
  1030. (+) Stop conversion of regular group and disable interruptions.
  1031. (+) Handle ADC interrupt request
  1032. (+) Start conversion of regular group and enable DMA transfer.
  1033. (+) Stop conversion of regular group and disable ADC DMA transfer.
  1034. @endverbatim
  1035. * @{
  1036. */
  1037. /**
  1038. * @brief Enable ADC, start conversion of regular group.
  1039. * @note Interruptions enabled in this function: None.
  1040. * @note Case of multimode enabled (when multimode feature is available):
  1041. * if ADC is Slave, ADC is enabled but conversion is not started,
  1042. * if ADC is master, ADC is enabled and multimode conversion is started.
  1043. * @param hadc ADC handle
  1044. * @retval HAL status
  1045. */
  1046. HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
  1047. {
  1048. HAL_StatusTypeDef tmp_hal_status;
  1049. const ADC_TypeDef *tmpADC_Master;
  1050. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  1051. /* Check the parameters */
  1052. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1053. /* Perform ADC enable and conversion start if no conversion is on going */
  1054. if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
  1055. {
  1056. /* Process locked */
  1057. __HAL_LOCK(hadc);
  1058. /* Enable the ADC peripheral */
  1059. tmp_hal_status = ADC_Enable(hadc);
  1060. /* Start conversion if ADC is effectively enabled */
  1061. if (tmp_hal_status == HAL_OK)
  1062. {
  1063. /* Set ADC state */
  1064. /* - Clear state bitfield related to regular group conversion results */
  1065. /* - Set state bitfield related to regular operation */
  1066. ADC_STATE_CLR_SET(hadc->State,
  1067. HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
  1068. HAL_ADC_STATE_REG_BUSY);
  1069. /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
  1070. - if ADC instance is master or if multimode feature is not available
  1071. - if multimode setting is disabled (ADC instance slave in independent mode) */
  1072. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  1073. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1074. )
  1075. {
  1076. CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  1077. }
  1078. /* Set ADC error code */
  1079. /* Check if a conversion is on going on ADC group injected */
  1080. if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
  1081. {
  1082. /* Reset ADC error code fields related to regular conversions only */
  1083. CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
  1084. }
  1085. else
  1086. {
  1087. /* Reset all ADC error code fields */
  1088. ADC_CLEAR_ERRORCODE(hadc);
  1089. }
  1090. /* Clear ADC group regular conversion flag and overrun flag */
  1091. /* (To ensure of no unknown state from potential previous ADC operations) */
  1092. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
  1093. /* Process unlocked */
  1094. /* Unlock before starting ADC conversions: in case of potential */
  1095. /* interruption, to let the process to ADC IRQ Handler. */
  1096. __HAL_UNLOCK(hadc);
  1097. /* Enable conversion of regular group. */
  1098. /* If software start has been selected, conversion starts immediately. */
  1099. /* If external trigger has been selected, conversion will start at next */
  1100. /* trigger event. */
  1101. /* Case of multimode enabled (when multimode feature is available): */
  1102. /* - if ADC is slave and dual regular conversions are enabled, ADC is */
  1103. /* enabled only (conversion is not started), */
  1104. /* - if ADC is master, ADC is enabled and conversion is started. */
  1105. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  1106. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1107. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
  1108. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
  1109. )
  1110. {
  1111. /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
  1112. if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
  1113. {
  1114. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
  1115. }
  1116. /* Start ADC group regular conversion */
  1117. LL_ADC_REG_StartConversion(hadc->Instance);
  1118. }
  1119. else
  1120. {
  1121. /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
  1122. SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  1123. /* if Master ADC JAUTO bit is set, update Slave State in setting
  1124. HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
  1125. tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
  1126. if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
  1127. {
  1128. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
  1129. }
  1130. }
  1131. }
  1132. else
  1133. {
  1134. /* Process unlocked */
  1135. __HAL_UNLOCK(hadc);
  1136. }
  1137. }
  1138. else
  1139. {
  1140. tmp_hal_status = HAL_BUSY;
  1141. }
  1142. /* Return function status */
  1143. return tmp_hal_status;
  1144. }
  1145. /**
  1146. * @brief Stop ADC conversion of regular group (and injected channels in
  1147. * case of auto_injection mode), disable ADC peripheral.
  1148. * @note: ADC peripheral disable is forcing stop of potential
  1149. * conversion on injected group. If injected group is under use, it
  1150. * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
  1151. * @param hadc ADC handle
  1152. * @retval HAL status.
  1153. */
  1154. HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
  1155. {
  1156. HAL_StatusTypeDef tmp_hal_status;
  1157. /* Check the parameters */
  1158. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1159. /* Process locked */
  1160. __HAL_LOCK(hadc);
  1161. /* 1. Stop potential conversion on going, on ADC groups regular and injected */
  1162. tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
  1163. /* Disable ADC peripheral if conversions are effectively stopped */
  1164. if (tmp_hal_status == HAL_OK)
  1165. {
  1166. /* 2. Disable the ADC peripheral */
  1167. tmp_hal_status = ADC_Disable(hadc);
  1168. /* Check if ADC is effectively disabled */
  1169. if (tmp_hal_status == HAL_OK)
  1170. {
  1171. /* Set ADC state */
  1172. ADC_STATE_CLR_SET(hadc->State,
  1173. HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  1174. HAL_ADC_STATE_READY);
  1175. }
  1176. }
  1177. /* Process unlocked */
  1178. __HAL_UNLOCK(hadc);
  1179. /* Return function status */
  1180. return tmp_hal_status;
  1181. }
  1182. /**
  1183. * @brief Wait for regular group conversion to be completed.
  1184. * @note ADC conversion flags EOS (end of sequence) and EOC (end of
  1185. * conversion) are cleared by this function, with an exception:
  1186. * if low power feature "LowPowerAutoWait" is enabled, flags are
  1187. * not cleared to not interfere with this feature until data register
  1188. * is read using function HAL_ADC_GetValue().
  1189. * @note This function cannot be used in a particular setup: ADC configured
  1190. * in DMA mode and polling for end of each conversion (ADC init
  1191. * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
  1192. * In this case, DMA resets the flag EOC and polling cannot be
  1193. * performed on each conversion. Nevertheless, polling can still
  1194. * be performed on the complete sequence (ADC init
  1195. * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
  1196. * @param hadc ADC handle
  1197. * @param Timeout Timeout value in millisecond.
  1198. * @retval HAL status
  1199. */
  1200. HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
  1201. {
  1202. uint32_t tickstart;
  1203. uint32_t tmp_Flag_End;
  1204. uint32_t tmp_cfgr;
  1205. const ADC_TypeDef *tmpADC_Master;
  1206. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  1207. /* Check the parameters */
  1208. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1209. /* If end of conversion selected to end of sequence conversions */
  1210. if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
  1211. {
  1212. tmp_Flag_End = ADC_FLAG_EOS;
  1213. }
  1214. /* If end of conversion selected to end of unitary conversion */
  1215. else /* ADC_EOC_SINGLE_CONV */
  1216. {
  1217. /* Verification that ADC configuration is compliant with polling for */
  1218. /* each conversion: */
  1219. /* Particular case is ADC configured in DMA mode and ADC sequencer with */
  1220. /* several ranks and polling for end of each conversion. */
  1221. /* For code simplicity sake, this particular case is generalized to */
  1222. /* ADC configured in DMA mode and and polling for end of each conversion. */
  1223. if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1224. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
  1225. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
  1226. )
  1227. {
  1228. /* Check DMNGT bit in handle ADC CFGR register */
  1229. if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != 0UL)
  1230. {
  1231. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1232. return HAL_ERROR;
  1233. }
  1234. else
  1235. {
  1236. tmp_Flag_End = (ADC_FLAG_EOC);
  1237. }
  1238. }
  1239. else
  1240. {
  1241. /* Check ADC DMA mode in multimode on ADC group regular */
  1242. if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
  1243. {
  1244. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1245. return HAL_ERROR;
  1246. }
  1247. else
  1248. {
  1249. tmp_Flag_End = (ADC_FLAG_EOC);
  1250. }
  1251. }
  1252. }
  1253. /* Get tick count */
  1254. tickstart = HAL_GetTick();
  1255. /* Wait until End of unitary conversion or sequence conversions flag is raised */
  1256. while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
  1257. {
  1258. /* Check if timeout is disabled (set to infinite wait) */
  1259. if (Timeout != HAL_MAX_DELAY)
  1260. {
  1261. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
  1262. {
  1263. /* Update ADC state machine to timeout */
  1264. SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
  1265. /* Process unlocked */
  1266. __HAL_UNLOCK(hadc);
  1267. return HAL_TIMEOUT;
  1268. }
  1269. }
  1270. }
  1271. /* Update ADC state machine */
  1272. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
  1273. /* Determine whether any further conversion upcoming on group regular */
  1274. /* by external trigger, continuous mode or scan sequence on going. */
  1275. if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
  1276. && (hadc->Init.ContinuousConvMode == DISABLE)
  1277. )
  1278. {
  1279. /* Check whether end of sequence is reached */
  1280. if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
  1281. {
  1282. /* Set ADC state */
  1283. CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
  1284. if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
  1285. {
  1286. SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  1287. }
  1288. }
  1289. }
  1290. /* Get relevant register CFGR in ADC instance of ADC master or slave */
  1291. /* in function of multimode state (for devices with multimode */
  1292. /* available). */
  1293. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  1294. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1295. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
  1296. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
  1297. )
  1298. {
  1299. /* Retrieve handle ADC CFGR register */
  1300. tmp_cfgr = READ_REG(hadc->Instance->CFGR);
  1301. }
  1302. else
  1303. {
  1304. /* Retrieve Master ADC CFGR register */
  1305. tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
  1306. tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
  1307. }
  1308. /* Clear polled flag */
  1309. if (tmp_Flag_End == ADC_FLAG_EOS)
  1310. {
  1311. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
  1312. }
  1313. else
  1314. {
  1315. /* Clear end of conversion EOC flag of regular group if low power feature */
  1316. /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
  1317. /* until data register is read using function HAL_ADC_GetValue(). */
  1318. if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
  1319. {
  1320. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
  1321. }
  1322. }
  1323. /* Return function status */
  1324. return HAL_OK;
  1325. }
  1326. /**
  1327. * @brief Poll for ADC event.
  1328. * @param hadc ADC handle
  1329. * @param EventType the ADC event type.
  1330. * This parameter can be one of the following values:
  1331. * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
  1332. * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
  1333. * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
  1334. * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
  1335. * @arg @ref ADC_OVR_EVENT ADC Overrun event
  1336. * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
  1337. * @param Timeout Timeout value in millisecond.
  1338. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
  1339. * Indeed, the latter is reset only if hadc->Init.Overrun field is set
  1340. * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
  1341. * by a new converted data as soon as OVR is cleared.
  1342. * To reset OVR flag once the preserved data is retrieved, the user can resort
  1343. * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
  1344. * @retval HAL status
  1345. */
  1346. HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
  1347. {
  1348. uint32_t tickstart;
  1349. /* Check the parameters */
  1350. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1351. assert_param(IS_ADC_EVENT_TYPE(EventType));
  1352. /* Get tick count */
  1353. tickstart = HAL_GetTick();
  1354. /* Check selected event flag */
  1355. while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
  1356. {
  1357. /* Check if timeout is disabled (set to infinite wait) */
  1358. if (Timeout != HAL_MAX_DELAY)
  1359. {
  1360. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
  1361. {
  1362. /* Update ADC state machine to timeout */
  1363. SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
  1364. /* Process unlocked */
  1365. __HAL_UNLOCK(hadc);
  1366. return HAL_TIMEOUT;
  1367. }
  1368. }
  1369. }
  1370. switch (EventType)
  1371. {
  1372. /* End Of Sampling event */
  1373. case ADC_EOSMP_EVENT:
  1374. /* Set ADC state */
  1375. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
  1376. /* Clear the End Of Sampling flag */
  1377. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
  1378. break;
  1379. /* Analog watchdog (level out of window) event */
  1380. /* Note: In case of several analog watchdog enabled, if needed to know */
  1381. /* which one triggered and on which ADCx, test ADC state of analog watchdog */
  1382. /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
  1383. /* For example: */
  1384. /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
  1385. /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
  1386. /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
  1387. /* Check analog watchdog 1 flag */
  1388. case ADC_AWD_EVENT:
  1389. /* Set ADC state */
  1390. SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
  1391. /* Clear ADC analog watchdog flag */
  1392. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
  1393. break;
  1394. /* Check analog watchdog 2 flag */
  1395. case ADC_AWD2_EVENT:
  1396. /* Set ADC state */
  1397. SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
  1398. /* Clear ADC analog watchdog flag */
  1399. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
  1400. break;
  1401. /* Check analog watchdog 3 flag */
  1402. case ADC_AWD3_EVENT:
  1403. /* Set ADC state */
  1404. SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
  1405. /* Clear ADC analog watchdog flag */
  1406. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
  1407. break;
  1408. /* Injected context queue overflow event */
  1409. case ADC_JQOVF_EVENT:
  1410. /* Set ADC state */
  1411. SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
  1412. /* Set ADC error code to Injected context queue overflow */
  1413. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
  1414. /* Clear ADC Injected context queue overflow flag */
  1415. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
  1416. break;
  1417. /* Overrun event */
  1418. default: /* Case ADC_OVR_EVENT */
  1419. /* If overrun is set to overwrite previous data, overrun event is not */
  1420. /* considered as an error. */
  1421. /* (cf ref manual "Managing conversions without using the DMA and without */
  1422. /* overrun ") */
  1423. if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
  1424. {
  1425. /* Set ADC state */
  1426. SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
  1427. /* Set ADC error code to overrun */
  1428. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
  1429. }
  1430. else
  1431. {
  1432. /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
  1433. otherwise, data register is potentially overwritten by new converted data as soon
  1434. as OVR is cleared. */
  1435. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
  1436. }
  1437. break;
  1438. }
  1439. /* Return function status */
  1440. return HAL_OK;
  1441. }
  1442. /**
  1443. * @brief Enable ADC, start conversion of regular group with interruption.
  1444. * @note Interruptions enabled in this function according to initialization
  1445. * setting : EOC (end of conversion), EOS (end of sequence),
  1446. * OVR overrun.
  1447. * Each of these interruptions has its dedicated callback function.
  1448. * @note Case of multimode enabled (when multimode feature is available):
  1449. * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
  1450. * ADC Master.
  1451. * For ADC Slave, ADC is enabled only (conversion is not started).
  1452. * For ADC Master, ADC is enabled and multimode conversion is started.
  1453. * @note To guarantee a proper reset of all interruptions once all the needed
  1454. * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
  1455. * a correct stop of the IT-based conversions.
  1456. * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
  1457. * interruption. If required (e.g. in case of oversampling with trigger
  1458. * mode), the user must:
  1459. * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
  1460. * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
  1461. * before calling HAL_ADC_Start_IT().
  1462. * @param hadc ADC handle
  1463. * @retval HAL status
  1464. */
  1465. HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
  1466. {
  1467. HAL_StatusTypeDef tmp_hal_status;
  1468. const ADC_TypeDef *tmpADC_Master;
  1469. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  1470. /* Check the parameters */
  1471. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1472. /* Perform ADC enable and conversion start if no conversion is on going */
  1473. if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
  1474. {
  1475. /* Process locked */
  1476. __HAL_LOCK(hadc);
  1477. /* Enable the ADC peripheral */
  1478. tmp_hal_status = ADC_Enable(hadc);
  1479. /* Start conversion if ADC is effectively enabled */
  1480. if (tmp_hal_status == HAL_OK)
  1481. {
  1482. /* Set ADC state */
  1483. /* - Clear state bitfield related to regular group conversion results */
  1484. /* - Set state bitfield related to regular operation */
  1485. ADC_STATE_CLR_SET(hadc->State,
  1486. HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
  1487. HAL_ADC_STATE_REG_BUSY);
  1488. /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
  1489. - if ADC instance is master or if multimode feature is not available
  1490. - if multimode setting is disabled (ADC instance slave in independent mode) */
  1491. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  1492. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1493. )
  1494. {
  1495. CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  1496. }
  1497. /* Set ADC error code */
  1498. /* Check if a conversion is on going on ADC group injected */
  1499. if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
  1500. {
  1501. /* Reset ADC error code fields related to regular conversions only */
  1502. CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
  1503. }
  1504. else
  1505. {
  1506. /* Reset all ADC error code fields */
  1507. ADC_CLEAR_ERRORCODE(hadc);
  1508. }
  1509. /* Clear ADC group regular conversion flag and overrun flag */
  1510. /* (To ensure of no unknown state from potential previous ADC operations) */
  1511. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
  1512. /* Process unlocked */
  1513. /* Unlock before starting ADC conversions: in case of potential */
  1514. /* interruption, to let the process to ADC IRQ Handler. */
  1515. __HAL_UNLOCK(hadc);
  1516. /* Disable all interruptions before enabling the desired ones */
  1517. __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
  1518. /* Enable ADC end of conversion interrupt */
  1519. switch (hadc->Init.EOCSelection)
  1520. {
  1521. case ADC_EOC_SEQ_CONV:
  1522. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
  1523. break;
  1524. /* case ADC_EOC_SINGLE_CONV */
  1525. default:
  1526. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
  1527. break;
  1528. }
  1529. /* Enable ADC overrun interrupt */
  1530. /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
  1531. ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
  1532. behavior and no CPU time is lost for a non-processed interruption */
  1533. if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
  1534. {
  1535. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
  1536. }
  1537. /* Enable conversion of regular group. */
  1538. /* If software start has been selected, conversion starts immediately. */
  1539. /* If external trigger has been selected, conversion will start at next */
  1540. /* trigger event. */
  1541. /* Case of multimode enabled (when multimode feature is available): */
  1542. /* - if ADC is slave and dual regular conversions are enabled, ADC is */
  1543. /* enabled only (conversion is not started), */
  1544. /* - if ADC is master, ADC is enabled and conversion is started. */
  1545. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  1546. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1547. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
  1548. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
  1549. )
  1550. {
  1551. /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
  1552. if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
  1553. {
  1554. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
  1555. /* Enable as well injected interruptions in case
  1556. HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
  1557. allows to start regular and injected conversions when JAUTO is
  1558. set with a single call to HAL_ADC_Start_IT() */
  1559. switch (hadc->Init.EOCSelection)
  1560. {
  1561. case ADC_EOC_SEQ_CONV:
  1562. __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
  1563. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
  1564. break;
  1565. /* case ADC_EOC_SINGLE_CONV */
  1566. default:
  1567. __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
  1568. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
  1569. break;
  1570. }
  1571. }
  1572. /* Start ADC group regular conversion */
  1573. LL_ADC_REG_StartConversion(hadc->Instance);
  1574. }
  1575. else
  1576. {
  1577. /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
  1578. SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  1579. /* if Master ADC JAUTO bit is set, Slave injected interruptions
  1580. are enabled nevertheless (for same reason as above) */
  1581. tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
  1582. if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
  1583. {
  1584. /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
  1585. and in resetting HAL_ADC_STATE_INJ_EOC bit */
  1586. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
  1587. /* Next, set Slave injected interruptions */
  1588. switch (hadc->Init.EOCSelection)
  1589. {
  1590. case ADC_EOC_SEQ_CONV:
  1591. __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
  1592. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
  1593. break;
  1594. /* case ADC_EOC_SINGLE_CONV */
  1595. default:
  1596. __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
  1597. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
  1598. break;
  1599. }
  1600. }
  1601. }
  1602. }
  1603. else
  1604. {
  1605. /* Process unlocked */
  1606. __HAL_UNLOCK(hadc);
  1607. }
  1608. }
  1609. else
  1610. {
  1611. tmp_hal_status = HAL_BUSY;
  1612. }
  1613. /* Return function status */
  1614. return tmp_hal_status;
  1615. }
  1616. /**
  1617. * @brief Stop ADC conversion of regular group (and injected group in
  1618. * case of auto_injection mode), disable interrution of
  1619. * end-of-conversion, disable ADC peripheral.
  1620. * @param hadc ADC handle
  1621. * @retval HAL status.
  1622. */
  1623. HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
  1624. {
  1625. HAL_StatusTypeDef tmp_hal_status;
  1626. /* Check the parameters */
  1627. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1628. /* Process locked */
  1629. __HAL_LOCK(hadc);
  1630. /* 1. Stop potential conversion on going, on ADC groups regular and injected */
  1631. tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
  1632. /* Disable ADC peripheral if conversions are effectively stopped */
  1633. if (tmp_hal_status == HAL_OK)
  1634. {
  1635. /* Disable ADC end of conversion interrupt for regular group */
  1636. /* Disable ADC overrun interrupt */
  1637. __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
  1638. /* 2. Disable the ADC peripheral */
  1639. tmp_hal_status = ADC_Disable(hadc);
  1640. /* Check if ADC is effectively disabled */
  1641. if (tmp_hal_status == HAL_OK)
  1642. {
  1643. /* Set ADC state */
  1644. ADC_STATE_CLR_SET(hadc->State,
  1645. HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  1646. HAL_ADC_STATE_READY);
  1647. }
  1648. }
  1649. /* Process unlocked */
  1650. __HAL_UNLOCK(hadc);
  1651. /* Return function status */
  1652. return tmp_hal_status;
  1653. }
  1654. /**
  1655. * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
  1656. * @note Interruptions enabled in this function:
  1657. * overrun (if applicable), DMA half transfer, DMA transfer complete.
  1658. * Each of these interruptions has its dedicated callback function.
  1659. * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
  1660. * is designed for single-ADC mode only. For multimode, the dedicated
  1661. * HAL_ADCEx_MultiModeStart_DMA() function must be used.
  1662. * @param hadc ADC handle
  1663. * @param pData Destination Buffer address.
  1664. * @param Length Number of data to be transferred from ADC peripheral to memory
  1665. * @retval HAL status.
  1666. */
  1667. HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
  1668. {
  1669. HAL_StatusTypeDef tmp_hal_status;
  1670. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  1671. /* Check the parameters */
  1672. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1673. /* Perform ADC enable and conversion start if no conversion is on going */
  1674. if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
  1675. {
  1676. /* Process locked */
  1677. __HAL_LOCK(hadc);
  1678. /* Ensure that multimode regular conversions are not enabled. */
  1679. /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
  1680. if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1681. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
  1682. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
  1683. )
  1684. {
  1685. /* Enable the ADC peripheral */
  1686. tmp_hal_status = ADC_Enable(hadc);
  1687. /* Start conversion if ADC is effectively enabled */
  1688. if (tmp_hal_status == HAL_OK)
  1689. {
  1690. /* Set ADC state */
  1691. /* - Clear state bitfield related to regular group conversion results */
  1692. /* - Set state bitfield related to regular operation */
  1693. ADC_STATE_CLR_SET(hadc->State,
  1694. HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
  1695. HAL_ADC_STATE_REG_BUSY);
  1696. /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
  1697. - if ADC instance is master or if multimode feature is not available
  1698. - if multimode setting is disabled (ADC instance slave in independent mode) */
  1699. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  1700. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1701. )
  1702. {
  1703. CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  1704. }
  1705. /* Check if a conversion is on going on ADC group injected */
  1706. if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
  1707. {
  1708. /* Reset ADC error code fields related to regular conversions only */
  1709. CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
  1710. }
  1711. else
  1712. {
  1713. /* Reset all ADC error code fields */
  1714. ADC_CLEAR_ERRORCODE(hadc);
  1715. }
  1716. /* Set the DMA transfer complete callback */
  1717. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  1718. /* Set the DMA half transfer complete callback */
  1719. hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
  1720. /* Set the DMA error callback */
  1721. hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
  1722. /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
  1723. /* ADC start (in case of SW start): */
  1724. /* Clear regular group conversion flag and overrun flag */
  1725. /* (To ensure of no unknown state from potential previous ADC */
  1726. /* operations) */
  1727. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
  1728. /* Process unlocked */
  1729. /* Unlock before starting ADC conversions: in case of potential */
  1730. /* interruption, to let the process to ADC IRQ Handler. */
  1731. __HAL_UNLOCK(hadc);
  1732. /* With DMA, overrun event is always considered as an error even if
  1733. hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
  1734. ADC_IT_OVR is enabled. */
  1735. __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
  1736. /* Enable ADC DMA mode*/
  1737. LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
  1738. /* Start the DMA channel */
  1739. tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  1740. /* Enable conversion of regular group. */
  1741. /* If software start has been selected, conversion starts immediately. */
  1742. /* If external trigger has been selected, conversion will start at next */
  1743. /* trigger event. */
  1744. /* Start ADC group regular conversion */
  1745. LL_ADC_REG_StartConversion(hadc->Instance);
  1746. }
  1747. else
  1748. {
  1749. /* Process unlocked */
  1750. __HAL_UNLOCK(hadc);
  1751. }
  1752. }
  1753. else
  1754. {
  1755. tmp_hal_status = HAL_ERROR;
  1756. /* Process unlocked */
  1757. __HAL_UNLOCK(hadc);
  1758. }
  1759. }
  1760. else
  1761. {
  1762. tmp_hal_status = HAL_BUSY;
  1763. }
  1764. /* Return function status */
  1765. return tmp_hal_status;
  1766. }
  1767. /**
  1768. * @brief Stop ADC conversion of regular group (and injected group in
  1769. * case of auto_injection mode), disable ADC DMA transfer, disable
  1770. * ADC peripheral.
  1771. * @note: ADC peripheral disable is forcing stop of potential
  1772. * conversion on ADC group injected. If ADC group injected is under use, it
  1773. * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
  1774. * @note Case of multimode enabled (when multimode feature is available):
  1775. * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
  1776. * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
  1777. * @param hadc ADC handle
  1778. * @retval HAL status.
  1779. */
  1780. HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
  1781. {
  1782. HAL_StatusTypeDef tmp_hal_status;
  1783. /* Check the parameters */
  1784. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1785. /* Process locked */
  1786. __HAL_LOCK(hadc);
  1787. /* 1. Stop potential ADC group regular conversion on going */
  1788. tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
  1789. /* Disable ADC peripheral if conversions are effectively stopped */
  1790. if (tmp_hal_status == HAL_OK)
  1791. {
  1792. /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
  1793. MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
  1794. /* Disable the DMA channel (in case of DMA in circular mode or stop */
  1795. /* while DMA transfer is on going) */
  1796. if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
  1797. {
  1798. tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
  1799. /* Check if DMA channel effectively disabled */
  1800. if (tmp_hal_status != HAL_OK)
  1801. {
  1802. /* Update ADC state machine to error */
  1803. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
  1804. }
  1805. }
  1806. /* Disable ADC overrun interrupt */
  1807. __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
  1808. /* 2. Disable the ADC peripheral */
  1809. /* Update "tmp_hal_status" only if DMA channel disabling passed, */
  1810. /* to keep in memory a potential failing status. */
  1811. if (tmp_hal_status == HAL_OK)
  1812. {
  1813. tmp_hal_status = ADC_Disable(hadc);
  1814. }
  1815. else
  1816. {
  1817. (void)ADC_Disable(hadc);
  1818. }
  1819. /* Check if ADC is effectively disabled */
  1820. if (tmp_hal_status == HAL_OK)
  1821. {
  1822. /* Set ADC state */
  1823. ADC_STATE_CLR_SET(hadc->State,
  1824. HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  1825. HAL_ADC_STATE_READY);
  1826. }
  1827. }
  1828. /* Process unlocked */
  1829. __HAL_UNLOCK(hadc);
  1830. /* Return function status */
  1831. return tmp_hal_status;
  1832. }
  1833. /**
  1834. * @brief Get ADC regular group conversion result.
  1835. * @note Reading register DR automatically clears ADC flag EOC
  1836. * (ADC group regular end of unitary conversion).
  1837. * @note This function does not clear ADC flag EOS
  1838. * (ADC group regular end of sequence conversion).
  1839. * Occurrence of flag EOS rising:
  1840. * - If sequencer is composed of 1 rank, flag EOS is equivalent
  1841. * to flag EOC.
  1842. * - If sequencer is composed of several ranks, during the scan
  1843. * sequence flag EOC only is raised, at the end of the scan sequence
  1844. * both flags EOC and EOS are raised.
  1845. * To clear this flag, either use function:
  1846. * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
  1847. * model polling: @ref HAL_ADC_PollForConversion()
  1848. * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
  1849. * @param hadc ADC handle
  1850. * @retval ADC group regular conversion data
  1851. */
  1852. uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
  1853. {
  1854. /* Check the parameters */
  1855. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1856. /* Note: EOC flag is not cleared here by software because automatically */
  1857. /* cleared by hardware when reading register DR. */
  1858. /* Return ADC converted value */
  1859. return hadc->Instance->DR;
  1860. }
  1861. /**
  1862. * @brief Handle ADC interrupt request.
  1863. * @param hadc ADC handle
  1864. * @retval None
  1865. */
  1866. void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
  1867. {
  1868. uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
  1869. uint32_t tmp_isr = hadc->Instance->ISR;
  1870. uint32_t tmp_ier = hadc->Instance->IER;
  1871. uint32_t tmp_adc_inj_is_trigger_source_sw_start;
  1872. uint32_t tmp_adc_reg_is_trigger_source_sw_start;
  1873. uint32_t tmp_cfgr;
  1874. const ADC_TypeDef *tmpADC_Master;
  1875. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  1876. /* Check the parameters */
  1877. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1878. assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
  1879. /* ========== Check End of Sampling flag for ADC group regular ========== */
  1880. if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
  1881. {
  1882. /* Update state machine on end of sampling status if not in error state */
  1883. if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
  1884. {
  1885. /* Set ADC state */
  1886. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
  1887. }
  1888. /* End Of Sampling callback */
  1889. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  1890. hadc->EndOfSamplingCallback(hadc);
  1891. #else
  1892. HAL_ADCEx_EndOfSamplingCallback(hadc);
  1893. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  1894. /* Clear regular group conversion flag */
  1895. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
  1896. }
  1897. /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
  1898. if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
  1899. (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
  1900. {
  1901. /* Update state machine on conversion status if not in error state */
  1902. if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
  1903. {
  1904. /* Set ADC state */
  1905. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
  1906. }
  1907. /* Determine whether any further conversion upcoming on group regular */
  1908. /* by external trigger, continuous mode or scan sequence on going */
  1909. /* to disable interruption. */
  1910. if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
  1911. {
  1912. /* Get relevant register CFGR in ADC instance of ADC master or slave */
  1913. /* in function of multimode state (for devices with multimode */
  1914. /* available). */
  1915. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  1916. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1917. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
  1918. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
  1919. )
  1920. {
  1921. /* check CONT bit directly in handle ADC CFGR register */
  1922. tmp_cfgr = READ_REG(hadc->Instance->CFGR);
  1923. }
  1924. else
  1925. {
  1926. /* else need to check Master ADC CONT bit */
  1927. tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
  1928. tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
  1929. }
  1930. /* Carry on if continuous mode is disabled */
  1931. if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
  1932. {
  1933. /* If End of Sequence is reached, disable interrupts */
  1934. if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
  1935. {
  1936. /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
  1937. /* ADSTART==0 (no conversion on going) */
  1938. if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
  1939. {
  1940. /* Disable ADC end of sequence conversion interrupt */
  1941. /* Note: Overrun interrupt was enabled with EOC interrupt in */
  1942. /* HAL_Start_IT(), but is not disabled here because can be used */
  1943. /* by overrun IRQ process below. */
  1944. __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
  1945. /* Set ADC state */
  1946. CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
  1947. if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
  1948. {
  1949. SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  1950. }
  1951. }
  1952. else
  1953. {
  1954. /* Change ADC state to error state */
  1955. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  1956. /* Set ADC error code to ADC peripheral internal error */
  1957. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  1958. }
  1959. }
  1960. }
  1961. }
  1962. /* Conversion complete callback */
  1963. /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
  1964. /* to determine if conversion has been triggered from EOC or EOS, */
  1965. /* possibility to use: */
  1966. /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
  1967. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  1968. hadc->ConvCpltCallback(hadc);
  1969. #else
  1970. HAL_ADC_ConvCpltCallback(hadc);
  1971. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  1972. /* Clear regular group conversion flag */
  1973. /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
  1974. /* conversion flags clear induces the release of the preserved data.*/
  1975. /* Therefore, if the preserved data value is needed, it must be */
  1976. /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
  1977. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
  1978. }
  1979. /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
  1980. if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
  1981. (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
  1982. {
  1983. /* Update state machine on conversion status if not in error state */
  1984. if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
  1985. {
  1986. /* Set ADC state */
  1987. SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
  1988. }
  1989. /* Retrieve ADC configuration */
  1990. tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
  1991. tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
  1992. /* Get relevant register CFGR in ADC instance of ADC master or slave */
  1993. /* in function of multimode state (for devices with multimode */
  1994. /* available). */
  1995. if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  1996. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  1997. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
  1998. || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
  1999. )
  2000. {
  2001. tmp_cfgr = READ_REG(hadc->Instance->CFGR);
  2002. }
  2003. else
  2004. {
  2005. tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
  2006. tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
  2007. }
  2008. /* Disable interruption if no further conversion upcoming by injected */
  2009. /* external trigger or by automatic injected conversion with regular */
  2010. /* group having no further conversion upcoming (same conditions as */
  2011. /* regular group interruption disabling above), */
  2012. /* and if injected scan sequence is completed. */
  2013. if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
  2014. ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
  2015. ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
  2016. (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
  2017. {
  2018. /* If End of Sequence is reached, disable interrupts */
  2019. if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
  2020. {
  2021. /* Particular case if injected contexts queue is enabled: */
  2022. /* when the last context has been fully processed, JSQR is reset */
  2023. /* by the hardware. Even if no injected conversion is planned to come */
  2024. /* (queue empty, triggers are ignored), it can start again */
  2025. /* immediately after setting a new context (JADSTART is still set). */
  2026. /* Therefore, state of HAL ADC injected group is kept to busy. */
  2027. if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
  2028. {
  2029. /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
  2030. /* JADSTART==0 (no conversion on going) */
  2031. if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
  2032. {
  2033. /* Disable ADC end of sequence conversion interrupt */
  2034. __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
  2035. /* Set ADC state */
  2036. CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
  2037. if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
  2038. {
  2039. SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  2040. }
  2041. }
  2042. else
  2043. {
  2044. /* Update ADC state machine to error */
  2045. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2046. /* Set ADC error code to ADC peripheral internal error */
  2047. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2048. }
  2049. }
  2050. }
  2051. }
  2052. /* Injected Conversion complete callback */
  2053. /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
  2054. if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
  2055. if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
  2056. interruption has been triggered by end of conversion or end of
  2057. sequence. */
  2058. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  2059. hadc->InjectedConvCpltCallback(hadc);
  2060. #else
  2061. HAL_ADCEx_InjectedConvCpltCallback(hadc);
  2062. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  2063. /* Clear injected group conversion flag */
  2064. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
  2065. }
  2066. /* ========== Check Analog watchdog 1 flag ========== */
  2067. if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
  2068. {
  2069. /* Set ADC state */
  2070. SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
  2071. /* Level out of window 1 callback */
  2072. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  2073. hadc->LevelOutOfWindowCallback(hadc);
  2074. #else
  2075. HAL_ADC_LevelOutOfWindowCallback(hadc);
  2076. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  2077. /* Clear ADC analog watchdog flag */
  2078. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
  2079. }
  2080. /* ========== Check analog watchdog 2 flag ========== */
  2081. if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
  2082. {
  2083. /* Set ADC state */
  2084. SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
  2085. /* Level out of window 2 callback */
  2086. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  2087. hadc->LevelOutOfWindow2Callback(hadc);
  2088. #else
  2089. HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
  2090. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  2091. /* Clear ADC analog watchdog flag */
  2092. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
  2093. }
  2094. /* ========== Check analog watchdog 3 flag ========== */
  2095. if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
  2096. {
  2097. /* Set ADC state */
  2098. SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
  2099. /* Level out of window 3 callback */
  2100. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  2101. hadc->LevelOutOfWindow3Callback(hadc);
  2102. #else
  2103. HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
  2104. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  2105. /* Clear ADC analog watchdog flag */
  2106. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
  2107. }
  2108. /* ========== Check Overrun flag ========== */
  2109. if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
  2110. {
  2111. /* If overrun is set to overwrite previous data (default setting), */
  2112. /* overrun event is not considered as an error. */
  2113. /* (cf ref manual "Managing conversions without using the DMA and without */
  2114. /* overrun ") */
  2115. /* Exception for usage with DMA overrun event always considered as an */
  2116. /* error. */
  2117. if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
  2118. {
  2119. overrun_error = 1UL;
  2120. }
  2121. else
  2122. {
  2123. /* Check DMA configuration */
  2124. if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
  2125. {
  2126. /* Multimode (when feature is available) is enabled,
  2127. Common Control Register MDMA bits must be checked. */
  2128. if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
  2129. {
  2130. overrun_error = 1UL;
  2131. }
  2132. }
  2133. else
  2134. {
  2135. /* Multimode not set or feature not available or ADC independent */
  2136. if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL)
  2137. {
  2138. overrun_error = 1UL;
  2139. }
  2140. }
  2141. }
  2142. if (overrun_error == 1UL)
  2143. {
  2144. /* Change ADC state to error state */
  2145. SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
  2146. /* Set ADC error code to overrun */
  2147. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
  2148. /* Error callback */
  2149. /* Note: In case of overrun, ADC conversion data is preserved until */
  2150. /* flag OVR is reset. */
  2151. /* Therefore, old ADC conversion data can be retrieved in */
  2152. /* function "HAL_ADC_ErrorCallback()". */
  2153. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  2154. hadc->ErrorCallback(hadc);
  2155. #else
  2156. HAL_ADC_ErrorCallback(hadc);
  2157. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  2158. }
  2159. /* Clear ADC overrun flag */
  2160. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
  2161. }
  2162. /* ========== Check Injected context queue overflow flag ========== */
  2163. if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
  2164. {
  2165. /* Change ADC state to overrun state */
  2166. SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
  2167. /* Set ADC error code to Injected context queue overflow */
  2168. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
  2169. /* Clear the Injected context queue overflow flag */
  2170. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
  2171. /* Injected context queue overflow callback */
  2172. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  2173. hadc->InjectedQueueOverflowCallback(hadc);
  2174. #else
  2175. HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
  2176. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  2177. }
  2178. }
  2179. /**
  2180. * @brief Conversion complete callback in non-blocking mode.
  2181. * @param hadc ADC handle
  2182. * @retval None
  2183. */
  2184. __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
  2185. {
  2186. /* Prevent unused argument(s) compilation warning */
  2187. UNUSED(hadc);
  2188. /* NOTE : This function should not be modified. When the callback is needed,
  2189. function HAL_ADC_ConvCpltCallback must be implemented in the user file.
  2190. */
  2191. }
  2192. /**
  2193. * @brief Conversion DMA half-transfer callback in non-blocking mode.
  2194. * @param hadc ADC handle
  2195. * @retval None
  2196. */
  2197. __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
  2198. {
  2199. /* Prevent unused argument(s) compilation warning */
  2200. UNUSED(hadc);
  2201. /* NOTE : This function should not be modified. When the callback is needed,
  2202. function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
  2203. */
  2204. }
  2205. /**
  2206. * @brief Analog watchdog 1 callback in non-blocking mode.
  2207. * @param hadc ADC handle
  2208. * @retval None
  2209. */
  2210. __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
  2211. {
  2212. /* Prevent unused argument(s) compilation warning */
  2213. UNUSED(hadc);
  2214. /* NOTE : This function should not be modified. When the callback is needed,
  2215. function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
  2216. */
  2217. }
  2218. /**
  2219. * @brief ADC error callback in non-blocking mode
  2220. * (ADC conversion with interruption or transfer by DMA).
  2221. * @note In case of error due to overrun when using ADC with DMA transfer
  2222. * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
  2223. * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
  2224. * - If needed, restart a new ADC conversion using function
  2225. * "HAL_ADC_Start_DMA()"
  2226. * (this function is also clearing overrun flag)
  2227. * @param hadc ADC handle
  2228. * @retval None
  2229. */
  2230. __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
  2231. {
  2232. /* Prevent unused argument(s) compilation warning */
  2233. UNUSED(hadc);
  2234. /* NOTE : This function should not be modified. When the callback is needed,
  2235. function HAL_ADC_ErrorCallback must be implemented in the user file.
  2236. */
  2237. }
  2238. /**
  2239. * @}
  2240. */
  2241. /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
  2242. * @brief Peripheral Control functions
  2243. *
  2244. @verbatim
  2245. ===============================================================================
  2246. ##### Peripheral Control functions #####
  2247. ===============================================================================
  2248. [..] This section provides functions allowing to:
  2249. (+) Configure channels on regular group
  2250. (+) Configure the analog watchdog
  2251. @endverbatim
  2252. * @{
  2253. */
  2254. /**
  2255. * @brief Configure a channel to be assigned to ADC group regular.
  2256. * @note In case of usage of internal measurement channels:
  2257. * Vbat/VrefInt/TempSensor.
  2258. * These internal paths can be disabled using function
  2259. * HAL_ADC_DeInit().
  2260. * @note Possibility to update parameters on the fly:
  2261. * This function initializes channel into ADC group regular,
  2262. * following calls to this function can be used to reconfigure
  2263. * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
  2264. * without resetting the ADC.
  2265. * The setting of these parameters is conditioned to ADC state:
  2266. * Refer to comments of structure "ADC_ChannelConfTypeDef".
  2267. * @param hadc ADC handle
  2268. * @param sConfig Structure of ADC channel assigned to ADC group regular.
  2269. * @retval HAL status
  2270. */
  2271. HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
  2272. {
  2273. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  2274. uint32_t tmpOffsetShifted;
  2275. uint32_t tmp_config_internal_channel;
  2276. __IO uint32_t wait_loop_index = 0;
  2277. uint32_t tmp_adc_is_conversion_on_going_regular;
  2278. uint32_t tmp_adc_is_conversion_on_going_injected;
  2279. /* Check the parameters */
  2280. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  2281. assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  2282. assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  2283. assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
  2284. assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
  2285. /* Check offset range according to oversampling setting */
  2286. if (hadc->Init.OversamplingMode == ENABLE)
  2287. {
  2288. assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset/(hadc->Init.Oversampling.Ratio+1U)));
  2289. }
  2290. else
  2291. {
  2292. assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
  2293. }
  2294. /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
  2295. ignored (considered as reset) */
  2296. assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
  2297. /* Verification of channel number */
  2298. if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
  2299. {
  2300. assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  2301. }
  2302. else
  2303. {
  2304. if (hadc->Instance == ADC1)
  2305. {
  2306. assert_param(IS_ADC1_DIFF_CHANNEL(sConfig->Channel));
  2307. }
  2308. if (hadc->Instance == ADC2)
  2309. {
  2310. assert_param(IS_ADC2_DIFF_CHANNEL(sConfig->Channel));
  2311. }
  2312. #if defined(ADC3)
  2313. /* ADC3 is not available on some STM32H7 products */
  2314. if (hadc->Instance == ADC3)
  2315. {
  2316. assert_param(IS_ADC3_DIFF_CHANNEL(sConfig->Channel));
  2317. }
  2318. #endif
  2319. }
  2320. /* Process locked */
  2321. __HAL_LOCK(hadc);
  2322. /* Parameters update conditioned to ADC state: */
  2323. /* Parameters that can be updated when ADC is disabled or enabled without */
  2324. /* conversion on going on regular group: */
  2325. /* - Channel number */
  2326. /* - Channel rank */
  2327. if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
  2328. {
  2329. /* ADC channels preselection */
  2330. hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
  2331. /* Set ADC group regular sequence: channel on the selected scan sequence rank */
  2332. LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
  2333. /* Parameters update conditioned to ADC state: */
  2334. /* Parameters that can be updated when ADC is disabled or enabled without */
  2335. /* conversion on going on regular group: */
  2336. /* - Channel sampling time */
  2337. /* - Channel offset */
  2338. tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
  2339. tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
  2340. if ((tmp_adc_is_conversion_on_going_regular == 0UL)
  2341. && (tmp_adc_is_conversion_on_going_injected == 0UL)
  2342. )
  2343. {
  2344. /* Set sampling time of the selected ADC channel */
  2345. LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
  2346. /* Configure the offset: offset enable/disable, channel, offset value */
  2347. /* Shift the offset with respect to the selected ADC resolution. */
  2348. /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
  2349. tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
  2350. if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
  2351. {
  2352. /* Set ADC selected offset number */
  2353. LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
  2354. assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
  2355. /* Set ADC selected offset signed saturation */
  2356. LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
  2357. assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
  2358. /* Set ADC selected offset right shift */
  2359. LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
  2360. }
  2361. else
  2362. {
  2363. /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
  2364. If this is the case, offset OFRx is disabled since
  2365. sConfig->OffsetNumber = ADC_OFFSET_NONE. */
  2366. if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
  2367. {
  2368. CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
  2369. }
  2370. if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
  2371. {
  2372. CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
  2373. }
  2374. if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
  2375. {
  2376. CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
  2377. }
  2378. if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
  2379. {
  2380. CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
  2381. }
  2382. }
  2383. }
  2384. /* Parameters update conditioned to ADC state: */
  2385. /* Parameters that can be updated only when ADC is disabled: */
  2386. /* - Single or differential mode */
  2387. /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
  2388. if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
  2389. {
  2390. /* Set mode single-ended or differential input of the selected ADC channel */
  2391. LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
  2392. /* Configuration of differential mode */
  2393. if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
  2394. {
  2395. /* Set sampling time of the selected ADC channel */
  2396. /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
  2397. LL_ADC_SetChannelSamplingTime(hadc->Instance,
  2398. (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
  2399. sConfig->SamplingTime);
  2400. }
  2401. /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
  2402. /* If internal channel selected, enable dedicated internal buffers and */
  2403. /* paths. */
  2404. /* Note: these internal measurement paths can be disabled using */
  2405. /* HAL_ADC_DeInit(). */
  2406. if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
  2407. {
  2408. /* Configuration of common ADC parameters */
  2409. tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  2410. /* Software is allowed to change common parameters only when all ADCs */
  2411. /* of the common group are disabled. */
  2412. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
  2413. {
  2414. /* If the requested internal measurement path has already been enabled, */
  2415. /* bypass the configuration processing. */
  2416. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
  2417. {
  2418. if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
  2419. {
  2420. LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
  2421. /* Delay for temperature sensor stabilization time */
  2422. /* Wait loop initialization and execution */
  2423. /* Note: Variable divided by 2 to compensate partially */
  2424. /* CPU processing cycles, scaling in us split to not */
  2425. /* exceed 32 bits register capacity and handle low frequency. */
  2426. wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
  2427. while(wait_loop_index != 0UL)
  2428. {
  2429. wait_loop_index--;
  2430. }
  2431. }
  2432. }
  2433. else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
  2434. {
  2435. if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
  2436. {
  2437. LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
  2438. }
  2439. }
  2440. else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
  2441. {
  2442. if (ADC_VREFINT_INSTANCE(hadc))
  2443. {
  2444. LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
  2445. }
  2446. }
  2447. else
  2448. {
  2449. /* nothing to do */
  2450. }
  2451. }
  2452. /* If the requested internal measurement path has already been */
  2453. /* enabled and other ADC of the common group are enabled, internal */
  2454. /* measurement paths cannot be enabled. */
  2455. else
  2456. {
  2457. /* Update ADC state machine to error */
  2458. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  2459. tmp_hal_status = HAL_ERROR;
  2460. }
  2461. }
  2462. }
  2463. }
  2464. /* If a conversion is on going on regular group, no update on regular */
  2465. /* channel could be done on neither of the channel configuration structure */
  2466. /* parameters. */
  2467. else
  2468. {
  2469. /* Update ADC state machine to error */
  2470. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  2471. tmp_hal_status = HAL_ERROR;
  2472. }
  2473. /* Process unlocked */
  2474. __HAL_UNLOCK(hadc);
  2475. /* Return function status */
  2476. return tmp_hal_status;
  2477. }
  2478. /**
  2479. * @brief Configure the analog watchdog.
  2480. * @note Possibility to update parameters on the fly:
  2481. * This function initializes the selected analog watchdog, successive
  2482. * calls to this function can be used to reconfigure some parameters
  2483. * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
  2484. * the ADC.
  2485. * The setting of these parameters is conditioned to ADC state.
  2486. * For parameters constraints, see comments of structure
  2487. * "ADC_AnalogWDGConfTypeDef".
  2488. * @note On this STM32 serie, analog watchdog thresholds cannot be modified
  2489. * while ADC conversion is on going.
  2490. * @param hadc ADC handle
  2491. * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
  2492. * @retval HAL status
  2493. */
  2494. HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
  2495. {
  2496. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  2497. uint32_t tmpAWDHighThresholdShifted;
  2498. uint32_t tmpAWDLowThresholdShifted;
  2499. uint32_t tmp_adc_is_conversion_on_going_regular;
  2500. uint32_t tmp_adc_is_conversion_on_going_injected;
  2501. /* Check the parameters */
  2502. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  2503. assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
  2504. assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
  2505. assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
  2506. if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
  2507. (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
  2508. (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
  2509. {
  2510. assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
  2511. }
  2512. /* Verify thresholds range */
  2513. if (hadc->Init.OversamplingMode == ENABLE)
  2514. {
  2515. /* Case of oversampling enabled: thresholds are compared to oversampling
  2516. intermediate computation (after ratio, before shift application) */
  2517. assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
  2518. assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
  2519. }
  2520. else
  2521. {
  2522. /* Verify if thresholds are within the selected ADC resolution */
  2523. assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
  2524. assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
  2525. }
  2526. /* Process locked */
  2527. __HAL_LOCK(hadc);
  2528. /* Parameters update conditioned to ADC state: */
  2529. /* Parameters that can be updated when ADC is disabled or enabled without */
  2530. /* conversion on going on ADC groups regular and injected: */
  2531. /* - Analog watchdog channels */
  2532. /* - Analog watchdog thresholds */
  2533. tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
  2534. tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
  2535. if ((tmp_adc_is_conversion_on_going_regular == 0UL)
  2536. && (tmp_adc_is_conversion_on_going_injected == 0UL)
  2537. )
  2538. {
  2539. /* Analog watchdog configuration */
  2540. if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
  2541. {
  2542. /* Configuration of analog watchdog: */
  2543. /* - Set the analog watchdog enable mode: one or overall group of */
  2544. /* channels, on groups regular and-or injected. */
  2545. switch (AnalogWDGConfig->WatchdogMode)
  2546. {
  2547. case ADC_ANALOGWATCHDOG_SINGLE_REG:
  2548. LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
  2549. LL_ADC_GROUP_REGULAR));
  2550. break;
  2551. case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
  2552. LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
  2553. LL_ADC_GROUP_INJECTED));
  2554. break;
  2555. case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
  2556. LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
  2557. LL_ADC_GROUP_REGULAR_INJECTED));
  2558. break;
  2559. case ADC_ANALOGWATCHDOG_ALL_REG:
  2560. LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
  2561. break;
  2562. case ADC_ANALOGWATCHDOG_ALL_INJEC:
  2563. LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
  2564. break;
  2565. case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
  2566. LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
  2567. break;
  2568. default: /* ADC_ANALOGWATCHDOG_NONE */
  2569. LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
  2570. break;
  2571. }
  2572. /* Shift the offset in function of the selected ADC resolution: */
  2573. /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
  2574. /* are set to 0 */
  2575. tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
  2576. tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
  2577. /* Set the high and low thresholds */
  2578. MODIFY_REG(hadc->Instance->LTR1, ADC_LTR_LT , tmpAWDLowThresholdShifted);
  2579. MODIFY_REG(hadc->Instance->HTR1, ADC_HTR_HT , tmpAWDHighThresholdShifted);
  2580. /* Update state, clear previous result related to AWD1 */
  2581. CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
  2582. /* Clear flag ADC analog watchdog */
  2583. /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
  2584. /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
  2585. /* (in case left enabled by previous ADC operations). */
  2586. LL_ADC_ClearFlag_AWD1(hadc->Instance);
  2587. /* Configure ADC analog watchdog interrupt */
  2588. if (AnalogWDGConfig->ITMode == ENABLE)
  2589. {
  2590. LL_ADC_EnableIT_AWD1(hadc->Instance);
  2591. }
  2592. else
  2593. {
  2594. LL_ADC_DisableIT_AWD1(hadc->Instance);
  2595. }
  2596. }
  2597. /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
  2598. else
  2599. {
  2600. switch (AnalogWDGConfig->WatchdogMode)
  2601. {
  2602. case ADC_ANALOGWATCHDOG_SINGLE_REG:
  2603. case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
  2604. case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
  2605. /* Update AWD by bitfield to keep the possibility to monitor */
  2606. /* several channels by successive calls of this function. */
  2607. if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
  2608. {
  2609. SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
  2610. }
  2611. else
  2612. {
  2613. SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
  2614. }
  2615. break;
  2616. case ADC_ANALOGWATCHDOG_ALL_REG:
  2617. case ADC_ANALOGWATCHDOG_ALL_INJEC:
  2618. case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
  2619. /* Update AWD by bitfield to keep the possibility to monitor */
  2620. /* several channels by successive calls of this function. */
  2621. if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
  2622. {
  2623. SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
  2624. }
  2625. else
  2626. {
  2627. SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
  2628. }
  2629. break;
  2630. default: /* ADC_ANALOGWATCHDOG_NONE */
  2631. LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
  2632. break;
  2633. }
  2634. /* Shift the thresholds in function of the selected ADC resolution */
  2635. /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
  2636. tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
  2637. tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
  2638. if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
  2639. {
  2640. /* Set ADC analog watchdog thresholds value of both thresholds high and low */
  2641. MODIFY_REG(hadc->Instance->LTR2, ADC_LTR_LT , tmpAWDLowThresholdShifted);
  2642. MODIFY_REG(hadc->Instance->HTR2, ADC_HTR_HT , tmpAWDHighThresholdShifted);
  2643. }
  2644. else
  2645. {
  2646. /* Set ADC analog watchdog thresholds value of both thresholds high and low */
  2647. MODIFY_REG(hadc->Instance->LTR3, ADC_LTR_LT , tmpAWDLowThresholdShifted);
  2648. MODIFY_REG(hadc->Instance->HTR3, ADC_HTR_HT , tmpAWDHighThresholdShifted);
  2649. }
  2650. if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
  2651. {
  2652. /* Update state, clear previous result related to AWD2 */
  2653. CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
  2654. /* Clear flag ADC analog watchdog */
  2655. /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
  2656. /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
  2657. /* (in case left enabled by previous ADC operations). */
  2658. LL_ADC_ClearFlag_AWD2(hadc->Instance);
  2659. /* Configure ADC analog watchdog interrupt */
  2660. if (AnalogWDGConfig->ITMode == ENABLE)
  2661. {
  2662. LL_ADC_EnableIT_AWD2(hadc->Instance);
  2663. }
  2664. else
  2665. {
  2666. LL_ADC_DisableIT_AWD2(hadc->Instance);
  2667. }
  2668. }
  2669. /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
  2670. else
  2671. {
  2672. /* Update state, clear previous result related to AWD3 */
  2673. CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
  2674. /* Clear flag ADC analog watchdog */
  2675. /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
  2676. /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
  2677. /* (in case left enabled by previous ADC operations). */
  2678. LL_ADC_ClearFlag_AWD3(hadc->Instance);
  2679. /* Configure ADC analog watchdog interrupt */
  2680. if (AnalogWDGConfig->ITMode == ENABLE)
  2681. {
  2682. LL_ADC_EnableIT_AWD3(hadc->Instance);
  2683. }
  2684. else
  2685. {
  2686. LL_ADC_DisableIT_AWD3(hadc->Instance);
  2687. }
  2688. }
  2689. }
  2690. }
  2691. /* If a conversion is on going on ADC group regular or injected, no update */
  2692. /* could be done on neither of the AWD configuration structure parameters. */
  2693. else
  2694. {
  2695. /* Update ADC state machine to error */
  2696. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  2697. tmp_hal_status = HAL_ERROR;
  2698. }
  2699. /* Process unlocked */
  2700. __HAL_UNLOCK(hadc);
  2701. /* Return function status */
  2702. return tmp_hal_status;
  2703. }
  2704. /**
  2705. * @}
  2706. */
  2707. /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
  2708. * @brief ADC Peripheral State functions
  2709. *
  2710. @verbatim
  2711. ===============================================================================
  2712. ##### Peripheral state and errors functions #####
  2713. ===============================================================================
  2714. [..]
  2715. This subsection provides functions to get in run-time the status of the
  2716. peripheral.
  2717. (+) Check the ADC state
  2718. (+) Check the ADC error code
  2719. @endverbatim
  2720. * @{
  2721. */
  2722. /**
  2723. * @brief Return the ADC handle state.
  2724. * @note ADC state machine is managed by bitfields, ADC status must be
  2725. * compared with states bits.
  2726. * For example:
  2727. * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
  2728. * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
  2729. * @param hadc ADC handle
  2730. * @retval ADC handle state (bitfield on 32 bits)
  2731. */
  2732. uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
  2733. {
  2734. /* Check the parameters */
  2735. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  2736. /* Return ADC handle state */
  2737. return hadc->State;
  2738. }
  2739. /**
  2740. * @brief Return the ADC error code.
  2741. * @param hadc ADC handle
  2742. * @retval ADC error code (bitfield on 32 bits)
  2743. */
  2744. uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
  2745. {
  2746. /* Check the parameters */
  2747. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  2748. return hadc->ErrorCode;
  2749. }
  2750. /**
  2751. * @}
  2752. */
  2753. /**
  2754. * @}
  2755. */
  2756. /** @defgroup ADC_Private_Functions ADC Private Functions
  2757. * @{
  2758. */
  2759. /**
  2760. * @brief Stop ADC conversion.
  2761. * @param hadc ADC handle
  2762. * @param ConversionGroup ADC group regular and/or injected.
  2763. * This parameter can be one of the following values:
  2764. * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
  2765. * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
  2766. * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
  2767. * @retval HAL status.
  2768. */
  2769. HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
  2770. {
  2771. uint32_t tickstart;
  2772. uint32_t Conversion_Timeout_CPU_cycles = 0UL;
  2773. uint32_t conversion_group_reassigned = ConversionGroup;
  2774. uint32_t tmp_ADC_CR_ADSTART_JADSTART;
  2775. uint32_t tmp_adc_is_conversion_on_going_regular;
  2776. uint32_t tmp_adc_is_conversion_on_going_injected;
  2777. /* Check the parameters */
  2778. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  2779. assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
  2780. /* Verification if ADC is not already stopped (on regular and injected */
  2781. /* groups) to bypass this function if not needed. */
  2782. tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
  2783. tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
  2784. if ((tmp_adc_is_conversion_on_going_regular != 0UL)
  2785. || (tmp_adc_is_conversion_on_going_injected != 0UL)
  2786. )
  2787. {
  2788. /* Particular case of continuous auto-injection mode combined with */
  2789. /* auto-delay mode. */
  2790. /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
  2791. /* injected group stop ADC_CR_JADSTP). */
  2792. /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
  2793. /* (see reference manual). */
  2794. if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
  2795. && (hadc->Init.ContinuousConvMode == ENABLE)
  2796. && (hadc->Init.LowPowerAutoWait == ENABLE)
  2797. )
  2798. {
  2799. /* Use stop of regular group */
  2800. conversion_group_reassigned = ADC_REGULAR_GROUP;
  2801. /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
  2802. while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
  2803. {
  2804. if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
  2805. {
  2806. /* Update ADC state machine to error */
  2807. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2808. /* Set ADC error code to ADC peripheral internal error */
  2809. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2810. return HAL_ERROR;
  2811. }
  2812. Conversion_Timeout_CPU_cycles ++;
  2813. }
  2814. /* Clear JEOS */
  2815. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
  2816. }
  2817. /* Stop potential conversion on going on ADC group regular */
  2818. if (conversion_group_reassigned != ADC_INJECTED_GROUP)
  2819. {
  2820. /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
  2821. if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
  2822. {
  2823. if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
  2824. {
  2825. /* Stop ADC group regular conversion */
  2826. LL_ADC_REG_StopConversion(hadc->Instance);
  2827. }
  2828. }
  2829. }
  2830. /* Stop potential conversion on going on ADC group injected */
  2831. if (conversion_group_reassigned != ADC_REGULAR_GROUP)
  2832. {
  2833. /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
  2834. if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
  2835. {
  2836. if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
  2837. {
  2838. /* Stop ADC group injected conversion */
  2839. LL_ADC_INJ_StopConversion(hadc->Instance);
  2840. }
  2841. }
  2842. }
  2843. /* Selection of start and stop bits with respect to the regular or injected group */
  2844. switch (conversion_group_reassigned)
  2845. {
  2846. case ADC_REGULAR_INJECTED_GROUP:
  2847. tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
  2848. break;
  2849. case ADC_INJECTED_GROUP:
  2850. tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
  2851. break;
  2852. /* Case ADC_REGULAR_GROUP only*/
  2853. default:
  2854. tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
  2855. break;
  2856. }
  2857. /* Wait for conversion effectively stopped */
  2858. tickstart = HAL_GetTick();
  2859. while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
  2860. {
  2861. if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
  2862. {
  2863. /* Update ADC state machine to error */
  2864. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2865. /* Set ADC error code to ADC peripheral internal error */
  2866. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2867. return HAL_ERROR;
  2868. }
  2869. }
  2870. }
  2871. /* Return HAL status */
  2872. return HAL_OK;
  2873. }
  2874. /**
  2875. * @brief Enable the selected ADC.
  2876. * @note Prerequisite condition to use this function: ADC must be disabled
  2877. * and voltage regulator must be enabled (done into HAL_ADC_Init()).
  2878. * @param hadc ADC handle
  2879. * @retval HAL status.
  2880. */
  2881. HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
  2882. {
  2883. uint32_t tickstart;
  2884. /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
  2885. /* enabling phase not yet completed: flag ADC ready not yet set). */
  2886. /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
  2887. /* causes: ADC clock not running, ...). */
  2888. if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
  2889. {
  2890. /* Check if conditions to enable the ADC are fulfilled */
  2891. if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
  2892. {
  2893. /* Update ADC state machine to error */
  2894. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2895. /* Set ADC error code to ADC peripheral internal error */
  2896. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2897. return HAL_ERROR;
  2898. }
  2899. /* Enable the ADC peripheral */
  2900. LL_ADC_Enable(hadc->Instance);
  2901. /* Wait for ADC effectively enabled */
  2902. tickstart = HAL_GetTick();
  2903. /* Poll for ADC ready flag raised except case of multimode enabled
  2904. and ADC slave selected. */
  2905. uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
  2906. if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
  2907. || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
  2908. )
  2909. {
  2910. while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
  2911. {
  2912. /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
  2913. has been cleared (after a calibration), ADEN bit is reset by the
  2914. calibration logic.
  2915. The workaround is to continue setting ADEN until ADRDY is becomes 1.
  2916. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
  2917. 4 ADC clock cycle duration */
  2918. /* Note: Test of ADC enabled required due to hardware constraint to */
  2919. /* not enable ADC if already enabled. */
  2920. if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
  2921. {
  2922. LL_ADC_Enable(hadc->Instance);
  2923. }
  2924. if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
  2925. {
  2926. /* Update ADC state machine to error */
  2927. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2928. /* Set ADC error code to ADC peripheral internal error */
  2929. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2930. return HAL_ERROR;
  2931. }
  2932. }
  2933. }
  2934. }
  2935. /* Return HAL status */
  2936. return HAL_OK;
  2937. }
  2938. /**
  2939. * @brief Disable the selected ADC.
  2940. * @note Prerequisite condition to use this function: ADC conversions must be
  2941. * stopped.
  2942. * @param hadc ADC handle
  2943. * @retval HAL status.
  2944. */
  2945. HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
  2946. {
  2947. uint32_t tickstart;
  2948. const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
  2949. /* Verification if ADC is not already disabled: */
  2950. /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
  2951. /* disabled. */
  2952. if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
  2953. && (tmp_adc_is_disable_on_going == 0UL)
  2954. )
  2955. {
  2956. /* Check if conditions to disable the ADC are fulfilled */
  2957. if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
  2958. {
  2959. /* Disable the ADC peripheral */
  2960. LL_ADC_Disable(hadc->Instance);
  2961. __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
  2962. }
  2963. else
  2964. {
  2965. /* Update ADC state machine to error */
  2966. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2967. /* Set ADC error code to ADC peripheral internal error */
  2968. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2969. return HAL_ERROR;
  2970. }
  2971. /* Wait for ADC effectively disabled */
  2972. /* Get tick count */
  2973. tickstart = HAL_GetTick();
  2974. while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
  2975. {
  2976. if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
  2977. {
  2978. /* Update ADC state machine to error */
  2979. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2980. /* Set ADC error code to ADC peripheral internal error */
  2981. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2982. return HAL_ERROR;
  2983. }
  2984. }
  2985. }
  2986. /* Return HAL status */
  2987. return HAL_OK;
  2988. }
  2989. /**
  2990. * @brief DMA transfer complete callback.
  2991. * @param hdma pointer to DMA handle.
  2992. * @retval None
  2993. */
  2994. void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
  2995. {
  2996. /* Retrieve ADC handle corresponding to current DMA handle */
  2997. ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2998. /* Update state machine on conversion status if not in error state */
  2999. if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
  3000. {
  3001. /* Set ADC state */
  3002. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
  3003. /* Determine whether any further conversion upcoming on group regular */
  3004. /* by external trigger, continuous mode or scan sequence on going */
  3005. /* to disable interruption. */
  3006. /* Is it the end of the regular sequence ? */
  3007. if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
  3008. {
  3009. /* Are conversions software-triggered ? */
  3010. if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
  3011. {
  3012. /* Is CONT bit set ? */
  3013. if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
  3014. {
  3015. /* CONT bit is not set, no more conversions expected */
  3016. CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
  3017. if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
  3018. {
  3019. SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  3020. }
  3021. }
  3022. }
  3023. }
  3024. else
  3025. {
  3026. /* DMA End of Transfer interrupt was triggered but conversions sequence
  3027. is not over. If DMACFG is set to 0, conversions are stopped. */
  3028. if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL)
  3029. {
  3030. /* DMACFG bit is not set, conversions are stopped. */
  3031. CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
  3032. if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
  3033. {
  3034. SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  3035. }
  3036. }
  3037. }
  3038. /* Conversion complete callback */
  3039. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  3040. hadc->ConvCpltCallback(hadc);
  3041. #else
  3042. HAL_ADC_ConvCpltCallback(hadc);
  3043. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  3044. }
  3045. else /* DMA and-or internal error occurred */
  3046. {
  3047. if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
  3048. {
  3049. /* Call HAL ADC Error Callback function */
  3050. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  3051. hadc->ErrorCallback(hadc);
  3052. #else
  3053. HAL_ADC_ErrorCallback(hadc);
  3054. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  3055. }
  3056. else
  3057. {
  3058. /* Call ADC DMA error callback */
  3059. hadc->DMA_Handle->XferErrorCallback(hdma);
  3060. }
  3061. }
  3062. }
  3063. /**
  3064. * @brief DMA half transfer complete callback.
  3065. * @param hdma pointer to DMA handle.
  3066. * @retval None
  3067. */
  3068. void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
  3069. {
  3070. /* Retrieve ADC handle corresponding to current DMA handle */
  3071. ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  3072. /* Half conversion callback */
  3073. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  3074. hadc->ConvHalfCpltCallback(hadc);
  3075. #else
  3076. HAL_ADC_ConvHalfCpltCallback(hadc);
  3077. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  3078. }
  3079. /**
  3080. * @brief DMA error callback.
  3081. * @param hdma pointer to DMA handle.
  3082. * @retval None
  3083. */
  3084. void ADC_DMAError(DMA_HandleTypeDef *hdma)
  3085. {
  3086. /* Retrieve ADC handle corresponding to current DMA handle */
  3087. ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  3088. /* Set ADC state */
  3089. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
  3090. /* Set ADC error code to DMA error */
  3091. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
  3092. /* Error callback */
  3093. #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  3094. hadc->ErrorCallback(hadc);
  3095. #else
  3096. HAL_ADC_ErrorCallback(hadc);
  3097. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  3098. }
  3099. /**
  3100. * @brief Configure boost mode of selected ADC.
  3101. * @note Prerequisite condition to use this function: ADC conversions must be
  3102. * stopped.
  3103. * @param hadc ADC handle
  3104. * @retval None.
  3105. */
  3106. void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
  3107. {
  3108. uint32_t freq;
  3109. if(ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
  3110. {
  3111. freq = HAL_RCC_GetHCLKFreq();
  3112. switch(hadc->Init.ClockPrescaler)
  3113. {
  3114. case ADC_CLOCK_SYNC_PCLK_DIV1:
  3115. case ADC_CLOCK_SYNC_PCLK_DIV2:
  3116. freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
  3117. break;
  3118. case ADC_CLOCK_SYNC_PCLK_DIV4:
  3119. freq /= 4UL;
  3120. break;
  3121. default:
  3122. break;
  3123. }
  3124. }
  3125. else
  3126. {
  3127. freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
  3128. switch(hadc->Init.ClockPrescaler)
  3129. {
  3130. case ADC_CLOCK_ASYNC_DIV2:
  3131. case ADC_CLOCK_ASYNC_DIV4:
  3132. case ADC_CLOCK_ASYNC_DIV6:
  3133. case ADC_CLOCK_ASYNC_DIV8:
  3134. case ADC_CLOCK_ASYNC_DIV10:
  3135. case ADC_CLOCK_ASYNC_DIV12:
  3136. freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
  3137. break;
  3138. case ADC_CLOCK_ASYNC_DIV16:
  3139. freq /= 16UL;
  3140. break;
  3141. case ADC_CLOCK_ASYNC_DIV32:
  3142. freq /= 32UL;
  3143. break;
  3144. case ADC_CLOCK_ASYNC_DIV64:
  3145. freq /= 64UL;
  3146. break;
  3147. case ADC_CLOCK_ASYNC_DIV128:
  3148. freq /= 128UL;
  3149. break;
  3150. case ADC_CLOCK_ASYNC_DIV256:
  3151. freq /= 256UL;
  3152. break;
  3153. default:
  3154. break;
  3155. }
  3156. }
  3157. #if defined(ADC_VER_V5_3)
  3158. freq /= 2U;
  3159. if (freq <= 6250000UL)
  3160. {
  3161. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
  3162. }
  3163. else if(freq <= 12500000UL)
  3164. {
  3165. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
  3166. }
  3167. else if(freq <= 25000000UL)
  3168. {
  3169. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
  3170. }
  3171. else /* if(freq > 25000000UL) */
  3172. {
  3173. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
  3174. }
  3175. #else
  3176. if(HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
  3177. {
  3178. if(freq > 20000000UL)
  3179. {
  3180. SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
  3181. }
  3182. else
  3183. {
  3184. CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
  3185. }
  3186. }
  3187. else /* STM32H7 silicon Rev.V */
  3188. {
  3189. freq /= 2U; /* divider by 2 for Rev.V */
  3190. if (freq <= 6250000UL)
  3191. {
  3192. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
  3193. }
  3194. else if(freq <= 12500000UL)
  3195. {
  3196. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
  3197. }
  3198. else if(freq <= 25000000UL)
  3199. {
  3200. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
  3201. }
  3202. else /* if(freq > 25000000UL) */
  3203. {
  3204. MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
  3205. }
  3206. }
  3207. #endif /* ADC_VER_V5_3 */
  3208. }
  3209. /**
  3210. * @}
  3211. */
  3212. #endif /* HAL_ADC_MODULE_ENABLED */
  3213. /**
  3214. * @}
  3215. */
  3216. /**
  3217. * @}
  3218. */
  3219. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/