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  1. /**
  2. ******************************************************************************
  3. * @file stm32h7xx_hal_eth.c
  4. * @author MCD Application Team
  5. * @brief ETH HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Ethernet (ETH) peripheral:
  8. * + Initialization and deinitialization functions
  9. * + IO operation functions
  10. * + Peripheral Control functions
  11. * + Peripheral State and Errors functions
  12. *
  13. @verbatim
  14. ==============================================================================
  15. ##### How to use this driver #####
  16. ==============================================================================
  17. [..]
  18. The ETH HAL driver can be used as follows:
  19. (#)Declare a ETH_HandleTypeDef handle structure, for example:
  20. ETH_HandleTypeDef heth;
  21. (#)Fill parameters of Init structure in heth handle
  22. (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
  23. (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
  24. (##) Enable the Ethernet interface clock using
  25. (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE()
  26. (+++) __HAL_RCC_ETH1TX_CLK_ENABLE()
  27. (+++) __HAL_RCC_ETH1RX_CLK_ENABLE()
  28. (##) Initialize the related GPIO clocks
  29. (##) Configure Ethernet pinout
  30. (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
  31. (#) Ethernet data reception is asynchronous, so call the following API
  32. to start the listening mode:
  33. (##) HAL_ETH_Start():
  34. This API starts the MAC and DMA transmission and reception process,
  35. without enabling end of transfer interrupts, in this mode user
  36. has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
  37. (##) HAL_ETH_Start_IT():
  38. This API starts the MAC and DMA transmission and reception process,
  39. end of transfer interrupts are enabled in this mode,
  40. HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
  41. (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
  42. occurred), user can call the following APIs to get received data:
  43. (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
  44. (##) HAL_ETH_GetRxDataLength(): Get received frame length
  45. (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
  46. please refer to ETH_RxPacketInfo typedef structure
  47. (#) For transmission path, two APIs are available:
  48. (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
  49. (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
  50. HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
  51. (#) Communication with an external PHY device:
  52. (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
  53. (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
  54. (#) Configure the Ethernet MAC after ETH peripheral initialization
  55. (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
  56. (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
  57. (#) Configure the Ethernet DMA after ETH peripheral initialization
  58. (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
  59. (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
  60. -@- The PTP protocol offload APIs are not supported in this driver.
  61. *** Callback registration ***
  62. =============================================
  63. The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
  64. allows the user to configure dynamically the driver callbacks.
  65. Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
  66. Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
  67. (+) TxCpltCallback : Tx Complete Callback.
  68. (+) RxCpltCallback : Rx Complete Callback.
  69. (+) DMAErrorCallback : DMA Error Callback.
  70. (+) MACErrorCallback : MAC Error Callback.
  71. (+) PMTCallback : Power Management Callback
  72. (+) EEECallback : EEE Callback.
  73. (+) WakeUpCallback : Wake UP Callback
  74. (+) MspInitCallback : MspInit Callback.
  75. (+) MspDeInitCallback: MspDeInit Callback.
  76. This function takes as parameters the HAL peripheral handle, the Callback ID
  77. and a pointer to the user callback function.
  78. Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
  79. weak function.
  80. @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
  81. and the Callback ID.
  82. This function allows to reset following callbacks:
  83. (+) TxCpltCallback : Tx Complete Callback.
  84. (+) RxCpltCallback : Rx Complete Callback.
  85. (+) DMAErrorCallback : DMA Error Callback.
  86. (+) MACErrorCallback : MAC Error Callback.
  87. (+) PMTCallback : Power Management Callback
  88. (+) EEECallback : EEE Callback.
  89. (+) WakeUpCallback : Wake UP Callback
  90. (+) MspInitCallback : MspInit Callback.
  91. (+) MspDeInitCallback: MspDeInit Callback.
  92. By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
  93. all callbacks are set to the corresponding weak functions:
  94. examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
  95. Exception done for MspInit and MspDeInit functions that are
  96. reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
  97. these callbacks are null (not registered beforehand).
  98. if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
  99. keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
  100. Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
  101. Exception done MspInit/MspDeInit that can be registered/unregistered
  102. in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
  103. thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  104. In that case first register the MspInit/MspDeInit user callbacks
  105. using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
  106. or HAL_ETH_Init function.
  107. When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
  108. not defined, the callback registration feature is not available and all callbacks
  109. are set to the corresponding weak functions.
  110. @endverbatim
  111. ******************************************************************************
  112. * @attention
  113. *
  114. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  115. * All rights reserved.</center></h2>
  116. *
  117. * This software component is licensed by ST under BSD 3-Clause license,
  118. * the "License"; You may not use this file except in compliance with the
  119. * License. You may obtain a copy of the License at:
  120. * opensource.org/licenses/BSD-3-Clause
  121. *
  122. ******************************************************************************
  123. */
  124. /* Includes ------------------------------------------------------------------*/
  125. #include "stm32h7xx_hal.h"
  126. /** @addtogroup STM32H7xx_HAL_Driver
  127. * @{
  128. */
  129. #ifdef HAL_ETH_MODULE_ENABLED
  130. #if defined(ETH)
  131. /** @defgroup ETH ETH
  132. * @brief ETH HAL module driver
  133. * @{
  134. */
  135. /* Private typedef -----------------------------------------------------------*/
  136. /* Private define ------------------------------------------------------------*/
  137. /** @addtogroup ETH_Private_Constants ETH Private Constants
  138. * @{
  139. */
  140. #define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU)
  141. #define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU)
  142. #define ETH_MACPFR_MASK ((uint32_t)0x800007FFU)
  143. #define ETH_MACWTR_MASK ((uint32_t)0x0000010FU)
  144. #define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U)
  145. #define ETH_MACRFCR_MASK ((uint32_t)0x00000003U)
  146. #define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U)
  147. #define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU)
  148. #define ETH_DMAMR_MASK ((uint32_t)0x00007802U)
  149. #define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U)
  150. #define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU)
  151. #define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U)
  152. #define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U)
  153. #define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
  154. ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
  155. ETH_MACPCSR_RWKPFE)
  156. /* Timeout values */
  157. #define ETH_SWRESET_TIMEOUT ((uint32_t)500U)
  158. #define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
  159. #define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
  160. ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
  161. ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
  162. #define ETH_MAC_US_TICK ((uint32_t)1000000U)
  163. /**
  164. * @}
  165. */
  166. /* Private macros ------------------------------------------------------------*/
  167. /** @defgroup ETH_Private_Macros ETH Private Macros
  168. * @{
  169. */
  170. /* Helper macros for TX descriptor handling */
  171. #define INCR_TX_DESC_INDEX(inx, offset) do {\
  172. (inx) += (offset);\
  173. if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
  174. (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
  175. } while (0)
  176. /* Helper macros for RX descriptor handling */
  177. #define INCR_RX_DESC_INDEX(inx, offset) do {\
  178. (inx) += (offset);\
  179. if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
  180. (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
  181. } while (0)
  182. /**
  183. * @}
  184. */
  185. /* Private function prototypes -----------------------------------------------*/
  186. /** @defgroup ETH_Private_Functions ETH Private Functions
  187. * @{
  188. */
  189. static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
  190. static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
  191. static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
  192. static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
  193. static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
  194. static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
  195. static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
  196. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  197. static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
  198. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  199. /**
  200. * @}
  201. */
  202. /* Exported functions ---------------------------------------------------------*/
  203. /** @defgroup ETH_Exported_Functions ETH Exported Functions
  204. * @{
  205. */
  206. /** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
  207. * @brief Initialization and Configuration functions
  208. *
  209. @verbatim
  210. ===============================================================================
  211. ##### Initialization and Configuration functions #####
  212. ===============================================================================
  213. [..] This subsection provides a set of functions allowing to initialize and
  214. deinitialize the ETH peripheral:
  215. (+) User must Implement HAL_ETH_MspInit() function in which he configures
  216. all related peripherals resources (CLOCK, GPIO and NVIC ).
  217. (+) Call the function HAL_ETH_Init() to configure the selected device with
  218. the selected configuration:
  219. (++) MAC address
  220. (++) Media interface (MII or RMII)
  221. (++) Rx DMA Descriptors Tab
  222. (++) Tx DMA Descriptors Tab
  223. (++) Length of Rx Buffers
  224. (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
  225. for each Rx DMA Descriptor
  226. (+) Call the function HAL_ETH_DeInit() to restore the default configuration
  227. of the selected ETH peripheral.
  228. @endverbatim
  229. * @{
  230. */
  231. /**
  232. * @brief Initialize the Ethernet peripheral registers.
  233. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  234. * the configuration information for ETHERNET module
  235. * @retval HAL status
  236. */
  237. HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
  238. {
  239. uint32_t tickstart;
  240. if(heth == NULL)
  241. {
  242. return HAL_ERROR;
  243. }
  244. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  245. if(heth->gState == HAL_ETH_STATE_RESET)
  246. {
  247. /* Allocate lock resource and initialize it */
  248. heth->Lock = HAL_UNLOCKED;
  249. ETH_InitCallbacksToDefault(heth);
  250. if(heth->MspInitCallback == NULL)
  251. {
  252. heth->MspInitCallback = HAL_ETH_MspInit;
  253. }
  254. /* Init the low level hardware */
  255. heth->MspInitCallback(heth);
  256. }
  257. #else
  258. /* Check the ETH peripheral state */
  259. if(heth->gState == HAL_ETH_STATE_RESET)
  260. {
  261. /* Init the low level hardware : GPIO, CLOCK, NVIC. */
  262. HAL_ETH_MspInit(heth);
  263. }
  264. #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
  265. heth->gState = HAL_ETH_STATE_BUSY;
  266. __HAL_RCC_SYSCFG_CLK_ENABLE();
  267. if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
  268. {
  269. HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
  270. }
  271. else
  272. {
  273. HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
  274. }
  275. /* Ethernet Software reset */
  276. /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
  277. /* After reset all the registers holds their respective reset values */
  278. SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
  279. /* Get tick */
  280. tickstart = HAL_GetTick();
  281. /* Wait for software reset */
  282. while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
  283. {
  284. if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
  285. {
  286. /* Set Error Code */
  287. heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
  288. /* Set State as Error */
  289. heth->gState = HAL_ETH_STATE_ERROR;
  290. /* Return Error */
  291. return HAL_ERROR;
  292. }
  293. }
  294. /*------------------ MDIO CSR Clock Range Configuration --------------------*/
  295. ETH_MAC_MDIO_ClkConfig(heth);
  296. /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
  297. WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
  298. /*------------------ MAC, MTL and DMA default Configuration ----------------*/
  299. ETH_MACDMAConfig(heth);
  300. /* SET DSL to 64 bit */
  301. MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
  302. /* Set Receive Buffers Length (must be a multiple of 4) */
  303. if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
  304. {
  305. /* Set Error Code */
  306. heth->ErrorCode = HAL_ETH_ERROR_PARAM;
  307. /* Set State as Error */
  308. heth->gState = HAL_ETH_STATE_ERROR;
  309. /* Return Error */
  310. return HAL_ERROR;
  311. }
  312. else
  313. {
  314. MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
  315. }
  316. /*------------------ DMA Tx Descriptors Configuration ----------------------*/
  317. ETH_DMATxDescListInit(heth);
  318. /*------------------ DMA Rx Descriptors Configuration ----------------------*/
  319. ETH_DMARxDescListInit(heth);
  320. /*--------------------- ETHERNET MAC Address Configuration ------------------*/
  321. /* Set MAC addr bits 32 to 47 */
  322. heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
  323. /* Set MAC addr bits 0 to 31 */
  324. heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
  325. ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
  326. heth->ErrorCode = HAL_ETH_ERROR_NONE;
  327. heth->gState = HAL_ETH_STATE_READY;
  328. heth->RxState = HAL_ETH_STATE_READY;
  329. return HAL_OK;
  330. }
  331. /**
  332. * @brief DeInitializes the ETH peripheral.
  333. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  334. * the configuration information for ETHERNET module
  335. * @retval HAL status
  336. */
  337. HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
  338. {
  339. /* Set the ETH peripheral state to BUSY */
  340. heth->gState = HAL_ETH_STATE_BUSY;
  341. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  342. if(heth->MspDeInitCallback == NULL)
  343. {
  344. heth->MspDeInitCallback = HAL_ETH_MspDeInit;
  345. }
  346. /* DeInit the low level hardware */
  347. heth->MspDeInitCallback(heth);
  348. #else
  349. /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
  350. HAL_ETH_MspDeInit(heth);
  351. #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
  352. /* Set ETH HAL state to Disabled */
  353. heth->gState= HAL_ETH_STATE_RESET;
  354. /* Return function status */
  355. return HAL_OK;
  356. }
  357. /**
  358. * @brief Initializes the ETH MSP.
  359. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  360. * the configuration information for ETHERNET module
  361. * @retval None
  362. */
  363. __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
  364. {
  365. /* Prevent unused argument(s) compilation warning */
  366. UNUSED(heth);
  367. /* NOTE : This function Should not be modified, when the callback is needed,
  368. the HAL_ETH_MspInit could be implemented in the user file
  369. */
  370. }
  371. /**
  372. * @brief DeInitializes ETH MSP.
  373. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  374. * the configuration information for ETHERNET module
  375. * @retval None
  376. */
  377. __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
  378. {
  379. /* Prevent unused argument(s) compilation warning */
  380. UNUSED(heth);
  381. /* NOTE : This function Should not be modified, when the callback is needed,
  382. the HAL_ETH_MspDeInit could be implemented in the user file
  383. */
  384. }
  385. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  386. /**
  387. * @brief Register a User ETH Callback
  388. * To be used instead of the weak predefined callback
  389. * @param heth eth handle
  390. * @param CallbackID ID of the callback to be registered
  391. * This parameter can be one of the following values:
  392. * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
  393. * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
  394. * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
  395. * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID
  396. * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
  397. * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
  398. * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
  399. * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
  400. * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
  401. * @param pCallback pointer to the Callback function
  402. * @retval status
  403. */
  404. HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
  405. {
  406. HAL_StatusTypeDef status = HAL_OK;
  407. if(pCallback == NULL)
  408. {
  409. /* Update the error code */
  410. heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
  411. return HAL_ERROR;
  412. }
  413. /* Process locked */
  414. __HAL_LOCK(heth);
  415. if(heth->gState == HAL_ETH_STATE_READY)
  416. {
  417. switch (CallbackID)
  418. {
  419. case HAL_ETH_TX_COMPLETE_CB_ID :
  420. heth->TxCpltCallback = pCallback;
  421. break;
  422. case HAL_ETH_RX_COMPLETE_CB_ID :
  423. heth->RxCpltCallback = pCallback;
  424. break;
  425. case HAL_ETH_DMA_ERROR_CB_ID :
  426. heth->DMAErrorCallback = pCallback;
  427. break;
  428. case HAL_ETH_MAC_ERROR_CB_ID :
  429. heth->MACErrorCallback = pCallback;
  430. break;
  431. case HAL_ETH_PMT_CB_ID :
  432. heth->PMTCallback = pCallback;
  433. break;
  434. case HAL_ETH_EEE_CB_ID :
  435. heth->EEECallback = pCallback;
  436. break;
  437. case HAL_ETH_WAKEUP_CB_ID :
  438. heth->WakeUpCallback = pCallback;
  439. break;
  440. case HAL_ETH_MSPINIT_CB_ID :
  441. heth->MspInitCallback = pCallback;
  442. break;
  443. case HAL_ETH_MSPDEINIT_CB_ID :
  444. heth->MspDeInitCallback = pCallback;
  445. break;
  446. default :
  447. /* Update the error code */
  448. heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
  449. /* Return error status */
  450. status = HAL_ERROR;
  451. break;
  452. }
  453. }
  454. else if(heth->gState == HAL_ETH_STATE_RESET)
  455. {
  456. switch (CallbackID)
  457. {
  458. case HAL_ETH_MSPINIT_CB_ID :
  459. heth->MspInitCallback = pCallback;
  460. break;
  461. case HAL_ETH_MSPDEINIT_CB_ID :
  462. heth->MspDeInitCallback = pCallback;
  463. break;
  464. default :
  465. /* Update the error code */
  466. heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
  467. /* Return error status */
  468. status = HAL_ERROR;
  469. break;
  470. }
  471. }
  472. else
  473. {
  474. /* Update the error code */
  475. heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
  476. /* Return error status */
  477. status = HAL_ERROR;
  478. }
  479. /* Release Lock */
  480. __HAL_UNLOCK(heth);
  481. return status;
  482. }
  483. /**
  484. * @brief Unregister an ETH Callback
  485. * ETH callabck is redirected to the weak predefined callback
  486. * @param heth eth handle
  487. * @param CallbackID ID of the callback to be unregistered
  488. * This parameter can be one of the following values:
  489. * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
  490. * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
  491. * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
  492. * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID
  493. * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
  494. * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
  495. * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
  496. * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
  497. * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
  498. * @retval status
  499. */
  500. HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
  501. {
  502. HAL_StatusTypeDef status = HAL_OK;
  503. /* Process locked */
  504. __HAL_LOCK(heth);
  505. if(heth->gState == HAL_ETH_STATE_READY)
  506. {
  507. switch (CallbackID)
  508. {
  509. case HAL_ETH_TX_COMPLETE_CB_ID :
  510. heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
  511. break;
  512. case HAL_ETH_RX_COMPLETE_CB_ID :
  513. heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
  514. break;
  515. case HAL_ETH_DMA_ERROR_CB_ID :
  516. heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;
  517. break;
  518. case HAL_ETH_MAC_ERROR_CB_ID :
  519. heth->MACErrorCallback = HAL_ETH_MACErrorCallback;
  520. break;
  521. case HAL_ETH_PMT_CB_ID :
  522. heth->PMTCallback = HAL_ETH_PMTCallback;
  523. break;
  524. case HAL_ETH_EEE_CB_ID :
  525. heth->EEECallback = HAL_ETH_EEECallback;
  526. break;
  527. case HAL_ETH_WAKEUP_CB_ID :
  528. heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
  529. break;
  530. case HAL_ETH_MSPINIT_CB_ID :
  531. heth->MspInitCallback = HAL_ETH_MspInit;
  532. break;
  533. case HAL_ETH_MSPDEINIT_CB_ID :
  534. heth->MspDeInitCallback = HAL_ETH_MspDeInit;
  535. break;
  536. default :
  537. /* Update the error code */
  538. heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
  539. /* Return error status */
  540. status = HAL_ERROR;
  541. break;
  542. }
  543. }
  544. else if(heth->gState == HAL_ETH_STATE_RESET)
  545. {
  546. switch (CallbackID)
  547. {
  548. case HAL_ETH_MSPINIT_CB_ID :
  549. heth->MspInitCallback = HAL_ETH_MspInit;
  550. break;
  551. case HAL_ETH_MSPDEINIT_CB_ID :
  552. heth->MspDeInitCallback = HAL_ETH_MspDeInit;
  553. break;
  554. default :
  555. /* Update the error code */
  556. heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
  557. /* Return error status */
  558. status = HAL_ERROR;
  559. break;
  560. }
  561. }
  562. else
  563. {
  564. /* Update the error code */
  565. heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
  566. /* Return error status */
  567. status = HAL_ERROR;
  568. }
  569. /* Release Lock */
  570. __HAL_UNLOCK(heth);
  571. return status;
  572. }
  573. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  574. /**
  575. * @brief Assign memory buffers to a DMA Rx descriptor
  576. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  577. * the configuration information for ETHERNET module
  578. * @param Index : index of the DMA Rx descriptor
  579. * this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
  580. * @param pBuffer1: address of buffer 1
  581. * @param pBuffer2: address of buffer 2 if available
  582. * @retval HAL status
  583. */
  584. HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
  585. {
  586. ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
  587. if((pBuffer1 == NULL) || (Index >= (uint32_t)ETH_RX_DESC_CNT))
  588. {
  589. /* Set Error Code */
  590. heth->ErrorCode = HAL_ETH_ERROR_PARAM;
  591. /* Return Error */
  592. return HAL_ERROR;
  593. }
  594. /* write buffer address to RDES0 */
  595. WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
  596. /* store buffer address */
  597. WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
  598. /* set buffer address valid bit to RDES3 */
  599. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
  600. if(pBuffer2 != NULL)
  601. {
  602. /* write buffer 2 address to RDES1 */
  603. WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
  604. /* store buffer 2 address */
  605. WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
  606. /* set buffer 2 address valid bit to RDES3 */
  607. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
  608. }
  609. /* set OWN bit to RDES3 */
  610. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
  611. return HAL_OK;
  612. }
  613. /**
  614. * @}
  615. */
  616. /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
  617. * @brief ETH Transmit and Receive functions
  618. *
  619. @verbatim
  620. ==============================================================================
  621. ##### IO operation functions #####
  622. ==============================================================================
  623. [..]
  624. This subsection provides a set of functions allowing to manage the ETH
  625. data transfer.
  626. @endverbatim
  627. * @{
  628. */
  629. /**
  630. * @brief Enables Ethernet MAC and DMA reception and transmission
  631. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  632. * the configuration information for ETHERNET module
  633. * @retval HAL status
  634. */
  635. HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
  636. {
  637. if(heth->gState == HAL_ETH_STATE_READY)
  638. {
  639. heth->gState = HAL_ETH_STATE_BUSY;
  640. /* Enable the MAC transmission */
  641. SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
  642. /* Enable the MAC reception */
  643. SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
  644. /* Set the Flush Transmit FIFO bit */
  645. SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
  646. /* Enable the DMA transmission */
  647. SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
  648. /* Enable the DMA reception */
  649. SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
  650. /* Clear Tx and Rx process stopped flags */
  651. heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
  652. heth->gState = HAL_ETH_STATE_READY;
  653. heth->RxState = HAL_ETH_STATE_BUSY_RX;
  654. return HAL_OK;
  655. }
  656. else
  657. {
  658. return HAL_ERROR;
  659. }
  660. }
  661. /**
  662. * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
  663. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  664. * the configuration information for ETHERNET module
  665. * @retval HAL status
  666. */
  667. HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
  668. {
  669. uint32_t descindex = 0, counter;
  670. ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
  671. if(heth->gState == HAL_ETH_STATE_READY)
  672. {
  673. heth->gState = HAL_ETH_STATE_BUSY;
  674. /* Set IOC bit to all Rx descriptors */
  675. for(counter= 0; counter < (uint32_t)ETH_RX_DESC_CNT; counter++)
  676. {
  677. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
  678. INCR_RX_DESC_INDEX(descindex, 1U);
  679. dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
  680. }
  681. /* save IT mode to ETH Handle */
  682. heth->RxDescList.ItMode = 1U;
  683. /* Enable the MAC transmission */
  684. SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
  685. /* Enable the MAC reception */
  686. SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
  687. /* Set the Flush Transmit FIFO bit */
  688. SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
  689. /* Enable the DMA transmission */
  690. SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
  691. /* Enable the DMA reception */
  692. SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
  693. /* Clear Tx and Rx process stopped flags */
  694. heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
  695. heth->gState = HAL_ETH_STATE_READY;
  696. heth->RxState = HAL_ETH_STATE_BUSY_RX;
  697. /* Enable ETH DMA interrupts:
  698. - Tx complete interrupt
  699. - Rx complete interrupt
  700. - Fatal bus interrupt
  701. */
  702. __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
  703. ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
  704. return HAL_OK;
  705. }
  706. else
  707. {
  708. return HAL_ERROR;
  709. }
  710. }
  711. /**
  712. * @brief Stop Ethernet MAC and DMA reception/transmission
  713. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  714. * the configuration information for ETHERNET module
  715. * @retval HAL status
  716. */
  717. HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
  718. {
  719. if(heth->gState != HAL_ETH_STATE_RESET)
  720. {
  721. /* Set the ETH peripheral state to BUSY */
  722. heth->gState = HAL_ETH_STATE_BUSY;
  723. /* Disable the DMA transmission */
  724. CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
  725. /* Disable the DMA reception */
  726. CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
  727. /* Disable the MAC reception */
  728. CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
  729. /* Set the Flush Transmit FIFO bit */
  730. SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
  731. /* Disable the MAC transmission */
  732. CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
  733. heth->gState = HAL_ETH_STATE_READY;
  734. heth->RxState = HAL_ETH_STATE_READY;
  735. /* Return function status */
  736. return HAL_OK;
  737. }
  738. else
  739. {
  740. return HAL_ERROR;
  741. }
  742. }
  743. /**
  744. * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
  745. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  746. * the configuration information for ETHERNET module
  747. * @retval HAL status
  748. */
  749. HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
  750. {
  751. ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[0];
  752. uint32_t index;
  753. if(heth->gState != HAL_ETH_STATE_RESET)
  754. {
  755. /* Set the ETH peripheral state to BUSY */
  756. heth->gState = HAL_ETH_STATE_BUSY;
  757. /* Disable intrrupts:
  758. - Tx complete interrupt
  759. - Rx complete interrupt */
  760. __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMA_NORMAL_IT | ETH_DMA_RX_IT | ETH_DMA_TX_IT));
  761. /* Disable the DMA transmission */
  762. CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
  763. /* Disable the DMA reception */
  764. CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
  765. /* Disable the MAC reception */
  766. CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
  767. /* Set the Flush Transmit FIFO bit */
  768. SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
  769. /* Disable the MAC transmission */
  770. CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
  771. /* Clear IOC bit to all Rx descriptors */
  772. for(index = 0; index < (uint32_t)ETH_RX_DESC_CNT; index++)
  773. {
  774. CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
  775. }
  776. heth->RxDescList.ItMode = 0U;
  777. heth->gState = HAL_ETH_STATE_READY;
  778. heth->RxState = HAL_ETH_STATE_READY;
  779. /* Return function status */
  780. return HAL_OK;
  781. }
  782. else
  783. {
  784. return HAL_ERROR;
  785. }
  786. }
  787. /**
  788. * @brief Sends an Ethernet Packet in polling mode.
  789. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  790. * the configuration information for ETHERNET module
  791. * @param pTxConfig: Hold the configuration of packet to be transmitted
  792. * @param Timeout: timeout value
  793. * @retval HAL status
  794. */
  795. HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
  796. {
  797. uint32_t tickstart;
  798. const ETH_DMADescTypeDef *dmatxdesc;
  799. if(pTxConfig == NULL)
  800. {
  801. heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
  802. return HAL_ERROR;
  803. }
  804. if(heth->gState == HAL_ETH_STATE_READY)
  805. {
  806. /* Config DMA Tx descriptor by Tx Packet info */
  807. if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
  808. {
  809. /* Set the ETH error code */
  810. heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
  811. return HAL_ERROR;
  812. }
  813. dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
  814. /* Incr current tx desc index */
  815. INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
  816. /* Start transmission */
  817. /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
  818. WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
  819. tickstart = HAL_GetTick();
  820. /* Wait for data to be transmitted or timeout occured */
  821. while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
  822. {
  823. if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
  824. {
  825. heth->ErrorCode |= HAL_ETH_ERROR_DMA;
  826. heth->DMAErrorCode = heth->Instance->DMACSR;
  827. /* Set ETH HAL State to Ready */
  828. heth->gState = HAL_ETH_STATE_ERROR;
  829. /* Return function status */
  830. return HAL_ERROR;
  831. }
  832. /* Check for the Timeout */
  833. if(Timeout != HAL_MAX_DELAY)
  834. {
  835. if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
  836. {
  837. heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
  838. heth->gState = HAL_ETH_STATE_READY;
  839. return HAL_ERROR;
  840. }
  841. }
  842. }
  843. /* Set ETH HAL State to Ready */
  844. heth->gState = HAL_ETH_STATE_READY;
  845. /* Return function status */
  846. return HAL_OK;
  847. }
  848. else
  849. {
  850. return HAL_ERROR;
  851. }
  852. }
  853. /**
  854. * @brief Sends an Ethernet Packet in interrupt mode.
  855. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  856. * the configuration information for ETHERNET module
  857. * @param pTxConfig: Hold the configuration of packet to be transmitted
  858. * @retval HAL status
  859. */
  860. HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
  861. {
  862. if(pTxConfig == NULL)
  863. {
  864. return HAL_ERROR;
  865. }
  866. if(heth->gState == HAL_ETH_STATE_READY)
  867. {
  868. /* Config DMA Tx descriptor by Tx Packet info */
  869. if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
  870. {
  871. heth->ErrorCode = HAL_ETH_ERROR_BUSY;
  872. return HAL_ERROR;
  873. }
  874. /* Incr current tx desc index */
  875. INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
  876. /* Start transmission */
  877. /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
  878. WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
  879. return HAL_OK;
  880. }
  881. else
  882. {
  883. return HAL_ERROR;
  884. }
  885. }
  886. /**
  887. * @brief Checks for received Packets.
  888. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  889. * the configuration information for ETHERNET module
  890. * @retval 1: A Packet is received
  891. * 0: no Packet received
  892. */
  893. uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
  894. {
  895. ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
  896. uint32_t descidx = dmarxdesclist->CurRxDesc;
  897. ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  898. uint32_t descscancnt = 0;
  899. uint32_t appdesccnt = 0, firstappdescidx = 0;
  900. if(dmarxdesclist->AppDescNbr != 0U)
  901. {
  902. /* data already received by not yet processed*/
  903. return 0;
  904. }
  905. /* Check if descriptor is not owned by DMA */
  906. while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT))
  907. {
  908. descscancnt++;
  909. /* Check if last descriptor */
  910. if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
  911. {
  912. /* Increment the number of descriptors to be passed to the application */
  913. appdesccnt += 1U;
  914. if(appdesccnt == 1U)
  915. {
  916. WRITE_REG(firstappdescidx, descidx);
  917. }
  918. /* Increment current rx descriptor index */
  919. INCR_RX_DESC_INDEX(descidx, 1U);
  920. /* Check for Context descriptor */
  921. /* Get current descriptor address */
  922. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  923. if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET)
  924. {
  925. if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET)
  926. {
  927. /* Increment the number of descriptors to be passed to the application */
  928. dmarxdesclist->AppContextDesc = 1;
  929. /* Increment current rx descriptor index */
  930. INCR_RX_DESC_INDEX(descidx, 1U);
  931. }
  932. }
  933. /* Fill information to Rx descriptors list */
  934. dmarxdesclist->CurRxDesc = descidx;
  935. dmarxdesclist->FirstAppDesc = firstappdescidx;
  936. dmarxdesclist->AppDescNbr = appdesccnt;
  937. /* Return function status */
  938. return 1;
  939. }
  940. /* Check if first descriptor */
  941. else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
  942. {
  943. WRITE_REG(firstappdescidx, descidx);
  944. /* Increment the number of descriptors to be passed to the application */
  945. appdesccnt = 1U;
  946. /* Increment current rx descriptor index */
  947. INCR_RX_DESC_INDEX(descidx, 1U);
  948. /* Get current descriptor address */
  949. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  950. }
  951. /* It should be an intermediate descriptor */
  952. else
  953. {
  954. /* Increment the number of descriptors to be passed to the application */
  955. appdesccnt += 1U;
  956. /* Increment current rx descriptor index */
  957. INCR_RX_DESC_INDEX(descidx, 1U);
  958. /* Get current descriptor address */
  959. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  960. }
  961. }
  962. /* Build Descriptors if an incomplete Packet is received */
  963. if(appdesccnt > 0U)
  964. {
  965. descidx = firstappdescidx;
  966. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  967. for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
  968. {
  969. WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
  970. WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
  971. if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))
  972. {
  973. WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
  974. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
  975. }
  976. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
  977. if(dmarxdesclist->ItMode != ((uint32_t)RESET))
  978. {
  979. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
  980. }
  981. /* Increment rx descriptor index */
  982. INCR_RX_DESC_INDEX(descidx, 1U);
  983. /* Get descriptor address */
  984. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  985. }
  986. }
  987. /* Fill information to Rx descriptors list: No received Packet */
  988. dmarxdesclist->AppDescNbr = 0U;
  989. return 0;
  990. }
  991. /**
  992. * @brief This function gets the buffer address of last received Packet.
  993. * @note Please insure to allocate the RxBuffer structure before calling this function
  994. * how to use example:
  995. * HAL_ETH_GetRxDataLength(heth, &Length);
  996. * BuffersNbr = (Length / heth->Init.RxBuffLen) + 1;
  997. * RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef));
  998. * HAL_ETH_GetRxDataBuffer(heth, RxBuffer);
  999. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1000. * the configuration information for ETHERNET module
  1001. * @param RxBuffer: Pointer to a ETH_BufferTypeDef structure
  1002. * @retval HAL status
  1003. */
  1004. HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
  1005. {
  1006. ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
  1007. uint32_t descidx = dmarxdesclist->FirstAppDesc;
  1008. uint32_t index, accumulatedlen = 0, lastdesclen;
  1009. __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  1010. ETH_BufferTypeDef *rxbuff = RxBuffer;
  1011. if(rxbuff == NULL)
  1012. {
  1013. heth->ErrorCode = HAL_ETH_ERROR_PARAM;
  1014. return HAL_ERROR;
  1015. }
  1016. if(dmarxdesclist->AppDescNbr == 0U)
  1017. {
  1018. if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
  1019. {
  1020. /* No data to be transferred to the application */
  1021. return HAL_ERROR;
  1022. }
  1023. else
  1024. {
  1025. descidx = dmarxdesclist->FirstAppDesc;
  1026. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  1027. }
  1028. }
  1029. /* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */
  1030. for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++)
  1031. {
  1032. /* Get Address and length of the first buffer address */
  1033. rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
  1034. rxbuff->len = heth->Init.RxBuffLen;
  1035. /* Check if the second buffer address of this descriptor is valid */
  1036. if(dmarxdesc->BackupAddr1 != 0U)
  1037. {
  1038. /* Point to next buffer */
  1039. rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
  1040. /* Get Address and length of the second buffer address */
  1041. rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
  1042. rxbuff->len = heth->Init.RxBuffLen;
  1043. }
  1044. else
  1045. {
  1046. /* Nothing to do here */
  1047. }
  1048. /* get total length until this descriptor */
  1049. accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
  1050. /* Increment to next descriptor */
  1051. INCR_RX_DESC_INDEX(descidx, 1U);
  1052. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  1053. /* Point to next buffer */
  1054. rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
  1055. }
  1056. /* last descriptor data length */
  1057. lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
  1058. /* Get Address of the first buffer address */
  1059. rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
  1060. /* data is in only one buffer */
  1061. if(lastdesclen <= heth->Init.RxBuffLen)
  1062. {
  1063. rxbuff->len = lastdesclen;
  1064. }
  1065. /* data is in two buffers */
  1066. else if(dmarxdesc->BackupAddr1 != 0U)
  1067. {
  1068. /* Get the Length of the first buffer address */
  1069. rxbuff->len = heth->Init.RxBuffLen;
  1070. /* Point to next buffer */
  1071. rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
  1072. /* Get the Address the Length of the second buffer address */
  1073. rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
  1074. rxbuff->len = lastdesclen - (heth->Init.RxBuffLen);
  1075. }
  1076. else /* Buffer 2 not valid*/
  1077. {
  1078. return HAL_ERROR;
  1079. }
  1080. return HAL_OK;
  1081. }
  1082. /**
  1083. * @brief This function gets the length of last received Packet.
  1084. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1085. * the configuration information for ETHERNET module
  1086. * @param Length: parameter to hold Rx packet length
  1087. * @retval HAL Status
  1088. */
  1089. HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
  1090. {
  1091. ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
  1092. uint32_t descidx = dmarxdesclist->FirstAppDesc;
  1093. __IO const ETH_DMADescTypeDef *dmarxdesc;
  1094. if(dmarxdesclist->AppDescNbr == 0U)
  1095. {
  1096. if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
  1097. {
  1098. /* No data to be transferred to the application */
  1099. return HAL_ERROR;
  1100. }
  1101. }
  1102. /* Get index of last descriptor */
  1103. INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U));
  1104. /* Point to last descriptor */
  1105. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  1106. *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
  1107. return HAL_OK;
  1108. }
  1109. /**
  1110. * @brief Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
  1111. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1112. * the configuration information for ETHERNET module
  1113. * @param RxPacketInfo: parameter to hold info of received buffer
  1114. * @retval HAL status
  1115. */
  1116. HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
  1117. {
  1118. ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
  1119. uint32_t descidx = dmarxdesclist->FirstAppDesc;
  1120. __IO const ETH_DMADescTypeDef *dmarxdesc;
  1121. if(dmarxdesclist->AppDescNbr == 0U)
  1122. {
  1123. if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
  1124. {
  1125. /* No data to be transferred to the application */
  1126. return HAL_ERROR;
  1127. }
  1128. }
  1129. /* Get index of last descriptor */
  1130. INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
  1131. /* Point to last descriptor */
  1132. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
  1133. if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET)
  1134. {
  1135. RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
  1136. }
  1137. else
  1138. {
  1139. if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U)
  1140. {
  1141. if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
  1142. {
  1143. RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
  1144. RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
  1145. }
  1146. else
  1147. {
  1148. RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
  1149. }
  1150. }
  1151. if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U)
  1152. {
  1153. /* Get Payload type */
  1154. RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
  1155. /* Get Header type */
  1156. RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
  1157. /* Get Checksum status */
  1158. RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
  1159. }
  1160. if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U)
  1161. {
  1162. RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
  1163. RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
  1164. RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
  1165. }
  1166. }
  1167. /* Get the segment count */
  1168. WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
  1169. return HAL_OK;
  1170. }
  1171. /**
  1172. * @brief This function gives back Rx Desc of the last received Packet
  1173. * to the DMA, so ETH DMA will be able to use these descriptors
  1174. * to receive next Packets.
  1175. * It should be called after processing the received Packet.
  1176. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1177. * the configuration information for ETHERNET module
  1178. * @retval HAL status.
  1179. */
  1180. HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
  1181. {
  1182. ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
  1183. uint32_t descindex = dmarxdesclist->FirstAppDesc;
  1184. __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
  1185. uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
  1186. uint32_t descscan;
  1187. if(dmarxdesclist->AppDescNbr == 0U)
  1188. {
  1189. /* No Rx descriptors to build */
  1190. return HAL_ERROR;
  1191. }
  1192. if(dmarxdesclist->AppContextDesc != 0U)
  1193. {
  1194. /* A context descriptor is available */
  1195. totalappdescnbr += 1U;
  1196. }
  1197. for(descscan =0; descscan < totalappdescnbr; descscan++)
  1198. {
  1199. WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
  1200. WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
  1201. if (READ_REG(dmarxdesc->BackupAddr1) != 0U)
  1202. {
  1203. WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
  1204. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
  1205. }
  1206. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
  1207. if(dmarxdesclist->ItMode != 0U)
  1208. {
  1209. SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
  1210. }
  1211. if(descscan < (dmarxdesclist->AppDescNbr - 1U))
  1212. {
  1213. /* Increment rx descriptor index */
  1214. INCR_RX_DESC_INDEX(descindex, 1U);
  1215. /* Get descriptor address */
  1216. dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
  1217. }
  1218. }
  1219. /* Set the Tail pointer address to the last rx descriptor hold by the app */
  1220. WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
  1221. /* reset the Application desc number */
  1222. WRITE_REG(dmarxdesclist->AppDescNbr, 0);
  1223. return HAL_OK;
  1224. }
  1225. /**
  1226. * @brief This function handles ETH interrupt request.
  1227. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1228. * the configuration information for ETHERNET module
  1229. * @retval HAL status
  1230. */
  1231. void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
  1232. {
  1233. /* Packet received */
  1234. if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
  1235. {
  1236. if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
  1237. {
  1238. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1239. /*Call registered Receive complete callback*/
  1240. heth->RxCpltCallback(heth);
  1241. #else
  1242. /* Receive complete callback */
  1243. HAL_ETH_RxCpltCallback(heth);
  1244. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  1245. /* Clear the Eth DMA Rx IT pending bits */
  1246. __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
  1247. }
  1248. }
  1249. /* Packet transmitted */
  1250. if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
  1251. {
  1252. if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
  1253. {
  1254. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1255. /*Call registered Transmit complete callback*/
  1256. heth->TxCpltCallback(heth);
  1257. #else
  1258. /* Transfer complete callback */
  1259. HAL_ETH_TxCpltCallback(heth);
  1260. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  1261. /* Clear the Eth DMA Tx IT pending bits */
  1262. __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
  1263. }
  1264. }
  1265. /* ETH DMA Error */
  1266. if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
  1267. {
  1268. if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
  1269. {
  1270. heth->ErrorCode |= HAL_ETH_ERROR_DMA;
  1271. /* if fatal bus error occured */
  1272. if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
  1273. {
  1274. /* Get DMA error code */
  1275. heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
  1276. /* Disable all interrupts */
  1277. __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
  1278. /* Set HAL state to ERROR */
  1279. heth->gState = HAL_ETH_STATE_ERROR;
  1280. }
  1281. else
  1282. {
  1283. /* Get DMA error status */
  1284. heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
  1285. ETH_DMACSR_RBU | ETH_DMACSR_AIS));
  1286. /* Clear the interrupt summary flag */
  1287. __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
  1288. ETH_DMACSR_RBU | ETH_DMACSR_AIS));
  1289. }
  1290. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1291. /* Call registered DMA Error callback*/
  1292. heth->DMAErrorCallback(heth);
  1293. #else
  1294. /* Ethernet DMA Error callback */
  1295. HAL_ETH_DMAErrorCallback(heth);
  1296. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  1297. }
  1298. }
  1299. /* ETH MAC Error IT */
  1300. if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
  1301. {
  1302. /* Get MAC Rx Tx status and clear Status register pending bit */
  1303. heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
  1304. heth->gState = HAL_ETH_STATE_ERROR;
  1305. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1306. /* Call registered MAC Error callback*/
  1307. heth->DMAErrorCallback(heth);
  1308. #else
  1309. /* Ethernet MAC Error callback */
  1310. HAL_ETH_MACErrorCallback(heth);
  1311. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  1312. heth->MACErrorCode = (uint32_t)(0x0U);
  1313. }
  1314. /* ETH PMT IT */
  1315. if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
  1316. {
  1317. /* Get MAC Wake-up source and clear the status register pending bit */
  1318. heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
  1319. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1320. /* Call registered PMT callback*/
  1321. heth->PMTCallback(heth);
  1322. #else
  1323. /* Ethernet PMT callback */
  1324. HAL_ETH_PMTCallback(heth);
  1325. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  1326. heth->MACWakeUpEvent = (uint32_t)(0x0U);
  1327. }
  1328. /* ETH EEE IT */
  1329. if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
  1330. {
  1331. /* Get MAC LPI interrupt source and clear the status register pending bit */
  1332. heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
  1333. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1334. /* Call registered EEE callback*/
  1335. heth->EEECallback(heth);
  1336. #else
  1337. /* Ethernet EEE callback */
  1338. HAL_ETH_EEECallback(heth);
  1339. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  1340. heth->MACLPIEvent = (uint32_t)(0x0U);
  1341. }
  1342. #if defined(DUAL_CORE)
  1343. if (HAL_GetCurrentCPUID() == CM7_CPUID)
  1344. {
  1345. /* check ETH WAKEUP exti flag */
  1346. if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
  1347. {
  1348. /* Clear ETH WAKEUP Exti pending bit */
  1349. __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
  1350. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1351. /* Call registered WakeUp callback*/
  1352. heth->WakeUpCallback(heth);
  1353. #else
  1354. /* ETH WAKEUP callback */
  1355. HAL_ETH_WakeUpCallback(heth);
  1356. #endif
  1357. }
  1358. }
  1359. else
  1360. {
  1361. /* check ETH WAKEUP exti flag */
  1362. if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
  1363. {
  1364. /* Clear ETH WAKEUP Exti pending bit */
  1365. __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
  1366. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1367. /* Call registered WakeUp callback*/
  1368. heth->WakeUpCallback(heth);
  1369. #else
  1370. /* ETH WAKEUP callback */
  1371. HAL_ETH_WakeUpCallback(heth);
  1372. #endif
  1373. }
  1374. }
  1375. #else
  1376. /* check ETH WAKEUP exti flag */
  1377. if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
  1378. {
  1379. /* Clear ETH WAKEUP Exti pending bit */
  1380. __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
  1381. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  1382. /* Call registered WakeUp callback*/
  1383. heth->WakeUpCallback(heth);
  1384. #else
  1385. /* ETH WAKEUP callback */
  1386. HAL_ETH_WakeUpCallback(heth);
  1387. #endif
  1388. }
  1389. #endif
  1390. }
  1391. /**
  1392. * @brief Tx Transfer completed callbacks.
  1393. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1394. * the configuration information for ETHERNET module
  1395. * @retval None
  1396. */
  1397. __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
  1398. {
  1399. /* Prevent unused argument(s) compilation warning */
  1400. UNUSED(heth);
  1401. /* NOTE : This function Should not be modified, when the callback is needed,
  1402. the HAL_ETH_TxCpltCallback could be implemented in the user file
  1403. */
  1404. }
  1405. /**
  1406. * @brief Rx Transfer completed callbacks.
  1407. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1408. * the configuration information for ETHERNET module
  1409. * @retval None
  1410. */
  1411. __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
  1412. {
  1413. /* Prevent unused argument(s) compilation warning */
  1414. UNUSED(heth);
  1415. /* NOTE : This function Should not be modified, when the callback is needed,
  1416. the HAL_ETH_RxCpltCallback could be implemented in the user file
  1417. */
  1418. }
  1419. /**
  1420. * @brief Ethernet DMA transfer error callbacks
  1421. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1422. * the configuration information for ETHERNET module
  1423. * @retval None
  1424. */
  1425. __weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
  1426. {
  1427. /* Prevent unused argument(s) compilation warning */
  1428. UNUSED(heth);
  1429. /* NOTE : This function Should not be modified, when the callback is needed,
  1430. the HAL_ETH_DMAErrorCallback could be implemented in the user file
  1431. */
  1432. }
  1433. /**
  1434. * @brief Ethernet MAC transfer error callbacks
  1435. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1436. * the configuration information for ETHERNET module
  1437. * @retval None
  1438. */
  1439. __weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
  1440. {
  1441. /* Prevent unused argument(s) compilation warning */
  1442. UNUSED(heth);
  1443. /* NOTE : This function Should not be modified, when the callback is needed,
  1444. the HAL_ETH_MACErrorCallback could be implemented in the user file
  1445. */
  1446. }
  1447. /**
  1448. * @brief Ethernet Power Management module IT callback
  1449. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1450. * the configuration information for ETHERNET module
  1451. * @retval None
  1452. */
  1453. __weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
  1454. {
  1455. /* Prevent unused argument(s) compilation warning */
  1456. UNUSED(heth);
  1457. /* NOTE : This function Should not be modified, when the callback is needed,
  1458. the HAL_ETH_PMTCallback could be implemented in the user file
  1459. */
  1460. }
  1461. /**
  1462. * @brief Energy Efficient Etherent IT callback
  1463. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1464. * the configuration information for ETHERNET module
  1465. * @retval None
  1466. */
  1467. __weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
  1468. {
  1469. /* Prevent unused argument(s) compilation warning */
  1470. UNUSED(heth);
  1471. /* NOTE : This function Should not be modified, when the callback is needed,
  1472. the HAL_ETH_EEECallback could be implemented in the user file
  1473. */
  1474. }
  1475. /**
  1476. * @brief ETH WAKEUP interrupt callback
  1477. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1478. * the configuration information for ETHERNET module
  1479. * @retval None
  1480. */
  1481. __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
  1482. {
  1483. /* Prevent unused argument(s) compilation warning */
  1484. UNUSED(heth);
  1485. /* NOTE : This function Should not be modified, when the callback is needed,
  1486. the HAL_ETH_WakeUpCallback could be implemented in the user file
  1487. */
  1488. }
  1489. /**
  1490. * @brief Read a PHY register
  1491. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1492. * the configuration information for ETHERNET module
  1493. * @param PHYAddr: PHY port address, must be a value from 0 to 31
  1494. * @param PHYReg: PHY register address, must be a value from 0 to 31
  1495. * @param pRegValue: parameter to hold read value
  1496. * @retval HAL status
  1497. */
  1498. HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
  1499. {
  1500. uint32_t tmpreg, tickstart;
  1501. /* Check for the Busy flag */
  1502. if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
  1503. {
  1504. return HAL_ERROR;
  1505. }
  1506. /* Get the MACMDIOAR value */
  1507. WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
  1508. /* Prepare the MDIO Address Register value
  1509. - Set the PHY device address
  1510. - Set the PHY register address
  1511. - Set the read mode
  1512. - Set the MII Busy bit */
  1513. MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
  1514. MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
  1515. MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
  1516. SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
  1517. /* Write the result value into the MDII Address register */
  1518. WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
  1519. tickstart = HAL_GetTick();
  1520. /* Wait for the Busy flag */
  1521. while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
  1522. {
  1523. if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
  1524. {
  1525. return HAL_ERROR;
  1526. }
  1527. }
  1528. /* Get MACMIIDR value */
  1529. WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
  1530. return HAL_OK;
  1531. }
  1532. /**
  1533. * @brief Writes to a PHY register.
  1534. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1535. * the configuration information for ETHERNET module
  1536. * @param PHYAddr: PHY port address, must be a value from 0 to 31
  1537. * @param PHYReg: PHY register address, must be a value from 0 to 31
  1538. * @param RegValue: the value to write
  1539. * @retval HAL status
  1540. */
  1541. HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
  1542. {
  1543. uint32_t tmpreg, tickstart;
  1544. /* Check for the Busy flag */
  1545. if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
  1546. {
  1547. return HAL_ERROR;
  1548. }
  1549. /* Get the MACMDIOAR value */
  1550. WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
  1551. /* Prepare the MDIO Address Register value
  1552. - Set the PHY device address
  1553. - Set the PHY register address
  1554. - Set the write mode
  1555. - Set the MII Busy bit */
  1556. MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
  1557. MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
  1558. MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
  1559. SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
  1560. /* Give the value to the MII data register */
  1561. WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
  1562. /* Write the result value into the MII Address register */
  1563. WRITE_REG(ETH->MACMDIOAR, tmpreg);
  1564. tickstart = HAL_GetTick();
  1565. /* Wait for the Busy flag */
  1566. while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
  1567. {
  1568. if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
  1569. {
  1570. return HAL_ERROR;
  1571. }
  1572. }
  1573. return HAL_OK;
  1574. }
  1575. /**
  1576. * @}
  1577. */
  1578. /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
  1579. * @brief ETH control functions
  1580. *
  1581. @verbatim
  1582. ==============================================================================
  1583. ##### Peripheral Control functions #####
  1584. ==============================================================================
  1585. [..]
  1586. This subsection provides a set of functions allowing to control the ETH
  1587. peripheral.
  1588. @endverbatim
  1589. * @{
  1590. */
  1591. /**
  1592. * @brief Get the configuration of the MAC and MTL subsystems.
  1593. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1594. * the configuration information for ETHERNET module
  1595. * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
  1596. * the configuration of the MAC.
  1597. * @retval HAL Status
  1598. */
  1599. HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
  1600. {
  1601. if (macconf == NULL)
  1602. {
  1603. return HAL_ERROR;
  1604. }
  1605. /* Get MAC parameters */
  1606. macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
  1607. macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4) > 0U) ? ENABLE : DISABLE;
  1608. macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
  1609. macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
  1610. macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE;
  1611. macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
  1612. macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
  1613. macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
  1614. macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
  1615. macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
  1616. macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
  1617. macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17) == 0U) ? ENABLE : DISABLE;
  1618. macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19) == 0U) ? ENABLE : DISABLE;
  1619. macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
  1620. macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
  1621. macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
  1622. macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
  1623. macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
  1624. macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
  1625. macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
  1626. macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
  1627. macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
  1628. macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
  1629. macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
  1630. macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE;
  1631. macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
  1632. macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
  1633. macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
  1634. macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
  1635. macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
  1636. macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
  1637. macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
  1638. macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
  1639. macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE;
  1640. macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
  1641. macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
  1642. macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
  1643. macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
  1644. macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
  1645. return HAL_OK;
  1646. }
  1647. /**
  1648. * @brief Get the configuration of the DMA.
  1649. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1650. * the configuration information for ETHERNET module
  1651. * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
  1652. * the configuration of the ETH DMA.
  1653. * @retval HAL Status
  1654. */
  1655. HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
  1656. {
  1657. if (dmaconf == NULL)
  1658. {
  1659. return HAL_ERROR;
  1660. }
  1661. dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
  1662. dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
  1663. dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15) > 0U) ? ENABLE : DISABLE;
  1664. dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
  1665. dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16) > 0U) ? ENABLE : DISABLE;
  1666. dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
  1667. dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
  1668. dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL);
  1669. dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
  1670. dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
  1671. dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
  1672. return HAL_OK;
  1673. }
  1674. /**
  1675. * @brief Set the MAC configuration.
  1676. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1677. * the configuration information for ETHERNET module
  1678. * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains
  1679. * the configuration of the MAC.
  1680. * @retval HAL status
  1681. */
  1682. HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
  1683. {
  1684. if(macconf == NULL)
  1685. {
  1686. return HAL_ERROR;
  1687. }
  1688. if(heth->RxState == HAL_ETH_STATE_READY)
  1689. {
  1690. ETH_SetMACConfig(heth, macconf);
  1691. return HAL_OK;
  1692. }
  1693. else
  1694. {
  1695. return HAL_ERROR;
  1696. }
  1697. }
  1698. /**
  1699. * @brief Set the ETH DMA configuration.
  1700. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1701. * the configuration information for ETHERNET module
  1702. * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
  1703. * the configuration of the ETH DMA.
  1704. * @retval HAL status
  1705. */
  1706. HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
  1707. {
  1708. if(dmaconf == NULL)
  1709. {
  1710. return HAL_ERROR;
  1711. }
  1712. if(heth->RxState == HAL_ETH_STATE_READY)
  1713. {
  1714. ETH_SetDMAConfig(heth, dmaconf);
  1715. return HAL_OK;
  1716. }
  1717. else
  1718. {
  1719. return HAL_ERROR;
  1720. }
  1721. }
  1722. /**
  1723. * @brief Configures the Clock range of ETH MDIO interface.
  1724. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1725. * the configuration information for ETHERNET module
  1726. * @retval None
  1727. */
  1728. void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
  1729. {
  1730. uint32_t tmpreg, hclk;
  1731. /* Get the ETHERNET MACMDIOAR value */
  1732. tmpreg = (heth->Instance)->MACMDIOAR;
  1733. /* Clear CSR Clock Range bits */
  1734. tmpreg &= ~ETH_MACMDIOAR_CR;
  1735. /* Get hclk frequency value */
  1736. hclk = HAL_RCC_GetHCLKFreq();
  1737. /* Set CR bits depending on hclk value */
  1738. if((hclk >= 20000000U)&&(hclk < 35000000U))
  1739. {
  1740. /* CSR Clock Range between 20-35 MHz */
  1741. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
  1742. }
  1743. else if((hclk >= 35000000U)&&(hclk < 60000000U))
  1744. {
  1745. /* CSR Clock Range between 35-60 MHz */
  1746. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
  1747. }
  1748. else if((hclk >= 60000000U)&&(hclk < 100000000U))
  1749. {
  1750. /* CSR Clock Range between 60-100 MHz */
  1751. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
  1752. }
  1753. else if((hclk >= 100000000U)&&(hclk < 150000000U))
  1754. {
  1755. /* CSR Clock Range between 100-150 MHz */
  1756. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
  1757. }
  1758. else /* (hclk >= 150000000)&&(hclk <= 200000000) */
  1759. {
  1760. /* CSR Clock Range between 150-200 MHz */
  1761. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
  1762. }
  1763. /* Configure the CSR Clock Range */
  1764. (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
  1765. }
  1766. /**
  1767. * @brief Set the ETH MAC (L2) Filters configuration.
  1768. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1769. * the configuration information for ETHERNET module
  1770. * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
  1771. * the configuration of the ETH MAC filters.
  1772. * @retval HAL status
  1773. */
  1774. HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
  1775. {
  1776. uint32_t filterconfig;
  1777. if(pFilterConfig == NULL)
  1778. {
  1779. return HAL_ERROR;
  1780. }
  1781. filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
  1782. ((uint32_t)pFilterConfig->HashUnicast << 1) |
  1783. ((uint32_t)pFilterConfig->HashMulticast << 2) |
  1784. ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
  1785. ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
  1786. ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
  1787. ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
  1788. ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
  1789. ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
  1790. ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
  1791. pFilterConfig->ControlPacketsFilter);
  1792. MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
  1793. return HAL_OK;
  1794. }
  1795. /**
  1796. * @brief Get the ETH MAC (L2) Filters configuration.
  1797. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1798. * the configuration information for ETHERNET module
  1799. * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
  1800. * the configuration of the ETH MAC filters.
  1801. * @retval HAL status
  1802. */
  1803. HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
  1804. {
  1805. if(pFilterConfig == NULL)
  1806. {
  1807. return HAL_ERROR;
  1808. }
  1809. pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
  1810. pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
  1811. pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
  1812. pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
  1813. pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
  1814. pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE;
  1815. pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
  1816. pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
  1817. pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
  1818. pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) ? ENABLE : DISABLE;
  1819. pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
  1820. return HAL_OK;
  1821. }
  1822. /**
  1823. * @brief Set the source MAC Address to be matched.
  1824. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1825. * the configuration information for ETHERNET module
  1826. * @param AddrNbr: The MAC address to configure
  1827. * This parameter must be a value of the following:
  1828. * ETH_MAC_ADDRESS1
  1829. * ETH_MAC_ADDRESS2
  1830. * ETH_MAC_ADDRESS3
  1831. * @param pMACAddr: Pointer to MAC address buffer data (6 bytes)
  1832. * @retval HAL status
  1833. */
  1834. HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
  1835. {
  1836. uint32_t macaddrhr, macaddrlr;
  1837. if(pMACAddr == NULL)
  1838. {
  1839. return HAL_ERROR;
  1840. }
  1841. /* Get mac addr high reg offset */
  1842. macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
  1843. /* Get mac addr low reg offset */
  1844. macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
  1845. /* Set MAC addr bits 32 to 47 */
  1846. (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
  1847. /* Set MAC addr bits 0 to 31 */
  1848. (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
  1849. ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
  1850. /* Enable address and set source address bit */
  1851. (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
  1852. return HAL_OK;
  1853. }
  1854. /**
  1855. * @brief Set the ETH Hash Table Value.
  1856. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1857. * the configuration information for ETHERNET module
  1858. * @param pHashTable: pointer to a table of two 32 bit values, that contains
  1859. * the 64 bits of the hash table.
  1860. * @retval HAL status
  1861. */
  1862. HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
  1863. {
  1864. if(pHashTable == NULL)
  1865. {
  1866. return HAL_ERROR;
  1867. }
  1868. heth->Instance->MACHT0R = pHashTable[0];
  1869. heth->Instance->MACHT1R = pHashTable[1];
  1870. return HAL_OK;
  1871. }
  1872. /**
  1873. * @brief Set the VLAN Identifier for Rx packets
  1874. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1875. * the configuration information for ETHERNET module
  1876. * @param ComparisonBits: 12 or 16 bit comparison mode
  1877. must be a value of @ref ETH_VLAN_Tag_Comparison
  1878. * @param VLANIdentifier: VLAN Identifier value
  1879. * @retval None
  1880. */
  1881. void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
  1882. {
  1883. if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
  1884. {
  1885. MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
  1886. CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
  1887. }
  1888. else
  1889. {
  1890. MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
  1891. SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
  1892. }
  1893. }
  1894. /**
  1895. * @brief Enters the Power down mode.
  1896. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1897. * the configuration information for ETHERNET module
  1898. * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
  1899. * that contains the Power Down configration
  1900. * @retval None.
  1901. */
  1902. void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
  1903. {
  1904. uint32_t powerdownconfig;
  1905. powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
  1906. ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
  1907. ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
  1908. ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
  1909. ETH_MACPCSR_PWRDWN);
  1910. /* Enable PMT interrupt */
  1911. __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
  1912. MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
  1913. }
  1914. /**
  1915. * @brief Exits from the Power down mode.
  1916. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1917. * the configuration information for ETHERNET module
  1918. * @retval None.
  1919. */
  1920. void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
  1921. {
  1922. /* clear wake up sources */
  1923. CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
  1924. if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U)
  1925. {
  1926. /* Exit power down mode */
  1927. CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
  1928. }
  1929. /* Disable PMT interrupt */
  1930. __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
  1931. }
  1932. /**
  1933. * @brief Set the WakeUp filter.
  1934. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1935. * the configuration information for ETHERNET module
  1936. * @param pFilter: pointer to filter registers values
  1937. * @param Count: number of filter registers, must be from 1 to 8.
  1938. * @retval None.
  1939. */
  1940. HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
  1941. {
  1942. uint32_t regindex;
  1943. if(pFilter == NULL)
  1944. {
  1945. return HAL_ERROR;
  1946. }
  1947. /* Reset Filter Pointer */
  1948. SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
  1949. /* Wake up packet filter config */
  1950. for(regindex = 0; regindex < Count; regindex++)
  1951. {
  1952. /* Write filter regs */
  1953. WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
  1954. }
  1955. return HAL_OK;
  1956. }
  1957. /**
  1958. * @}
  1959. */
  1960. /** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
  1961. * @brief ETH State and Errors functions
  1962. *
  1963. @verbatim
  1964. ==============================================================================
  1965. ##### Peripheral State and Errors functions #####
  1966. ==============================================================================
  1967. [..]
  1968. This subsection provides a set of functions allowing to return the State of
  1969. ETH communication process, return Peripheral Errors occurred during communication
  1970. process
  1971. @endverbatim
  1972. * @{
  1973. */
  1974. /**
  1975. * @brief Returns the ETH state.
  1976. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1977. * the configuration information for ETHERNET module
  1978. * @retval HAL state
  1979. */
  1980. HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
  1981. {
  1982. HAL_ETH_StateTypeDef ret;
  1983. HAL_ETH_StateTypeDef gstate = heth->gState;
  1984. HAL_ETH_StateTypeDef rxstate =heth->RxState;
  1985. ret = gstate;
  1986. ret |= rxstate;
  1987. return ret;
  1988. }
  1989. /**
  1990. * @brief Returns the ETH error code
  1991. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1992. * the configuration information for ETHERNET module
  1993. * @retval ETH Error Code
  1994. */
  1995. uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
  1996. {
  1997. return heth->ErrorCode;
  1998. }
  1999. /**
  2000. * @brief Returns the ETH DMA error code
  2001. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  2002. * the configuration information for ETHERNET module
  2003. * @retval ETH DMA Error Code
  2004. */
  2005. uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
  2006. {
  2007. return heth->DMAErrorCode;
  2008. }
  2009. /**
  2010. * @brief Returns the ETH MAC error code
  2011. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  2012. * the configuration information for ETHERNET module
  2013. * @retval ETH MAC Error Code
  2014. */
  2015. uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
  2016. {
  2017. return heth->MACErrorCode;
  2018. }
  2019. /**
  2020. * @brief Returns the ETH MAC WakeUp event source
  2021. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  2022. * the configuration information for ETHERNET module
  2023. * @retval ETH MAC WakeUp event source
  2024. */
  2025. uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
  2026. {
  2027. return heth->MACWakeUpEvent;
  2028. }
  2029. /**
  2030. * @}
  2031. */
  2032. /**
  2033. * @}
  2034. */
  2035. static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
  2036. {
  2037. uint32_t macregval;
  2038. /*------------------------ MACCR Configuration --------------------*/
  2039. macregval =(macconf->InterPacketGapVal |
  2040. macconf->SourceAddrControl |
  2041. ((uint32_t)macconf->ChecksumOffload<< 27) |
  2042. ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
  2043. ((uint32_t)macconf->Support2KPacket << 22) |
  2044. ((uint32_t)macconf->CRCStripTypePacket << 21) |
  2045. ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
  2046. ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
  2047. ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
  2048. ((uint32_t)macconf->JumboPacket << 16) |
  2049. macconf->Speed |
  2050. macconf->DuplexMode |
  2051. ((uint32_t)macconf->LoopbackMode << 12) |
  2052. ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11)|
  2053. ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10)|
  2054. ((uint32_t)macconf->CarrierSenseDuringTransmit << 9)|
  2055. ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8)|
  2056. macconf->BackOffLimit |
  2057. ((uint32_t)macconf->DeferralCheck << 4)|
  2058. macconf->PreambleLength);
  2059. /* Write to MACCR */
  2060. MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
  2061. /*------------------------ MACECR Configuration --------------------*/
  2062. macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
  2063. ((uint32_t)macconf->ExtendedInterPacketGap << 24)|
  2064. ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18)|
  2065. ((uint32_t)macconf->SlowProtocolDetect << 17)|
  2066. ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U)<< 16) |
  2067. macconf->GiantPacketSizeLimit);
  2068. /* Write to MACECR */
  2069. MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
  2070. /*------------------------ MACWTR Configuration --------------------*/
  2071. macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
  2072. macconf->WatchdogTimeout);
  2073. /* Write to MACWTR */
  2074. MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
  2075. /*------------------------ MACTFCR Configuration --------------------*/
  2076. macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
  2077. macconf->PauseLowThreshold |
  2078. ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U)<< 7) |
  2079. (macconf->PauseTime << 16));
  2080. /* Write to MACTFCR */
  2081. MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
  2082. /*------------------------ MACRFCR Configuration --------------------*/
  2083. macregval = ((uint32_t)macconf->ReceiveFlowControl |
  2084. ((uint32_t)macconf->UnicastPausePacketDetect << 1));
  2085. /* Write to MACRFCR */
  2086. MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
  2087. /*------------------------ MTLTQOMR Configuration --------------------*/
  2088. /* Write to MTLTQOMR */
  2089. MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
  2090. /*------------------------ MTLRQOMR Configuration --------------------*/
  2091. macregval = (macconf->ReceiveQueueMode |
  2092. ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
  2093. ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
  2094. ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
  2095. /* Write to MTLRQOMR */
  2096. MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
  2097. }
  2098. static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
  2099. {
  2100. uint32_t dmaregval;
  2101. /*------------------------ DMAMR Configuration --------------------*/
  2102. MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
  2103. /*------------------------ DMASBMR Configuration --------------------*/
  2104. dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
  2105. dmaconf->BurstMode |
  2106. ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
  2107. MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
  2108. /*------------------------ DMACCR Configuration --------------------*/
  2109. dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
  2110. dmaconf->MaximumSegmentSize);
  2111. MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
  2112. /*------------------------ DMACTCR Configuration --------------------*/
  2113. dmaregval = (dmaconf->TxDMABurstLength |
  2114. ((uint32_t)dmaconf->SecondPacketOperate << 4)|
  2115. ((uint32_t)dmaconf->TCPSegmentation << 12));
  2116. MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
  2117. /*------------------------ DMACRCR Configuration --------------------*/
  2118. dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) |
  2119. dmaconf->RxDMABurstLength);
  2120. /* Write to DMACRCR */
  2121. MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
  2122. }
  2123. /**
  2124. * @brief Configures Ethernet MAC and DMA with default parameters.
  2125. * called by HAL_ETH_Init() API.
  2126. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  2127. * the configuration information for ETHERNET module
  2128. * @retval HAL status
  2129. */
  2130. static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
  2131. {
  2132. ETH_MACConfigTypeDef macDefaultConf;
  2133. ETH_DMAConfigTypeDef dmaDefaultConf;
  2134. /*--------------- ETHERNET MAC registers default Configuration --------------*/
  2135. macDefaultConf.AutomaticPadCRCStrip = ENABLE;
  2136. macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
  2137. macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
  2138. macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
  2139. macDefaultConf.ChecksumOffload = ENABLE;
  2140. macDefaultConf.CRCCheckingRxPackets = ENABLE;
  2141. macDefaultConf.CRCStripTypePacket = ENABLE;
  2142. macDefaultConf.DeferralCheck = DISABLE;
  2143. macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
  2144. macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
  2145. macDefaultConf.ExtendedInterPacketGap = DISABLE;
  2146. macDefaultConf.ExtendedInterPacketGapVal = 0x0;
  2147. macDefaultConf.ForwardRxErrorPacket = DISABLE;
  2148. macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
  2149. macDefaultConf.GiantPacketSizeLimit = 0x618;
  2150. macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
  2151. macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
  2152. macDefaultConf.Jabber = ENABLE;
  2153. macDefaultConf.JumboPacket = DISABLE;
  2154. macDefaultConf.LoopbackMode = DISABLE;
  2155. macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
  2156. macDefaultConf.PauseTime = 0x0;
  2157. macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
  2158. macDefaultConf.ProgrammableWatchdog = DISABLE;
  2159. macDefaultConf.ReceiveFlowControl = DISABLE;
  2160. macDefaultConf.ReceiveOwn = ENABLE;
  2161. macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
  2162. macDefaultConf.RetryTransmission = ENABLE;
  2163. macDefaultConf.SlowProtocolDetect = DISABLE;
  2164. macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
  2165. macDefaultConf.Speed = ETH_SPEED_100M;
  2166. macDefaultConf.Support2KPacket = DISABLE;
  2167. macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
  2168. macDefaultConf.TransmitFlowControl = DISABLE;
  2169. macDefaultConf.UnicastPausePacketDetect = DISABLE;
  2170. macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
  2171. macDefaultConf.Watchdog = ENABLE;
  2172. macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB;
  2173. macDefaultConf.ZeroQuantaPause = ENABLE;
  2174. /* MAC default configuration */
  2175. ETH_SetMACConfig(heth, &macDefaultConf);
  2176. /*--------------- ETHERNET DMA registers default Configuration --------------*/
  2177. dmaDefaultConf.AddressAlignedBeats = ENABLE;
  2178. dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
  2179. dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
  2180. dmaDefaultConf.FlushRxPacket = DISABLE;
  2181. dmaDefaultConf.PBLx8Mode = DISABLE;
  2182. dmaDefaultConf.RebuildINCRxBurst = DISABLE;
  2183. dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
  2184. dmaDefaultConf.SecondPacketOperate = DISABLE;
  2185. dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
  2186. dmaDefaultConf.TCPSegmentation = DISABLE;
  2187. dmaDefaultConf.MaximumSegmentSize = 536;
  2188. /* DMA default configuration */
  2189. ETH_SetDMAConfig(heth, &dmaDefaultConf);
  2190. }
  2191. /**
  2192. * @brief Configures the Clock range of SMI interface.
  2193. * called by HAL_ETH_Init() API.
  2194. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  2195. * the configuration information for ETHERNET module
  2196. * @retval None
  2197. */
  2198. static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
  2199. {
  2200. uint32_t tmpreg, hclk;
  2201. /* Get the ETHERNET MACMDIOAR value */
  2202. tmpreg = (heth->Instance)->MACMDIOAR;
  2203. /* Clear CSR Clock Range bits */
  2204. tmpreg &= ~ETH_MACMDIOAR_CR;
  2205. /* Get hclk frequency value */
  2206. hclk = HAL_RCC_GetHCLKFreq();
  2207. /* Set CR bits depending on hclk value */
  2208. if((hclk >= 20000000U)&&(hclk < 35000000U))
  2209. {
  2210. /* CSR Clock Range between 20-35 MHz */
  2211. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
  2212. }
  2213. else if((hclk >= 35000000U)&&(hclk < 60000000U))
  2214. {
  2215. /* CSR Clock Range between 35-60 MHz */
  2216. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
  2217. }
  2218. else if((hclk >= 60000000U)&&(hclk < 100000000U))
  2219. {
  2220. /* CSR Clock Range between 60-100 MHz */
  2221. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
  2222. }
  2223. else if((hclk >= 100000000U)&&(hclk < 150000000U))
  2224. {
  2225. /* CSR Clock Range between 100-150 MHz */
  2226. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
  2227. }
  2228. else /* (hclk >= 150000000)&&(hclk <= 200000000) */
  2229. {
  2230. /* CSR Clock Range between 150-200 MHz */
  2231. tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
  2232. }
  2233. /* Configure the CSR Clock Range */
  2234. (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
  2235. }
  2236. /**
  2237. * @brief Initializes the DMA Tx descriptors.
  2238. * called by HAL_ETH_Init() API.
  2239. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  2240. * the configuration information for ETHERNET module
  2241. * @retval None
  2242. */
  2243. static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
  2244. {
  2245. ETH_DMADescTypeDef *dmatxdesc;
  2246. uint32_t i;
  2247. /* Fill each DMATxDesc descriptor with the right values */
  2248. for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
  2249. {
  2250. dmatxdesc = heth->Init.TxDesc + i;
  2251. WRITE_REG(dmatxdesc->DESC0, 0x0);
  2252. WRITE_REG(dmatxdesc->DESC1, 0x0);
  2253. WRITE_REG(dmatxdesc->DESC2, 0x0);
  2254. WRITE_REG(dmatxdesc->DESC3, 0x0);
  2255. WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
  2256. }
  2257. heth->TxDescList.CurTxDesc = 0;
  2258. /* Set Transmit Descriptor Ring Length */
  2259. WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
  2260. /* Set Transmit Descriptor List Address */
  2261. WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
  2262. /* Set Transmit Descriptor Tail pointer */
  2263. WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
  2264. }
  2265. /**
  2266. * @brief Initializes the DMA Rx descriptors in chain mode.
  2267. * called by HAL_ETH_Init() API.
  2268. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  2269. * the configuration information for ETHERNET module
  2270. * @retval None
  2271. */
  2272. static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
  2273. {
  2274. ETH_DMADescTypeDef *dmarxdesc;
  2275. uint32_t i;
  2276. for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
  2277. {
  2278. dmarxdesc = heth->Init.RxDesc + i;
  2279. WRITE_REG(dmarxdesc->DESC0, 0x0);
  2280. WRITE_REG(dmarxdesc->DESC1, 0x0);
  2281. WRITE_REG(dmarxdesc->DESC2, 0x0);
  2282. WRITE_REG(dmarxdesc->DESC3, 0x0);
  2283. WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
  2284. WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
  2285. /* Set Rx descritors adresses */
  2286. WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
  2287. }
  2288. WRITE_REG(heth->RxDescList.CurRxDesc, 0);
  2289. WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
  2290. WRITE_REG(heth->RxDescList.AppDescNbr, 0);
  2291. WRITE_REG(heth->RxDescList.ItMode, 0);
  2292. WRITE_REG(heth->RxDescList.AppContextDesc, 0);
  2293. /* Set Receive Descriptor Ring Length */
  2294. WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1)));
  2295. /* Set Receive Descriptor List Address */
  2296. WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
  2297. /* Set Receive Descriptor Tail pointer Address */
  2298. WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (((uint32_t)(ETH_RX_DESC_CNT - 1))*sizeof(ETH_DMADescTypeDef)))));
  2299. }
  2300. /**
  2301. * @brief Prepare Tx DMA descriptor before transmission.
  2302. * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
  2303. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  2304. * the configuration information for ETHERNET module
  2305. * @param pTxConfig: Tx packet configuration
  2306. * @param ItMode: Enable or disable Tx EOT interrept
  2307. * @retval Status
  2308. */
  2309. static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
  2310. {
  2311. ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
  2312. uint32_t descidx = dmatxdesclist->CurTxDesc;
  2313. uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
  2314. uint32_t descnbr = 0, idx;
  2315. ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
  2316. ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
  2317. /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
  2318. if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
  2319. {
  2320. return HAL_ETH_ERROR_BUSY;
  2321. }
  2322. /***************************************************************************/
  2323. /***************** Context descriptor configuration (Optional) **********/
  2324. /***************************************************************************/
  2325. /* If VLAN tag is enabled for this packet */
  2326. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
  2327. {
  2328. /* Set vlan tag value */
  2329. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
  2330. /* Set vlan tag valid bit */
  2331. SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
  2332. /* Set the descriptor as the vlan input source */
  2333. SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
  2334. /* if inner VLAN is enabled */
  2335. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U)
  2336. {
  2337. /* Set inner vlan tag value */
  2338. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
  2339. /* Set inner vlan tag valid bit */
  2340. SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
  2341. /* Set Vlan Tag control */
  2342. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
  2343. /* Set the descriptor as the inner vlan input source */
  2344. SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
  2345. /* Enable double VLAN processing */
  2346. SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
  2347. }
  2348. }
  2349. /* if tcp segementation is enabled for this packet */
  2350. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
  2351. {
  2352. /* Set MSS value */
  2353. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
  2354. /* Set MSS valid bit */
  2355. SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
  2356. }
  2357. if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U))
  2358. {
  2359. /* Set as context descriptor */
  2360. SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
  2361. /* Set own bit */
  2362. SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
  2363. /* Increment current tx descriptor index */
  2364. INCR_TX_DESC_INDEX(descidx, 1U);
  2365. /* Get current descriptor address */
  2366. dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
  2367. descnbr += 1U;
  2368. /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
  2369. if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
  2370. {
  2371. dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
  2372. /* Clear own bit */
  2373. CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
  2374. return HAL_ETH_ERROR_BUSY;
  2375. }
  2376. }
  2377. /***************************************************************************/
  2378. /***************** Normal descriptors configuration *****************/
  2379. /***************************************************************************/
  2380. descnbr += 1U;
  2381. /* Set header or buffer 1 address */
  2382. WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
  2383. /* Set header or buffer 1 Length */
  2384. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
  2385. if(txbuffer->next != NULL)
  2386. {
  2387. txbuffer = txbuffer->next;
  2388. /* Set buffer 2 address */
  2389. WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
  2390. /* Set buffer 2 Length */
  2391. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
  2392. }
  2393. else
  2394. {
  2395. WRITE_REG(dmatxdesc->DESC1, 0x0);
  2396. /* Set buffer 2 Length */
  2397. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
  2398. }
  2399. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
  2400. {
  2401. /* Set TCP Header length */
  2402. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
  2403. /* Set TCP payload length */
  2404. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
  2405. /* Set TCP Segmentation Enabled bit */
  2406. SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
  2407. }
  2408. else
  2409. {
  2410. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
  2411. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
  2412. {
  2413. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
  2414. }
  2415. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)
  2416. {
  2417. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
  2418. }
  2419. }
  2420. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
  2421. {
  2422. /* Set Vlan Tag control */
  2423. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
  2424. }
  2425. /* Mark it as First Descriptor */
  2426. SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
  2427. /* Mark it as NORMAL descriptor */
  2428. CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
  2429. /* set OWN bit of FIRST descriptor */
  2430. SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
  2431. /* If source address insertion/replacement is enabled for this packet */
  2432. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U)
  2433. {
  2434. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
  2435. }
  2436. /* only if the packet is splitted into more than one descriptors > 1 */
  2437. while (txbuffer->next != NULL)
  2438. {
  2439. /* Clear the LD bit of previous descriptor */
  2440. CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
  2441. /* Increment current tx descriptor index */
  2442. INCR_TX_DESC_INDEX(descidx, 1U);
  2443. /* Get current descriptor address */
  2444. dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
  2445. /* Clear the FD bit of new Descriptor */
  2446. CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
  2447. /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
  2448. if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
  2449. {
  2450. descidx = firstdescidx;
  2451. dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
  2452. /* clear previous desc own bit */
  2453. for(idx = 0; idx < descnbr; idx ++)
  2454. {
  2455. CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
  2456. /* Increment current tx descriptor index */
  2457. INCR_TX_DESC_INDEX(descidx, 1U);
  2458. /* Get current descriptor address */
  2459. dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
  2460. }
  2461. return HAL_ETH_ERROR_BUSY;
  2462. }
  2463. descnbr += 1U;
  2464. /* Get the next Tx buffer in the list */
  2465. txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
  2466. /* Set header or buffer 1 address */
  2467. WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
  2468. /* Set header or buffer 1 Length */
  2469. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
  2470. if (txbuffer->next != NULL)
  2471. {
  2472. /* Get the next Tx buffer in the list */
  2473. txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
  2474. /* Set buffer 2 address */
  2475. WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
  2476. /* Set buffer 2 Length */
  2477. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
  2478. }
  2479. else
  2480. {
  2481. WRITE_REG(dmatxdesc->DESC1, 0x0);
  2482. /* Set buffer 2 Length */
  2483. MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
  2484. }
  2485. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
  2486. {
  2487. /* Set TCP payload length */
  2488. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
  2489. /* Set TCP Segmentation Enabled bit */
  2490. SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
  2491. }
  2492. else
  2493. {
  2494. /* Set the packet length */
  2495. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
  2496. if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
  2497. {
  2498. /* Checksum Insertion Control */
  2499. MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
  2500. }
  2501. }
  2502. /* Set Own bit */
  2503. SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
  2504. /* Mark it as NORMAL descriptor */
  2505. CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
  2506. }
  2507. if(ItMode != ((uint32_t)RESET))
  2508. {
  2509. /* Set Interrupt on completition bit */
  2510. SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
  2511. }
  2512. else
  2513. {
  2514. /* Clear Interrupt on completition bit */
  2515. CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
  2516. }
  2517. /* Mark it as LAST descriptor */
  2518. SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
  2519. dmatxdesclist->CurTxDesc = descidx;
  2520. /* Return function status */
  2521. return HAL_ETH_ERROR_NONE;
  2522. }
  2523. #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
  2524. static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
  2525. {
  2526. /* Init the ETH Callback settings */
  2527. heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
  2528. heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
  2529. heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback; /* Legacy weak DMAErrorCallback */
  2530. heth->MACErrorCallback = HAL_ETH_MACErrorCallback; /* Legacy weak MACErrorCallback */
  2531. heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */
  2532. heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */
  2533. heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */
  2534. }
  2535. #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
  2536. /**
  2537. * @}
  2538. */
  2539. #endif /* ETH */
  2540. #endif /* HAL_ETH_MODULE_ENABLED */
  2541. /**
  2542. * @}
  2543. */
  2544. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/