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  1. /**
  2. ******************************************************************************
  3. * @file stm32h7xx_hal_nor.c
  4. * @author MCD Application Team
  5. * @brief NOR HAL module driver.
  6. * This file provides a generic firmware to drive NOR memories mounted
  7. * as external device.
  8. *
  9. @verbatim
  10. ==============================================================================
  11. ##### How to use this driver #####
  12. ==============================================================================
  13. [..]
  14. This driver is a generic layered driver which contains a set of APIs used to
  15. control NOR flash memories. It uses the FMC layer functions to interface
  16. with NOR devices. This driver is used as follows:
  17. (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
  18. with control and timing parameters for both normal and extended mode.
  19. (+) Read NOR flash memory manufacturer code and device IDs using the function
  20. HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
  21. structure declared by the function caller.
  22. (+) Access NOR flash memory by read/write data unit operations using the functions
  23. HAL_NOR_Read(), HAL_NOR_Program().
  24. (+) Perform NOR flash erase block/chip operations using the functions
  25. HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
  26. (+) Read the NOR flash CFI (common flash interface) IDs using the function
  27. HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
  28. structure declared by the function caller.
  29. (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
  30. HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
  31. (+) You can monitor the NOR device HAL state by calling the function
  32. HAL_NOR_GetState()
  33. [..]
  34. (@) This driver is a set of generic APIs which handle standard NOR flash operations.
  35. If a NOR flash device contains different operations and/or implementations,
  36. it should be implemented separately.
  37. *** NOR HAL driver macros list ***
  38. =============================================
  39. [..]
  40. Below the list of most used macros in NOR HAL driver.
  41. (+) NOR_WRITE : NOR memory write data to specified address
  42. *** Callback registration ***
  43. =============================================
  44. [..]
  45. The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
  46. allows the user to configure dynamically the driver callbacks.
  47. Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
  48. it allows to register following callbacks:
  49. (+) MspInitCallback : NOR MspInit.
  50. (+) MspDeInitCallback : NOR MspDeInit.
  51. This function takes as parameters the HAL peripheral handle, the Callback ID
  52. and a pointer to the user callback function.
  53. Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
  54. weak (surcharged) function. It allows to reset following callbacks:
  55. (+) MspInitCallback : NOR MspInit.
  56. (+) MspDeInitCallback : NOR MspDeInit.
  57. This function) takes as parameters the HAL peripheral handle and the Callback ID.
  58. By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
  59. all callbacks are reset to the corresponding legacy weak (surcharged) functions.
  60. Exception done for MspInit and MspDeInit callbacks that are respectively
  61. reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
  62. and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
  63. If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
  64. keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
  65. Callbacks can be registered/unregistered in READY state only.
  66. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
  67. in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
  68. during the Init/DeInit.
  69. In that case first register the MspInit/MspDeInit user callbacks
  70. using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
  71. or @ref HAL_NOR_Init function.
  72. When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
  73. not defined, the callback registering feature is not available
  74. and weak (surcharged) callbacks are used.
  75. @endverbatim
  76. ******************************************************************************
  77. * @attention
  78. *
  79. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  80. * All rights reserved.</center></h2>
  81. *
  82. * This software component is licensed by ST under BSD 3-Clause license,
  83. * the "License"; You may not use this file except in compliance with the
  84. * License. You may obtain a copy of the License at:
  85. * opensource.org/licenses/BSD-3-Clause
  86. *
  87. ******************************************************************************
  88. */
  89. /* Includes ------------------------------------------------------------------*/
  90. #include "stm32h7xx_hal.h"
  91. /** @addtogroup STM32H7xx_HAL_Driver
  92. * @{
  93. */
  94. #ifdef HAL_NOR_MODULE_ENABLED
  95. /** @defgroup NOR NOR
  96. * @brief NOR driver modules
  97. * @{
  98. */
  99. /* Private typedef -----------------------------------------------------------*/
  100. /* Private define ------------------------------------------------------------*/
  101. /** @defgroup NOR_Private_Defines NOR Private Defines
  102. * @{
  103. */
  104. /* Constants to define address to set to write a command */
  105. #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
  106. #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
  107. #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
  108. #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
  109. #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
  110. #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
  111. #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
  112. /* Constants to define data to program a command */
  113. #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
  114. #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
  115. #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
  116. #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
  117. #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
  118. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
  119. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
  120. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
  121. #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
  122. #define NOR_CMD_DATA_CFI (uint16_t)0x0098
  123. #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
  124. #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
  125. #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
  126. /* Mask on NOR STATUS REGISTER */
  127. #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
  128. #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
  129. /**
  130. * @}
  131. */
  132. /* Private macro -------------------------------------------------------------*/
  133. /* Private variables ---------------------------------------------------------*/
  134. /** @defgroup NOR_Private_Variables NOR Private Variables
  135. * @{
  136. */
  137. static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
  138. /**
  139. * @}
  140. */
  141. /* Private functions ---------------------------------------------------------*/
  142. /* Exported functions --------------------------------------------------------*/
  143. /** @defgroup NOR_Exported_Functions NOR Exported Functions
  144. * @{
  145. */
  146. /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
  147. * @brief Initialization and Configuration functions
  148. *
  149. @verbatim
  150. ==============================================================================
  151. ##### NOR Initialization and de_initialization functions #####
  152. ==============================================================================
  153. [..]
  154. This section provides functions allowing to initialize/de-initialize
  155. the NOR memory
  156. @endverbatim
  157. * @{
  158. */
  159. /**
  160. * @brief Perform the NOR memory Initialization sequence
  161. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  162. * the configuration information for NOR module.
  163. * @param Timing pointer to NOR control timing structure
  164. * @param ExtTiming pointer to NOR extended mode timing structure
  165. * @retval HAL status
  166. */
  167. HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
  168. {
  169. /* Check the NOR handle parameter */
  170. if (hnor == NULL)
  171. {
  172. return HAL_ERROR;
  173. }
  174. if (hnor->State == HAL_NOR_STATE_RESET)
  175. {
  176. /* Allocate lock resource and initialize it */
  177. hnor->Lock = HAL_UNLOCKED;
  178. #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
  179. if(hnor->MspInitCallback == NULL)
  180. {
  181. hnor->MspInitCallback = HAL_NOR_MspInit;
  182. }
  183. /* Init the low level hardware */
  184. hnor->MspInitCallback(hnor);
  185. #else
  186. /* Initialize the low level hardware (MSP) */
  187. HAL_NOR_MspInit(hnor);
  188. #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
  189. }
  190. /* Initialize NOR control Interface */
  191. (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
  192. /* Initialize NOR timing Interface */
  193. (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
  194. /* Initialize NOR extended mode timing Interface */
  195. (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
  196. /* Enable the NORSRAM device */
  197. __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
  198. /* Initialize NOR Memory Data Width*/
  199. if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
  200. {
  201. uwNORMemoryDataWidth = NOR_MEMORY_8B;
  202. }
  203. else
  204. {
  205. uwNORMemoryDataWidth = NOR_MEMORY_16B;
  206. }
  207. /* Enable FMC Peripheral */
  208. __FMC_ENABLE();
  209. /* Initialize the NOR controller state */
  210. hnor->State = HAL_NOR_STATE_READY;
  211. return HAL_OK;
  212. }
  213. /**
  214. * @brief Perform NOR memory De-Initialization sequence
  215. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  216. * the configuration information for NOR module.
  217. * @retval HAL status
  218. */
  219. HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
  220. {
  221. #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
  222. if(hnor->MspDeInitCallback == NULL)
  223. {
  224. hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
  225. }
  226. /* DeInit the low level hardware */
  227. hnor->MspDeInitCallback(hnor);
  228. #else
  229. /* De-Initialize the low level hardware (MSP) */
  230. HAL_NOR_MspDeInit(hnor);
  231. #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
  232. /* Configure the NOR registers with their reset values */
  233. (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
  234. /* Reset the NOR controller state */
  235. hnor->State = HAL_NOR_STATE_RESET;
  236. /* Release Lock */
  237. __HAL_UNLOCK(hnor);
  238. return HAL_OK;
  239. }
  240. /**
  241. * @brief NOR MSP Init
  242. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  243. * the configuration information for NOR module.
  244. * @retval None
  245. */
  246. __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
  247. {
  248. /* Prevent unused argument(s) compilation warning */
  249. UNUSED(hnor);
  250. /* NOTE : This function Should not be modified, when the callback is needed,
  251. the HAL_NOR_MspInit could be implemented in the user file
  252. */
  253. }
  254. /**
  255. * @brief NOR MSP DeInit
  256. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  257. * the configuration information for NOR module.
  258. * @retval None
  259. */
  260. __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
  261. {
  262. /* Prevent unused argument(s) compilation warning */
  263. UNUSED(hnor);
  264. /* NOTE : This function Should not be modified, when the callback is needed,
  265. the HAL_NOR_MspDeInit could be implemented in the user file
  266. */
  267. }
  268. /**
  269. * @brief NOR MSP Wait for Ready/Busy signal
  270. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  271. * the configuration information for NOR module.
  272. * @param Timeout Maximum timeout value
  273. * @retval None
  274. */
  275. __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
  276. {
  277. /* Prevent unused argument(s) compilation warning */
  278. UNUSED(hnor);
  279. UNUSED(Timeout);
  280. /* NOTE : This function Should not be modified, when the callback is needed,
  281. the HAL_NOR_MspWait could be implemented in the user file
  282. */
  283. }
  284. /**
  285. * @}
  286. */
  287. /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
  288. * @brief Input Output and memory control functions
  289. *
  290. @verbatim
  291. ==============================================================================
  292. ##### NOR Input and Output functions #####
  293. ==============================================================================
  294. [..]
  295. This section provides functions allowing to use and control the NOR memory
  296. @endverbatim
  297. * @{
  298. */
  299. /**
  300. * @brief Read NOR flash IDs
  301. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  302. * the configuration information for NOR module.
  303. * @param pNOR_ID pointer to NOR ID structure
  304. * @retval HAL status
  305. */
  306. HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
  307. {
  308. uint32_t deviceaddress;
  309. HAL_NOR_StateTypeDef state;
  310. /* Check the NOR controller state */
  311. state = hnor->State;
  312. if (state == HAL_NOR_STATE_BUSY)
  313. {
  314. return HAL_BUSY;
  315. }
  316. else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
  317. {
  318. /* Process Locked */
  319. __HAL_LOCK(hnor);
  320. /* Update the NOR controller state */
  321. hnor->State = HAL_NOR_STATE_BUSY;
  322. /* Select the NOR device address */
  323. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  324. {
  325. deviceaddress = NOR_MEMORY_ADRESS1;
  326. }
  327. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  328. {
  329. deviceaddress = NOR_MEMORY_ADRESS2;
  330. }
  331. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  332. {
  333. deviceaddress = NOR_MEMORY_ADRESS3;
  334. }
  335. else /* FMC_NORSRAM_BANK4 */
  336. {
  337. deviceaddress = NOR_MEMORY_ADRESS4;
  338. }
  339. /* Send read ID command */
  340. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  341. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  342. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
  343. /* Read the NOR IDs */
  344. pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
  345. pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
  346. pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
  347. pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
  348. /* Check the NOR controller state */
  349. hnor->State = state;
  350. /* Process unlocked */
  351. __HAL_UNLOCK(hnor);
  352. }
  353. else
  354. {
  355. return HAL_ERROR;
  356. }
  357. return HAL_OK;
  358. }
  359. /**
  360. * @brief Returns the NOR memory to Read mode.
  361. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  362. * the configuration information for NOR module.
  363. * @retval HAL status
  364. */
  365. HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
  366. {
  367. uint32_t deviceaddress;
  368. HAL_NOR_StateTypeDef state;
  369. /* Check the NOR controller state */
  370. state = hnor->State;
  371. if (state == HAL_NOR_STATE_BUSY)
  372. {
  373. return HAL_BUSY;
  374. }
  375. else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
  376. {
  377. /* Process Locked */
  378. __HAL_LOCK(hnor);
  379. /* Update the NOR controller state */
  380. hnor->State = HAL_NOR_STATE_BUSY;
  381. /* Select the NOR device address */
  382. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  383. {
  384. deviceaddress = NOR_MEMORY_ADRESS1;
  385. }
  386. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  387. {
  388. deviceaddress = NOR_MEMORY_ADRESS2;
  389. }
  390. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  391. {
  392. deviceaddress = NOR_MEMORY_ADRESS3;
  393. }
  394. else /* FMC_NORSRAM_BANK4 */
  395. {
  396. deviceaddress = NOR_MEMORY_ADRESS4;
  397. }
  398. NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
  399. /* Check the NOR controller state */
  400. hnor->State = state;
  401. /* Process unlocked */
  402. __HAL_UNLOCK(hnor);
  403. }
  404. else
  405. {
  406. return HAL_ERROR;
  407. }
  408. return HAL_OK;
  409. }
  410. /**
  411. * @brief Read data from NOR memory
  412. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  413. * the configuration information for NOR module.
  414. * @param pAddress pointer to Device address
  415. * @param pData pointer to read data
  416. * @retval HAL status
  417. */
  418. HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
  419. {
  420. uint32_t deviceaddress;
  421. HAL_NOR_StateTypeDef state;
  422. /* Check the NOR controller state */
  423. state = hnor->State;
  424. if (state == HAL_NOR_STATE_BUSY)
  425. {
  426. return HAL_BUSY;
  427. }
  428. else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
  429. {
  430. /* Process Locked */
  431. __HAL_LOCK(hnor);
  432. /* Update the NOR controller state */
  433. hnor->State = HAL_NOR_STATE_BUSY;
  434. /* Select the NOR device address */
  435. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  436. {
  437. deviceaddress = NOR_MEMORY_ADRESS1;
  438. }
  439. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  440. {
  441. deviceaddress = NOR_MEMORY_ADRESS2;
  442. }
  443. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  444. {
  445. deviceaddress = NOR_MEMORY_ADRESS3;
  446. }
  447. else /* FMC_NORSRAM_BANK4 */
  448. {
  449. deviceaddress = NOR_MEMORY_ADRESS4;
  450. }
  451. /* Send read data command */
  452. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  453. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  454. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
  455. /* Read the data */
  456. *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
  457. /* Check the NOR controller state */
  458. hnor->State = state;
  459. /* Process unlocked */
  460. __HAL_UNLOCK(hnor);
  461. }
  462. else
  463. {
  464. return HAL_ERROR;
  465. }
  466. return HAL_OK;
  467. }
  468. /**
  469. * @brief Program data to NOR memory
  470. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  471. * the configuration information for NOR module.
  472. * @param pAddress Device address
  473. * @param pData pointer to the data to write
  474. * @retval HAL status
  475. */
  476. HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
  477. {
  478. uint32_t deviceaddress;
  479. /* Check the NOR controller state */
  480. if (hnor->State == HAL_NOR_STATE_BUSY)
  481. {
  482. return HAL_BUSY;
  483. }
  484. else if (hnor->State == HAL_NOR_STATE_READY)
  485. {
  486. /* Process Locked */
  487. __HAL_LOCK(hnor);
  488. /* Update the NOR controller state */
  489. hnor->State = HAL_NOR_STATE_BUSY;
  490. /* Select the NOR device address */
  491. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  492. {
  493. deviceaddress = NOR_MEMORY_ADRESS1;
  494. }
  495. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  496. {
  497. deviceaddress = NOR_MEMORY_ADRESS2;
  498. }
  499. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  500. {
  501. deviceaddress = NOR_MEMORY_ADRESS3;
  502. }
  503. else /* FMC_NORSRAM_BANK4 */
  504. {
  505. deviceaddress = NOR_MEMORY_ADRESS4;
  506. }
  507. /* Send program data command */
  508. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  509. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  510. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
  511. /* Write the data */
  512. NOR_WRITE(pAddress, *pData);
  513. /* Check the NOR controller state */
  514. hnor->State = HAL_NOR_STATE_READY;
  515. /* Process unlocked */
  516. __HAL_UNLOCK(hnor);
  517. }
  518. else
  519. {
  520. return HAL_ERROR;
  521. }
  522. return HAL_OK;
  523. }
  524. /**
  525. * @brief Reads a half-word buffer from the NOR memory.
  526. * @param hnor pointer to the NOR handle
  527. * @param uwAddress NOR memory internal address to read from.
  528. * @param pData pointer to the buffer that receives the data read from the
  529. * NOR memory.
  530. * @param uwBufferSize number of Half word to read.
  531. * @retval HAL status
  532. */
  533. HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
  534. {
  535. uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
  536. uint16_t *data = pData;
  537. HAL_NOR_StateTypeDef state;
  538. /* Check the NOR controller state */
  539. state = hnor->State;
  540. if (state == HAL_NOR_STATE_BUSY)
  541. {
  542. return HAL_BUSY;
  543. }
  544. else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
  545. {
  546. /* Process Locked */
  547. __HAL_LOCK(hnor);
  548. /* Update the NOR controller state */
  549. hnor->State = HAL_NOR_STATE_BUSY;
  550. /* Select the NOR device address */
  551. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  552. {
  553. deviceaddress = NOR_MEMORY_ADRESS1;
  554. }
  555. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  556. {
  557. deviceaddress = NOR_MEMORY_ADRESS2;
  558. }
  559. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  560. {
  561. deviceaddress = NOR_MEMORY_ADRESS3;
  562. }
  563. else /* FMC_NORSRAM_BANK4 */
  564. {
  565. deviceaddress = NOR_MEMORY_ADRESS4;
  566. }
  567. /* Send read data command */
  568. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  569. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  570. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
  571. /* Read buffer */
  572. while (size > 0U)
  573. {
  574. *data = *(__IO uint16_t *)address;
  575. data++;
  576. address += 2U;
  577. size--;
  578. }
  579. /* Check the NOR controller state */
  580. hnor->State = state;
  581. /* Process unlocked */
  582. __HAL_UNLOCK(hnor);
  583. }
  584. else
  585. {
  586. return HAL_ERROR;
  587. }
  588. return HAL_OK;
  589. }
  590. /**
  591. * @brief Writes a half-word buffer to the NOR memory. This function must be used
  592. only with S29GL128P NOR memory.
  593. * @param hnor pointer to the NOR handle
  594. * @param uwAddress NOR memory internal start write address
  595. * @param pData pointer to source data buffer.
  596. * @param uwBufferSize Size of the buffer to write
  597. * @retval HAL status
  598. */
  599. HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
  600. {
  601. uint16_t *p_currentaddress;
  602. const uint16_t *p_endaddress;
  603. uint16_t *data = pData;
  604. uint32_t lastloadedaddress, deviceaddress;
  605. /* Check the NOR controller state */
  606. if (hnor->State == HAL_NOR_STATE_BUSY)
  607. {
  608. return HAL_BUSY;
  609. }
  610. else if (hnor->State == HAL_NOR_STATE_READY)
  611. {
  612. /* Process Locked */
  613. __HAL_LOCK(hnor);
  614. /* Update the NOR controller state */
  615. hnor->State = HAL_NOR_STATE_BUSY;
  616. /* Select the NOR device address */
  617. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  618. {
  619. deviceaddress = NOR_MEMORY_ADRESS1;
  620. }
  621. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  622. {
  623. deviceaddress = NOR_MEMORY_ADRESS2;
  624. }
  625. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  626. {
  627. deviceaddress = NOR_MEMORY_ADRESS3;
  628. }
  629. else /* FMC_NORSRAM_BANK4 */
  630. {
  631. deviceaddress = NOR_MEMORY_ADRESS4;
  632. }
  633. /* Initialize variables */
  634. p_currentaddress = (uint16_t *)(uwAddress);
  635. p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
  636. lastloadedaddress = uwAddress;
  637. /* Issue unlock command sequence */
  638. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  639. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  640. /* Write Buffer Load Command */
  641. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
  642. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
  643. /* Load Data into NOR Buffer */
  644. while (p_currentaddress <= p_endaddress)
  645. {
  646. /* Store last loaded address & data value (for polling) */
  647. lastloadedaddress = (uint32_t)p_currentaddress;
  648. NOR_WRITE(p_currentaddress, *data);
  649. data++;
  650. p_currentaddress ++;
  651. }
  652. NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
  653. /* Check the NOR controller state */
  654. hnor->State = HAL_NOR_STATE_READY;
  655. /* Process unlocked */
  656. __HAL_UNLOCK(hnor);
  657. }
  658. else
  659. {
  660. return HAL_ERROR;
  661. }
  662. return HAL_OK;
  663. }
  664. /**
  665. * @brief Erase the specified block of the NOR memory
  666. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  667. * the configuration information for NOR module.
  668. * @param BlockAddress Block to erase address
  669. * @param Address Device address
  670. * @retval HAL status
  671. */
  672. HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
  673. {
  674. uint32_t deviceaddress;
  675. /* Check the NOR controller state */
  676. if (hnor->State == HAL_NOR_STATE_BUSY)
  677. {
  678. return HAL_BUSY;
  679. }
  680. else if (hnor->State == HAL_NOR_STATE_READY)
  681. {
  682. /* Process Locked */
  683. __HAL_LOCK(hnor);
  684. /* Update the NOR controller state */
  685. hnor->State = HAL_NOR_STATE_BUSY;
  686. /* Select the NOR device address */
  687. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  688. {
  689. deviceaddress = NOR_MEMORY_ADRESS1;
  690. }
  691. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  692. {
  693. deviceaddress = NOR_MEMORY_ADRESS2;
  694. }
  695. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  696. {
  697. deviceaddress = NOR_MEMORY_ADRESS3;
  698. }
  699. else /* FMC_NORSRAM_BANK4 */
  700. {
  701. deviceaddress = NOR_MEMORY_ADRESS4;
  702. }
  703. /* Send block erase command sequence */
  704. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  705. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  706. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  707. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  708. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
  709. NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
  710. /* Check the NOR memory status and update the controller state */
  711. hnor->State = HAL_NOR_STATE_READY;
  712. /* Process unlocked */
  713. __HAL_UNLOCK(hnor);
  714. }
  715. else
  716. {
  717. return HAL_ERROR;
  718. }
  719. return HAL_OK;
  720. }
  721. /**
  722. * @brief Erase the entire NOR chip.
  723. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  724. * the configuration information for NOR module.
  725. * @param Address Device address
  726. * @retval HAL status
  727. */
  728. HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
  729. {
  730. uint32_t deviceaddress;
  731. UNUSED(Address);
  732. /* Check the NOR controller state */
  733. if (hnor->State == HAL_NOR_STATE_BUSY)
  734. {
  735. return HAL_BUSY;
  736. }
  737. else if (hnor->State == HAL_NOR_STATE_READY)
  738. {
  739. /* Process Locked */
  740. __HAL_LOCK(hnor);
  741. /* Update the NOR controller state */
  742. hnor->State = HAL_NOR_STATE_BUSY;
  743. /* Select the NOR device address */
  744. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  745. {
  746. deviceaddress = NOR_MEMORY_ADRESS1;
  747. }
  748. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  749. {
  750. deviceaddress = NOR_MEMORY_ADRESS2;
  751. }
  752. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  753. {
  754. deviceaddress = NOR_MEMORY_ADRESS3;
  755. }
  756. else /* FMC_NORSRAM_BANK4 */
  757. {
  758. deviceaddress = NOR_MEMORY_ADRESS4;
  759. }
  760. /* Send NOR chip erase command sequence */
  761. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  762. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  763. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  764. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  765. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
  766. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
  767. /* Check the NOR memory status and update the controller state */
  768. hnor->State = HAL_NOR_STATE_READY;
  769. /* Process unlocked */
  770. __HAL_UNLOCK(hnor);
  771. }
  772. else
  773. {
  774. return HAL_ERROR;
  775. }
  776. return HAL_OK;
  777. }
  778. /**
  779. * @brief Read NOR flash CFI IDs
  780. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  781. * the configuration information for NOR module.
  782. * @param pNOR_CFI pointer to NOR CFI IDs structure
  783. * @retval HAL status
  784. */
  785. HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
  786. {
  787. uint32_t deviceaddress;
  788. HAL_NOR_StateTypeDef state;
  789. /* Check the NOR controller state */
  790. state = hnor->State;
  791. if (state == HAL_NOR_STATE_BUSY)
  792. {
  793. return HAL_BUSY;
  794. }
  795. else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
  796. {
  797. /* Process Locked */
  798. __HAL_LOCK(hnor);
  799. /* Update the NOR controller state */
  800. hnor->State = HAL_NOR_STATE_BUSY;
  801. /* Select the NOR device address */
  802. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  803. {
  804. deviceaddress = NOR_MEMORY_ADRESS1;
  805. }
  806. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  807. {
  808. deviceaddress = NOR_MEMORY_ADRESS2;
  809. }
  810. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  811. {
  812. deviceaddress = NOR_MEMORY_ADRESS3;
  813. }
  814. else /* FMC_NORSRAM_BANK4 */
  815. {
  816. deviceaddress = NOR_MEMORY_ADRESS4;
  817. }
  818. /* Send read CFI query command */
  819. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
  820. /* read the NOR CFI information */
  821. pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
  822. pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
  823. pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
  824. pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
  825. /* Check the NOR controller state */
  826. hnor->State = state;
  827. /* Process unlocked */
  828. __HAL_UNLOCK(hnor);
  829. }
  830. else
  831. {
  832. return HAL_ERROR;
  833. }
  834. return HAL_OK;
  835. }
  836. #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
  837. /**
  838. * @brief Register a User NOR Callback
  839. * To be used instead of the weak (surcharged) predefined callback
  840. * @param hnor : NOR handle
  841. * @param CallbackId : ID of the callback to be registered
  842. * This parameter can be one of the following values:
  843. * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
  844. * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
  845. * @param pCallback : pointer to the Callback function
  846. * @retval status
  847. */
  848. HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
  849. {
  850. HAL_StatusTypeDef status = HAL_OK;
  851. HAL_NOR_StateTypeDef state;
  852. if(pCallback == NULL)
  853. {
  854. return HAL_ERROR;
  855. }
  856. /* Process locked */
  857. __HAL_LOCK(hnor);
  858. state = hnor->State;
  859. if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
  860. {
  861. switch (CallbackId)
  862. {
  863. case HAL_NOR_MSP_INIT_CB_ID :
  864. hnor->MspInitCallback = pCallback;
  865. break;
  866. case HAL_NOR_MSP_DEINIT_CB_ID :
  867. hnor->MspDeInitCallback = pCallback;
  868. break;
  869. default :
  870. /* update return status */
  871. status = HAL_ERROR;
  872. break;
  873. }
  874. }
  875. else
  876. {
  877. /* update return status */
  878. status = HAL_ERROR;
  879. }
  880. /* Release Lock */
  881. __HAL_UNLOCK(hnor);
  882. return status;
  883. }
  884. /**
  885. * @brief Unregister a User NOR Callback
  886. * NOR Callback is redirected to the weak (surcharged) predefined callback
  887. * @param hnor : NOR handle
  888. * @param CallbackId : ID of the callback to be unregistered
  889. * This parameter can be one of the following values:
  890. * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
  891. * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
  892. * @retval status
  893. */
  894. HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
  895. {
  896. HAL_StatusTypeDef status = HAL_OK;
  897. HAL_NOR_StateTypeDef state;
  898. /* Process locked */
  899. __HAL_LOCK(hnor);
  900. state = hnor->State;
  901. if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
  902. {
  903. switch (CallbackId)
  904. {
  905. case HAL_NOR_MSP_INIT_CB_ID :
  906. hnor->MspInitCallback = HAL_NOR_MspInit;
  907. break;
  908. case HAL_NOR_MSP_DEINIT_CB_ID :
  909. hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
  910. break;
  911. default :
  912. /* update return status */
  913. status = HAL_ERROR;
  914. break;
  915. }
  916. }
  917. else
  918. {
  919. /* update return status */
  920. status = HAL_ERROR;
  921. }
  922. /* Release Lock */
  923. __HAL_UNLOCK(hnor);
  924. return status;
  925. }
  926. #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
  927. /**
  928. * @}
  929. */
  930. /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
  931. * @brief management functions
  932. *
  933. @verbatim
  934. ==============================================================================
  935. ##### NOR Control functions #####
  936. ==============================================================================
  937. [..]
  938. This subsection provides a set of functions allowing to control dynamically
  939. the NOR interface.
  940. @endverbatim
  941. * @{
  942. */
  943. /**
  944. * @brief Enables dynamically NOR write operation.
  945. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  946. * the configuration information for NOR module.
  947. * @retval HAL status
  948. */
  949. HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
  950. {
  951. /* Check the NOR controller state */
  952. if(hnor->State == HAL_NOR_STATE_PROTECTED)
  953. {
  954. /* Process Locked */
  955. __HAL_LOCK(hnor);
  956. /* Update the NOR controller state */
  957. hnor->State = HAL_NOR_STATE_BUSY;
  958. /* Enable write operation */
  959. (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
  960. /* Update the NOR controller state */
  961. hnor->State = HAL_NOR_STATE_READY;
  962. /* Process unlocked */
  963. __HAL_UNLOCK(hnor);
  964. }
  965. else
  966. {
  967. return HAL_ERROR;
  968. }
  969. return HAL_OK;
  970. }
  971. /**
  972. * @brief Disables dynamically NOR write operation.
  973. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  974. * the configuration information for NOR module.
  975. * @retval HAL status
  976. */
  977. HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
  978. {
  979. /* Check the NOR controller state */
  980. if(hnor->State == HAL_NOR_STATE_READY)
  981. {
  982. /* Process Locked */
  983. __HAL_LOCK(hnor);
  984. /* Update the NOR controller state */
  985. hnor->State = HAL_NOR_STATE_BUSY;
  986. /* Disable write operation */
  987. (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
  988. /* Update the NOR controller state */
  989. hnor->State = HAL_NOR_STATE_PROTECTED;
  990. /* Process unlocked */
  991. __HAL_UNLOCK(hnor);
  992. }
  993. else
  994. {
  995. return HAL_ERROR;
  996. }
  997. return HAL_OK;
  998. }
  999. /**
  1000. * @}
  1001. */
  1002. /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
  1003. * @brief Peripheral State functions
  1004. *
  1005. @verbatim
  1006. ==============================================================================
  1007. ##### NOR State functions #####
  1008. ==============================================================================
  1009. [..]
  1010. This subsection permits to get in run-time the status of the NOR controller
  1011. and the data flow.
  1012. @endverbatim
  1013. * @{
  1014. */
  1015. /**
  1016. * @brief return the NOR controller state
  1017. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  1018. * the configuration information for NOR module.
  1019. * @retval NOR controller state
  1020. */
  1021. HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
  1022. {
  1023. return hnor->State;
  1024. }
  1025. /**
  1026. * @brief Returns the NOR operation status.
  1027. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  1028. * the configuration information for NOR module.
  1029. * @param Address Device address
  1030. * @param Timeout NOR programming Timeout
  1031. * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
  1032. * or HAL_NOR_STATUS_TIMEOUT
  1033. */
  1034. HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
  1035. {
  1036. HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
  1037. uint16_t tmpSR1, tmpSR2;
  1038. uint32_t tickstart;
  1039. /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
  1040. HAL_NOR_MspWait(hnor, Timeout);
  1041. /* Get the NOR memory operation status -------------------------------------*/
  1042. /* Get tick */
  1043. tickstart = HAL_GetTick();
  1044. while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
  1045. {
  1046. /* Check for the Timeout */
  1047. if (Timeout != HAL_MAX_DELAY)
  1048. {
  1049. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  1050. {
  1051. status = HAL_NOR_STATUS_TIMEOUT;
  1052. }
  1053. }
  1054. /* Read NOR status register (DQ6 and DQ5) */
  1055. tmpSR1 = *(__IO uint16_t *)Address;
  1056. tmpSR2 = *(__IO uint16_t *)Address;
  1057. /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
  1058. if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
  1059. {
  1060. return HAL_NOR_STATUS_SUCCESS ;
  1061. }
  1062. if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
  1063. {
  1064. status = HAL_NOR_STATUS_ONGOING;
  1065. }
  1066. tmpSR1 = *(__IO uint16_t *)Address;
  1067. tmpSR2 = *(__IO uint16_t *)Address;
  1068. /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
  1069. if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
  1070. {
  1071. return HAL_NOR_STATUS_SUCCESS;
  1072. }
  1073. if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
  1074. {
  1075. return HAL_NOR_STATUS_ERROR;
  1076. }
  1077. }
  1078. /* Return the operation status */
  1079. return status;
  1080. }
  1081. /**
  1082. * @}
  1083. */
  1084. /**
  1085. * @}
  1086. */
  1087. /**
  1088. * @}
  1089. */
  1090. #endif /* HAL_NOR_MODULE_ENABLED */
  1091. /**
  1092. * @}
  1093. */
  1094. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/