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  1. /**
  2. ******************************************************************************
  3. * @file stm32h7xx_hal_spi_ex.c
  4. * @author MCD Application Team
  5. * @brief Extended SPI HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * SPI peripheral extended functionalities :
  8. * + IO operation functions
  9. * + Peripheral Control functions
  10. *
  11. ******************************************************************************
  12. * @attention
  13. *
  14. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  15. * All rights reserved.</center></h2>
  16. *
  17. * This software component is licensed by ST under BSD 3-Clause license,
  18. * the "License"; You may not use this file except in compliance with the
  19. * License. You may obtain a copy of the License at:
  20. * opensource.org/licenses/BSD-3-Clause
  21. *
  22. ******************************************************************************
  23. */
  24. /* Includes ------------------------------------------------------------------*/
  25. #include "stm32h7xx_hal.h"
  26. /** @addtogroup STM32H7xx_HAL_Driver
  27. * @{
  28. */
  29. /** @defgroup SPIEx SPIEx
  30. * @brief SPI Extended HAL module driver
  31. * @{
  32. */
  33. #ifdef HAL_SPI_MODULE_ENABLED
  34. /* Private typedef -----------------------------------------------------------*/
  35. /* Private defines -----------------------------------------------------------*/
  36. /* Private macros ------------------------------------------------------------*/
  37. /* Private variables ---------------------------------------------------------*/
  38. /* Private function prototypes -----------------------------------------------*/
  39. /* Exported functions --------------------------------------------------------*/
  40. /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
  41. * @{
  42. */
  43. /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
  44. * @brief Data transfers functions
  45. *
  46. @verbatim
  47. ==============================================================================
  48. ##### IO operation functions #####
  49. ===============================================================================
  50. [..]
  51. This subsection provides a set of extended functions to manage the SPI
  52. data transfers.
  53. (#) SPIEx function:
  54. (++) HAL_SPIEx_FlushRxFifo()
  55. (++) HAL_SPIEx_FlushRxFifo()
  56. (++) HAL_SPIEx_EnableLockConfiguration()
  57. (++) HAL_SPIEx_ConfigureUnderrun()
  58. @endverbatim
  59. * @{
  60. */
  61. /**
  62. * @brief Flush the RX fifo.
  63. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
  64. * the configuration information for the specified SPI module.
  65. * @retval HAL status
  66. */
  67. HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
  68. {
  69. uint8_t count = 0;
  70. uint32_t itflag = hspi->Instance->SR;
  71. __IO uint32_t tmpreg;
  72. while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL))
  73. {
  74. count += (uint8_t)4UL;
  75. tmpreg = hspi->Instance->RXDR;
  76. UNUSED(tmpreg); /* To avoid GCC warning */
  77. if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
  78. {
  79. if (count > SPI_HIGHEND_FIFO_SIZE)
  80. {
  81. return HAL_TIMEOUT;
  82. }
  83. }
  84. else
  85. {
  86. if (count > SPI_LOWEND_FIFO_SIZE)
  87. {
  88. return HAL_TIMEOUT;
  89. }
  90. }
  91. }
  92. return HAL_OK;
  93. }
  94. /**
  95. * @brief Enable the Lock for the AF configuration of associated IOs
  96. * and write protect the Content of Configuration register 2
  97. * when SPI is enabled
  98. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
  99. * the configuration information for SPI module.
  100. * @retval None
  101. */
  102. HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
  103. {
  104. HAL_StatusTypeDef errorcode = HAL_OK;
  105. /* Process Locked */
  106. __HAL_LOCK(hspi);
  107. if (hspi->State != HAL_SPI_STATE_READY)
  108. {
  109. errorcode = HAL_BUSY;
  110. hspi->State = HAL_SPI_STATE_READY;
  111. /* Process Unlocked */
  112. __HAL_UNLOCK(hspi);
  113. return errorcode;
  114. }
  115. /* Check if the SPI is disabled to edit IOLOCK bit */
  116. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  117. {
  118. SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
  119. }
  120. else
  121. {
  122. /* Disable SPI peripheral */
  123. __HAL_SPI_DISABLE(hspi);
  124. SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
  125. /* Enable SPI peripheral */
  126. __HAL_SPI_ENABLE(hspi);
  127. }
  128. hspi->State = HAL_SPI_STATE_READY;
  129. /* Process Unlocked */
  130. __HAL_UNLOCK(hspi);
  131. return errorcode;
  132. }
  133. /**
  134. * @brief Configure the UNDERRUN condition and behavior of slave transmitter.
  135. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
  136. * the configuration information for SPI module.
  137. * @param UnderrunDetection : Detection of underrun condition at slave transmitter
  138. * This parameter can be a value of @ref SPI_Underrun_Detection.
  139. * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition
  140. * This parameter can be a value of @ref SPI_Underrun_Behaviour.
  141. * @retval None
  142. */
  143. HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
  144. {
  145. HAL_StatusTypeDef errorcode = HAL_OK;
  146. /* Process Locked */
  147. __HAL_LOCK(hspi);
  148. /* Check State and Insure that Underrun configuration is managed only by Salve */
  149. if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
  150. {
  151. errorcode = HAL_BUSY;
  152. hspi->State = HAL_SPI_STATE_READY;
  153. /* Process Unlocked */
  154. __HAL_UNLOCK(hspi);
  155. return errorcode;
  156. }
  157. /* Check the parameters */
  158. assert_param(IS_SPI_UNDERRUN_DETECTION(UnderrunDetection));
  159. assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
  160. /* Check if the SPI is disabled to edit CFG1 register */
  161. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  162. {
  163. /* Configure Underrun fields */
  164. MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
  165. MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
  166. }
  167. else
  168. {
  169. /* Disable SPI peripheral */
  170. __HAL_SPI_DISABLE(hspi);
  171. /* Configure Underrun fields */
  172. MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
  173. MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
  174. /* Enable SPI peripheral */
  175. __HAL_SPI_ENABLE(hspi);
  176. }
  177. hspi->State = HAL_SPI_STATE_READY;
  178. /* Process Unlocked */
  179. __HAL_UNLOCK(hspi);
  180. return errorcode;
  181. }
  182. /**
  183. * @}
  184. */
  185. /**
  186. * @}
  187. */
  188. #endif /* HAL_SPI_MODULE_ENABLED */
  189. /**
  190. * @}
  191. */
  192. /**
  193. * @}
  194. */
  195. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/