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  1. /**
  2. ******************************************************************************
  3. * @file stm32h7xx_hal_sram.c
  4. * @author MCD Application Team
  5. * @brief SRAM HAL module driver.
  6. * This file provides a generic firmware to drive SRAM memories
  7. * mounted as external device.
  8. *
  9. @verbatim
  10. ==============================================================================
  11. ##### How to use this driver #####
  12. ==============================================================================
  13. [..]
  14. This driver is a generic layered driver which contains a set of APIs used to
  15. control SRAM memories. It uses the FMC layer functions to interface
  16. with SRAM devices.
  17. The following sequence should be followed to configure the FMC to interface
  18. with SRAM/PSRAM memories:
  19. (#) Declare a SRAM_HandleTypeDef handle structure, for example:
  20. SRAM_HandleTypeDef hsram; and:
  21. (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
  22. values of the structure member.
  23. (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
  24. base register instance for NOR or SRAM device
  25. (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
  26. base register instance for NOR or SRAM extended mode
  27. (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
  28. mode timings; for example:
  29. FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
  30. and fill its fields with the allowed values of the structure member.
  31. (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
  32. performs the following sequence:
  33. (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
  34. (##) Control register configuration using the FMC NORSRAM interface function
  35. FMC_NORSRAM_Init()
  36. (##) Timing register configuration using the FMC NORSRAM interface function
  37. FMC_NORSRAM_Timing_Init()
  38. (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
  39. FMC_NORSRAM_Extended_Timing_Init()
  40. (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
  41. (#) At this stage you can perform read/write accesses from/to the memory connected
  42. to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
  43. following APIs:
  44. (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
  45. (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
  46. (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
  47. HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
  48. (#) You can continuously monitor the SRAM device HAL state by calling the function
  49. HAL_SRAM_GetState()
  50. *** Callback registration ***
  51. =============================================
  52. [..]
  53. The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
  54. allows the user to configure dynamically the driver callbacks.
  55. Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
  56. it allows to register following callbacks:
  57. (+) MspInitCallback : SRAM MspInit.
  58. (+) MspDeInitCallback : SRAM MspDeInit.
  59. This function takes as parameters the HAL peripheral handle, the Callback ID
  60. and a pointer to the user callback function.
  61. Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
  62. weak (surcharged) function. It allows to reset following callbacks:
  63. (+) MspInitCallback : SRAM MspInit.
  64. (+) MspDeInitCallback : SRAM MspDeInit.
  65. This function) takes as parameters the HAL peripheral handle and the Callback ID.
  66. By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
  67. all callbacks are reset to the corresponding legacy weak (surcharged) functions.
  68. Exception done for MspInit and MspDeInit callbacks that are respectively
  69. reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
  70. and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
  71. If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
  72. keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
  73. Callbacks can be registered/unregistered in READY state only.
  74. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
  75. in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
  76. during the Init/DeInit.
  77. In that case first register the MspInit/MspDeInit user callbacks
  78. using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
  79. or @ref HAL_SRAM_Init function.
  80. When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
  81. not defined, the callback registering feature is not available
  82. and weak (surcharged) callbacks are used.
  83. @endverbatim
  84. ******************************************************************************
  85. * @attention
  86. *
  87. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  88. * All rights reserved.</center></h2>
  89. *
  90. * This software component is licensed by ST under BSD 3-Clause license,
  91. * the "License"; You may not use this file except in compliance with the
  92. * License. You may obtain a copy of the License at:
  93. * opensource.org/licenses/BSD-3-Clause
  94. *
  95. ******************************************************************************
  96. */
  97. /* Includes ------------------------------------------------------------------*/
  98. #include "stm32h7xx_hal.h"
  99. /** @addtogroup STM32H7xx_HAL_Driver
  100. * @{
  101. */
  102. #ifdef HAL_SRAM_MODULE_ENABLED
  103. /** @defgroup SRAM SRAM
  104. * @brief SRAM driver modules
  105. * @{
  106. */
  107. /**
  108. @cond 0
  109. */
  110. /* Private typedef -----------------------------------------------------------*/
  111. /* Private define ------------------------------------------------------------*/
  112. /* Private macro -------------------------------------------------------------*/
  113. /* Private variables ---------------------------------------------------------*/
  114. /* Private function prototypes -----------------------------------------------*/
  115. static void SRAM_DMACplt (MDMA_HandleTypeDef *hmdma);
  116. static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
  117. static void SRAM_DMAError (MDMA_HandleTypeDef *hmdma);
  118. /**
  119. @endcond
  120. */
  121. /* Exported functions --------------------------------------------------------*/
  122. /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
  123. * @{
  124. */
  125. /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
  126. * @brief Initialization and Configuration functions.
  127. *
  128. @verbatim
  129. ==============================================================================
  130. ##### SRAM Initialization and de_initialization functions #####
  131. ==============================================================================
  132. [..] This section provides functions allowing to initialize/de-initialize
  133. the SRAM memory
  134. @endverbatim
  135. * @{
  136. */
  137. /**
  138. * @brief Performs the SRAM device initialization sequence
  139. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  140. * the configuration information for SRAM module.
  141. * @param Timing Pointer to SRAM control timing structure
  142. * @param ExtTiming Pointer to SRAM extended mode timing structure
  143. * @retval HAL status
  144. */
  145. HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
  146. {
  147. /* Check the SRAM handle parameter */
  148. if (hsram == NULL)
  149. {
  150. return HAL_ERROR;
  151. }
  152. if (hsram->State == HAL_SRAM_STATE_RESET)
  153. {
  154. /* Allocate lock resource and initialize it */
  155. hsram->Lock = HAL_UNLOCKED;
  156. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  157. if(hsram->MspInitCallback == NULL)
  158. {
  159. hsram->MspInitCallback = HAL_SRAM_MspInit;
  160. }
  161. hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
  162. hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
  163. /* Init the low level hardware */
  164. hsram->MspInitCallback(hsram);
  165. #else
  166. /* Initialize the low level hardware (MSP) */
  167. HAL_SRAM_MspInit(hsram);
  168. #endif
  169. }
  170. /* Initialize SRAM control Interface */
  171. (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
  172. /* Initialize SRAM timing Interface */
  173. (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
  174. /* Initialize SRAM extended mode timing Interface */
  175. (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
  176. /* Enable the NORSRAM device */
  177. __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
  178. /* Enable FMC Peripheral */
  179. __FMC_ENABLE();
  180. /* Initialize the SRAM controller state */
  181. hsram->State = HAL_SRAM_STATE_READY;
  182. return HAL_OK;
  183. }
  184. /**
  185. * @brief Performs the SRAM device De-initialization sequence.
  186. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  187. * the configuration information for SRAM module.
  188. * @retval HAL status
  189. */
  190. HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
  191. {
  192. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  193. if(hsram->MspDeInitCallback == NULL)
  194. {
  195. hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
  196. }
  197. /* DeInit the low level hardware */
  198. hsram->MspDeInitCallback(hsram);
  199. #else
  200. /* De-Initialize the low level hardware (MSP) */
  201. HAL_SRAM_MspDeInit(hsram);
  202. #endif
  203. /* Configure the SRAM registers with their reset values */
  204. (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
  205. /* Reset the SRAM controller state */
  206. hsram->State = HAL_SRAM_STATE_RESET;
  207. /* Release Lock */
  208. __HAL_UNLOCK(hsram);
  209. return HAL_OK;
  210. }
  211. /**
  212. * @brief SRAM MSP Init.
  213. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  214. * the configuration information for SRAM module.
  215. * @retval None
  216. */
  217. __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
  218. {
  219. /* Prevent unused argument(s) compilation warning */
  220. UNUSED(hsram);
  221. /* NOTE : This function Should not be modified, when the callback is needed,
  222. the HAL_SRAM_MspInit could be implemented in the user file
  223. */
  224. }
  225. /**
  226. * @brief SRAM MSP DeInit.
  227. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  228. * the configuration information for SRAM module.
  229. * @retval None
  230. */
  231. __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
  232. {
  233. /* Prevent unused argument(s) compilation warning */
  234. UNUSED(hsram);
  235. /* NOTE : This function Should not be modified, when the callback is needed,
  236. the HAL_SRAM_MspDeInit could be implemented in the user file
  237. */
  238. }
  239. /**
  240. * @brief DMA transfer complete callback.
  241. * @param hmdma pointer to a SRAM_HandleTypeDef structure that contains
  242. * the configuration information for SRAM module.
  243. * @retval None
  244. */
  245. __weak void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
  246. {
  247. /* Prevent unused argument(s) compilation warning */
  248. UNUSED(hmdma);
  249. /* NOTE : This function Should not be modified, when the callback is needed,
  250. the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
  251. */
  252. }
  253. /**
  254. * @brief DMA transfer complete error callback.
  255. * @param hmdma pointer to a SRAM_HandleTypeDef structure that contains
  256. * the configuration information for SRAM module.
  257. * @retval None
  258. */
  259. __weak void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
  260. {
  261. /* Prevent unused argument(s) compilation warning */
  262. UNUSED(hmdma);
  263. /* NOTE : This function Should not be modified, when the callback is needed,
  264. the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
  265. */
  266. }
  267. /**
  268. * @}
  269. */
  270. /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
  271. * @brief Input Output and memory control functions
  272. *
  273. @verbatim
  274. ==============================================================================
  275. ##### SRAM Input and Output functions #####
  276. ==============================================================================
  277. [..]
  278. This section provides functions allowing to use and control the SRAM memory
  279. @endverbatim
  280. * @{
  281. */
  282. /**
  283. * @brief Reads 8-bit buffer from SRAM memory.
  284. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  285. * the configuration information for SRAM module.
  286. * @param pAddress Pointer to read start address
  287. * @param pDstBuffer Pointer to destination buffer
  288. * @param BufferSize Size of the buffer to read from memory
  289. * @retval HAL status
  290. */
  291. HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
  292. {
  293. uint32_t size;
  294. __IO uint8_t *psramaddress = (uint8_t *)pAddress;
  295. uint8_t * pdestbuff = pDstBuffer;
  296. HAL_SRAM_StateTypeDef state = hsram->State;
  297. /* Check the SRAM controller state */
  298. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  299. {
  300. /* Process Locked */
  301. __HAL_LOCK(hsram);
  302. /* Update the SRAM controller state */
  303. hsram->State = HAL_SRAM_STATE_BUSY;
  304. /* Read data from memory */
  305. for (size = BufferSize; size != 0U; size--)
  306. {
  307. *pdestbuff = *psramaddress;
  308. pdestbuff++;
  309. psramaddress++;
  310. }
  311. /* Update the SRAM controller state */
  312. hsram->State = state;
  313. /* Process unlocked */
  314. __HAL_UNLOCK(hsram);
  315. }
  316. else
  317. {
  318. return HAL_ERROR;
  319. }
  320. return HAL_OK;
  321. }
  322. /**
  323. * @brief Writes 8-bit buffer to SRAM memory.
  324. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  325. * the configuration information for SRAM module.
  326. * @param pAddress Pointer to write start address
  327. * @param pSrcBuffer Pointer to source buffer to write
  328. * @param BufferSize Size of the buffer to write to memory
  329. * @retval HAL status
  330. */
  331. HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
  332. {
  333. uint32_t size;
  334. __IO uint8_t *psramaddress = (uint8_t *)pAddress;
  335. uint8_t * psrcbuff = pSrcBuffer;
  336. /* Check the SRAM controller state */
  337. if (hsram->State == HAL_SRAM_STATE_READY)
  338. {
  339. /* Process Locked */
  340. __HAL_LOCK(hsram);
  341. /* Update the SRAM controller state */
  342. hsram->State = HAL_SRAM_STATE_BUSY;
  343. /* Write data to memory */
  344. for (size = BufferSize; size != 0U; size--)
  345. {
  346. *psramaddress = *psrcbuff;
  347. psrcbuff++;
  348. psramaddress++;
  349. }
  350. /* Update the SRAM controller state */
  351. hsram->State = HAL_SRAM_STATE_READY;
  352. /* Process unlocked */
  353. __HAL_UNLOCK(hsram);
  354. }
  355. else
  356. {
  357. return HAL_ERROR;
  358. }
  359. return HAL_OK;
  360. }
  361. /**
  362. * @brief Reads 16-bit buffer from SRAM memory.
  363. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  364. * the configuration information for SRAM module.
  365. * @param pAddress Pointer to read start address
  366. * @param pDstBuffer Pointer to destination buffer
  367. * @param BufferSize Size of the buffer to read from memory
  368. * @retval HAL status
  369. */
  370. HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
  371. {
  372. uint32_t size;
  373. __IO uint32_t *psramaddress = pAddress;
  374. uint16_t *pdestbuff = pDstBuffer;
  375. uint8_t limit;
  376. HAL_SRAM_StateTypeDef state = hsram->State;
  377. /* Check the SRAM controller state */
  378. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  379. {
  380. /* Process Locked */
  381. __HAL_LOCK(hsram);
  382. /* Update the SRAM controller state */
  383. hsram->State = HAL_SRAM_STATE_BUSY;
  384. /* Check if the size is a 32-bits mulitple */
  385. limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
  386. /* Read data from memory */
  387. for (size = BufferSize; size != limit; size-=2U)
  388. {
  389. *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
  390. pdestbuff++;
  391. *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
  392. pdestbuff++;
  393. psramaddress++;
  394. }
  395. /* Read last 16-bits if size is not 32-bits multiple */
  396. if (limit != 0U)
  397. {
  398. *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
  399. }
  400. /* Update the SRAM controller state */
  401. hsram->State = state;
  402. /* Process unlocked */
  403. __HAL_UNLOCK(hsram);
  404. }
  405. else
  406. {
  407. return HAL_ERROR;
  408. }
  409. return HAL_OK;
  410. }
  411. /**
  412. * @brief Writes 16-bit buffer to SRAM memory.
  413. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  414. * the configuration information for SRAM module.
  415. * @param pAddress Pointer to write start address
  416. * @param pSrcBuffer Pointer to source buffer to write
  417. * @param BufferSize Size of the buffer to write to memory
  418. * @retval HAL status
  419. */
  420. HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
  421. {
  422. uint32_t size;
  423. __IO uint32_t *psramaddress = pAddress;
  424. uint16_t * psrcbuff = pSrcBuffer;
  425. uint8_t limit;
  426. /* Check the SRAM controller state */
  427. if (hsram->State == HAL_SRAM_STATE_READY)
  428. {
  429. /* Process Locked */
  430. __HAL_LOCK(hsram);
  431. /* Update the SRAM controller state */
  432. hsram->State = HAL_SRAM_STATE_BUSY;
  433. /* Check if the size is a 32-bits mulitple */
  434. limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
  435. /* Write data to memory */
  436. for (size = BufferSize; size != limit; size-=2U)
  437. {
  438. *psramaddress = (uint32_t)(*psrcbuff);
  439. psrcbuff++;
  440. *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
  441. psrcbuff++;
  442. psramaddress++;
  443. }
  444. /* Write last 16-bits if size is not 32-bits multiple */
  445. if (limit != 0U)
  446. {
  447. *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
  448. }
  449. /* Update the SRAM controller state */
  450. hsram->State = HAL_SRAM_STATE_READY;
  451. /* Process unlocked */
  452. __HAL_UNLOCK(hsram);
  453. }
  454. else
  455. {
  456. return HAL_ERROR;
  457. }
  458. return HAL_OK;
  459. }
  460. /**
  461. * @brief Reads 32-bit buffer from SRAM memory.
  462. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  463. * the configuration information for SRAM module.
  464. * @param pAddress Pointer to read start address
  465. * @param pDstBuffer Pointer to destination buffer
  466. * @param BufferSize Size of the buffer to read from memory
  467. * @retval HAL status
  468. */
  469. HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
  470. {
  471. uint32_t size;
  472. __IO uint32_t * psramaddress = pAddress;
  473. uint32_t * pdestbuff = pDstBuffer;
  474. HAL_SRAM_StateTypeDef state = hsram->State;
  475. /* Check the SRAM controller state */
  476. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  477. {
  478. /* Process Locked */
  479. __HAL_LOCK(hsram);
  480. /* Update the SRAM controller state */
  481. hsram->State = HAL_SRAM_STATE_BUSY;
  482. /* Read data from memory */
  483. for (size = BufferSize; size != 0U; size--)
  484. {
  485. *pdestbuff = *psramaddress;
  486. pdestbuff++;
  487. psramaddress++;
  488. }
  489. /* Update the SRAM controller state */
  490. hsram->State = state;
  491. /* Process unlocked */
  492. __HAL_UNLOCK(hsram);
  493. }
  494. else
  495. {
  496. return HAL_ERROR;
  497. }
  498. return HAL_OK;
  499. }
  500. /**
  501. * @brief Writes 32-bit buffer to SRAM memory.
  502. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  503. * the configuration information for SRAM module.
  504. * @param pAddress Pointer to write start address
  505. * @param pSrcBuffer Pointer to source buffer to write
  506. * @param BufferSize Size of the buffer to write to memory
  507. * @retval HAL status
  508. */
  509. HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
  510. {
  511. uint32_t size;
  512. __IO uint32_t * psramaddress = pAddress;
  513. uint32_t * psrcbuff = pSrcBuffer;
  514. /* Check the SRAM controller state */
  515. if (hsram->State == HAL_SRAM_STATE_READY)
  516. {
  517. /* Process Locked */
  518. __HAL_LOCK(hsram);
  519. /* Update the SRAM controller state */
  520. hsram->State = HAL_SRAM_STATE_BUSY;
  521. /* Write data to memory */
  522. for (size = BufferSize; size != 0U; size--)
  523. {
  524. *psramaddress = *psrcbuff;
  525. psrcbuff++;
  526. psramaddress++;
  527. }
  528. /* Update the SRAM controller state */
  529. hsram->State = HAL_SRAM_STATE_READY;
  530. /* Process unlocked */
  531. __HAL_UNLOCK(hsram);
  532. }
  533. else
  534. {
  535. return HAL_ERROR;
  536. }
  537. return HAL_OK;
  538. }
  539. /**
  540. * @brief Reads a Words data from the SRAM memory using DMA transfer.
  541. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  542. * the configuration information for SRAM module.
  543. * @param pAddress Pointer to read start address
  544. * @param pDstBuffer Pointer to destination buffer
  545. * @param BufferSize Size of the buffer to read from memory
  546. * @retval HAL status
  547. */
  548. HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
  549. {
  550. HAL_StatusTypeDef status;
  551. HAL_SRAM_StateTypeDef state = hsram->State;
  552. /* Check the SRAM controller state */
  553. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  554. {
  555. /* Process Locked */
  556. __HAL_LOCK(hsram);
  557. /* Update the SRAM controller state */
  558. hsram->State = HAL_SRAM_STATE_BUSY;
  559. /* Configure DMA user callbacks */
  560. if (state == HAL_SRAM_STATE_READY)
  561. {
  562. hsram->hmdma->XferCpltCallback = SRAM_DMACplt;
  563. }
  564. else
  565. {
  566. hsram->hmdma->XferCpltCallback = SRAM_DMACpltProt;
  567. }
  568. hsram->hmdma->XferErrorCallback = SRAM_DMAError;
  569. /* Enable the DMA Stream */
  570. status = HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
  571. /* Process unlocked */
  572. __HAL_UNLOCK(hsram);
  573. }
  574. else
  575. {
  576. return HAL_ERROR;
  577. }
  578. return status;
  579. }
  580. /**
  581. * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
  582. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  583. * the configuration information for SRAM module.
  584. * @param pAddress Pointer to write start address
  585. * @param pSrcBuffer Pointer to source buffer to write
  586. * @param BufferSize Size of the buffer to write to memory
  587. * @retval HAL status
  588. */
  589. HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
  590. {
  591. HAL_StatusTypeDef status;
  592. /* Check the SRAM controller state */
  593. if (hsram->State == HAL_SRAM_STATE_READY)
  594. {
  595. /* Process Locked */
  596. __HAL_LOCK(hsram);
  597. /* Update the SRAM controller state */
  598. hsram->State = HAL_SRAM_STATE_BUSY;
  599. /* Configure DMA user callbacks */
  600. hsram->hmdma->XferCpltCallback = SRAM_DMACplt;
  601. hsram->hmdma->XferErrorCallback = SRAM_DMAError;
  602. /* Enable the DMA Stream */
  603. status = HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
  604. /* Process unlocked */
  605. __HAL_UNLOCK(hsram);
  606. }
  607. else
  608. {
  609. return HAL_ERROR;
  610. }
  611. return status;
  612. }
  613. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  614. /**
  615. * @brief Register a User SRAM Callback
  616. * To be used instead of the weak (surcharged) predefined callback
  617. * @param hsram : SRAM handle
  618. * @param CallbackId : ID of the callback to be registered
  619. * This parameter can be one of the following values:
  620. * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
  621. * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
  622. * @param pCallback : pointer to the Callback function
  623. * @retval status
  624. */
  625. HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
  626. {
  627. HAL_StatusTypeDef status = HAL_OK;
  628. HAL_SRAM_StateTypeDef state;
  629. if(pCallback == NULL)
  630. {
  631. return HAL_ERROR;
  632. }
  633. /* Process locked */
  634. __HAL_LOCK(hsram);
  635. state = hsram->State;
  636. if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
  637. {
  638. switch (CallbackId)
  639. {
  640. case HAL_SRAM_MSP_INIT_CB_ID :
  641. hsram->MspInitCallback = pCallback;
  642. break;
  643. case HAL_SRAM_MSP_DEINIT_CB_ID :
  644. hsram->MspDeInitCallback = pCallback;
  645. break;
  646. default :
  647. /* update return status */
  648. status = HAL_ERROR;
  649. break;
  650. }
  651. }
  652. else
  653. {
  654. /* update return status */
  655. status = HAL_ERROR;
  656. }
  657. /* Release Lock */
  658. __HAL_UNLOCK(hsram);
  659. return status;
  660. }
  661. /**
  662. * @brief Unregister a User SRAM Callback
  663. * SRAM Callback is redirected to the weak (surcharged) predefined callback
  664. * @param hsram : SRAM handle
  665. * @param CallbackId : ID of the callback to be unregistered
  666. * This parameter can be one of the following values:
  667. * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
  668. * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
  669. * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
  670. * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
  671. * @retval status
  672. */
  673. HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
  674. {
  675. HAL_StatusTypeDef status = HAL_OK;
  676. HAL_SRAM_StateTypeDef state;
  677. /* Process locked */
  678. __HAL_LOCK(hsram);
  679. state = hsram->State;
  680. if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  681. {
  682. switch (CallbackId)
  683. {
  684. case HAL_SRAM_MSP_INIT_CB_ID :
  685. hsram->MspInitCallback = HAL_SRAM_MspInit;
  686. break;
  687. case HAL_SRAM_MSP_DEINIT_CB_ID :
  688. hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
  689. break;
  690. case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
  691. hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
  692. break;
  693. case HAL_SRAM_DMA_XFER_ERR_CB_ID :
  694. hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
  695. break;
  696. default :
  697. /* update return status */
  698. status = HAL_ERROR;
  699. break;
  700. }
  701. }
  702. else if(state == HAL_SRAM_STATE_RESET)
  703. {
  704. switch (CallbackId)
  705. {
  706. case HAL_SRAM_MSP_INIT_CB_ID :
  707. hsram->MspInitCallback = HAL_SRAM_MspInit;
  708. break;
  709. case HAL_SRAM_MSP_DEINIT_CB_ID :
  710. hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
  711. break;
  712. default :
  713. /* update return status */
  714. status = HAL_ERROR;
  715. break;
  716. }
  717. }
  718. else
  719. {
  720. /* update return status */
  721. status = HAL_ERROR;
  722. }
  723. /* Release Lock */
  724. __HAL_UNLOCK(hsram);
  725. return status;
  726. }
  727. /**
  728. * @brief Register a User SRAM Callback for DMA transfers
  729. * To be used instead of the weak (surcharged) predefined callback
  730. * @param hsram : SRAM handle
  731. * @param CallbackId : ID of the callback to be registered
  732. * This parameter can be one of the following values:
  733. * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
  734. * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
  735. * @param pCallback : pointer to the Callback function
  736. * @retval status
  737. */
  738. HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
  739. {
  740. HAL_StatusTypeDef status = HAL_OK;
  741. HAL_SRAM_StateTypeDef state;
  742. if(pCallback == NULL)
  743. {
  744. return HAL_ERROR;
  745. }
  746. /* Process locked */
  747. __HAL_LOCK(hsram);
  748. state = hsram->State;
  749. if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  750. {
  751. switch (CallbackId)
  752. {
  753. case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
  754. hsram->DmaXferCpltCallback = pCallback;
  755. break;
  756. case HAL_SRAM_DMA_XFER_ERR_CB_ID :
  757. hsram->DmaXferErrorCallback = pCallback;
  758. break;
  759. default :
  760. /* update return status */
  761. status = HAL_ERROR;
  762. break;
  763. }
  764. }
  765. else
  766. {
  767. /* update return status */
  768. status = HAL_ERROR;
  769. }
  770. /* Release Lock */
  771. __HAL_UNLOCK(hsram);
  772. return status;
  773. }
  774. #endif
  775. /**
  776. * @}
  777. */
  778. /** @defgroup SRAM_Exported_Functions_Group3 Control functions
  779. * @brief Control functions
  780. *
  781. @verbatim
  782. ==============================================================================
  783. ##### SRAM Control functions #####
  784. ==============================================================================
  785. [..]
  786. This subsection provides a set of functions allowing to control dynamically
  787. the SRAM interface.
  788. @endverbatim
  789. * @{
  790. */
  791. /**
  792. * @brief Enables dynamically SRAM write operation.
  793. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  794. * the configuration information for SRAM module.
  795. * @retval HAL status
  796. */
  797. HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
  798. {
  799. /* Check the SRAM controller state */
  800. if(hsram->State == HAL_SRAM_STATE_PROTECTED)
  801. {
  802. /* Process Locked */
  803. __HAL_LOCK(hsram);
  804. /* Update the SRAM controller state */
  805. hsram->State = HAL_SRAM_STATE_BUSY;
  806. /* Enable write operation */
  807. (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
  808. /* Update the SRAM controller state */
  809. hsram->State = HAL_SRAM_STATE_READY;
  810. /* Process unlocked */
  811. __HAL_UNLOCK(hsram);
  812. }
  813. else
  814. {
  815. return HAL_ERROR;
  816. }
  817. return HAL_OK;
  818. }
  819. /**
  820. * @brief Disables dynamically SRAM write operation.
  821. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  822. * the configuration information for SRAM module.
  823. * @retval HAL status
  824. */
  825. HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
  826. {
  827. /* Check the SRAM controller state */
  828. if(hsram->State == HAL_SRAM_STATE_READY)
  829. {
  830. /* Process Locked */
  831. __HAL_LOCK(hsram);
  832. /* Update the SRAM controller state */
  833. hsram->State = HAL_SRAM_STATE_BUSY;
  834. /* Disable write operation */
  835. (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
  836. /* Update the SRAM controller state */
  837. hsram->State = HAL_SRAM_STATE_PROTECTED;
  838. /* Process unlocked */
  839. __HAL_UNLOCK(hsram);
  840. }
  841. else
  842. {
  843. return HAL_ERROR;
  844. }
  845. return HAL_OK;
  846. }
  847. /**
  848. * @}
  849. */
  850. /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
  851. * @brief Peripheral State functions
  852. *
  853. @verbatim
  854. ==============================================================================
  855. ##### SRAM State functions #####
  856. ==============================================================================
  857. [..]
  858. This subsection permits to get in run-time the status of the SRAM controller
  859. and the data flow.
  860. @endverbatim
  861. * @{
  862. */
  863. /**
  864. * @brief Returns the SRAM controller state
  865. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  866. * the configuration information for SRAM module.
  867. * @retval HAL state
  868. */
  869. HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
  870. {
  871. return hsram->State;
  872. }
  873. /**
  874. * @}
  875. */
  876. /**
  877. * @}
  878. */
  879. /**
  880. @cond 0
  881. */
  882. /**
  883. * @brief MDMA SRAM process complete callback.
  884. * @param hmdma : MDMA handle
  885. * @retval None
  886. */
  887. static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
  888. {
  889. SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
  890. /* Disable the MDMA channel */
  891. __HAL_MDMA_DISABLE(hmdma);
  892. /* Update the SRAM controller state */
  893. hsram->State = HAL_SRAM_STATE_READY;
  894. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  895. hsram->DmaXferCpltCallback(hmdma);
  896. #else
  897. HAL_SRAM_DMA_XferCpltCallback(hmdma);
  898. #endif
  899. }
  900. /**
  901. * @brief MDMA SRAM process complete callback.
  902. * @param hmdma : MDMA handle
  903. * @retval None
  904. */
  905. static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
  906. {
  907. SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
  908. /* Disable the MDMA channel */
  909. __HAL_MDMA_DISABLE(hmdma);
  910. /* Update the SRAM controller state */
  911. hsram->State = HAL_SRAM_STATE_PROTECTED;
  912. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  913. hsram->DmaXferCpltCallback(hmdma);
  914. #else
  915. HAL_SRAM_DMA_XferCpltCallback(hmdma);
  916. #endif
  917. }
  918. /**
  919. * @brief MDMA SRAM error callback.
  920. * @param hmdma : MDMA handle
  921. * @retval None
  922. */
  923. static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma)
  924. {
  925. SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
  926. /* Disable the MDMA channel */
  927. __HAL_MDMA_DISABLE(hmdma);
  928. /* Update the SRAM controller state */
  929. hsram->State = HAL_SRAM_STATE_ERROR;
  930. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  931. hsram->DmaXferErrorCallback(hmdma);
  932. #else
  933. HAL_SRAM_DMA_XferErrorCallback(hmdma);
  934. #endif
  935. }
  936. /**
  937. @endcond
  938. */
  939. /**
  940. * @}
  941. */
  942. #endif /* HAL_SRAM_MODULE_ENABLED */
  943. /**
  944. * @}
  945. */
  946. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/