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  1. /**
  2. ******************************************************************************
  3. * @file stm32h7xx_ll_tim.c
  4. * @author MCD Application Team
  5. * @brief TIM LL module driver.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. #if defined(USE_FULL_LL_DRIVER)
  20. /* Includes ------------------------------------------------------------------*/
  21. #include "stm32h7xx_ll_tim.h"
  22. #include "stm32h7xx_ll_bus.h"
  23. #ifdef USE_FULL_ASSERT
  24. #include "stm32_assert.h"
  25. #else
  26. #define assert_param(expr) ((void)0U)
  27. #endif /* USE_FULL_ASSERT */
  28. /** @addtogroup STM32H7xx_LL_Driver
  29. * @{
  30. */
  31. #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
  32. /** @addtogroup TIM_LL
  33. * @{
  34. */
  35. /* Private types -------------------------------------------------------------*/
  36. /* Private variables ---------------------------------------------------------*/
  37. /* Private constants ---------------------------------------------------------*/
  38. /* Private macros ------------------------------------------------------------*/
  39. /** @addtogroup TIM_LL_Private_Macros
  40. * @{
  41. */
  42. #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  43. || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  44. || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  45. || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  46. || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  47. #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  48. || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  49. || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  50. #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  51. || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  52. || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  53. || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  54. || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  55. || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  56. || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  57. || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
  58. || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
  59. || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
  60. || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
  61. || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
  62. || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
  63. || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
  64. #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  65. || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  66. #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  67. || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  68. #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  69. || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  70. #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  71. || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  72. || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  73. #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  74. || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
  75. || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
  76. || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
  77. #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
  78. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
  79. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
  80. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
  81. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
  82. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
  83. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
  84. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
  85. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
  86. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
  87. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
  88. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
  89. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
  90. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
  91. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
  92. || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
  93. #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  94. || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
  95. || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
  96. #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
  97. || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
  98. || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
  99. #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  100. || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
  101. #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
  102. || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
  103. #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
  104. || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
  105. #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
  106. || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
  107. || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
  108. || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
  109. #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
  110. || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
  111. #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
  112. || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
  113. #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
  114. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
  115. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
  116. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
  117. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
  118. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
  119. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
  120. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
  121. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
  122. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
  123. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
  124. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
  125. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
  126. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
  127. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
  128. || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
  129. #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
  130. || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
  131. #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
  132. || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
  133. #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
  134. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
  135. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
  136. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
  137. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
  138. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
  139. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
  140. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
  141. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
  142. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
  143. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
  144. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
  145. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
  146. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
  147. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
  148. || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
  149. #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
  150. || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
  151. /**
  152. * @}
  153. */
  154. /* Private function prototypes -----------------------------------------------*/
  155. /** @defgroup TIM_LL_Private_Functions TIM Private Functions
  156. * @{
  157. */
  158. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  159. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  160. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  161. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  162. static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  163. static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  164. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  165. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  166. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  167. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  168. /**
  169. * @}
  170. */
  171. /* Exported functions --------------------------------------------------------*/
  172. /** @addtogroup TIM_LL_Exported_Functions
  173. * @{
  174. */
  175. /** @addtogroup TIM_LL_EF_Init
  176. * @{
  177. */
  178. /**
  179. * @brief Set TIMx registers to their reset values.
  180. * @param TIMx Timer instance
  181. * @retval An ErrorStatus enumeration value:
  182. * - SUCCESS: TIMx registers are de-initialized
  183. * - ERROR: invalid TIMx instance
  184. */
  185. ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
  186. {
  187. ErrorStatus result = SUCCESS;
  188. /* Check the parameters */
  189. assert_param(IS_TIM_INSTANCE(TIMx));
  190. if (TIMx == TIM1)
  191. {
  192. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
  193. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
  194. }
  195. #if defined(TIM2)
  196. else if (TIMx == TIM2)
  197. {
  198. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
  199. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
  200. }
  201. #endif
  202. #if defined(TIM3)
  203. else if (TIMx == TIM3)
  204. {
  205. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
  206. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
  207. }
  208. #endif
  209. #if defined(TIM4)
  210. else if (TIMx == TIM4)
  211. {
  212. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
  213. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
  214. }
  215. #endif
  216. #if defined(TIM5)
  217. else if (TIMx == TIM5)
  218. {
  219. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
  220. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
  221. }
  222. #endif
  223. #if defined(TIM6)
  224. else if (TIMx == TIM6)
  225. {
  226. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
  227. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
  228. }
  229. #endif
  230. #if defined (TIM7)
  231. else if (TIMx == TIM7)
  232. {
  233. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
  234. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
  235. }
  236. #endif
  237. #if defined(TIM8)
  238. else if (TIMx == TIM8)
  239. {
  240. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
  241. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
  242. }
  243. #endif
  244. #if defined(TIM12)
  245. else if (TIMx == TIM12)
  246. {
  247. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
  248. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
  249. }
  250. #endif
  251. #if defined(TIM13)
  252. else if (TIMx == TIM13)
  253. {
  254. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
  255. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
  256. }
  257. #endif
  258. #if defined(TIM14)
  259. else if (TIMx == TIM14)
  260. {
  261. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
  262. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
  263. }
  264. #endif
  265. #if defined(TIM15)
  266. else if (TIMx == TIM15)
  267. {
  268. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
  269. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
  270. }
  271. #endif
  272. #if defined(TIM16)
  273. else if (TIMx == TIM16)
  274. {
  275. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
  276. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
  277. }
  278. #endif
  279. #if defined(TIM17)
  280. else if (TIMx == TIM17)
  281. {
  282. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
  283. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
  284. }
  285. #endif
  286. else
  287. {
  288. result = ERROR;
  289. }
  290. return result;
  291. }
  292. /**
  293. * @brief Set the fields of the time base unit configuration data structure
  294. * to their default values.
  295. * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
  296. * @retval None
  297. */
  298. void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
  299. {
  300. /* Set the default configuration */
  301. TIM_InitStruct->Prescaler = (uint16_t)0x0000;
  302. TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
  303. TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
  304. TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
  305. TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
  306. }
  307. /**
  308. * @brief Configure the TIMx time base unit.
  309. * @param TIMx Timer Instance
  310. * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
  311. * @retval An ErrorStatus enumeration value:
  312. * - SUCCESS: TIMx registers are de-initialized
  313. * - ERROR: not applicable
  314. */
  315. ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
  316. {
  317. uint32_t tmpcr1;
  318. /* Check the parameters */
  319. assert_param(IS_TIM_INSTANCE(TIMx));
  320. assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
  321. assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
  322. tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
  323. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  324. {
  325. /* Select the Counter Mode */
  326. MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
  327. }
  328. if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  329. {
  330. /* Set the clock division */
  331. MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
  332. }
  333. /* Write to TIMx CR1 */
  334. LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
  335. /* Set the Autoreload value */
  336. LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
  337. /* Set the Prescaler value */
  338. LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
  339. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  340. {
  341. /* Set the Repetition Counter value */
  342. LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
  343. }
  344. /* Generate an update event to reload the Prescaler
  345. and the repetition counter value (if applicable) immediately */
  346. LL_TIM_GenerateEvent_UPDATE(TIMx);
  347. return SUCCESS;
  348. }
  349. /**
  350. * @brief Set the fields of the TIMx output channel configuration data
  351. * structure to their default values.
  352. * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
  353. * @retval None
  354. */
  355. void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  356. {
  357. /* Set the default configuration */
  358. TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
  359. TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
  360. TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
  361. TIM_OC_InitStruct->CompareValue = 0x00000000U;
  362. TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
  363. TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
  364. TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
  365. TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
  366. }
  367. /**
  368. * @brief Configure the TIMx output channel.
  369. * @param TIMx Timer Instance
  370. * @param Channel This parameter can be one of the following values:
  371. * @arg @ref LL_TIM_CHANNEL_CH1
  372. * @arg @ref LL_TIM_CHANNEL_CH2
  373. * @arg @ref LL_TIM_CHANNEL_CH3
  374. * @arg @ref LL_TIM_CHANNEL_CH4
  375. * @arg @ref LL_TIM_CHANNEL_CH5
  376. * @arg @ref LL_TIM_CHANNEL_CH6
  377. * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
  378. * @retval An ErrorStatus enumeration value:
  379. * - SUCCESS: TIMx output channel is initialized
  380. * - ERROR: TIMx output channel is not initialized
  381. */
  382. ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  383. {
  384. ErrorStatus result = ERROR;
  385. switch (Channel)
  386. {
  387. case LL_TIM_CHANNEL_CH1:
  388. result = OC1Config(TIMx, TIM_OC_InitStruct);
  389. break;
  390. case LL_TIM_CHANNEL_CH2:
  391. result = OC2Config(TIMx, TIM_OC_InitStruct);
  392. break;
  393. case LL_TIM_CHANNEL_CH3:
  394. result = OC3Config(TIMx, TIM_OC_InitStruct);
  395. break;
  396. case LL_TIM_CHANNEL_CH4:
  397. result = OC4Config(TIMx, TIM_OC_InitStruct);
  398. break;
  399. case LL_TIM_CHANNEL_CH5:
  400. result = OC5Config(TIMx, TIM_OC_InitStruct);
  401. break;
  402. case LL_TIM_CHANNEL_CH6:
  403. result = OC6Config(TIMx, TIM_OC_InitStruct);
  404. break;
  405. default:
  406. break;
  407. }
  408. return result;
  409. }
  410. /**
  411. * @brief Set the fields of the TIMx input channel configuration data
  412. * structure to their default values.
  413. * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
  414. * @retval None
  415. */
  416. void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  417. {
  418. /* Set the default configuration */
  419. TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
  420. TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  421. TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
  422. TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
  423. }
  424. /**
  425. * @brief Configure the TIMx input channel.
  426. * @param TIMx Timer Instance
  427. * @param Channel This parameter can be one of the following values:
  428. * @arg @ref LL_TIM_CHANNEL_CH1
  429. * @arg @ref LL_TIM_CHANNEL_CH2
  430. * @arg @ref LL_TIM_CHANNEL_CH3
  431. * @arg @ref LL_TIM_CHANNEL_CH4
  432. * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
  433. * @retval An ErrorStatus enumeration value:
  434. * - SUCCESS: TIMx output channel is initialized
  435. * - ERROR: TIMx output channel is not initialized
  436. */
  437. ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
  438. {
  439. ErrorStatus result = ERROR;
  440. switch (Channel)
  441. {
  442. case LL_TIM_CHANNEL_CH1:
  443. result = IC1Config(TIMx, TIM_IC_InitStruct);
  444. break;
  445. case LL_TIM_CHANNEL_CH2:
  446. result = IC2Config(TIMx, TIM_IC_InitStruct);
  447. break;
  448. case LL_TIM_CHANNEL_CH3:
  449. result = IC3Config(TIMx, TIM_IC_InitStruct);
  450. break;
  451. case LL_TIM_CHANNEL_CH4:
  452. result = IC4Config(TIMx, TIM_IC_InitStruct);
  453. break;
  454. default:
  455. break;
  456. }
  457. return result;
  458. }
  459. /**
  460. * @brief Fills each TIM_EncoderInitStruct field with its default value
  461. * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
  462. * @retval None
  463. */
  464. void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  465. {
  466. /* Set the default configuration */
  467. TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
  468. TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
  469. TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  470. TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
  471. TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
  472. TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
  473. TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  474. TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
  475. TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
  476. }
  477. /**
  478. * @brief Configure the encoder interface of the timer instance.
  479. * @param TIMx Timer Instance
  480. * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
  481. * @retval An ErrorStatus enumeration value:
  482. * - SUCCESS: TIMx registers are de-initialized
  483. * - ERROR: not applicable
  484. */
  485. ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  486. {
  487. uint32_t tmpccmr1;
  488. uint32_t tmpccer;
  489. /* Check the parameters */
  490. assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
  491. assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
  492. assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
  493. assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
  494. assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
  495. assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
  496. assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
  497. assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
  498. assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
  499. assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
  500. /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  501. TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
  502. /* Get the TIMx CCMR1 register value */
  503. tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  504. /* Get the TIMx CCER register value */
  505. tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  506. /* Configure TI1 */
  507. tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
  508. tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
  509. tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
  510. tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
  511. /* Configure TI2 */
  512. tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
  513. tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
  514. tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
  515. tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
  516. /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
  517. tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
  518. tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
  519. tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
  520. tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
  521. /* Set encoder mode */
  522. LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
  523. /* Write to TIMx CCMR1 */
  524. LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  525. /* Write to TIMx CCER */
  526. LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  527. return SUCCESS;
  528. }
  529. /**
  530. * @brief Set the fields of the TIMx Hall sensor interface configuration data
  531. * structure to their default values.
  532. * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
  533. * @retval None
  534. */
  535. void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
  536. {
  537. /* Set the default configuration */
  538. TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
  539. TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
  540. TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
  541. TIM_HallSensorInitStruct->CommutationDelay = 0U;
  542. }
  543. /**
  544. * @brief Configure the Hall sensor interface of the timer instance.
  545. * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
  546. * to the TI1 input channel
  547. * @note TIMx slave mode controller is configured in reset mode.
  548. Selected internal trigger is TI1F_ED.
  549. * @note Channel 1 is configured as input, IC1 is mapped on TRC.
  550. * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
  551. * between 2 changes on the inputs. It gives information about motor speed.
  552. * @note Channel 2 is configured in output PWM 2 mode.
  553. * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
  554. * @note OC2REF is selected as trigger output on TRGO.
  555. * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
  556. * when TIMx operates in Hall sensor interface mode.
  557. * @param TIMx Timer Instance
  558. * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
  559. * @retval An ErrorStatus enumeration value:
  560. * - SUCCESS: TIMx registers are de-initialized
  561. * - ERROR: not applicable
  562. */
  563. ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
  564. {
  565. uint32_t tmpcr2;
  566. uint32_t tmpccmr1;
  567. uint32_t tmpccer;
  568. uint32_t tmpsmcr;
  569. /* Check the parameters */
  570. assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
  571. assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
  572. assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
  573. assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
  574. /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  575. TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
  576. /* Get the TIMx CR2 register value */
  577. tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  578. /* Get the TIMx CCMR1 register value */
  579. tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  580. /* Get the TIMx CCER register value */
  581. tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  582. /* Get the TIMx SMCR register value */
  583. tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
  584. /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
  585. tmpcr2 |= TIM_CR2_TI1S;
  586. /* OC2REF signal is used as trigger output (TRGO) */
  587. tmpcr2 |= LL_TIM_TRGO_OC2REF;
  588. /* Configure the slave mode controller */
  589. tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
  590. tmpsmcr |= LL_TIM_TS_TI1F_ED;
  591. tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
  592. /* Configure input channel 1 */
  593. tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
  594. tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
  595. tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
  596. tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
  597. /* Configure input channel 2 */
  598. tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
  599. tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
  600. /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
  601. tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
  602. tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
  603. tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
  604. /* Write to TIMx CR2 */
  605. LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  606. /* Write to TIMx SMCR */
  607. LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
  608. /* Write to TIMx CCMR1 */
  609. LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  610. /* Write to TIMx CCER */
  611. LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  612. /* Write to TIMx CCR2 */
  613. LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
  614. return SUCCESS;
  615. }
  616. /**
  617. * @brief Set the fields of the Break and Dead Time configuration data structure
  618. * to their default values.
  619. * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
  620. * @retval None
  621. */
  622. void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
  623. {
  624. /* Set the default configuration */
  625. TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
  626. TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
  627. TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
  628. TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
  629. TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
  630. TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
  631. TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
  632. TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
  633. TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
  634. TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
  635. TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
  636. }
  637. /**
  638. * @brief Configure the Break and Dead Time feature of the timer instance.
  639. * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
  640. * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
  641. * can be necessary to configure all of them during the first write access to
  642. * the TIMx_BDTR register.
  643. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  644. * a timer instance provides a break input.
  645. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
  646. * a timer instance provides a second break input.
  647. * @param TIMx Timer Instance
  648. * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
  649. * @retval An ErrorStatus enumeration value:
  650. * - SUCCESS: Break and Dead Time is initialized
  651. * - ERROR: not applicable
  652. */
  653. ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
  654. {
  655. uint32_t tmpbdtr = 0;
  656. /* Check the parameters */
  657. assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
  658. assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
  659. assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
  660. assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
  661. assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
  662. assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
  663. assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
  664. /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
  665. the OSSI State, the dead time value and the Automatic Output Enable Bit */
  666. /* Set the BDTR bits */
  667. MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
  668. MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
  669. MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
  670. MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
  671. MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
  672. MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
  673. MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
  674. MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
  675. if (IS_TIM_ADVANCED_INSTANCE(TIMx))
  676. {
  677. assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
  678. MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
  679. }
  680. if (IS_TIM_BKIN2_INSTANCE(TIMx))
  681. {
  682. assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
  683. assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
  684. assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
  685. /* Set the BREAK2 input related BDTR bit-fields */
  686. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
  687. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
  688. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
  689. }
  690. /* Set TIMx_BDTR */
  691. LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
  692. return SUCCESS;
  693. }
  694. /**
  695. * @}
  696. */
  697. /**
  698. * @}
  699. */
  700. /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
  701. * @brief Private functions
  702. * @{
  703. */
  704. /**
  705. * @brief Configure the TIMx output channel 1.
  706. * @param TIMx Timer Instance
  707. * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
  708. * @retval An ErrorStatus enumeration value:
  709. * - SUCCESS: TIMx registers are de-initialized
  710. * - ERROR: not applicable
  711. */
  712. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  713. {
  714. uint32_t tmpccmr1;
  715. uint32_t tmpccer;
  716. uint32_t tmpcr2;
  717. /* Check the parameters */
  718. assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  719. assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  720. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  721. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  722. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  723. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  724. /* Disable the Channel 1: Reset the CC1E Bit */
  725. CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
  726. /* Get the TIMx CCER register value */
  727. tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  728. /* Get the TIMx CR2 register value */
  729. tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  730. /* Get the TIMx CCMR1 register value */
  731. tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  732. /* Reset Capture/Compare selection Bits */
  733. CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
  734. /* Set the Output Compare Mode */
  735. MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
  736. /* Set the Output Compare Polarity */
  737. MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
  738. /* Set the Output State */
  739. MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
  740. if (IS_TIM_BREAK_INSTANCE(TIMx))
  741. {
  742. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  743. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  744. /* Set the complementary output Polarity */
  745. MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
  746. /* Set the complementary output State */
  747. MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
  748. /* Set the Output Idle state */
  749. MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
  750. /* Set the complementary output Idle state */
  751. MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
  752. }
  753. /* Write to TIMx CR2 */
  754. LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  755. /* Write to TIMx CCMR1 */
  756. LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  757. /* Set the Capture Compare Register value */
  758. LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
  759. /* Write to TIMx CCER */
  760. LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  761. return SUCCESS;
  762. }
  763. /**
  764. * @brief Configure the TIMx output channel 2.
  765. * @param TIMx Timer Instance
  766. * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
  767. * @retval An ErrorStatus enumeration value:
  768. * - SUCCESS: TIMx registers are de-initialized
  769. * - ERROR: not applicable
  770. */
  771. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  772. {
  773. uint32_t tmpccmr1;
  774. uint32_t tmpccer;
  775. uint32_t tmpcr2;
  776. /* Check the parameters */
  777. assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  778. assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  779. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  780. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  781. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  782. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  783. /* Disable the Channel 2: Reset the CC2E Bit */
  784. CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
  785. /* Get the TIMx CCER register value */
  786. tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  787. /* Get the TIMx CR2 register value */
  788. tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  789. /* Get the TIMx CCMR1 register value */
  790. tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  791. /* Reset Capture/Compare selection Bits */
  792. CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
  793. /* Select the Output Compare Mode */
  794. MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
  795. /* Set the Output Compare Polarity */
  796. MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
  797. /* Set the Output State */
  798. MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
  799. if (IS_TIM_BREAK_INSTANCE(TIMx))
  800. {
  801. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  802. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  803. /* Set the complementary output Polarity */
  804. MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
  805. /* Set the complementary output State */
  806. MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
  807. /* Set the Output Idle state */
  808. MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
  809. /* Set the complementary output Idle state */
  810. MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
  811. }
  812. /* Write to TIMx CR2 */
  813. LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  814. /* Write to TIMx CCMR1 */
  815. LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  816. /* Set the Capture Compare Register value */
  817. LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
  818. /* Write to TIMx CCER */
  819. LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  820. return SUCCESS;
  821. }
  822. /**
  823. * @brief Configure the TIMx output channel 3.
  824. * @param TIMx Timer Instance
  825. * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
  826. * @retval An ErrorStatus enumeration value:
  827. * - SUCCESS: TIMx registers are de-initialized
  828. * - ERROR: not applicable
  829. */
  830. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  831. {
  832. uint32_t tmpccmr2;
  833. uint32_t tmpccer;
  834. uint32_t tmpcr2;
  835. /* Check the parameters */
  836. assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  837. assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  838. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  839. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  840. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  841. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  842. /* Disable the Channel 3: Reset the CC3E Bit */
  843. CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
  844. /* Get the TIMx CCER register value */
  845. tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  846. /* Get the TIMx CR2 register value */
  847. tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  848. /* Get the TIMx CCMR2 register value */
  849. tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  850. /* Reset Capture/Compare selection Bits */
  851. CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
  852. /* Select the Output Compare Mode */
  853. MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
  854. /* Set the Output Compare Polarity */
  855. MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
  856. /* Set the Output State */
  857. MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
  858. if (IS_TIM_BREAK_INSTANCE(TIMx))
  859. {
  860. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  861. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  862. /* Set the complementary output Polarity */
  863. MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
  864. /* Set the complementary output State */
  865. MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
  866. /* Set the Output Idle state */
  867. MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
  868. /* Set the complementary output Idle state */
  869. MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
  870. }
  871. /* Write to TIMx CR2 */
  872. LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  873. /* Write to TIMx CCMR2 */
  874. LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  875. /* Set the Capture Compare Register value */
  876. LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
  877. /* Write to TIMx CCER */
  878. LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  879. return SUCCESS;
  880. }
  881. /**
  882. * @brief Configure the TIMx output channel 4.
  883. * @param TIMx Timer Instance
  884. * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
  885. * @retval An ErrorStatus enumeration value:
  886. * - SUCCESS: TIMx registers are de-initialized
  887. * - ERROR: not applicable
  888. */
  889. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  890. {
  891. uint32_t tmpccmr2;
  892. uint32_t tmpccer;
  893. uint32_t tmpcr2;
  894. /* Check the parameters */
  895. assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  896. assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  897. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  898. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  899. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  900. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  901. /* Disable the Channel 4: Reset the CC4E Bit */
  902. CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
  903. /* Get the TIMx CCER register value */
  904. tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  905. /* Get the TIMx CR2 register value */
  906. tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  907. /* Get the TIMx CCMR2 register value */
  908. tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  909. /* Reset Capture/Compare selection Bits */
  910. CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
  911. /* Select the Output Compare Mode */
  912. MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
  913. /* Set the Output Compare Polarity */
  914. MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
  915. /* Set the Output State */
  916. MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
  917. if (IS_TIM_BREAK_INSTANCE(TIMx))
  918. {
  919. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  920. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  921. /* Set the Output Idle state */
  922. MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
  923. }
  924. /* Write to TIMx CR2 */
  925. LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  926. /* Write to TIMx CCMR2 */
  927. LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  928. /* Set the Capture Compare Register value */
  929. LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
  930. /* Write to TIMx CCER */
  931. LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  932. return SUCCESS;
  933. }
  934. /**
  935. * @brief Configure the TIMx output channel 5.
  936. * @param TIMx Timer Instance
  937. * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
  938. * @retval An ErrorStatus enumeration value:
  939. * - SUCCESS: TIMx registers are de-initialized
  940. * - ERROR: not applicable
  941. */
  942. static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  943. {
  944. uint32_t tmpccmr3;
  945. uint32_t tmpccer;
  946. /* Check the parameters */
  947. assert_param(IS_TIM_CC5_INSTANCE(TIMx));
  948. assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  949. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  950. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  951. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  952. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  953. /* Disable the Channel 5: Reset the CC5E Bit */
  954. CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
  955. /* Get the TIMx CCER register value */
  956. tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  957. /* Get the TIMx CCMR3 register value */
  958. tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
  959. /* Select the Output Compare Mode */
  960. MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
  961. /* Set the Output Compare Polarity */
  962. MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
  963. /* Set the Output State */
  964. MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
  965. if (IS_TIM_BREAK_INSTANCE(TIMx))
  966. {
  967. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  968. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  969. /* Set the Output Idle state */
  970. MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
  971. }
  972. /* Write to TIMx CCMR3 */
  973. LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
  974. /* Set the Capture Compare Register value */
  975. LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
  976. /* Write to TIMx CCER */
  977. LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  978. return SUCCESS;
  979. }
  980. /**
  981. * @brief Configure the TIMx output channel 6.
  982. * @param TIMx Timer Instance
  983. * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
  984. * @retval An ErrorStatus enumeration value:
  985. * - SUCCESS: TIMx registers are de-initialized
  986. * - ERROR: not applicable
  987. */
  988. static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  989. {
  990. uint32_t tmpccmr3;
  991. uint32_t tmpccer;
  992. /* Check the parameters */
  993. assert_param(IS_TIM_CC6_INSTANCE(TIMx));
  994. assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  995. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  996. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  997. assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  998. assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  999. /* Disable the Channel 5: Reset the CC6E Bit */
  1000. CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
  1001. /* Get the TIMx CCER register value */
  1002. tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  1003. /* Get the TIMx CCMR3 register value */
  1004. tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
  1005. /* Select the Output Compare Mode */
  1006. MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
  1007. /* Set the Output Compare Polarity */
  1008. MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
  1009. /* Set the Output State */
  1010. MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
  1011. if (IS_TIM_BREAK_INSTANCE(TIMx))
  1012. {
  1013. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  1014. assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  1015. /* Set the Output Idle state */
  1016. MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
  1017. }
  1018. /* Write to TIMx CCMR3 */
  1019. LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
  1020. /* Set the Capture Compare Register value */
  1021. LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
  1022. /* Write to TIMx CCER */
  1023. LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  1024. return SUCCESS;
  1025. }
  1026. /**
  1027. * @brief Configure the TIMx input channel 1.
  1028. * @param TIMx Timer Instance
  1029. * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
  1030. * @retval An ErrorStatus enumeration value:
  1031. * - SUCCESS: TIMx registers are de-initialized
  1032. * - ERROR: not applicable
  1033. */
  1034. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1035. {
  1036. /* Check the parameters */
  1037. assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  1038. assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1039. assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1040. assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1041. assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1042. /* Disable the Channel 1: Reset the CC1E Bit */
  1043. TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
  1044. /* Select the Input and set the filter and the prescaler value */
  1045. MODIFY_REG(TIMx->CCMR1,
  1046. (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
  1047. (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  1048. /* Select the Polarity and set the CC1E Bit */
  1049. MODIFY_REG(TIMx->CCER,
  1050. (TIM_CCER_CC1P | TIM_CCER_CC1NP),
  1051. (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
  1052. return SUCCESS;
  1053. }
  1054. /**
  1055. * @brief Configure the TIMx input channel 2.
  1056. * @param TIMx Timer Instance
  1057. * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
  1058. * @retval An ErrorStatus enumeration value:
  1059. * - SUCCESS: TIMx registers are de-initialized
  1060. * - ERROR: not applicable
  1061. */
  1062. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1063. {
  1064. /* Check the parameters */
  1065. assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  1066. assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1067. assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1068. assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1069. assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1070. /* Disable the Channel 2: Reset the CC2E Bit */
  1071. TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
  1072. /* Select the Input and set the filter and the prescaler value */
  1073. MODIFY_REG(TIMx->CCMR1,
  1074. (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
  1075. (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  1076. /* Select the Polarity and set the CC2E Bit */
  1077. MODIFY_REG(TIMx->CCER,
  1078. (TIM_CCER_CC2P | TIM_CCER_CC2NP),
  1079. ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
  1080. return SUCCESS;
  1081. }
  1082. /**
  1083. * @brief Configure the TIMx input channel 3.
  1084. * @param TIMx Timer Instance
  1085. * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
  1086. * @retval An ErrorStatus enumeration value:
  1087. * - SUCCESS: TIMx registers are de-initialized
  1088. * - ERROR: not applicable
  1089. */
  1090. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1091. {
  1092. /* Check the parameters */
  1093. assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  1094. assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1095. assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1096. assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1097. assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1098. /* Disable the Channel 3: Reset the CC3E Bit */
  1099. TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
  1100. /* Select the Input and set the filter and the prescaler value */
  1101. MODIFY_REG(TIMx->CCMR2,
  1102. (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
  1103. (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  1104. /* Select the Polarity and set the CC3E Bit */
  1105. MODIFY_REG(TIMx->CCER,
  1106. (TIM_CCER_CC3P | TIM_CCER_CC3NP),
  1107. ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
  1108. return SUCCESS;
  1109. }
  1110. /**
  1111. * @brief Configure the TIMx input channel 4.
  1112. * @param TIMx Timer Instance
  1113. * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
  1114. * @retval An ErrorStatus enumeration value:
  1115. * - SUCCESS: TIMx registers are de-initialized
  1116. * - ERROR: not applicable
  1117. */
  1118. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1119. {
  1120. /* Check the parameters */
  1121. assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  1122. assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1123. assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1124. assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1125. assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1126. /* Disable the Channel 4: Reset the CC4E Bit */
  1127. TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
  1128. /* Select the Input and set the filter and the prescaler value */
  1129. MODIFY_REG(TIMx->CCMR2,
  1130. (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
  1131. (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  1132. /* Select the Polarity and set the CC2E Bit */
  1133. MODIFY_REG(TIMx->CCER,
  1134. (TIM_CCER_CC4P | TIM_CCER_CC4NP),
  1135. ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
  1136. return SUCCESS;
  1137. }
  1138. /**
  1139. * @}
  1140. */
  1141. /**
  1142. * @}
  1143. */
  1144. #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 */
  1145. /**
  1146. * @}
  1147. */
  1148. #endif /* USE_FULL_LL_DRIVER */
  1149. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/