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  1. /**
  2. ******************************************************************************
  3. * @file stm32l0xx_hal_dma.c
  4. * @author MCD Application Team
  5. * @brief DMA HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Direct Memory Access (DMA) peripheral:
  8. * + Initialization and de-initialization functions
  9. * + IO operation functions
  10. * + Peripheral State and errors functions
  11. @verbatim
  12. ==============================================================================
  13. ##### How to use this driver #####
  14. ==============================================================================
  15. [..]
  16. (#) Enable and configure the peripheral to be connected to the DMA Channel
  17. (except for internal SRAM / FLASH memories: no initialization is
  18. necessary).
  19. (#) For a given Channel, program the required configuration through the following parameters:
  20. Channel request, Transfer Direction, Source and Destination data formats,
  21. Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
  22. using HAL_DMA_Init() function.
  23. (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
  24. detection.
  25. (#) Use HAL_DMA_Abort() function to abort the current transfer
  26. -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
  27. *** Polling mode IO operation ***
  28. =================================
  29. [..]
  30. (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
  31. address and destination address and the Length of data to be transferred
  32. (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
  33. case a fixed Timeout can be configured by User depending from his application.
  34. *** Interrupt mode IO operation ***
  35. ===================================
  36. [..]
  37. (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
  38. (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
  39. (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
  40. Source address and destination address and the Length of data to be transferred.
  41. In this case the DMA interrupt is configured
  42. (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
  43. (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
  44. add his own function to register callbacks with HAL_DMA_RegisterCallback().
  45. *** DMA HAL driver macros list ***
  46. =============================================
  47. [..]
  48. Below the list of macros in DMA HAL driver.
  49. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
  50. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
  51. (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
  52. (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
  53. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
  54. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
  55. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
  56. [..]
  57. (@) You can refer to the DMA HAL driver header file for more useful macros
  58. @endverbatim
  59. ******************************************************************************
  60. * @attention
  61. *
  62. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics.
  63. * All rights reserved.</center></h2>
  64. *
  65. * This software component is licensed by ST under BSD 3-Clause license,
  66. * the "License"; You may not use this file except in compliance with the
  67. * License. You may obtain a copy of the License at:
  68. * opensource.org/licenses/BSD-3-Clause
  69. *
  70. ******************************************************************************
  71. */
  72. /* Includes ------------------------------------------------------------------*/
  73. #include "stm32l0xx_hal.h"
  74. /** @addtogroup STM32L0xx_HAL_Driver
  75. * @{
  76. */
  77. /** @defgroup DMA DMA
  78. * @brief DMA HAL module driver
  79. * @{
  80. */
  81. #ifdef HAL_DMA_MODULE_ENABLED
  82. /* Private typedef -----------------------------------------------------------*/
  83. /** @defgroup DMA_Private_Functions DMA Private Functions
  84. * @{
  85. */
  86. static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  87. /**
  88. * @}
  89. */
  90. /* Exported functions ---------------------------------------------------------*/
  91. /** @defgroup DMA_Exported_Functions DMA Exported Functions
  92. * @{
  93. */
  94. /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
  95. * @brief Initialization and de-initialization functions
  96. *
  97. @verbatim
  98. ===============================================================================
  99. ##### Initialization and de-initialization functions #####
  100. ===============================================================================
  101. [..]
  102. This section provides functions allowing to initialize the DMA Channel source
  103. and destination addresses, incrementation and data sizes, transfer direction,
  104. circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
  105. [..]
  106. The HAL_DMA_Init() function follows the DMA configuration procedures as described in
  107. reference manual.
  108. @endverbatim
  109. * @{
  110. */
  111. /**
  112. * @brief Initialize the DMA according to the specified
  113. * parameters in the DMA_InitTypeDef and initialize the associated handle.
  114. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
  115. * the configuration information for the specified DMA Channel.
  116. * @retval HAL status
  117. */
  118. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
  119. {
  120. uint32_t tmp;
  121. /* Check the DMA handle allocation */
  122. if(hdma == NULL)
  123. {
  124. return HAL_ERROR;
  125. }
  126. /* Check the parameters */
  127. assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
  128. assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
  129. assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
  130. assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
  131. assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
  132. assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
  133. assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
  134. assert_param(IS_DMA_MODE(hdma->Init.Mode));
  135. assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
  136. /* Compute the channel index */
  137. /* Only one DMA: DMA1 */
  138. hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
  139. hdma->DmaBaseAddress = DMA1;
  140. /* Change DMA peripheral state */
  141. hdma->State = HAL_DMA_STATE_BUSY;
  142. /* Get the CR register value */
  143. tmp = hdma->Instance->CCR;
  144. /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
  145. tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
  146. DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
  147. DMA_CCR_DIR | DMA_CCR_MEM2MEM));
  148. /* Prepare the DMA Channel configuration */
  149. tmp |= hdma->Init.Direction |
  150. hdma->Init.PeriphInc | hdma->Init.MemInc |
  151. hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
  152. hdma->Init.Mode | hdma->Init.Priority;
  153. /* Write to DMA Channel CR register */
  154. hdma->Instance->CCR = tmp;
  155. /* Set request selection */
  156. if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
  157. {
  158. /* Write to DMA channel selection register */
  159. /* Reset request selection for DMA1 Channelx */
  160. DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
  161. /* Configure request selection for DMA1 Channelx */
  162. DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
  163. }
  164. /* Initialise the error code */
  165. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  166. /* Initialize the DMA state*/
  167. hdma->State = HAL_DMA_STATE_READY;
  168. /* Allocate lock resource and initialize it */
  169. hdma->Lock = HAL_UNLOCKED;
  170. return HAL_OK;
  171. }
  172. /**
  173. * @brief DeInitialize the DMA peripheral.
  174. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  175. * the configuration information for the specified DMA Channel.
  176. * @retval HAL status
  177. */
  178. HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
  179. {
  180. /* Check the DMA handle allocation */
  181. if (NULL == hdma )
  182. {
  183. return HAL_ERROR;
  184. }
  185. /* Check the parameters */
  186. assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
  187. /* Disable the selected DMA Channelx */
  188. __HAL_DMA_DISABLE(hdma);
  189. /* Compute the channel index */
  190. /* DMA1 */
  191. hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
  192. hdma->DmaBaseAddress = DMA1;
  193. /* Reset DMA Channel control register */
  194. hdma->Instance->CCR = 0U;
  195. /* Clear all flags */
  196. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
  197. /* Reset DMA channel selection register */
  198. /* DMA1 */
  199. DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
  200. /* Clean callbacks */
  201. hdma->XferCpltCallback = NULL;
  202. hdma->XferHalfCpltCallback = NULL;
  203. hdma->XferErrorCallback = NULL;
  204. hdma->XferAbortCallback = NULL;
  205. /* Initialise the error code */
  206. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  207. /* Initialize the DMA state */
  208. hdma->State = HAL_DMA_STATE_RESET;
  209. /* Release Lock */
  210. __HAL_UNLOCK(hdma);
  211. return HAL_OK;
  212. }
  213. /**
  214. * @}
  215. */
  216. /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
  217. * @brief Input and Output operation functions
  218. *
  219. @verbatim
  220. ===============================================================================
  221. ##### IO operation functions #####
  222. ===============================================================================
  223. [..] This section provides functions allowing to:
  224. (+) Configure the source, destination address and data length and Start DMA transfer
  225. (+) Configure the source, destination address and data length and
  226. Start DMA transfer with interrupt
  227. (+) Abort DMA transfer
  228. (+) Poll for transfer complete
  229. (+) Handle DMA interrupt request
  230. @endverbatim
  231. * @{
  232. */
  233. /**
  234. * @brief Start the DMA Transfer.
  235. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  236. * the configuration information for the specified DMA Channel.
  237. * @param SrcAddress The source memory Buffer address
  238. * @param DstAddress The destination memory Buffer address
  239. * @param DataLength The length of data to be transferred from source to destination
  240. * @retval HAL status
  241. */
  242. HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
  243. {
  244. HAL_StatusTypeDef status = HAL_OK;
  245. /* Check the parameters */
  246. assert_param(IS_DMA_BUFFER_SIZE(DataLength));
  247. /* Process locked */
  248. __HAL_LOCK(hdma);
  249. if(HAL_DMA_STATE_READY == hdma->State)
  250. {
  251. /* Change DMA peripheral state */
  252. hdma->State = HAL_DMA_STATE_BUSY;
  253. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  254. /* Disable the peripheral */
  255. __HAL_DMA_DISABLE(hdma);
  256. /* Configure the source, destination address and the data length & clear flags*/
  257. DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
  258. /* Enable the Peripheral */
  259. __HAL_DMA_ENABLE(hdma);
  260. }
  261. else
  262. {
  263. /* Process Unlocked */
  264. __HAL_UNLOCK(hdma);
  265. status = HAL_BUSY;
  266. }
  267. return status;
  268. }
  269. /**
  270. * @brief Start the DMA Transfer with interrupt enabled.
  271. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  272. * the configuration information for the specified DMA Channel.
  273. * @param SrcAddress The source memory Buffer address
  274. * @param DstAddress The destination memory Buffer address
  275. * @param DataLength The length of data to be transferred from source to destination
  276. * @retval HAL status
  277. */
  278. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
  279. {
  280. HAL_StatusTypeDef status = HAL_OK;
  281. /* Check the parameters */
  282. assert_param(IS_DMA_BUFFER_SIZE(DataLength));
  283. /* Process locked */
  284. __HAL_LOCK(hdma);
  285. if(HAL_DMA_STATE_READY == hdma->State)
  286. {
  287. /* Change DMA peripheral state */
  288. hdma->State = HAL_DMA_STATE_BUSY;
  289. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  290. /* Disable the peripheral */
  291. __HAL_DMA_DISABLE(hdma);
  292. /* Configure the source, destination address and the data length & clear flags*/
  293. DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
  294. /* Enable the transfer complete interrupt */
  295. /* Enable the transfer Error interrupt */
  296. if(NULL != hdma->XferHalfCpltCallback )
  297. {
  298. /* Enable the Half transfer complete interrupt as well */
  299. __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  300. }
  301. else
  302. {
  303. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
  304. __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
  305. }
  306. /* Enable the Peripheral */
  307. __HAL_DMA_ENABLE(hdma);
  308. }
  309. else
  310. {
  311. /* Process Unlocked */
  312. __HAL_UNLOCK(hdma);
  313. /* Remain BUSY */
  314. status = HAL_BUSY;
  315. }
  316. return status;
  317. }
  318. /**
  319. * @brief Abort the DMA Transfer.
  320. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  321. * the configuration information for the specified DMA Channel.
  322. * @retval HAL status
  323. */
  324. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
  325. {
  326. HAL_StatusTypeDef status = HAL_OK;
  327. /* Check the DMA peripheral state */
  328. if(hdma->State != HAL_DMA_STATE_BUSY)
  329. {
  330. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  331. /* Process Unlocked */
  332. __HAL_UNLOCK(hdma);
  333. return HAL_ERROR;
  334. }
  335. else
  336. {
  337. /* Disable DMA IT */
  338. __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  339. /* Disable the channel */
  340. __HAL_DMA_DISABLE(hdma);
  341. /* Clear all flags */
  342. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
  343. /* Change the DMA state */
  344. hdma->State = HAL_DMA_STATE_READY;
  345. /* Process Unlocked */
  346. __HAL_UNLOCK(hdma);
  347. return status;
  348. }
  349. }
  350. /**
  351. * @brief Aborts the DMA Transfer in Interrupt mode.
  352. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  353. * the configuration information for the specified DMA Channel.
  354. * @retval HAL status
  355. */
  356. HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
  357. {
  358. HAL_StatusTypeDef status = HAL_OK;
  359. if(HAL_DMA_STATE_BUSY != hdma->State)
  360. {
  361. /* no transfer ongoing */
  362. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  363. status = HAL_ERROR;
  364. }
  365. else
  366. {
  367. /* Disable DMA IT */
  368. __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  369. /* Disable the channel */
  370. __HAL_DMA_DISABLE(hdma);
  371. /* Clear all flags */
  372. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
  373. /* Change the DMA state */
  374. hdma->State = HAL_DMA_STATE_READY;
  375. /* Process Unlocked */
  376. __HAL_UNLOCK(hdma);
  377. /* Call User Abort callback */
  378. if(hdma->XferAbortCallback != NULL)
  379. {
  380. hdma->XferAbortCallback(hdma);
  381. }
  382. }
  383. return status;
  384. }
  385. /**
  386. * @brief Polling for transfer complete.
  387. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  388. * the configuration information for the specified DMA Channel.
  389. * @param CompleteLevel Specifies the DMA level complete.
  390. * @param Timeout Timeout duration.
  391. * @retval HAL status
  392. */
  393. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
  394. {
  395. uint32_t temp;
  396. uint32_t tickstart;
  397. if(HAL_DMA_STATE_BUSY != hdma->State)
  398. {
  399. /* no transfer ongoing */
  400. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  401. __HAL_UNLOCK(hdma);
  402. return HAL_ERROR;
  403. }
  404. /* Polling mode not supported in circular mode */
  405. if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
  406. {
  407. hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
  408. return HAL_ERROR;
  409. }
  410. /* Get the level transfer complete flag */
  411. if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
  412. {
  413. /* Transfer Complete flag */
  414. temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU);
  415. }
  416. else
  417. {
  418. /* Half Transfer Complete flag */
  419. temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU);
  420. }
  421. /* Get tick */
  422. tickstart = HAL_GetTick();
  423. while(0U == (hdma->DmaBaseAddress->ISR & temp))
  424. {
  425. if((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1cU)))))
  426. {
  427. /* When a DMA transfer error occurs */
  428. /* A hardware clear of its EN bits is performed */
  429. /* Clear all flags */
  430. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
  431. /* Update error code */
  432. hdma->ErrorCode = HAL_DMA_ERROR_TE;
  433. /* Change the DMA state */
  434. hdma->State= HAL_DMA_STATE_READY;
  435. /* Process Unlocked */
  436. __HAL_UNLOCK(hdma);
  437. return HAL_ERROR;
  438. }
  439. /* Check for the Timeout */
  440. if(Timeout != HAL_MAX_DELAY)
  441. {
  442. if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  443. {
  444. /* Update error code */
  445. hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
  446. /* Change the DMA state */
  447. hdma->State = HAL_DMA_STATE_READY;
  448. /* Process Unlocked */
  449. __HAL_UNLOCK(hdma);
  450. return HAL_ERROR;
  451. }
  452. }
  453. }
  454. if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
  455. {
  456. /* Clear the transfer complete flag */
  457. hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1cU));
  458. /* The selected Channelx EN bit is cleared (DMA is disabled and
  459. all transfers are complete) */
  460. hdma->State = HAL_DMA_STATE_READY;
  461. }
  462. else
  463. {
  464. /* Clear the half transfer complete flag */
  465. hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU));
  466. }
  467. /* Process unlocked */
  468. __HAL_UNLOCK(hdma);
  469. return HAL_OK;
  470. }
  471. /**
  472. * @brief Handle DMA interrupt request.
  473. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  474. * the configuration information for the specified DMA Channel.
  475. * @retval None
  476. */
  477. void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
  478. {
  479. uint32_t flag_it = hdma->DmaBaseAddress->ISR;
  480. uint32_t source_it = hdma->Instance->CCR;
  481. /* Half Transfer Complete Interrupt management ******************************/
  482. if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT)))
  483. {
  484. /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
  485. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  486. {
  487. /* Disable the half transfer interrupt */
  488. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
  489. }
  490. /* Clear the half transfer complete flag */
  491. hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU);
  492. /* DMA peripheral state is not updated in Half Transfer */
  493. /* but in Transfer Complete case */
  494. if(hdma->XferHalfCpltCallback != NULL)
  495. {
  496. /* Half transfer callback */
  497. hdma->XferHalfCpltCallback(hdma);
  498. }
  499. }
  500. /* Transfer Complete Interrupt management ***********************************/
  501. else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
  502. {
  503. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  504. {
  505. /* Disable the transfer complete and error interrupt */
  506. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
  507. /* Change the DMA state */
  508. hdma->State = HAL_DMA_STATE_READY;
  509. }
  510. /* Clear the transfer complete flag */
  511. hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
  512. /* Process Unlocked */
  513. __HAL_UNLOCK(hdma);
  514. if(hdma->XferCpltCallback != NULL)
  515. {
  516. /* Transfer complete callback */
  517. hdma->XferCpltCallback(hdma);
  518. }
  519. }
  520. /* Transfer Error Interrupt management **************************************/
  521. else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE)))
  522. {
  523. /* When a DMA transfer error occurs */
  524. /* A hardware clear of its EN bits is performed */
  525. /* Disable ALL DMA IT */
  526. __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  527. /* Clear all flags */
  528. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
  529. /* Update error code */
  530. hdma->ErrorCode = HAL_DMA_ERROR_TE;
  531. /* Change the DMA state */
  532. hdma->State = HAL_DMA_STATE_READY;
  533. /* Process Unlocked */
  534. __HAL_UNLOCK(hdma);
  535. if (hdma->XferErrorCallback != NULL)
  536. {
  537. /* Transfer error callback */
  538. hdma->XferErrorCallback(hdma);
  539. }
  540. }
  541. else
  542. {
  543. /* Nothing To Do */
  544. }
  545. return;
  546. }
  547. /**
  548. * @brief Register callbacks
  549. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  550. * the configuration information for the specified DMA Channel.
  551. * @param CallbackID User Callback identifer
  552. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
  553. * @param pCallback pointer to private callbacsk function which has pointer to
  554. * a DMA_HandleTypeDef structure as parameter.
  555. * @retval HAL status
  556. */
  557. HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
  558. {
  559. HAL_StatusTypeDef status = HAL_OK;
  560. /* Process locked */
  561. __HAL_LOCK(hdma);
  562. if(HAL_DMA_STATE_READY == hdma->State)
  563. {
  564. switch (CallbackID)
  565. {
  566. case HAL_DMA_XFER_CPLT_CB_ID:
  567. hdma->XferCpltCallback = pCallback;
  568. break;
  569. case HAL_DMA_XFER_HALFCPLT_CB_ID:
  570. hdma->XferHalfCpltCallback = pCallback;
  571. break;
  572. case HAL_DMA_XFER_ERROR_CB_ID:
  573. hdma->XferErrorCallback = pCallback;
  574. break;
  575. case HAL_DMA_XFER_ABORT_CB_ID:
  576. hdma->XferAbortCallback = pCallback;
  577. break;
  578. default:
  579. status = HAL_ERROR;
  580. break;
  581. }
  582. }
  583. else
  584. {
  585. status = HAL_ERROR;
  586. }
  587. /* Release Lock */
  588. __HAL_UNLOCK(hdma);
  589. return status;
  590. }
  591. /**
  592. * @brief UnRegister callbacks
  593. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  594. * the configuration information for the specified DMA Channel.
  595. * @param CallbackID User Callback identifer
  596. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
  597. * @retval HAL status
  598. */
  599. HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
  600. {
  601. HAL_StatusTypeDef status = HAL_OK;
  602. /* Process locked */
  603. __HAL_LOCK(hdma);
  604. if(HAL_DMA_STATE_READY == hdma->State)
  605. {
  606. switch (CallbackID)
  607. {
  608. case HAL_DMA_XFER_CPLT_CB_ID:
  609. hdma->XferCpltCallback = NULL;
  610. break;
  611. case HAL_DMA_XFER_HALFCPLT_CB_ID:
  612. hdma->XferHalfCpltCallback = NULL;
  613. break;
  614. case HAL_DMA_XFER_ERROR_CB_ID:
  615. hdma->XferErrorCallback = NULL;
  616. break;
  617. case HAL_DMA_XFER_ABORT_CB_ID:
  618. hdma->XferAbortCallback = NULL;
  619. break;
  620. case HAL_DMA_XFER_ALL_CB_ID:
  621. hdma->XferCpltCallback = NULL;
  622. hdma->XferHalfCpltCallback = NULL;
  623. hdma->XferErrorCallback = NULL;
  624. hdma->XferAbortCallback = NULL;
  625. break;
  626. default:
  627. status = HAL_ERROR;
  628. break;
  629. }
  630. }
  631. else
  632. {
  633. status = HAL_ERROR;
  634. }
  635. /* Release Lock */
  636. __HAL_UNLOCK(hdma);
  637. return status;
  638. }
  639. /**
  640. * @}
  641. */
  642. /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
  643. * @brief Peripheral State and Errors functions
  644. *
  645. @verbatim
  646. ===============================================================================
  647. ##### Peripheral State and Errors functions #####
  648. ===============================================================================
  649. [..]
  650. This subsection provides functions allowing to
  651. (+) Check the DMA state
  652. (+) Get error code
  653. @endverbatim
  654. * @{
  655. */
  656. /**
  657. * @brief Return the DMA handle state.
  658. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  659. * the configuration information for the specified DMA Channel.
  660. * @retval HAL state
  661. */
  662. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
  663. {
  664. /* Return DMA handle state */
  665. return hdma->State;
  666. }
  667. /**
  668. * @brief Return the DMA error code.
  669. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
  670. * the configuration information for the specified DMA Channel.
  671. * @retval DMA Error Code
  672. */
  673. uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
  674. {
  675. return hdma->ErrorCode;
  676. }
  677. /**
  678. * @}
  679. */
  680. /**
  681. * @}
  682. */
  683. /** @addtogroup DMA_Private_Functions
  684. * @{
  685. */
  686. /**
  687. * @brief Sets the DMA Transfer parameter.
  688. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  689. * the configuration information for the specified DMA Channel.
  690. * @param SrcAddress The source memory Buffer address
  691. * @param DstAddress The destination memory Buffer address
  692. * @param DataLength The length of data to be transferred from source to destination
  693. * @retval HAL status
  694. */
  695. static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
  696. {
  697. /* Clear all flags */
  698. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
  699. /* Configure DMA Channel data length */
  700. hdma->Instance->CNDTR = DataLength;
  701. /* Memory to Peripheral */
  702. if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
  703. {
  704. /* Configure DMA Channel destination address */
  705. hdma->Instance->CPAR = DstAddress;
  706. /* Configure DMA Channel source address */
  707. hdma->Instance->CMAR = SrcAddress;
  708. }
  709. /* Peripheral to Memory */
  710. else
  711. {
  712. /* Configure DMA Channel source address */
  713. hdma->Instance->CPAR = SrcAddress;
  714. /* Configure DMA Channel destination address */
  715. hdma->Instance->CMAR = DstAddress;
  716. }
  717. }
  718. /**
  719. * @}
  720. */
  721. /**
  722. * @}
  723. */
  724. #endif /* HAL_DMA_MODULE_ENABLED */
  725. /**
  726. * @}
  727. */
  728. /**
  729. * @}
  730. */
  731. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/