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  1. /**
  2. ******************************************************************************
  3. * @file stm32l0xx_hal_smbus.c
  4. * @author MCD Application Team
  5. * @brief SMBUS HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the System Management Bus (SMBus) peripheral,
  8. * based on I2C principles of operation :
  9. * + Initialization and de-initialization functions
  10. * + IO operation functions
  11. * + Peripheral State and Errors functions
  12. *
  13. @verbatim
  14. ==============================================================================
  15. ##### How to use this driver #####
  16. ==============================================================================
  17. [..]
  18. The SMBUS HAL driver can be used as follows:
  19. (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
  20. SMBUS_HandleTypeDef hsmbus;
  21. (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
  22. (##) Enable the SMBUSx interface clock
  23. (##) SMBUS pins configuration
  24. (+++) Enable the clock for the SMBUS GPIOs
  25. (+++) Configure SMBUS pins as alternate function open-drain
  26. (##) NVIC configuration if you need to use interrupt process
  27. (+++) Configure the SMBUSx interrupt priority
  28. (+++) Enable the NVIC SMBUS IRQ Channel
  29. (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
  30. Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
  31. Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
  32. (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
  33. (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
  34. by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
  35. (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
  36. (#) For SMBUS IO operations, only one mode of operations is available within this driver
  37. *** Interrupt mode IO operation ***
  38. ===================================
  39. [..]
  40. (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
  41. (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
  42. add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
  43. (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
  44. (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
  45. add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
  46. (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
  47. (++) The associated previous transfer callback is called at the end of abort process
  48. (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
  49. (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
  50. (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
  51. using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
  52. (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
  53. add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
  54. (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
  55. add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
  56. (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
  57. (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
  58. add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
  59. (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
  60. (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
  61. add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
  62. (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
  63. (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
  64. add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
  65. to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
  66. (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
  67. (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
  68. add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
  69. to check the Error Code using function @ref HAL_SMBUS_GetError()
  70. *** SMBUS HAL driver macros list ***
  71. ==================================
  72. [..]
  73. Below the list of most used macros in SMBUS HAL driver.
  74. (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
  75. (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
  76. (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
  77. (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
  78. (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
  79. (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
  80. *** Callback registration ***
  81. =============================================
  82. The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
  83. allows the user to configure dynamically the driver callbacks.
  84. Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
  85. to register an interrupt callback.
  86. Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
  87. (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
  88. (+) MasterRxCpltCallback : callback for Master reception end of transfer.
  89. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
  90. (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
  91. (+) ListenCpltCallback : callback for end of listen mode.
  92. (+) ErrorCallback : callback for error detection.
  93. (+) MspInitCallback : callback for Msp Init.
  94. (+) MspDeInitCallback : callback for Msp DeInit.
  95. This function takes as parameters the HAL peripheral handle, the Callback ID
  96. and a pointer to the user callback function.
  97. For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
  98. Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
  99. weak function.
  100. @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
  101. and the Callback ID.
  102. This function allows to reset following callbacks:
  103. (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
  104. (+) MasterRxCpltCallback : callback for Master reception end of transfer.
  105. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
  106. (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
  107. (+) ListenCpltCallback : callback for end of listen mode.
  108. (+) ErrorCallback : callback for error detection.
  109. (+) MspInitCallback : callback for Msp Init.
  110. (+) MspDeInitCallback : callback for Msp DeInit.
  111. For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
  112. By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
  113. all callbacks are set to the corresponding weak functions:
  114. examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
  115. Exception done for MspInit and MspDeInit functions that are
  116. reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
  117. these callbacks are null (not registered beforehand).
  118. If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
  119. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
  120. Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
  121. Exception done MspInit/MspDeInit functions that can be registered/unregistered
  122. in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
  123. thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  124. Then, the user first registers the MspInit/MspDeInit user callbacks
  125. using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
  126. or @ref HAL_SMBUS_Init() function.
  127. When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
  128. not defined, the callback registration feature is not available and all callbacks
  129. are set to the corresponding weak functions.
  130. [..]
  131. (@) You can refer to the SMBUS HAL driver header file for more useful macros
  132. @endverbatim
  133. ******************************************************************************
  134. * @attention
  135. *
  136. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  137. * All rights reserved.</center></h2>
  138. *
  139. * This software component is licensed by ST under BSD 3-Clause license,
  140. * the "License"; You may not use this file except in compliance with the
  141. * License. You may obtain a copy of the License at:
  142. * opensource.org/licenses/BSD-3-Clause
  143. *
  144. ******************************************************************************
  145. */
  146. /* Includes ------------------------------------------------------------------*/
  147. #include "stm32l0xx_hal.h"
  148. /** @addtogroup STM32L0xx_HAL_Driver
  149. * @{
  150. */
  151. /** @defgroup SMBUS SMBUS
  152. * @brief SMBUS HAL module driver
  153. * @{
  154. */
  155. #ifdef HAL_SMBUS_MODULE_ENABLED
  156. /* Private typedef -----------------------------------------------------------*/
  157. /* Private constants ---------------------------------------------------------*/
  158. /** @defgroup SMBUS_Private_Define SMBUS Private Constants
  159. * @{
  160. */
  161. #define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */
  162. #define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
  163. #define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
  164. #define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
  165. #define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
  166. #define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
  167. #define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
  168. #define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
  169. #define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
  170. #define MAX_NBYTE_SIZE 255U
  171. /**
  172. * @}
  173. */
  174. /* Private macro -------------------------------------------------------------*/
  175. /* Private variables ---------------------------------------------------------*/
  176. /* Private function prototypes -----------------------------------------------*/
  177. /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
  178. * @{
  179. */
  180. static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
  181. static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
  182. static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
  183. static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
  184. static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
  185. static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus);
  186. static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus);
  187. static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
  188. /**
  189. * @}
  190. */
  191. /* Exported functions --------------------------------------------------------*/
  192. /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
  193. * @{
  194. */
  195. /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
  196. * @brief Initialization and Configuration functions
  197. *
  198. @verbatim
  199. ===============================================================================
  200. ##### Initialization and de-initialization functions #####
  201. ===============================================================================
  202. [..] This subsection provides a set of functions allowing to initialize and
  203. deinitialize the SMBUSx peripheral:
  204. (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
  205. all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
  206. (+) Call the function HAL_SMBUS_Init() to configure the selected device with
  207. the selected configuration:
  208. (++) Clock Timing
  209. (++) Bus Timeout
  210. (++) Analog Filer mode
  211. (++) Own Address 1
  212. (++) Addressing mode (Master, Slave)
  213. (++) Dual Addressing mode
  214. (++) Own Address 2
  215. (++) Own Address 2 Mask
  216. (++) General call mode
  217. (++) Nostretch mode
  218. (++) Packet Error Check mode
  219. (++) Peripheral mode
  220. (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
  221. of the selected SMBUSx peripheral.
  222. (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
  223. HAL_SMBUS_ConfigDigitalFilter().
  224. @endverbatim
  225. * @{
  226. */
  227. /**
  228. * @brief Initialize the SMBUS according to the specified parameters
  229. * in the SMBUS_InitTypeDef and initialize the associated handle.
  230. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  231. * the configuration information for the specified SMBUS.
  232. * @retval HAL status
  233. */
  234. HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
  235. {
  236. /* Check the SMBUS handle allocation */
  237. if (hsmbus == NULL)
  238. {
  239. return HAL_ERROR;
  240. }
  241. /* Check the parameters */
  242. assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
  243. assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
  244. assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
  245. assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
  246. assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
  247. assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
  248. assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
  249. assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
  250. assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
  251. assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
  252. assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
  253. if (hsmbus->State == HAL_SMBUS_STATE_RESET)
  254. {
  255. /* Allocate lock resource and initialize it */
  256. hsmbus->Lock = HAL_UNLOCKED;
  257. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  258. hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
  259. hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
  260. hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
  261. hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
  262. hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
  263. hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
  264. hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
  265. if (hsmbus->MspInitCallback == NULL)
  266. {
  267. hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
  268. }
  269. /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
  270. hsmbus->MspInitCallback(hsmbus);
  271. #else
  272. /* Init the low level hardware : GPIO, CLOCK, NVIC */
  273. HAL_SMBUS_MspInit(hsmbus);
  274. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  275. }
  276. hsmbus->State = HAL_SMBUS_STATE_BUSY;
  277. /* Disable the selected SMBUS peripheral */
  278. __HAL_SMBUS_DISABLE(hsmbus);
  279. /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
  280. /* Configure SMBUSx: Frequency range */
  281. hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
  282. /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
  283. /* Configure SMBUSx: Bus Timeout */
  284. hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
  285. hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
  286. hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
  287. /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
  288. /* Configure SMBUSx: Own Address1 and ack own address1 mode */
  289. hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
  290. if (hsmbus->Init.OwnAddress1 != 0UL)
  291. {
  292. if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
  293. {
  294. hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
  295. }
  296. else /* SMBUS_ADDRESSINGMODE_10BIT */
  297. {
  298. hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
  299. }
  300. }
  301. /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
  302. /* Configure SMBUSx: Addressing Master mode */
  303. if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
  304. {
  305. hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
  306. }
  307. /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
  308. /* AUTOEND and NACK bit will be manage during Transfer process */
  309. hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
  310. /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
  311. /* Configure SMBUSx: Dual mode and Own Address2 */
  312. hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
  313. /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
  314. /* Configure SMBUSx: Generalcall and NoStretch mode */
  315. hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
  316. /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
  317. if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
  318. && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
  319. {
  320. hsmbus->Instance->CR1 |= I2C_CR1_SBC;
  321. }
  322. /* Enable the selected SMBUS peripheral */
  323. __HAL_SMBUS_ENABLE(hsmbus);
  324. hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
  325. hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
  326. hsmbus->State = HAL_SMBUS_STATE_READY;
  327. return HAL_OK;
  328. }
  329. /**
  330. * @brief DeInitialize the SMBUS peripheral.
  331. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  332. * the configuration information for the specified SMBUS.
  333. * @retval HAL status
  334. */
  335. HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
  336. {
  337. /* Check the SMBUS handle allocation */
  338. if (hsmbus == NULL)
  339. {
  340. return HAL_ERROR;
  341. }
  342. /* Check the parameters */
  343. assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
  344. hsmbus->State = HAL_SMBUS_STATE_BUSY;
  345. /* Disable the SMBUS Peripheral Clock */
  346. __HAL_SMBUS_DISABLE(hsmbus);
  347. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  348. if (hsmbus->MspDeInitCallback == NULL)
  349. {
  350. hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
  351. }
  352. /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  353. hsmbus->MspDeInitCallback(hsmbus);
  354. #else
  355. /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  356. HAL_SMBUS_MspDeInit(hsmbus);
  357. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  358. hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
  359. hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
  360. hsmbus->State = HAL_SMBUS_STATE_RESET;
  361. /* Release Lock */
  362. __HAL_UNLOCK(hsmbus);
  363. return HAL_OK;
  364. }
  365. /**
  366. * @brief Initialize the SMBUS MSP.
  367. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  368. * the configuration information for the specified SMBUS.
  369. * @retval None
  370. */
  371. __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
  372. {
  373. /* Prevent unused argument(s) compilation warning */
  374. UNUSED(hsmbus);
  375. /* NOTE : This function should not be modified, when the callback is needed,
  376. the HAL_SMBUS_MspInit could be implemented in the user file
  377. */
  378. }
  379. /**
  380. * @brief DeInitialize the SMBUS MSP.
  381. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  382. * the configuration information for the specified SMBUS.
  383. * @retval None
  384. */
  385. __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
  386. {
  387. /* Prevent unused argument(s) compilation warning */
  388. UNUSED(hsmbus);
  389. /* NOTE : This function should not be modified, when the callback is needed,
  390. the HAL_SMBUS_MspDeInit could be implemented in the user file
  391. */
  392. }
  393. /**
  394. * @brief Configure Analog noise filter.
  395. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  396. * the configuration information for the specified SMBUS.
  397. * @param AnalogFilter This parameter can be one of the following values:
  398. * @arg @ref SMBUS_ANALOGFILTER_ENABLE
  399. * @arg @ref SMBUS_ANALOGFILTER_DISABLE
  400. * @retval HAL status
  401. */
  402. HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
  403. {
  404. /* Check the parameters */
  405. assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
  406. assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
  407. if (hsmbus->State == HAL_SMBUS_STATE_READY)
  408. {
  409. /* Process Locked */
  410. __HAL_LOCK(hsmbus);
  411. hsmbus->State = HAL_SMBUS_STATE_BUSY;
  412. /* Disable the selected SMBUS peripheral */
  413. __HAL_SMBUS_DISABLE(hsmbus);
  414. /* Reset ANOFF bit */
  415. hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
  416. /* Set analog filter bit*/
  417. hsmbus->Instance->CR1 |= AnalogFilter;
  418. __HAL_SMBUS_ENABLE(hsmbus);
  419. hsmbus->State = HAL_SMBUS_STATE_READY;
  420. /* Process Unlocked */
  421. __HAL_UNLOCK(hsmbus);
  422. return HAL_OK;
  423. }
  424. else
  425. {
  426. return HAL_BUSY;
  427. }
  428. }
  429. /**
  430. * @brief Configure Digital noise filter.
  431. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  432. * the configuration information for the specified SMBUS.
  433. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
  434. * @retval HAL status
  435. */
  436. HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
  437. {
  438. uint32_t tmpreg;
  439. /* Check the parameters */
  440. assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
  441. assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
  442. if (hsmbus->State == HAL_SMBUS_STATE_READY)
  443. {
  444. /* Process Locked */
  445. __HAL_LOCK(hsmbus);
  446. hsmbus->State = HAL_SMBUS_STATE_BUSY;
  447. /* Disable the selected SMBUS peripheral */
  448. __HAL_SMBUS_DISABLE(hsmbus);
  449. /* Get the old register value */
  450. tmpreg = hsmbus->Instance->CR1;
  451. /* Reset I2C DNF bits [11:8] */
  452. tmpreg &= ~(I2C_CR1_DNF);
  453. /* Set I2Cx DNF coefficient */
  454. tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
  455. /* Store the new register value */
  456. hsmbus->Instance->CR1 = tmpreg;
  457. __HAL_SMBUS_ENABLE(hsmbus);
  458. hsmbus->State = HAL_SMBUS_STATE_READY;
  459. /* Process Unlocked */
  460. __HAL_UNLOCK(hsmbus);
  461. return HAL_OK;
  462. }
  463. else
  464. {
  465. return HAL_BUSY;
  466. }
  467. }
  468. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  469. /**
  470. * @brief Register a User SMBUS Callback
  471. * To be used instead of the weak predefined callback
  472. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  473. * the configuration information for the specified SMBUS.
  474. * @param CallbackID ID of the callback to be registered
  475. * This parameter can be one of the following values:
  476. * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  477. * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  478. * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  479. * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  480. * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  481. * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
  482. * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  483. * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
  484. * @param pCallback pointer to the Callback function
  485. * @retval HAL status
  486. */
  487. HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
  488. {
  489. HAL_StatusTypeDef status = HAL_OK;
  490. if (pCallback == NULL)
  491. {
  492. /* Update the error code */
  493. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  494. return HAL_ERROR;
  495. }
  496. /* Process locked */
  497. __HAL_LOCK(hsmbus);
  498. if (HAL_SMBUS_STATE_READY == hsmbus->State)
  499. {
  500. switch (CallbackID)
  501. {
  502. case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
  503. hsmbus->MasterTxCpltCallback = pCallback;
  504. break;
  505. case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
  506. hsmbus->MasterRxCpltCallback = pCallback;
  507. break;
  508. case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
  509. hsmbus->SlaveTxCpltCallback = pCallback;
  510. break;
  511. case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
  512. hsmbus->SlaveRxCpltCallback = pCallback;
  513. break;
  514. case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
  515. hsmbus->ListenCpltCallback = pCallback;
  516. break;
  517. case HAL_SMBUS_ERROR_CB_ID :
  518. hsmbus->ErrorCallback = pCallback;
  519. break;
  520. case HAL_SMBUS_MSPINIT_CB_ID :
  521. hsmbus->MspInitCallback = pCallback;
  522. break;
  523. case HAL_SMBUS_MSPDEINIT_CB_ID :
  524. hsmbus->MspDeInitCallback = pCallback;
  525. break;
  526. default :
  527. /* Update the error code */
  528. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  529. /* Return error status */
  530. status = HAL_ERROR;
  531. break;
  532. }
  533. }
  534. else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
  535. {
  536. switch (CallbackID)
  537. {
  538. case HAL_SMBUS_MSPINIT_CB_ID :
  539. hsmbus->MspInitCallback = pCallback;
  540. break;
  541. case HAL_SMBUS_MSPDEINIT_CB_ID :
  542. hsmbus->MspDeInitCallback = pCallback;
  543. break;
  544. default :
  545. /* Update the error code */
  546. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  547. /* Return error status */
  548. status = HAL_ERROR;
  549. break;
  550. }
  551. }
  552. else
  553. {
  554. /* Update the error code */
  555. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  556. /* Return error status */
  557. status = HAL_ERROR;
  558. }
  559. /* Release Lock */
  560. __HAL_UNLOCK(hsmbus);
  561. return status;
  562. }
  563. /**
  564. * @brief Unregister an SMBUS Callback
  565. * SMBUS callback is redirected to the weak predefined callback
  566. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  567. * the configuration information for the specified SMBUS.
  568. * @param CallbackID ID of the callback to be unregistered
  569. * This parameter can be one of the following values:
  570. * This parameter can be one of the following values:
  571. * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  572. * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  573. * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  574. * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  575. * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  576. * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
  577. * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  578. * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
  579. * @retval HAL status
  580. */
  581. HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
  582. {
  583. HAL_StatusTypeDef status = HAL_OK;
  584. /* Process locked */
  585. __HAL_LOCK(hsmbus);
  586. if (HAL_SMBUS_STATE_READY == hsmbus->State)
  587. {
  588. switch (CallbackID)
  589. {
  590. case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
  591. hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
  592. break;
  593. case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
  594. hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
  595. break;
  596. case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
  597. hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
  598. break;
  599. case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
  600. hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
  601. break;
  602. case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
  603. hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
  604. break;
  605. case HAL_SMBUS_ERROR_CB_ID :
  606. hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
  607. break;
  608. case HAL_SMBUS_MSPINIT_CB_ID :
  609. hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
  610. break;
  611. case HAL_SMBUS_MSPDEINIT_CB_ID :
  612. hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
  613. break;
  614. default :
  615. /* Update the error code */
  616. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  617. /* Return error status */
  618. status = HAL_ERROR;
  619. break;
  620. }
  621. }
  622. else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
  623. {
  624. switch (CallbackID)
  625. {
  626. case HAL_SMBUS_MSPINIT_CB_ID :
  627. hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
  628. break;
  629. case HAL_SMBUS_MSPDEINIT_CB_ID :
  630. hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
  631. break;
  632. default :
  633. /* Update the error code */
  634. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  635. /* Return error status */
  636. status = HAL_ERROR;
  637. break;
  638. }
  639. }
  640. else
  641. {
  642. /* Update the error code */
  643. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  644. /* Return error status */
  645. status = HAL_ERROR;
  646. }
  647. /* Release Lock */
  648. __HAL_UNLOCK(hsmbus);
  649. return status;
  650. }
  651. /**
  652. * @brief Register the Slave Address Match SMBUS Callback
  653. * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
  654. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  655. * the configuration information for the specified SMBUS.
  656. * @param pCallback pointer to the Address Match Callback function
  657. * @retval HAL status
  658. */
  659. HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
  660. {
  661. HAL_StatusTypeDef status = HAL_OK;
  662. if (pCallback == NULL)
  663. {
  664. /* Update the error code */
  665. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  666. return HAL_ERROR;
  667. }
  668. /* Process locked */
  669. __HAL_LOCK(hsmbus);
  670. if (HAL_SMBUS_STATE_READY == hsmbus->State)
  671. {
  672. hsmbus->AddrCallback = pCallback;
  673. }
  674. else
  675. {
  676. /* Update the error code */
  677. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  678. /* Return error status */
  679. status = HAL_ERROR;
  680. }
  681. /* Release Lock */
  682. __HAL_UNLOCK(hsmbus);
  683. return status;
  684. }
  685. /**
  686. * @brief UnRegister the Slave Address Match SMBUS Callback
  687. * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
  688. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  689. * the configuration information for the specified SMBUS.
  690. * @retval HAL status
  691. */
  692. HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
  693. {
  694. HAL_StatusTypeDef status = HAL_OK;
  695. /* Process locked */
  696. __HAL_LOCK(hsmbus);
  697. if (HAL_SMBUS_STATE_READY == hsmbus->State)
  698. {
  699. hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
  700. }
  701. else
  702. {
  703. /* Update the error code */
  704. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
  705. /* Return error status */
  706. status = HAL_ERROR;
  707. }
  708. /* Release Lock */
  709. __HAL_UNLOCK(hsmbus);
  710. return status;
  711. }
  712. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  713. /**
  714. * @}
  715. */
  716. /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
  717. * @brief Data transfers functions
  718. *
  719. @verbatim
  720. ===============================================================================
  721. ##### IO operation functions #####
  722. ===============================================================================
  723. [..]
  724. This subsection provides a set of functions allowing to manage the SMBUS data
  725. transfers.
  726. (#) Blocking mode function to check if device is ready for usage is :
  727. (++) HAL_SMBUS_IsDeviceReady()
  728. (#) There is only one mode of transfer:
  729. (++) Non-Blocking mode : The communication is performed using Interrupts.
  730. These functions return the status of the transfer startup.
  731. The end of the data processing will be indicated through the
  732. dedicated SMBUS IRQ when using Interrupt mode.
  733. (#) Non-Blocking mode functions with Interrupt are :
  734. (++) HAL_SMBUS_Master_Transmit_IT()
  735. (++) HAL_SMBUS_Master_Receive_IT()
  736. (++) HAL_SMBUS_Slave_Transmit_IT()
  737. (++) HAL_SMBUS_Slave_Receive_IT()
  738. (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
  739. (++) HAL_SMBUS_DisableListen_IT()
  740. (++) HAL_SMBUS_EnableAlert_IT()
  741. (++) HAL_SMBUS_DisableAlert_IT()
  742. (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
  743. (++) HAL_SMBUS_MasterTxCpltCallback()
  744. (++) HAL_SMBUS_MasterRxCpltCallback()
  745. (++) HAL_SMBUS_SlaveTxCpltCallback()
  746. (++) HAL_SMBUS_SlaveRxCpltCallback()
  747. (++) HAL_SMBUS_AddrCallback()
  748. (++) HAL_SMBUS_ListenCpltCallback()
  749. (++) HAL_SMBUS_ErrorCallback()
  750. @endverbatim
  751. * @{
  752. */
  753. /**
  754. * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
  755. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  756. * the configuration information for the specified SMBUS.
  757. * @param DevAddress Target device address: The device 7 bits address value
  758. * in datasheet must be shifted to the left before calling the interface
  759. * @param pData Pointer to data buffer
  760. * @param Size Amount of data to be sent
  761. * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
  762. * @retval HAL status
  763. */
  764. HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
  765. {
  766. uint32_t tmp;
  767. /* Check the parameters */
  768. assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
  769. if (hsmbus->State == HAL_SMBUS_STATE_READY)
  770. {
  771. /* Process Locked */
  772. __HAL_LOCK(hsmbus);
  773. hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
  774. hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
  775. /* Prepare transfer parameters */
  776. hsmbus->pBuffPtr = pData;
  777. hsmbus->XferCount = Size;
  778. hsmbus->XferOptions = XferOptions;
  779. /* In case of Quick command, remove autoend mode */
  780. /* Manage the stop generation by software */
  781. if (hsmbus->pBuffPtr == NULL)
  782. {
  783. hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
  784. }
  785. if (Size > MAX_NBYTE_SIZE)
  786. {
  787. hsmbus->XferSize = MAX_NBYTE_SIZE;
  788. }
  789. else
  790. {
  791. hsmbus->XferSize = Size;
  792. }
  793. /* Send Slave Address */
  794. /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
  795. if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
  796. {
  797. SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
  798. }
  799. else
  800. {
  801. /* If transfer direction not change, do not generate Restart Condition */
  802. /* Mean Previous state is same as current state */
  803. /* Store current volatile XferOptions, misra rule */
  804. tmp = hsmbus->XferOptions;
  805. if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
  806. {
  807. SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
  808. }
  809. /* Else transfer direction change, so generate Restart with new transfer direction */
  810. else
  811. {
  812. /* Convert OTHER_xxx XferOptions if any */
  813. SMBUS_ConvertOtherXferOptions(hsmbus);
  814. /* Handle Transfer */
  815. SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
  816. }
  817. /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
  818. /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
  819. if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
  820. {
  821. hsmbus->XferSize--;
  822. hsmbus->XferCount--;
  823. }
  824. }
  825. /* Process Unlocked */
  826. __HAL_UNLOCK(hsmbus);
  827. /* Note : The SMBUS interrupts must be enabled after unlocking current process
  828. to avoid the risk of SMBUS interrupt handle execution before current
  829. process unlock */
  830. SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
  831. return HAL_OK;
  832. }
  833. else
  834. {
  835. return HAL_BUSY;
  836. }
  837. }
  838. /**
  839. * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
  840. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  841. * the configuration information for the specified SMBUS.
  842. * @param DevAddress Target device address: The device 7 bits address value
  843. * in datasheet must be shifted to the left before calling the interface
  844. * @param pData Pointer to data buffer
  845. * @param Size Amount of data to be sent
  846. * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
  847. * @retval HAL status
  848. */
  849. HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
  850. {
  851. uint32_t tmp;
  852. /* Check the parameters */
  853. assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
  854. if (hsmbus->State == HAL_SMBUS_STATE_READY)
  855. {
  856. /* Process Locked */
  857. __HAL_LOCK(hsmbus);
  858. hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
  859. hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
  860. /* Prepare transfer parameters */
  861. hsmbus->pBuffPtr = pData;
  862. hsmbus->XferCount = Size;
  863. hsmbus->XferOptions = XferOptions;
  864. /* In case of Quick command, remove autoend mode */
  865. /* Manage the stop generation by software */
  866. if (hsmbus->pBuffPtr == NULL)
  867. {
  868. hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
  869. }
  870. if (Size > MAX_NBYTE_SIZE)
  871. {
  872. hsmbus->XferSize = MAX_NBYTE_SIZE;
  873. }
  874. else
  875. {
  876. hsmbus->XferSize = Size;
  877. }
  878. /* Send Slave Address */
  879. /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
  880. if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
  881. {
  882. SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
  883. }
  884. else
  885. {
  886. /* If transfer direction not change, do not generate Restart Condition */
  887. /* Mean Previous state is same as current state */
  888. /* Store current volatile XferOptions, Misra rule */
  889. tmp = hsmbus->XferOptions;
  890. if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
  891. {
  892. SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
  893. }
  894. /* Else transfer direction change, so generate Restart with new transfer direction */
  895. else
  896. {
  897. /* Convert OTHER_xxx XferOptions if any */
  898. SMBUS_ConvertOtherXferOptions(hsmbus);
  899. /* Handle Transfer */
  900. SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
  901. }
  902. }
  903. /* Process Unlocked */
  904. __HAL_UNLOCK(hsmbus);
  905. /* Note : The SMBUS interrupts must be enabled after unlocking current process
  906. to avoid the risk of SMBUS interrupt handle execution before current
  907. process unlock */
  908. SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
  909. return HAL_OK;
  910. }
  911. else
  912. {
  913. return HAL_BUSY;
  914. }
  915. }
  916. /**
  917. * @brief Abort a master/host SMBUS process communication with Interrupt.
  918. * @note This abort can be called only if state is ready
  919. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  920. * the configuration information for the specified SMBUS.
  921. * @param DevAddress Target device address: The device 7 bits address value
  922. * in datasheet must be shifted to the left before calling the interface
  923. * @retval HAL status
  924. */
  925. HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
  926. {
  927. if (hsmbus->State == HAL_SMBUS_STATE_READY)
  928. {
  929. /* Process Locked */
  930. __HAL_LOCK(hsmbus);
  931. /* Keep the same state as previous */
  932. /* to perform as well the call of the corresponding end of transfer callback */
  933. if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
  934. {
  935. hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
  936. }
  937. else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
  938. {
  939. hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
  940. }
  941. else
  942. {
  943. /* Wrong usage of abort function */
  944. /* This function should be used only in case of abort monitored by master device */
  945. return HAL_ERROR;
  946. }
  947. hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
  948. /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
  949. /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
  950. SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
  951. /* Process Unlocked */
  952. __HAL_UNLOCK(hsmbus);
  953. /* Note : The SMBUS interrupts must be enabled after unlocking current process
  954. to avoid the risk of SMBUS interrupt handle execution before current
  955. process unlock */
  956. if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
  957. {
  958. SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
  959. }
  960. else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
  961. {
  962. SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
  963. }
  964. else
  965. {
  966. /* Nothing to do */
  967. }
  968. return HAL_OK;
  969. }
  970. else
  971. {
  972. return HAL_BUSY;
  973. }
  974. }
  975. /**
  976. * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
  977. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  978. * the configuration information for the specified SMBUS.
  979. * @param pData Pointer to data buffer
  980. * @param Size Amount of data to be sent
  981. * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
  982. * @retval HAL status
  983. */
  984. HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
  985. {
  986. /* Check the parameters */
  987. assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
  988. if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
  989. {
  990. if ((pData == NULL) || (Size == 0UL))
  991. {
  992. hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
  993. return HAL_ERROR;
  994. }
  995. /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
  996. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
  997. /* Process Locked */
  998. __HAL_LOCK(hsmbus);
  999. hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
  1000. hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
  1001. /* Set SBC bit to manage Acknowledge at each bit */
  1002. hsmbus->Instance->CR1 |= I2C_CR1_SBC;
  1003. /* Enable Address Acknowledge */
  1004. hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
  1005. /* Prepare transfer parameters */
  1006. hsmbus->pBuffPtr = pData;
  1007. hsmbus->XferCount = Size;
  1008. hsmbus->XferOptions = XferOptions;
  1009. /* Convert OTHER_xxx XferOptions if any */
  1010. SMBUS_ConvertOtherXferOptions(hsmbus);
  1011. if (Size > MAX_NBYTE_SIZE)
  1012. {
  1013. hsmbus->XferSize = MAX_NBYTE_SIZE;
  1014. }
  1015. else
  1016. {
  1017. hsmbus->XferSize = Size;
  1018. }
  1019. /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
  1020. if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
  1021. {
  1022. SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
  1023. }
  1024. else
  1025. {
  1026. /* Set NBYTE to transmit */
  1027. SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
  1028. /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
  1029. /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
  1030. if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
  1031. {
  1032. hsmbus->XferSize--;
  1033. hsmbus->XferCount--;
  1034. }
  1035. }
  1036. /* Clear ADDR flag after prepare the transfer parameters */
  1037. /* This action will generate an acknowledge to the HOST */
  1038. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
  1039. /* Process Unlocked */
  1040. __HAL_UNLOCK(hsmbus);
  1041. /* Note : The SMBUS interrupts must be enabled after unlocking current process
  1042. to avoid the risk of SMBUS interrupt handle execution before current
  1043. process unlock */
  1044. /* REnable ADDR interrupt */
  1045. SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
  1046. return HAL_OK;
  1047. }
  1048. else
  1049. {
  1050. return HAL_BUSY;
  1051. }
  1052. }
  1053. /**
  1054. * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
  1055. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1056. * the configuration information for the specified SMBUS.
  1057. * @param pData Pointer to data buffer
  1058. * @param Size Amount of data to be sent
  1059. * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
  1060. * @retval HAL status
  1061. */
  1062. HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
  1063. {
  1064. /* Check the parameters */
  1065. assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
  1066. if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
  1067. {
  1068. if ((pData == NULL) || (Size == 0UL))
  1069. {
  1070. hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
  1071. return HAL_ERROR;
  1072. }
  1073. /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
  1074. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
  1075. /* Process Locked */
  1076. __HAL_LOCK(hsmbus);
  1077. hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
  1078. hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
  1079. /* Set SBC bit to manage Acknowledge at each bit */
  1080. hsmbus->Instance->CR1 |= I2C_CR1_SBC;
  1081. /* Enable Address Acknowledge */
  1082. hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
  1083. /* Prepare transfer parameters */
  1084. hsmbus->pBuffPtr = pData;
  1085. hsmbus->XferSize = Size;
  1086. hsmbus->XferCount = Size;
  1087. hsmbus->XferOptions = XferOptions;
  1088. /* Convert OTHER_xxx XferOptions if any */
  1089. SMBUS_ConvertOtherXferOptions(hsmbus);
  1090. /* Set NBYTE to receive */
  1091. /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
  1092. /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
  1093. /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
  1094. /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
  1095. if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
  1096. {
  1097. SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
  1098. }
  1099. else
  1100. {
  1101. SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
  1102. }
  1103. /* Clear ADDR flag after prepare the transfer parameters */
  1104. /* This action will generate an acknowledge to the HOST */
  1105. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
  1106. /* Process Unlocked */
  1107. __HAL_UNLOCK(hsmbus);
  1108. /* Note : The SMBUS interrupts must be enabled after unlocking current process
  1109. to avoid the risk of SMBUS interrupt handle execution before current
  1110. process unlock */
  1111. /* REnable ADDR interrupt */
  1112. SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
  1113. return HAL_OK;
  1114. }
  1115. else
  1116. {
  1117. return HAL_BUSY;
  1118. }
  1119. }
  1120. /**
  1121. * @brief Enable the Address listen mode with Interrupt.
  1122. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1123. * the configuration information for the specified SMBUS.
  1124. * @retval HAL status
  1125. */
  1126. HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
  1127. {
  1128. hsmbus->State = HAL_SMBUS_STATE_LISTEN;
  1129. /* Enable the Address Match interrupt */
  1130. SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
  1131. return HAL_OK;
  1132. }
  1133. /**
  1134. * @brief Disable the Address listen mode with Interrupt.
  1135. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1136. * the configuration information for the specified SMBUS.
  1137. * @retval HAL status
  1138. */
  1139. HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
  1140. {
  1141. /* Disable Address listen mode only if a transfer is not ongoing */
  1142. if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
  1143. {
  1144. hsmbus->State = HAL_SMBUS_STATE_READY;
  1145. /* Disable the Address Match interrupt */
  1146. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
  1147. return HAL_OK;
  1148. }
  1149. else
  1150. {
  1151. return HAL_BUSY;
  1152. }
  1153. }
  1154. /**
  1155. * @brief Enable the SMBUS alert mode with Interrupt.
  1156. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1157. * the configuration information for the specified SMBUSx peripheral.
  1158. * @retval HAL status
  1159. */
  1160. HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
  1161. {
  1162. /* Enable SMBus alert */
  1163. hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
  1164. /* Clear ALERT flag */
  1165. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
  1166. /* Enable Alert Interrupt */
  1167. SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
  1168. return HAL_OK;
  1169. }
  1170. /**
  1171. * @brief Disable the SMBUS alert mode with Interrupt.
  1172. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1173. * the configuration information for the specified SMBUSx peripheral.
  1174. * @retval HAL status
  1175. */
  1176. HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
  1177. {
  1178. /* Enable SMBus alert */
  1179. hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
  1180. /* Disable Alert Interrupt */
  1181. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
  1182. return HAL_OK;
  1183. }
  1184. /**
  1185. * @brief Check if target device is ready for communication.
  1186. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1187. * the configuration information for the specified SMBUS.
  1188. * @param DevAddress Target device address: The device 7 bits address value
  1189. * in datasheet must be shifted to the left before calling the interface
  1190. * @param Trials Number of trials
  1191. * @param Timeout Timeout duration
  1192. * @retval HAL status
  1193. */
  1194. HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
  1195. {
  1196. uint32_t tickstart;
  1197. __IO uint32_t SMBUS_Trials = 0UL;
  1198. FlagStatus tmp1;
  1199. FlagStatus tmp2;
  1200. if (hsmbus->State == HAL_SMBUS_STATE_READY)
  1201. {
  1202. if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
  1203. {
  1204. return HAL_BUSY;
  1205. }
  1206. /* Process Locked */
  1207. __HAL_LOCK(hsmbus);
  1208. hsmbus->State = HAL_SMBUS_STATE_BUSY;
  1209. hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
  1210. do
  1211. {
  1212. /* Generate Start */
  1213. hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
  1214. /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
  1215. /* Wait until STOPF flag is set or a NACK flag is set*/
  1216. tickstart = HAL_GetTick();
  1217. tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
  1218. tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
  1219. while ((tmp1 == RESET) && (tmp2 == RESET))
  1220. {
  1221. if (Timeout != HAL_MAX_DELAY)
  1222. {
  1223. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
  1224. {
  1225. /* Device is ready */
  1226. hsmbus->State = HAL_SMBUS_STATE_READY;
  1227. /* Update SMBUS error code */
  1228. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
  1229. /* Process Unlocked */
  1230. __HAL_UNLOCK(hsmbus);
  1231. return HAL_ERROR;
  1232. }
  1233. }
  1234. tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
  1235. tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
  1236. }
  1237. /* Check if the NACKF flag has not been set */
  1238. if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
  1239. {
  1240. /* Wait until STOPF flag is reset */
  1241. if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
  1242. {
  1243. return HAL_ERROR;
  1244. }
  1245. /* Clear STOP Flag */
  1246. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
  1247. /* Device is ready */
  1248. hsmbus->State = HAL_SMBUS_STATE_READY;
  1249. /* Process Unlocked */
  1250. __HAL_UNLOCK(hsmbus);
  1251. return HAL_OK;
  1252. }
  1253. else
  1254. {
  1255. /* Wait until STOPF flag is reset */
  1256. if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
  1257. {
  1258. return HAL_ERROR;
  1259. }
  1260. /* Clear NACK Flag */
  1261. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
  1262. /* Clear STOP Flag, auto generated with autoend*/
  1263. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
  1264. }
  1265. /* Check if the maximum allowed number of trials has been reached */
  1266. if (SMBUS_Trials == Trials)
  1267. {
  1268. /* Generate Stop */
  1269. hsmbus->Instance->CR2 |= I2C_CR2_STOP;
  1270. /* Wait until STOPF flag is reset */
  1271. if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
  1272. {
  1273. return HAL_ERROR;
  1274. }
  1275. /* Clear STOP Flag */
  1276. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
  1277. }
  1278. /* Increment Trials */
  1279. SMBUS_Trials++;
  1280. }
  1281. while (SMBUS_Trials < Trials);
  1282. hsmbus->State = HAL_SMBUS_STATE_READY;
  1283. /* Update SMBUS error code */
  1284. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
  1285. /* Process Unlocked */
  1286. __HAL_UNLOCK(hsmbus);
  1287. return HAL_ERROR;
  1288. }
  1289. else
  1290. {
  1291. return HAL_BUSY;
  1292. }
  1293. }
  1294. /**
  1295. * @}
  1296. */
  1297. /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
  1298. * @{
  1299. */
  1300. /**
  1301. * @brief Handle SMBUS event interrupt request.
  1302. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1303. * the configuration information for the specified SMBUS.
  1304. * @retval None
  1305. */
  1306. void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
  1307. {
  1308. /* Use a local variable to store the current ISR flags */
  1309. /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
  1310. uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
  1311. uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
  1312. /* SMBUS in mode Transmitter ---------------------------------------------------*/
  1313. if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
  1314. {
  1315. /* Slave mode selected */
  1316. if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
  1317. {
  1318. (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
  1319. }
  1320. /* Master mode selected */
  1321. else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
  1322. {
  1323. (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
  1324. }
  1325. else
  1326. {
  1327. /* Nothing to do */
  1328. }
  1329. }
  1330. /* SMBUS in mode Receiver ----------------------------------------------------*/
  1331. if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
  1332. {
  1333. /* Slave mode selected */
  1334. if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
  1335. {
  1336. (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
  1337. }
  1338. /* Master mode selected */
  1339. else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
  1340. {
  1341. (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
  1342. }
  1343. else
  1344. {
  1345. /* Nothing to do */
  1346. }
  1347. }
  1348. /* SMBUS in mode Listener Only --------------------------------------------------*/
  1349. if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
  1350. {
  1351. if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
  1352. {
  1353. (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
  1354. }
  1355. }
  1356. }
  1357. /**
  1358. * @brief Handle SMBUS error interrupt request.
  1359. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1360. * the configuration information for the specified SMBUS.
  1361. * @retval None
  1362. */
  1363. void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
  1364. {
  1365. SMBUS_ITErrorHandler(hsmbus);
  1366. }
  1367. /**
  1368. * @brief Master Tx Transfer completed callback.
  1369. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1370. * the configuration information for the specified SMBUS.
  1371. * @retval None
  1372. */
  1373. __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  1374. {
  1375. /* Prevent unused argument(s) compilation warning */
  1376. UNUSED(hsmbus);
  1377. /* NOTE : This function should not be modified, when the callback is needed,
  1378. the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
  1379. */
  1380. }
  1381. /**
  1382. * @brief Master Rx Transfer completed callback.
  1383. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1384. * the configuration information for the specified SMBUS.
  1385. * @retval None
  1386. */
  1387. __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  1388. {
  1389. /* Prevent unused argument(s) compilation warning */
  1390. UNUSED(hsmbus);
  1391. /* NOTE : This function should not be modified, when the callback is needed,
  1392. the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
  1393. */
  1394. }
  1395. /** @brief Slave Tx Transfer completed callback.
  1396. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1397. * the configuration information for the specified SMBUS.
  1398. * @retval None
  1399. */
  1400. __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  1401. {
  1402. /* Prevent unused argument(s) compilation warning */
  1403. UNUSED(hsmbus);
  1404. /* NOTE : This function should not be modified, when the callback is needed,
  1405. the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
  1406. */
  1407. }
  1408. /**
  1409. * @brief Slave Rx Transfer completed callback.
  1410. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1411. * the configuration information for the specified SMBUS.
  1412. * @retval None
  1413. */
  1414. __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  1415. {
  1416. /* Prevent unused argument(s) compilation warning */
  1417. UNUSED(hsmbus);
  1418. /* NOTE : This function should not be modified, when the callback is needed,
  1419. the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
  1420. */
  1421. }
  1422. /**
  1423. * @brief Slave Address Match callback.
  1424. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1425. * the configuration information for the specified SMBUS.
  1426. * @param TransferDirection Master request Transfer Direction (Write/Read)
  1427. * @param AddrMatchCode Address Match Code
  1428. * @retval None
  1429. */
  1430. __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
  1431. {
  1432. /* Prevent unused argument(s) compilation warning */
  1433. UNUSED(hsmbus);
  1434. UNUSED(TransferDirection);
  1435. UNUSED(AddrMatchCode);
  1436. /* NOTE : This function should not be modified, when the callback is needed,
  1437. the HAL_SMBUS_AddrCallback() could be implemented in the user file
  1438. */
  1439. }
  1440. /**
  1441. * @brief Listen Complete callback.
  1442. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1443. * the configuration information for the specified SMBUS.
  1444. * @retval None
  1445. */
  1446. __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  1447. {
  1448. /* Prevent unused argument(s) compilation warning */
  1449. UNUSED(hsmbus);
  1450. /* NOTE : This function should not be modified, when the callback is needed,
  1451. the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
  1452. */
  1453. }
  1454. /**
  1455. * @brief SMBUS error callback.
  1456. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1457. * the configuration information for the specified SMBUS.
  1458. * @retval None
  1459. */
  1460. __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
  1461. {
  1462. /* Prevent unused argument(s) compilation warning */
  1463. UNUSED(hsmbus);
  1464. /* NOTE : This function should not be modified, when the callback is needed,
  1465. the HAL_SMBUS_ErrorCallback() could be implemented in the user file
  1466. */
  1467. }
  1468. /**
  1469. * @}
  1470. */
  1471. /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
  1472. * @brief Peripheral State and Errors functions
  1473. *
  1474. @verbatim
  1475. ===============================================================================
  1476. ##### Peripheral State and Errors functions #####
  1477. ===============================================================================
  1478. [..]
  1479. This subsection permits to get in run-time the status of the peripheral
  1480. and the data flow.
  1481. @endverbatim
  1482. * @{
  1483. */
  1484. /**
  1485. * @brief Return the SMBUS handle state.
  1486. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1487. * the configuration information for the specified SMBUS.
  1488. * @retval HAL state
  1489. */
  1490. uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
  1491. {
  1492. /* Return SMBUS handle state */
  1493. return hsmbus->State;
  1494. }
  1495. /**
  1496. * @brief Return the SMBUS error code.
  1497. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1498. * the configuration information for the specified SMBUS.
  1499. * @retval SMBUS Error Code
  1500. */
  1501. uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
  1502. {
  1503. return hsmbus->ErrorCode;
  1504. }
  1505. /**
  1506. * @}
  1507. */
  1508. /**
  1509. * @}
  1510. */
  1511. /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
  1512. * @brief Data transfers Private functions
  1513. * @{
  1514. */
  1515. /**
  1516. * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
  1517. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1518. * the configuration information for the specified SMBUS.
  1519. * @param StatusFlags Value of Interrupt Flags.
  1520. * @retval HAL status
  1521. */
  1522. static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
  1523. {
  1524. uint16_t DevAddress;
  1525. /* Process Locked */
  1526. __HAL_LOCK(hsmbus);
  1527. if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
  1528. {
  1529. /* Clear NACK Flag */
  1530. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
  1531. /* Set corresponding Error Code */
  1532. /* No need to generate STOP, it is automatically done */
  1533. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
  1534. /* Process Unlocked */
  1535. __HAL_UNLOCK(hsmbus);
  1536. /* Call the Error callback to inform upper layer */
  1537. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1538. hsmbus->ErrorCallback(hsmbus);
  1539. #else
  1540. HAL_SMBUS_ErrorCallback(hsmbus);
  1541. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1542. }
  1543. else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
  1544. {
  1545. /* Check and treat errors if errors occurs during STOP process */
  1546. SMBUS_ITErrorHandler(hsmbus);
  1547. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1548. if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
  1549. {
  1550. /* Disable Interrupt */
  1551. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
  1552. /* Clear STOP Flag */
  1553. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
  1554. /* Clear Configuration Register 2 */
  1555. SMBUS_RESET_CR2(hsmbus);
  1556. /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
  1557. /* Disable the selected SMBUS peripheral */
  1558. __HAL_SMBUS_DISABLE(hsmbus);
  1559. hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
  1560. hsmbus->State = HAL_SMBUS_STATE_READY;
  1561. /* Process Unlocked */
  1562. __HAL_UNLOCK(hsmbus);
  1563. /* REenable the selected SMBUS peripheral */
  1564. __HAL_SMBUS_ENABLE(hsmbus);
  1565. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1566. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1567. hsmbus->MasterTxCpltCallback(hsmbus);
  1568. #else
  1569. HAL_SMBUS_MasterTxCpltCallback(hsmbus);
  1570. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1571. }
  1572. else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
  1573. {
  1574. /* Store Last receive data if any */
  1575. if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
  1576. {
  1577. /* Read data from RXDR */
  1578. *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
  1579. /* Increment Buffer pointer */
  1580. hsmbus->pBuffPtr++;
  1581. if ((hsmbus->XferSize > 0U))
  1582. {
  1583. hsmbus->XferSize--;
  1584. hsmbus->XferCount--;
  1585. }
  1586. }
  1587. /* Disable Interrupt */
  1588. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
  1589. /* Clear STOP Flag */
  1590. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
  1591. /* Clear Configuration Register 2 */
  1592. SMBUS_RESET_CR2(hsmbus);
  1593. hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
  1594. hsmbus->State = HAL_SMBUS_STATE_READY;
  1595. /* Process Unlocked */
  1596. __HAL_UNLOCK(hsmbus);
  1597. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1598. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1599. hsmbus->MasterRxCpltCallback(hsmbus);
  1600. #else
  1601. HAL_SMBUS_MasterRxCpltCallback(hsmbus);
  1602. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1603. }
  1604. else
  1605. {
  1606. /* Nothing to do */
  1607. }
  1608. }
  1609. else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
  1610. {
  1611. /* Read data from RXDR */
  1612. *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
  1613. /* Increment Buffer pointer */
  1614. hsmbus->pBuffPtr++;
  1615. /* Increment Size counter */
  1616. hsmbus->XferSize--;
  1617. hsmbus->XferCount--;
  1618. }
  1619. else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
  1620. {
  1621. /* Write data to TXDR */
  1622. hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
  1623. /* Increment Buffer pointer */
  1624. hsmbus->pBuffPtr++;
  1625. /* Increment Size counter */
  1626. hsmbus->XferSize--;
  1627. hsmbus->XferCount--;
  1628. }
  1629. else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
  1630. {
  1631. if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
  1632. {
  1633. DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
  1634. if (hsmbus->XferCount > MAX_NBYTE_SIZE)
  1635. {
  1636. SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
  1637. hsmbus->XferSize = MAX_NBYTE_SIZE;
  1638. }
  1639. else
  1640. {
  1641. hsmbus->XferSize = hsmbus->XferCount;
  1642. SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
  1643. /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
  1644. /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
  1645. if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
  1646. {
  1647. hsmbus->XferSize--;
  1648. hsmbus->XferCount--;
  1649. }
  1650. }
  1651. }
  1652. else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
  1653. {
  1654. /* Call TxCpltCallback() if no stop mode is set */
  1655. if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
  1656. {
  1657. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1658. if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
  1659. {
  1660. /* Disable Interrupt */
  1661. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
  1662. hsmbus->PreviousState = hsmbus->State;
  1663. hsmbus->State = HAL_SMBUS_STATE_READY;
  1664. /* Process Unlocked */
  1665. __HAL_UNLOCK(hsmbus);
  1666. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1667. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1668. hsmbus->MasterTxCpltCallback(hsmbus);
  1669. #else
  1670. HAL_SMBUS_MasterTxCpltCallback(hsmbus);
  1671. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1672. }
  1673. else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
  1674. {
  1675. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
  1676. hsmbus->PreviousState = hsmbus->State;
  1677. hsmbus->State = HAL_SMBUS_STATE_READY;
  1678. /* Process Unlocked */
  1679. __HAL_UNLOCK(hsmbus);
  1680. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1681. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1682. hsmbus->MasterRxCpltCallback(hsmbus);
  1683. #else
  1684. HAL_SMBUS_MasterRxCpltCallback(hsmbus);
  1685. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1686. }
  1687. else
  1688. {
  1689. /* Nothing to do */
  1690. }
  1691. }
  1692. }
  1693. else
  1694. {
  1695. /* Nothing to do */
  1696. }
  1697. }
  1698. else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
  1699. {
  1700. if (hsmbus->XferCount == 0U)
  1701. {
  1702. /* Specific use case for Quick command */
  1703. if (hsmbus->pBuffPtr == NULL)
  1704. {
  1705. /* Generate a Stop command */
  1706. hsmbus->Instance->CR2 |= I2C_CR2_STOP;
  1707. }
  1708. /* Call TxCpltCallback() if no stop mode is set */
  1709. else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
  1710. {
  1711. /* No Generate Stop, to permit restart mode */
  1712. /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
  1713. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1714. if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
  1715. {
  1716. /* Disable Interrupt */
  1717. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
  1718. hsmbus->PreviousState = hsmbus->State;
  1719. hsmbus->State = HAL_SMBUS_STATE_READY;
  1720. /* Process Unlocked */
  1721. __HAL_UNLOCK(hsmbus);
  1722. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1723. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1724. hsmbus->MasterTxCpltCallback(hsmbus);
  1725. #else
  1726. HAL_SMBUS_MasterTxCpltCallback(hsmbus);
  1727. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1728. }
  1729. else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
  1730. {
  1731. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
  1732. hsmbus->PreviousState = hsmbus->State;
  1733. hsmbus->State = HAL_SMBUS_STATE_READY;
  1734. /* Process Unlocked */
  1735. __HAL_UNLOCK(hsmbus);
  1736. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1737. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1738. hsmbus->MasterRxCpltCallback(hsmbus);
  1739. #else
  1740. HAL_SMBUS_MasterRxCpltCallback(hsmbus);
  1741. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1742. }
  1743. else
  1744. {
  1745. /* Nothing to do */
  1746. }
  1747. }
  1748. else
  1749. {
  1750. /* Nothing to do */
  1751. }
  1752. }
  1753. }
  1754. else
  1755. {
  1756. /* Nothing to do */
  1757. }
  1758. /* Process Unlocked */
  1759. __HAL_UNLOCK(hsmbus);
  1760. return HAL_OK;
  1761. }
  1762. /**
  1763. * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
  1764. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1765. * the configuration information for the specified SMBUS.
  1766. * @param StatusFlags Value of Interrupt Flags.
  1767. * @retval HAL status
  1768. */
  1769. static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
  1770. {
  1771. uint8_t TransferDirection;
  1772. uint16_t SlaveAddrCode;
  1773. /* Process Locked */
  1774. __HAL_LOCK(hsmbus);
  1775. if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
  1776. {
  1777. /* Check that SMBUS transfer finished */
  1778. /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
  1779. /* Mean XferCount == 0*/
  1780. /* So clear Flag NACKF only */
  1781. if (hsmbus->XferCount == 0U)
  1782. {
  1783. /* Clear NACK Flag */
  1784. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
  1785. /* Process Unlocked */
  1786. __HAL_UNLOCK(hsmbus);
  1787. }
  1788. else
  1789. {
  1790. /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
  1791. /* Clear NACK Flag */
  1792. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
  1793. /* Set HAL State to "Idle" State, mean to LISTEN state */
  1794. /* So reset Slave Busy state */
  1795. hsmbus->PreviousState = hsmbus->State;
  1796. hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
  1797. hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
  1798. /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
  1799. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
  1800. /* Set ErrorCode corresponding to a Non-Acknowledge */
  1801. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
  1802. /* Process Unlocked */
  1803. __HAL_UNLOCK(hsmbus);
  1804. /* Call the Error callback to inform upper layer */
  1805. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1806. hsmbus->ErrorCallback(hsmbus);
  1807. #else
  1808. HAL_SMBUS_ErrorCallback(hsmbus);
  1809. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1810. }
  1811. }
  1812. else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
  1813. {
  1814. TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
  1815. SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
  1816. /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
  1817. /* Other ADDRInterrupt will be treat in next Listen usecase */
  1818. __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
  1819. /* Process Unlocked */
  1820. __HAL_UNLOCK(hsmbus);
  1821. /* Call Slave Addr callback */
  1822. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1823. hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
  1824. #else
  1825. HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
  1826. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1827. }
  1828. else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
  1829. {
  1830. if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
  1831. {
  1832. /* Read data from RXDR */
  1833. *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
  1834. /* Increment Buffer pointer */
  1835. hsmbus->pBuffPtr++;
  1836. hsmbus->XferSize--;
  1837. hsmbus->XferCount--;
  1838. if (hsmbus->XferCount == 1U)
  1839. {
  1840. /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
  1841. /* or only the last Byte of Transfer */
  1842. /* So reset the RELOAD bit mode */
  1843. hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
  1844. SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
  1845. }
  1846. else if (hsmbus->XferCount == 0U)
  1847. {
  1848. /* Last Byte is received, disable Interrupt */
  1849. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
  1850. /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
  1851. hsmbus->PreviousState = hsmbus->State;
  1852. hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
  1853. /* Process Unlocked */
  1854. __HAL_UNLOCK(hsmbus);
  1855. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1856. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1857. hsmbus->SlaveRxCpltCallback(hsmbus);
  1858. #else
  1859. HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
  1860. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1861. }
  1862. else
  1863. {
  1864. /* Set Reload for next Bytes */
  1865. SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
  1866. /* Ack last Byte Read */
  1867. hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
  1868. }
  1869. }
  1870. else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
  1871. {
  1872. if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
  1873. {
  1874. if (hsmbus->XferCount > MAX_NBYTE_SIZE)
  1875. {
  1876. SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
  1877. hsmbus->XferSize = MAX_NBYTE_SIZE;
  1878. }
  1879. else
  1880. {
  1881. hsmbus->XferSize = hsmbus->XferCount;
  1882. SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
  1883. /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
  1884. /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
  1885. if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
  1886. {
  1887. hsmbus->XferSize--;
  1888. hsmbus->XferCount--;
  1889. }
  1890. }
  1891. }
  1892. }
  1893. else
  1894. {
  1895. /* Nothing to do */
  1896. }
  1897. }
  1898. else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
  1899. {
  1900. /* Write data to TXDR only if XferCount not reach "0" */
  1901. /* A TXIS flag can be set, during STOP treatment */
  1902. /* Check if all Data have already been sent */
  1903. /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
  1904. if (hsmbus->XferCount > 0U)
  1905. {
  1906. /* Write data to TXDR */
  1907. hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
  1908. /* Increment Buffer pointer */
  1909. hsmbus->pBuffPtr++;
  1910. hsmbus->XferCount--;
  1911. hsmbus->XferSize--;
  1912. }
  1913. if (hsmbus->XferCount == 0U)
  1914. {
  1915. /* Last Byte is Transmitted */
  1916. /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
  1917. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
  1918. hsmbus->PreviousState = hsmbus->State;
  1919. hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
  1920. /* Process Unlocked */
  1921. __HAL_UNLOCK(hsmbus);
  1922. /* Call the corresponding callback to inform upper layer of End of Transfer */
  1923. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1924. hsmbus->SlaveTxCpltCallback(hsmbus);
  1925. #else
  1926. HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
  1927. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1928. }
  1929. }
  1930. else
  1931. {
  1932. /* Nothing to do */
  1933. }
  1934. /* Check if STOPF is set */
  1935. if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
  1936. {
  1937. if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
  1938. {
  1939. /* Store Last receive data if any */
  1940. if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
  1941. {
  1942. /* Read data from RXDR */
  1943. *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
  1944. /* Increment Buffer pointer */
  1945. hsmbus->pBuffPtr++;
  1946. if ((hsmbus->XferSize > 0U))
  1947. {
  1948. hsmbus->XferSize--;
  1949. hsmbus->XferCount--;
  1950. }
  1951. }
  1952. /* Disable RX and TX Interrupts */
  1953. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
  1954. /* Disable ADDR Interrupt */
  1955. SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
  1956. /* Disable Address Acknowledge */
  1957. hsmbus->Instance->CR2 |= I2C_CR2_NACK;
  1958. /* Clear Configuration Register 2 */
  1959. SMBUS_RESET_CR2(hsmbus);
  1960. /* Clear STOP Flag */
  1961. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
  1962. /* Clear ADDR flag */
  1963. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
  1964. hsmbus->XferOptions = 0;
  1965. hsmbus->PreviousState = hsmbus->State;
  1966. hsmbus->State = HAL_SMBUS_STATE_READY;
  1967. /* Process Unlocked */
  1968. __HAL_UNLOCK(hsmbus);
  1969. /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
  1970. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  1971. hsmbus->ListenCpltCallback(hsmbus);
  1972. #else
  1973. HAL_SMBUS_ListenCpltCallback(hsmbus);
  1974. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  1975. }
  1976. }
  1977. /* Process Unlocked */
  1978. __HAL_UNLOCK(hsmbus);
  1979. return HAL_OK;
  1980. }
  1981. /**
  1982. * @brief Manage the enabling of Interrupts.
  1983. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  1984. * the configuration information for the specified SMBUS.
  1985. * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
  1986. * @retval HAL status
  1987. */
  1988. static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
  1989. {
  1990. uint32_t tmpisr = 0UL;
  1991. if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
  1992. {
  1993. /* Enable ERR interrupt */
  1994. tmpisr |= SMBUS_IT_ERRI;
  1995. }
  1996. if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
  1997. {
  1998. /* Enable ADDR, STOP interrupt */
  1999. tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
  2000. }
  2001. if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
  2002. {
  2003. /* Enable ERR, TC, STOP, NACK, RXI interrupt */
  2004. tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
  2005. }
  2006. if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
  2007. {
  2008. /* Enable ERR, TC, STOP, NACK, TXI interrupt */
  2009. tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
  2010. }
  2011. /* Enable interrupts only at the end */
  2012. /* to avoid the risk of SMBUS interrupt handle execution before */
  2013. /* all interrupts requested done */
  2014. __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
  2015. }
  2016. /**
  2017. * @brief Manage the disabling of Interrupts.
  2018. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  2019. * the configuration information for the specified SMBUS.
  2020. * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
  2021. * @retval HAL status
  2022. */
  2023. static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
  2024. {
  2025. uint32_t tmpisr = 0UL;
  2026. uint32_t tmpstate = hsmbus->State;
  2027. if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
  2028. {
  2029. /* Disable ERR interrupt */
  2030. tmpisr |= SMBUS_IT_ERRI;
  2031. }
  2032. if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
  2033. {
  2034. /* Disable TC, STOP, NACK and TXI interrupt */
  2035. tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
  2036. if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
  2037. && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
  2038. {
  2039. /* Disable ERR interrupt */
  2040. tmpisr |= SMBUS_IT_ERRI;
  2041. }
  2042. if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
  2043. {
  2044. /* Disable STOP and NACK interrupt */
  2045. tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
  2046. }
  2047. }
  2048. if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
  2049. {
  2050. /* Disable TC, STOP, NACK and RXI interrupt */
  2051. tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
  2052. if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
  2053. && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
  2054. {
  2055. /* Disable ERR interrupt */
  2056. tmpisr |= SMBUS_IT_ERRI;
  2057. }
  2058. if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
  2059. {
  2060. /* Disable STOP and NACK interrupt */
  2061. tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
  2062. }
  2063. }
  2064. if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
  2065. {
  2066. /* Disable ADDR, STOP and NACK interrupt */
  2067. tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
  2068. if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
  2069. {
  2070. /* Disable ERR interrupt */
  2071. tmpisr |= SMBUS_IT_ERRI;
  2072. }
  2073. }
  2074. /* Disable interrupts only at the end */
  2075. /* to avoid a breaking situation like at "t" time */
  2076. /* all disable interrupts request are not done */
  2077. __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
  2078. }
  2079. /**
  2080. * @brief SMBUS interrupts error handler.
  2081. * @param hsmbus SMBUS handle.
  2082. * @retval None
  2083. */
  2084. static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus)
  2085. {
  2086. uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
  2087. uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
  2088. uint32_t tmpstate;
  2089. uint32_t tmperror;
  2090. /* SMBUS Bus error interrupt occurred ------------------------------------*/
  2091. if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
  2092. {
  2093. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
  2094. /* Clear BERR flag */
  2095. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
  2096. }
  2097. /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
  2098. if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
  2099. {
  2100. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
  2101. /* Clear OVR flag */
  2102. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
  2103. }
  2104. /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
  2105. if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
  2106. {
  2107. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
  2108. /* Clear ARLO flag */
  2109. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
  2110. }
  2111. /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
  2112. if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
  2113. {
  2114. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
  2115. /* Clear TIMEOUT flag */
  2116. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
  2117. }
  2118. /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
  2119. if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
  2120. {
  2121. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
  2122. /* Clear ALERT flag */
  2123. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
  2124. }
  2125. /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
  2126. if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
  2127. {
  2128. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
  2129. /* Clear PEC error flag */
  2130. __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
  2131. }
  2132. /* Store current volatile hsmbus->State, misra rule */
  2133. tmperror = hsmbus->ErrorCode;
  2134. /* Call the Error Callback in case of Error detected */
  2135. if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
  2136. {
  2137. /* Do not Reset the HAL state in case of ALERT error */
  2138. if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
  2139. {
  2140. /* Store current volatile hsmbus->State, misra rule */
  2141. tmpstate = hsmbus->State;
  2142. if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
  2143. || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
  2144. {
  2145. /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
  2146. /* keep HAL_SMBUS_STATE_LISTEN if set */
  2147. hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
  2148. hsmbus->State = HAL_SMBUS_STATE_LISTEN;
  2149. }
  2150. }
  2151. /* Call the Error callback to inform upper layer */
  2152. #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
  2153. hsmbus->ErrorCallback(hsmbus);
  2154. #else
  2155. HAL_SMBUS_ErrorCallback(hsmbus);
  2156. #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
  2157. }
  2158. }
  2159. /**
  2160. * @brief Handle SMBUS Communication Timeout.
  2161. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
  2162. * the configuration information for the specified SMBUS.
  2163. * @param Flag Specifies the SMBUS flag to check.
  2164. * @param Status The new Flag status (SET or RESET).
  2165. * @param Timeout Timeout duration
  2166. * @retval HAL status
  2167. */
  2168. static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
  2169. {
  2170. uint32_t tickstart = HAL_GetTick();
  2171. /* Wait until flag is set */
  2172. while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
  2173. {
  2174. /* Check for the Timeout */
  2175. if (Timeout != HAL_MAX_DELAY)
  2176. {
  2177. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
  2178. {
  2179. hsmbus->PreviousState = hsmbus->State;
  2180. hsmbus->State = HAL_SMBUS_STATE_READY;
  2181. /* Update SMBUS error code */
  2182. hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
  2183. /* Process Unlocked */
  2184. __HAL_UNLOCK(hsmbus);
  2185. return HAL_ERROR;
  2186. }
  2187. }
  2188. }
  2189. return HAL_OK;
  2190. }
  2191. /**
  2192. * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
  2193. * @param hsmbus SMBUS handle.
  2194. * @param DevAddress specifies the slave address to be programmed.
  2195. * @param Size specifies the number of bytes to be programmed.
  2196. * This parameter must be a value between 0 and 255.
  2197. * @param Mode New state of the SMBUS START condition generation.
  2198. * This parameter can be one or a combination of the following values:
  2199. * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
  2200. * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
  2201. * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
  2202. * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
  2203. * @param Request New state of the SMBUS START condition generation.
  2204. * This parameter can be one of the following values:
  2205. * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
  2206. * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
  2207. * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
  2208. * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
  2209. * @retval None
  2210. */
  2211. static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
  2212. {
  2213. /* Check the parameters */
  2214. assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
  2215. assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
  2216. assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
  2217. /* update CR2 register */
  2218. MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
  2219. (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
  2220. }
  2221. /**
  2222. * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
  2223. * @param hsmbus SMBUS handle.
  2224. * @retval None
  2225. */
  2226. static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus)
  2227. {
  2228. /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
  2229. /* it request implicitly to generate a restart condition */
  2230. /* set XferOptions to SMBUS_FIRST_FRAME */
  2231. if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
  2232. {
  2233. hsmbus->XferOptions = SMBUS_FIRST_FRAME;
  2234. }
  2235. /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
  2236. /* it request implicitly to generate a restart condition */
  2237. /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
  2238. else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
  2239. {
  2240. hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
  2241. }
  2242. /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
  2243. /* it request implicitly to generate a restart condition */
  2244. /* then generate a stop condition at the end of transfer */
  2245. /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
  2246. else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
  2247. {
  2248. hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
  2249. }
  2250. /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
  2251. /* it request implicitly to generate a restart condition */
  2252. /* then generate a stop condition at the end of transfer */
  2253. /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
  2254. else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
  2255. {
  2256. hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
  2257. }
  2258. else
  2259. {
  2260. /* Nothing to do */
  2261. }
  2262. }
  2263. /**
  2264. * @}
  2265. */
  2266. #endif /* HAL_SMBUS_MODULE_ENABLED */
  2267. /**
  2268. * @}
  2269. */
  2270. /**
  2271. * @}
  2272. */
  2273. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/