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  1. /**
  2. ******************************************************************************
  3. * @file stm32l0xx_ll_adc.c
  4. * @author MCD Application Team
  5. * @brief ADC LL module driver
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. #if defined(USE_FULL_LL_DRIVER)
  20. /* Includes ------------------------------------------------------------------*/
  21. #include "stm32l0xx_ll_adc.h"
  22. #include "stm32l0xx_ll_bus.h"
  23. #ifdef USE_FULL_ASSERT
  24. #include "stm32_assert.h"
  25. #else
  26. #define assert_param(expr) ((void)0U)
  27. #endif
  28. /** @addtogroup STM32L0xx_LL_Driver
  29. * @{
  30. */
  31. #if defined (ADC1)
  32. /** @addtogroup ADC_LL ADC
  33. * @{
  34. */
  35. /* Private types -------------------------------------------------------------*/
  36. /* Private variables ---------------------------------------------------------*/
  37. /* Private constants ---------------------------------------------------------*/
  38. /** @addtogroup ADC_LL_Private_Constants
  39. * @{
  40. */
  41. /* Definitions of ADC hardware constraints delays */
  42. /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
  43. /* not timeout values: */
  44. /* Timeout values for ADC operations are dependent to device clock */
  45. /* configuration (system clock versus ADC clock), */
  46. /* and therefore must be defined in user application. */
  47. /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
  48. /* values definition. */
  49. /* Note: ADC timeout values are defined here in CPU cycles to be independent */
  50. /* of device clock setting. */
  51. /* In user application, ADC timeout values should be defined with */
  52. /* temporal values, in function of device clock settings. */
  53. /* Highest ratio CPU clock frequency vs ADC clock frequency: */
  54. /* - ADC clock from synchronous clock with AHB prescaler 512, */
  55. /* APB prescaler 16, ADC prescaler 4. */
  56. /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
  57. /* with highest ratio CPU clock frequency vs HSI clock frequency: */
  58. /* CPU clock frequency max 32MHz, HSI frequency 16MHz: ratio 2. */
  59. /* Unit: CPU cycles. */
  60. #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
  61. #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
  62. #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
  63. /**
  64. * @}
  65. */
  66. /* Private macros ------------------------------------------------------------*/
  67. /** @addtogroup ADC_LL_Private_Macros
  68. * @{
  69. */
  70. /* Check of parameters for configuration of ADC hierarchical scope: */
  71. /* common to several ADC instances. */
  72. #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
  73. ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
  74. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
  75. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
  76. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
  77. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
  78. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
  79. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
  80. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
  81. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
  82. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
  83. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
  84. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
  85. )
  86. #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
  87. ( ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
  88. || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
  89. )
  90. /* Check of parameters for configuration of ADC hierarchical scope: */
  91. /* ADC instance. */
  92. #define IS_LL_ADC_CLOCK(__CLOCK__) \
  93. ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
  94. || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
  95. || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
  96. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
  97. )
  98. #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
  99. ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
  100. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
  101. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
  102. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
  103. )
  104. #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
  105. ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
  106. || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
  107. )
  108. #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
  109. ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
  110. || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
  111. || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
  112. || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
  113. )
  114. /* Check of parameters for configuration of ADC hierarchical scope: */
  115. /* ADC group regular */
  116. /* ADC group regular external trigger TIM2_CC3 available only on */
  117. /* STM32L0 devices categories: Cat.1, Cat.2, Cat.5 */
  118. #if defined (STM32L011xx) || defined (STM32L021xx) || \
  119. defined (STM32L031xx) || defined (STM32L041xx) || \
  120. defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
  121. defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
  122. #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
  123. ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
  124. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
  125. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM21_CH2) \
  126. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
  127. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
  128. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM22_TRGO) \
  129. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
  130. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
  131. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
  132. )
  133. #else
  134. #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
  135. ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
  136. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
  137. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM21_CH2) \
  138. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
  139. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
  140. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM22_TRGO) \
  141. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
  142. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
  143. )
  144. #endif
  145. #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
  146. ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
  147. || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
  148. )
  149. #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
  150. ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
  151. || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
  152. || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
  153. )
  154. #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
  155. ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
  156. || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
  157. )
  158. #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
  159. ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
  160. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
  161. )
  162. /**
  163. * @}
  164. */
  165. /* Private function prototypes -----------------------------------------------*/
  166. /* Exported functions --------------------------------------------------------*/
  167. /** @addtogroup ADC_LL_Exported_Functions
  168. * @{
  169. */
  170. /** @addtogroup ADC_LL_EF_Init
  171. * @{
  172. */
  173. /**
  174. * @brief De-initialize registers of all ADC instances belonging to
  175. * the same ADC common instance to their default reset values.
  176. * @note This function is performing a hard reset, using high level
  177. * clock source RCC ADC reset.
  178. * @param ADCxy_COMMON ADC common instance
  179. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  180. * @retval An ErrorStatus enumeration value:
  181. * - SUCCESS: ADC common registers are de-initialized
  182. * - ERROR: not applicable
  183. */
  184. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
  185. {
  186. /* Check the parameters */
  187. assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
  188. /* Force reset of ADC clock (core clock) */
  189. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
  190. /* Release reset of ADC clock (core clock) */
  191. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
  192. return SUCCESS;
  193. }
  194. /**
  195. * @brief Initialize some features of ADC common parameters
  196. * (all ADC instances belonging to the same ADC common instance)
  197. * and multimode (for devices with several ADC instances available).
  198. * @note The setting of ADC common parameters is conditioned to
  199. * ADC instances state:
  200. * All ADC instances belonging to the same ADC common instance
  201. * must be disabled.
  202. * @param ADCxy_COMMON ADC common instance
  203. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  204. * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
  205. * @retval An ErrorStatus enumeration value:
  206. * - SUCCESS: ADC common registers are initialized
  207. * - ERROR: ADC common registers are not initialized
  208. */
  209. ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
  210. {
  211. ErrorStatus status = SUCCESS;
  212. /* Check the parameters */
  213. assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
  214. assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
  215. /* Note: Hardware constraint (refer to description of functions */
  216. /* "LL_ADC_SetCommonXXX()": */
  217. /* On this STM32 serie, setting of these features is conditioned to */
  218. /* ADC state: */
  219. /* All ADC instances of the ADC common group must be disabled. */
  220. if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
  221. {
  222. /* Configuration of ADC hierarchical scope: */
  223. /* - common to several ADC */
  224. /* (all ADC instances belonging to the same ADC common instance) */
  225. /* - Set ADC clock (conversion clock) */
  226. LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
  227. }
  228. else
  229. {
  230. /* Initialization error: One or several ADC instances belonging to */
  231. /* the same ADC common instance are not disabled. */
  232. status = ERROR;
  233. }
  234. return status;
  235. }
  236. /**
  237. * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
  238. * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
  239. * whose fields will be set to default values.
  240. * @retval None
  241. */
  242. void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
  243. {
  244. /* Set ADC_CommonInitStruct fields to default values */
  245. /* Set fields of ADC common */
  246. /* (all ADC instances belonging to the same ADC common instance) */
  247. ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
  248. }
  249. /**
  250. * @brief De-initialize registers of the selected ADC instance
  251. * to their default reset values.
  252. * @note To reset all ADC instances quickly (perform a hard reset),
  253. * use function @ref LL_ADC_CommonDeInit().
  254. * @note If this functions returns error status, it means that ADC instance
  255. * is in an unknown state.
  256. * In this case, perform a hard reset using high level
  257. * clock source RCC ADC reset.
  258. * Refer to function @ref LL_ADC_CommonDeInit().
  259. * @param ADCx ADC instance
  260. * @retval An ErrorStatus enumeration value:
  261. * - SUCCESS: ADC registers are de-initialized
  262. * - ERROR: ADC registers are not de-initialized
  263. */
  264. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
  265. {
  266. ErrorStatus status = SUCCESS;
  267. __IO uint32_t timeout_cpu_cycles = 0U;
  268. /* Check the parameters */
  269. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  270. /* Disable ADC instance if not already disabled. */
  271. if(LL_ADC_IsEnabled(ADCx) == 1U)
  272. {
  273. /* Set ADC group regular trigger source to SW start to ensure to not */
  274. /* have an external trigger event occurring during the conversion stop */
  275. /* ADC disable process. */
  276. LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
  277. /* Stop potential ADC conversion on going on ADC group regular. */
  278. if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
  279. {
  280. if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
  281. {
  282. LL_ADC_REG_StopConversion(ADCx);
  283. }
  284. }
  285. /* Wait for ADC conversions are effectively stopped */
  286. timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
  287. while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
  288. {
  289. if(timeout_cpu_cycles-- == 0U)
  290. {
  291. /* Time-out error */
  292. status = ERROR;
  293. }
  294. }
  295. /* Disable the ADC instance */
  296. LL_ADC_Disable(ADCx);
  297. /* Wait for ADC instance is effectively disabled */
  298. timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
  299. while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
  300. {
  301. if(timeout_cpu_cycles-- == 0U)
  302. {
  303. /* Time-out error */
  304. status = ERROR;
  305. }
  306. }
  307. }
  308. /* Check whether ADC state is compliant with expected state */
  309. if(READ_BIT(ADCx->CR,
  310. ( ADC_CR_ADSTP | ADC_CR_ADSTART
  311. | ADC_CR_ADDIS | ADC_CR_ADEN )
  312. )
  313. == 0U)
  314. {
  315. /* ========== Reset ADC registers ========== */
  316. /* Reset register IER */
  317. CLEAR_BIT(ADCx->IER,
  318. ( LL_ADC_IT_ADRDY
  319. | LL_ADC_IT_EOC
  320. | LL_ADC_IT_EOS
  321. | LL_ADC_IT_OVR
  322. | LL_ADC_IT_EOSMP
  323. | LL_ADC_IT_AWD1 )
  324. );
  325. /* Reset register ISR */
  326. SET_BIT(ADCx->ISR,
  327. ( LL_ADC_FLAG_ADRDY
  328. | LL_ADC_FLAG_EOC
  329. | LL_ADC_FLAG_EOS
  330. | LL_ADC_FLAG_OVR
  331. | LL_ADC_FLAG_EOSMP
  332. | LL_ADC_FLAG_AWD1 )
  333. );
  334. /* Reset register CR */
  335. /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
  336. /* "read-set": no direct reset applicable. */
  337. CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
  338. /* Reset register CFGR1 */
  339. CLEAR_BIT(ADCx->CFGR1,
  340. ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN
  341. | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
  342. | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
  343. | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
  344. );
  345. /* Reset register CFGR2 */
  346. /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
  347. /* already done above. */
  348. CLEAR_BIT(ADCx->CFGR2,
  349. ( ADC_CFGR2_CKMODE
  350. | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
  351. | ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE )
  352. );
  353. /* Reset register SMPR */
  354. CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
  355. /* Reset register TR */
  356. MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
  357. /* Reset register CHSELR */
  358. #if defined(ADC_CCR_VLCDEN)
  359. CLEAR_BIT(ADCx->CHSELR,
  360. ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
  361. | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
  362. | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
  363. | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
  364. | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
  365. );
  366. #else
  367. CLEAR_BIT(ADCx->CHSELR,
  368. ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17
  369. | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
  370. | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
  371. | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
  372. | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
  373. );
  374. #endif
  375. /* Reset register DR */
  376. /* bits in access mode read only, no direct reset applicable */
  377. /* Reset register CALFACT */
  378. CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
  379. }
  380. else
  381. {
  382. /* ADC instance is in an unknown state */
  383. /* Need to performing a hard reset of ADC instance, using high level */
  384. /* clock source RCC ADC reset. */
  385. /* Caution: On this STM32 serie, if several ADC instances are available */
  386. /* on the selected device, RCC ADC reset will reset */
  387. /* all ADC instances belonging to the common ADC instance. */
  388. status = ERROR;
  389. }
  390. return status;
  391. }
  392. /**
  393. * @brief Initialize some features of ADC instance.
  394. * @note These parameters have an impact on ADC scope: ADC instance.
  395. * Refer to corresponding unitary functions into
  396. * @ref ADC_LL_EF_Configuration_ADC_Instance .
  397. * @note The setting of these parameters by function @ref LL_ADC_Init()
  398. * is conditioned to ADC state:
  399. * ADC instance must be disabled.
  400. * This condition is applied to all ADC features, for efficiency
  401. * and compatibility over all STM32 families. However, the different
  402. * features can be set under different ADC state conditions
  403. * (setting possible with ADC enabled without conversion on going,
  404. * ADC enabled with conversion on going, ...)
  405. * Each feature can be updated afterwards with a unitary function
  406. * and potentially with ADC in a different state than disabled,
  407. * refer to description of each function for setting
  408. * conditioned to ADC state.
  409. * @note After using this function, some other features must be configured
  410. * using LL unitary functions.
  411. * The minimum configuration remaining to be done is:
  412. * - Set ADC group regular sequencer:
  413. * map channel on rank corresponding to channel number.
  414. * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
  415. * - Set ADC channel sampling time
  416. * Refer to function LL_ADC_SetChannelSamplingTime();
  417. * @param ADCx ADC instance
  418. * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  419. * @retval An ErrorStatus enumeration value:
  420. * - SUCCESS: ADC registers are initialized
  421. * - ERROR: ADC registers are not initialized
  422. */
  423. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
  424. {
  425. ErrorStatus status = SUCCESS;
  426. /* Check the parameters */
  427. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  428. assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
  429. assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
  430. assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
  431. assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
  432. /* Note: Hardware constraint (refer to description of this function): */
  433. /* ADC instance must be disabled. */
  434. if(LL_ADC_IsEnabled(ADCx) == 0U)
  435. {
  436. /* Configuration of ADC hierarchical scope: */
  437. /* - ADC instance */
  438. /* - Set ADC data resolution */
  439. /* - Set ADC conversion data alignment */
  440. /* - Set ADC low power mode */
  441. MODIFY_REG(ADCx->CFGR1,
  442. ADC_CFGR1_RES
  443. | ADC_CFGR1_ALIGN
  444. | ADC_CFGR1_WAIT
  445. | ADC_CFGR1_AUTOFF
  446. ,
  447. ADC_InitStruct->Resolution
  448. | ADC_InitStruct->DataAlignment
  449. | ADC_InitStruct->LowPowerMode
  450. );
  451. MODIFY_REG(ADCx->CFGR2,
  452. ADC_CFGR2_CKMODE
  453. ,
  454. ADC_InitStruct->Clock
  455. );
  456. }
  457. else
  458. {
  459. /* Initialization error: ADC instance is not disabled. */
  460. status = ERROR;
  461. }
  462. return status;
  463. }
  464. /**
  465. * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
  466. * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
  467. * whose fields will be set to default values.
  468. * @retval None
  469. */
  470. void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
  471. {
  472. /* Set ADC_InitStruct fields to default values */
  473. /* Set fields of ADC instance */
  474. ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
  475. ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
  476. ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
  477. ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
  478. }
  479. /**
  480. * @brief Initialize some features of ADC group regular.
  481. * @note These parameters have an impact on ADC scope: ADC group regular.
  482. * Refer to corresponding unitary functions into
  483. * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
  484. * (functions with prefix "REG").
  485. * @note The setting of these parameters by function @ref LL_ADC_Init()
  486. * is conditioned to ADC state:
  487. * ADC instance must be disabled.
  488. * This condition is applied to all ADC features, for efficiency
  489. * and compatibility over all STM32 families. However, the different
  490. * features can be set under different ADC state conditions
  491. * (setting possible with ADC enabled without conversion on going,
  492. * ADC enabled with conversion on going, ...)
  493. * Each feature can be updated afterwards with a unitary function
  494. * and potentially with ADC in a different state than disabled,
  495. * refer to description of each function for setting
  496. * conditioned to ADC state.
  497. * @note After using this function, other features must be configured
  498. * using LL unitary functions.
  499. * The minimum configuration remaining to be done is:
  500. * - Set ADC group regular sequencer:
  501. * map channel on rank corresponding to channel number.
  502. * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
  503. * - Set ADC channel sampling time
  504. * Refer to function LL_ADC_SetChannelSamplingTime();
  505. * @param ADCx ADC instance
  506. * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  507. * @retval An ErrorStatus enumeration value:
  508. * - SUCCESS: ADC registers are initialized
  509. * - ERROR: ADC registers are not initialized
  510. */
  511. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
  512. {
  513. ErrorStatus status = SUCCESS;
  514. /* Check the parameters */
  515. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  516. assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
  517. assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
  518. assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
  519. assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
  520. assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
  521. /* Note: Hardware constraint (refer to description of this function): */
  522. /* ADC instance must be disabled. */
  523. if(LL_ADC_IsEnabled(ADCx) == 0U)
  524. {
  525. /* Configuration of ADC hierarchical scope: */
  526. /* - ADC group regular */
  527. /* - Set ADC group regular trigger source */
  528. /* - Set ADC group regular sequencer discontinuous mode */
  529. /* - Set ADC group regular continuous mode */
  530. /* - Set ADC group regular conversion data transfer: no transfer or */
  531. /* transfer by DMA, and DMA requests mode */
  532. /* - Set ADC group regular overrun behavior */
  533. /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
  534. /* setting of trigger source to SW start. */
  535. MODIFY_REG(ADCx->CFGR1,
  536. ADC_CFGR1_EXTSEL
  537. | ADC_CFGR1_EXTEN
  538. | ADC_CFGR1_DISCEN
  539. | ADC_CFGR1_CONT
  540. | ADC_CFGR1_DMAEN
  541. | ADC_CFGR1_DMACFG
  542. | ADC_CFGR1_OVRMOD
  543. ,
  544. ADC_REG_InitStruct->TriggerSource
  545. | ADC_REG_InitStruct->SequencerDiscont
  546. | ADC_REG_InitStruct->ContinuousMode
  547. | ADC_REG_InitStruct->DMATransfer
  548. | ADC_REG_InitStruct->Overrun
  549. );
  550. }
  551. else
  552. {
  553. /* Initialization error: ADC instance is not disabled. */
  554. status = ERROR;
  555. }
  556. return status;
  557. }
  558. /**
  559. * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
  560. * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  561. * whose fields will be set to default values.
  562. * @retval None
  563. */
  564. void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
  565. {
  566. /* Set ADC_REG_InitStruct fields to default values */
  567. /* Set fields of ADC group regular */
  568. /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
  569. /* setting of trigger source to SW start. */
  570. ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
  571. ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
  572. ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
  573. ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
  574. ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
  575. }
  576. /**
  577. * @}
  578. */
  579. /**
  580. * @}
  581. */
  582. /**
  583. * @}
  584. */
  585. #endif /* ADC1 */
  586. /**
  587. * @}
  588. */
  589. #endif /* USE_FULL_LL_DRIVER */
  590. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/