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  1. /**
  2. ******************************************************************************
  3. * @file stm32wbxx_ll_adc.c
  4. * @author MCD Application Team
  5. * @brief ADC LL module driver
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. #if defined(USE_FULL_LL_DRIVER)
  20. /* Includes ------------------------------------------------------------------*/
  21. #include "stm32wbxx_ll_adc.h"
  22. #include "stm32wbxx_ll_bus.h"
  23. #ifdef USE_FULL_ASSERT
  24. #include "stm32_assert.h"
  25. #else
  26. #define assert_param(expr) ((void)0U)
  27. #endif
  28. /** @addtogroup STM32WBxx_LL_Driver
  29. * @{
  30. */
  31. #if defined (ADC1)
  32. /** @addtogroup ADC_LL ADC
  33. * @{
  34. */
  35. /* Private types -------------------------------------------------------------*/
  36. /* Private variables ---------------------------------------------------------*/
  37. /* Private constants ---------------------------------------------------------*/
  38. /** @addtogroup ADC_LL_Private_Constants
  39. * @{
  40. */
  41. /* Definitions of ADC hardware constraints delays */
  42. /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
  43. /* not timeout values: */
  44. /* Timeout values for ADC operations are dependent to device clock */
  45. /* configuration (system clock versus ADC clock), */
  46. /* and therefore must be defined in user application. */
  47. /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
  48. /* values definition. */
  49. /* Note: ADC timeout values are defined here in CPU cycles to be independent */
  50. /* of device clock setting. */
  51. /* In user application, ADC timeout values should be defined with */
  52. /* temporal values, in function of device clock settings. */
  53. /* Highest ratio CPU clock frequency vs ADC clock frequency: */
  54. /* - ADC clock from synchronous clock with AHB prescaler 512, */
  55. /* APB prescaler 16, ADC prescaler 4. */
  56. /* - ADC clock from asynchronous clock (PLLSAI) with prescaler 1, */
  57. /* with highest ratio CPU clock frequency vs HSI clock frequency: */
  58. /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */
  59. /* Unit: CPU cycles. */
  60. #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
  61. #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
  62. #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
  63. #if defined (ADC_SUPPORT_2_5_MSPS)
  64. /* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
  65. /* after the channel configuration has been changed. */
  66. /* Driver timeout is approximated to 6 CPU cycles. */
  67. #define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
  68. #endif
  69. /**
  70. * @}
  71. */
  72. /* Private macros ------------------------------------------------------------*/
  73. /** @addtogroup ADC_LL_Private_Macros
  74. * @{
  75. */
  76. /* Check of parameters for configuration of ADC hierarchical scope: */
  77. /* common to several ADC instances. */
  78. #if defined (ADC_SUPPORT_2_5_MSPS)
  79. #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
  80. ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
  81. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
  82. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
  83. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
  84. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
  85. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
  86. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
  87. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
  88. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
  89. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
  90. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
  91. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
  92. )
  93. #else
  94. #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
  95. ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
  96. || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
  97. || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
  98. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
  99. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
  100. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
  101. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
  102. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
  103. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
  104. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
  105. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
  106. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
  107. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
  108. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
  109. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
  110. )
  111. #endif
  112. /* Check of parameters for configuration of ADC hierarchical scope: */
  113. /* ADC instance. */
  114. #if defined (ADC_SUPPORT_2_5_MSPS)
  115. #define IS_LL_ADC_CLOCK(__CLOCK__) \
  116. ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
  117. || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
  118. || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
  119. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
  120. )
  121. #endif
  122. #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
  123. ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
  124. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
  125. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
  126. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
  127. )
  128. #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
  129. ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
  130. || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
  131. )
  132. #if defined (ADC_SUPPORT_2_5_MSPS)
  133. #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
  134. ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
  135. || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
  136. || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
  137. || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
  138. )
  139. #else
  140. #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
  141. ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
  142. || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
  143. )
  144. #endif
  145. /* Check of parameters for configuration of ADC hierarchical scope: */
  146. /* ADC group regular */
  147. #if defined (ADC_SUPPORT_2_5_MSPS)
  148. #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
  149. ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
  150. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
  151. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
  152. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
  153. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
  154. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
  155. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
  156. )
  157. #else
  158. #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
  159. ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
  160. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
  161. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
  162. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
  163. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
  164. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
  165. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
  166. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
  167. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
  168. )
  169. #endif
  170. #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
  171. ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
  172. || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
  173. )
  174. #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
  175. ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
  176. || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
  177. || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
  178. )
  179. #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
  180. ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
  181. || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
  182. )
  183. #if defined (ADC_SUPPORT_2_5_MSPS)
  184. #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
  185. ( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
  186. || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
  187. )
  188. #endif
  189. #if defined (ADC_SUPPORT_2_5_MSPS)
  190. #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
  191. ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
  192. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
  193. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
  194. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
  195. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
  196. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
  197. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
  198. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
  199. )
  200. #else
  201. #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
  202. ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
  203. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
  204. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
  205. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
  206. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
  207. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
  208. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
  209. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
  210. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
  211. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
  212. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
  213. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
  214. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
  215. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
  216. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
  217. || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
  218. )
  219. #endif
  220. #if defined (ADC_SUPPORT_2_5_MSPS)
  221. #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
  222. ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
  223. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
  224. )
  225. #else
  226. #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
  227. ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
  228. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
  229. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
  230. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
  231. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
  232. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
  233. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
  234. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
  235. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
  236. )
  237. #endif
  238. /* Check of parameters for configuration of ADC hierarchical scope: */
  239. /* ADC group injected */
  240. #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
  241. ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
  242. || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
  243. || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
  244. || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
  245. || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
  246. || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
  247. || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
  248. )
  249. #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
  250. ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
  251. || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
  252. || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
  253. )
  254. #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
  255. ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
  256. || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
  257. )
  258. #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
  259. ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
  260. || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
  261. || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
  262. || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
  263. )
  264. #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
  265. ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
  266. || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
  267. )
  268. /**
  269. * @}
  270. */
  271. /* Private function prototypes -----------------------------------------------*/
  272. /* Exported functions --------------------------------------------------------*/
  273. /** @addtogroup ADC_LL_Exported_Functions
  274. * @{
  275. */
  276. /** @addtogroup ADC_LL_EF_Init
  277. * @{
  278. */
  279. /**
  280. * @brief De-initialize registers of all ADC instances belonging to
  281. * the same ADC common instance to their default reset values.
  282. * @note This function is performing a hard reset, using high level
  283. * clock source RCC ADC reset.
  284. * @param ADCxy_COMMON ADC common instance
  285. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  286. * @retval An ErrorStatus enumeration value:
  287. * - SUCCESS: ADC common registers are de-initialized
  288. * - ERROR: not applicable
  289. */
  290. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
  291. {
  292. /* Check the parameters */
  293. assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
  294. #if defined (ADC_SUPPORT_2_5_MSPS)
  295. /* Force reset of ADC clock (core clock) */
  296. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
  297. /* Release reset of ADC clock (core clock) */
  298. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
  299. #else
  300. /* Force reset of ADC clock (core clock) */
  301. LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
  302. /* Release reset of ADC clock (core clock) */
  303. LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
  304. #endif /* ADC_SUPPORT_2_5_MSPS */
  305. return SUCCESS;
  306. }
  307. /**
  308. * @brief Initialize some features of ADC common parameters
  309. * (all ADC instances belonging to the same ADC common instance)
  310. * and multimode (for devices with several ADC instances available).
  311. * @note The setting of ADC common parameters is conditioned to
  312. * ADC instances state:
  313. * All ADC instances belonging to the same ADC common instance
  314. * must be disabled.
  315. * @param ADCxy_COMMON ADC common instance
  316. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  317. * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
  318. * @retval An ErrorStatus enumeration value:
  319. * - SUCCESS: ADC common registers are initialized
  320. * - ERROR: ADC common registers are not initialized
  321. */
  322. ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
  323. {
  324. ErrorStatus status = SUCCESS;
  325. /* Check the parameters */
  326. assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
  327. assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
  328. /* Note: Hardware constraint (refer to description of functions */
  329. /* "LL_ADC_SetCommonXXX()": */
  330. /* On this STM32 serie, setting of these features is conditioned to */
  331. /* ADC state: */
  332. /* All ADC instances of the ADC common group must be disabled. */
  333. if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
  334. {
  335. /* Configuration of ADC hierarchical scope: */
  336. /* - common to several ADC */
  337. /* (all ADC instances belonging to the same ADC common instance) */
  338. /* - Set ADC clock (conversion clock) */
  339. #if defined(ADC_MULTIMODE_SUPPORT)
  340. if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
  341. {
  342. MODIFY_REG(ADCxy_COMMON->CCR,
  343. ADC_CCR_CKMODE
  344. | ADC_CCR_PRESC
  345. | ADC_CCR_DUAL
  346. | ADC_CCR_MDMA
  347. | ADC_CCR_DELAY
  348. ,
  349. ADC_CommonInitStruct->CommonClock
  350. | ADC_CommonInitStruct->Multimode
  351. | ADC_CommonInitStruct->MultiDMATransfer
  352. | ADC_CommonInitStruct->MultiTwoSamplingDelay
  353. );
  354. }
  355. else
  356. {
  357. MODIFY_REG(ADCxy_COMMON->CCR,
  358. ADC_CCR_CKMODE
  359. | ADC_CCR_PRESC
  360. | ADC_CCR_DUAL
  361. | ADC_CCR_MDMA
  362. | ADC_CCR_DELAY
  363. ,
  364. ADC_CommonInitStruct->CommonClock
  365. | LL_ADC_MULTI_INDEPENDENT
  366. );
  367. }
  368. #else
  369. LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
  370. #endif
  371. }
  372. else
  373. {
  374. /* Initialization error: One or several ADC instances belonging to */
  375. /* the same ADC common instance are not disabled. */
  376. status = ERROR;
  377. }
  378. return status;
  379. }
  380. /**
  381. * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
  382. * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
  383. * whose fields will be set to default values.
  384. * @retval None
  385. */
  386. void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
  387. {
  388. /* Set ADC_CommonInitStruct fields to default values */
  389. /* Set fields of ADC common */
  390. /* (all ADC instances belonging to the same ADC common instance) */
  391. #if defined (ADC_SUPPORT_2_5_MSPS)
  392. ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
  393. #else
  394. ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
  395. #endif /* ADC_SUPPORT_2_5_MSPS */
  396. }
  397. /**
  398. * @brief De-initialize registers of the selected ADC instance
  399. * to their default reset values.
  400. * @note To reset all ADC instances quickly (perform a hard reset),
  401. * use function @ref LL_ADC_CommonDeInit().
  402. * @note If this functions returns error status, it means that ADC instance
  403. * is in an unknown state.
  404. * In this case, perform a hard reset using high level
  405. * clock source RCC ADC reset.
  406. * Refer to function @ref LL_ADC_CommonDeInit().
  407. * @param ADCx ADC instance
  408. * @retval An ErrorStatus enumeration value:
  409. * - SUCCESS: ADC registers are de-initialized
  410. * - ERROR: ADC registers are not de-initialized
  411. */
  412. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
  413. {
  414. ErrorStatus status = SUCCESS;
  415. __IO uint32_t timeout_cpu_cycles = 0UL;
  416. /* Check the parameters */
  417. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  418. /* Disable ADC instance if not already disabled. */
  419. if (LL_ADC_IsEnabled(ADCx) == 1UL)
  420. {
  421. /* Set ADC group regular trigger source to SW start to ensure to not */
  422. /* have an external trigger event occurring during the conversion stop */
  423. /* ADC disable process. */
  424. LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
  425. /* Stop potential ADC conversion on going on ADC group regular. */
  426. if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
  427. {
  428. if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
  429. {
  430. LL_ADC_REG_StopConversion(ADCx);
  431. }
  432. }
  433. #if !defined (ADC_SUPPORT_2_5_MSPS)
  434. /* Set ADC group injected trigger source to SW start to ensure to not */
  435. /* have an external trigger event occurring during the conversion stop */
  436. /* ADC disable process. */
  437. LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
  438. /* Stop potential ADC conversion on going on ADC group injected. */
  439. if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
  440. {
  441. if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
  442. {
  443. LL_ADC_INJ_StopConversion(ADCx);
  444. }
  445. }
  446. /* Wait for ADC conversions are effectively stopped */
  447. timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
  448. while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
  449. | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
  450. {
  451. timeout_cpu_cycles--;
  452. if (timeout_cpu_cycles == 0UL)
  453. {
  454. /* Time-out error */
  455. status = ERROR;
  456. break;
  457. }
  458. }
  459. #else
  460. /* Wait for ADC conversions are effectively stopped */
  461. timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
  462. while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
  463. {
  464. timeout_cpu_cycles--;
  465. if(timeout_cpu_cycles == 0UL)
  466. {
  467. /* Time-out error */
  468. status = ERROR;
  469. break;
  470. }
  471. }
  472. #endif /* ADC_SUPPORT_2_5_MSPS */
  473. #if !defined (ADC_SUPPORT_2_5_MSPS)
  474. /* Flush group injected contexts queue (register JSQR): */
  475. /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
  476. /* contexts queue is maintained with the last active context). */
  477. LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
  478. #endif
  479. /* Disable the ADC instance */
  480. LL_ADC_Disable(ADCx);
  481. /* Wait for ADC instance is effectively disabled */
  482. timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
  483. while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
  484. {
  485. timeout_cpu_cycles--;
  486. if (timeout_cpu_cycles == 0UL)
  487. {
  488. /* Time-out error */
  489. status = ERROR;
  490. break;
  491. }
  492. }
  493. }
  494. /* Check whether ADC state is compliant with expected state */
  495. #if defined (ADC_SUPPORT_2_5_MSPS)
  496. if (READ_BIT(ADCx->CR,
  497. (ADC_CR_ADSTP | ADC_CR_ADSTART
  498. | ADC_CR_ADDIS | ADC_CR_ADEN )
  499. )
  500. == 0UL)
  501. #else
  502. if (READ_BIT(ADCx->CR,
  503. (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
  504. | ADC_CR_ADDIS | ADC_CR_ADEN)
  505. )
  506. == 0UL)
  507. #endif
  508. {
  509. /* ========== Reset ADC registers ========== */
  510. /* Reset register IER */
  511. CLEAR_BIT(ADCx->IER,
  512. (LL_ADC_IT_ADRDY
  513. | LL_ADC_IT_EOC
  514. | LL_ADC_IT_EOS
  515. | LL_ADC_IT_OVR
  516. | LL_ADC_IT_EOSMP
  517. #if !defined (ADC_SUPPORT_2_5_MSPS)
  518. | LL_ADC_IT_JEOC
  519. | LL_ADC_IT_JEOS
  520. | LL_ADC_IT_JQOVF
  521. #endif
  522. | LL_ADC_IT_AWD1
  523. | LL_ADC_IT_AWD2
  524. | LL_ADC_IT_AWD3
  525. #if defined (ADC_SUPPORT_2_5_MSPS)
  526. | LL_ADC_IT_CCRDY
  527. #endif
  528. )
  529. );
  530. /* Reset register ISR */
  531. SET_BIT(ADCx->ISR,
  532. (LL_ADC_FLAG_ADRDY
  533. | LL_ADC_FLAG_EOC
  534. | LL_ADC_FLAG_EOS
  535. | LL_ADC_FLAG_OVR
  536. | LL_ADC_FLAG_EOSMP
  537. #if !defined (ADC_SUPPORT_2_5_MSPS)
  538. | LL_ADC_FLAG_JEOC
  539. | LL_ADC_FLAG_JEOS
  540. | LL_ADC_FLAG_JQOVF
  541. #endif
  542. | LL_ADC_FLAG_AWD1
  543. | LL_ADC_FLAG_AWD2
  544. | LL_ADC_FLAG_AWD3
  545. #if defined (ADC_SUPPORT_2_5_MSPS)
  546. | LL_ADC_FLAG_CCRDY
  547. #endif
  548. )
  549. );
  550. #if defined (ADC_SUPPORT_2_5_MSPS)
  551. /* Reset register CR */
  552. /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
  553. /* "read-set": no direct reset applicable. */
  554. CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
  555. #else
  556. /* Reset register CR */
  557. /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
  558. /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
  559. /* access mode "read-set": no direct reset applicable. */
  560. /* - Reset Calibration mode to default setting (single ended). */
  561. /* - Disable ADC internal voltage regulator. */
  562. /* - Enable ADC deep power down. */
  563. /* Note: ADC internal voltage regulator disable and ADC deep power */
  564. /* down enable are conditioned to ADC state disabled: */
  565. /* already done above. */
  566. CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
  567. SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
  568. #endif
  569. #if defined (ADC_SUPPORT_2_5_MSPS)
  570. /* Reset register CFGR1 */
  571. CLEAR_BIT(ADCx->CFGR1,
  572. ( ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
  573. | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
  574. | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
  575. | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
  576. );
  577. /* Reset register SMPR */
  578. CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
  579. /* Reset register TR1 */
  580. MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
  581. /* Reset register CHSELR */
  582. CLEAR_BIT(ADCx->CHSELR,
  583. ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
  584. | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
  585. | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
  586. | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
  587. | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
  588. );
  589. /* Wait for ADC channel configuration ready */
  590. timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
  591. while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
  592. {
  593. timeout_cpu_cycles--;
  594. if(timeout_cpu_cycles == 0UL)
  595. {
  596. /* Time-out error */
  597. status = ERROR;
  598. break;
  599. }
  600. }
  601. /* Clear flag ADC channel configuration ready */
  602. LL_ADC_ClearFlag_CCRDY(ADCx);
  603. /* Reset register DR */
  604. /* bits in access mode read only, no direct reset applicable */
  605. /* Reset register CALFACT */
  606. CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
  607. /* Reset register CFGR2 */
  608. /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
  609. /* already done above. */
  610. /* Note: Register reset last due to selection of asynchronous clock, */
  611. /* ADC clock then depends of configuration clock source at system */
  612. /* level. */
  613. CLEAR_BIT(ADCx->CFGR2,
  614. ( ADC_CFGR2_CKMODE
  615. | ADC_CFGR2_LFTRIG )
  616. );
  617. #else
  618. /* Reset register CFGR */
  619. MODIFY_REG(ADCx->CFGR,
  620. (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
  621. | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
  622. | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
  623. | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
  624. | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
  625. | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
  626. ADC_CFGR_JQDIS
  627. );
  628. /* Reset register CFGR2 */
  629. CLEAR_BIT(ADCx->CFGR2,
  630. (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
  631. | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
  632. );
  633. /* Reset register SMPR1 */
  634. CLEAR_BIT(ADCx->SMPR1,
  635. (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
  636. | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
  637. | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
  638. );
  639. /* Reset register SMPR2 */
  640. CLEAR_BIT(ADCx->SMPR2,
  641. (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
  642. | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
  643. | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
  644. );
  645. /* Reset register TR1 */
  646. MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
  647. /* Reset register TR2 */
  648. MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
  649. /* Reset register TR3 */
  650. MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
  651. /* Reset register SQR1 */
  652. CLEAR_BIT(ADCx->SQR1,
  653. (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
  654. | ADC_SQR1_SQ1 | ADC_SQR1_L)
  655. );
  656. /* Reset register SQR2 */
  657. CLEAR_BIT(ADCx->SQR2,
  658. (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
  659. | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
  660. );
  661. /* Reset register SQR3 */
  662. CLEAR_BIT(ADCx->SQR3,
  663. (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
  664. | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
  665. );
  666. /* Reset register SQR4 */
  667. CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
  668. /* Reset register JSQR */
  669. CLEAR_BIT(ADCx->JSQR,
  670. (ADC_JSQR_JL
  671. | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
  672. | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
  673. | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
  674. );
  675. /* Reset register DR */
  676. /* Note: bits in access mode read only, no direct reset applicable */
  677. /* Reset register OFR1 */
  678. CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
  679. /* Reset register OFR2 */
  680. CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
  681. /* Reset register OFR3 */
  682. CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
  683. /* Reset register OFR4 */
  684. CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
  685. /* Reset registers JDR1, JDR2, JDR3, JDR4 */
  686. /* Note: bits in access mode read only, no direct reset applicable */
  687. /* Reset register AWD2CR */
  688. CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
  689. /* Reset register AWD3CR */
  690. CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
  691. /* Reset register DIFSEL */
  692. CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
  693. /* Reset register CALFACT */
  694. CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
  695. #endif
  696. }
  697. else
  698. {
  699. /* ADC instance is in an unknown state */
  700. /* Need to performing a hard reset of ADC instance, using high level */
  701. /* clock source RCC ADC reset. */
  702. /* Caution: On this STM32 serie, if several ADC instances are available */
  703. /* on the selected device, RCC ADC reset will reset */
  704. /* all ADC instances belonging to the common ADC instance. */
  705. status = ERROR;
  706. }
  707. return status;
  708. }
  709. /**
  710. * @brief Initialize some features of ADC instance.
  711. * @note These parameters have an impact on ADC scope: ADC instance.
  712. * Affects both group regular and group injected (availability
  713. * of ADC group injected depends on STM32 families).
  714. * Refer to corresponding unitary functions into
  715. * @ref ADC_LL_EF_Configuration_ADC_Instance .
  716. * @note The setting of these parameters by function @ref LL_ADC_Init()
  717. * is conditioned to ADC state:
  718. * ADC instance must be disabled.
  719. * This condition is applied to all ADC features, for efficiency
  720. * and compatibility over all STM32 families. However, the different
  721. * features can be set under different ADC state conditions
  722. * (setting possible with ADC enabled without conversion on going,
  723. * ADC enabled with conversion on going, ...)
  724. * Each feature can be updated afterwards with a unitary function
  725. * and potentially with ADC in a different state than disabled,
  726. * refer to description of each function for setting
  727. * conditioned to ADC state.
  728. * @note After using this function, some other features must be configured
  729. * using LL unitary functions.
  730. * The minimum configuration remaining to be done is:
  731. * - Set ADC group regular or group injected sequencer:
  732. * map channel on the selected sequencer rank.
  733. * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
  734. * - Set ADC channel sampling time
  735. * Refer to function LL_ADC_SetChannelSamplingTime();
  736. * @param ADCx ADC instance
  737. * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  738. * @retval An ErrorStatus enumeration value:
  739. * - SUCCESS: ADC registers are initialized
  740. * - ERROR: ADC registers are not initialized
  741. */
  742. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
  743. {
  744. ErrorStatus status = SUCCESS;
  745. /* Check the parameters */
  746. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  747. #if defined (ADC_SUPPORT_2_5_MSPS)
  748. assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
  749. #endif
  750. assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
  751. assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
  752. assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
  753. /* Note: Hardware constraint (refer to description of this function): */
  754. /* ADC instance must be disabled. */
  755. if (LL_ADC_IsEnabled(ADCx) == 0UL)
  756. {
  757. /* Configuration of ADC hierarchical scope: */
  758. /* - ADC instance */
  759. /* - Set ADC data resolution */
  760. /* - Set ADC conversion data alignment */
  761. /* - Set ADC low power mode */
  762. #if defined (ADC_SUPPORT_2_5_MSPS)
  763. MODIFY_REG(ADCx->CFGR1,
  764. ADC_CFGR1_RES
  765. | ADC_CFGR1_ALIGN
  766. | ADC_CFGR1_WAIT
  767. | ADC_CFGR1_AUTOFF
  768. ,
  769. ADC_InitStruct->Resolution
  770. | ADC_InitStruct->DataAlignment
  771. | ADC_InitStruct->LowPowerMode
  772. );
  773. MODIFY_REG(ADCx->CFGR2,
  774. ADC_CFGR2_CKMODE
  775. ,
  776. ADC_InitStruct->Clock
  777. );
  778. #else
  779. MODIFY_REG(ADCx->CFGR,
  780. ADC_CFGR_RES
  781. | ADC_CFGR_ALIGN
  782. | ADC_CFGR_AUTDLY
  783. ,
  784. ADC_InitStruct->Resolution
  785. | ADC_InitStruct->DataAlignment
  786. | ADC_InitStruct->LowPowerMode
  787. );
  788. #endif
  789. }
  790. else
  791. {
  792. /* Initialization error: ADC instance is not disabled. */
  793. status = ERROR;
  794. }
  795. return status;
  796. }
  797. /**
  798. * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
  799. * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
  800. * whose fields will be set to default values.
  801. * @retval None
  802. */
  803. void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
  804. {
  805. /* Set ADC_InitStruct fields to default values */
  806. /* Set fields of ADC instance */
  807. #if defined (ADC_SUPPORT_2_5_MSPS)
  808. ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
  809. #endif
  810. ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
  811. ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
  812. ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
  813. }
  814. /**
  815. * @brief Initialize some features of ADC group regular.
  816. * @note These parameters have an impact on ADC scope: ADC group regular.
  817. * Refer to corresponding unitary functions into
  818. * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
  819. * (functions with prefix "REG").
  820. * @note The setting of these parameters by function @ref LL_ADC_Init()
  821. * is conditioned to ADC state:
  822. * ADC instance must be disabled.
  823. * This condition is applied to all ADC features, for efficiency
  824. * and compatibility over all STM32 families. However, the different
  825. * features can be set under different ADC state conditions
  826. * (setting possible with ADC enabled without conversion on going,
  827. * ADC enabled with conversion on going, ...)
  828. * Each feature can be updated afterwards with a unitary function
  829. * and potentially with ADC in a different state than disabled,
  830. * refer to description of each function for setting
  831. * conditioned to ADC state.
  832. * @note On devices STM32WB10xx, STM32WB15xx: Before using this function,
  833. * ADC group regular sequencer must be configured: refer to function
  834. * @ref LL_ADC_REG_SetSequencerConfigurable().
  835. * @note After using this function, other features must be configured
  836. * using LL unitary functions.
  837. * The minimum configuration remaining to be done is:
  838. * - Set ADC group regular or group injected sequencer:
  839. * map channel on the selected sequencer rank.
  840. * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
  841. * - Set ADC channel sampling time
  842. * Refer to function LL_ADC_SetChannelSamplingTime();
  843. * @param ADCx ADC instance
  844. * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  845. * @retval An ErrorStatus enumeration value:
  846. * - SUCCESS: ADC registers are initialized
  847. * - ERROR: ADC registers are not initialized
  848. */
  849. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
  850. {
  851. ErrorStatus status = SUCCESS;
  852. /* Check the parameters */
  853. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  854. assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
  855. #if defined (ADC_SUPPORT_2_5_MSPS)
  856. if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
  857. {
  858. assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
  859. }
  860. if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
  861. || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
  862. )
  863. {
  864. assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
  865. /* ADC group regular continuous mode and discontinuous mode */
  866. /* can not be enabled simultenaeously */
  867. assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
  868. || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
  869. }
  870. #else
  871. assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
  872. if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
  873. {
  874. assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
  875. /* ADC group regular continuous mode and discontinuous mode */
  876. /* can not be enabled simultenaeously */
  877. assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
  878. || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
  879. }
  880. #endif
  881. assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
  882. assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
  883. assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
  884. /* Note: Hardware constraint (refer to description of this function): */
  885. /* ADC instance must be disabled. */
  886. if (LL_ADC_IsEnabled(ADCx) == 0UL)
  887. {
  888. /* Configuration of ADC hierarchical scope: */
  889. /* - ADC group regular */
  890. /* - Set ADC group regular trigger source */
  891. /* - Set ADC group regular sequencer length */
  892. /* - Set ADC group regular sequencer discontinuous mode */
  893. /* - Set ADC group regular continuous mode */
  894. /* - Set ADC group regular conversion data transfer: no transfer or */
  895. /* transfer by DMA, and DMA requests mode */
  896. /* - Set ADC group regular overrun behavior */
  897. /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
  898. /* setting of trigger source to SW start. */
  899. #if defined (ADC_SUPPORT_2_5_MSPS)
  900. if( (LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
  901. || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
  902. )
  903. {
  904. /* Case of sequencer mode fixed
  905. or sequencer length >= 2 ranks with sequencer mode fully configurable:
  906. discontinuous mode configured */
  907. MODIFY_REG(ADCx->CFGR1,
  908. ADC_CFGR1_EXTSEL
  909. | ADC_CFGR1_EXTEN
  910. | ADC_CFGR1_DISCEN
  911. | ADC_CFGR1_CONT
  912. | ADC_CFGR1_DMAEN
  913. | ADC_CFGR1_DMACFG
  914. | ADC_CFGR1_OVRMOD
  915. ,
  916. ADC_REG_InitStruct->TriggerSource
  917. | ADC_REG_InitStruct->SequencerDiscont
  918. | ADC_REG_InitStruct->ContinuousMode
  919. | ADC_REG_InitStruct->DMATransfer
  920. | ADC_REG_InitStruct->Overrun
  921. );
  922. }
  923. else
  924. {
  925. /* Case of sequencer mode fully configurable
  926. and sequencer length 1 rank (sequencer disabled):
  927. discontinuous mode discarded (fixed to disable) */
  928. MODIFY_REG(ADCx->CFGR1,
  929. ADC_CFGR1_EXTSEL
  930. | ADC_CFGR1_EXTEN
  931. | ADC_CFGR1_DISCEN
  932. | ADC_CFGR1_CONT
  933. | ADC_CFGR1_DMAEN
  934. | ADC_CFGR1_DMACFG
  935. | ADC_CFGR1_OVRMOD
  936. ,
  937. ADC_REG_InitStruct->TriggerSource
  938. | LL_ADC_REG_SEQ_DISCONT_DISABLE
  939. | ADC_REG_InitStruct->ContinuousMode
  940. | ADC_REG_InitStruct->DMATransfer
  941. | ADC_REG_InitStruct->Overrun
  942. );
  943. }
  944. #else
  945. if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
  946. {
  947. MODIFY_REG(ADCx->CFGR,
  948. ADC_CFGR_EXTSEL
  949. | ADC_CFGR_EXTEN
  950. | ADC_CFGR_DISCEN
  951. | ADC_CFGR_DISCNUM
  952. | ADC_CFGR_CONT
  953. | ADC_CFGR_DMAEN
  954. | ADC_CFGR_DMACFG
  955. | ADC_CFGR_OVRMOD
  956. ,
  957. ADC_REG_InitStruct->TriggerSource
  958. | ADC_REG_InitStruct->SequencerDiscont
  959. | ADC_REG_InitStruct->ContinuousMode
  960. | ADC_REG_InitStruct->DMATransfer
  961. | ADC_REG_InitStruct->Overrun
  962. );
  963. }
  964. else
  965. {
  966. MODIFY_REG(ADCx->CFGR,
  967. ADC_CFGR_EXTSEL
  968. | ADC_CFGR_EXTEN
  969. | ADC_CFGR_DISCEN
  970. | ADC_CFGR_DISCNUM
  971. | ADC_CFGR_CONT
  972. | ADC_CFGR_DMAEN
  973. | ADC_CFGR_DMACFG
  974. | ADC_CFGR_OVRMOD
  975. ,
  976. ADC_REG_InitStruct->TriggerSource
  977. | LL_ADC_REG_SEQ_DISCONT_DISABLE
  978. | ADC_REG_InitStruct->ContinuousMode
  979. | ADC_REG_InitStruct->DMATransfer
  980. | ADC_REG_InitStruct->Overrun
  981. );
  982. }
  983. #endif /* ADC_SUPPORT_2_5_MSPS */
  984. /* Set ADC group regular sequencer length and scan direction */
  985. #if defined (ADC_SUPPORT_2_5_MSPS)
  986. if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
  987. {
  988. LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
  989. }
  990. #else
  991. LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
  992. #endif
  993. }
  994. else
  995. {
  996. /* Initialization error: ADC instance is not disabled. */
  997. status = ERROR;
  998. }
  999. return status;
  1000. }
  1001. /**
  1002. * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
  1003. * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  1004. * whose fields will be set to default values.
  1005. * @retval None
  1006. */
  1007. void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
  1008. {
  1009. /* Set ADC_REG_InitStruct fields to default values */
  1010. /* Set fields of ADC group regular */
  1011. /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
  1012. /* setting of trigger source to SW start. */
  1013. ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
  1014. ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
  1015. ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
  1016. ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
  1017. ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
  1018. ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
  1019. }
  1020. #if defined (ADC_SUPPORT_2_5_MSPS)
  1021. /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
  1022. #else
  1023. /**
  1024. * @brief Initialize some features of ADC group injected.
  1025. * @note These parameters have an impact on ADC scope: ADC group injected.
  1026. * Refer to corresponding unitary functions into
  1027. * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
  1028. * (functions with prefix "INJ").
  1029. * @note The setting of these parameters by function @ref LL_ADC_Init()
  1030. * is conditioned to ADC state:
  1031. * ADC instance must be disabled.
  1032. * This condition is applied to all ADC features, for efficiency
  1033. * and compatibility over all STM32 families. However, the different
  1034. * features can be set under different ADC state conditions
  1035. * (setting possible with ADC enabled without conversion on going,
  1036. * ADC enabled with conversion on going, ...)
  1037. * Each feature can be updated afterwards with a unitary function
  1038. * and potentially with ADC in a different state than disabled,
  1039. * refer to description of each function for setting
  1040. * conditioned to ADC state.
  1041. * @note After using this function, other features must be configured
  1042. * using LL unitary functions.
  1043. * The minimum configuration remaining to be done is:
  1044. * - Set ADC group injected sequencer:
  1045. * map channel on the selected sequencer rank.
  1046. * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
  1047. * - Set ADC channel sampling time
  1048. * Refer to function LL_ADC_SetChannelSamplingTime();
  1049. * @note Caution if feature ADC group injected contexts queue is enabled
  1050. * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
  1051. * using successively several times this function will appear as
  1052. * having no effect.
  1053. * To set several features of ADC group injected, use
  1054. * function @ref LL_ADC_INJ_ConfigQueueContext().
  1055. * @param ADCx ADC instance
  1056. * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
  1057. * @retval An ErrorStatus enumeration value:
  1058. * - SUCCESS: ADC registers are initialized
  1059. * - ERROR: ADC registers are not initialized
  1060. */
  1061. ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
  1062. {
  1063. ErrorStatus status = SUCCESS;
  1064. /* Check the parameters */
  1065. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  1066. assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
  1067. assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
  1068. if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
  1069. {
  1070. assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
  1071. }
  1072. assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
  1073. /* Note: Hardware constraint (refer to description of this function): */
  1074. /* ADC instance must be disabled. */
  1075. if (LL_ADC_IsEnabled(ADCx) == 0UL)
  1076. {
  1077. /* Configuration of ADC hierarchical scope: */
  1078. /* - ADC group injected */
  1079. /* - Set ADC group injected trigger source */
  1080. /* - Set ADC group injected sequencer length */
  1081. /* - Set ADC group injected sequencer discontinuous mode */
  1082. /* - Set ADC group injected conversion trigger: independent or */
  1083. /* from ADC group regular */
  1084. /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
  1085. /* setting of trigger source to SW start. */
  1086. if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
  1087. {
  1088. MODIFY_REG(ADCx->CFGR,
  1089. ADC_CFGR_JDISCEN
  1090. | ADC_CFGR_JAUTO
  1091. ,
  1092. ADC_INJ_InitStruct->SequencerDiscont
  1093. | ADC_INJ_InitStruct->TrigAuto
  1094. );
  1095. }
  1096. else
  1097. {
  1098. MODIFY_REG(ADCx->CFGR,
  1099. ADC_CFGR_JDISCEN
  1100. | ADC_CFGR_JAUTO
  1101. ,
  1102. LL_ADC_REG_SEQ_DISCONT_DISABLE
  1103. | ADC_INJ_InitStruct->TrigAuto
  1104. );
  1105. }
  1106. MODIFY_REG(ADCx->JSQR,
  1107. ADC_JSQR_JEXTSEL
  1108. | ADC_JSQR_JEXTEN
  1109. | ADC_JSQR_JL
  1110. ,
  1111. ADC_INJ_InitStruct->TriggerSource
  1112. | ADC_INJ_InitStruct->SequencerLength
  1113. );
  1114. }
  1115. else
  1116. {
  1117. /* Initialization error: ADC instance is not disabled. */
  1118. status = ERROR;
  1119. }
  1120. return status;
  1121. }
  1122. /**
  1123. * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
  1124. * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
  1125. * whose fields will be set to default values.
  1126. * @retval None
  1127. */
  1128. void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
  1129. {
  1130. /* Set ADC_INJ_InitStruct fields to default values */
  1131. /* Set fields of ADC group injected */
  1132. ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
  1133. ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
  1134. ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
  1135. ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
  1136. }
  1137. #endif
  1138. /**
  1139. * @}
  1140. */
  1141. /**
  1142. * @}
  1143. */
  1144. /**
  1145. * @}
  1146. */
  1147. #endif /* ADC1 */
  1148. /**
  1149. * @}
  1150. */
  1151. #endif /* USE_FULL_LL_DRIVER */
  1152. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/