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stm32lib/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_adc.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32l1xx_ll_adc.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of ADC LL module.

  6.   ******************************************************************************

  7.   * @attention

  8.   *

  9.   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

  10.   * All rights reserved.</center></h2>

  11.   *

  12.   * This software component is licensed by ST under BSD 3-Clause license,

  13.   * the "License"; You may not use this file except in compliance with the

  14.   * License. You may obtain a copy of the License at:

  15.   *                        opensource.org/licenses/BSD-3-Clause

  16.   *

  17.   ******************************************************************************

  18.   */

  19. 

  20. /* Define to prevent recursive inclusion -------------------------------------*/

  21. #ifndef __STM32L1xx_LL_ADC_H

  22. #define __STM32L1xx_LL_ADC_H

  23. 

  24. #ifdef __cplusplus

  25. extern "C" {

  26. #endif

  27. 

  28. /* Includes ------------------------------------------------------------------*/

  29. #include "stm32l1xx.h"

  30. 

  31. /** @addtogroup STM32L1xx_LL_Driver

  32.   * @{

  33.   */

  34. 

  35. #if defined (ADC1)

  36. 

  37. /** @defgroup ADC_LL ADC

  38.   * @{

  39.   */

  40. 

  41. /* Private types -------------------------------------------------------------*/

  42. /* Private variables ---------------------------------------------------------*/

  43. 

  44. /* Private constants ---------------------------------------------------------*/

  45. /** @defgroup ADC_LL_Private_Constants ADC Private Constants

  46.   * @{

  47.   */

  48. 

  49. /* Internal mask for ADC group regular sequencer:                             */

  50. /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */

  51. /* - sequencer register offset                                                */

  52. /* - sequencer rank bits position into the selected register                  */

  53. 

  54. /* Internal register offset for ADC group regular sequencer configuration */

  55. /* (offset placed into a spare area of literal definition) */

  56. #define ADC_SQR1_REGOFFSET                 0x00000000U

  57. #define ADC_SQR2_REGOFFSET                 0x00000100U

  58. #define ADC_SQR3_REGOFFSET                 0x00000200U

  59. #define ADC_SQR4_REGOFFSET                 0x00000300U

  60. #define ADC_SQR5_REGOFFSET                 0x00000400U

  61. 

  62. #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET | ADC_SQR5_REGOFFSET)

  63. #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  64. 

  65. /* Definition of ADC group regular sequencer bits information to be inserted  */

  66. /* into ADC group regular sequencer ranks literals definition.                */

  67. #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ1) */

  68. #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ2) */

  69. #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ3) */

  70. #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ4) */

  71. #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (20U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ5) */

  72. #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (25U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ6) */

  73. #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ7) */

  74. #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ8) */

  75. #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ9) */

  76. #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ10) */

  77. #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ11) */

  78. #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ12) */

  79. #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */

  80. #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */

  81. #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ15) */

  82. #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ16) */

  83. #define ADC_REG_RANK_17_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ17) */

  84. #define ADC_REG_RANK_18_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ18) */

  85. #define ADC_REG_RANK_19_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ29) */

  86. #define ADC_REG_RANK_20_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ20) */

  87. #define ADC_REG_RANK_21_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ21) */

  88. #define ADC_REG_RANK_22_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ22) */

  89. #define ADC_REG_RANK_23_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ23) */

  90. #define ADC_REG_RANK_24_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ24) */

  91. #define ADC_REG_RANK_25_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ25) */

  92. #define ADC_REG_RANK_26_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ26) */

  93. #define ADC_REG_RANK_27_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ27) */

  94. #if defined(ADC_SQR1_SQ28)

  95. #define ADC_REG_RANK_28_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ28) */

  96. #endif

  97. 

  98. 

  99. 

  100. /* Internal mask for ADC group injected sequencer:                            */

  101. /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */

  102. /* - data register offset                                                     */

  103. /* - offset register offset                                                   */

  104. /* - sequencer rank bits position into the selected register                  */

  105. 

  106. /* Internal register offset for ADC group injected data register */

  107. /* (offset placed into a spare area of literal definition) */

  108. #define ADC_JDR1_REGOFFSET                 0x00000000U

  109. #define ADC_JDR2_REGOFFSET                 0x00000100U

  110. #define ADC_JDR3_REGOFFSET                 0x00000200U

  111. #define ADC_JDR4_REGOFFSET                 0x00000300U

  112. 

  113. /* Internal register offset for ADC group injected offset configuration */

  114. /* (offset placed into a spare area of literal definition) */

  115. #define ADC_JOFR1_REGOFFSET                0x00000000U

  116. #define ADC_JOFR2_REGOFFSET                0x00001000U

  117. #define ADC_JOFR3_REGOFFSET                0x00002000U

  118. #define ADC_JOFR4_REGOFFSET                0x00003000U

  119. 

  120. #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

  121. #define ADC_INJ_JOFRX_REGOFFSET_MASK       (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)

  122. #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  123. 

  124. /* Definition of ADC group injected sequencer bits information to be inserted */

  125. /* into ADC group injected sequencer ranks literals definition.               */

  126. #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */

  127. #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */

  128. #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */

  129. #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */

  130. 

  131. 

  132. 

  133. /* Internal mask for ADC group regular trigger:                               */

  134. /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */

  135. /* - regular trigger source                                                   */

  136. /* - regular trigger edge                                                     */

  137. #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  138. 

  139. /* Mask containing trigger source masks for each of possible                  */

  140. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  141. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  142. #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \

  143.                                              ((ADC_CR2_EXTSEL)                            >> (4U * 1U)) | \

  144.                                              ((ADC_CR2_EXTSEL)                            >> (4U * 2U)) | \

  145.                                              ((ADC_CR2_EXTSEL)                            >> (4U * 3U)))

  146. 

  147. /* Mask containing trigger edge masks for each of possible                    */

  148. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  149. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  150. #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \

  151.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 1U)) | \

  152.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 2U)) | \

  153.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 3U)))

  154. 

  155. /* Definition of ADC group regular trigger bits information.                  */

  156. #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */

  157. #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */

  158. 

  159. 

  160. 

  161. /* Internal mask for ADC group injected trigger:                              */

  162. /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */

  163. /* - injected trigger source                                                  */

  164. /* - injected trigger edge                                                    */

  165. #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  166. 

  167. /* Mask containing trigger source masks for each of possible                  */

  168. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  169. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  170. #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \

  171.                                              ((ADC_CR2_JEXTSEL)                            >> (4U * 1U)) | \

  172.                                              ((ADC_CR2_JEXTSEL)                            >> (4U * 2U)) | \

  173.                                              ((ADC_CR2_JEXTSEL)                            >> (4U * 3U)))

  174. 

  175. /* Mask containing trigger edge masks for each of possible                    */

  176. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  177. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  178. #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \

  179.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 1U)) | \

  180.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 2U)) | \

  181.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 3U)))

  182. 

  183. /* Definition of ADC group injected trigger bits information.                 */

  184. #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */

  185. #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */

  186. 

  187. 

  188. 

  189. 

  190. 

  191. 

  192. /* Internal mask for ADC channel:                                             */

  193. /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */

  194. /* - channel identifier defined by number                                     */

  195. /* - channel differentiation between external channels (connected to          */

  196. /*   GPIO pins) and internal channels (connected to internal paths)           */

  197. /* - channel sampling time defined by SMPRx register offset                   */

  198. /*   and SMPx bits positions into SMPRx register                              */

  199. #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CR1_AWDCH)

  200. #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */

  201. #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  202. /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */

  203. #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */

  204. 

  205. /* Channel differentiation between external and internal channels */

  206. #define ADC_CHANNEL_ID_INTERNAL_CH         0x80000000U   /* Marker of internal channel */

  207. #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)

  208. 

  209. /* Internal register offset for ADC channel sampling time configuration */

  210. /* (offset placed into a spare area of literal definition) */

  211. #define ADC_SMPR1_REGOFFSET                0x00000000U

  212. #define ADC_SMPR2_REGOFFSET                0x02000000U

  213. #define ADC_SMPR3_REGOFFSET                0x04000000U

  214. #if defined(ADC_SMPR0_SMP31)

  215. #define ADC_SMPR0_REGOFFSET                0x28000000U   /* SMPR0 register offset from SMPR1 is 20 registers. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */

  216. #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET | ADC_SMPR0_REGOFFSET)

  217. #else

  218. #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET)

  219. #endif /* ADC_SMPR0_SMP31 */

  220. 

  221. #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    0x01F00000U

  222. #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */

  223. 

  224. /* Definition of channels ID number information to be inserted into           */

  225. /* channels literals definition.                                              */

  226. #define ADC_CHANNEL_0_NUMBER               0x00000000U

  227. #define ADC_CHANNEL_1_NUMBER               (                                                                        ADC_CR1_AWDCH_0)

  228. #define ADC_CHANNEL_2_NUMBER               (                                                      ADC_CR1_AWDCH_1                  )

  229. #define ADC_CHANNEL_3_NUMBER               (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  230. #define ADC_CHANNEL_4_NUMBER               (                                    ADC_CR1_AWDCH_2                                    )

  231. #define ADC_CHANNEL_5_NUMBER               (                                    ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)

  232. #define ADC_CHANNEL_6_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )

  233. #define ADC_CHANNEL_7_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  234. #define ADC_CHANNEL_8_NUMBER               (                  ADC_CR1_AWDCH_3                                                      )

  235. #define ADC_CHANNEL_9_NUMBER               (                  ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)

  236. #define ADC_CHANNEL_10_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )

  237. #define ADC_CHANNEL_11_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  238. #define ADC_CHANNEL_12_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )

  239. #define ADC_CHANNEL_13_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)

  240. #define ADC_CHANNEL_14_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )

  241. #define ADC_CHANNEL_15_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  242. #define ADC_CHANNEL_16_NUMBER              (ADC_CR1_AWDCH_4                                                                        )

  243. #define ADC_CHANNEL_17_NUMBER              (ADC_CR1_AWDCH_4                                                       | ADC_CR1_AWDCH_0)

  244. #define ADC_CHANNEL_18_NUMBER              (ADC_CR1_AWDCH_4                                     | ADC_CR1_AWDCH_1                  )

  245. #define ADC_CHANNEL_19_NUMBER              (ADC_CR1_AWDCH_4                                     | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  246. #define ADC_CHANNEL_20_NUMBER              (ADC_CR1_AWDCH_4                   | ADC_CR1_AWDCH_2                                    )

  247. #define ADC_CHANNEL_21_NUMBER              (ADC_CR1_AWDCH_4                   | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)

  248. #define ADC_CHANNEL_22_NUMBER              (ADC_CR1_AWDCH_4                   | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )

  249. #define ADC_CHANNEL_23_NUMBER              (ADC_CR1_AWDCH_4                   | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  250. #define ADC_CHANNEL_24_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3                                                      )

  251. #define ADC_CHANNEL_25_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)

  252. #define ADC_CHANNEL_26_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )

  253. #if defined(ADC_SMPR0_SMP31)

  254. #define ADC_CHANNEL_27_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  255. #define ADC_CHANNEL_28_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )

  256. #define ADC_CHANNEL_29_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)

  257. #define ADC_CHANNEL_30_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )

  258. #define ADC_CHANNEL_31_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  259. #endif /* ADC_SMPR0_SMP31 */

  260. 

  261. /* Definition of channels sampling time information to be inserted into       */

  262. /* channels literals definition.                                              */

  263. #define ADC_CHANNEL_0_SMP                  (ADC_SMPR3_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP0) */

  264. #define ADC_CHANNEL_1_SMP                  (ADC_SMPR3_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP1) */

  265. #define ADC_CHANNEL_2_SMP                  (ADC_SMPR3_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP2) */

  266. #define ADC_CHANNEL_3_SMP                  (ADC_SMPR3_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP3) */

  267. #define ADC_CHANNEL_4_SMP                  (ADC_SMPR3_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP4) */

  268. #define ADC_CHANNEL_5_SMP                  (ADC_SMPR3_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP5) */

  269. #define ADC_CHANNEL_6_SMP                  (ADC_SMPR3_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP6) */

  270. #define ADC_CHANNEL_7_SMP                  (ADC_SMPR3_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP7) */

  271. #define ADC_CHANNEL_8_SMP                  (ADC_SMPR3_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP8) */

  272. #define ADC_CHANNEL_9_SMP                  (ADC_SMPR3_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP9) */

  273. #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */

  274. #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */

  275. #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */

  276. #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */

  277. #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */

  278. #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */

  279. #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */

  280. #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */

  281. #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */

  282. #define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP19) */

  283. #define ADC_CHANNEL_20_SMP                 (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP20) */

  284. #define ADC_CHANNEL_21_SMP                 (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP21) */

  285. #define ADC_CHANNEL_22_SMP                 (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP22) */

  286. #define ADC_CHANNEL_23_SMP                 (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP23) */

  287. #define ADC_CHANNEL_24_SMP                 (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP24) */

  288. #define ADC_CHANNEL_25_SMP                 (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP25) */

  289. #define ADC_CHANNEL_26_SMP                 (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP26) */

  290. #if defined(ADC_SMPR0_SMP31)

  291. #define ADC_CHANNEL_27_SMP                 (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP27) */

  292. #define ADC_CHANNEL_28_SMP                 (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP28) */

  293. #define ADC_CHANNEL_29_SMP                 (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP19) */

  294. #define ADC_CHANNEL_30_SMP                 (ADC_SMPR0_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP30) */

  295. #define ADC_CHANNEL_31_SMP                 (ADC_SMPR0_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP31) */

  296. #endif /* ADC_SMPR0_SMP31 */

  297. 

  298. 

  299. /* Internal mask for ADC analog watchdog:                                     */

  300. /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */

  301. /* (concatenation of multiple bits used in different analog watchdogs,        */

  302. /* (feature of several watchdogs not available on all STM32 families)).       */

  303. /* - analog watchdog 1: monitored channel defined by number,                  */

  304. /*   selection of ADC group (ADC groups regular and-or injected).             */

  305. 

  306. /* Internal register offset for ADC analog watchdog channel configuration */

  307. #define ADC_AWD_CR1_REGOFFSET              0x00000000U

  308. 

  309. #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)

  310. 

  311. #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

  312. #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)

  313. 

  314. /* Internal register offset for ADC analog watchdog threshold configuration */

  315. #define ADC_AWD_TR1_HIGH_REGOFFSET         0x00000000U

  316. #define ADC_AWD_TR1_LOW_REGOFFSET          0x00000001U

  317. #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)

  318. 

  319. 

  320. /* ADC registers bits positions */

  321. #define ADC_CR1_RES_BITOFFSET_POS          (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */

  322. #define ADC_TR_HT_BITOFFSET_POS            (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */

  323. 

  324. 

  325. /* ADC internal channels related definitions */

  326. /* Internal voltage reference VrefInt */

  327. #define VREFINT_CAL_ADDR                   ((uint16_t*) VREFINT_CAL_ADDR_CMSIS)     /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

  328. #define VREFINT_CAL_VREF                   ( 3000U)                                 /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

  329. /* Temperature sensor */

  330. #if defined (TEMPSENSOR_CAL1_ADDR_CMSIS)

  331. #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) TEMPSENSOR_CAL1_ADDR_CMSIS) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

  332. #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) TEMPSENSOR_CAL2_ADDR_CMSIS) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

  333. #endif /* TEMPSENSOR_CAL1_ADDR_CMSIS */

  334. #define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  335. #define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  336. #define TEMPSENSOR_CAL_VREFANALOG          ( 3000U)                                 /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

  337. 

  338. 

  339. /**

  340.   * @}

  341.   */

  342. 

  343. 

  344. /* Private macros ------------------------------------------------------------*/

  345. /** @defgroup ADC_LL_Private_Macros ADC Private Macros

  346.   * @{

  347.   */

  348. 

  349. /**

  350.   * @brief  Driver macro reserved for internal use: isolate bits with the

  351.   *         selected mask and shift them to the register LSB

  352.   *         (shift mask on register position bit 0).

  353.   * @param  __BITS__ Bits in register 32 bits

  354.   * @param  __MASK__ Mask in register 32 bits

  355.   * @retval Bits in register 32 bits

  356.   */

  357. #define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \

  358.   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))

  359. 

  360. /**

  361.   * @brief  Driver macro reserved for internal use: set a pointer to

  362.   *         a register from a register basis from which an offset

  363.   *         is applied.

  364.   * @param  __REG__ Register basis from which the offset is applied.

  365.   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).

  366.   * @retval Pointer to register address

  367.   */

  368. #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \

  369.  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))

  370. 

  371. /**

  372.   * @}

  373.   */

  374. 

  375. 

  376. /* Exported types ------------------------------------------------------------*/

  377. #if defined(USE_FULL_LL_DRIVER)

  378. /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure

  379.   * @{

  380.   */

  381. 

  382. /**

  383.   * @brief  Structure definition of some features of ADC common parameters

  384.   *         and multimode

  385.   *         (all ADC instances belonging to the same ADC common instance).

  386.   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()

  387.   *         is conditioned to ADC instances state (all ADC instances

  388.   *         sharing the same ADC common instance):

  389.   *         All ADC instances sharing the same ADC common instance must be

  390.   *         disabled.

  391.   */

  392. typedef struct

  393. {

  394.   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.

  395.                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE

  396.                                              @note On this STM32 serie, HSI RC oscillator is the only clock source for ADC.

  397.                                                    Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level.

  398.                                              @note On this STM32 serie, some clock ratio constraints between ADC clock and APB clock

  399.                                                    must be respected:

  400.                                                     - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted.

  401.                                                     - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits.

  402.                                                    Refer to reference manual.

  403. 

  404.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */

  405. 

  406. } LL_ADC_CommonInitTypeDef;

  407. 

  408. /**

  409.   * @brief  Structure definition of some features of ADC instance.

  410.   * @note   These parameters have an impact on ADC scope: ADC instance.

  411.   *         Affects both group regular and group injected (availability

  412.   *         of ADC group injected depends on STM32 families).

  413.   *         Refer to corresponding unitary functions into

  414.   *         @ref ADC_LL_EF_Configuration_ADC_Instance .

  415.   * @note   The setting of these parameters by function @ref LL_ADC_Init()

  416.   *         is conditioned to ADC state:

  417.   *         ADC instance must be disabled.

  418.   *         This condition is applied to all ADC features, for efficiency

  419.   *         and compatibility over all STM32 families. However, the different

  420.   *         features can be set under different ADC state conditions

  421.   *         (setting possible with ADC enabled without conversion on going,

  422.   *         ADC enabled with conversion on going, ...)

  423.   *         Each feature can be updated afterwards with a unitary function

  424.   *         and potentially with ADC in a different state than disabled,

  425.   *         refer to description of each function for setting

  426.   *         conditioned to ADC state.

  427.   */

  428. typedef struct

  429. {

  430.   uint32_t Resolution;                  /*!< Set ADC resolution.

  431.                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION

  432. 

  433.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */

  434. 

  435.   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.

  436.                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN

  437. 

  438.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */

  439. 

  440.   uint32_t LowPowerMode;                /*!< Set ADC low power mode.

  441.                                              This parameter can be a concatenation of a value of @ref ADC_LL_EC_LP_MODE_AUTOWAIT and a value of @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF

  442. 

  443.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerModeAutoWait() and @ref LL_ADC_SetLowPowerModeAutoPowerOff(). */

  444. 

  445.   uint32_t SequencersScanMode;          /*!< Set ADC scan selection.

  446.                                              This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION

  447. 

  448.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */

  449. 

  450. } LL_ADC_InitTypeDef;

  451. 

  452. /**

  453.   * @brief  Structure definition of some features of ADC group regular.

  454.   * @note   These parameters have an impact on ADC scope: ADC group regular.

  455.   *         Refer to corresponding unitary functions into

  456.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  457.   *         (functions with prefix "REG").

  458.   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()

  459.   *         is conditioned to ADC state:

  460.   *         ADC instance must be disabled.

  461.   *         This condition is applied to all ADC features, for efficiency

  462.   *         and compatibility over all STM32 families. However, the different

  463.   *         features can be set under different ADC state conditions

  464.   *         (setting possible with ADC enabled without conversion on going,

  465.   *         ADC enabled with conversion on going, ...)

  466.   *         Each feature can be updated afterwards with a unitary function

  467.   *         and potentially with ADC in a different state than disabled,

  468.   *         refer to description of each function for setting

  469.   *         conditioned to ADC state.

  470.   */

  471. typedef struct

  472. {

  473.   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

  474.                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE

  475.                                              @note On this STM32 serie, setting of external trigger edge is performed

  476.                                                    using function @ref LL_ADC_REG_StartConversionExtTrig().

  477. 

  478.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */

  479. 

  480.   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.

  481.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH

  482.                                              @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').

  483. 

  484.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */

  485. 

  486.   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  487.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE

  488.                                              @note This parameter has an effect only if group regular sequencer is enabled

  489.                                                    (scan length of 2 ranks or more).

  490. 

  491.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */

  492. 

  493.   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).

  494.                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE

  495.                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

  496. 

  497.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */

  498. 

  499.   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

  500.                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER

  501. 

  502.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */

  503. 

  504. } LL_ADC_REG_InitTypeDef;

  505. 

  506. /**

  507.   * @brief  Structure definition of some features of ADC group injected.

  508.   * @note   These parameters have an impact on ADC scope: ADC group injected.

  509.   *         Refer to corresponding unitary functions into

  510.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  511.   *         (functions with prefix "INJ").

  512.   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()

  513.   *         is conditioned to ADC state:

  514.   *         ADC instance must be disabled.

  515.   *         This condition is applied to all ADC features, for efficiency

  516.   *         and compatibility over all STM32 families. However, the different

  517.   *         features can be set under different ADC state conditions

  518.   *         (setting possible with ADC enabled without conversion on going,

  519.   *         ADC enabled with conversion on going, ...)

  520.   *         Each feature can be updated afterwards with a unitary function

  521.   *         and potentially with ADC in a different state than disabled,

  522.   *         refer to description of each function for setting

  523.   *         conditioned to ADC state.

  524.   */

  525. typedef struct

  526. {

  527.   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

  528.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE

  529.                                              @note On this STM32 serie, setting of external trigger edge is performed

  530.                                                    using function @ref LL_ADC_INJ_StartConversionExtTrig().

  531. 

  532.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */

  533. 

  534.   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.

  535.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH

  536.                                              @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').

  537. 

  538.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */

  539. 

  540.   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  541.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE

  542.                                              @note This parameter has an effect only if group injected sequencer is enabled

  543.                                                    (scan length of 2 ranks or more).

  544. 

  545.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */

  546. 

  547.   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.

  548.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO

  549.                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

  550. 

  551.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */

  552. 

  553. } LL_ADC_INJ_InitTypeDef;

  554. 

  555. /**

  556.   * @}

  557.   */

  558. #endif /* USE_FULL_LL_DRIVER */

  559. 

  560. /* Exported constants --------------------------------------------------------*/

  561. /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants

  562.   * @{

  563.   */

  564. 

  565. /** @defgroup ADC_LL_EC_FLAG ADC flags

  566.   * @brief    Flags defines which can be used with LL_ADC_ReadReg function

  567.   * @{

  568.   */

  569. #define LL_ADC_FLAG_ADRDY                  ADC_SR_ADONS       /*!< ADC flag ADC instance ready */

  570. #define LL_ADC_FLAG_STRT                   ADC_SR_STRT        /*!< ADC flag ADC group regular conversion start */

  571. #define LL_ADC_FLAG_EOCS                   ADC_SR_EOC         /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */

  572. #define LL_ADC_FLAG_OVR                    ADC_SR_OVR         /*!< ADC flag ADC group regular overrun */

  573. #define LL_ADC_FLAG_JSTRT                  ADC_SR_JSTRT       /*!< ADC flag ADC group injected conversion start */

  574. #define LL_ADC_FLAG_JEOS                   ADC_SR_JEOC        /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */

  575. #define LL_ADC_FLAG_AWD1                   ADC_SR_AWD         /*!< ADC flag ADC analog watchdog 1 */

  576. /**

  577.   * @}

  578.   */

  579. 

  580. /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)

  581.   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions

  582.   * @{

  583.   */

  584. #define LL_ADC_IT_EOCS                     ADC_CR1_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */

  585. #define LL_ADC_IT_OVR                      ADC_CR1_OVRIE      /*!< ADC interruption ADC group regular overrun */

  586. #define LL_ADC_IT_JEOS                     ADC_CR1_JEOCIE     /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */

  587. #define LL_ADC_IT_AWD1                     ADC_CR1_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */

  588. /**

  589.   * @}

  590.   */

  591. 

  592. /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose

  593.   * @{

  594.   */

  595. /* List of ADC registers intended to be used (most commonly) with             */

  596. /* DMA transfer.                                                              */

  597. /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */

  598. #define LL_ADC_DMA_REG_REGULAR_DATA          0x00000000U   /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

  599. /**

  600.   * @}

  601.   */

  602. 

  603. /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source

  604.   * @{

  605.   */

  606. #define LL_ADC_CLOCK_ASYNC_DIV1            0x00000000U                                           /*!< ADC asynchronous clock without prescaler */

  607. #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_ADCPRE_0)                                    /*!< ADC asynchronous clock with prescaler division by 2   */

  608. #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_ADCPRE_1)                                    /*!< ADC asynchronous clock with prescaler division by 4   */

  609. /**

  610.   * @}

  611.   */

  612. 

  613. /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels

  614.   * @{

  615.   */

  616. /* Note: Other measurement paths to internal channels may be available        */

  617. /*       (connections to other peripherals).                                  */

  618. /*       If they are not listed below, they do not require any specific       */

  619. /*       path enable. In this case, Access to measurement path is done        */

  620. /*       only by selecting the corresponding ADC internal channel.            */

  621. #define LL_ADC_PATH_INTERNAL_NONE          0x00000000U            /*!< ADC measurement pathes all disabled */

  622. #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel VrefInt */

  623. #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel temperature sensor */

  624. /**

  625.   * @}

  626.   */

  627. 

  628. /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution

  629.   * @{

  630.   */

  631. #define LL_ADC_RESOLUTION_12B              0x00000000U                         /*!< ADC resolution 12 bits */

  632. #define LL_ADC_RESOLUTION_10B              (                ADC_CR1_RES_0)     /*!< ADC resolution 10 bits */

  633. #define LL_ADC_RESOLUTION_8B               (ADC_CR1_RES_1                )     /*!< ADC resolution  8 bits */

  634. #define LL_ADC_RESOLUTION_6B               (ADC_CR1_RES_1 | ADC_CR1_RES_0)     /*!< ADC resolution  6 bits */

  635. /**

  636.   * @}

  637.   */

  638. 

  639. /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment

  640.   * @{

  641.   */

  642. #define LL_ADC_DATA_ALIGN_RIGHT            0x00000000U            /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/

  643. #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CR2_ALIGN)        /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/

  644. /**

  645.   * @}

  646.   */

  647. 

  648. /** @defgroup ADC_LL_EC_LP_MODE_AUTOWAIT  ADC instance - Low power mode auto wait (auto delay)

  649.   * @{

  650.   */

  651. #define LL_ADC_LP_AUTOWAIT_NONE               0x00000000U                                        /*!< ADC low power mode auto wait not activated */

  652. #define LL_ADC_LP_AUTOWAIT                    (                                  ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerModeAutoWait(). */

  653. #define LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES   (                 ADC_CR2_DELS_1                 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 7 APB clock cycles */

  654. #define LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES  (                 ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 15 APB clock cycles */

  655. #define LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES  (ADC_CR2_DELS_2                                  ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 31 APB clock cycles */

  656. #define LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES  (ADC_CR2_DELS_2                  | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 63 APB clock cycles */

  657. #define LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_1                 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 127 APB clock cycles */

  658. #define LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 255 APB clock cycles */

  659. /**

  660.   * @}

  661.   */

  662. 

  663. /** @defgroup ADC_LL_EC_LP_MODE_AUTOPOWEROFF  ADC instance - Low power mode auto power-off

  664.   * @{

  665.   */

  666. #define LL_ADC_LP_AUTOPOWEROFF_NONE                 0x00000000U                                  /*!< ADC low power mode auto power-off not activated */

  667. #define LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE           (ADC_CR1_PDI)                                /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) */

  668. #define LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE       (ADC_CR1_PDD)                                /*!< ADC low power mode auto power-off: ADC power off when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */

  669. #define LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES (ADC_CR1_PDI | ADC_CR1_PDD)                  /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */

  670. /**

  671.   * @}

  672.   */

  673. 

  674. /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection

  675.   * @{

  676.   */

  677. #define LL_ADC_SEQ_SCAN_DISABLE            0x00000000U    /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/

  678. #define LL_ADC_SEQ_SCAN_ENABLE             (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */

  679. /**

  680.   * @}

  681.   */

  682. 

  683. #if defined(ADC_CR2_CFG)

  684. /** @defgroup ADC_LL_EC_CHANNELS_BANK ADC instance - Channels bank

  685.   * @{

  686.   */

  687. #define LL_ADC_CHANNELS_BANK_A             0x00000000U   /*!< ADC channels bank A */

  688. #define LL_ADC_CHANNELS_BANK_B             (ADC_CR2_CFG) /*!< ADC channels bank B, available in devices categories 3, 4, 5. */

  689. /**

  690.   * @}

  691.   */

  692. #endif

  693. 

  694. /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups

  695.   * @{

  696.   */

  697. #define LL_ADC_GROUP_REGULAR               0x00000001U   /*!< ADC group regular (available on all STM32 devices) */

  698. #define LL_ADC_GROUP_INJECTED              0x00000002U   /*!< ADC group injected (not available on all STM32 devices)*/

  699. #define LL_ADC_GROUP_REGULAR_INJECTED      0x00000003U   /*!< ADC both groups regular and injected */

  700. /**

  701.   * @}

  702.   */

  703. 

  704. /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number

  705.   * @{

  706.   */

  707. #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 . Channel different in bank A and bank B. */

  708. #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 . Channel different in bank A and bank B. */

  709. #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 . Channel different in bank A and bank B. */

  710. #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 . Channel different in bank A and bank B. */

  711. #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 . Direct (fast) channel. */

  712. #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 . Direct (fast) channel. */

  713. #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 . Channel different in bank A and bank B. */

  714. #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 . Channel different in bank A and bank B. */

  715. #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 . Channel different in bank A and bank B. */

  716. #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 . Channel different in bank A and bank B. */

  717. #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10. Channel different in bank A and bank B. */

  718. #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11. Channel different in bank A and bank B. */

  719. #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12. Channel different in bank A and bank B. */

  720. #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13. Channel common to both bank A and bank B. */

  721. #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14. Channel common to both bank A and bank B. */

  722. #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15. Channel common to both bank A and bank B. */

  723. #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16. Channel common to both bank A and bank B. */

  724. #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17. Channel common to both bank A and bank B. */

  725. #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18. Channel common to both bank A and bank B. */

  726. #define LL_ADC_CHANNEL_19                  (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19. Channel common to both bank A and bank B. */

  727. #define LL_ADC_CHANNEL_20                  (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20. Channel common to both bank A and bank B. */

  728. #define LL_ADC_CHANNEL_21                  (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21. Channel common to both bank A and bank B. */

  729. #define LL_ADC_CHANNEL_22                  (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22. Direct (fast) channel. */

  730. #define LL_ADC_CHANNEL_23                  (ADC_CHANNEL_23_NUMBER | ADC_CHANNEL_23_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23. Direct (fast) channel. */

  731. #define LL_ADC_CHANNEL_24                  (ADC_CHANNEL_24_NUMBER | ADC_CHANNEL_24_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN24. Direct (fast) channel. */

  732. #define LL_ADC_CHANNEL_25                  (ADC_CHANNEL_25_NUMBER | ADC_CHANNEL_25_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN25. Direct (fast) channel. */

  733. #define LL_ADC_CHANNEL_26                  (ADC_CHANNEL_26_NUMBER | ADC_CHANNEL_26_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN26. Direct (fast) channel. */

  734. #if defined(ADC_SMPR0_SMP31)

  735. #define LL_ADC_CHANNEL_27                  (ADC_CHANNEL_27_NUMBER | ADC_CHANNEL_27_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN27. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */

  736. #define LL_ADC_CHANNEL_28                  (ADC_CHANNEL_28_NUMBER | ADC_CHANNEL_28_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN28. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */

  737. #define LL_ADC_CHANNEL_29                  (ADC_CHANNEL_29_NUMBER | ADC_CHANNEL_29_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN29. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */

  738. #define LL_ADC_CHANNEL_30                  (ADC_CHANNEL_30_NUMBER | ADC_CHANNEL_30_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN30. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */

  739. #define LL_ADC_CHANNEL_31                  (ADC_CHANNEL_31_NUMBER | ADC_CHANNEL_31_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN31. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */

  740. #endif /* ADC_SMPR0_SMP31 */

  741. #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. Channel common to both bank A and bank B. */

  742. #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. Channel common to both bank A and bank B. */

  743. #define LL_ADC_CHANNEL_VCOMP               (LL_ADC_CHANNEL_26 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */

  744. #if defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) || defined (OPAMP_CSR_OPA3PD)

  745. #define LL_ADC_CHANNEL_VOPAMP1             (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */

  746. #define LL_ADC_CHANNEL_VOPAMP2             (LL_ADC_CHANNEL_8 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */

  747. #if defined(OPAMP_CSR_OPA3PD)

  748. #define LL_ADC_CHANNEL_VOPAMP3             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */

  749. #endif /* OPAMP_CSR_OPA3PD */

  750. #endif /* OPAMP_CSR_OPA1PD || OPAMP_CSR_OPA2PD || OPAMP_CSR_OPA3PD */

  751. /**

  752.   * @}

  753.   */

  754. 

  755. /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source

  756.   * @{

  757.   */

  758. #define LL_ADC_REG_TRIG_SOFTWARE           0x00000000U                                                                                                 /*!< ADC group regular conversion trigger internal: SW start. */

  759. #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */

  760. #define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  761. #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */

  762. #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  763. #define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  764. #define LL_ADC_REG_TRIG_EXT_TIM3_CH3       (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  765. #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */

  766. #define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  767. #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */

  768. #define LL_ADC_REG_TRIG_EXT_TIM9_CH2       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                             /*!< ADC group regular conversion trigger from external IP: TIM9 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  769. #define LL_ADC_REG_TRIG_EXT_TIM9_TRGO      (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */

  770. #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */

  771. /**

  772.   * @}

  773.   */

  774. 

  775. /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge

  776.   * @{

  777.   */

  778. #define LL_ADC_REG_TRIG_EXT_RISING         (                  ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to rising edge */

  779. #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CR2_EXTEN_1                  )     /*!< ADC group regular conversion trigger polarity set to falling edge */

  780. #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */

  781. /**

  782.   * @}

  783.   */

  784. 

  785. /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode

  786. * @{

  787. */

  788. #define LL_ADC_REG_CONV_SINGLE             0x00000000U             /*!< ADC conversions are performed in single mode: one conversion per trigger */

  789. #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CR2_CONT)          /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */

  790. /**

  791.   * @}

  792.   */

  793. 

  794. /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data

  795.   * @{

  796.   */

  797. #define LL_ADC_REG_DMA_TRANSFER_NONE       0x00000000U              /*!< ADC conversions are not transferred by DMA */

  798. #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (              ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */

  799. #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CR2_DDS | ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */

  800. /**

  801.   * @}

  802.   */

  803. 

  804. /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)

  805.   * @{

  806.   */

  807. #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV       0x00000000U    /*!< ADC flag EOC (end of unitary conversion) selected */

  808. #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV        (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */

  809. /**

  810.   * @}

  811.   */

  812. 

  813. /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length

  814.   * @{

  815.   */

  816. #define LL_ADC_REG_SEQ_SCAN_DISABLE        0x00000000U                                                 /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  817. #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */

  818. #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */

  819. #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */

  820. #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */

  821. #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */

  822. #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */

  823. #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */

  824. #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */

  825. #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */

  826. #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */

  827. #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */

  828. #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */

  829. #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */

  830. #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */

  831. #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */

  832. /**

  833.   * @}

  834.   */

  835. 

  836. /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode

  837.   * @{

  838.   */

  839. #define LL_ADC_REG_SEQ_DISCONT_DISABLE     0x00000000U                                                                  /*!< ADC group regular sequencer discontinuous mode disable */

  840. #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                            ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */

  841. #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                        ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */

  842. #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                    ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */

  843. #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                    ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */

  844. #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CR1_DISCNUM_2                                         | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */

  845. #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CR1_DISCNUM_2                     | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */

  846. #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */

  847. #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */

  848. /**

  849.   * @}

  850.   */

  851. 

  852. /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks

  853.   * @{

  854.   */

  855. #define LL_ADC_REG_RANK_1                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */

  856. #define LL_ADC_REG_RANK_2                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */

  857. #define LL_ADC_REG_RANK_3                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */

  858. #define LL_ADC_REG_RANK_4                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */

  859. #define LL_ADC_REG_RANK_5                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */

  860. #define LL_ADC_REG_RANK_6                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */

  861. #define LL_ADC_REG_RANK_7                  (ADC_SQR4_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */

  862. #define LL_ADC_REG_RANK_8                  (ADC_SQR4_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */

  863. #define LL_ADC_REG_RANK_9                  (ADC_SQR4_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */

  864. #define LL_ADC_REG_RANK_10                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */

  865. #define LL_ADC_REG_RANK_11                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */

  866. #define LL_ADC_REG_RANK_12                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */

  867. #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */

  868. #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */

  869. #define LL_ADC_REG_RANK_15                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */

  870. #define LL_ADC_REG_RANK_16                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */

  871. #define LL_ADC_REG_RANK_17                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_17_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 17 */

  872. #define LL_ADC_REG_RANK_18                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_18_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 18 */

  873. #define LL_ADC_REG_RANK_19                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_19_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 19 */

  874. #define LL_ADC_REG_RANK_20                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_20_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 20 */

  875. #define LL_ADC_REG_RANK_21                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_21_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 21 */

  876. #define LL_ADC_REG_RANK_22                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_22_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 22 */

  877. #define LL_ADC_REG_RANK_23                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_23_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 23 */

  878. #define LL_ADC_REG_RANK_24                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_24_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 24 */

  879. #define LL_ADC_REG_RANK_25                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_25_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 25 */

  880. #define LL_ADC_REG_RANK_26                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_26_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 26 */

  881. #define LL_ADC_REG_RANK_27                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_27_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 27 */

  882. #if defined(ADC_SQR1_SQ28)

  883. #define LL_ADC_REG_RANK_28                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_28_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 28 */

  884. #endif

  885. /**

  886.   * @}

  887.   */

  888. 

  889. /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source

  890.   * @{

  891.   */

  892. #define LL_ADC_INJ_TRIG_SOFTWARE           0x00000000U                                                                                                     /*!< ADC group injected conversion trigger internal: SW start. */

  893. #define LL_ADC_INJ_TRIG_EXT_TIM9_CH1       (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group injected conversion trigger from external IP: TIM9 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  894. #define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO      (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */

  895. #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */

  896. #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  897. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  898. #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */

  899. #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  900. #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  901. #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  902. #define LL_ADC_INJ_TRIG_EXT_TIM10_CH1      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM10 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  903. #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */

  904. #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */

  905. /**

  906.   * @}

  907.   */

  908. 

  909. /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge

  910.   * @{

  911.   */

  912. #define LL_ADC_INJ_TRIG_EXT_RISING         (                   ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to rising edge */

  913. #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_CR2_JEXTEN_1                   )   /*!< ADC group injected conversion trigger polarity set to falling edge */

  914. #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */

  915. /**

  916.   * @}

  917.   */

  918. 

  919. /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode

  920. * @{

  921. */

  922. #define LL_ADC_INJ_TRIG_INDEPENDENT        0x00000000U            /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */

  923. #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CR1_JAUTO)        /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */

  924. /**

  925.   * @}

  926.   */

  927. 

  928. 

  929. /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length

  930.   * @{

  931.   */

  932. #define LL_ADC_INJ_SEQ_SCAN_DISABLE        0x00000000U                     /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  933. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */

  934. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */

  935. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */

  936. /**

  937.   * @}

  938.   */

  939. 

  940. /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode

  941.   * @{

  942.   */

  943. #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     0x00000000U            /*!< ADC group injected sequencer discontinuous mode disable */

  944. #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CR1_JDISCEN)      /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */

  945. /**

  946.   * @}

  947.   */

  948. 

  949. /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks

  950.   * @{

  951.   */

  952. #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */

  953. #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */

  954. #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */

  955. #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */

  956. /**

  957.   * @}

  958.   */

  959. 

  960. /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time

  961.   * @{

  962.   */

  963. #define LL_ADC_SAMPLINGTIME_4CYCLES        0x00000000U                                              /*!< Sampling time 4 ADC clock cycles */

  964. #define LL_ADC_SAMPLINGTIME_9CYCLES        (ADC_SMPR3_SMP0_0)                                       /*!< Sampling time 9 ADC clock cycles */

  965. #define LL_ADC_SAMPLINGTIME_16CYCLES       (ADC_SMPR3_SMP0_1)                                       /*!< Sampling time 16 ADC clock cycles */

  966. #define LL_ADC_SAMPLINGTIME_24CYCLES       (ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)                    /*!< Sampling time 24 ADC clock cycles */

  967. #define LL_ADC_SAMPLINGTIME_48CYCLES       (ADC_SMPR3_SMP0_2)                                       /*!< Sampling time 48 ADC clock cycles */

  968. #define LL_ADC_SAMPLINGTIME_96CYCLES       (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)                    /*!< Sampling time 96 ADC clock cycles */

  969. #define LL_ADC_SAMPLINGTIME_192CYCLES      (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)                    /*!< Sampling time 192 ADC clock cycles */

  970. #define LL_ADC_SAMPLINGTIME_384CYCLES      (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0) /*!< Sampling time 384 ADC clock cycles */

  971. /**

  972.   * @}

  973.   */

  974. 

  975. #if defined(COMP_CSR_FCH3)

  976. /** @defgroup ADC_LL_EC_CHANNEL_ROUTING_LIST  Channel - Routing channels list

  977.   * @{

  978.   */

  979. #define LL_ADC_CHANNEL_3_ROUTING           (COMP_CSR_FCH3)  /*!< ADC channel 3 routing. Used as ADC direct channel (fast channel) if OPAMP1 is in power down mode. */

  980. #define LL_ADC_CHANNEL_8_ROUTING           (COMP_CSR_FCH8)  /*!< ADC channel 8 routing. Used as ADC direct channel (fast channel) if OPAMP2 is in power down mode. */

  981. #define LL_ADC_CHANNEL_13_ROUTING          (COMP_CSR_RCH13) /*!< ADC channel 13 routing. Used as ADC re-routed channel if OPAMP3 is in power down mode. Otherwise, channel 13 is connected to OPAMP3 output and routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. (Note: OPAMP3 is available on STM32L1 Cat.4 only). */

  982. /**

  983.   * @}

  984.   */

  985. 

  986. /** @defgroup ADC_LL_EC_CHANNEL_ROUTING_SELECTION  Channel - Routing selection

  987.   * @{

  988.   */

  989. #define LL_ADC_CHANNEL_ROUTING_DEFAULT     0x00000000U  /*!< ADC channel routing default: slow channel */

  990. #define LL_ADC_CHANNEL_ROUTING_DIRECT      0x00000001U  /*!< ADC channel routing direct: fast channel. */

  991. /**

  992.   * @}

  993.   */

  994. #endif

  995. 

  996. /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number

  997.   * @{

  998.   */

  999. #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */

  1000. /**

  1001.   * @}

  1002.   */

  1003. 

  1004. /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels

  1005.   * @{

  1006.   */

  1007. #define LL_ADC_AWD_DISABLE                 0x00000000U                                                                                   /*!< ADC analog watchdog monitoring disabled */

  1008. #define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                             ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */

  1009. #define LL_ADC_AWD_ALL_CHANNELS_INJ        (                                            ADC_CR1_JAWDEN                                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */

  1010. #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (                                            ADC_CR1_JAWDEN | ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */

  1011. #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */

  1012. #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */

  1013. #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */

  1014. #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */

  1015. #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */

  1016. #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */

  1017. #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */

  1018. #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */

  1019. #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */

  1020. #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */

  1021. #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */

  1022. #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */

  1023. #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */

  1024. #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */

  1025. #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */

  1026. #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */

  1027. #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */

  1028. #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */

  1029. #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */

  1030. #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */

  1031. #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */

  1032. #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */

  1033. #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */

  1034. #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */

  1035. #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */

  1036. #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */

  1037. #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */

  1038. #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */

  1039. #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */

  1040. #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */

  1041. #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */

  1042. #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */

  1043. #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */

  1044. #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */

  1045. #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */

  1046. #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */

  1047. #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */

  1048. #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */

  1049. #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */

  1050. #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */

  1051. #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */

  1052. #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */

  1053. #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */

  1054. #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */

  1055. #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */

  1056. #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */

  1057. #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */

  1058. #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */

  1059. #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */

  1060. #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */

  1061. #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */

  1062. #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */

  1063. #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */

  1064. #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */

  1065. #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */

  1066. #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */

  1067. #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */

  1068. #define LL_ADC_AWD_CHANNEL_19_REG          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */

  1069. #define LL_ADC_AWD_CHANNEL_19_INJ          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */

  1070. #define LL_ADC_AWD_CHANNEL_19_REG_INJ      ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */

  1071. #define LL_ADC_AWD_CHANNEL_20_REG          ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group regular only */

  1072. #define LL_ADC_AWD_CHANNEL_20_INJ          ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group injected only */

  1073. #define LL_ADC_AWD_CHANNEL_20_REG_INJ      ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by either group regular or injected */

  1074. #define LL_ADC_AWD_CHANNEL_21_REG          ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group regular only */

  1075. #define LL_ADC_AWD_CHANNEL_21_INJ          ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group injected only */

  1076. #define LL_ADC_AWD_CHANNEL_21_REG_INJ      ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by either group regular or injected */

  1077. #define LL_ADC_AWD_CHANNEL_22_REG          ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group regular only */

  1078. #define LL_ADC_AWD_CHANNEL_22_INJ          ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group injected only */

  1079. #define LL_ADC_AWD_CHANNEL_22_REG_INJ      ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by either group regular or injected */

  1080. #define LL_ADC_AWD_CHANNEL_23_REG          ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group regular only */

  1081. #define LL_ADC_AWD_CHANNEL_23_INJ          ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group injected only */

  1082. #define LL_ADC_AWD_CHANNEL_23_REG_INJ      ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by either group regular or injected */

  1083. #define LL_ADC_AWD_CHANNEL_24_REG          ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group regular only */

  1084. #define LL_ADC_AWD_CHANNEL_24_INJ          ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group injected only */

  1085. #define LL_ADC_AWD_CHANNEL_24_REG_INJ      ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by either group regular or injected */

  1086. #define LL_ADC_AWD_CHANNEL_25_REG          ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group regular only */

  1087. #define LL_ADC_AWD_CHANNEL_25_INJ          ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group injected only */

  1088. #define LL_ADC_AWD_CHANNEL_25_REG_INJ      ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by either group regular or injected */

  1089. #define LL_ADC_AWD_CHANNEL_26_REG          ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group regular only */

  1090. #define LL_ADC_AWD_CHANNEL_26_INJ          ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group injected only */

  1091. #define LL_ADC_AWD_CHANNEL_26_REG_INJ      ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by either group regular or injected */

  1092. #if defined(ADC_SMPR0_SMP31)

  1093. #define LL_ADC_AWD_CHANNEL_27_REG          ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1094. #define LL_ADC_AWD_CHANNEL_27_INJ          ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1095. #define LL_ADC_AWD_CHANNEL_27_REG_INJ      ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1096. #define LL_ADC_AWD_CHANNEL_28_REG          ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1097. #define LL_ADC_AWD_CHANNEL_28_INJ          ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1098. #define LL_ADC_AWD_CHANNEL_28_REG_INJ      ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1099. #define LL_ADC_AWD_CHANNEL_29_REG          ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1100. #define LL_ADC_AWD_CHANNEL_29_INJ          ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1101. #define LL_ADC_AWD_CHANNEL_29_REG_INJ      ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1102. #define LL_ADC_AWD_CHANNEL_30_REG          ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1103. #define LL_ADC_AWD_CHANNEL_30_INJ          ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1104. #define LL_ADC_AWD_CHANNEL_30_REG_INJ      ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1105. #define LL_ADC_AWD_CHANNEL_31_REG          ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1106. #define LL_ADC_AWD_CHANNEL_31_INJ          ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1107. #define LL_ADC_AWD_CHANNEL_31_REG_INJ      ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */

  1108. #endif /* ADC_SMPR0_SMP31 */

  1109. #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only. Channel common to both bank A and bank B. */

  1110. #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only. Channel common to both bank A and bank B. */

  1111. #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected. Channel common to both bank A and bank B. */

  1112. #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. Channel common to both bank A and bank B. */

  1113. #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. Channel common to both bank A and bank B. */

  1114. #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. Channel common to both bank A and bank B. */

  1115. #define LL_ADC_AWD_CH_VCOMP_REG            ((LL_ADC_CHANNEL_VCOMP      & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */

  1116. #define LL_ADC_AWD_CH_VCOMP_INJ            ((LL_ADC_CHANNEL_VCOMP      & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */

  1117. #define LL_ADC_AWD_CH_VCOMP_REG_INJ        ((LL_ADC_CHANNEL_VCOMP      & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */

  1118. #if defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) || defined (OPAMP_CSR_OPA3PD)

  1119. #define LL_ADC_AWD_CH_VOPAMP1_REG          ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1120. #define LL_ADC_AWD_CH_VOPAMP1_INJ          ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1121. #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1122. #define LL_ADC_AWD_CH_VOPAMP2_REG          ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1123. #define LL_ADC_AWD_CH_VOPAMP2_INJ          ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1124. #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1125. #if defined(OPAMP_CSR_OPA3PD)

  1126. #define LL_ADC_AWD_CH_VOPAMP3_REG          ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1127. #define LL_ADC_AWD_CH_VOPAMP3_INJ          ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1128. #define LL_ADC_AWD_CH_VOPAMP3_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */

  1129. #endif /* OPAMP_CSR_OPA3PD */

  1130. #endif /* OPAMP_CSR_OPA1PD || OPAMP_CSR_OPA2PD || OPAMP_CSR_OPA3PD */

  1131. /**

  1132.   * @}

  1133.   */

  1134. 

  1135. /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds

  1136.   * @{

  1137.   */

  1138. #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */

  1139. #define LL_ADC_AWD_THRESHOLD_LOW           (ADC_AWD_TR1_LOW_REGOFFSET)  /*!< ADC analog watchdog threshold low */

  1140. /**

  1141.   * @}

  1142.   */

  1143. 

  1144. 

  1145. /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays

  1146.   * @note   Only ADC IP HW delays are defined in ADC LL driver driver,

  1147.   *         not timeout values.

  1148.   *         For details on delays values, refer to descriptions in source code

  1149.   *         above each literal definition.

  1150.   * @{

  1151.   */

  1152. 

  1153. /* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */

  1154. /*       not timeout values.                                                  */

  1155. /*       Timeout values for ADC operations are dependent to device clock      */

  1156. /*       configuration (system clock versus ADC clock),                       */

  1157. /*       and therefore must be defined in user application.                   */

  1158. /*       Indications for estimation of ADC timeout delays, for this           */

  1159. /*       STM32 serie:                                                         */

  1160. /*       - ADC enable time: maximum delay is 3.5us                            */

  1161. /*         (refer to device datasheet, parameter "tSTAB")                     */

  1162. /*       - ADC conversion time: duration depending on ADC clock and ADC       */

  1163. /*         configuration.                                                     */

  1164. /*         (refer to device reference manual, section "Timing")               */

  1165. 

  1166. /* Delay for internal voltage reference stabilization time.                   */

  1167. /* Delay set to maximum value (refer to device datasheet,                     */

  1168. /* parameter "TADC_BUF").                                                     */

  1169. /* Unit: us                                                                   */

  1170. #define LL_ADC_DELAY_VREFINT_STAB_US       (  10U)  /*!< Delay for internal voltage reference stabilization time */

  1171. 

  1172. /* Delay for temperature sensor stabilization time.                           */

  1173. /* Literal set to maximum value (refer to device datasheet,                   */

  1174. /* parameter "tSTART").                                                       */

  1175. /* Unit: us                                                                   */

  1176. #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (  10U)  /*!< Delay for internal voltage reference stabilization time */

  1177. 

  1178. /**

  1179.   * @}

  1180.   */

  1181. 

  1182. /**

  1183.   * @}

  1184.   */

  1185. 

  1186. 

  1187. /* Exported macro ------------------------------------------------------------*/

  1188. /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros

  1189.   * @{

  1190.   */

  1191. 

  1192. /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros

  1193.   * @{

  1194.   */

  1195. 

  1196. /**

  1197.   * @brief  Write a value in ADC register

  1198.   * @param  __INSTANCE__ ADC Instance

  1199.   * @param  __REG__ Register to be written

  1200.   * @param  __VALUE__ Value to be written in the register

  1201.   * @retval None

  1202.   */

  1203. #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

  1204. 

  1205. /**

  1206.   * @brief  Read a value in ADC register

  1207.   * @param  __INSTANCE__ ADC Instance

  1208.   * @param  __REG__ Register to be read

  1209.   * @retval Register value

  1210.   */

  1211. #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

  1212. /**

  1213.   * @}

  1214.   */

  1215. 

  1216. /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro

  1217.   * @{

  1218.   */

  1219. 

  1220. /**

  1221.   * @brief  Helper macro to get ADC channel number in decimal format

  1222.   *         from literals LL_ADC_CHANNEL_x.

  1223.   * @note   Example:

  1224.   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)

  1225.   *           will return decimal number "4".

  1226.   * @note   The input can be a value from functions where a channel

  1227.   *         number is returned, either defined with number

  1228.   *         or with bitfield (only one bit must be set).

  1229.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1230.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  1231.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  1232.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  1233.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  1234.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  1235.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  1236.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  1237.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  1238.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  1239.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  1240.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  1241.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  1242.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  1243.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  1244.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  1245.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  1246.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  1247.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  1248.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  1249.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  1250.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  1251.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  1252.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  1253.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  1254.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  1255.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  1256.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  1257.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  1258.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  1259.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  1260.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  1261.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  1262.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)

  1263.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)

  1264.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)

  1265.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  1266.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  1267.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  1268.   *

  1269.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  1270.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  1271.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  1272.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  1273.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  1274.   * @retval Value between Min_Data=0 and Max_Data=18

  1275.   */

  1276. #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \

  1277.   (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)

  1278. 

  1279. /**

  1280.   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x

  1281.   *         from number in decimal format.

  1282.   * @note   Example:

  1283.   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)

  1284.   *           will return a data equivalent to "LL_ADC_CHANNEL_4".

  1285.   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18

  1286.   * @retval Returned value can be one of the following values:

  1287.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  1288.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  1289.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  1290.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  1291.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  1292.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  1293.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  1294.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  1295.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  1296.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  1297.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  1298.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  1299.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  1300.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  1301.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  1302.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  1303.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  1304.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  1305.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  1306.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  1307.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  1308.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  1309.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  1310.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  1311.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  1312.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  1313.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  1314.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  1315.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  1316.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  1317.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  1318.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  1319.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)(6)

  1320.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)

  1321.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)(6)

  1322.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  1323.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  1324.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  1325.   *

  1326.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  1327.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  1328.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  1329.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  1330.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n

  1331.   *         (6) For ADC channel read back from ADC register,

  1332.   *             comparison with internal channel parameter to be done

  1333.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1334.   */

  1335. #if defined(ADC_SMPR0_SMP31)

  1336. #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                                  \

  1337.   (((__DECIMAL_NB__) <= 9U)                                                                                             \

  1338.     ? (                                                                                                                 \

  1339.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |                \

  1340.        (ADC_SMPR3_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))                 \

  1341.       )                                                                                                                 \

  1342.       :                                                                                                                 \

  1343.       (((__DECIMAL_NB__) <= 19U)                                                                                        \

  1344.         ? (                                                                                                             \

  1345.            ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |            \

  1346.            (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))      \

  1347.           )                                                                                                             \

  1348.           :                                                                                                             \

  1349.           (((__DECIMAL_NB__) <= 28U)                                                                                    \

  1350.             ? (                                                                                                         \

  1351.                ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \

  1352.                (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \

  1353.               )                                                                                                         \

  1354.               :                                                                                                         \

  1355.               (                                                                                                         \

  1356.                ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \

  1357.                (ADC_SMPR0_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 30U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \

  1358.               )                                                                                                         \

  1359.           )                                                                                                             \

  1360.       )                                                                                                                 \

  1361.   )

  1362. #else

  1363. #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                                  \

  1364.   (((__DECIMAL_NB__) <= 9U)                                                                                             \

  1365.     ? (                                                                                                                 \

  1366.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |                \

  1367.        (ADC_SMPR3_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))                 \

  1368.       )                                                                                                                 \

  1369.       :                                                                                                                 \

  1370.       (((__DECIMAL_NB__) <= 19U)                                                                                        \

  1371.         ? (                                                                                                             \

  1372.            ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |            \

  1373.            (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))      \

  1374.           )                                                                                                             \

  1375.           :                                                                                                             \

  1376.           (                                                                                                             \

  1377.            ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |            \

  1378.            (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))      \

  1379.           )                                                                                                             \

  1380.       )                                                                                                                 \

  1381.   )

  1382. #endif /* ADC_SMPR0_SMP31 */

  1383. 

  1384. /**

  1385.   * @brief  Helper macro to determine whether the selected channel

  1386.   *         corresponds to literal definitions of driver.

  1387.   * @note   The different literal definitions of ADC channels are:

  1388.   *         - ADC internal channel:

  1389.   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...

  1390.   *         - ADC external channel (channel connected to a GPIO pin):

  1391.   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...

  1392.   * @note   The channel parameter must be a value defined from literal

  1393.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1394.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1395.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),

  1396.   *         must not be a value from functions where a channel number is

  1397.   *         returned from ADC registers,

  1398.   *         because internal and external channels share the same channel

  1399.   *         number in ADC registers. The differentiation is made only with

  1400.   *         parameters definitions of driver.

  1401.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1402.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  1403.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  1404.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  1405.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  1406.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  1407.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  1408.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  1409.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  1410.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  1411.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  1412.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  1413.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  1414.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  1415.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  1416.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  1417.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  1418.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  1419.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  1420.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  1421.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  1422.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  1423.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  1424.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  1425.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  1426.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  1427.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  1428.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  1429.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  1430.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  1431.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  1432.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  1433.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  1434.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)

  1435.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)

  1436.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)

  1437.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  1438.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  1439.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  1440.   *

  1441.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  1442.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  1443.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  1444.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  1445.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  1446.   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).

  1447.   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

  1448.   */

  1449. #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \

  1450.   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)

  1451. 

  1452. /**

  1453.   * @brief  Helper macro to convert a channel defined from parameter

  1454.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1455.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1456.   *         to its equivalent parameter definition of a ADC external channel

  1457.   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

  1458.   * @note   The channel parameter can be, additionally to a value

  1459.   *         defined from parameter definition of a ADC internal channel

  1460.   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1461.   *         a value defined from parameter definition of

  1462.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1463.   *         or a value from functions where a channel number is returned

  1464.   *         from ADC registers.

  1465.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1466.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  1467.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  1468.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  1469.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  1470.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  1471.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  1472.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  1473.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  1474.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  1475.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  1476.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  1477.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  1478.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  1479.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  1480.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  1481.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  1482.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  1483.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  1484.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  1485.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  1486.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  1487.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  1488.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  1489.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  1490.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  1491.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  1492.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  1493.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  1494.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  1495.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  1496.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  1497.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  1498.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)

  1499.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)

  1500.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)

  1501.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  1502.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  1503.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  1504.   *

  1505.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  1506.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  1507.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  1508.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  1509.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  1510.   * @retval Returned value can be one of the following values:

  1511.   *         @arg @ref LL_ADC_CHANNEL_0

  1512.   *         @arg @ref LL_ADC_CHANNEL_1

  1513.   *         @arg @ref LL_ADC_CHANNEL_2

  1514.   *         @arg @ref LL_ADC_CHANNEL_3

  1515.   *         @arg @ref LL_ADC_CHANNEL_4

  1516.   *         @arg @ref LL_ADC_CHANNEL_5

  1517.   *         @arg @ref LL_ADC_CHANNEL_6

  1518.   *         @arg @ref LL_ADC_CHANNEL_7

  1519.   *         @arg @ref LL_ADC_CHANNEL_8

  1520.   *         @arg @ref LL_ADC_CHANNEL_9

  1521.   *         @arg @ref LL_ADC_CHANNEL_10

  1522.   *         @arg @ref LL_ADC_CHANNEL_11

  1523.   *         @arg @ref LL_ADC_CHANNEL_12

  1524.   *         @arg @ref LL_ADC_CHANNEL_13

  1525.   *         @arg @ref LL_ADC_CHANNEL_14

  1526.   *         @arg @ref LL_ADC_CHANNEL_15

  1527.   *         @arg @ref LL_ADC_CHANNEL_16

  1528.   *         @arg @ref LL_ADC_CHANNEL_17

  1529.   *         @arg @ref LL_ADC_CHANNEL_18

  1530.   */

  1531. #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \

  1532.   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  1533. 

  1534. /**

  1535.   * @brief  Helper macro to determine whether the internal channel

  1536.   *         selected is available on the ADC instance selected.

  1537.   * @note   The channel parameter must be a value defined from parameter

  1538.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1539.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1540.   *         must not be a value defined from parameter definition of

  1541.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1542.   *         or a value from functions where a channel number is

  1543.   *         returned from ADC registers,

  1544.   *         because internal and external channels share the same channel

  1545.   *         number in ADC registers. The differentiation is made only with

  1546.   *         parameters definitions of driver.

  1547.   * @param  __ADC_INSTANCE__ ADC instance

  1548.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1549.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)

  1550.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)

  1551.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)

  1552.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  1553.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  1554.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  1555.   *

  1556.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  1557.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  1558.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  1559.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  1560.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  1561.   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.

  1562.   *         Value "1" if the internal channel selected is available on the ADC instance selected.

  1563.   */

  1564. #if defined (OPAMP_CSR_OPA3PD)

  1565. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

  1566.   (                                                                            \

  1567.     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \

  1568.     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \

  1569.     ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP)      ||                            \

  1570.     ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)    ||                            \

  1571.     ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)    ||                            \

  1572.     ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3)                                  \

  1573.   )

  1574. #elif defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD)

  1575. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

  1576.   (                                                                            \

  1577.     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \

  1578.     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \

  1579.     ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP)      ||                            \

  1580.     ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)    ||                            \

  1581.     ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)                                  \

  1582.   )

  1583. #else

  1584. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

  1585.   (                                                                            \

  1586.     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \

  1587.     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \

  1588.     ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP)                                    \

  1589.   )

  1590. #endif

  1591. 

  1592. /**

  1593.   * @brief  Helper macro to define ADC analog watchdog parameter:

  1594.   *         define a single channel to monitor with analog watchdog

  1595.   *         from sequencer channel and groups definition.

  1596.   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().

  1597.   *         Example:

  1598.   *           LL_ADC_SetAnalogWDMonitChannels(

  1599.   *             ADC1, LL_ADC_AWD1,

  1600.   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))

  1601.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1602.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  1603.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  1604.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  1605.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  1606.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  1607.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  1608.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  1609.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  1610.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  1611.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  1612.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  1613.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  1614.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  1615.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  1616.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  1617.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  1618.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  1619.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  1620.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  1621.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  1622.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  1623.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  1624.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  1625.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  1626.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  1627.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  1628.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  1629.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  1630.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  1631.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  1632.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  1633.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  1634.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)(6)

  1635.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)

  1636.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)(6)

  1637.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  1638.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  1639.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  1640.   *

  1641.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  1642.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  1643.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  1644.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  1645.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n

  1646.   *         (6) For ADC channel read back from ADC register,

  1647.   *             comparison with internal channel parameter to be done

  1648.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1649.   * @param  __GROUP__ This parameter can be one of the following values:

  1650.   *         @arg @ref LL_ADC_GROUP_REGULAR

  1651.   *         @arg @ref LL_ADC_GROUP_INJECTED

  1652.   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED

  1653.   * @retval Returned value can be one of the following values:

  1654.   *         @arg @ref LL_ADC_AWD_DISABLE

  1655.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG

  1656.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ

  1657.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  1658.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (2)

  1659.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (2)

  1660.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ       (2)

  1661.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (2)

  1662.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (2)

  1663.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ       (2)

  1664.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (2)

  1665.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (2)

  1666.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ       (2)

  1667.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (2)

  1668.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (2)

  1669.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ       (2)

  1670.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (1)

  1671.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (1)

  1672.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ       (1)

  1673.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (1)

  1674.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (1)

  1675.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ       (1)

  1676.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (2)

  1677.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (2)

  1678.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ       (2)

  1679.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (2)

  1680.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (2)

  1681.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ       (2)

  1682.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (2)

  1683.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (2)

  1684.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ       (2)

  1685.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (2)

  1686.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (2)

  1687.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ       (2)

  1688.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (2)

  1689.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (2)

  1690.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ      (2)

  1691.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (2)

  1692.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (2)

  1693.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ      (2)

  1694.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (2)

  1695.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (2)

  1696.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ      (2)

  1697.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (3)

  1698.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (3)

  1699.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ      (3)

  1700.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (3)

  1701.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (3)

  1702.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ      (3)

  1703.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (3)

  1704.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (3)

  1705.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ      (3)

  1706.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (3)

  1707.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (3)

  1708.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ      (3)

  1709.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (3)

  1710.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (3)

  1711.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ      (3)

  1712.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (3)

  1713.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (3)

  1714.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ      (3)

  1715.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (3)

  1716.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (3)

  1717.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ      (3)

  1718.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (3)

  1719.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_INJ          (3)

  1720.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ      (3)

  1721.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (3)

  1722.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_INJ          (3)

  1723.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ      (3)

  1724.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)

  1725.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_INJ          (1)

  1726.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ      (1)

  1727.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG          (1)

  1728.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_INJ          (1)

  1729.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ      (1)

  1730.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG          (1)

  1731.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_INJ          (1)

  1732.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ      (1)

  1733.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG          (1)

  1734.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_INJ          (1)

  1735.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ      (1)

  1736.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG          (3)

  1737.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_INJ          (3)

  1738.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ      (3)

  1739.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG          (3)(4)

  1740.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_INJ          (3)(4)

  1741.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ      (3)(4)

  1742.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG          (3)(4)

  1743.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_INJ          (3)(4)

  1744.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ      (3)(4)

  1745.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG          (3)(4)

  1746.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_INJ          (3)(4)

  1747.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ      (3)(4)

  1748.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG          (3)(4)

  1749.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_INJ          (3)(4)

  1750.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ      (3)(4)

  1751.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG          (3)(4)

  1752.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_INJ          (3)(4)

  1753.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ      (3)(4)

  1754.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (3)

  1755.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (3)

  1756.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (3)

  1757.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (3)

  1758.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (3)

  1759.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (3)

  1760.   *         @arg @ref LL_ADC_AWD_CH_VCOMP_REG            (3)

  1761.   *         @arg @ref LL_ADC_AWD_CH_VCOMP_INJ            (3)

  1762.   *         @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ        (3)

  1763.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (3)(5)

  1764.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (3)(5)

  1765.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ      (3)(5)

  1766.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (3)(5)

  1767.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (3)(5)

  1768.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ      (3)(5)

  1769.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG          (3)(5)

  1770.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ          (3)(5)

  1771.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ      (3)(5)

  1772.   *

  1773.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  1774.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  1775.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  1776.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  1777.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  1778.   */

  1779. #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \

  1780.   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \

  1781.     ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \

  1782.       :                                                                                                   \

  1783.       ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \

  1784.        ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \

  1785.          :                                                                                                \

  1786.          (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \

  1787.   )

  1788. 

  1789. /**

  1790.   * @brief  Helper macro to set the value of ADC analog watchdog threshold high

  1791.   *         or low in function of ADC resolution, when ADC resolution is

  1792.   *         different of 12 bits.

  1793.   * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().

  1794.   *         Example, with a ADC resolution of 8 bits, to set the value of

  1795.   *         analog watchdog threshold high (on 8 bits):

  1796.   *           LL_ADC_SetAnalogWDThresholds

  1797.   *            (< ADCx param >,

  1798.   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)

  1799.   *            );

  1800.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1801.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1802.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1803.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1804.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1805.   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF

  1806.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  1807.   */

  1808. #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \

  1809.   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))

  1810. 

  1811. /**

  1812.   * @brief  Helper macro to get the value of ADC analog watchdog threshold high

  1813.   *         or low in function of ADC resolution, when ADC resolution is

  1814.   *         different of 12 bits.

  1815.   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().

  1816.   *         Example, with a ADC resolution of 8 bits, to get the value of

  1817.   *         analog watchdog threshold high (on 8 bits):

  1818.   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION

  1819.   *            (LL_ADC_RESOLUTION_8B,

  1820.   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)

  1821.   *            );

  1822.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1823.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1824.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1825.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1826.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1827.   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF

  1828.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  1829.   */

  1830. #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \

  1831.   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))

  1832. 

  1833. /**

  1834.   * @brief  Helper macro to select the ADC common instance

  1835.   *         to which is belonging the selected ADC instance.

  1836.   * @note   ADC common register instance can be used for:

  1837.   *         - Set parameters common to several ADC instances

  1838.   *         - Multimode (for devices with several ADC instances)

  1839.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  1840.   * @param  __ADCx__ ADC instance

  1841.   * @retval ADC common register instance

  1842.   */

  1843. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  1844.   (ADC1_COMMON)

  1845. 

  1846. /**

  1847.   * @brief  Helper macro to check if all ADC instances sharing the same

  1848.   *         ADC common instance are disabled.

  1849.   * @note   This check is required by functions with setting conditioned to

  1850.   *         ADC state:

  1851.   *         All ADC instances of the ADC common group must be disabled.

  1852.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  1853.   * @note   On devices with only 1 ADC common instance, parameter of this macro

  1854.   *         is useless and can be ignored (parameter kept for compatibility

  1855.   *         with devices featuring several ADC common instances).

  1856.   * @param  __ADCXY_COMMON__ ADC common instance

  1857.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  1858.   * @retval Value "0" if all ADC instances sharing the same ADC common instance

  1859.   *         are disabled.

  1860.   *         Value "1" if at least one ADC instance sharing the same ADC common instance

  1861.   *         is enabled.

  1862.   */

  1863. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  1864.   LL_ADC_IsEnabled(ADC1)

  1865. 

  1866. /**

  1867.   * @brief  Helper macro to define the ADC conversion data full-scale digital

  1868.   *         value corresponding to the selected ADC resolution.

  1869.   * @note   ADC conversion data full-scale corresponds to voltage range

  1870.   *         determined by analog voltage references Vref+ and Vref-

  1871.   *         (refer to reference manual).

  1872.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1873.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1874.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1875.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1876.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1877.   * @retval ADC conversion data equivalent voltage value (unit: mVolt)

  1878.   */

  1879. #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \

  1880.   (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))

  1881. 

  1882. /**

  1883.   * @brief  Helper macro to convert the ADC conversion data from

  1884.   *         a resolution to another resolution.

  1885.   * @param  __DATA__ ADC conversion data to be converted

  1886.   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted

  1887.   *         This parameter can be one of the following values:

  1888.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1889.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1890.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1891.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1892.   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion

  1893.   *         This parameter can be one of the following values:

  1894.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1895.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1896.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1897.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1898.   * @retval ADC conversion data to the requested resolution

  1899.   */

  1900. #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \

  1901.   (((__DATA__)                                                                 \

  1902.     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))     \

  1903.    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))        \

  1904.   )

  1905. 

  1906. /**

  1907.   * @brief  Helper macro to calculate the voltage (unit: mVolt)

  1908.   *         corresponding to a ADC conversion data (unit: digital value).

  1909.   * @note   Analog reference voltage (Vref+) must be either known from

  1910.   *         user board environment or can be calculated using ADC measurement

  1911.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  1912.   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)

  1913.   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)

  1914.   *                       (unit: digital value).

  1915.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1916.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1917.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1918.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1919.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1920.   * @retval ADC conversion data equivalent voltage value (unit: mVolt)

  1921.   */

  1922. #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\

  1923.                                       __ADC_DATA__,\

  1924.                                       __ADC_RESOLUTION__)                      \

  1925.   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \

  1926.    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \

  1927.   )

  1928. 

  1929. /**

  1930.   * @brief  Helper macro to calculate analog reference voltage (Vref+)

  1931.   *         (unit: mVolt) from ADC conversion data of internal voltage

  1932.   *         reference VrefInt.

  1933.   * @note   Computation is using VrefInt calibration value

  1934.   *         stored in system memory for each device during production.

  1935.   * @note   This voltage depends on user board environment: voltage level

  1936.   *         connected to pin Vref+.

  1937.   *         On devices with small package, the pin Vref+ is not present

  1938.   *         and internally bonded to pin Vdda.

  1939.   * @note   On this STM32 serie, calibration data of internal voltage reference

  1940.   *         VrefInt corresponds to a resolution of 12 bits,

  1941.   *         this is the recommended ADC resolution to convert voltage of

  1942.   *         internal voltage reference VrefInt.

  1943.   *         Otherwise, this macro performs the processing to scale

  1944.   *         ADC conversion data to 12 bits.

  1945.   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)

  1946.   *         of internal voltage reference VrefInt (unit: digital value).

  1947.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1948.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1949.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1950.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1951.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1952.   * @retval Analog reference voltage (unit: mV)

  1953.   */

  1954. #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\

  1955.                                          __ADC_RESOLUTION__)                   \

  1956.   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \

  1957.     / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \

  1958.                                        (__ADC_RESOLUTION__),                   \

  1959.                                        LL_ADC_RESOLUTION_12B)                  \

  1960.   )

  1961. 

  1962. /**

  1963.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  1964.   *         from ADC conversion data of internal temperature sensor.

  1965.   * @note   Computation is using temperature sensor calibration values

  1966.   *         stored in system memory for each device during production.

  1967.   * @note   Calculation formula:

  1968.   *           Temperature = ((TS_ADC_DATA - TS_CAL1)

  1969.   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))

  1970.   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP

  1971.   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC

  1972.   *                Avg_Slope = (TS_CAL2 - TS_CAL1)

  1973.   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)

  1974.   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature

  1975.   *                            TEMP_DEGC_CAL1 (calibrated in factory)

  1976.   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature

  1977.   *                            TEMP_DEGC_CAL2 (calibrated in factory)

  1978.   *         Caution: Calculation relevancy under reserve that calibration

  1979.   *                  parameters are correct (address and data).

  1980.   *                  To calculate temperature using temperature sensor

  1981.   *                  datasheet typical values (generic values less, therefore

  1982.   *                  less accurate than calibrated values),

  1983.   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().

  1984.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  1985.   *         defined as it impacts the ADC LSB equivalent voltage.

  1986.   * @note   Analog reference voltage (Vref+) must be either known from

  1987.   *         user board environment or can be calculated using ADC measurement

  1988.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  1989.   * @note   On this STM32 serie, calibration data of temperature sensor

  1990.   *         corresponds to a resolution of 12 bits,

  1991.   *         this is the recommended ADC resolution to convert voltage of

  1992.   *         temperature sensor.

  1993.   *         Otherwise, this macro performs the processing to scale

  1994.   *         ADC conversion data to 12 bits.

  1995.   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)

  1996.   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal

  1997.   *                                 temperature sensor (unit: digital value).

  1998.   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature

  1999.   *                                 sensor voltage has been measured.

  2000.   *         This parameter can be one of the following values:

  2001.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2002.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2003.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2004.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2005.   * @retval Temperature (unit: degree Celsius)

  2006.   */

  2007. #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\

  2008.                                   __TEMPSENSOR_ADC_DATA__,\

  2009.                                   __ADC_RESOLUTION__)                              \

  2010.   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \

  2011.                                                     (__ADC_RESOLUTION__),          \

  2012.                                                     LL_ADC_RESOLUTION_12B)         \

  2013.                    * (__VREFANALOG_VOLTAGE__))                                     \

  2014.                   / TEMPSENSOR_CAL_VREFANALOG)                                     \

  2015.         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \

  2016.      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \

  2017.     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \

  2018.    ) + TEMPSENSOR_CAL1_TEMP                                                        \

  2019.   )

  2020. 

  2021. /**

  2022.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  2023.   *         from ADC conversion data of internal temperature sensor.

  2024.   * @note   Computation is using temperature sensor typical values

  2025.   *         (refer to device datasheet).

  2026.   * @note   Calculation formula:

  2027.   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)

  2028.   *                         / Avg_Slope + CALx_TEMP

  2029.   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC

  2030.   *                                   (unit: digital value)

  2031.   *                Avg_Slope        = temperature sensor slope

  2032.   *                                   (unit: uV/Degree Celsius)

  2033.   *                TS_TYP_CALx_VOLT = temperature sensor digital value at

  2034.   *                                   temperature CALx_TEMP (unit: mV)

  2035.   *         Caution: Calculation relevancy under reserve the temperature sensor

  2036.   *                  of the current device has characteristics in line with

  2037.   *                  datasheet typical values.

  2038.   *                  If temperature sensor calibration values are available on

  2039.   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),

  2040.   *                  temperature calculation will be more accurate using

  2041.   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().

  2042.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  2043.   *         defined as it impacts the ADC LSB equivalent voltage.

  2044.   * @note   Analog reference voltage (Vref+) must be either known from

  2045.   *         user board environment or can be calculated using ADC measurement

  2046.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  2047.   * @note   ADC measurement data must correspond to a resolution of 12bits

  2048.   *         (full scale digital value 4095). If not the case, the data must be

  2049.   *         preliminarily rescaled to an equivalent resolution of 12 bits.

  2050.   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).

  2051.   *                                       On STM32L1, refer to device datasheet parameter "Avg_Slope".

  2052.   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).

  2053.   *                                       On STM32L1, refer to device datasheet parameter "V110" (corresponding to TS_CAL2).

  2054.   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)

  2055.   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)

  2056.   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).

  2057.   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.

  2058.   *         This parameter can be one of the following values:

  2059.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2060.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2061.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2062.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2063.   * @retval Temperature (unit: degree Celsius)

  2064.   */

  2065. #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\

  2066.                                              __TEMPSENSOR_TYP_CALX_V__,\

  2067.                                              __TEMPSENSOR_CALX_TEMP__,\

  2068.                                              __VREFANALOG_VOLTAGE__,\

  2069.                                              __TEMPSENSOR_ADC_DATA__,\

  2070.                                              __ADC_RESOLUTION__)               \

  2071.   ((( (                                                                        \

  2072.        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \

  2073.                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \

  2074.                  * 1000)                                                       \

  2075.        -                                                                       \

  2076.        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \

  2077.                  * 1000)                                                       \

  2078.       )                                                                        \

  2079.     ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \

  2080.    ) + (__TEMPSENSOR_CALX_TEMP__)                                              \

  2081.   )

  2082. 

  2083. /**

  2084.   * @}

  2085.   */

  2086. 

  2087. /**

  2088.   * @}

  2089.   */

  2090. 

  2091. 

  2092. /* Exported functions --------------------------------------------------------*/

  2093. /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions

  2094.   * @{

  2095.   */

  2096. 

  2097. /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management

  2098.   * @{

  2099.   */

  2100. /* Note: LL ADC functions to set DMA transfer are located into sections of    */

  2101. /*       configuration of ADC instance, groups and multimode (if available):  */

  2102. /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */

  2103. 

  2104. /**

  2105.   * @brief  Function to help to configure DMA transfer from ADC: retrieve the

  2106.   *         ADC register address from ADC instance and a list of ADC registers

  2107.   *         intended to be used (most commonly) with DMA transfer.

  2108.   * @note   These ADC registers are data registers:

  2109.   *         when ADC conversion data is available in ADC data registers,

  2110.   *         ADC generates a DMA transfer request.

  2111.   * @note   This macro is intended to be used with LL DMA driver, refer to

  2112.   *         function "LL_DMA_ConfigAddresses()".

  2113.   *         Example:

  2114.   *           LL_DMA_ConfigAddresses(DMA1,

  2115.   *                                  LL_DMA_CHANNEL_1,

  2116.   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),

  2117.   *                                  (uint32_t)&< array or variable >,

  2118.   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

  2119.   * @note   For devices with several ADC: in multimode, some devices

  2120.   *         use a different data register outside of ADC instance scope

  2121.   *         (common data register). This macro manages this register difference,

  2122.   *         only ADC instance has to be set as parameter.

  2123.   * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr

  2124.   * @param  ADCx ADC instance

  2125.   * @param  Register This parameter can be one of the following values:

  2126.   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA

  2127.   * @retval ADC register address

  2128.   */

  2129. __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)

  2130. {

  2131.   /* Retrieve address of register DR */

  2132.   return (uint32_t)&(ADCx->DR);

  2133. }

  2134. 

  2135. /**

  2136.   * @}

  2137.   */

  2138. 

  2139. /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances

  2140.   * @{

  2141.   */

  2142. 

  2143. /**

  2144.   * @brief  Set parameter common to several ADC: Clock source and prescaler.

  2145.   * @note   On this STM32 serie, HSI RC oscillator is the only clock source for ADC.

  2146.   *         Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level.

  2147.   * @note   On this STM32 serie, some clock ratio constraints between ADC clock and APB clock

  2148.   *         must be respected:

  2149.   *         - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted.

  2150.   *         - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits.

  2151.   *         Refer to reference manual.

  2152.   * @rmtoll CCR      ADCPRE         LL_ADC_SetCommonClock

  2153.   * @param  ADCxy_COMMON ADC common instance

  2154.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2155.   * @param  CommonClock This parameter can be one of the following values:

  2156.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

  2157.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

  2158.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

  2159.   * @retval None

  2160.   */

  2161. __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)

  2162. {

  2163.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);

  2164. }

  2165. 

  2166. /**

  2167.   * @brief  Get parameter common to several ADC: Clock source and prescaler.

  2168.   * @rmtoll CCR      ADCPRE         LL_ADC_GetCommonClock

  2169.   * @param  ADCxy_COMMON ADC common instance

  2170.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2171.   * @retval Returned value can be one of the following values:

  2172.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

  2173.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

  2174.   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

  2175.   */

  2176. __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)

  2177. {

  2178.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));

  2179. }

  2180. 

  2181. /**

  2182.   * @brief  Set parameter common to several ADC: measurement path to internal

  2183.   *         channels (VrefInt, temperature sensor, ...).

  2184.   * @note   One or several values can be selected.

  2185.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2186.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2187.   * @note   Stabilization time of measurement path to internal channel:

  2188.   *         After enabling internal paths, before starting ADC conversion,

  2189.   *         a delay is required for internal voltage reference and

  2190.   *         temperature sensor stabilization time.

  2191.   *         Refer to device datasheet.

  2192.   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.

  2193.   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.

  2194.   * @note   ADC internal channel sampling time constraint:

  2195.   *         For ADC conversion of internal channels,

  2196.   *         a sampling time minimum value is required.

  2197.   *         Refer to device datasheet.

  2198.   * @rmtoll CCR      TSVREFE        LL_ADC_SetCommonPathInternalCh

  2199.   * @param  ADCxy_COMMON ADC common instance

  2200.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2201.   * @param  PathInternal This parameter can be a combination of the following values:

  2202.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2203.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2204.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2205.   * @retval None

  2206.   */

  2207. __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)

  2208. {

  2209.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE, PathInternal);

  2210. }

  2211. 

  2212. /**

  2213.   * @brief  Get parameter common to several ADC: measurement path to internal

  2214.   *         channels (VrefInt, temperature sensor, ...).

  2215.   * @note   One or several values can be selected.

  2216.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  2217.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  2218.   * @rmtoll CCR      TSVREFE        LL_ADC_GetCommonPathInternalCh

  2219.   * @param  ADCxy_COMMON ADC common instance

  2220.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  2221.   * @retval Returned value can be a combination of the following values:

  2222.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  2223.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  2224.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  2225.   */

  2226. __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)

  2227. {

  2228.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE));

  2229. }

  2230. 

  2231. /**

  2232.   * @}

  2233.   */

  2234. 

  2235. /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance

  2236.   * @{

  2237.   */

  2238. 

  2239. /**

  2240.   * @brief  Set ADC resolution.

  2241.   *         Refer to reference manual for alignments formats

  2242.   *         dependencies to ADC resolutions.

  2243.   * @rmtoll CR1      RES            LL_ADC_SetResolution

  2244.   * @param  ADCx ADC instance

  2245.   * @param  Resolution This parameter can be one of the following values:

  2246.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2247.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2248.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2249.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2250.   * @retval None

  2251.   */

  2252. __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)

  2253. {

  2254.   MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);

  2255. }

  2256. 

  2257. /**

  2258.   * @brief  Get ADC resolution.

  2259.   *         Refer to reference manual for alignments formats

  2260.   *         dependencies to ADC resolutions.

  2261.   * @rmtoll CR1      RES            LL_ADC_GetResolution

  2262.   * @param  ADCx ADC instance

  2263.   * @retval Returned value can be one of the following values:

  2264.   *         @arg @ref LL_ADC_RESOLUTION_12B

  2265.   *         @arg @ref LL_ADC_RESOLUTION_10B

  2266.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2267.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2268.   */

  2269. __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)

  2270. {

  2271.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));

  2272. }

  2273. 

  2274. /**

  2275.   * @brief  Set ADC conversion data alignment.

  2276.   * @note   Refer to reference manual for alignments formats

  2277.   *         dependencies to ADC resolutions.

  2278.   * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment

  2279.   * @param  ADCx ADC instance

  2280.   * @param  DataAlignment This parameter can be one of the following values:

  2281.   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT

  2282.   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT

  2283.   * @retval None

  2284.   */

  2285. __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)

  2286. {

  2287.   MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);

  2288. }

  2289. 

  2290. /**

  2291.   * @brief  Get ADC conversion data alignment.

  2292.   * @note   Refer to reference manual for alignments formats

  2293.   *         dependencies to ADC resolutions.

  2294.   * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment

  2295.   * @param  ADCx ADC instance

  2296.   * @retval Returned value can be one of the following values:

  2297.   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT

  2298.   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT

  2299.   */

  2300. __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)

  2301. {

  2302.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));

  2303. }

  2304. 

  2305. /**

  2306.   * @brief  Set ADC low power mode auto wait.

  2307.   * @note   Description of ADC low power modes:

  2308.   *         - ADC low power mode "auto wait": Dynamic low power mode,

  2309.   *           ADC conversions occurrences are limited to the minimum necessary

  2310.   *           in order to reduce power consumption.

  2311.   *           New ADC conversion starts only when the previous

  2312.   *           unitary conversion data (for ADC group regular)

  2313.   *           or previous sequence conversions data (for ADC group injected)

  2314.   *           has been retrieved by user software.

  2315.   *           In the meantime, ADC remains idle: does not performs any

  2316.   *           other conversion.

  2317.   *           This mode allows to automatically adapt the ADC conversions

  2318.   *           triggers to the speed of the software that reads the data.

  2319.   *           Moreover, this avoids risk of overrun for low frequency

  2320.   *           applications.

  2321.   *           How to use this low power mode:

  2322.   *           - Do not use with interruption or DMA since these modes

  2323.   *             have to clear immediately the EOC flag to free the

  2324.   *             IRQ vector sequencer.

  2325.   *           - Do use with polling: 1. Start conversion,

  2326.   *             2. Later on, when conversion data is needed: poll for end of

  2327.   *             conversion  to ensure that conversion is completed and

  2328.   *             retrieve ADC conversion data. This will trig another

  2329.   *             ADC conversion start.

  2330.   *         - ADC low power mode "auto power-off":

  2331.   *           refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff().

  2332.   * @note   With ADC low power mode "auto wait", the ADC conversion data read

  2333.   *         is corresponding to previous ADC conversion start, independently

  2334.   *         of delay during which ADC was idle.

  2335.   *         Therefore, the ADC conversion data may be outdated: does not

  2336.   *         correspond to the current voltage level on the selected

  2337.   *         ADC channel.

  2338.   * @rmtoll CR2      DELS           LL_ADC_SetLowPowerModeAutoWait

  2339.   * @param  ADCx ADC instance

  2340.   * @param  LowPowerModeAutoWait This parameter can be one of the following values:

  2341.   *         @arg @ref LL_ADC_LP_AUTOWAIT_NONE

  2342.   *         @arg @ref LL_ADC_LP_AUTOWAIT

  2343.   *         @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES

  2344.   *         @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES

  2345.   *         @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES

  2346.   *         @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES

  2347.   *         @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES

  2348.   *         @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES

  2349.   * @retval None

  2350.   */

  2351. __STATIC_INLINE void LL_ADC_SetLowPowerModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoWait)

  2352. {

  2353.   MODIFY_REG(ADCx->CR2, ADC_CR2_DELS, LowPowerModeAutoWait);

  2354. }

  2355. 

  2356. /**

  2357.   * @brief  Get ADC low power mode auto wait.

  2358.   * @note   Description of ADC low power modes:

  2359.   *         - ADC low power mode "auto wait": Dynamic low power mode,

  2360.   *           ADC conversions occurrences are limited to the minimum necessary

  2361.   *           in order to reduce power consumption.

  2362.   *           New ADC conversion starts only when the previous

  2363.   *           unitary conversion data (for ADC group regular)

  2364.   *           or previous sequence conversions data (for ADC group injected)

  2365.   *           has been retrieved by user software.

  2366.   *           In the meantime, ADC remains idle: does not performs any

  2367.   *           other conversion.

  2368.   *           This mode allows to automatically adapt the ADC conversions

  2369.   *           triggers to the speed of the software that reads the data.

  2370.   *           Moreover, this avoids risk of overrun for low frequency

  2371.   *           applications.

  2372.   *           How to use this low power mode:

  2373.   *           - Do not use with interruption or DMA since these modes

  2374.   *             have to clear immediately the EOC flag to free the

  2375.   *             IRQ vector sequencer.

  2376.   *           - Do use with polling: 1. Start conversion,

  2377.   *             2. Later on, when conversion data is needed: poll for end of

  2378.   *             conversion  to ensure that conversion is completed and

  2379.   *             retrieve ADC conversion data. This will trig another

  2380.   *             ADC conversion start.

  2381.   *         - ADC low power mode "auto power-off":

  2382.   *           refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff().

  2383.   * @note   With ADC low power mode "auto wait", the ADC conversion data read

  2384.   *         is corresponding to previous ADC conversion start, independently

  2385.   *         of delay during which ADC was idle.

  2386.   *         Therefore, the ADC conversion data may be outdated: does not

  2387.   *         correspond to the current voltage level on the selected

  2388.   *         ADC channel.

  2389.   * @rmtoll CR2      DELS           LL_ADC_GetLowPowerModeAutoWait

  2390.   * @param  ADCx ADC instance

  2391.   * @retval Returned value can be one of the following values:

  2392.   *         @arg @ref LL_ADC_LP_AUTOWAIT_NONE

  2393.   *         @arg @ref LL_ADC_LP_AUTOWAIT

  2394.   *         @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES

  2395.   *         @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES

  2396.   *         @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES

  2397.   *         @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES

  2398.   *         @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES

  2399.   *         @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES

  2400.   */

  2401. __STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoWait(ADC_TypeDef *ADCx)

  2402. {

  2403.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DELS));

  2404. }

  2405. 

  2406. /**

  2407.   * @brief  Set ADC low power mode auto power-off.

  2408.   * @note   Description of ADC low power modes:

  2409.   *         - ADC low power mode "auto wait":

  2410.   *           refer to function @ref LL_ADC_SetLowPowerModeAutoWait().

  2411.   *         - ADC low power mode "auto power-off":

  2412.   *           the ADC automatically powers-off after a conversion and

  2413.   *           automatically wakes up when a new conversion is triggered

  2414.   *           (with startup time between trigger and start of sampling).

  2415.   *           This feature can be combined with low power mode "auto wait".

  2416.   * @rmtoll CR1      PDI            LL_ADC_GetLowPowerModeAutoPowerOff\n

  2417.   *         CR1      PDD            LL_ADC_GetLowPowerModeAutoPowerOff

  2418.   * @param  ADCx ADC instance

  2419.   * @param  LowPowerModeAutoPowerOff This parameter can be one of the following values:

  2420.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE

  2421.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE

  2422.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE

  2423.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES

  2424.   * @retval None

  2425.   */

  2426. __STATIC_INLINE void LL_ADC_SetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoPowerOff)

  2427. {

  2428.   MODIFY_REG(ADCx->CR1, (ADC_CR1_PDI | ADC_CR1_PDD), LowPowerModeAutoPowerOff);

  2429. }

  2430. 

  2431. /**

  2432.   * @brief  Get ADC low power mode auto power-off.

  2433.   * @note   Description of ADC low power modes:

  2434.   *         - ADC low power mode "auto wait":

  2435.   *           refer to function @ref LL_ADC_SetLowPowerModeAutoWait().

  2436.   *         - ADC low power mode "auto power-off":

  2437.   *           the ADC automatically powers-off after a conversion and

  2438.   *           automatically wakes up when a new conversion is triggered

  2439.   *           (with startup time between trigger and start of sampling).

  2440.   *           This feature can be combined with low power mode "auto wait".

  2441.   * @rmtoll CR1      PDI            LL_ADC_GetLowPowerModeAutoPowerOff\n

  2442.   *         CR1      PDD            LL_ADC_GetLowPowerModeAutoPowerOff

  2443.   * @param  ADCx ADC instance

  2444.   * @retval Returned value can be one of the following values:

  2445.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE

  2446.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE

  2447.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE

  2448.   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES

  2449.   */

  2450. __STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx)

  2451. {

  2452.   return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_PDI | ADC_CR1_PDD)));

  2453. }

  2454. 

  2455. /**

  2456.   * @brief  Set ADC sequencers scan mode, for all ADC groups

  2457.   *         (group regular, group injected).

  2458.   * @note  According to sequencers scan mode :

  2459.   *         - If disabled: ADC conversion is performed in unitary conversion

  2460.   *           mode (one channel converted, that defined in rank 1).

  2461.   *           Configuration of sequencers of all ADC groups

  2462.   *           (sequencer scan length, ...) is discarded: equivalent to

  2463.   *           scan length of 1 rank.

  2464.   *         - If enabled: ADC conversions are performed in sequence conversions

  2465.   *           mode, according to configuration of sequencers of

  2466.   *           each ADC group (sequencer scan length, ...).

  2467.   *           Refer to function @ref LL_ADC_REG_SetSequencerLength()

  2468.   *           and to function @ref LL_ADC_INJ_SetSequencerLength().

  2469.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2470.   *         ADC state:

  2471.   *         ADC must be disabled or enabled without conversion on going

  2472.   *         on either groups regular or injected.

  2473.   * @rmtoll CR1      SCAN           LL_ADC_SetSequencersScanMode

  2474.   * @param  ADCx ADC instance

  2475.   * @param  ScanMode This parameter can be one of the following values:

  2476.   *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE

  2477.   *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE

  2478.   * @retval None

  2479.   */

  2480. __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)

  2481. {

  2482.   MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);

  2483. }

  2484. 

  2485. /**

  2486.   * @brief  Get ADC sequencers scan mode, for all ADC groups

  2487.   *         (group regular, group injected).

  2488.   * @note  According to sequencers scan mode :

  2489.   *         - If disabled: ADC conversion is performed in unitary conversion

  2490.   *           mode (one channel converted, that defined in rank 1).

  2491.   *           Configuration of sequencers of all ADC groups

  2492.   *           (sequencer scan length, ...) is discarded: equivalent to

  2493.   *           scan length of 1 rank.

  2494.   *         - If enabled: ADC conversions are performed in sequence conversions

  2495.   *           mode, according to configuration of sequencers of

  2496.   *           each ADC group (sequencer scan length, ...).

  2497.   *           Refer to function @ref LL_ADC_REG_SetSequencerLength()

  2498.   *           and to function @ref LL_ADC_INJ_SetSequencerLength().

  2499.   * @rmtoll CR1      SCAN           LL_ADC_GetSequencersScanMode

  2500.   * @param  ADCx ADC instance

  2501.   * @retval Returned value can be one of the following values:

  2502.   *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE

  2503.   *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE

  2504.   */

  2505. __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)

  2506. {

  2507.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));

  2508. }

  2509. 

  2510. #if defined(ADC_CR2_CFG)

  2511. /**

  2512.   * @brief  Set ADC channels bank.

  2513.   * @note   Bank selected applies to ADC scope, on all channels

  2514.   *         (independently of channel mapped on ADC group regular

  2515.   *         or group injected).

  2516.   * @note   Banks availability depends on devices categories.

  2517.   * @note   On this STM32 serie, setting of this feature is conditioned to

  2518.   *         ADC state:

  2519.   *         ADC must be disabled or enabled without conversion on going

  2520.   *         on either groups regular or injected.

  2521.   * @rmtoll CR2      ADC_CFG        LL_ADC_SetChannelsBank

  2522.   * @param  ADCx ADC instance

  2523.   * @param  ChannelsBank This parameter can be one of the following values:

  2524.   *         @arg @ref LL_ADC_CHANNELS_BANK_A

  2525.   *         @arg @ref LL_ADC_CHANNELS_BANK_B

  2526.   * @retval None

  2527.   */

  2528. __STATIC_INLINE void LL_ADC_SetChannelsBank(ADC_TypeDef *ADCx, uint32_t ChannelsBank)

  2529. {

  2530.   MODIFY_REG(ADCx->CR2, ADC_CR2_CFG, ChannelsBank);

  2531. }

  2532. 

  2533. /**

  2534.   * @brief  Get ADC channels bank.

  2535.   * @note   Bank selected applies to ADC scope, on all channels

  2536.   *         (independently of channel mapped on ADC group regular

  2537.   *         or group injected).

  2538.   * @note   Banks availability depends on devices categories.

  2539.   * @rmtoll CR2      ADC_CFG        LL_ADC_GetChannelsBank

  2540.   * @param  ADCx ADC instance

  2541.   * @retval Returned value can be one of the following values:

  2542.   *         @arg @ref LL_ADC_CHANNELS_BANK_A

  2543.   *         @arg @ref LL_ADC_CHANNELS_BANK_B

  2544.   */

  2545. __STATIC_INLINE uint32_t LL_ADC_GetChannelsBank(ADC_TypeDef *ADCx)

  2546. {

  2547.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CFG));

  2548. }

  2549. #endif

  2550. 

  2551. /**

  2552.   * @}

  2553.   */

  2554. 

  2555. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular

  2556.   * @{

  2557.   */

  2558. 

  2559. /**

  2560.   * @brief  Set ADC group regular conversion trigger source:

  2561.   *         internal (SW start) or from external IP (timer event,

  2562.   *         external interrupt line).

  2563.   * @note   On this STM32 serie, setting of external trigger edge is performed

  2564.   *         using function @ref LL_ADC_REG_StartConversionExtTrig().

  2565.   * @note   Availability of parameters of trigger sources from timer

  2566.   *         depends on timers availability on the selected device.

  2567.   * @rmtoll CR2      EXTSEL         LL_ADC_REG_SetTriggerSource\n

  2568.   *         CR2      EXTEN          LL_ADC_REG_SetTriggerSource

  2569.   * @param  ADCx ADC instance

  2570.   * @param  TriggerSource This parameter can be one of the following values:

  2571.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  2572.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  2573.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3

  2574.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO

  2575.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  2576.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1

  2577.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3

  2578.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

  2579.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

  2580.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

  2581.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2

  2582.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO

  2583.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  2584.   * @retval None

  2585.   */

  2586. __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  2587. {

  2588. /* Note: On this STM32 serie, ADC group regular external trigger edge        */

  2589. /*       is used to perform a ADC conversion start.                           */

  2590. /*       This function does not set external trigger edge.                    */

  2591. /*       This feature is set using function                                   */

  2592. /*       @ref LL_ADC_REG_StartConversionExtTrig().                            */

  2593.   MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));

  2594. }

  2595. 

  2596. /**

  2597.   * @brief  Get ADC group regular conversion trigger source:

  2598.   *         internal (SW start) or from external IP (timer event,

  2599.   *         external interrupt line).

  2600.   * @note   To determine whether group regular trigger source is

  2601.   *         internal (SW start) or external, without detail

  2602.   *         of which peripheral is selected as external trigger,

  2603.   *         (equivalent to

  2604.   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")

  2605.   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.

  2606.   * @note   Availability of parameters of trigger sources from timer

  2607.   *         depends on timers availability on the selected device.

  2608.   * @rmtoll CR2      EXTSEL         LL_ADC_REG_GetTriggerSource\n

  2609.   *         CR2      EXTEN          LL_ADC_REG_GetTriggerSource

  2610.   * @param  ADCx ADC instance

  2611.   * @retval Returned value can be one of the following values:

  2612.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  2613.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  2614.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3

  2615.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO

  2616.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  2617.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1

  2618.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3

  2619.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

  2620.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

  2621.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

  2622.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2

  2623.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO

  2624.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  2625.   */

  2626. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)

  2627. {

  2628.   uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);

  2629. 

  2630.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  2631.   /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}.                             */

  2632.   uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));

  2633. 

  2634.   /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL           */

  2635.   /* to match with triggers literals definition.                              */

  2636.   return ((TriggerSource

  2637.            & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)

  2638.           | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)

  2639.          );

  2640. }

  2641. 

  2642. /**

  2643.   * @brief  Get ADC group regular conversion trigger source internal (SW start)

  2644.             or external.

  2645.   * @note   In case of group regular trigger source set to external trigger,

  2646.   *         to determine which peripheral is selected as external trigger,

  2647.   *         use function @ref LL_ADC_REG_GetTriggerSource().

  2648.   * @rmtoll CR2      EXTEN          LL_ADC_REG_IsTriggerSourceSWStart

  2649.   * @param  ADCx ADC instance

  2650.   * @retval Value "0" if trigger source external trigger

  2651.   *         Value "1" if trigger source SW start.

  2652.   */

  2653. __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  2654. {

  2655.   return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));

  2656. }

  2657. 

  2658. /**

  2659.   * @brief  Get ADC group regular conversion trigger polarity.

  2660.   * @note   Applicable only for trigger source set to external trigger.

  2661.   * @note   On this STM32 serie, setting of external trigger edge is performed

  2662.   *         using function @ref LL_ADC_REG_StartConversionExtTrig().

  2663.   * @rmtoll CR2      EXTEN          LL_ADC_REG_GetTriggerEdge

  2664.   * @param  ADCx ADC instance

  2665.   * @retval Returned value can be one of the following values:

  2666.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  2667.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  2668.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  2669.   */

  2670. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)

  2671. {

  2672.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));

  2673. }

  2674. 

  2675. 

  2676. /**

  2677.   * @brief  Set ADC group regular sequencer length and scan direction.

  2678.   * @note   Description of ADC group regular sequencer features:

  2679.   *         - For devices with sequencer fully configurable

  2680.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  2681.   *           sequencer length and each rank affectation to a channel

  2682.   *           are configurable.

  2683.   *           This function performs configuration of:

  2684.   *           - Sequence length: Number of ranks in the scan sequence.

  2685.   *           - Sequence direction: Unless specified in parameters, sequencer

  2686.   *             scan direction is forward (from rank 1 to rank n).

  2687.   *           Sequencer ranks are selected using

  2688.   *           function "LL_ADC_REG_SetSequencerRanks()".

  2689.   *         - For devices with sequencer not fully configurable

  2690.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  2691.   *           sequencer length and each rank affectation to a channel

  2692.   *           are defined by channel number.

  2693.   *           This function performs configuration of:

  2694.   *           - Sequence length: Number of ranks in the scan sequence is

  2695.   *             defined by number of channels set in the sequence,

  2696.   *             rank of each channel is fixed by channel HW number.

  2697.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  2698.   *           - Sequence direction: Unless specified in parameters, sequencer

  2699.   *             scan direction is forward (from lowest channel number to

  2700.   *             highest channel number).

  2701.   *           Sequencer ranks are selected using

  2702.   *           function "LL_ADC_REG_SetSequencerChannels()".

  2703.   * @note   On this STM32 serie, group regular sequencer configuration

  2704.   *         is conditioned to ADC instance sequencer mode.

  2705.   *         If ADC instance sequencer mode is disabled, sequencers of

  2706.   *         all groups (group regular, group injected) can be configured

  2707.   *         but their execution is disabled (limited to rank 1).

  2708.   *         Refer to function @ref LL_ADC_SetSequencersScanMode().

  2709.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  2710.   *         ADC conversion on only 1 channel.

  2711.   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength

  2712.   * @param  ADCx ADC instance

  2713.   * @param  SequencerNbRanks This parameter can be one of the following values:

  2714.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  2715.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  2716.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  2717.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  2718.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  2719.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  2720.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  2721.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  2722.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

  2723.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

  2724.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

  2725.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

  2726.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

  2727.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

  2728.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

  2729.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  2730.   * @retval None

  2731.   */

  2732. __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  2733. {

  2734.   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);

  2735. }

  2736. 

  2737. /**

  2738.   * @brief  Get ADC group regular sequencer length and scan direction.

  2739.   * @note   Description of ADC group regular sequencer features:

  2740.   *         - For devices with sequencer fully configurable

  2741.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  2742.   *           sequencer length and each rank affectation to a channel

  2743.   *           are configurable.

  2744.   *           This function retrieves:

  2745.   *           - Sequence length: Number of ranks in the scan sequence.

  2746.   *           - Sequence direction: Unless specified in parameters, sequencer

  2747.   *             scan direction is forward (from rank 1 to rank n).

  2748.   *           Sequencer ranks are selected using

  2749.   *           function "LL_ADC_REG_SetSequencerRanks()".

  2750.   *         - For devices with sequencer not fully configurable

  2751.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  2752.   *           sequencer length and each rank affectation to a channel

  2753.   *           are defined by channel number.

  2754.   *           This function retrieves:

  2755.   *           - Sequence length: Number of ranks in the scan sequence is

  2756.   *             defined by number of channels set in the sequence,

  2757.   *             rank of each channel is fixed by channel HW number.

  2758.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  2759.   *           - Sequence direction: Unless specified in parameters, sequencer

  2760.   *             scan direction is forward (from lowest channel number to

  2761.   *             highest channel number).

  2762.   *           Sequencer ranks are selected using

  2763.   *           function "LL_ADC_REG_SetSequencerChannels()".

  2764.   * @note   On this STM32 serie, group regular sequencer configuration

  2765.   *         is conditioned to ADC instance sequencer mode.

  2766.   *         If ADC instance sequencer mode is disabled, sequencers of

  2767.   *         all groups (group regular, group injected) can be configured

  2768.   *         but their execution is disabled (limited to rank 1).

  2769.   *         Refer to function @ref LL_ADC_SetSequencersScanMode().

  2770.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  2771.   *         ADC conversion on only 1 channel.

  2772.   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength

  2773.   * @param  ADCx ADC instance

  2774.   * @retval Returned value can be one of the following values:

  2775.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  2776.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  2777.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  2778.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  2779.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  2780.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  2781.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  2782.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  2783.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

  2784.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

  2785.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

  2786.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

  2787.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

  2788.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

  2789.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

  2790.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  2791.   */

  2792. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)

  2793. {

  2794.   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));

  2795. }

  2796. 

  2797. /**

  2798.   * @brief  Set ADC group regular sequencer discontinuous mode:

  2799.   *         sequence subdivided and scan conversions interrupted every selected

  2800.   *         number of ranks.

  2801.   * @note   It is not possible to enable both ADC group regular

  2802.   *         continuous mode and sequencer discontinuous mode.

  2803.   * @note   It is not possible to enable both ADC auto-injected mode

  2804.   *         and ADC group regular sequencer discontinuous mode.

  2805.   * @rmtoll CR1      DISCEN         LL_ADC_REG_SetSequencerDiscont\n

  2806.   *         CR1      DISCNUM        LL_ADC_REG_SetSequencerDiscont

  2807.   * @param  ADCx ADC instance

  2808.   * @param  SeqDiscont This parameter can be one of the following values:

  2809.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  2810.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  2811.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

  2812.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

  2813.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

  2814.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

  2815.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

  2816.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

  2817.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

  2818.   * @retval None

  2819.   */

  2820. __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  2821. {

  2822.   MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);

  2823. }

  2824. 

  2825. /**

  2826.   * @brief  Get ADC group regular sequencer discontinuous mode:

  2827.   *         sequence subdivided and scan conversions interrupted every selected

  2828.   *         number of ranks.

  2829.   * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont\n

  2830.   *         CR1      DISCNUM        LL_ADC_REG_GetSequencerDiscont

  2831.   * @param  ADCx ADC instance

  2832.   * @retval Returned value can be one of the following values:

  2833.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  2834.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  2835.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

  2836.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

  2837.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

  2838.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

  2839.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

  2840.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

  2841.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

  2842.   */

  2843. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)

  2844. {

  2845.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));

  2846. }

  2847. 

  2848. /**

  2849.   * @brief  Set ADC group regular sequence: channel on the selected

  2850.   *         scan sequence rank.

  2851.   * @note   This function performs configuration of:

  2852.   *         - Channels ordering into each rank of scan sequence:

  2853.   *           whatever channel can be placed into whatever rank.

  2854.   * @note   On this STM32 serie, ADC group regular sequencer is

  2855.   *         fully configurable: sequencer length and each rank

  2856.   *         affectation to a channel are configurable.

  2857.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  2858.   * @note   Depending on devices and packages, some channels may not be available.

  2859.   *         Refer to device datasheet for channels availability.

  2860.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  2861.   *         TempSensor, ...), measurement paths to internal channels must be

  2862.   *         enabled separately.

  2863.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  2864.   * @rmtoll SQR5     SQ1            LL_ADC_REG_SetSequencerRanks\n

  2865.   *         SQR5     SQ2            LL_ADC_REG_SetSequencerRanks\n

  2866.   *         SQR5     SQ3            LL_ADC_REG_SetSequencerRanks\n

  2867.   *         SQR5     SQ4            LL_ADC_REG_SetSequencerRanks\n

  2868.   *         SQR5     SQ5            LL_ADC_REG_SetSequencerRanks\n

  2869.   *         SQR5     SQ6            LL_ADC_REG_SetSequencerRanks\n

  2870.   *         SQR4     SQ7            LL_ADC_REG_SetSequencerRanks\n

  2871.   *         SQR4     SQ8            LL_ADC_REG_SetSequencerRanks\n

  2872.   *         SQR4     SQ9            LL_ADC_REG_SetSequencerRanks\n

  2873.   *         SQR4     SQ10           LL_ADC_REG_SetSequencerRanks\n

  2874.   *         SQR4     SQ11           LL_ADC_REG_SetSequencerRanks\n

  2875.   *         SQR4     SQ12           LL_ADC_REG_SetSequencerRanks\n

  2876.   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n

  2877.   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n

  2878.   *         SQR3     SQ15           LL_ADC_REG_SetSequencerRanks\n

  2879.   *         SQR3     SQ16           LL_ADC_REG_SetSequencerRanks\n

  2880.   *         SQR3     SQ17           LL_ADC_REG_SetSequencerRanks\n

  2881.   *         SQR3     SQ18           LL_ADC_REG_SetSequencerRanks\n

  2882.   *         SQR2     SQ19           LL_ADC_REG_SetSequencerRanks\n

  2883.   *         SQR2     SQ20           LL_ADC_REG_SetSequencerRanks\n

  2884.   *         SQR2     SQ21           LL_ADC_REG_SetSequencerRanks\n

  2885.   *         SQR2     SQ22           LL_ADC_REG_SetSequencerRanks\n

  2886.   *         SQR2     SQ23           LL_ADC_REG_SetSequencerRanks\n

  2887.   *         SQR2     SQ24           LL_ADC_REG_SetSequencerRanks\n

  2888.   *         SQR1     SQ25           LL_ADC_REG_SetSequencerRanks\n

  2889.   *         SQR1     SQ26           LL_ADC_REG_SetSequencerRanks\n

  2890.   *         SQR1     SQ27           LL_ADC_REG_SetSequencerRanks\n

  2891.   *         SQR1     SQ28           LL_ADC_REG_SetSequencerRanks

  2892.   * @param  ADCx ADC instance

  2893.   * @param  Rank This parameter can be one of the following values:

  2894.   *         @arg @ref LL_ADC_REG_RANK_1

  2895.   *         @arg @ref LL_ADC_REG_RANK_2

  2896.   *         @arg @ref LL_ADC_REG_RANK_3

  2897.   *         @arg @ref LL_ADC_REG_RANK_4

  2898.   *         @arg @ref LL_ADC_REG_RANK_5

  2899.   *         @arg @ref LL_ADC_REG_RANK_6

  2900.   *         @arg @ref LL_ADC_REG_RANK_7

  2901.   *         @arg @ref LL_ADC_REG_RANK_8

  2902.   *         @arg @ref LL_ADC_REG_RANK_9

  2903.   *         @arg @ref LL_ADC_REG_RANK_10

  2904.   *         @arg @ref LL_ADC_REG_RANK_11

  2905.   *         @arg @ref LL_ADC_REG_RANK_12

  2906.   *         @arg @ref LL_ADC_REG_RANK_13

  2907.   *         @arg @ref LL_ADC_REG_RANK_14

  2908.   *         @arg @ref LL_ADC_REG_RANK_15

  2909.   *         @arg @ref LL_ADC_REG_RANK_16

  2910.   *         @arg @ref LL_ADC_REG_RANK_17

  2911.   *         @arg @ref LL_ADC_REG_RANK_18

  2912.   *         @arg @ref LL_ADC_REG_RANK_19

  2913.   *         @arg @ref LL_ADC_REG_RANK_20

  2914.   *         @arg @ref LL_ADC_REG_RANK_21

  2915.   *         @arg @ref LL_ADC_REG_RANK_22

  2916.   *         @arg @ref LL_ADC_REG_RANK_23

  2917.   *         @arg @ref LL_ADC_REG_RANK_24

  2918.   *         @arg @ref LL_ADC_REG_RANK_25

  2919.   *         @arg @ref LL_ADC_REG_RANK_26

  2920.   *         @arg @ref LL_ADC_REG_RANK_27

  2921.   *         @arg @ref LL_ADC_REG_RANK_28 (1)

  2922.   *

  2923.   *         (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5.

  2924.   * @param  Channel This parameter can be one of the following values:

  2925.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  2926.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  2927.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  2928.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  2929.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  2930.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  2931.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  2932.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  2933.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  2934.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  2935.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  2936.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  2937.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  2938.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  2939.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  2940.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  2941.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  2942.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  2943.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  2944.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  2945.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  2946.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  2947.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  2948.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  2949.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  2950.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  2951.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  2952.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  2953.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  2954.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  2955.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  2956.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  2957.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)

  2958.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)

  2959.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)

  2960.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  2961.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  2962.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  2963.   *

  2964.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  2965.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  2966.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  2967.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  2968.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  2969.   * @retval None

  2970.   */

  2971. __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  2972. {

  2973.   /* Set bits with content of parameter "Channel" with bits position          */

  2974.   /* in register and register position depending on parameter "Rank".         */

  2975.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  2976.   /* other bits reserved for other purpose.                                   */

  2977.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));

  2978. 

  2979.   MODIFY_REG(*preg,

  2980.              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),

  2981.              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));

  2982. }

  2983. 

  2984. /**

  2985.   * @brief  Get ADC group regular sequence: channel on the selected

  2986.   *         scan sequence rank.

  2987.   * @note   On this STM32 serie, ADC group regular sequencer is

  2988.   *         fully configurable: sequencer length and each rank

  2989.   *         affectation to a channel are configurable.

  2990.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  2991.   * @note   Depending on devices and packages, some channels may not be available.

  2992.   *         Refer to device datasheet for channels availability.

  2993.   * @note   Usage of the returned channel number:

  2994.   *         - To reinject this channel into another function LL_ADC_xxx:

  2995.   *           the returned channel number is only partly formatted on definition

  2996.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  2997.   *           with parts of literals LL_ADC_CHANNEL_x or using

  2998.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  2999.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3000.   *           as parameter for another function.

  3001.   *         - To get the channel number in decimal format:

  3002.   *           process the returned value with the helper macro

  3003.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3004.   * @rmtoll SQR5     SQ1            LL_ADC_REG_GetSequencerRanks\n

  3005.   *         SQR5     SQ2            LL_ADC_REG_GetSequencerRanks\n

  3006.   *         SQR5     SQ3            LL_ADC_REG_GetSequencerRanks\n

  3007.   *         SQR5     SQ4            LL_ADC_REG_GetSequencerRanks\n

  3008.   *         SQR5     SQ5            LL_ADC_REG_GetSequencerRanks\n

  3009.   *         SQR5     SQ6            LL_ADC_REG_GetSequencerRanks\n

  3010.   *         SQR4     SQ7            LL_ADC_REG_GetSequencerRanks\n

  3011.   *         SQR4     SQ8            LL_ADC_REG_GetSequencerRanks\n

  3012.   *         SQR4     SQ9            LL_ADC_REG_GetSequencerRanks\n

  3013.   *         SQR4     SQ10           LL_ADC_REG_GetSequencerRanks\n

  3014.   *         SQR4     SQ11           LL_ADC_REG_GetSequencerRanks\n

  3015.   *         SQR4     SQ12           LL_ADC_REG_GetSequencerRanks\n

  3016.   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n

  3017.   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n

  3018.   *         SQR3     SQ15           LL_ADC_REG_GetSequencerRanks\n

  3019.   *         SQR3     SQ16           LL_ADC_REG_GetSequencerRanks\n

  3020.   *         SQR3     SQ17           LL_ADC_REG_GetSequencerRanks\n

  3021.   *         SQR3     SQ18           LL_ADC_REG_GetSequencerRanks\n

  3022.   *         SQR2     SQ19           LL_ADC_REG_GetSequencerRanks\n

  3023.   *         SQR2     SQ20           LL_ADC_REG_GetSequencerRanks\n

  3024.   *         SQR2     SQ21           LL_ADC_REG_GetSequencerRanks\n

  3025.   *         SQR2     SQ22           LL_ADC_REG_GetSequencerRanks\n

  3026.   *         SQR2     SQ23           LL_ADC_REG_GetSequencerRanks\n

  3027.   *         SQR2     SQ24           LL_ADC_REG_GetSequencerRanks\n

  3028.   *         SQR1     SQ25           LL_ADC_REG_GetSequencerRanks\n

  3029.   *         SQR1     SQ26           LL_ADC_REG_GetSequencerRanks\n

  3030.   *         SQR1     SQ27           LL_ADC_REG_GetSequencerRanks\n

  3031.   *         SQR1     SQ28           LL_ADC_REG_GetSequencerRanks

  3032.   * @param  ADCx ADC instance

  3033.   * @param  Rank This parameter can be one of the following values:

  3034.   *         @arg @ref LL_ADC_REG_RANK_1

  3035.   *         @arg @ref LL_ADC_REG_RANK_2

  3036.   *         @arg @ref LL_ADC_REG_RANK_3

  3037.   *         @arg @ref LL_ADC_REG_RANK_4

  3038.   *         @arg @ref LL_ADC_REG_RANK_5

  3039.   *         @arg @ref LL_ADC_REG_RANK_6

  3040.   *         @arg @ref LL_ADC_REG_RANK_7

  3041.   *         @arg @ref LL_ADC_REG_RANK_8

  3042.   *         @arg @ref LL_ADC_REG_RANK_9

  3043.   *         @arg @ref LL_ADC_REG_RANK_10

  3044.   *         @arg @ref LL_ADC_REG_RANK_11

  3045.   *         @arg @ref LL_ADC_REG_RANK_12

  3046.   *         @arg @ref LL_ADC_REG_RANK_13

  3047.   *         @arg @ref LL_ADC_REG_RANK_14

  3048.   *         @arg @ref LL_ADC_REG_RANK_15

  3049.   *         @arg @ref LL_ADC_REG_RANK_16

  3050.   *         @arg @ref LL_ADC_REG_RANK_17

  3051.   *         @arg @ref LL_ADC_REG_RANK_18

  3052.   *         @arg @ref LL_ADC_REG_RANK_19

  3053.   *         @arg @ref LL_ADC_REG_RANK_20

  3054.   *         @arg @ref LL_ADC_REG_RANK_21

  3055.   *         @arg @ref LL_ADC_REG_RANK_22

  3056.   *         @arg @ref LL_ADC_REG_RANK_23

  3057.   *         @arg @ref LL_ADC_REG_RANK_24

  3058.   *         @arg @ref LL_ADC_REG_RANK_25

  3059.   *         @arg @ref LL_ADC_REG_RANK_26

  3060.   *         @arg @ref LL_ADC_REG_RANK_27

  3061.   *         @arg @ref LL_ADC_REG_RANK_28 (1)

  3062.   *

  3063.   *         (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5.

  3064.   * @retval Returned value can be one of the following values:

  3065.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  3066.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  3067.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  3068.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  3069.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  3070.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  3071.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  3072.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  3073.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  3074.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  3075.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  3076.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  3077.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  3078.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  3079.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  3080.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  3081.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  3082.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  3083.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  3084.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  3085.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  3086.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  3087.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  3088.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  3089.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  3090.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  3091.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  3092.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  3093.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  3094.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  3095.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  3096.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  3097.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)(6)

  3098.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)

  3099.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)(6)

  3100.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  3101.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  3102.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  3103.   *

  3104.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  3105.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  3106.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  3107.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  3108.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n

  3109.   *         (6) For ADC channel read back from ADC register,

  3110.   *             comparison with internal channel parameter to be done

  3111.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  3112.   */

  3113. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  3114. {

  3115.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));

  3116. 

  3117.   return (uint32_t) (READ_BIT(*preg,

  3118.                               ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))

  3119.                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)

  3120.                     );

  3121. }

  3122. 

  3123. /**

  3124.   * @brief  Set ADC continuous conversion mode on ADC group regular.

  3125.   * @note   Description of ADC continuous conversion mode:

  3126.   *         - single mode: one conversion per trigger

  3127.   *         - continuous mode: after the first trigger, following

  3128.   *           conversions launched successively automatically.

  3129.   * @note   It is not possible to enable both ADC group regular

  3130.   *         continuous mode and sequencer discontinuous mode.

  3131.   * @rmtoll CR2      CONT           LL_ADC_REG_SetContinuousMode

  3132.   * @param  ADCx ADC instance

  3133.   * @param  Continuous This parameter can be one of the following values:

  3134.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  3135.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  3136.   * @retval None

  3137.   */

  3138. __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)

  3139. {

  3140.   MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);

  3141. }

  3142. 

  3143. /**

  3144.   * @brief  Get ADC continuous conversion mode on ADC group regular.

  3145.   * @note   Description of ADC continuous conversion mode:

  3146.   *         - single mode: one conversion per trigger

  3147.   *         - continuous mode: after the first trigger, following

  3148.   *           conversions launched successively automatically.

  3149.   * @rmtoll CR2      CONT           LL_ADC_REG_GetContinuousMode

  3150.   * @param  ADCx ADC instance

  3151.   * @retval Returned value can be one of the following values:

  3152.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  3153.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  3154.   */

  3155. __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)

  3156. {

  3157.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));

  3158. }

  3159. 

  3160. /**

  3161.   * @brief  Set ADC group regular conversion data transfer: no transfer or

  3162.   *         transfer by DMA, and DMA requests mode.

  3163.   * @note   If transfer by DMA selected, specifies the DMA requests

  3164.   *         mode:

  3165.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  3166.   *           when number of DMA data transfers (number of

  3167.   *           ADC conversions) is reached.

  3168.   *           This ADC mode is intended to be used with DMA mode non-circular.

  3169.   *         - Unlimited mode: DMA transfer requests are unlimited,

  3170.   *           whatever number of DMA data transfers (number of

  3171.   *           ADC conversions).

  3172.   *           This ADC mode is intended to be used with DMA mode circular.

  3173.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  3174.   *         mode non-circular:

  3175.   *         when DMA transfers size will be reached, DMA will stop transfers of

  3176.   *         ADC conversions data ADC will raise an overrun error

  3177.   *        (overrun flag and interruption if enabled).

  3178.   * @note   To configure DMA source address (peripheral address),

  3179.   *         use function @ref LL_ADC_DMA_GetRegAddr().

  3180.   * @rmtoll CR2      DMA            LL_ADC_REG_SetDMATransfer\n

  3181.   *         CR2      DDS            LL_ADC_REG_SetDMATransfer

  3182.   * @param  ADCx ADC instance

  3183.   * @param  DMATransfer This parameter can be one of the following values:

  3184.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE

  3185.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  3186.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  3187.   * @retval None

  3188.   */

  3189. __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)

  3190. {

  3191.   MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);

  3192. }

  3193. 

  3194. /**

  3195.   * @brief  Get ADC group regular conversion data transfer: no transfer or

  3196.   *         transfer by DMA, and DMA requests mode.

  3197.   * @note   If transfer by DMA selected, specifies the DMA requests

  3198.   *         mode:

  3199.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  3200.   *           when number of DMA data transfers (number of

  3201.   *           ADC conversions) is reached.

  3202.   *           This ADC mode is intended to be used with DMA mode non-circular.

  3203.   *         - Unlimited mode: DMA transfer requests are unlimited,

  3204.   *           whatever number of DMA data transfers (number of

  3205.   *           ADC conversions).

  3206.   *           This ADC mode is intended to be used with DMA mode circular.

  3207.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  3208.   *         mode non-circular:

  3209.   *         when DMA transfers size will be reached, DMA will stop transfers of

  3210.   *         ADC conversions data ADC will raise an overrun error

  3211.   *         (overrun flag and interruption if enabled).

  3212.   * @note   To configure DMA source address (peripheral address),

  3213.   *         use function @ref LL_ADC_DMA_GetRegAddr().

  3214.   * @rmtoll CR2      DMA            LL_ADC_REG_GetDMATransfer\n

  3215.   *         CR2      DDS            LL_ADC_REG_GetDMATransfer

  3216.   * @param  ADCx ADC instance

  3217.   * @retval Returned value can be one of the following values:

  3218.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE

  3219.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  3220.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  3221.   */

  3222. __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)

  3223. {

  3224.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));

  3225. }

  3226. 

  3227. /**

  3228.   * @brief  Specify which ADC flag between EOC (end of unitary conversion)

  3229.   *         or EOS (end of sequence conversions) is used to indicate

  3230.   *         the end of conversion.

  3231.   * @note   This feature is aimed to be set when using ADC with

  3232.   *         programming model by polling or interruption

  3233.   *         (programming model by DMA usually uses DMA interruptions

  3234.   *         to indicate end of conversion and data transfer).

  3235.   * @note   For ADC group injected, end of conversion (flag&IT) is raised

  3236.   *         only at the end of the sequence.

  3237.   * @rmtoll CR2      EOCS           LL_ADC_REG_SetFlagEndOfConversion

  3238.   * @param  ADCx ADC instance

  3239.   * @param  EocSelection This parameter can be one of the following values:

  3240.   *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV

  3241.   *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV

  3242.   * @retval None

  3243.   */

  3244. __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)

  3245. {

  3246.   MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);

  3247. }

  3248. 

  3249. /**

  3250.   * @brief  Get which ADC flag between EOC (end of unitary conversion)

  3251.   *         or EOS (end of sequence conversions) is used to indicate

  3252.   *         the end of conversion.

  3253.   * @rmtoll CR2      EOCS           LL_ADC_REG_GetFlagEndOfConversion

  3254.   * @param  ADCx ADC instance

  3255.   * @retval Returned value can be one of the following values:

  3256.   *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV

  3257.   *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV

  3258.   */

  3259. __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)

  3260. {

  3261.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));

  3262. }

  3263. 

  3264. /**

  3265.   * @}

  3266.   */

  3267. 

  3268. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected

  3269.   * @{

  3270.   */

  3271. 

  3272. /**

  3273.   * @brief  Set ADC group injected conversion trigger source:

  3274.   *         internal (SW start) or from external IP (timer event,

  3275.   *         external interrupt line).

  3276.   * @note   On this STM32 serie, setting of external trigger edge is performed

  3277.   *         using function @ref LL_ADC_INJ_StartConversionExtTrig().

  3278.   * @note   Availability of parameters of trigger sources from timer

  3279.   *         depends on timers availability on the selected device.

  3280.   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_SetTriggerSource\n

  3281.   *         CR2      JEXTEN         LL_ADC_INJ_SetTriggerSource

  3282.   * @param  ADCx ADC instance

  3283.   * @param  TriggerSource This parameter can be one of the following values:

  3284.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  3285.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1

  3286.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO

  3287.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  3288.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  3289.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  3290.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  3291.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1

  3292.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2

  3293.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3

  3294.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1

  3295.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO

  3296.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  3297.   * @retval None

  3298.   */

  3299. __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  3300. {

  3301. /* Note: On this STM32 serie, ADC group injected external trigger edge       */

  3302. /*       is used to perform a ADC conversion start.                           */

  3303. /*       This function does not set external trigger edge.                    */

  3304. /*       This feature is set using function                                   */

  3305. /*       @ref LL_ADC_INJ_StartConversionExtTrig().                            */

  3306.   MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));

  3307. }

  3308. 

  3309. /**

  3310.   * @brief  Get ADC group injected conversion trigger source:

  3311.   *         internal (SW start) or from external IP (timer event,

  3312.   *         external interrupt line).

  3313.   * @note   To determine whether group injected trigger source is

  3314.   *         internal (SW start) or external, without detail

  3315.   *         of which peripheral is selected as external trigger,

  3316.   *         (equivalent to

  3317.   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")

  3318.   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.

  3319.   * @note   Availability of parameters of trigger sources from timer

  3320.   *         depends on timers availability on the selected device.

  3321.   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_GetTriggerSource\n

  3322.   *         CR2      JEXTEN         LL_ADC_INJ_GetTriggerSource

  3323.   * @param  ADCx ADC instance

  3324.   * @retval Returned value can be one of the following values:

  3325.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  3326.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1

  3327.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO

  3328.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  3329.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  3330.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  3331.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  3332.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1

  3333.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2

  3334.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3

  3335.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1

  3336.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO

  3337.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

  3338.   */

  3339. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)

  3340. {

  3341.   uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);

  3342. 

  3343.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  3344.   /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}.                            */

  3345.   uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));

  3346. 

  3347.   /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL         */

  3348.   /* to match with triggers literals definition.                              */

  3349.   return ((TriggerSource

  3350.            & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)

  3351.           | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)

  3352.          );

  3353. }

  3354. 

  3355. /**

  3356.   * @brief  Get ADC group injected conversion trigger source internal (SW start)

  3357.             or external

  3358.   * @note   In case of group injected trigger source set to external trigger,

  3359.   *         to determine which peripheral is selected as external trigger,

  3360.   *         use function @ref LL_ADC_INJ_GetTriggerSource.

  3361.   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart

  3362.   * @param  ADCx ADC instance

  3363.   * @retval Value "0" if trigger source external trigger

  3364.   *         Value "1" if trigger source SW start.

  3365.   */

  3366. __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  3367. {

  3368.   return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));

  3369. }

  3370. 

  3371. /**

  3372.   * @brief  Get ADC group injected conversion trigger polarity.

  3373.   *         Applicable only for trigger source set to external trigger.

  3374.   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_GetTriggerEdge

  3375.   * @param  ADCx ADC instance

  3376.   * @retval Returned value can be one of the following values:

  3377.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  3378.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  3379.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  3380.   */

  3381. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)

  3382. {

  3383.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));

  3384. }

  3385. 

  3386. /**

  3387.   * @brief  Set ADC group injected sequencer length and scan direction.

  3388.   * @note   This function performs configuration of:

  3389.   *         - Sequence length: Number of ranks in the scan sequence.

  3390.   *         - Sequence direction: Unless specified in parameters, sequencer

  3391.   *           scan direction is forward (from rank 1 to rank n).

  3392.   * @note   On this STM32 serie, group injected sequencer configuration

  3393.   *         is conditioned to ADC instance sequencer mode.

  3394.   *         If ADC instance sequencer mode is disabled, sequencers of

  3395.   *         all groups (group regular, group injected) can be configured

  3396.   *         but their execution is disabled (limited to rank 1).

  3397.   *         Refer to function @ref LL_ADC_SetSequencersScanMode().

  3398.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3399.   *         ADC conversion on only 1 channel.

  3400.   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength

  3401.   * @param  ADCx ADC instance

  3402.   * @param  SequencerNbRanks This parameter can be one of the following values:

  3403.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  3404.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  3405.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  3406.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  3407.   * @retval None

  3408.   */

  3409. __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  3410. {

  3411.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);

  3412. }

  3413. 

  3414. /**

  3415.   * @brief  Get ADC group injected sequencer length and scan direction.

  3416.   * @note   This function retrieves:

  3417.   *         - Sequence length: Number of ranks in the scan sequence.

  3418.   *         - Sequence direction: Unless specified in parameters, sequencer

  3419.   *           scan direction is forward (from rank 1 to rank n).

  3420.   * @note   On this STM32 serie, group injected sequencer configuration

  3421.   *         is conditioned to ADC instance sequencer mode.

  3422.   *         If ADC instance sequencer mode is disabled, sequencers of

  3423.   *         all groups (group regular, group injected) can be configured

  3424.   *         but their execution is disabled (limited to rank 1).

  3425.   *         Refer to function @ref LL_ADC_SetSequencersScanMode().

  3426.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  3427.   *         ADC conversion on only 1 channel.

  3428.   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength

  3429.   * @param  ADCx ADC instance

  3430.   * @retval Returned value can be one of the following values:

  3431.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  3432.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  3433.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  3434.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  3435.   */

  3436. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)

  3437. {

  3438.   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));

  3439. }

  3440. 

  3441. /**

  3442.   * @brief  Set ADC group injected sequencer discontinuous mode:

  3443.   *         sequence subdivided and scan conversions interrupted every selected

  3444.   *         number of ranks.

  3445.   * @note   It is not possible to enable both ADC group injected

  3446.   *         auto-injected mode and sequencer discontinuous mode.

  3447.   * @rmtoll CR1      DISCEN         LL_ADC_INJ_SetSequencerDiscont

  3448.   * @param  ADCx ADC instance

  3449.   * @param  SeqDiscont This parameter can be one of the following values:

  3450.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  3451.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  3452.   * @retval None

  3453.   */

  3454. __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  3455. {

  3456.   MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);

  3457. }

  3458. 

  3459. /**

  3460.   * @brief  Get ADC group injected sequencer discontinuous mode:

  3461.   *         sequence subdivided and scan conversions interrupted every selected

  3462.   *         number of ranks.

  3463.   * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont

  3464.   * @param  ADCx ADC instance

  3465.   * @retval Returned value can be one of the following values:

  3466.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  3467.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  3468.   */

  3469. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)

  3470. {

  3471.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));

  3472. }

  3473. 

  3474. /**

  3475.   * @brief  Set ADC group injected sequence: channel on the selected

  3476.   *         sequence rank.

  3477.   * @note   Depending on devices and packages, some channels may not be available.

  3478.   *         Refer to device datasheet for channels availability.

  3479.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  3480.   *         TempSensor, ...), measurement paths to internal channels must be

  3481.   *         enabled separately.

  3482.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  3483.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n

  3484.   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n

  3485.   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n

  3486.   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks

  3487.   * @param  ADCx ADC instance

  3488.   * @param  Rank This parameter can be one of the following values:

  3489.   *         @arg @ref LL_ADC_INJ_RANK_1

  3490.   *         @arg @ref LL_ADC_INJ_RANK_2

  3491.   *         @arg @ref LL_ADC_INJ_RANK_3

  3492.   *         @arg @ref LL_ADC_INJ_RANK_4

  3493.   * @param  Channel This parameter can be one of the following values:

  3494.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  3495.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  3496.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  3497.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  3498.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  3499.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  3500.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  3501.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  3502.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  3503.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  3504.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  3505.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  3506.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  3507.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  3508.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  3509.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  3510.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  3511.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  3512.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  3513.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  3514.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  3515.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  3516.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  3517.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  3518.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  3519.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  3520.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  3521.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  3522.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  3523.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  3524.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  3525.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  3526.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)

  3527.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)

  3528.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)

  3529.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  3530.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  3531.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  3532.   *

  3533.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  3534.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  3535.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  3536.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  3537.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  3538.   * @retval None

  3539.   */

  3540. __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  3541. {

  3542.   /* Set bits with content of parameter "Channel" with bits position          */

  3543.   /* in register depending on parameter "Rank".                               */

  3544.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  3545.   /* other bits reserved for other purpose.                                   */

  3546.   MODIFY_REG(ADCx->JSQR,

  3547.              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),

  3548.              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));

  3549. }

  3550. 

  3551. /**

  3552.   * @brief  Get ADC group injected sequence: channel on the selected

  3553.   *         sequence rank.

  3554.   * @note   Depending on devices and packages, some channels may not be available.

  3555.   *         Refer to device datasheet for channels availability.

  3556.   * @note   Usage of the returned channel number:

  3557.   *         - To reinject this channel into another function LL_ADC_xxx:

  3558.   *           the returned channel number is only partly formatted on definition

  3559.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  3560.   *           with parts of literals LL_ADC_CHANNEL_x or using

  3561.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3562.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3563.   *           as parameter for another function.

  3564.   *         - To get the channel number in decimal format:

  3565.   *           process the returned value with the helper macro

  3566.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3567.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n

  3568.   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n

  3569.   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n

  3570.   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks

  3571.   * @param  ADCx ADC instance

  3572.   * @param  Rank This parameter can be one of the following values:

  3573.   *         @arg @ref LL_ADC_INJ_RANK_1

  3574.   *         @arg @ref LL_ADC_INJ_RANK_2

  3575.   *         @arg @ref LL_ADC_INJ_RANK_3

  3576.   *         @arg @ref LL_ADC_INJ_RANK_4

  3577.   * @retval Returned value can be one of the following values:

  3578.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  3579.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  3580.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  3581.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  3582.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  3583.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  3584.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  3585.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  3586.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  3587.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  3588.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  3589.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  3590.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  3591.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  3592.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  3593.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  3594.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  3595.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  3596.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  3597.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  3598.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  3599.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  3600.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  3601.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  3602.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  3603.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  3604.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  3605.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  3606.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  3607.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  3608.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  3609.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  3610.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)(6)

  3611.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)

  3612.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)(6)

  3613.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  3614.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  3615.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  3616.   *

  3617.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  3618.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  3619.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  3620.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  3621.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n

  3622.   *         (6) For ADC channel read back from ADC register,

  3623.   *             comparison with internal channel parameter to be done

  3624.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  3625.   */

  3626. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  3627. {

  3628.   return (uint32_t)(READ_BIT(ADCx->JSQR,

  3629.                              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))

  3630.                     >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)

  3631.                    );

  3632. }

  3633. 

  3634. /**

  3635.   * @brief  Set ADC group injected conversion trigger:

  3636.   *         independent or from ADC group regular.

  3637.   * @note   This mode can be used to extend number of data registers

  3638.   *         updated after one ADC conversion trigger and with data

  3639.   *         permanently kept (not erased by successive conversions of scan of

  3640.   *         ADC sequencer ranks), up to 5 data registers:

  3641.   *         1 data register on ADC group regular, 4 data registers

  3642.   *         on ADC group injected.

  3643.   * @note   If ADC group injected injected trigger source is set to an

  3644.   *         external trigger, this feature must be must be set to

  3645.   *         independent trigger.

  3646.   *         ADC group injected automatic trigger is compliant only with

  3647.   *         group injected trigger source set to SW start, without any

  3648.   *         further action on  ADC group injected conversion start or stop:

  3649.   *         in this case, ADC group injected is controlled only

  3650.   *         from ADC group regular.

  3651.   * @note   It is not possible to enable both ADC group injected

  3652.   *         auto-injected mode and sequencer discontinuous mode.

  3653.   * @rmtoll CR1      JAUTO          LL_ADC_INJ_SetTrigAuto

  3654.   * @param  ADCx ADC instance

  3655.   * @param  TrigAuto This parameter can be one of the following values:

  3656.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  3657.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  3658.   * @retval None

  3659.   */

  3660. __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)

  3661. {

  3662.   MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);

  3663. }

  3664. 

  3665. /**

  3666.   * @brief  Get ADC group injected conversion trigger:

  3667.   *         independent or from ADC group regular.

  3668.   * @rmtoll CR1      JAUTO          LL_ADC_INJ_GetTrigAuto

  3669.   * @param  ADCx ADC instance

  3670.   * @retval Returned value can be one of the following values:

  3671.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  3672.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  3673.   */

  3674. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)

  3675. {

  3676.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));

  3677. }

  3678. 

  3679. /**

  3680.   * @brief  Set ADC group injected offset.

  3681.   * @note   It sets:

  3682.   *         - ADC group injected rank to which the offset programmed

  3683.   *           will be applied

  3684.   *         - Offset level (offset to be subtracted from the raw

  3685.   *           converted data).

  3686.   *         Caution: Offset format is dependent to ADC resolution:

  3687.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  3688.   *         are set to 0.

  3689.   * @note   Offset cannot be enabled or disabled.

  3690.   *         To emulate offset disabled, set an offset value equal to 0.

  3691.   * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_SetOffset\n

  3692.   *         JOFR2    JOFFSET2       LL_ADC_INJ_SetOffset\n

  3693.   *         JOFR3    JOFFSET3       LL_ADC_INJ_SetOffset\n

  3694.   *         JOFR4    JOFFSET4       LL_ADC_INJ_SetOffset

  3695.   * @param  ADCx ADC instance

  3696.   * @param  Rank This parameter can be one of the following values:

  3697.   *         @arg @ref LL_ADC_INJ_RANK_1

  3698.   *         @arg @ref LL_ADC_INJ_RANK_2

  3699.   *         @arg @ref LL_ADC_INJ_RANK_3

  3700.   *         @arg @ref LL_ADC_INJ_RANK_4

  3701.   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF

  3702.   * @retval None

  3703.   */

  3704. __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)

  3705. {

  3706.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));

  3707. 

  3708.   MODIFY_REG(*preg,

  3709.              ADC_JOFR1_JOFFSET1,

  3710.              OffsetLevel);

  3711. }

  3712. 

  3713. /**

  3714.   * @brief  Get ADC group injected offset.

  3715.   * @note   It gives offset level (offset to be subtracted from the raw converted data).

  3716.   *         Caution: Offset format is dependent to ADC resolution:

  3717.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  3718.   *         are set to 0.

  3719.   * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_GetOffset\n

  3720.   *         JOFR2    JOFFSET2       LL_ADC_INJ_GetOffset\n

  3721.   *         JOFR3    JOFFSET3       LL_ADC_INJ_GetOffset\n

  3722.   *         JOFR4    JOFFSET4       LL_ADC_INJ_GetOffset

  3723.   * @param  ADCx ADC instance

  3724.   * @param  Rank This parameter can be one of the following values:

  3725.   *         @arg @ref LL_ADC_INJ_RANK_1

  3726.   *         @arg @ref LL_ADC_INJ_RANK_2

  3727.   *         @arg @ref LL_ADC_INJ_RANK_3

  3728.   *         @arg @ref LL_ADC_INJ_RANK_4

  3729.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  3730.   */

  3731. __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)

  3732. {

  3733.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));

  3734. 

  3735.   return (uint32_t)(READ_BIT(*preg,

  3736.                              ADC_JOFR1_JOFFSET1)

  3737.                    );

  3738. }

  3739. 

  3740. /**

  3741.   * @}

  3742.   */

  3743. 

  3744. /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels

  3745.   * @{

  3746.   */

  3747. 

  3748. /**

  3749.   * @brief  Set sampling time of the selected ADC channel

  3750.   *         Unit: ADC clock cycles.

  3751.   * @note   On this device, sampling time is on channel scope: independently

  3752.   *         of channel mapped on ADC group regular or injected.

  3753.   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be

  3754.   *         converted:

  3755.   *         sampling time constraints must be respected (sampling time can be

  3756.   *         adjusted in function of ADC clock frequency and sampling time

  3757.   *         setting).

  3758.   *         Refer to device datasheet for timings values (parameters TS_vrefint,

  3759.   *         TS_temp, ...).

  3760.   * @note   Conversion time is the addition of sampling time and processing time.

  3761.   *         Refer to reference manual for ADC processing time of

  3762.   *         this STM32 serie.

  3763.   * @note   In case of ADC conversion of internal channel (VrefInt,

  3764.   *         temperature sensor, ...), a sampling time minimum value

  3765.   *         is required.

  3766.   *         Refer to device datasheet.

  3767.   * @rmtoll SMPR0    SMP31          LL_ADC_SetChannelSamplingTime\n

  3768.   *         SMPR0    SMP30          LL_ADC_SetChannelSamplingTime\n

  3769.   *         SMPR1    SMP29          LL_ADC_SetChannelSamplingTime\n

  3770.   *         SMPR1    SMP28          LL_ADC_SetChannelSamplingTime\n

  3771.   *         SMPR1    SMP27          LL_ADC_SetChannelSamplingTime\n

  3772.   *         SMPR1    SMP26          LL_ADC_SetChannelSamplingTime\n

  3773.   *         SMPR1    SMP25          LL_ADC_SetChannelSamplingTime\n

  3774.   *         SMPR1    SMP24          LL_ADC_SetChannelSamplingTime\n

  3775.   *         SMPR1    SMP23          LL_ADC_SetChannelSamplingTime\n

  3776.   *         SMPR1    SMP22          LL_ADC_SetChannelSamplingTime\n

  3777.   *         SMPR1    SMP21          LL_ADC_SetChannelSamplingTime\n

  3778.   *         SMPR1    SMP20          LL_ADC_SetChannelSamplingTime\n

  3779.   *         SMPR2    SMP19          LL_ADC_SetChannelSamplingTime\n

  3780.   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime\n

  3781.   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n

  3782.   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n

  3783.   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n

  3784.   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n

  3785.   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n

  3786.   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n

  3787.   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n

  3788.   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n

  3789.   *         SMPR3    SMP9           LL_ADC_SetChannelSamplingTime\n

  3790.   *         SMPR3    SMP8           LL_ADC_SetChannelSamplingTime\n

  3791.   *         SMPR3    SMP7           LL_ADC_SetChannelSamplingTime\n

  3792.   *         SMPR3    SMP6           LL_ADC_SetChannelSamplingTime\n

  3793.   *         SMPR3    SMP5           LL_ADC_SetChannelSamplingTime\n

  3794.   *         SMPR3    SMP4           LL_ADC_SetChannelSamplingTime\n

  3795.   *         SMPR3    SMP3           LL_ADC_SetChannelSamplingTime\n

  3796.   *         SMPR3    SMP2           LL_ADC_SetChannelSamplingTime\n

  3797.   *         SMPR3    SMP1           LL_ADC_SetChannelSamplingTime\n

  3798.   *         SMPR3    SMP0           LL_ADC_SetChannelSamplingTime

  3799.   * @param  ADCx ADC instance

  3800.   * @param  Channel This parameter can be one of the following values:

  3801.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  3802.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  3803.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  3804.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  3805.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  3806.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  3807.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  3808.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  3809.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  3810.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  3811.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  3812.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  3813.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  3814.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  3815.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  3816.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  3817.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  3818.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  3819.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  3820.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  3821.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  3822.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  3823.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  3824.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  3825.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  3826.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  3827.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  3828.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  3829.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  3830.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  3831.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  3832.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  3833.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)

  3834.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)

  3835.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)

  3836.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  3837.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  3838.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  3839.   *

  3840.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  3841.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  3842.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  3843.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  3844.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  3845.   * @param  SamplingTime This parameter can be one of the following values:

  3846.   *         @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES

  3847.   *         @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES

  3848.   *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES

  3849.   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES

  3850.   *         @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES

  3851.   *         @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES

  3852.   *         @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES

  3853.   *         @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES

  3854.   * @retval None

  3855.   */

  3856. __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)

  3857. {

  3858.   /* Set bits with content of parameter "SamplingTime" with bits position     */

  3859.   /* in register and register position depending on parameter "Channel".      */

  3860.   /* Parameter "Channel" is used with masks because containing                */

  3861.   /* other bits reserved for other purpose.                                   */

  3862.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));

  3863. 

  3864.   MODIFY_REG(*preg,

  3865.              ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),

  3866.              SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));

  3867. }

  3868. 

  3869. /**

  3870.   * @brief  Get sampling time of the selected ADC channel

  3871.   *         Unit: ADC clock cycles.

  3872.   * @note   On this device, sampling time is on channel scope: independently

  3873.   *         of channel mapped on ADC group regular or injected.

  3874.   * @note   Conversion time is the addition of sampling time and processing time.

  3875.   *         Refer to reference manual for ADC processing time of

  3876.   *         this STM32 serie.

  3877.   * @rmtoll SMPR0    SMP31          LL_ADC_GetChannelSamplingTime\n

  3878.   *         SMPR0    SMP30          LL_ADC_GetChannelSamplingTime\n

  3879.   *         SMPR1    SMP29          LL_ADC_GetChannelSamplingTime\n

  3880.   *         SMPR1    SMP28          LL_ADC_GetChannelSamplingTime\n

  3881.   *         SMPR1    SMP27          LL_ADC_GetChannelSamplingTime\n

  3882.   *         SMPR1    SMP26          LL_ADC_GetChannelSamplingTime\n

  3883.   *         SMPR1    SMP25          LL_ADC_GetChannelSamplingTime\n

  3884.   *         SMPR1    SMP24          LL_ADC_GetChannelSamplingTime\n

  3885.   *         SMPR1    SMP23          LL_ADC_GetChannelSamplingTime\n

  3886.   *         SMPR1    SMP22          LL_ADC_GetChannelSamplingTime\n

  3887.   *         SMPR1    SMP21          LL_ADC_GetChannelSamplingTime\n

  3888.   *         SMPR1    SMP20          LL_ADC_GetChannelSamplingTime\n

  3889.   *         SMPR2    SMP19          LL_ADC_GetChannelSamplingTime\n

  3890.   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime\n

  3891.   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n

  3892.   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n

  3893.   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n

  3894.   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n

  3895.   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n

  3896.   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n

  3897.   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n

  3898.   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n

  3899.   *         SMPR3    SMP9           LL_ADC_GetChannelSamplingTime\n

  3900.   *         SMPR3    SMP8           LL_ADC_GetChannelSamplingTime\n

  3901.   *         SMPR3    SMP7           LL_ADC_GetChannelSamplingTime\n

  3902.   *         SMPR3    SMP6           LL_ADC_GetChannelSamplingTime\n

  3903.   *         SMPR3    SMP5           LL_ADC_GetChannelSamplingTime\n

  3904.   *         SMPR3    SMP4           LL_ADC_GetChannelSamplingTime\n

  3905.   *         SMPR3    SMP3           LL_ADC_GetChannelSamplingTime\n

  3906.   *         SMPR3    SMP2           LL_ADC_GetChannelSamplingTime\n

  3907.   *         SMPR3    SMP1           LL_ADC_GetChannelSamplingTime\n

  3908.   *         SMPR3    SMP0           LL_ADC_GetChannelSamplingTime

  3909.   * @param  ADCx ADC instance

  3910.   * @param  Channel This parameter can be one of the following values:

  3911.   *         @arg @ref LL_ADC_CHANNEL_0          (2)

  3912.   *         @arg @ref LL_ADC_CHANNEL_1          (2)

  3913.   *         @arg @ref LL_ADC_CHANNEL_2          (2)

  3914.   *         @arg @ref LL_ADC_CHANNEL_3          (2)

  3915.   *         @arg @ref LL_ADC_CHANNEL_4          (1)

  3916.   *         @arg @ref LL_ADC_CHANNEL_5          (1)

  3917.   *         @arg @ref LL_ADC_CHANNEL_6          (2)

  3918.   *         @arg @ref LL_ADC_CHANNEL_7          (2)

  3919.   *         @arg @ref LL_ADC_CHANNEL_8          (2)

  3920.   *         @arg @ref LL_ADC_CHANNEL_9          (2)

  3921.   *         @arg @ref LL_ADC_CHANNEL_10         (2)

  3922.   *         @arg @ref LL_ADC_CHANNEL_11         (2)

  3923.   *         @arg @ref LL_ADC_CHANNEL_12         (2)

  3924.   *         @arg @ref LL_ADC_CHANNEL_13         (3)

  3925.   *         @arg @ref LL_ADC_CHANNEL_14         (3)

  3926.   *         @arg @ref LL_ADC_CHANNEL_15         (3)

  3927.   *         @arg @ref LL_ADC_CHANNEL_16         (3)

  3928.   *         @arg @ref LL_ADC_CHANNEL_17         (3)

  3929.   *         @arg @ref LL_ADC_CHANNEL_18         (3)

  3930.   *         @arg @ref LL_ADC_CHANNEL_19         (3)

  3931.   *         @arg @ref LL_ADC_CHANNEL_20         (3)

  3932.   *         @arg @ref LL_ADC_CHANNEL_21         (3)

  3933.   *         @arg @ref LL_ADC_CHANNEL_22         (1)

  3934.   *         @arg @ref LL_ADC_CHANNEL_23         (1)

  3935.   *         @arg @ref LL_ADC_CHANNEL_24         (1)

  3936.   *         @arg @ref LL_ADC_CHANNEL_25         (1)

  3937.   *         @arg @ref LL_ADC_CHANNEL_26         (3)

  3938.   *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)

  3939.   *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)

  3940.   *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)

  3941.   *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)

  3942.   *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)

  3943.   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)

  3944.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)

  3945.   *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)

  3946.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)

  3947.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)

  3948.   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)

  3949.   *

  3950.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  3951.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  3952.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  3953.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  3954.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  3955.   * @retval Returned value can be one of the following values:

  3956.   *         @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES

  3957.   *         @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES

  3958.   *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES

  3959.   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES

  3960.   *         @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES

  3961.   *         @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES

  3962.   *         @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES

  3963.   *         @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES

  3964.   */

  3965. __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)

  3966. {

  3967.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));

  3968. 

  3969.   return (uint32_t)(READ_BIT(*preg,

  3970.                              ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))

  3971.                     >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)

  3972.                    );

  3973. }

  3974. 

  3975. #if defined(COMP_CSR_FCH3)

  3976. /**

  3977.   * @brief  Set ADC channels routing.

  3978.   * @note   Channel routing set configuration between ADC IP and GPIO pads,

  3979.   *         it is used to increase ADC channels speed (setting of

  3980.   *         direct channel).

  3981.   * @note   This feature is specific to STM32L1, on devices

  3982.   *         category Cat.3, Cat.4, Cat.5.

  3983.   *         To use this function, COMP RCC clock domain must be enabled.

  3984.   *         Refer to @ref LL_APB1_GRP1_PERIPH_COMP.

  3985.   * @rmtoll CSR      FCH3           LL_ADC_SetChannelRouting

  3986.   * @rmtoll CSR      FCH8           LL_ADC_SetChannelRouting

  3987.   * @rmtoll CSR      RCH13          LL_ADC_SetChannelRouting

  3988.   * @param  ADCx ADC instance

  3989.   * @param  Channel This parameter can be one of the following values:

  3990.   *         @arg @ref LL_ADC_CHANNEL_3_ROUTING  (1)

  3991.   *         @arg @ref LL_ADC_CHANNEL_8_ROUTING  (2)

  3992.   *         @arg @ref LL_ADC_CHANNEL_13_ROUTING (3)

  3993.   *

  3994.   *         (1) Used as ADC direct channel (fast channel) if OPAMP1 is

  3995.   *             in power down mode.\n

  3996.   *         (2) Used as ADC direct channel (fast channel) if OPAMP2 is

  3997.   *             in power down mode.\n

  3998.   *         (3) Used as ADC re-routed channel if OPAMP3 is

  3999.   *             in power down mode.

  4000.   *             Otherwise, channel 13 is connected to OPAMP3 output and routed

  4001.   *             through switches COMP1_SW1 and VCOMP to ADC switch matrix.

  4002.   *             (Note: OPAMP3 is available on STM32L1 Cat.4 only).

  4003.   * @param  Routing This parameter can be one of the following values:

  4004.   *         @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT

  4005.   *         @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT

  4006.   */

  4007. __STATIC_INLINE void LL_ADC_SetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Routing)

  4008. {

  4009.   /* Note: Bit is located in comparator IP, but dedicated to ADC */

  4010.   MODIFY_REG(COMP->CSR, Channel, (Routing << POSITION_VAL(Channel)));

  4011. }

  4012. 

  4013. /**

  4014.   * @brief  Get ADC channels speed.

  4015.   * @note   Channel routing set configuration between ADC IP and GPIO pads,

  4016.   *         it is used to increase ADC channels speed (setting of

  4017.   *         direct channel).

  4018.   * @note   This feature is specific to STM32L1, on devices

  4019.   *         category Cat.3, Cat.4, Cat.5.

  4020.   *         To use this function, COMP RCC clock domain must be enabled.

  4021.   *         Refer to @ref LL_APB1_GRP1_PERIPH_COMP.

  4022.   * @rmtoll CSR      FCH3           LL_ADC_GetChannelRouting

  4023.   * @rmtoll CSR      FCH8           LL_ADC_GetChannelRouting

  4024.   * @rmtoll CSR      RCH13          LL_ADC_GetChannelRouting

  4025.   * @param  ADCx ADC instance

  4026.   * @param  Channel This parameter can be one of the following values:

  4027.   *         @arg @ref LL_ADC_CHANNEL_3_ROUTING  (1)

  4028.   *         @arg @ref LL_ADC_CHANNEL_8_ROUTING  (2)

  4029.   *         @arg @ref LL_ADC_CHANNEL_13_ROUTING (3)

  4030.   *

  4031.   *         (1) Used as ADC direct channel (fast channel) if OPAMP1 is

  4032.   *             in power down mode.\n

  4033.   *         (2) Used as ADC direct channel (fast channel) if OPAMP2 is

  4034.   *             in power down mode.\n

  4035.   *         (3) Used as ADC re-routed channel if OPAMP3 is

  4036.   *             in power down mode.

  4037.   *             Otherwise, channel 13 is connected to OPAMP3 output and routed

  4038.   *             through switches COMP1_SW1 and VCOMP to ADC switch matrix.

  4039.   *             (Note: OPAMP3 is available on STM32L1 Cat.4 only).

  4040.   * @retval Returned value can be one of the following values:

  4041.   *         @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT

  4042.   *         @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT

  4043.   */

  4044. __STATIC_INLINE uint32_t LL_ADC_GetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel)

  4045. {

  4046.   /* Note: Bit is located in comparator IP, but dedicated to ADC */

  4047.   return (uint32_t)(READ_BIT(COMP->CSR, Channel) >> POSITION_VAL(Channel));

  4048. }

  4049. #endif

  4050. 

  4051. /**

  4052.   * @}

  4053.   */

  4054. 

  4055. /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog

  4056.   * @{

  4057.   */

  4058. 

  4059. /**

  4060.   * @brief  Set ADC analog watchdog monitored channels:

  4061.   *         a single channel or all channels,

  4062.   *         on ADC groups regular and-or injected.

  4063.   * @note   Once monitored channels are selected, analog watchdog

  4064.   *         is enabled.

  4065.   * @note   In case of need to define a single channel to monitor

  4066.   *         with analog watchdog from sequencer channel definition,

  4067.   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().

  4068.   * @note   On this STM32 serie, there is only 1 kind of analog watchdog

  4069.   *         instance:

  4070.   *         - AWD standard (instance AWD1):

  4071.   *           - channels monitored: can monitor 1 channel or all channels.

  4072.   *           - groups monitored: ADC groups regular and-or injected.

  4073.   *           - resolution: resolution is not limited (corresponds to

  4074.   *             ADC resolution configured).

  4075.   * @rmtoll CR1      AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n

  4076.   *         CR1      AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n

  4077.   *         CR1      AWD1EN         LL_ADC_SetAnalogWDMonitChannels

  4078.   * @param  ADCx ADC instance

  4079.   * @param  AWDChannelGroup This parameter can be one of the following values:

  4080.   *         @arg @ref LL_ADC_AWD_DISABLE

  4081.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG

  4082.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ

  4083.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  4084.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (2)

  4085.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (2)

  4086.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ       (2)

  4087.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (2)

  4088.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (2)

  4089.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ       (2)

  4090.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (2)

  4091.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (2)

  4092.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ       (2)

  4093.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (2)

  4094.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (2)

  4095.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ       (2)

  4096.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (1)

  4097.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (1)

  4098.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ       (1)

  4099.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (1)

  4100.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (1)

  4101.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ       (1)

  4102.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (2)

  4103.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (2)

  4104.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ       (2)

  4105.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (2)

  4106.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (2)

  4107.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ       (2)

  4108.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (2)

  4109.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (2)

  4110.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ       (2)

  4111.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (2)

  4112.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (2)

  4113.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ       (2)

  4114.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (2)

  4115.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (2)

  4116.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ      (2)

  4117.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (2)

  4118.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (2)

  4119.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ      (2)

  4120.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (2)

  4121.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (2)

  4122.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ      (2)

  4123.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (3)

  4124.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (3)

  4125.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ      (3)

  4126.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (3)

  4127.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (3)

  4128.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ      (3)

  4129.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (3)

  4130.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (3)

  4131.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ      (3)

  4132.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (3)

  4133.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (3)

  4134.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ      (3)

  4135.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (3)

  4136.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (3)

  4137.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ      (3)

  4138.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (3)

  4139.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (3)

  4140.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ      (3)

  4141.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (3)

  4142.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (3)

  4143.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ      (3)

  4144.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (3)

  4145.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_INJ          (3)

  4146.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ      (3)

  4147.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (3)

  4148.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_INJ          (3)

  4149.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ      (3)

  4150.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)

  4151.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_INJ          (1)

  4152.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ      (1)

  4153.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG          (1)

  4154.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_INJ          (1)

  4155.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ      (1)

  4156.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG          (1)

  4157.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_INJ          (1)

  4158.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ      (1)

  4159.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG          (1)

  4160.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_INJ          (1)

  4161.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ      (1)

  4162.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG          (3)

  4163.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_INJ          (3)

  4164.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ      (3)

  4165.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG          (3)(4)

  4166.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_INJ          (3)(4)

  4167.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ      (3)(4)

  4168.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG          (3)(4)

  4169.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_INJ          (3)(4)

  4170.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ      (3)(4)

  4171.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG          (3)(4)

  4172.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_INJ          (3)(4)

  4173.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ      (3)(4)

  4174.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG          (3)(4)

  4175.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_INJ          (3)(4)

  4176.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ      (3)(4)

  4177.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG          (3)(4)

  4178.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_INJ          (3)(4)

  4179.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ      (3)(4)

  4180.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (3)

  4181.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (3)

  4182.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (3)

  4183.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (3)

  4184.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (3)

  4185.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (3)

  4186.   *         @arg @ref LL_ADC_AWD_CH_VCOMP_REG            (3)

  4187.   *         @arg @ref LL_ADC_AWD_CH_VCOMP_INJ            (3)

  4188.   *         @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ        (3)

  4189.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (3)(5)

  4190.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (3)(5)

  4191.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ      (3)(5)

  4192.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (3)(5)

  4193.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (3)(5)

  4194.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ      (3)(5)

  4195.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG          (3)(5)

  4196.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ          (3)(5)

  4197.   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ      (3)(5)

  4198.   *

  4199.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  4200.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  4201.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  4202.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n

  4203.   *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5

  4204.   * @retval None

  4205.   */

  4206. __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)

  4207. {

  4208.   MODIFY_REG(ADCx->CR1,

  4209.              (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),

  4210.              AWDChannelGroup);

  4211. }

  4212. 

  4213. /**

  4214.   * @brief  Get ADC analog watchdog monitored channel.

  4215.   * @note   Usage of the returned channel number:

  4216.   *         - To reinject this channel into another function LL_ADC_xxx:

  4217.   *           the returned channel number is only partly formatted on definition

  4218.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  4219.   *           with parts of literals LL_ADC_CHANNEL_x or using

  4220.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4221.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  4222.   *           as parameter for another function.

  4223.   *         - To get the channel number in decimal format:

  4224.   *           process the returned value with the helper macro

  4225.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  4226.   *           Applicable only when the analog watchdog is set to monitor

  4227.   *           one channel.

  4228.   * @note   On this STM32 serie, there is only 1 kind of analog watchdog

  4229.   *         instance:

  4230.   *         - AWD standard (instance AWD1):

  4231.   *           - channels monitored: can monitor 1 channel or all channels.

  4232.   *           - groups monitored: ADC groups regular and-or injected.

  4233.   *           - resolution: resolution is not limited (corresponds to

  4234.   *             ADC resolution configured).

  4235.   * @rmtoll CR1      AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n

  4236.   *         CR1      AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n

  4237.   *         CR1      AWD1EN         LL_ADC_GetAnalogWDMonitChannels

  4238.   * @param  ADCx ADC instance

  4239.   * @retval Returned value can be one of the following values:

  4240.   *         @arg @ref LL_ADC_AWD_DISABLE

  4241.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG

  4242.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ

  4243.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  4244.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (2)

  4245.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (2)

  4246.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ       (2)

  4247.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (2)

  4248.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (2)

  4249.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ       (2)

  4250.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (2)

  4251.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (2)

  4252.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ       (2)

  4253.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (2)

  4254.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (2)

  4255.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ       (2)

  4256.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (1)

  4257.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (1)

  4258.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ       (1)

  4259.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (1)

  4260.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (1)

  4261.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ       (1)

  4262.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (2)

  4263.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (2)

  4264.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ       (2)

  4265.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (2)

  4266.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (2)

  4267.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ       (2)

  4268.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (2)

  4269.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (2)

  4270.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ       (2)

  4271.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (2)

  4272.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (2)

  4273.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ       (2)

  4274.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (2)

  4275.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (2)

  4276.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ      (2)

  4277.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (2)

  4278.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (2)

  4279.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ      (2)

  4280.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (2)

  4281.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (2)

  4282.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ      (2)

  4283.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (3)

  4284.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (3)

  4285.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ      (3)

  4286.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (3)

  4287.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (3)

  4288.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ      (3)

  4289.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (3)

  4290.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (3)

  4291.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ      (3)

  4292.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (3)

  4293.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (3)

  4294.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ      (3)

  4295.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (3)

  4296.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (3)

  4297.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ      (3)

  4298.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (3)

  4299.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (3)

  4300.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ      (3)

  4301.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (3)

  4302.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (3)

  4303.   *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ      (3)

  4304.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (3)

  4305.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_INJ          (3)

  4306.   *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ      (3)

  4307.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (3)

  4308.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_INJ          (3)

  4309.   *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ      (3)

  4310.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)

  4311.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_INJ          (1)

  4312.   *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ      (1)

  4313.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG          (1)

  4314.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_INJ          (1)

  4315.   *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ      (1)

  4316.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG          (1)

  4317.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_INJ          (1)

  4318.   *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ      (1)

  4319.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG          (1)

  4320.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_INJ          (1)

  4321.   *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ      (1)

  4322.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG          (3)

  4323.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_INJ          (3)

  4324.   *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ      (3)

  4325.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG          (3)(4)

  4326.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_INJ          (3)(4)

  4327.   *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ      (3)(4)

  4328.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG          (3)(4)

  4329.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_INJ          (3)(4)

  4330.   *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ      (3)(4)

  4331.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG          (3)(4)

  4332.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_INJ          (3)(4)

  4333.   *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ      (3)(4)

  4334.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG          (3)(4)

  4335.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_INJ          (3)(4)

  4336.   *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ      (3)(4)

  4337.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG          (3)(4)

  4338.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_INJ          (3)(4)

  4339.   *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ      (3)(4)

  4340.   *

  4341.   *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n

  4342.   *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n

  4343.   *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n

  4344.   *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.

  4345.   */

  4346. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)

  4347. {

  4348.   return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));

  4349. }

  4350. 

  4351. /**

  4352.   * @brief  Set ADC analog watchdog threshold value of threshold

  4353.   *         high or low.

  4354.   * @note   In case of ADC resolution different of 12 bits,

  4355.   *         analog watchdog thresholds data require a specific shift.

  4356.   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().

  4357.   * @note   On this STM32 serie, there is only 1 kind of analog watchdog

  4358.   *         instance:

  4359.   *         - AWD standard (instance AWD1):

  4360.   *           - channels monitored: can monitor 1 channel or all channels.

  4361.   *           - groups monitored: ADC groups regular and-or injected.

  4362.   *           - resolution: resolution is not limited (corresponds to

  4363.   *             ADC resolution configured).

  4364.   * @rmtoll HTR      HT             LL_ADC_SetAnalogWDThresholds\n

  4365.   *         LTR      LT             LL_ADC_SetAnalogWDThresholds

  4366.   * @param  ADCx ADC instance

  4367.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  4368.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  4369.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  4370.   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF

  4371.   * @retval None

  4372.   */

  4373. __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)

  4374. {

  4375.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);

  4376. 

  4377.   MODIFY_REG(*preg,

  4378.              ADC_HTR_HT,

  4379.              AWDThresholdValue);

  4380. }

  4381. 

  4382. /**

  4383.   * @brief  Get ADC analog watchdog threshold value of threshold high or

  4384.   *         threshold low.

  4385.   * @note   In case of ADC resolution different of 12 bits,

  4386.   *         analog watchdog thresholds data require a specific shift.

  4387.   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().

  4388.   * @rmtoll HTR      HT             LL_ADC_GetAnalogWDThresholds\n

  4389.   *         LTR      LT             LL_ADC_GetAnalogWDThresholds

  4390.   * @param  ADCx ADC instance

  4391.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  4392.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  4393.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  4394.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  4395. */

  4396. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)

  4397. {

  4398.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);

  4399. 

  4400.   return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));

  4401. }

  4402. 

  4403. /**

  4404.   * @}

  4405.   */

  4406. 

  4407. /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance

  4408.   * @{

  4409.   */

  4410. 

  4411. /**

  4412.   * @brief  Enable the selected ADC instance.

  4413.   * @note   On this STM32 serie, after ADC enable, a delay for

  4414.   *         ADC internal analog stabilization is required before performing a

  4415.   *         ADC conversion start.

  4416.   *         Refer to device datasheet, parameter tSTAB.

  4417.   * @note   Due to the latency introduced by the synchronization between

  4418.   *         two clock domains (ADC clock source asynchronous),

  4419.   *         some hardware constraints must be respected:

  4420.   *         - ADC must be enabled (@ref LL_ADC_Enable() ) only

  4421.   *           when ADC is not ready to convert.

  4422.   *         - ADC must be disabled (@ref LL_ADC_Disable() ) only

  4423.   *           when ADC is ready to convert.

  4424.   *         Status of ADC ready to convert can be checked using function

  4425.   *         @ref LL_ADC_IsActiveFlag_ADRDY().

  4426.   * @rmtoll CR2      ADON           LL_ADC_Enable

  4427.   * @param  ADCx ADC instance

  4428.   * @retval None

  4429.   */

  4430. __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)

  4431. {

  4432.   SET_BIT(ADCx->CR2, ADC_CR2_ADON);

  4433. }

  4434. 

  4435. /**

  4436.   * @brief  Disable the selected ADC instance.

  4437.   * @note   Due to the latency introduced by the synchronization between

  4438.   *         two clock domains (ADC clock source asynchronous),

  4439.   *         some hardware constraints must be respected:

  4440.   *         - ADC must be enabled (@ref LL_ADC_Enable() ) only

  4441.   *           when ADC is not ready to convert.

  4442.   *         - ADC must be disabled (@ref LL_ADC_Disable() ) only

  4443.   *           when ADC is ready to convert.

  4444.   *         Status of ADC ready to convert can be checked using function

  4445.   *         @ref LL_ADC_IsActiveFlag_ADRDY().

  4446.   * @rmtoll CR2      ADON           LL_ADC_Disable

  4447.   * @param  ADCx ADC instance

  4448.   * @retval None

  4449.   */

  4450. __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)

  4451. {

  4452.   CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);

  4453. }

  4454. 

  4455. /**

  4456.   * @brief  Get the selected ADC instance enable state.

  4457.   * @rmtoll CR2      ADON           LL_ADC_IsEnabled

  4458.   * @param  ADCx ADC instance

  4459.   * @retval 0: ADC is disabled, 1: ADC is enabled.

  4460.   */

  4461. __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)

  4462. {

  4463.   return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));

  4464. }

  4465. 

  4466. /**

  4467.   * @}

  4468.   */

  4469. 

  4470. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular

  4471.   * @{

  4472.   */

  4473. 

  4474. /**

  4475.   * @brief  Start ADC group regular conversion.

  4476.   * @note   On this STM32 serie, this function is relevant only for

  4477.   *         internal trigger (SW start), not for external trigger:

  4478.   *         - If ADC trigger has been set to software start, ADC conversion

  4479.   *           starts immediately.

  4480.   *         - If ADC trigger has been set to external trigger, ADC conversion

  4481.   *           start must be performed using function

  4482.   *           @ref LL_ADC_REG_StartConversionExtTrig().

  4483.   *           (if external trigger edge would have been set during ADC other

  4484.   *           settings, ADC conversion would start at trigger event

  4485.   *           as soon as ADC is enabled).

  4486.   * @rmtoll CR2      SWSTART        LL_ADC_REG_StartConversionSWStart

  4487.   * @param  ADCx ADC instance

  4488.   * @retval None

  4489.   */

  4490. __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)

  4491. {

  4492.   SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);

  4493. }

  4494. 

  4495. /**

  4496.   * @brief  Start ADC group regular conversion from external trigger.

  4497.   * @note   ADC conversion will start at next trigger event (on the selected

  4498.   *         trigger edge) following the ADC start conversion command.

  4499.   * @note   On this STM32 serie, this function is relevant for

  4500.   *         ADC conversion start from external trigger.

  4501.   *         If internal trigger (SW start) is needed, perform ADC conversion

  4502.   *         start using function @ref LL_ADC_REG_StartConversionSWStart().

  4503.   * @rmtoll CR2      EXTEN          LL_ADC_REG_StartConversionExtTrig

  4504.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  4505.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  4506.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  4507.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  4508.   * @param  ADCx ADC instance

  4509.   * @retval None

  4510.   */

  4511. __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  4512. {

  4513.   SET_BIT(ADCx->CR2, ExternalTriggerEdge);

  4514. }

  4515. 

  4516. /**

  4517.   * @brief  Stop ADC group regular conversion from external trigger.

  4518.   * @note   No more ADC conversion will start at next trigger event

  4519.   *         following the ADC stop conversion command.

  4520.   *         If a conversion is on-going, it will be completed.

  4521.   * @note   On this STM32 serie, there is no specific command

  4522.   *         to stop a conversion on-going or to stop ADC converting

  4523.   *         in continuous mode. These actions can be performed

  4524.   *         using function @ref LL_ADC_Disable().

  4525.   * @rmtoll CR2      EXTEN          LL_ADC_REG_StopConversionExtTrig

  4526.   * @param  ADCx ADC instance

  4527.   * @retval None

  4528.   */

  4529. __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)

  4530. {

  4531.   CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);

  4532. }

  4533. 

  4534. /**

  4535.   * @brief  Get ADC group regular conversion data, range fit for

  4536.   *         all ADC configurations: all ADC resolutions and

  4537.   *         all oversampling increased data width (for devices

  4538.   *         with feature oversampling).

  4539.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32

  4540.   * @param  ADCx ADC instance

  4541.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  4542.   */

  4543. __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)

  4544. {

  4545.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  4546. }

  4547. 

  4548. /**

  4549.   * @brief  Get ADC group regular conversion data, range fit for

  4550.   *         ADC resolution 12 bits.

  4551.   * @note   For devices with feature oversampling: Oversampling

  4552.   *         can increase data width, function for extended range

  4553.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  4554.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12

  4555.   * @param  ADCx ADC instance

  4556.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  4557.   */

  4558. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)

  4559. {

  4560.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  4561. }

  4562. 

  4563. /**

  4564.   * @brief  Get ADC group regular conversion data, range fit for

  4565.   *         ADC resolution 10 bits.

  4566.   * @note   For devices with feature oversampling: Oversampling

  4567.   *         can increase data width, function for extended range

  4568.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  4569.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10

  4570.   * @param  ADCx ADC instance

  4571.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  4572.   */

  4573. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)

  4574. {

  4575.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  4576. }

  4577. 

  4578. /**

  4579.   * @brief  Get ADC group regular conversion data, range fit for

  4580.   *         ADC resolution 8 bits.

  4581.   * @note   For devices with feature oversampling: Oversampling

  4582.   *         can increase data width, function for extended range

  4583.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  4584.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8

  4585.   * @param  ADCx ADC instance

  4586.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  4587.   */

  4588. __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)

  4589. {

  4590.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  4591. }

  4592. 

  4593. /**

  4594.   * @brief  Get ADC group regular conversion data, range fit for

  4595.   *         ADC resolution 6 bits.

  4596.   * @note   For devices with feature oversampling: Oversampling

  4597.   *         can increase data width, function for extended range

  4598.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  4599.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6

  4600.   * @param  ADCx ADC instance

  4601.   * @retval Value between Min_Data=0x00 and Max_Data=0x3F

  4602.   */

  4603. __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)

  4604. {

  4605.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  4606. }

  4607. 

  4608. /**

  4609.   * @}

  4610.   */

  4611. 

  4612. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected

  4613.   * @{

  4614.   */

  4615. 

  4616. /**

  4617.   * @brief  Start ADC group injected conversion.

  4618.   * @note   On this STM32 serie, this function is relevant only for

  4619.   *         internal trigger (SW start), not for external trigger:

  4620.   *         - If ADC trigger has been set to software start, ADC conversion

  4621.   *           starts immediately.

  4622.   *         - If ADC trigger has been set to external trigger, ADC conversion

  4623.   *           start must be performed using function

  4624.   *           @ref LL_ADC_INJ_StartConversionExtTrig().

  4625.   *           (if external trigger edge would have been set during ADC other

  4626.   *           settings, ADC conversion would start at trigger event

  4627.   *           as soon as ADC is enabled).

  4628.   * @rmtoll CR2      JSWSTART       LL_ADC_INJ_StartConversionSWStart

  4629.   * @param  ADCx ADC instance

  4630.   * @retval None

  4631.   */

  4632. __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)

  4633. {

  4634.   SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);

  4635. }

  4636. 

  4637. /**

  4638.   * @brief  Start ADC group injected conversion from external trigger.

  4639.   * @note   ADC conversion will start at next trigger event (on the selected

  4640.   *         trigger edge) following the ADC start conversion command.

  4641.   * @note   On this STM32 serie, this function is relevant for

  4642.   *         ADC conversion start from external trigger.

  4643.   *         If internal trigger (SW start) is needed, perform ADC conversion

  4644.   *         start using function @ref LL_ADC_INJ_StartConversionSWStart().

  4645.   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StartConversionExtTrig

  4646.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  4647.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  4648.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  4649.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  4650.   * @param  ADCx ADC instance

  4651.   * @retval None

  4652.   */

  4653. __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  4654. {

  4655.   SET_BIT(ADCx->CR2, ExternalTriggerEdge);

  4656. }

  4657. 

  4658. /**

  4659.   * @brief  Stop ADC group injected conversion from external trigger.

  4660.   * @note   No more ADC conversion will start at next trigger event

  4661.   *         following the ADC stop conversion command.

  4662.   *         If a conversion is on-going, it will be completed.

  4663.   * @note   On this STM32 serie, there is no specific command

  4664.   *         to stop a conversion on-going or to stop ADC converting

  4665.   *         in continuous mode. These actions can be performed

  4666.   *         using function @ref LL_ADC_Disable().

  4667.   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StopConversionExtTrig

  4668.   * @param  ADCx ADC instance

  4669.   * @retval None

  4670.   */

  4671. __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)

  4672. {

  4673.   CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);

  4674. }

  4675. 

  4676. /**

  4677.   * @brief  Get ADC group regular conversion data, range fit for

  4678.   *         all ADC configurations: all ADC resolutions and

  4679.   *         all oversampling increased data width (for devices

  4680.   *         with feature oversampling).

  4681.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n

  4682.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n

  4683.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n

  4684.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32

  4685.   * @param  ADCx ADC instance

  4686.   * @param  Rank This parameter can be one of the following values:

  4687.   *         @arg @ref LL_ADC_INJ_RANK_1

  4688.   *         @arg @ref LL_ADC_INJ_RANK_2

  4689.   *         @arg @ref LL_ADC_INJ_RANK_3

  4690.   *         @arg @ref LL_ADC_INJ_RANK_4

  4691.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  4692.   */

  4693. __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)

  4694. {

  4695.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4696. 

  4697.   return (uint32_t)(READ_BIT(*preg,

  4698.                              ADC_JDR1_JDATA)

  4699.                    );

  4700. }

  4701. 

  4702. /**

  4703.   * @brief  Get ADC group injected conversion data, range fit for

  4704.   *         ADC resolution 12 bits.

  4705.   * @note   For devices with feature oversampling: Oversampling

  4706.   *         can increase data width, function for extended range

  4707.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  4708.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n

  4709.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n

  4710.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n

  4711.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12

  4712.   * @param  ADCx ADC instance

  4713.   * @param  Rank This parameter can be one of the following values:

  4714.   *         @arg @ref LL_ADC_INJ_RANK_1

  4715.   *         @arg @ref LL_ADC_INJ_RANK_2

  4716.   *         @arg @ref LL_ADC_INJ_RANK_3

  4717.   *         @arg @ref LL_ADC_INJ_RANK_4

  4718.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  4719.   */

  4720. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)

  4721. {

  4722.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4723. 

  4724.   return (uint16_t)(READ_BIT(*preg,

  4725.                              ADC_JDR1_JDATA)

  4726.                    );

  4727. }

  4728. 

  4729. /**

  4730.   * @brief  Get ADC group injected conversion data, range fit for

  4731.   *         ADC resolution 10 bits.

  4732.   * @note   For devices with feature oversampling: Oversampling

  4733.   *         can increase data width, function for extended range

  4734.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  4735.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n

  4736.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n

  4737.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n

  4738.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10

  4739.   * @param  ADCx ADC instance

  4740.   * @param  Rank This parameter can be one of the following values:

  4741.   *         @arg @ref LL_ADC_INJ_RANK_1

  4742.   *         @arg @ref LL_ADC_INJ_RANK_2

  4743.   *         @arg @ref LL_ADC_INJ_RANK_3

  4744.   *         @arg @ref LL_ADC_INJ_RANK_4

  4745.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  4746.   */

  4747. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)

  4748. {

  4749.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4750. 

  4751.   return (uint16_t)(READ_BIT(*preg,

  4752.                              ADC_JDR1_JDATA)

  4753.                    );

  4754. }

  4755. 

  4756. /**

  4757.   * @brief  Get ADC group injected conversion data, range fit for

  4758.   *         ADC resolution 8 bits.

  4759.   * @note   For devices with feature oversampling: Oversampling

  4760.   *         can increase data width, function for extended range

  4761.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  4762.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n

  4763.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n

  4764.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n

  4765.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8

  4766.   * @param  ADCx ADC instance

  4767.   * @param  Rank This parameter can be one of the following values:

  4768.   *         @arg @ref LL_ADC_INJ_RANK_1

  4769.   *         @arg @ref LL_ADC_INJ_RANK_2

  4770.   *         @arg @ref LL_ADC_INJ_RANK_3

  4771.   *         @arg @ref LL_ADC_INJ_RANK_4

  4772.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  4773.   */

  4774. __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)

  4775. {

  4776.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4777. 

  4778.   return (uint8_t)(READ_BIT(*preg,

  4779.                             ADC_JDR1_JDATA)

  4780.                   );

  4781. }

  4782. 

  4783. /**

  4784.   * @brief  Get ADC group injected conversion data, range fit for

  4785.   *         ADC resolution 6 bits.

  4786.   * @note   For devices with feature oversampling: Oversampling

  4787.   *         can increase data width, function for extended range

  4788.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  4789.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n

  4790.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n

  4791.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n

  4792.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6

  4793.   * @param  ADCx ADC instance

  4794.   * @param  Rank This parameter can be one of the following values:

  4795.   *         @arg @ref LL_ADC_INJ_RANK_1

  4796.   *         @arg @ref LL_ADC_INJ_RANK_2

  4797.   *         @arg @ref LL_ADC_INJ_RANK_3

  4798.   *         @arg @ref LL_ADC_INJ_RANK_4

  4799.   * @retval Value between Min_Data=0x00 and Max_Data=0x3F

  4800.   */

  4801. __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)

  4802. {

  4803.   uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4804. 

  4805.   return (uint8_t)(READ_BIT(*preg,

  4806.                             ADC_JDR1_JDATA)

  4807.                   );

  4808. }

  4809. 

  4810. /**

  4811.   * @}

  4812.   */

  4813. 

  4814. /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management

  4815.   * @{

  4816.   */

  4817. 

  4818. /**

  4819.   * @brief  Get flag ADC ready.

  4820.   * @rmtoll SR       ADONS          LL_ADC_IsActiveFlag_ADRDY

  4821.   * @param  ADCx ADC instance

  4822.   * @retval State of bit (1 or 0).

  4823.   */

  4824. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)

  4825. {

  4826.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));

  4827. }

  4828. 

  4829. /**

  4830.   * @brief  Get flag ADC group regular end of unitary conversion

  4831.   *         or end of sequence conversions, depending on

  4832.   *         ADC configuration.

  4833.   * @note   To configure flag of end of conversion,

  4834.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4835.   * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_EOCS

  4836.   * @param  ADCx ADC instance

  4837.   * @retval State of bit (1 or 0).

  4838.   */

  4839. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)

  4840. {

  4841.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));

  4842. }

  4843. 

  4844. /**

  4845.   * @brief  Get flag ADC group regular overrun.

  4846.   * @rmtoll SR       OVR            LL_ADC_IsActiveFlag_OVR

  4847.   * @param  ADCx ADC instance

  4848.   * @retval State of bit (1 or 0).

  4849.   */

  4850. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)

  4851. {

  4852.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));

  4853. }

  4854. 

  4855. 

  4856. /**

  4857.   * @brief  Get flag ADC group injected end of sequence conversions.

  4858.   * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_JEOS

  4859.   * @param  ADCx ADC instance

  4860.   * @retval State of bit (1 or 0).

  4861.   */

  4862. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)

  4863. {

  4864.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4865.   /*       end of unitary conversion.                                         */

  4866.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4867.   /*       in other STM32 families).                                          */

  4868.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));

  4869. }

  4870. 

  4871. /**

  4872.   * @brief  Get flag ADC analog watchdog 1 flag

  4873.   * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_AWD1

  4874.   * @param  ADCx ADC instance

  4875.   * @retval State of bit (1 or 0).

  4876.   */

  4877. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)

  4878. {

  4879.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));

  4880. }

  4881. 

  4882. /**

  4883.   * @brief  Clear flag ADC group regular end of unitary conversion

  4884.   *         or end of sequence conversions, depending on

  4885.   *         ADC configuration.

  4886.   * @note   To configure flag of end of conversion,

  4887.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4888.   * @rmtoll SR       EOC            LL_ADC_ClearFlag_EOCS

  4889.   * @param  ADCx ADC instance

  4890.   * @retval None

  4891.   */

  4892. __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)

  4893. {

  4894.   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);

  4895. }

  4896. 

  4897. /**

  4898.   * @brief  Clear flag ADC group regular overrun.

  4899.   * @rmtoll SR       OVR            LL_ADC_ClearFlag_OVR

  4900.   * @param  ADCx ADC instance

  4901.   * @retval None

  4902.   */

  4903. __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)

  4904. {

  4905.   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);

  4906. }

  4907. 

  4908. 

  4909. /**

  4910.   * @brief  Clear flag ADC group injected end of sequence conversions.

  4911.   * @rmtoll SR       JEOC           LL_ADC_ClearFlag_JEOS

  4912.   * @param  ADCx ADC instance

  4913.   * @retval None

  4914.   */

  4915. __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)

  4916. {

  4917.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4918.   /*       end of unitary conversion.                                         */

  4919.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4920.   /*       in other STM32 families).                                          */

  4921.   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);

  4922. }

  4923. 

  4924. /**

  4925.   * @brief  Clear flag ADC analog watchdog 1.

  4926.   * @rmtoll SR       AWD            LL_ADC_ClearFlag_AWD1

  4927.   * @param  ADCx ADC instance

  4928.   * @retval None

  4929.   */

  4930. __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)

  4931. {

  4932.   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);

  4933. }

  4934. 

  4935. /**

  4936.   * @}

  4937.   */

  4938. 

  4939. /** @defgroup ADC_LL_EF_IT_Management ADC IT management

  4940.   * @{

  4941.   */

  4942. 

  4943. /**

  4944.   * @brief  Enable interruption ADC group regular end of unitary conversion

  4945.   *         or end of sequence conversions, depending on

  4946.   *         ADC configuration.

  4947.   * @note   To configure flag of end of conversion,

  4948.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4949.   * @rmtoll CR1      EOCIE          LL_ADC_EnableIT_EOCS

  4950.   * @param  ADCx ADC instance

  4951.   * @retval None

  4952.   */

  4953. __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)

  4954. {

  4955.   SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);

  4956. }

  4957. 

  4958. /**

  4959.   * @brief  Enable ADC group regular interruption overrun.

  4960.   * @rmtoll CR1      OVRIE          LL_ADC_EnableIT_OVR

  4961.   * @param  ADCx ADC instance

  4962.   * @retval None

  4963.   */

  4964. __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)

  4965. {

  4966.   SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);

  4967. }

  4968. 

  4969. 

  4970. /**

  4971.   * @brief  Enable interruption ADC group injected end of sequence conversions.

  4972.   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS

  4973.   * @param  ADCx ADC instance

  4974.   * @retval None

  4975.   */

  4976. __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)

  4977. {

  4978.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4979.   /*       end of unitary conversion.                                         */

  4980.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4981.   /*       in other STM32 families).                                          */

  4982.   SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);

  4983. }

  4984. 

  4985. /**

  4986.   * @brief  Enable interruption ADC analog watchdog 1.

  4987.   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1

  4988.   * @param  ADCx ADC instance

  4989.   * @retval None

  4990.   */

  4991. __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)

  4992. {

  4993.   SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);

  4994. }

  4995. 

  4996. /**

  4997.   * @brief  Disable interruption ADC group regular end of unitary conversion

  4998.   *         or end of sequence conversions, depending on

  4999.   *         ADC configuration.

  5000.   * @note   To configure flag of end of conversion,

  5001.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  5002.   * @rmtoll CR1      EOCIE          LL_ADC_DisableIT_EOCS

  5003.   * @param  ADCx ADC instance

  5004.   * @retval None

  5005.   */

  5006. __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)

  5007. {

  5008.   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);

  5009. }

  5010. 

  5011. /**

  5012.   * @brief  Disable interruption ADC group regular overrun.

  5013.   * @rmtoll CR1      OVRIE          LL_ADC_DisableIT_OVR

  5014.   * @param  ADCx ADC instance

  5015.   * @retval None

  5016.   */

  5017. __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)

  5018. {

  5019.   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);

  5020. }

  5021. 

  5022. 

  5023. /**

  5024.   * @brief  Disable interruption ADC group injected end of sequence conversions.

  5025.   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS

  5026.   * @param  ADCx ADC instance

  5027.   * @retval None

  5028.   */

  5029. __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)

  5030. {

  5031.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  5032.   /*       end of unitary conversion.                                         */

  5033.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  5034.   /*       in other STM32 families).                                          */

  5035.   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);

  5036. }

  5037. 

  5038. /**

  5039.   * @brief  Disable interruption ADC analog watchdog 1.

  5040.   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1

  5041.   * @param  ADCx ADC instance

  5042.   * @retval None

  5043.   */

  5044. __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)

  5045. {

  5046.   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);

  5047. }

  5048. 

  5049. /**

  5050.   * @brief  Get state of interruption ADC group regular end of unitary conversion

  5051.   *         or end of sequence conversions, depending on

  5052.   *         ADC configuration.

  5053.   * @note   To configure flag of end of conversion,

  5054.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  5055.   *         (0: interrupt disabled, 1: interrupt enabled)

  5056.   * @rmtoll CR1      EOCIE          LL_ADC_IsEnabledIT_EOCS

  5057.   * @param  ADCx ADC instance

  5058.   * @retval State of bit (1 or 0).

  5059.   */

  5060. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)

  5061. {

  5062.   return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));

  5063. }

  5064. 

  5065. /**

  5066.   * @brief  Get state of interruption ADC group regular overrun

  5067.   *         (0: interrupt disabled, 1: interrupt enabled).

  5068.   * @rmtoll CR1      OVRIE          LL_ADC_IsEnabledIT_OVR

  5069.   * @param  ADCx ADC instance

  5070.   * @retval State of bit (1 or 0).

  5071.   */

  5072. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)

  5073. {

  5074.   return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));

  5075. }

  5076. 

  5077. 

  5078. /**

  5079.   * @brief  Get state of interruption ADC group injected end of sequence conversions

  5080.   *         (0: interrupt disabled, 1: interrupt enabled).

  5081.   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS

  5082.   * @param  ADCx ADC instance

  5083.   * @retval State of bit (1 or 0).

  5084.   */

  5085. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)

  5086. {

  5087.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  5088.   /*       end of unitary conversion.                                         */

  5089.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  5090.   /*       in other STM32 families).                                          */

  5091.   return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));

  5092. }

  5093. 

  5094. /**

  5095.   * @brief  Get state of interruption ADC analog watchdog 1

  5096.   *         (0: interrupt disabled, 1: interrupt enabled).

  5097.   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1

  5098.   * @param  ADCx ADC instance

  5099.   * @retval State of bit (1 or 0).

  5100.   */

  5101. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)

  5102. {

  5103.   return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));

  5104. }

  5105. 

  5106. /**

  5107.   * @}

  5108.   */

  5109. 

  5110. #if defined(USE_FULL_LL_DRIVER)

  5111. /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions

  5112.   * @{

  5113.   */

  5114. 

  5115. /* Initialization of some features of ADC common parameters and multimode */

  5116. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);

  5117. ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  5118. void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  5119. 

  5120. /* De-initialization of ADC instance, ADC group regular and ADC group injected */

  5121. /* (availability of ADC group injected depends on STM32 families) */

  5122. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);

  5123. 

  5124. /* Initialization of some features of ADC instance */

  5125. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);

  5126. void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);

  5127. 

  5128. /* Initialization of some features of ADC instance and ADC group regular */

  5129. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  5130. void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  5131. 

  5132. /* Initialization of some features of ADC instance and ADC group injected */

  5133. ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  5134. void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  5135. 

  5136. /**

  5137.   * @}

  5138.   */

  5139. #endif /* USE_FULL_LL_DRIVER */

  5140. 

  5141. /**

  5142.   * @}

  5143.   */

  5144. 

  5145. /**

  5146.   * @}

  5147.   */

  5148. 

  5149. #endif /* ADC1 */

  5150. 

  5151. /**

  5152.   * @}

  5153.   */

  5154. 

  5155. #ifdef __cplusplus

  5156. }

  5157. #endif

  5158. 

  5159. #endif /* __STM32L1xx_LL_ADC_H */

  5160. 

  5161. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/