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  1. /**
  2. ******************************************************************************
  3. * @file stm32f0xx_hal_i2s.c
  4. * @author MCD Application Team
  5. * @brief I2S HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Integrated Interchip Sound (I2S) peripheral:
  8. * + Initialization and de-initialization functions
  9. * + IO operation functions
  10. * + Peripheral State and Errors functions
  11. @verbatim
  12. ===============================================================================
  13. ##### How to use this driver #####
  14. ===============================================================================
  15. [..]
  16. The I2S HAL driver can be used as follow:
  17. (#) Declare a I2S_HandleTypeDef handle structure.
  18. (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
  19. (##) Enable the SPIx interface clock.
  20. (##) I2S pins configuration:
  21. (+++) Enable the clock for the I2S GPIOs.
  22. (+++) Configure these I2S pins as alternate function pull-up.
  23. (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
  24. and HAL_I2S_Receive_IT() APIs).
  25. (+++) Configure the I2Sx interrupt priority.
  26. (+++) Enable the NVIC I2S IRQ handle.
  27. (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
  28. and HAL_I2S_Receive_DMA() APIs:
  29. (+++) Declare a DMA handle structure for the Tx/Rx Channel.
  30. (+++) Enable the DMAx interface clock.
  31. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
  32. (+++) Configure the DMA Tx/Rx Channel.
  33. (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
  34. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
  35. DMA Tx/Rx Channel.
  36. (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
  37. using HAL_I2S_Init() function.
  38. -@- The specific I2S interrupts (Transmission complete interrupt,
  39. RXNE interrupt and Error Interrupts) will be managed using the macros
  40. __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
  41. -@- Make sure that either:
  42. (+@) External clock source is configured after setting correctly
  43. the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file.
  44. (#) Three mode of operations are available within this driver :
  45. *** Polling mode IO operation ***
  46. =================================
  47. [..]
  48. (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
  49. (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
  50. *** Interrupt mode IO operation ***
  51. ===================================
  52. [..]
  53. (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
  54. (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  55. add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  56. (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  57. add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  58. (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
  59. (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  60. add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  61. (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  62. add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  63. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  64. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  65. *** DMA mode IO operation ***
  66. ==============================
  67. [..]
  68. (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
  69. (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  70. add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  71. (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  72. add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  73. (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
  74. (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  75. add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  76. (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  77. add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  78. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  79. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  80. (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
  81. (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
  82. (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
  83. *** I2S HAL driver macros list ***
  84. =============================================
  85. [..]
  86. Below the list of most used macros in I2S HAL driver.
  87. (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
  88. (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
  89. (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
  90. (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
  91. (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
  92. [..]
  93. (@) You can refer to the I2S HAL driver header file for more useful macros
  94. @endverbatim
  95. ******************************************************************************
  96. * @attention
  97. *
  98. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  99. *
  100. * Redistribution and use in source and binary forms, with or without modification,
  101. * are permitted provided that the following conditions are met:
  102. * 1. Redistributions of source code must retain the above copyright notice,
  103. * this list of conditions and the following disclaimer.
  104. * 2. Redistributions in binary form must reproduce the above copyright notice,
  105. * this list of conditions and the following disclaimer in the documentation
  106. * and/or other materials provided with the distribution.
  107. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  108. * may be used to endorse or promote products derived from this software
  109. * without specific prior written permission.
  110. *
  111. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  112. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  113. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  114. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  115. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  116. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  117. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  118. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  119. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  120. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  121. *
  122. ******************************************************************************
  123. */
  124. /* Includes ------------------------------------------------------------------*/
  125. #include "stm32f0xx_hal.h"
  126. #ifdef HAL_I2S_MODULE_ENABLED
  127. #if defined(STM32F031x6) || defined(STM32F038xx) || \
  128. defined(STM32F051x8) || defined(STM32F058xx) || \
  129. defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
  130. defined(STM32F042x6) || defined(STM32F048xx) || \
  131. defined(STM32F091xC) || defined(STM32F098xx)
  132. /** @addtogroup STM32F0xx_HAL_Driver
  133. * @{
  134. */
  135. /** @defgroup I2S I2S
  136. * @brief I2S HAL module driver
  137. * @{
  138. */
  139. /* Private typedef -----------------------------------------------------------*/
  140. /* Private define ------------------------------------------------------------*/
  141. /* Private macro -------------------------------------------------------------*/
  142. /* Private variables ---------------------------------------------------------*/
  143. /* Private function prototypes -----------------------------------------------*/
  144. /** @defgroup I2S_Private_Functions I2S Private Functions
  145. * @{
  146. */
  147. static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
  148. static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
  149. static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
  150. static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
  151. static void I2S_DMAError(DMA_HandleTypeDef *hdma);
  152. static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
  153. static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
  154. static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
  155. /**
  156. * @}
  157. */
  158. /* Exported functions ---------------------------------------------------------*/
  159. /** @defgroup I2S_Exported_Functions I2S Exported Functions
  160. * @{
  161. */
  162. /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
  163. * @brief Initialization and Configuration functions
  164. *
  165. @verbatim
  166. ===============================================================================
  167. ##### Initialization and de-initialization functions #####
  168. ===============================================================================
  169. [..] This subsection provides a set of functions allowing to initialize and
  170. de-initialiaze the I2Sx peripheral in simplex mode:
  171. (+) User must Implement HAL_I2S_MspInit() function in which he configures
  172. all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
  173. (+) Call the function HAL_I2S_Init() to configure the selected device with
  174. the selected configuration:
  175. (++) Mode
  176. (++) Standard
  177. (++) Data Format
  178. (++) MCLK Output
  179. (++) Audio frequency
  180. (++) Polarity
  181. (+) Call the function HAL_I2S_DeInit() to restore the default configuration
  182. of the selected I2Sx periperal.
  183. @endverbatim
  184. * @{
  185. */
  186. /**
  187. * @brief Initializes the I2S according to the specified parameters
  188. * in the I2S_InitTypeDef and create the associated handle.
  189. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  190. * the configuration information for I2S module
  191. * @retval HAL status
  192. */
  193. HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
  194. {
  195. uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
  196. uint32_t tmp = 0U, i2sclk = 0U;
  197. /* Check the I2S handle allocation */
  198. if(hi2s == NULL)
  199. {
  200. return HAL_ERROR;
  201. }
  202. /* Check the I2S parameters */
  203. assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
  204. assert_param(IS_I2S_MODE(hi2s->Init.Mode));
  205. assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
  206. assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
  207. assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
  208. assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
  209. assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
  210. if(hi2s->State == HAL_I2S_STATE_RESET)
  211. {
  212. /* Allocate lock resource and initialize it */
  213. hi2s->Lock = HAL_UNLOCKED;
  214. /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
  215. HAL_I2S_MspInit(hi2s);
  216. }
  217. hi2s->State = HAL_I2S_STATE_BUSY;
  218. /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
  219. /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  220. hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
  221. SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
  222. SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
  223. hi2s->Instance->I2SPR = 0x0002U;
  224. /* Get the I2SCFGR register value */
  225. tmpreg = hi2s->Instance->I2SCFGR;
  226. /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
  227. if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
  228. {
  229. i2sodd = (uint16_t)0U;
  230. i2sdiv = (uint16_t)2U;
  231. }
  232. /* If the requested audio frequency is not the default, compute the prescaler */
  233. else
  234. {
  235. /* Check the frame length (For the Prescaler computing) *******************/
  236. if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
  237. {
  238. /* Packet length is 16 bits */
  239. packetlength = 1U;
  240. }
  241. else
  242. {
  243. /* Packet length is 32 bits */
  244. packetlength = 2U;
  245. }
  246. /* Get I2S source Clock frequency ****************************************/
  247. i2sclk = HAL_RCC_GetSysClockFreq();
  248. /* Compute the Real divider depending on the MCLK output state, with a floating point */
  249. if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
  250. {
  251. /* MCLK output is enabled */
  252. tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
  253. }
  254. else
  255. {
  256. /* MCLK output is disabled */
  257. tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
  258. }
  259. /* Remove the flatting point */
  260. tmp = tmp / 10U;
  261. /* Check the parity of the divider */
  262. i2sodd = (uint32_t)(tmp & 1U);
  263. /* Compute the i2sdiv prescaler */
  264. i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
  265. /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
  266. i2sodd = (uint32_t) (i2sodd << 8U);
  267. }
  268. /* Test if the divider is 1 or 0 or greater than 0xFF */
  269. if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
  270. {
  271. /* Set the default values */
  272. i2sdiv = 2U;
  273. i2sodd = 0U;
  274. }
  275. /* Write to SPIx I2SPR register the computed value */
  276. hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
  277. /* Configure the I2S with the I2S_InitStruct values */
  278. tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
  279. /* Write to SPIx I2SCFGR */
  280. hi2s->Instance->I2SCFGR = tmpreg;
  281. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  282. hi2s->State= HAL_I2S_STATE_READY;
  283. return HAL_OK;
  284. }
  285. /**
  286. * @brief DeInitializes the I2S peripheral
  287. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  288. * the configuration information for I2S module
  289. * @retval HAL status
  290. */
  291. HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
  292. {
  293. /* Check the I2S handle allocation */
  294. if(hi2s == NULL)
  295. {
  296. return HAL_ERROR;
  297. }
  298. /* Check the parameters */
  299. assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
  300. hi2s->State = HAL_I2S_STATE_BUSY;
  301. /* Disable the I2S Peripheral Clock */
  302. __HAL_I2S_DISABLE(hi2s);
  303. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  304. HAL_I2S_MspDeInit(hi2s);
  305. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  306. hi2s->State = HAL_I2S_STATE_RESET;
  307. /* Release Lock */
  308. __HAL_UNLOCK(hi2s);
  309. return HAL_OK;
  310. }
  311. /**
  312. * @brief I2S MSP Init
  313. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  314. * the configuration information for I2S module
  315. * @retval None
  316. */
  317. __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
  318. {
  319. /* Prevent unused argument(s) compilation warning */
  320. UNUSED(hi2s);
  321. /* NOTE : This function Should not be modified, when the callback is needed,
  322. the HAL_I2S_MspInit could be implemented in the user file
  323. */
  324. }
  325. /**
  326. * @brief I2S MSP DeInit
  327. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  328. * the configuration information for I2S module
  329. * @retval None
  330. */
  331. __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
  332. {
  333. /* Prevent unused argument(s) compilation warning */
  334. UNUSED(hi2s);
  335. /* NOTE : This function Should not be modified, when the callback is needed,
  336. the HAL_I2S_MspDeInit could be implemented in the user file
  337. */
  338. }
  339. /**
  340. * @}
  341. */
  342. /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
  343. * @brief Data transfers functions
  344. *
  345. @verbatim
  346. ===============================================================================
  347. ##### IO operation functions #####
  348. ===============================================================================
  349. [..]
  350. This subsection provides a set of functions allowing to manage the I2S data
  351. transfers.
  352. (#) There are two modes of transfer:
  353. (++) Blocking mode : The communication is performed in the polling mode.
  354. The status of all data processing is returned by the same function
  355. after finishing transfer.
  356. (++) No-Blocking mode : The communication is performed using Interrupts
  357. or DMA. These functions return the status of the transfer startup.
  358. The end of the data processing will be indicated through the
  359. dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
  360. using DMA mode.
  361. (#) Blocking mode functions are :
  362. (++) HAL_I2S_Transmit()
  363. (++) HAL_I2S_Receive()
  364. (#) No-Blocking mode functions with Interrupt are :
  365. (++) HAL_I2S_Transmit_IT()
  366. (++) HAL_I2S_Receive_IT()
  367. (#) No-Blocking mode functions with DMA are :
  368. (++) HAL_I2S_Transmit_DMA()
  369. (++) HAL_I2S_Receive_DMA()
  370. (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
  371. (++) HAL_I2S_TxCpltCallback()
  372. (++) HAL_I2S_RxCpltCallback()
  373. (++) HAL_I2S_ErrorCallback()
  374. @endverbatim
  375. * @{
  376. */
  377. /**
  378. * @brief Transmit an amount of data in blocking mode
  379. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  380. * the configuration information for I2S module
  381. * @param pData a 16-bit pointer to data buffer.
  382. * @param Size number of data sample to be sent:
  383. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  384. * configuration phase, the Size parameter means the number of 16-bit data length
  385. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  386. * the Size parameter means the number of 16-bit data length.
  387. * @param Timeout Timeout duration
  388. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  389. * between Master and Slave(example: audio streaming).
  390. * @retval HAL status
  391. */
  392. HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
  393. {
  394. if((pData == NULL ) || (Size == 0U))
  395. {
  396. return HAL_ERROR;
  397. }
  398. /* Process Locked */
  399. __HAL_LOCK(hi2s);
  400. if(hi2s->State == HAL_I2S_STATE_READY)
  401. {
  402. if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
  403. ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
  404. {
  405. hi2s->TxXferSize = (Size << 1U);
  406. hi2s->TxXferCount = (Size << 1U);
  407. }
  408. else
  409. {
  410. hi2s->TxXferSize = Size;
  411. hi2s->TxXferCount = Size;
  412. }
  413. /* Set state and reset error code */
  414. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  415. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  416. hi2s->pTxBuffPtr = pData;
  417. /* Check if the I2S is already enabled */
  418. if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  419. {
  420. /* Enable I2S peripheral */
  421. __HAL_I2S_ENABLE(hi2s);
  422. }
  423. while(hi2s->TxXferCount > 0U)
  424. {
  425. /* Wait until TXE flag is set */
  426. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
  427. {
  428. return HAL_TIMEOUT;
  429. }
  430. hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
  431. hi2s->TxXferCount--;
  432. }
  433. /* Wait until TXE flag is set, to confirm the end of the transcation */
  434. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
  435. {
  436. return HAL_TIMEOUT;
  437. }
  438. /* Wait until Busy flag is reset */
  439. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
  440. {
  441. return HAL_TIMEOUT;
  442. }
  443. hi2s->State = HAL_I2S_STATE_READY;
  444. /* Process Unlocked */
  445. __HAL_UNLOCK(hi2s);
  446. return HAL_OK;
  447. }
  448. else
  449. {
  450. /* Process Unlocked */
  451. __HAL_UNLOCK(hi2s);
  452. return HAL_BUSY;
  453. }
  454. }
  455. /**
  456. * @brief Receive an amount of data in blocking mode
  457. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  458. * the configuration information for I2S module
  459. * @param pData a 16-bit pointer to data buffer.
  460. * @param Size number of data sample to be sent:
  461. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  462. * configuration phase, the Size parameter means the number of 16-bit data length
  463. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  464. * the Size parameter means the number of 16-bit data length.
  465. * @param Timeout Timeout duration
  466. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  467. * between Master and Slave(example: audio streaming).
  468. * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
  469. * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
  470. * @retval HAL status
  471. */
  472. HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
  473. {
  474. if((pData == NULL ) || (Size == 0U))
  475. {
  476. return HAL_ERROR;
  477. }
  478. /* Process Locked */
  479. __HAL_LOCK(hi2s);
  480. if(hi2s->State == HAL_I2S_STATE_READY)
  481. {
  482. if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
  483. ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
  484. {
  485. hi2s->RxXferSize = (Size << 1U);
  486. hi2s->RxXferCount = (Size << 1U);
  487. }
  488. else
  489. {
  490. hi2s->RxXferSize = Size;
  491. hi2s->RxXferCount = Size;
  492. }
  493. /* Set state and reset error code */
  494. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  495. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  496. hi2s->pRxBuffPtr = pData;
  497. /* Check if the I2S is already enabled */
  498. if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  499. {
  500. /* Enable I2S peripheral */
  501. __HAL_I2S_ENABLE(hi2s);
  502. }
  503. /* Receive data */
  504. while(hi2s->RxXferCount > 0U)
  505. {
  506. /* Wait until RXNE flag is set */
  507. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
  508. {
  509. return HAL_TIMEOUT;
  510. }
  511. (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
  512. hi2s->RxXferCount--;
  513. }
  514. hi2s->State = HAL_I2S_STATE_READY;
  515. /* Process Unlocked */
  516. __HAL_UNLOCK(hi2s);
  517. return HAL_OK;
  518. }
  519. else
  520. {
  521. /* Process Unlocked */
  522. __HAL_UNLOCK(hi2s);
  523. return HAL_BUSY;
  524. }
  525. }
  526. /**
  527. * @brief Transmit an amount of data in non-blocking mode with Interrupt
  528. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  529. * the configuration information for I2S module
  530. * @param pData a 16-bit pointer to data buffer.
  531. * @param Size number of data sample to be sent:
  532. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  533. * configuration phase, the Size parameter means the number of 16-bit data length
  534. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  535. * the Size parameter means the number of 16-bit data length.
  536. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  537. * between Master and Slave(example: audio streaming).
  538. * @retval HAL status
  539. */
  540. HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  541. {
  542. if((pData == NULL) || (Size == 0U))
  543. {
  544. return HAL_ERROR;
  545. }
  546. /* Process Locked */
  547. __HAL_LOCK(hi2s);
  548. if(hi2s->State == HAL_I2S_STATE_READY)
  549. {
  550. hi2s->pTxBuffPtr = pData;
  551. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  552. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  553. if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
  554. ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
  555. {
  556. hi2s->TxXferSize = (Size << 1U);
  557. hi2s->TxXferCount = (Size << 1U);
  558. }
  559. else
  560. {
  561. hi2s->TxXferSize = Size;
  562. hi2s->TxXferCount = Size;
  563. }
  564. /* Enable TXE and ERR interrupt */
  565. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  566. /* Check if the I2S is already enabled */
  567. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  568. {
  569. /* Enable I2S peripheral */
  570. __HAL_I2S_ENABLE(hi2s);
  571. }
  572. /* Process Unlocked */
  573. __HAL_UNLOCK(hi2s);
  574. return HAL_OK;
  575. }
  576. else
  577. {
  578. /* Process Unlocked */
  579. __HAL_UNLOCK(hi2s);
  580. return HAL_BUSY;
  581. }
  582. }
  583. /**
  584. * @brief Receive an amount of data in non-blocking mode with Interrupt
  585. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  586. * the configuration information for I2S module
  587. * @param pData a 16-bit pointer to the Receive data buffer.
  588. * @param Size number of data sample to be sent:
  589. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  590. * configuration phase, the Size parameter means the number of 16-bit data length
  591. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  592. * the Size parameter means the number of 16-bit data length.
  593. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  594. * between Master and Slave(example: audio streaming).
  595. * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
  596. * between Master and Slave otherwise the I2S interrupt should be optimized.
  597. * @retval HAL status
  598. */
  599. HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  600. {
  601. if((pData == NULL) || (Size == 0U))
  602. {
  603. return HAL_ERROR;
  604. }
  605. /* Process Locked */
  606. __HAL_LOCK(hi2s);
  607. if(hi2s->State == HAL_I2S_STATE_READY)
  608. {
  609. hi2s->pRxBuffPtr = pData;
  610. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  611. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  612. if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
  613. ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
  614. {
  615. hi2s->RxXferSize = (Size << 1U);
  616. hi2s->RxXferCount = (Size << 1U);
  617. }
  618. else
  619. {
  620. hi2s->RxXferSize = Size;
  621. hi2s->RxXferCount = Size;
  622. }
  623. /* Enable TXE and ERR interrupt */
  624. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  625. /* Check if the I2S is already enabled */
  626. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  627. {
  628. /* Enable I2S peripheral */
  629. __HAL_I2S_ENABLE(hi2s);
  630. }
  631. /* Process Unlocked */
  632. __HAL_UNLOCK(hi2s);
  633. return HAL_OK;
  634. }
  635. else
  636. {
  637. /* Process Unlocked */
  638. __HAL_UNLOCK(hi2s);
  639. return HAL_BUSY;
  640. }
  641. }
  642. /**
  643. * @brief Transmit an amount of data in non-blocking mode with DMA
  644. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  645. * the configuration information for I2S module
  646. * @param pData a 16-bit pointer to the Transmit data buffer.
  647. * @param Size number of data sample to be sent:
  648. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  649. * configuration phase, the Size parameter means the number of 16-bit data length
  650. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  651. * the Size parameter means the number of 16-bit data length.
  652. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  653. * between Master and Slave(example: audio streaming).
  654. * @retval HAL status
  655. */
  656. HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  657. {
  658. if((pData == NULL) || (Size == 0U))
  659. {
  660. return HAL_ERROR;
  661. }
  662. /* Process Locked */
  663. __HAL_LOCK(hi2s);
  664. if(hi2s->State == HAL_I2S_STATE_READY)
  665. {
  666. hi2s->pTxBuffPtr = pData;
  667. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  668. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  669. if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
  670. ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
  671. {
  672. hi2s->TxXferSize = (Size << 1U);
  673. hi2s->TxXferCount = (Size << 1U);
  674. }
  675. else
  676. {
  677. hi2s->TxXferSize = Size;
  678. hi2s->TxXferCount = Size;
  679. }
  680. /* Set the I2S Tx DMA Half transfert complete callback */
  681. hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
  682. /* Set the I2S Tx DMA transfert complete callback */
  683. hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
  684. /* Set the DMA error callback */
  685. hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
  686. /* Enable the Tx DMA Channel */
  687. HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
  688. /* Check if the I2S is already enabled */
  689. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  690. {
  691. /* Enable I2S peripheral */
  692. __HAL_I2S_ENABLE(hi2s);
  693. }
  694. /* Check if the I2S Tx request is already enabled */
  695. if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
  696. {
  697. /* Enable Tx DMA Request */
  698. hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
  699. }
  700. /* Process Unlocked */
  701. __HAL_UNLOCK(hi2s);
  702. return HAL_OK;
  703. }
  704. else
  705. {
  706. /* Process Unlocked */
  707. __HAL_UNLOCK(hi2s);
  708. return HAL_BUSY;
  709. }
  710. }
  711. /**
  712. * @brief Receive an amount of data in non-blocking mode with DMA
  713. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  714. * the configuration information for I2S module
  715. * @param pData a 16-bit pointer to the Receive data buffer.
  716. * @param Size number of data sample to be sent:
  717. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  718. * configuration phase, the Size parameter means the number of 16-bit data length
  719. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  720. * the Size parameter means the number of 16-bit data length.
  721. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  722. * between Master and Slave(example: audio streaming).
  723. * @retval HAL status
  724. */
  725. HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  726. {
  727. if((pData == NULL) || (Size == 0U))
  728. {
  729. return HAL_ERROR;
  730. }
  731. /* Process Locked */
  732. __HAL_LOCK(hi2s);
  733. if(hi2s->State == HAL_I2S_STATE_READY)
  734. {
  735. hi2s->pRxBuffPtr = pData;
  736. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  737. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  738. if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
  739. ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
  740. {
  741. hi2s->RxXferSize = (Size << 1U);
  742. hi2s->RxXferCount = (Size << 1U);
  743. }
  744. else
  745. {
  746. hi2s->RxXferSize = Size;
  747. hi2s->RxXferCount = Size;
  748. }
  749. /* Set the I2S Rx DMA Half transfert complete callback */
  750. hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
  751. /* Set the I2S Rx DMA transfert complete callback */
  752. hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
  753. /* Set the DMA error callback */
  754. hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
  755. /* Check if Master Receiver mode is selected */
  756. if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  757. {
  758. /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
  759. access to the SPI_SR register. */
  760. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  761. }
  762. /* Enable the Rx DMA Channel */
  763. HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
  764. /* Check if the I2S is already enabled */
  765. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  766. {
  767. /* Enable I2S peripheral */
  768. __HAL_I2S_ENABLE(hi2s);
  769. }
  770. /* Check if the I2S Rx request is already enabled */
  771. if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
  772. {
  773. /* Enable Rx DMA Request */
  774. hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
  775. }
  776. /* Process Unlocked */
  777. __HAL_UNLOCK(hi2s);
  778. return HAL_OK;
  779. }
  780. else
  781. {
  782. /* Process Unlocked */
  783. __HAL_UNLOCK(hi2s);
  784. return HAL_BUSY;
  785. }
  786. }
  787. /**
  788. * @brief Pauses the audio stream playing from the Media.
  789. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  790. * the configuration information for I2S module
  791. * @retval HAL status
  792. */
  793. HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
  794. {
  795. /* Process Locked */
  796. __HAL_LOCK(hi2s);
  797. if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
  798. {
  799. /* Disable the I2S DMA Tx request */
  800. hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
  801. }
  802. else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
  803. {
  804. /* Disable the I2S DMA Rx request */
  805. hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
  806. }
  807. /* Process Unlocked */
  808. __HAL_UNLOCK(hi2s);
  809. return HAL_OK;
  810. }
  811. /**
  812. * @brief Resumes the audio stream playing from the Media.
  813. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  814. * the configuration information for I2S module
  815. * @retval HAL status
  816. */
  817. HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
  818. {
  819. /* Process Locked */
  820. __HAL_LOCK(hi2s);
  821. if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
  822. {
  823. /* Enable the I2S DMA Tx request */
  824. hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
  825. }
  826. else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
  827. {
  828. /* Enable the I2S DMA Rx request */
  829. hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
  830. }
  831. /* If the I2S peripheral is still not enabled, enable it */
  832. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
  833. {
  834. /* Enable I2S peripheral */
  835. __HAL_I2S_ENABLE(hi2s);
  836. }
  837. /* Process Unlocked */
  838. __HAL_UNLOCK(hi2s);
  839. return HAL_OK;
  840. }
  841. /**
  842. * @brief Resumes the audio stream playing from the Media.
  843. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  844. * the configuration information for I2S module
  845. * @retval HAL status
  846. */
  847. HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
  848. {
  849. /* Process Locked */
  850. __HAL_LOCK(hi2s);
  851. /* Disable the I2S Tx/Rx DMA requests */
  852. hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
  853. hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
  854. /* Abort the I2S DMA tx channel */
  855. if(hi2s->hdmatx != NULL)
  856. {
  857. /* Disable the I2S DMA channel */
  858. __HAL_DMA_DISABLE(hi2s->hdmatx);
  859. HAL_DMA_Abort(hi2s->hdmatx);
  860. }
  861. /* Abort the I2S DMA rx channel */
  862. if(hi2s->hdmarx != NULL)
  863. {
  864. /* Disable the I2S DMA channel */
  865. __HAL_DMA_DISABLE(hi2s->hdmarx);
  866. HAL_DMA_Abort(hi2s->hdmarx);
  867. }
  868. /* Disable I2S peripheral */
  869. __HAL_I2S_DISABLE(hi2s);
  870. hi2s->State = HAL_I2S_STATE_READY;
  871. /* Process Unlocked */
  872. __HAL_UNLOCK(hi2s);
  873. return HAL_OK;
  874. }
  875. /**
  876. * @brief This function handles I2S interrupt request.
  877. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  878. * the configuration information for I2S module
  879. * @retval None
  880. */
  881. void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
  882. {
  883. uint32_t i2ssr = hi2s->Instance->SR;
  884. /* I2S in mode Receiver ------------------------------------------------*/
  885. if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
  886. ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
  887. {
  888. I2S_Receive_IT(hi2s);
  889. return;
  890. }
  891. /* I2S in mode Tramitter -----------------------------------------------*/
  892. if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
  893. {
  894. I2S_Transmit_IT(hi2s);
  895. return;
  896. }
  897. /* I2S Overrun error interrupt occured ---------------------------------*/
  898. if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
  899. {
  900. /* Disable RXNE and ERR interrupt */
  901. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  902. /* Set the I2S State ready */
  903. hi2s->State = HAL_I2S_STATE_READY;
  904. /* Set the error code and execute error callback*/
  905. hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
  906. HAL_I2S_ErrorCallback(hi2s);
  907. }
  908. /* I2S Underrun error interrupt occured --------------------------------*/
  909. if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
  910. {
  911. /* Disable TXE and ERR interrupt */
  912. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  913. /* Set the I2S State ready */
  914. hi2s->State = HAL_I2S_STATE_READY;
  915. /* Set the error code and execute error callback*/
  916. hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
  917. HAL_I2S_ErrorCallback(hi2s);
  918. }
  919. }
  920. /**
  921. * @brief Tx Transfer Half completed callbacks
  922. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  923. * the configuration information for I2S module
  924. * @retval None
  925. */
  926. __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  927. {
  928. /* Prevent unused argument(s) compilation warning */
  929. UNUSED(hi2s);
  930. /* NOTE : This function Should not be modified, when the callback is needed,
  931. the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
  932. */
  933. }
  934. /**
  935. * @brief Tx Transfer completed callbacks
  936. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  937. * the configuration information for I2S module
  938. * @retval None
  939. */
  940. __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
  941. {
  942. /* Prevent unused argument(s) compilation warning */
  943. UNUSED(hi2s);
  944. /* NOTE : This function Should not be modified, when the callback is needed,
  945. the HAL_I2S_TxCpltCallback could be implemented in the user file
  946. */
  947. }
  948. /**
  949. * @brief Rx Transfer half completed callbacks
  950. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  951. * the configuration information for I2S module
  952. * @retval None
  953. */
  954. __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  955. {
  956. /* Prevent unused argument(s) compilation warning */
  957. UNUSED(hi2s);
  958. /* NOTE : This function Should not be modified, when the callback is needed,
  959. the HAL_I2S_RxCpltCallback could be implemented in the user file
  960. */
  961. }
  962. /**
  963. * @brief Rx Transfer completed callbacks
  964. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  965. * the configuration information for I2S module
  966. * @retval None
  967. */
  968. __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
  969. {
  970. /* Prevent unused argument(s) compilation warning */
  971. UNUSED(hi2s);
  972. /* NOTE : This function Should not be modified, when the callback is needed,
  973. the HAL_I2S_RxCpltCallback could be implemented in the user file
  974. */
  975. }
  976. /**
  977. * @brief I2S error callbacks
  978. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  979. * the configuration information for I2S module
  980. * @retval None
  981. */
  982. __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
  983. {
  984. /* Prevent unused argument(s) compilation warning */
  985. UNUSED(hi2s);
  986. /* NOTE : This function Should not be modified, when the callback is needed,
  987. the HAL_I2S_ErrorCallback could be implemented in the user file
  988. */
  989. }
  990. /**
  991. * @}
  992. */
  993. /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
  994. * @brief Peripheral State functions
  995. *
  996. @verbatim
  997. ===============================================================================
  998. ##### Peripheral State and Errors functions #####
  999. ===============================================================================
  1000. [..]
  1001. This subsection permits to get in run-time the status of the peripheral
  1002. and the data flow.
  1003. @endverbatim
  1004. * @{
  1005. */
  1006. /**
  1007. * @brief Return the I2S state
  1008. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1009. * the configuration information for I2S module
  1010. * @retval HAL state
  1011. */
  1012. HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
  1013. {
  1014. return hi2s->State;
  1015. }
  1016. /**
  1017. * @brief Return the I2S error code
  1018. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1019. * the configuration information for I2S module
  1020. * @retval I2S Error Code
  1021. */
  1022. uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
  1023. {
  1024. return hi2s->ErrorCode;
  1025. }
  1026. /**
  1027. * @}
  1028. */
  1029. /**
  1030. * @}
  1031. */
  1032. /** @addtogroup I2S_Private_Functions I2S Private Functions
  1033. * @{
  1034. */
  1035. /**
  1036. * @brief DMA I2S transmit process complete callback
  1037. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1038. * the configuration information for the specified DMA module.
  1039. * @retval None
  1040. */
  1041. static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
  1042. {
  1043. I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
  1044. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  1045. {
  1046. /* Disable Tx DMA Request */
  1047. hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
  1048. hi2s->TxXferCount = 0U;
  1049. hi2s->State = HAL_I2S_STATE_READY;
  1050. }
  1051. HAL_I2S_TxCpltCallback(hi2s);
  1052. }
  1053. /**
  1054. * @brief DMA I2S transmit process half complete callback
  1055. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1056. * the configuration information for the specified DMA module.
  1057. * @retval None
  1058. */
  1059. static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  1060. {
  1061. I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
  1062. HAL_I2S_TxHalfCpltCallback(hi2s);
  1063. }
  1064. /**
  1065. * @brief DMA I2S receive process complete callback
  1066. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1067. * the configuration information for the specified DMA module.
  1068. * @retval None
  1069. */
  1070. static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
  1071. {
  1072. I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1073. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  1074. {
  1075. /* Disable Rx DMA Request */
  1076. hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
  1077. hi2s->RxXferCount = 0;
  1078. hi2s->State = HAL_I2S_STATE_READY;
  1079. }
  1080. HAL_I2S_RxCpltCallback(hi2s);
  1081. }
  1082. /**
  1083. * @brief DMA I2S receive process half complete callback
  1084. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1085. * the configuration information for the specified DMA module.
  1086. * @retval None
  1087. */
  1088. static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  1089. {
  1090. I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
  1091. HAL_I2S_RxHalfCpltCallback(hi2s);
  1092. }
  1093. /**
  1094. * @brief DMA I2S communication error callback
  1095. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1096. * the configuration information for the specified DMA module.
  1097. * @retval None
  1098. */
  1099. static void I2S_DMAError(DMA_HandleTypeDef *hdma)
  1100. {
  1101. I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1102. /* Disable Rx and Tx DMA Request */
  1103. hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
  1104. hi2s->TxXferCount = 0U;
  1105. hi2s->RxXferCount = 0U;
  1106. hi2s->State= HAL_I2S_STATE_READY;
  1107. /* Set the error code and execute error callback*/
  1108. hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
  1109. HAL_I2S_ErrorCallback(hi2s);
  1110. }
  1111. /**
  1112. * @brief Transmit an amount of data in non-blocking mode with Interrupt
  1113. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1114. * the configuration information for I2S module
  1115. * @retval None
  1116. */
  1117. static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
  1118. {
  1119. /* Transmit data */
  1120. hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
  1121. hi2s->TxXferCount--;
  1122. if(hi2s->TxXferCount == 0)
  1123. {
  1124. /* Disable TXE and ERR interrupt */
  1125. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  1126. hi2s->State = HAL_I2S_STATE_READY;
  1127. HAL_I2S_TxCpltCallback(hi2s);
  1128. }
  1129. }
  1130. /**
  1131. * @brief Receive an amount of data in non-blocking mode with Interrupt
  1132. * @param hi2s I2S handle
  1133. * @retval None
  1134. */
  1135. static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
  1136. {
  1137. /* Receive data */
  1138. (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
  1139. hi2s->RxXferCount--;
  1140. if(hi2s->RxXferCount == 0U)
  1141. {
  1142. /* Disable RXNE and ERR interrupt */
  1143. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  1144. hi2s->State = HAL_I2S_STATE_READY;
  1145. HAL_I2S_RxCpltCallback(hi2s);
  1146. }
  1147. }
  1148. /**
  1149. * @brief This function handles I2S Communication Timeout.
  1150. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1151. * the configuration information for I2S module
  1152. * @param Flag Flag checked
  1153. * @param State Value of the flag expected
  1154. * @param Timeout Duration of the timeout
  1155. * @retval HAL status
  1156. */
  1157. static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
  1158. {
  1159. uint32_t tickstart = HAL_GetTick();
  1160. /* Wait until flag is set */
  1161. if(State == RESET)
  1162. {
  1163. while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
  1164. {
  1165. if(Timeout != HAL_MAX_DELAY)
  1166. {
  1167. if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
  1168. {
  1169. /* Set the I2S State ready */
  1170. hi2s->State= HAL_I2S_STATE_READY;
  1171. /* Process Unlocked */
  1172. __HAL_UNLOCK(hi2s);
  1173. return HAL_TIMEOUT;
  1174. }
  1175. }
  1176. }
  1177. }
  1178. else
  1179. {
  1180. while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
  1181. {
  1182. if(Timeout != HAL_MAX_DELAY)
  1183. {
  1184. if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
  1185. {
  1186. /* Set the I2S State ready */
  1187. hi2s->State= HAL_I2S_STATE_READY;
  1188. /* Process Unlocked */
  1189. __HAL_UNLOCK(hi2s);
  1190. return HAL_TIMEOUT;
  1191. }
  1192. }
  1193. }
  1194. }
  1195. return HAL_OK;
  1196. }
  1197. /**
  1198. * @}
  1199. */
  1200. /**
  1201. * @}
  1202. */
  1203. /**
  1204. * @}
  1205. */
  1206. #endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
  1207. /* defined(STM32F051x8) || defined(STM32F058xx) || */
  1208. /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
  1209. /* defined(STM32F042x6) || defined(STM32F048xx) || */
  1210. /* defined(STM32F091xC) || defined(STM32F098xx) */
  1211. #endif /* HAL_I2S_MODULE_ENABLED */
  1212. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/