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  1. /**
  2. ******************************************************************************
  3. * @file stm32f0xx_ll_adc.c
  4. * @author MCD Application Team
  5. * @brief ADC LL module driver
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10. *
  11. * Redistribution and use in source and binary forms, with or without modification,
  12. * are permitted provided that the following conditions are met:
  13. * 1. Redistributions of source code must retain the above copyright notice,
  14. * this list of conditions and the following disclaimer.
  15. * 2. Redistributions in binary form must reproduce the above copyright notice,
  16. * this list of conditions and the following disclaimer in the documentation
  17. * and/or other materials provided with the distribution.
  18. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  19. * may be used to endorse or promote products derived from this software
  20. * without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. ******************************************************************************
  34. */
  35. #if defined(USE_FULL_LL_DRIVER)
  36. /* Includes ------------------------------------------------------------------*/
  37. #include "stm32f0xx_ll_adc.h"
  38. #include "stm32f0xx_ll_bus.h"
  39. #ifdef USE_FULL_ASSERT
  40. #include "stm32_assert.h"
  41. #else
  42. #define assert_param(expr) ((void)0U)
  43. #endif
  44. /** @addtogroup STM32F0xx_LL_Driver
  45. * @{
  46. */
  47. #if defined (ADC1)
  48. /** @addtogroup ADC_LL ADC
  49. * @{
  50. */
  51. /* Private types -------------------------------------------------------------*/
  52. /* Private variables ---------------------------------------------------------*/
  53. /* Private constants ---------------------------------------------------------*/
  54. /** @addtogroup ADC_LL_Private_Constants
  55. * @{
  56. */
  57. /* Definitions of ADC hardware constraints delays */
  58. /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
  59. /* not timeout values: */
  60. /* Timeout values for ADC operations are dependent to device clock */
  61. /* configuration (system clock versus ADC clock), */
  62. /* and therefore must be defined in user application. */
  63. /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
  64. /* values definition. */
  65. /* Note: ADC timeout values are defined here in CPU cycles to be independent */
  66. /* of device clock setting. */
  67. /* In user application, ADC timeout values should be defined with */
  68. /* temporal values, in function of device clock settings. */
  69. /* Highest ratio CPU clock frequency vs ADC clock frequency: */
  70. /* - ADC clock from synchronous clock with AHB prescaler 512, */
  71. /* APB prescaler 16, ADC prescaler 4. */
  72. /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
  73. /* with highest ratio CPU clock frequency vs HSI clock frequency: */
  74. /* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */
  75. /* Unit: CPU cycles. */
  76. #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
  77. #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
  78. #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
  79. /**
  80. * @}
  81. */
  82. /* Private macros ------------------------------------------------------------*/
  83. /** @addtogroup ADC_LL_Private_Macros
  84. * @{
  85. */
  86. /* Check of parameters for configuration of ADC hierarchical scope: */
  87. /* common to several ADC instances. */
  88. /* Check of parameters for configuration of ADC hierarchical scope: */
  89. /* ADC instance. */
  90. #define IS_LL_ADC_CLOCK(__CLOCK__) \
  91. ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
  92. || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
  93. || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
  94. )
  95. #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
  96. ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
  97. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
  98. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
  99. || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
  100. )
  101. #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
  102. ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
  103. || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
  104. )
  105. #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
  106. ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
  107. || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
  108. || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
  109. || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
  110. )
  111. /* Check of parameters for configuration of ADC hierarchical scope: */
  112. /* ADC group regular */
  113. #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
  114. ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
  115. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
  116. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \
  117. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
  118. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
  119. || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
  120. )
  121. #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
  122. ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
  123. || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
  124. )
  125. #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
  126. ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
  127. || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
  128. || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
  129. )
  130. #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
  131. ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
  132. || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
  133. )
  134. #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
  135. ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
  136. || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
  137. )
  138. /**
  139. * @}
  140. */
  141. /* Private function prototypes -----------------------------------------------*/
  142. /* Exported functions --------------------------------------------------------*/
  143. /** @addtogroup ADC_LL_Exported_Functions
  144. * @{
  145. */
  146. /** @addtogroup ADC_LL_EF_Init
  147. * @{
  148. */
  149. /**
  150. * @brief De-initialize registers of all ADC instances belonging to
  151. * the same ADC common instance to their default reset values.
  152. * @note This function is performing a hard reset, using high level
  153. * clock source RCC ADC reset.
  154. * @param ADCxy_COMMON ADC common instance
  155. * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  156. * @retval An ErrorStatus enumeration value:
  157. * - SUCCESS: ADC common registers are de-initialized
  158. * - ERROR: not applicable
  159. */
  160. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
  161. {
  162. /* Check the parameters */
  163. assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
  164. /* Force reset of ADC clock (core clock) */
  165. LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
  166. /* Release reset of ADC clock (core clock) */
  167. LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
  168. return SUCCESS;
  169. }
  170. /**
  171. * @brief De-initialize registers of the selected ADC instance
  172. * to their default reset values.
  173. * @note To reset all ADC instances quickly (perform a hard reset),
  174. * use function @ref LL_ADC_CommonDeInit().
  175. * @note If this functions returns error status, it means that ADC instance
  176. * is in an unknown state.
  177. * In this case, perform a hard reset using high level
  178. * clock source RCC ADC reset.
  179. * Refer to function @ref LL_ADC_CommonDeInit().
  180. * @param ADCx ADC instance
  181. * @retval An ErrorStatus enumeration value:
  182. * - SUCCESS: ADC registers are de-initialized
  183. * - ERROR: ADC registers are not de-initialized
  184. */
  185. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
  186. {
  187. ErrorStatus status = SUCCESS;
  188. __IO uint32_t timeout_cpu_cycles = 0U;
  189. /* Check the parameters */
  190. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  191. /* Disable ADC instance if not already disabled. */
  192. if(LL_ADC_IsEnabled(ADCx) == 1U)
  193. {
  194. /* Set ADC group regular trigger source to SW start to ensure to not */
  195. /* have an external trigger event occurring during the conversion stop */
  196. /* ADC disable process. */
  197. LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
  198. /* Stop potential ADC conversion on going on ADC group regular. */
  199. if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
  200. {
  201. if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
  202. {
  203. LL_ADC_REG_StopConversion(ADCx);
  204. }
  205. }
  206. /* Wait for ADC conversions are effectively stopped */
  207. timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
  208. while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
  209. {
  210. if(timeout_cpu_cycles-- == 0U)
  211. {
  212. /* Time-out error */
  213. status = ERROR;
  214. }
  215. }
  216. /* Disable the ADC instance */
  217. LL_ADC_Disable(ADCx);
  218. /* Wait for ADC instance is effectively disabled */
  219. timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
  220. while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
  221. {
  222. if(timeout_cpu_cycles-- == 0U)
  223. {
  224. /* Time-out error */
  225. status = ERROR;
  226. }
  227. }
  228. }
  229. /* Check whether ADC state is compliant with expected state */
  230. if(READ_BIT(ADCx->CR,
  231. ( ADC_CR_ADSTP | ADC_CR_ADSTART
  232. | ADC_CR_ADDIS | ADC_CR_ADEN )
  233. )
  234. == 0U)
  235. {
  236. /* ========== Reset ADC registers ========== */
  237. /* Reset register IER */
  238. CLEAR_BIT(ADCx->IER,
  239. ( LL_ADC_IT_ADRDY
  240. | LL_ADC_IT_EOC
  241. | LL_ADC_IT_EOS
  242. | LL_ADC_IT_OVR
  243. | LL_ADC_IT_EOSMP
  244. | LL_ADC_IT_AWD1 )
  245. );
  246. /* Reset register ISR */
  247. SET_BIT(ADCx->ISR,
  248. ( LL_ADC_FLAG_ADRDY
  249. | LL_ADC_FLAG_EOC
  250. | LL_ADC_FLAG_EOS
  251. | LL_ADC_FLAG_OVR
  252. | LL_ADC_FLAG_EOSMP
  253. | LL_ADC_FLAG_AWD1 )
  254. );
  255. /* Reset register CR */
  256. /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
  257. /* "read-set": no direct reset applicable. */
  258. /* No action on register CR */
  259. /* Reset register CFGR1 */
  260. CLEAR_BIT(ADCx->CFGR1,
  261. ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN
  262. | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
  263. | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
  264. | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
  265. );
  266. /* Reset register CFGR2 */
  267. /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
  268. /* already done above. */
  269. CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE);
  270. /* Reset register SMPR */
  271. CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
  272. /* Reset register TR */
  273. MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
  274. /* Reset register CHSELR */
  275. #if defined(ADC_CCR_VBATEN)
  276. CLEAR_BIT(ADCx->CHSELR,
  277. ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
  278. | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
  279. | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
  280. | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
  281. | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
  282. );
  283. #else
  284. CLEAR_BIT(ADCx->CHSELR,
  285. ( ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
  286. | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
  287. | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
  288. | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
  289. | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
  290. );
  291. #endif
  292. /* Reset register DR */
  293. /* bits in access mode read only, no direct reset applicable */
  294. }
  295. else
  296. {
  297. /* ADC instance is in an unknown state */
  298. /* Need to performing a hard reset of ADC instance, using high level */
  299. /* clock source RCC ADC reset. */
  300. /* Caution: On this STM32 serie, if several ADC instances are available */
  301. /* on the selected device, RCC ADC reset will reset */
  302. /* all ADC instances belonging to the common ADC instance. */
  303. status = ERROR;
  304. }
  305. return status;
  306. }
  307. /**
  308. * @brief Initialize some features of ADC instance.
  309. * @note These parameters have an impact on ADC scope: ADC instance.
  310. * Refer to corresponding unitary functions into
  311. * @ref ADC_LL_EF_Configuration_ADC_Instance .
  312. * @note The setting of these parameters by function @ref LL_ADC_Init()
  313. * is conditioned to ADC state:
  314. * ADC instance must be disabled.
  315. * This condition is applied to all ADC features, for efficiency
  316. * and compatibility over all STM32 families. However, the different
  317. * features can be set under different ADC state conditions
  318. * (setting possible with ADC enabled without conversion on going,
  319. * ADC enabled with conversion on going, ...)
  320. * Each feature can be updated afterwards with a unitary function
  321. * and potentially with ADC in a different state than disabled,
  322. * refer to description of each function for setting
  323. * conditioned to ADC state.
  324. * @note After using this function, some other features must be configured
  325. * using LL unitary functions.
  326. * The minimum configuration remaining to be done is:
  327. * - Set ADC group regular sequencer:
  328. * map channel on rank corresponding to channel number.
  329. * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
  330. * - Set ADC channel sampling time
  331. * Refer to function LL_ADC_SetChannelSamplingTime();
  332. * @param ADCx ADC instance
  333. * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  334. * @retval An ErrorStatus enumeration value:
  335. * - SUCCESS: ADC registers are initialized
  336. * - ERROR: ADC registers are not initialized
  337. */
  338. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
  339. {
  340. ErrorStatus status = SUCCESS;
  341. /* Check the parameters */
  342. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  343. assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
  344. assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
  345. assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
  346. assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
  347. /* Note: Hardware constraint (refer to description of this function): */
  348. /* ADC instance must be disabled. */
  349. if(LL_ADC_IsEnabled(ADCx) == 0U)
  350. {
  351. /* Configuration of ADC hierarchical scope: */
  352. /* - ADC instance */
  353. /* - Set ADC data resolution */
  354. /* - Set ADC conversion data alignment */
  355. /* - Set ADC low power mode */
  356. MODIFY_REG(ADCx->CFGR1,
  357. ADC_CFGR1_RES
  358. | ADC_CFGR1_ALIGN
  359. | ADC_CFGR1_WAIT
  360. | ADC_CFGR1_AUTOFF
  361. ,
  362. ADC_InitStruct->Resolution
  363. | ADC_InitStruct->DataAlignment
  364. | ADC_InitStruct->LowPowerMode
  365. );
  366. }
  367. else
  368. {
  369. /* Initialization error: ADC instance is not disabled. */
  370. status = ERROR;
  371. }
  372. return status;
  373. }
  374. /**
  375. * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
  376. * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
  377. * whose fields will be set to default values.
  378. * @retval None
  379. */
  380. void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
  381. {
  382. /* Set ADC_InitStruct fields to default values */
  383. /* Set fields of ADC instance */
  384. ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
  385. ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
  386. ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
  387. ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
  388. }
  389. /**
  390. * @brief Initialize some features of ADC group regular.
  391. * @note These parameters have an impact on ADC scope: ADC group regular.
  392. * Refer to corresponding unitary functions into
  393. * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
  394. * (functions with prefix "REG").
  395. * @note The setting of these parameters by function @ref LL_ADC_Init()
  396. * is conditioned to ADC state:
  397. * ADC instance must be disabled.
  398. * This condition is applied to all ADC features, for efficiency
  399. * and compatibility over all STM32 families. However, the different
  400. * features can be set under different ADC state conditions
  401. * (setting possible with ADC enabled without conversion on going,
  402. * ADC enabled with conversion on going, ...)
  403. * Each feature can be updated afterwards with a unitary function
  404. * and potentially with ADC in a different state than disabled,
  405. * refer to description of each function for setting
  406. * conditioned to ADC state.
  407. * @note After using this function, other features must be configured
  408. * using LL unitary functions.
  409. * The minimum configuration remaining to be done is:
  410. * - Set ADC group regular sequencer:
  411. * map channel on rank corresponding to channel number.
  412. * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
  413. * - Set ADC channel sampling time
  414. * Refer to function LL_ADC_SetChannelSamplingTime();
  415. * @param ADCx ADC instance
  416. * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  417. * @retval An ErrorStatus enumeration value:
  418. * - SUCCESS: ADC registers are initialized
  419. * - ERROR: ADC registers are not initialized
  420. */
  421. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
  422. {
  423. ErrorStatus status = SUCCESS;
  424. /* Check the parameters */
  425. assert_param(IS_ADC_ALL_INSTANCE(ADCx));
  426. assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
  427. assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
  428. assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
  429. assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
  430. assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
  431. /* Note: Hardware constraint (refer to description of this function): */
  432. /* ADC instance must be disabled. */
  433. if(LL_ADC_IsEnabled(ADCx) == 0U)
  434. {
  435. /* Configuration of ADC hierarchical scope: */
  436. /* - ADC group regular */
  437. /* - Set ADC group regular trigger source */
  438. /* - Set ADC group regular sequencer discontinuous mode */
  439. /* - Set ADC group regular continuous mode */
  440. /* - Set ADC group regular conversion data transfer: no transfer or */
  441. /* transfer by DMA, and DMA requests mode */
  442. /* - Set ADC group regular overrun behavior */
  443. /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
  444. /* setting of trigger source to SW start. */
  445. MODIFY_REG(ADCx->CFGR1,
  446. ADC_CFGR1_EXTSEL
  447. | ADC_CFGR1_EXTEN
  448. | ADC_CFGR1_DISCEN
  449. | ADC_CFGR1_CONT
  450. | ADC_CFGR1_DMAEN
  451. | ADC_CFGR1_DMACFG
  452. | ADC_CFGR1_OVRMOD
  453. ,
  454. ADC_REG_InitStruct->TriggerSource
  455. | ADC_REG_InitStruct->SequencerDiscont
  456. | ADC_REG_InitStruct->ContinuousMode
  457. | ADC_REG_InitStruct->DMATransfer
  458. | ADC_REG_InitStruct->Overrun
  459. );
  460. }
  461. else
  462. {
  463. /* Initialization error: ADC instance is not disabled. */
  464. status = ERROR;
  465. }
  466. return status;
  467. }
  468. /**
  469. * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
  470. * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
  471. * whose fields will be set to default values.
  472. * @retval None
  473. */
  474. void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
  475. {
  476. /* Set ADC_REG_InitStruct fields to default values */
  477. /* Set fields of ADC group regular */
  478. /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
  479. /* setting of trigger source to SW start. */
  480. ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
  481. ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
  482. ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
  483. ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
  484. ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
  485. }
  486. /**
  487. * @}
  488. */
  489. /**
  490. * @}
  491. */
  492. /**
  493. * @}
  494. */
  495. #endif /* ADC1 */
  496. /**
  497. * @}
  498. */
  499. #endif /* USE_FULL_LL_DRIVER */
  500. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/