You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 

2029 lines
64 KiB

  1. /**
  2. ******************************************************************************
  3. * @file stm32l0xx_ll_spi.h
  4. * @author MCD Application Team
  5. * @brief Header file of SPI LL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32L0xx_LL_SPI_H
  21. #define STM32L0xx_LL_SPI_H
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32l0xx.h"
  27. /** @addtogroup STM32L0xx_LL_Driver
  28. * @{
  29. */
  30. #if defined (SPI1) || defined (SPI2)
  31. /** @defgroup SPI_LL SPI
  32. * @{
  33. */
  34. /* Private types -------------------------------------------------------------*/
  35. /* Private variables ---------------------------------------------------------*/
  36. /* Private macros ------------------------------------------------------------*/
  37. /* Exported types ------------------------------------------------------------*/
  38. #if defined(USE_FULL_LL_DRIVER)
  39. /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
  40. * @{
  41. */
  42. /**
  43. * @brief SPI Init structures definition
  44. */
  45. typedef struct
  46. {
  47. uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
  48. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
  49. This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
  50. uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
  51. This parameter can be a value of @ref SPI_LL_EC_MODE.
  52. This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
  53. uint32_t DataWidth; /*!< Specifies the SPI data width.
  54. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
  55. This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
  56. uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
  57. This parameter can be a value of @ref SPI_LL_EC_POLARITY.
  58. This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
  59. uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
  60. This parameter can be a value of @ref SPI_LL_EC_PHASE.
  61. This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
  62. uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
  63. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
  64. This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
  65. uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
  66. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
  67. @note The communication clock is derived from the master clock. The slave clock does not need to be set.
  68. This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
  69. uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
  70. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
  71. This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
  72. uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
  73. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
  74. This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
  75. uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
  76. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
  77. This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
  78. } LL_SPI_InitTypeDef;
  79. /**
  80. * @}
  81. */
  82. #endif /* USE_FULL_LL_DRIVER */
  83. /* Exported constants --------------------------------------------------------*/
  84. /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
  85. * @{
  86. */
  87. /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
  88. * @brief Flags defines which can be used with LL_SPI_ReadReg function
  89. * @{
  90. */
  91. #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
  92. #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
  93. #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
  94. #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
  95. #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
  96. #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
  97. #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
  98. /**
  99. * @}
  100. */
  101. /** @defgroup SPI_LL_EC_IT IT Defines
  102. * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
  103. * @{
  104. */
  105. #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
  106. #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
  107. #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
  108. /**
  109. * @}
  110. */
  111. /** @defgroup SPI_LL_EC_MODE Operation Mode
  112. * @{
  113. */
  114. #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
  115. #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
  116. /**
  117. * @}
  118. */
  119. /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
  120. * @{
  121. */
  122. #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
  123. #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
  124. /**
  125. * @}
  126. */
  127. /** @defgroup SPI_LL_EC_PHASE Clock Phase
  128. * @{
  129. */
  130. #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
  131. #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
  132. /**
  133. * @}
  134. */
  135. /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
  136. * @{
  137. */
  138. #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
  139. #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
  140. /**
  141. * @}
  142. */
  143. /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
  144. * @{
  145. */
  146. #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
  147. #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
  148. #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
  149. #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
  150. #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
  151. #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
  152. #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
  153. #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
  154. /**
  155. * @}
  156. */
  157. /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
  158. * @{
  159. */
  160. #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
  161. #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
  162. /**
  163. * @}
  164. */
  165. /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
  166. * @{
  167. */
  168. #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
  169. #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
  170. #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
  171. #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
  172. /**
  173. * @}
  174. */
  175. /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
  176. * @{
  177. */
  178. #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
  179. #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
  180. #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
  181. /**
  182. * @}
  183. */
  184. /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
  185. * @{
  186. */
  187. #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
  188. #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
  189. /**
  190. * @}
  191. */
  192. #if defined(USE_FULL_LL_DRIVER)
  193. /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
  194. * @{
  195. */
  196. #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
  197. #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
  198. /**
  199. * @}
  200. */
  201. #endif /* USE_FULL_LL_DRIVER */
  202. /**
  203. * @}
  204. */
  205. /* Exported macro ------------------------------------------------------------*/
  206. /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
  207. * @{
  208. */
  209. /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
  210. * @{
  211. */
  212. /**
  213. * @brief Write a value in SPI register
  214. * @param __INSTANCE__ SPI Instance
  215. * @param __REG__ Register to be written
  216. * @param __VALUE__ Value to be written in the register
  217. * @retval None
  218. */
  219. #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  220. /**
  221. * @brief Read a value in SPI register
  222. * @param __INSTANCE__ SPI Instance
  223. * @param __REG__ Register to be read
  224. * @retval Register value
  225. */
  226. #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  227. /**
  228. * @}
  229. */
  230. /**
  231. * @}
  232. */
  233. /* Exported functions --------------------------------------------------------*/
  234. /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
  235. * @{
  236. */
  237. /** @defgroup SPI_LL_EF_Configuration Configuration
  238. * @{
  239. */
  240. /**
  241. * @brief Enable SPI peripheral
  242. * @rmtoll CR1 SPE LL_SPI_Enable
  243. * @param SPIx SPI Instance
  244. * @retval None
  245. */
  246. __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
  247. {
  248. SET_BIT(SPIx->CR1, SPI_CR1_SPE);
  249. }
  250. /**
  251. * @brief Disable SPI peripheral
  252. * @note When disabling the SPI, follow the procedure described in the Reference Manual.
  253. * @rmtoll CR1 SPE LL_SPI_Disable
  254. * @param SPIx SPI Instance
  255. * @retval None
  256. */
  257. __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
  258. {
  259. CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  260. }
  261. /**
  262. * @brief Check if SPI peripheral is enabled
  263. * @rmtoll CR1 SPE LL_SPI_IsEnabled
  264. * @param SPIx SPI Instance
  265. * @retval State of bit (1 or 0).
  266. */
  267. __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
  268. {
  269. return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
  270. }
  271. /**
  272. * @brief Set SPI operation mode to Master or Slave
  273. * @note This bit should not be changed when communication is ongoing.
  274. * @rmtoll CR1 MSTR LL_SPI_SetMode\n
  275. * CR1 SSI LL_SPI_SetMode
  276. * @param SPIx SPI Instance
  277. * @param Mode This parameter can be one of the following values:
  278. * @arg @ref LL_SPI_MODE_MASTER
  279. * @arg @ref LL_SPI_MODE_SLAVE
  280. * @retval None
  281. */
  282. __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
  283. {
  284. MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
  285. }
  286. /**
  287. * @brief Get SPI operation mode (Master or Slave)
  288. * @rmtoll CR1 MSTR LL_SPI_GetMode\n
  289. * CR1 SSI LL_SPI_GetMode
  290. * @param SPIx SPI Instance
  291. * @retval Returned value can be one of the following values:
  292. * @arg @ref LL_SPI_MODE_MASTER
  293. * @arg @ref LL_SPI_MODE_SLAVE
  294. */
  295. __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
  296. {
  297. return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
  298. }
  299. /**
  300. * @brief Set serial protocol used
  301. * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  302. * @rmtoll CR2 FRF LL_SPI_SetStandard
  303. * @param SPIx SPI Instance
  304. * @param Standard This parameter can be one of the following values:
  305. * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
  306. * @arg @ref LL_SPI_PROTOCOL_TI
  307. * @retval None
  308. */
  309. __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
  310. {
  311. MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
  312. }
  313. /**
  314. * @brief Get serial protocol used
  315. * @rmtoll CR2 FRF LL_SPI_GetStandard
  316. * @param SPIx SPI Instance
  317. * @retval Returned value can be one of the following values:
  318. * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
  319. * @arg @ref LL_SPI_PROTOCOL_TI
  320. */
  321. __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
  322. {
  323. return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
  324. }
  325. /**
  326. * @brief Set clock phase
  327. * @note This bit should not be changed when communication is ongoing.
  328. * This bit is not used in SPI TI mode.
  329. * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
  330. * @param SPIx SPI Instance
  331. * @param ClockPhase This parameter can be one of the following values:
  332. * @arg @ref LL_SPI_PHASE_1EDGE
  333. * @arg @ref LL_SPI_PHASE_2EDGE
  334. * @retval None
  335. */
  336. __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
  337. {
  338. MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
  339. }
  340. /**
  341. * @brief Get clock phase
  342. * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
  343. * @param SPIx SPI Instance
  344. * @retval Returned value can be one of the following values:
  345. * @arg @ref LL_SPI_PHASE_1EDGE
  346. * @arg @ref LL_SPI_PHASE_2EDGE
  347. */
  348. __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
  349. {
  350. return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
  351. }
  352. /**
  353. * @brief Set clock polarity
  354. * @note This bit should not be changed when communication is ongoing.
  355. * This bit is not used in SPI TI mode.
  356. * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
  357. * @param SPIx SPI Instance
  358. * @param ClockPolarity This parameter can be one of the following values:
  359. * @arg @ref LL_SPI_POLARITY_LOW
  360. * @arg @ref LL_SPI_POLARITY_HIGH
  361. * @retval None
  362. */
  363. __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  364. {
  365. MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
  366. }
  367. /**
  368. * @brief Get clock polarity
  369. * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
  370. * @param SPIx SPI Instance
  371. * @retval Returned value can be one of the following values:
  372. * @arg @ref LL_SPI_POLARITY_LOW
  373. * @arg @ref LL_SPI_POLARITY_HIGH
  374. */
  375. __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
  376. {
  377. return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
  378. }
  379. /**
  380. * @brief Set baud rate prescaler
  381. * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
  382. * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
  383. * @param SPIx SPI Instance
  384. * @param BaudRate This parameter can be one of the following values:
  385. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
  386. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
  387. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
  388. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
  389. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
  390. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
  391. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
  392. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
  393. * @retval None
  394. */
  395. __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
  396. {
  397. MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
  398. }
  399. /**
  400. * @brief Get baud rate prescaler
  401. * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
  402. * @param SPIx SPI Instance
  403. * @retval Returned value can be one of the following values:
  404. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
  405. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
  406. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
  407. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
  408. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
  409. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
  410. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
  411. * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
  412. */
  413. __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
  414. {
  415. return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
  416. }
  417. /**
  418. * @brief Set transfer bit order
  419. * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
  420. * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
  421. * @param SPIx SPI Instance
  422. * @param BitOrder This parameter can be one of the following values:
  423. * @arg @ref LL_SPI_LSB_FIRST
  424. * @arg @ref LL_SPI_MSB_FIRST
  425. * @retval None
  426. */
  427. __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
  428. {
  429. MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
  430. }
  431. /**
  432. * @brief Get transfer bit order
  433. * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
  434. * @param SPIx SPI Instance
  435. * @retval Returned value can be one of the following values:
  436. * @arg @ref LL_SPI_LSB_FIRST
  437. * @arg @ref LL_SPI_MSB_FIRST
  438. */
  439. __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
  440. {
  441. return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
  442. }
  443. /**
  444. * @brief Set transfer direction mode
  445. * @note For Half-Duplex mode, Rx Direction is set by default.
  446. * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
  447. * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
  448. * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
  449. * CR1 BIDIOE LL_SPI_SetTransferDirection
  450. * @param SPIx SPI Instance
  451. * @param TransferDirection This parameter can be one of the following values:
  452. * @arg @ref LL_SPI_FULL_DUPLEX
  453. * @arg @ref LL_SPI_SIMPLEX_RX
  454. * @arg @ref LL_SPI_HALF_DUPLEX_RX
  455. * @arg @ref LL_SPI_HALF_DUPLEX_TX
  456. * @retval None
  457. */
  458. __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
  459. {
  460. MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
  461. }
  462. /**
  463. * @brief Get transfer direction mode
  464. * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
  465. * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
  466. * CR1 BIDIOE LL_SPI_GetTransferDirection
  467. * @param SPIx SPI Instance
  468. * @retval Returned value can be one of the following values:
  469. * @arg @ref LL_SPI_FULL_DUPLEX
  470. * @arg @ref LL_SPI_SIMPLEX_RX
  471. * @arg @ref LL_SPI_HALF_DUPLEX_RX
  472. * @arg @ref LL_SPI_HALF_DUPLEX_TX
  473. */
  474. __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
  475. {
  476. return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
  477. }
  478. /**
  479. * @brief Set frame data width
  480. * @rmtoll CR1 DFF LL_SPI_SetDataWidth
  481. * @param SPIx SPI Instance
  482. * @param DataWidth This parameter can be one of the following values:
  483. * @arg @ref LL_SPI_DATAWIDTH_8BIT
  484. * @arg @ref LL_SPI_DATAWIDTH_16BIT
  485. * @retval None
  486. */
  487. __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
  488. {
  489. MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
  490. }
  491. /**
  492. * @brief Get frame data width
  493. * @rmtoll CR1 DFF LL_SPI_GetDataWidth
  494. * @param SPIx SPI Instance
  495. * @retval Returned value can be one of the following values:
  496. * @arg @ref LL_SPI_DATAWIDTH_8BIT
  497. * @arg @ref LL_SPI_DATAWIDTH_16BIT
  498. */
  499. __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
  500. {
  501. return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
  502. }
  503. /**
  504. * @}
  505. */
  506. /** @defgroup SPI_LL_EF_CRC_Management CRC Management
  507. * @{
  508. */
  509. /**
  510. * @brief Enable CRC
  511. * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  512. * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
  513. * @param SPIx SPI Instance
  514. * @retval None
  515. */
  516. __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
  517. {
  518. SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  519. }
  520. /**
  521. * @brief Disable CRC
  522. * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  523. * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
  524. * @param SPIx SPI Instance
  525. * @retval None
  526. */
  527. __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
  528. {
  529. CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  530. }
  531. /**
  532. * @brief Check if CRC is enabled
  533. * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  534. * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
  535. * @param SPIx SPI Instance
  536. * @retval State of bit (1 or 0).
  537. */
  538. __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
  539. {
  540. return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
  541. }
  542. /**
  543. * @brief Set CRCNext to transfer CRC on the line
  544. * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
  545. * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
  546. * @param SPIx SPI Instance
  547. * @retval None
  548. */
  549. __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
  550. {
  551. SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
  552. }
  553. /**
  554. * @brief Set polynomial for CRC calculation
  555. * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
  556. * @param SPIx SPI Instance
  557. * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  558. * @retval None
  559. */
  560. __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
  561. {
  562. WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
  563. }
  564. /**
  565. * @brief Get polynomial for CRC calculation
  566. * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
  567. * @param SPIx SPI Instance
  568. * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  569. */
  570. __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
  571. {
  572. return (uint32_t)(READ_REG(SPIx->CRCPR));
  573. }
  574. /**
  575. * @brief Get Rx CRC
  576. * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
  577. * @param SPIx SPI Instance
  578. * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  579. */
  580. __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
  581. {
  582. return (uint32_t)(READ_REG(SPIx->RXCRCR));
  583. }
  584. /**
  585. * @brief Get Tx CRC
  586. * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
  587. * @param SPIx SPI Instance
  588. * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  589. */
  590. __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
  591. {
  592. return (uint32_t)(READ_REG(SPIx->TXCRCR));
  593. }
  594. /**
  595. * @}
  596. */
  597. /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
  598. * @{
  599. */
  600. /**
  601. * @brief Set NSS mode
  602. * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
  603. * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
  604. * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
  605. * @param SPIx SPI Instance
  606. * @param NSS This parameter can be one of the following values:
  607. * @arg @ref LL_SPI_NSS_SOFT
  608. * @arg @ref LL_SPI_NSS_HARD_INPUT
  609. * @arg @ref LL_SPI_NSS_HARD_OUTPUT
  610. * @retval None
  611. */
  612. __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
  613. {
  614. MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
  615. MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
  616. }
  617. /**
  618. * @brief Get NSS mode
  619. * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
  620. * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
  621. * @param SPIx SPI Instance
  622. * @retval Returned value can be one of the following values:
  623. * @arg @ref LL_SPI_NSS_SOFT
  624. * @arg @ref LL_SPI_NSS_HARD_INPUT
  625. * @arg @ref LL_SPI_NSS_HARD_OUTPUT
  626. */
  627. __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
  628. {
  629. register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
  630. register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
  631. return (Ssm | Ssoe);
  632. }
  633. /**
  634. * @}
  635. */
  636. /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
  637. * @{
  638. */
  639. /**
  640. * @brief Check if Rx buffer is not empty
  641. * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
  642. * @param SPIx SPI Instance
  643. * @retval State of bit (1 or 0).
  644. */
  645. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  646. {
  647. return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
  648. }
  649. /**
  650. * @brief Check if Tx buffer is empty
  651. * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
  652. * @param SPIx SPI Instance
  653. * @retval State of bit (1 or 0).
  654. */
  655. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  656. {
  657. return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
  658. }
  659. /**
  660. * @brief Get CRC error flag
  661. * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
  662. * @param SPIx SPI Instance
  663. * @retval State of bit (1 or 0).
  664. */
  665. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
  666. {
  667. return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
  668. }
  669. /**
  670. * @brief Get mode fault error flag
  671. * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
  672. * @param SPIx SPI Instance
  673. * @retval State of bit (1 or 0).
  674. */
  675. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
  676. {
  677. return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
  678. }
  679. /**
  680. * @brief Get overrun error flag
  681. * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
  682. * @param SPIx SPI Instance
  683. * @retval State of bit (1 or 0).
  684. */
  685. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  686. {
  687. return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
  688. }
  689. /**
  690. * @brief Get busy flag
  691. * @note The BSY flag is cleared under any one of the following conditions:
  692. * -When the SPI is correctly disabled
  693. * -When a fault is detected in Master mode (MODF bit set to 1)
  694. * -In Master mode, when it finishes a data transmission and no new data is ready to be
  695. * sent
  696. * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
  697. * each data transfer.
  698. * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
  699. * @param SPIx SPI Instance
  700. * @retval State of bit (1 or 0).
  701. */
  702. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  703. {
  704. return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
  705. }
  706. /**
  707. * @brief Get frame format error flag
  708. * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
  709. * @param SPIx SPI Instance
  710. * @retval State of bit (1 or 0).
  711. */
  712. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
  713. {
  714. return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
  715. }
  716. /**
  717. * @brief Clear CRC error flag
  718. * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
  719. * @param SPIx SPI Instance
  720. * @retval None
  721. */
  722. __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
  723. {
  724. CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
  725. }
  726. /**
  727. * @brief Clear mode fault error flag
  728. * @note Clearing this flag is done by a read access to the SPIx_SR
  729. * register followed by a write access to the SPIx_CR1 register
  730. * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
  731. * @param SPIx SPI Instance
  732. * @retval None
  733. */
  734. __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
  735. {
  736. __IO uint32_t tmpreg_sr;
  737. tmpreg_sr = SPIx->SR;
  738. (void) tmpreg_sr;
  739. CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  740. }
  741. /**
  742. * @brief Clear overrun error flag
  743. * @note Clearing this flag is done by a read access to the SPIx_DR
  744. * register followed by a read access to the SPIx_SR register
  745. * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
  746. * @param SPIx SPI Instance
  747. * @retval None
  748. */
  749. __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
  750. {
  751. __IO uint32_t tmpreg;
  752. tmpreg = SPIx->DR;
  753. (void) tmpreg;
  754. tmpreg = SPIx->SR;
  755. (void) tmpreg;
  756. }
  757. /**
  758. * @brief Clear frame format error flag
  759. * @note Clearing this flag is done by reading SPIx_SR register
  760. * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
  761. * @param SPIx SPI Instance
  762. * @retval None
  763. */
  764. __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
  765. {
  766. __IO uint32_t tmpreg;
  767. tmpreg = SPIx->SR;
  768. (void) tmpreg;
  769. }
  770. /**
  771. * @}
  772. */
  773. /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
  774. * @{
  775. */
  776. /**
  777. * @brief Enable error interrupt
  778. * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
  779. * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
  780. * @param SPIx SPI Instance
  781. * @retval None
  782. */
  783. __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
  784. {
  785. SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  786. }
  787. /**
  788. * @brief Enable Rx buffer not empty interrupt
  789. * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
  790. * @param SPIx SPI Instance
  791. * @retval None
  792. */
  793. __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
  794. {
  795. SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  796. }
  797. /**
  798. * @brief Enable Tx buffer empty interrupt
  799. * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
  800. * @param SPIx SPI Instance
  801. * @retval None
  802. */
  803. __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
  804. {
  805. SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  806. }
  807. /**
  808. * @brief Disable error interrupt
  809. * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
  810. * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
  811. * @param SPIx SPI Instance
  812. * @retval None
  813. */
  814. __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
  815. {
  816. CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  817. }
  818. /**
  819. * @brief Disable Rx buffer not empty interrupt
  820. * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
  821. * @param SPIx SPI Instance
  822. * @retval None
  823. */
  824. __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
  825. {
  826. CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  827. }
  828. /**
  829. * @brief Disable Tx buffer empty interrupt
  830. * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
  831. * @param SPIx SPI Instance
  832. * @retval None
  833. */
  834. __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
  835. {
  836. CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  837. }
  838. /**
  839. * @brief Check if error interrupt is enabled
  840. * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
  841. * @param SPIx SPI Instance
  842. * @retval State of bit (1 or 0).
  843. */
  844. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  845. {
  846. return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
  847. }
  848. /**
  849. * @brief Check if Rx buffer not empty interrupt is enabled
  850. * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
  851. * @param SPIx SPI Instance
  852. * @retval State of bit (1 or 0).
  853. */
  854. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  855. {
  856. return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
  857. }
  858. /**
  859. * @brief Check if Tx buffer empty interrupt
  860. * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
  861. * @param SPIx SPI Instance
  862. * @retval State of bit (1 or 0).
  863. */
  864. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  865. {
  866. return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
  867. }
  868. /**
  869. * @}
  870. */
  871. /** @defgroup SPI_LL_EF_DMA_Management DMA Management
  872. * @{
  873. */
  874. /**
  875. * @brief Enable DMA Rx
  876. * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
  877. * @param SPIx SPI Instance
  878. * @retval None
  879. */
  880. __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  881. {
  882. SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  883. }
  884. /**
  885. * @brief Disable DMA Rx
  886. * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
  887. * @param SPIx SPI Instance
  888. * @retval None
  889. */
  890. __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  891. {
  892. CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  893. }
  894. /**
  895. * @brief Check if DMA Rx is enabled
  896. * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
  897. * @param SPIx SPI Instance
  898. * @retval State of bit (1 or 0).
  899. */
  900. __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  901. {
  902. return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
  903. }
  904. /**
  905. * @brief Enable DMA Tx
  906. * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
  907. * @param SPIx SPI Instance
  908. * @retval None
  909. */
  910. __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  911. {
  912. SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  913. }
  914. /**
  915. * @brief Disable DMA Tx
  916. * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
  917. * @param SPIx SPI Instance
  918. * @retval None
  919. */
  920. __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  921. {
  922. CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  923. }
  924. /**
  925. * @brief Check if DMA Tx is enabled
  926. * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
  927. * @param SPIx SPI Instance
  928. * @retval State of bit (1 or 0).
  929. */
  930. __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  931. {
  932. return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
  933. }
  934. /**
  935. * @brief Get the data register address used for DMA transfer
  936. * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
  937. * @param SPIx SPI Instance
  938. * @retval Address of data register
  939. */
  940. __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
  941. {
  942. return (uint32_t) & (SPIx->DR);
  943. }
  944. /**
  945. * @}
  946. */
  947. /** @defgroup SPI_LL_EF_DATA_Management DATA Management
  948. * @{
  949. */
  950. /**
  951. * @brief Read 8-Bits in the data register
  952. * @rmtoll DR DR LL_SPI_ReceiveData8
  953. * @param SPIx SPI Instance
  954. * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
  955. */
  956. __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
  957. {
  958. return (uint8_t)(READ_REG(SPIx->DR));
  959. }
  960. /**
  961. * @brief Read 16-Bits in the data register
  962. * @rmtoll DR DR LL_SPI_ReceiveData16
  963. * @param SPIx SPI Instance
  964. * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
  965. */
  966. __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
  967. {
  968. return (uint16_t)(READ_REG(SPIx->DR));
  969. }
  970. /**
  971. * @brief Write 8-Bits in the data register
  972. * @rmtoll DR DR LL_SPI_TransmitData8
  973. * @param SPIx SPI Instance
  974. * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
  975. * @retval None
  976. */
  977. __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
  978. {
  979. #if defined (__GNUC__)
  980. __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
  981. *spidr = TxData;
  982. #else
  983. *((__IO uint8_t *)&SPIx->DR) = TxData;
  984. #endif
  985. }
  986. /**
  987. * @brief Write 16-Bits in the data register
  988. * @rmtoll DR DR LL_SPI_TransmitData16
  989. * @param SPIx SPI Instance
  990. * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
  991. * @retval None
  992. */
  993. __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  994. {
  995. #if defined (__GNUC__)
  996. __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
  997. *spidr = TxData;
  998. #else
  999. SPIx->DR = TxData;
  1000. #endif
  1001. }
  1002. /**
  1003. * @}
  1004. */
  1005. #if defined(USE_FULL_LL_DRIVER)
  1006. /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
  1007. * @{
  1008. */
  1009. ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
  1010. ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
  1011. void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
  1012. /**
  1013. * @}
  1014. */
  1015. #endif /* USE_FULL_LL_DRIVER */
  1016. /**
  1017. * @}
  1018. */
  1019. /**
  1020. * @}
  1021. */
  1022. #if defined(SPI_I2S_SUPPORT)
  1023. /** @defgroup I2S_LL I2S
  1024. * @{
  1025. */
  1026. /* Private variables ---------------------------------------------------------*/
  1027. /* Private constants ---------------------------------------------------------*/
  1028. /* Private macros ------------------------------------------------------------*/
  1029. /* Exported types ------------------------------------------------------------*/
  1030. #if defined(USE_FULL_LL_DRIVER)
  1031. /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
  1032. * @{
  1033. */
  1034. /**
  1035. * @brief I2S Init structure definition
  1036. */
  1037. typedef struct
  1038. {
  1039. uint32_t Mode; /*!< Specifies the I2S operating mode.
  1040. This parameter can be a value of @ref I2S_LL_EC_MODE
  1041. This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
  1042. uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
  1043. This parameter can be a value of @ref I2S_LL_EC_STANDARD
  1044. This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
  1045. uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
  1046. This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
  1047. This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
  1048. uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
  1049. This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
  1050. This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
  1051. uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
  1052. This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
  1053. Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
  1054. and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
  1055. uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
  1056. This parameter can be a value of @ref I2S_LL_EC_POLARITY
  1057. This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
  1058. } LL_I2S_InitTypeDef;
  1059. /**
  1060. * @}
  1061. */
  1062. #endif /*USE_FULL_LL_DRIVER*/
  1063. /* Exported constants --------------------------------------------------------*/
  1064. /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
  1065. * @{
  1066. */
  1067. /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
  1068. * @brief Flags defines which can be used with LL_I2S_ReadReg function
  1069. * @{
  1070. */
  1071. #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
  1072. #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
  1073. #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
  1074. #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
  1075. #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
  1076. #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
  1077. /**
  1078. * @}
  1079. */
  1080. /** @defgroup SPI_LL_EC_IT IT Defines
  1081. * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
  1082. * @{
  1083. */
  1084. #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
  1085. #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
  1086. #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
  1087. /**
  1088. * @}
  1089. */
  1090. /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
  1091. * @{
  1092. */
  1093. #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
  1094. #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
  1095. #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
  1096. #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
  1097. /**
  1098. * @}
  1099. */
  1100. /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
  1101. * @{
  1102. */
  1103. #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
  1104. #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
  1105. /**
  1106. * @}
  1107. */
  1108. /** @defgroup I2S_LL_EC_STANDARD I2s Standard
  1109. * @{
  1110. */
  1111. #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
  1112. #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
  1113. #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
  1114. #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
  1115. #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
  1116. /**
  1117. * @}
  1118. */
  1119. /** @defgroup I2S_LL_EC_MODE Operation Mode
  1120. * @{
  1121. */
  1122. #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
  1123. #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
  1124. #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
  1125. #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
  1126. /**
  1127. * @}
  1128. */
  1129. /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
  1130. * @{
  1131. */
  1132. #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
  1133. #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
  1134. /**
  1135. * @}
  1136. */
  1137. #if defined(USE_FULL_LL_DRIVER)
  1138. /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
  1139. * @{
  1140. */
  1141. #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
  1142. #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
  1143. /**
  1144. * @}
  1145. */
  1146. /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
  1147. * @{
  1148. */
  1149. #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
  1150. #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
  1151. #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
  1152. #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
  1153. #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
  1154. #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
  1155. #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
  1156. #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
  1157. #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
  1158. #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
  1159. /**
  1160. * @}
  1161. */
  1162. #endif /* USE_FULL_LL_DRIVER */
  1163. /**
  1164. * @}
  1165. */
  1166. /* Exported macro ------------------------------------------------------------*/
  1167. /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
  1168. * @{
  1169. */
  1170. /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
  1171. * @{
  1172. */
  1173. /**
  1174. * @brief Write a value in I2S register
  1175. * @param __INSTANCE__ I2S Instance
  1176. * @param __REG__ Register to be written
  1177. * @param __VALUE__ Value to be written in the register
  1178. * @retval None
  1179. */
  1180. #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  1181. /**
  1182. * @brief Read a value in I2S register
  1183. * @param __INSTANCE__ I2S Instance
  1184. * @param __REG__ Register to be read
  1185. * @retval Register value
  1186. */
  1187. #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  1188. /**
  1189. * @}
  1190. */
  1191. /**
  1192. * @}
  1193. */
  1194. /* Exported functions --------------------------------------------------------*/
  1195. /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
  1196. * @{
  1197. */
  1198. /** @defgroup I2S_LL_EF_Configuration Configuration
  1199. * @{
  1200. */
  1201. /**
  1202. * @brief Select I2S mode and Enable I2S peripheral
  1203. * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
  1204. * I2SCFGR I2SE LL_I2S_Enable
  1205. * @param SPIx SPI Instance
  1206. * @retval None
  1207. */
  1208. __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
  1209. {
  1210. SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
  1211. }
  1212. /**
  1213. * @brief Disable I2S peripheral
  1214. * @rmtoll I2SCFGR I2SE LL_I2S_Disable
  1215. * @param SPIx SPI Instance
  1216. * @retval None
  1217. */
  1218. __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
  1219. {
  1220. CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
  1221. }
  1222. /**
  1223. * @brief Check if I2S peripheral is enabled
  1224. * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
  1225. * @param SPIx SPI Instance
  1226. * @retval State of bit (1 or 0).
  1227. */
  1228. __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
  1229. {
  1230. return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
  1231. }
  1232. /**
  1233. * @brief Set I2S data frame length
  1234. * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
  1235. * I2SCFGR CHLEN LL_I2S_SetDataFormat
  1236. * @param SPIx SPI Instance
  1237. * @param DataFormat This parameter can be one of the following values:
  1238. * @arg @ref LL_I2S_DATAFORMAT_16B
  1239. * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
  1240. * @arg @ref LL_I2S_DATAFORMAT_24B
  1241. * @arg @ref LL_I2S_DATAFORMAT_32B
  1242. * @retval None
  1243. */
  1244. __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
  1245. {
  1246. MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
  1247. }
  1248. /**
  1249. * @brief Get I2S data frame length
  1250. * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
  1251. * I2SCFGR CHLEN LL_I2S_GetDataFormat
  1252. * @param SPIx SPI Instance
  1253. * @retval Returned value can be one of the following values:
  1254. * @arg @ref LL_I2S_DATAFORMAT_16B
  1255. * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
  1256. * @arg @ref LL_I2S_DATAFORMAT_24B
  1257. * @arg @ref LL_I2S_DATAFORMAT_32B
  1258. */
  1259. __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
  1260. {
  1261. return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
  1262. }
  1263. /**
  1264. * @brief Set I2S clock polarity
  1265. * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
  1266. * @param SPIx SPI Instance
  1267. * @param ClockPolarity This parameter can be one of the following values:
  1268. * @arg @ref LL_I2S_POLARITY_LOW
  1269. * @arg @ref LL_I2S_POLARITY_HIGH
  1270. * @retval None
  1271. */
  1272. __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  1273. {
  1274. SET_BIT(SPIx->I2SCFGR, ClockPolarity);
  1275. }
  1276. /**
  1277. * @brief Get I2S clock polarity
  1278. * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
  1279. * @param SPIx SPI Instance
  1280. * @retval Returned value can be one of the following values:
  1281. * @arg @ref LL_I2S_POLARITY_LOW
  1282. * @arg @ref LL_I2S_POLARITY_HIGH
  1283. */
  1284. __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
  1285. {
  1286. return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
  1287. }
  1288. /**
  1289. * @brief Set I2S standard protocol
  1290. * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
  1291. * I2SCFGR PCMSYNC LL_I2S_SetStandard
  1292. * @param SPIx SPI Instance
  1293. * @param Standard This parameter can be one of the following values:
  1294. * @arg @ref LL_I2S_STANDARD_PHILIPS
  1295. * @arg @ref LL_I2S_STANDARD_MSB
  1296. * @arg @ref LL_I2S_STANDARD_LSB
  1297. * @arg @ref LL_I2S_STANDARD_PCM_SHORT
  1298. * @arg @ref LL_I2S_STANDARD_PCM_LONG
  1299. * @retval None
  1300. */
  1301. __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
  1302. {
  1303. MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
  1304. }
  1305. /**
  1306. * @brief Get I2S standard protocol
  1307. * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
  1308. * I2SCFGR PCMSYNC LL_I2S_GetStandard
  1309. * @param SPIx SPI Instance
  1310. * @retval Returned value can be one of the following values:
  1311. * @arg @ref LL_I2S_STANDARD_PHILIPS
  1312. * @arg @ref LL_I2S_STANDARD_MSB
  1313. * @arg @ref LL_I2S_STANDARD_LSB
  1314. * @arg @ref LL_I2S_STANDARD_PCM_SHORT
  1315. * @arg @ref LL_I2S_STANDARD_PCM_LONG
  1316. */
  1317. __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
  1318. {
  1319. return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
  1320. }
  1321. /**
  1322. * @brief Set I2S transfer mode
  1323. * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
  1324. * @param SPIx SPI Instance
  1325. * @param Mode This parameter can be one of the following values:
  1326. * @arg @ref LL_I2S_MODE_SLAVE_TX
  1327. * @arg @ref LL_I2S_MODE_SLAVE_RX
  1328. * @arg @ref LL_I2S_MODE_MASTER_TX
  1329. * @arg @ref LL_I2S_MODE_MASTER_RX
  1330. * @retval None
  1331. */
  1332. __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
  1333. {
  1334. MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
  1335. }
  1336. /**
  1337. * @brief Get I2S transfer mode
  1338. * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
  1339. * @param SPIx SPI Instance
  1340. * @retval Returned value can be one of the following values:
  1341. * @arg @ref LL_I2S_MODE_SLAVE_TX
  1342. * @arg @ref LL_I2S_MODE_SLAVE_RX
  1343. * @arg @ref LL_I2S_MODE_MASTER_TX
  1344. * @arg @ref LL_I2S_MODE_MASTER_RX
  1345. */
  1346. __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
  1347. {
  1348. return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
  1349. }
  1350. /**
  1351. * @brief Set I2S linear prescaler
  1352. * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
  1353. * @param SPIx SPI Instance
  1354. * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
  1355. * @retval None
  1356. */
  1357. __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
  1358. {
  1359. MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
  1360. }
  1361. /**
  1362. * @brief Get I2S linear prescaler
  1363. * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
  1364. * @param SPIx SPI Instance
  1365. * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
  1366. */
  1367. __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
  1368. {
  1369. return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
  1370. }
  1371. /**
  1372. * @brief Set I2S parity prescaler
  1373. * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
  1374. * @param SPIx SPI Instance
  1375. * @param PrescalerParity This parameter can be one of the following values:
  1376. * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
  1377. * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
  1378. * @retval None
  1379. */
  1380. __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
  1381. {
  1382. MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
  1383. }
  1384. /**
  1385. * @brief Get I2S parity prescaler
  1386. * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
  1387. * @param SPIx SPI Instance
  1388. * @retval Returned value can be one of the following values:
  1389. * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
  1390. * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
  1391. */
  1392. __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
  1393. {
  1394. return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
  1395. }
  1396. /**
  1397. * @brief Enable the master clock ouput (Pin MCK)
  1398. * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
  1399. * @param SPIx SPI Instance
  1400. * @retval None
  1401. */
  1402. __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
  1403. {
  1404. SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
  1405. }
  1406. /**
  1407. * @brief Disable the master clock ouput (Pin MCK)
  1408. * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
  1409. * @param SPIx SPI Instance
  1410. * @retval None
  1411. */
  1412. __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
  1413. {
  1414. CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
  1415. }
  1416. /**
  1417. * @brief Check if the master clock ouput (Pin MCK) is enabled
  1418. * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
  1419. * @param SPIx SPI Instance
  1420. * @retval State of bit (1 or 0).
  1421. */
  1422. __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
  1423. {
  1424. return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
  1425. }
  1426. #if defined(SPI_I2SCFGR_ASTRTEN)
  1427. /**
  1428. * @brief Enable asynchronous start
  1429. * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
  1430. * @param SPIx SPI Instance
  1431. * @retval None
  1432. */
  1433. __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
  1434. {
  1435. SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
  1436. }
  1437. /**
  1438. * @brief Disable asynchronous start
  1439. * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
  1440. * @param SPIx SPI Instance
  1441. * @retval None
  1442. */
  1443. __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
  1444. {
  1445. CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
  1446. }
  1447. /**
  1448. * @brief Check if asynchronous start is enabled
  1449. * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
  1450. * @param SPIx SPI Instance
  1451. * @retval State of bit (1 or 0).
  1452. */
  1453. __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
  1454. {
  1455. return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
  1456. }
  1457. #endif /* SPI_I2SCFGR_ASTRTEN */
  1458. /**
  1459. * @}
  1460. */
  1461. /** @defgroup I2S_LL_EF_FLAG FLAG Management
  1462. * @{
  1463. */
  1464. /**
  1465. * @brief Check if Rx buffer is not empty
  1466. * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
  1467. * @param SPIx SPI Instance
  1468. * @retval State of bit (1 or 0).
  1469. */
  1470. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  1471. {
  1472. return LL_SPI_IsActiveFlag_RXNE(SPIx);
  1473. }
  1474. /**
  1475. * @brief Check if Tx buffer is empty
  1476. * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
  1477. * @param SPIx SPI Instance
  1478. * @retval State of bit (1 or 0).
  1479. */
  1480. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  1481. {
  1482. return LL_SPI_IsActiveFlag_TXE(SPIx);
  1483. }
  1484. /**
  1485. * @brief Get busy flag
  1486. * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
  1487. * @param SPIx SPI Instance
  1488. * @retval State of bit (1 or 0).
  1489. */
  1490. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  1491. {
  1492. return LL_SPI_IsActiveFlag_BSY(SPIx);
  1493. }
  1494. /**
  1495. * @brief Get overrun error flag
  1496. * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
  1497. * @param SPIx SPI Instance
  1498. * @retval State of bit (1 or 0).
  1499. */
  1500. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  1501. {
  1502. return LL_SPI_IsActiveFlag_OVR(SPIx);
  1503. }
  1504. /**
  1505. * @brief Get underrun error flag
  1506. * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
  1507. * @param SPIx SPI Instance
  1508. * @retval State of bit (1 or 0).
  1509. */
  1510. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
  1511. {
  1512. return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
  1513. }
  1514. /**
  1515. * @brief Get frame format error flag
  1516. * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
  1517. * @param SPIx SPI Instance
  1518. * @retval State of bit (1 or 0).
  1519. */
  1520. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
  1521. {
  1522. return LL_SPI_IsActiveFlag_FRE(SPIx);
  1523. }
  1524. /**
  1525. * @brief Get channel side flag.
  1526. * @note 0: Channel Left has to be transmitted or has been received\n
  1527. * 1: Channel Right has to be transmitted or has been received\n
  1528. * It has no significance in PCM mode.
  1529. * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
  1530. * @param SPIx SPI Instance
  1531. * @retval State of bit (1 or 0).
  1532. */
  1533. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
  1534. {
  1535. return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
  1536. }
  1537. /**
  1538. * @brief Clear overrun error flag
  1539. * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
  1540. * @param SPIx SPI Instance
  1541. * @retval None
  1542. */
  1543. __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
  1544. {
  1545. LL_SPI_ClearFlag_OVR(SPIx);
  1546. }
  1547. /**
  1548. * @brief Clear underrun error flag
  1549. * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
  1550. * @param SPIx SPI Instance
  1551. * @retval None
  1552. */
  1553. __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
  1554. {
  1555. __IO uint32_t tmpreg;
  1556. tmpreg = SPIx->SR;
  1557. (void)tmpreg;
  1558. }
  1559. /**
  1560. * @brief Clear frame format error flag
  1561. * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
  1562. * @param SPIx SPI Instance
  1563. * @retval None
  1564. */
  1565. __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
  1566. {
  1567. LL_SPI_ClearFlag_FRE(SPIx);
  1568. }
  1569. /**
  1570. * @}
  1571. */
  1572. /** @defgroup I2S_LL_EF_IT Interrupt Management
  1573. * @{
  1574. */
  1575. /**
  1576. * @brief Enable error IT
  1577. * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
  1578. * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
  1579. * @param SPIx SPI Instance
  1580. * @retval None
  1581. */
  1582. __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
  1583. {
  1584. LL_SPI_EnableIT_ERR(SPIx);
  1585. }
  1586. /**
  1587. * @brief Enable Rx buffer not empty IT
  1588. * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
  1589. * @param SPIx SPI Instance
  1590. * @retval None
  1591. */
  1592. __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
  1593. {
  1594. LL_SPI_EnableIT_RXNE(SPIx);
  1595. }
  1596. /**
  1597. * @brief Enable Tx buffer empty IT
  1598. * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
  1599. * @param SPIx SPI Instance
  1600. * @retval None
  1601. */
  1602. __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
  1603. {
  1604. LL_SPI_EnableIT_TXE(SPIx);
  1605. }
  1606. /**
  1607. * @brief Disable error IT
  1608. * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
  1609. * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
  1610. * @param SPIx SPI Instance
  1611. * @retval None
  1612. */
  1613. __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
  1614. {
  1615. LL_SPI_DisableIT_ERR(SPIx);
  1616. }
  1617. /**
  1618. * @brief Disable Rx buffer not empty IT
  1619. * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
  1620. * @param SPIx SPI Instance
  1621. * @retval None
  1622. */
  1623. __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
  1624. {
  1625. LL_SPI_DisableIT_RXNE(SPIx);
  1626. }
  1627. /**
  1628. * @brief Disable Tx buffer empty IT
  1629. * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
  1630. * @param SPIx SPI Instance
  1631. * @retval None
  1632. */
  1633. __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
  1634. {
  1635. LL_SPI_DisableIT_TXE(SPIx);
  1636. }
  1637. /**
  1638. * @brief Check if ERR IT is enabled
  1639. * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
  1640. * @param SPIx SPI Instance
  1641. * @retval State of bit (1 or 0).
  1642. */
  1643. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  1644. {
  1645. return LL_SPI_IsEnabledIT_ERR(SPIx);
  1646. }
  1647. /**
  1648. * @brief Check if RXNE IT is enabled
  1649. * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
  1650. * @param SPIx SPI Instance
  1651. * @retval State of bit (1 or 0).
  1652. */
  1653. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  1654. {
  1655. return LL_SPI_IsEnabledIT_RXNE(SPIx);
  1656. }
  1657. /**
  1658. * @brief Check if TXE IT is enabled
  1659. * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
  1660. * @param SPIx SPI Instance
  1661. * @retval State of bit (1 or 0).
  1662. */
  1663. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  1664. {
  1665. return LL_SPI_IsEnabledIT_TXE(SPIx);
  1666. }
  1667. /**
  1668. * @}
  1669. */
  1670. /** @defgroup I2S_LL_EF_DMA DMA Management
  1671. * @{
  1672. */
  1673. /**
  1674. * @brief Enable DMA Rx
  1675. * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
  1676. * @param SPIx SPI Instance
  1677. * @retval None
  1678. */
  1679. __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  1680. {
  1681. LL_SPI_EnableDMAReq_RX(SPIx);
  1682. }
  1683. /**
  1684. * @brief Disable DMA Rx
  1685. * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
  1686. * @param SPIx SPI Instance
  1687. * @retval None
  1688. */
  1689. __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  1690. {
  1691. LL_SPI_DisableDMAReq_RX(SPIx);
  1692. }
  1693. /**
  1694. * @brief Check if DMA Rx is enabled
  1695. * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
  1696. * @param SPIx SPI Instance
  1697. * @retval State of bit (1 or 0).
  1698. */
  1699. __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  1700. {
  1701. return LL_SPI_IsEnabledDMAReq_RX(SPIx);
  1702. }
  1703. /**
  1704. * @brief Enable DMA Tx
  1705. * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
  1706. * @param SPIx SPI Instance
  1707. * @retval None
  1708. */
  1709. __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  1710. {
  1711. LL_SPI_EnableDMAReq_TX(SPIx);
  1712. }
  1713. /**
  1714. * @brief Disable DMA Tx
  1715. * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
  1716. * @param SPIx SPI Instance
  1717. * @retval None
  1718. */
  1719. __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  1720. {
  1721. LL_SPI_DisableDMAReq_TX(SPIx);
  1722. }
  1723. /**
  1724. * @brief Check if DMA Tx is enabled
  1725. * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
  1726. * @param SPIx SPI Instance
  1727. * @retval State of bit (1 or 0).
  1728. */
  1729. __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  1730. {
  1731. return LL_SPI_IsEnabledDMAReq_TX(SPIx);
  1732. }
  1733. /**
  1734. * @}
  1735. */
  1736. /** @defgroup I2S_LL_EF_DATA DATA Management
  1737. * @{
  1738. */
  1739. /**
  1740. * @brief Read 16-Bits in data register
  1741. * @rmtoll DR DR LL_I2S_ReceiveData16
  1742. * @param SPIx SPI Instance
  1743. * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
  1744. */
  1745. __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
  1746. {
  1747. return LL_SPI_ReceiveData16(SPIx);
  1748. }
  1749. /**
  1750. * @brief Write 16-Bits in data register
  1751. * @rmtoll DR DR LL_I2S_TransmitData16
  1752. * @param SPIx SPI Instance
  1753. * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
  1754. * @retval None
  1755. */
  1756. __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  1757. {
  1758. LL_SPI_TransmitData16(SPIx, TxData);
  1759. }
  1760. /**
  1761. * @}
  1762. */
  1763. #if defined(USE_FULL_LL_DRIVER)
  1764. /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
  1765. * @{
  1766. */
  1767. ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
  1768. ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
  1769. void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
  1770. void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
  1771. /**
  1772. * @}
  1773. */
  1774. #endif /* USE_FULL_LL_DRIVER */
  1775. /**
  1776. * @}
  1777. */
  1778. /**
  1779. * @}
  1780. */
  1781. #endif /* SPI_I2S_SUPPORT */
  1782. #endif /* defined (SPI1) || defined (SPI2) */
  1783. /**
  1784. * @}
  1785. */
  1786. #ifdef __cplusplus
  1787. }
  1788. #endif
  1789. #endif /* STM32L0xx_LL_SPI_H */
  1790. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/