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  1. ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
  2. ;* File Name : startup_stm32f030xc.s
  3. ;* Author : MCD Application Team
  4. ;* Description : STM32F030xc/STM32F030xb devices vector table for MDK-ARM toolchain.
  5. ;* This module performs:
  6. ;* - Set the initial SP
  7. ;* - Set the initial PC == Reset_Handler
  8. ;* - Set the vector table entries with the exceptions ISR address
  9. ;* - Branches to __main in the C library (which eventually
  10. ;* calls main()).
  11. ;* After Reset the CortexM0 processor is in Thread mode,
  12. ;* priority is Privileged, and the Stack is set to Main.
  13. ;* <<< Use Configuration Wizard in Context Menu >>>
  14. ;*******************************************************************************
  15. ;*
  16. ;* Redistribution and use in source and binary forms, with or without modification,
  17. ;* are permitted provided that the following conditions are met:
  18. ;* 1. Redistributions of source code must retain the above copyright notice,
  19. ;* this list of conditions and the following disclaimer.
  20. ;* 2. Redistributions in binary form must reproduce the above copyright notice,
  21. ;* this list of conditions and the following disclaimer in the documentation
  22. ;* and/or other materials provided with the distribution.
  23. ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
  24. ;* may be used to endorse or promote products derived from this software
  25. ;* without specific prior written permission.
  26. ;*
  27. ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  28. ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  29. ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  30. ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  31. ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  33. ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  34. ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  35. ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36. ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. ;
  38. ;*******************************************************************************
  39. ; Amount of memory (in bytes) allocated for Stack
  40. ; Tailor this value to your application needs
  41. ; <h> Stack Configuration
  42. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  43. ; </h>
  44. Stack_Size EQU 0x00000400
  45. AREA STACK, NOINIT, READWRITE, ALIGN=3
  46. Stack_Mem SPACE Stack_Size
  47. __initial_sp
  48. ; <h> Heap Configuration
  49. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  50. ; </h>
  51. Heap_Size EQU 0x00000200
  52. AREA HEAP, NOINIT, READWRITE, ALIGN=3
  53. __heap_base
  54. Heap_Mem SPACE Heap_Size
  55. __heap_limit
  56. PRESERVE8
  57. THUMB
  58. ; Vector Table Mapped to Address 0 at Reset
  59. AREA RESET, DATA, READONLY
  60. EXPORT __Vectors
  61. EXPORT __Vectors_End
  62. EXPORT __Vectors_Size
  63. __Vectors DCD __initial_sp ; Top of Stack
  64. DCD Reset_Handler ; Reset Handler
  65. DCD NMI_Handler ; NMI Handler
  66. DCD HardFault_Handler ; Hard Fault Handler
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD 0 ; Reserved
  71. DCD 0 ; Reserved
  72. DCD 0 ; Reserved
  73. DCD 0 ; Reserved
  74. DCD SVC_Handler ; SVCall Handler
  75. DCD 0 ; Reserved
  76. DCD 0 ; Reserved
  77. DCD PendSV_Handler ; PendSV Handler
  78. DCD SysTick_Handler ; SysTick Handler
  79. ; External Interrupts
  80. DCD WWDG_IRQHandler ; Window Watchdog
  81. DCD 0 ; Reserved
  82. DCD RTC_IRQHandler ; RTC through EXTI Line
  83. DCD FLASH_IRQHandler ; FLASH
  84. DCD RCC_IRQHandler ; RCC
  85. DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
  86. DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
  87. DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
  88. DCD 0 ; Reserved
  89. DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
  90. DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
  91. DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
  92. DCD ADC1_IRQHandler ; ADC1
  93. DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
  94. DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
  95. DCD 0 ; Reserved
  96. DCD TIM3_IRQHandler ; TIM3
  97. DCD TIM6_IRQHandler ; TIM6
  98. DCD TIM7_IRQHandler ; TIM7
  99. DCD TIM14_IRQHandler ; TIM14
  100. DCD TIM15_IRQHandler ; TIM15
  101. DCD TIM16_IRQHandler ; TIM16
  102. DCD TIM17_IRQHandler ; TIM17
  103. DCD I2C1_IRQHandler ; I2C1
  104. DCD I2C2_IRQHandler ; I2C2
  105. DCD SPI1_IRQHandler ; SPI1
  106. DCD SPI2_IRQHandler ; SPI2
  107. DCD USART1_IRQHandler ; USART1
  108. DCD USART2_IRQHandler ; USART2
  109. DCD USART3_6_IRQHandler ; USART3, USART4, USART5, USART6
  110. __Vectors_End
  111. __Vectors_Size EQU __Vectors_End - __Vectors
  112. AREA |.text|, CODE, READONLY
  113. ; Reset handler routine
  114. Reset_Handler PROC
  115. EXPORT Reset_Handler [WEAK]
  116. IMPORT __main
  117. IMPORT SystemInit
  118. LDR R0, =SystemInit
  119. BLX R0
  120. LDR R0, =__main
  121. BX R0
  122. ENDP
  123. ; Dummy Exception Handlers (infinite loops which can be modified)
  124. NMI_Handler PROC
  125. EXPORT NMI_Handler [WEAK]
  126. B .
  127. ENDP
  128. HardFault_Handler\
  129. PROC
  130. EXPORT HardFault_Handler [WEAK]
  131. B .
  132. ENDP
  133. SVC_Handler PROC
  134. EXPORT SVC_Handler [WEAK]
  135. B .
  136. ENDP
  137. PendSV_Handler PROC
  138. EXPORT PendSV_Handler [WEAK]
  139. B .
  140. ENDP
  141. SysTick_Handler PROC
  142. EXPORT SysTick_Handler [WEAK]
  143. B .
  144. ENDP
  145. Default_Handler PROC
  146. EXPORT WWDG_IRQHandler [WEAK]
  147. EXPORT RTC_IRQHandler [WEAK]
  148. EXPORT FLASH_IRQHandler [WEAK]
  149. EXPORT RCC_IRQHandler [WEAK]
  150. EXPORT EXTI0_1_IRQHandler [WEAK]
  151. EXPORT EXTI2_3_IRQHandler [WEAK]
  152. EXPORT EXTI4_15_IRQHandler [WEAK]
  153. EXPORT DMA1_Channel1_IRQHandler [WEAK]
  154. EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
  155. EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
  156. EXPORT ADC1_IRQHandler [WEAK]
  157. EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
  158. EXPORT TIM1_CC_IRQHandler [WEAK]
  159. EXPORT TIM3_IRQHandler [WEAK]
  160. EXPORT TIM6_IRQHandler [WEAK]
  161. EXPORT TIM7_IRQHandler [WEAK]
  162. EXPORT TIM14_IRQHandler [WEAK]
  163. EXPORT TIM15_IRQHandler [WEAK]
  164. EXPORT TIM16_IRQHandler [WEAK]
  165. EXPORT TIM17_IRQHandler [WEAK]
  166. EXPORT I2C1_IRQHandler [WEAK]
  167. EXPORT I2C2_IRQHandler [WEAK]
  168. EXPORT SPI1_IRQHandler [WEAK]
  169. EXPORT SPI2_IRQHandler [WEAK]
  170. EXPORT USART1_IRQHandler [WEAK]
  171. EXPORT USART2_IRQHandler [WEAK]
  172. EXPORT USART3_6_IRQHandler [WEAK]
  173. WWDG_IRQHandler
  174. RTC_IRQHandler
  175. FLASH_IRQHandler
  176. RCC_IRQHandler
  177. EXTI0_1_IRQHandler
  178. EXTI2_3_IRQHandler
  179. EXTI4_15_IRQHandler
  180. DMA1_Channel1_IRQHandler
  181. DMA1_Channel2_3_IRQHandler
  182. DMA1_Channel4_5_IRQHandler
  183. ADC1_IRQHandler
  184. TIM1_BRK_UP_TRG_COM_IRQHandler
  185. TIM1_CC_IRQHandler
  186. TIM3_IRQHandler
  187. TIM6_IRQHandler
  188. TIM7_IRQHandler
  189. TIM14_IRQHandler
  190. TIM15_IRQHandler
  191. TIM16_IRQHandler
  192. TIM17_IRQHandler
  193. I2C1_IRQHandler
  194. I2C2_IRQHandler
  195. SPI1_IRQHandler
  196. SPI2_IRQHandler
  197. USART1_IRQHandler
  198. USART2_IRQHandler
  199. USART3_6_IRQHandler
  200. B .
  201. ENDP
  202. ALIGN
  203. ;*******************************************************************************
  204. ; User Stack and Heap initialization
  205. ;*******************************************************************************
  206. IF :DEF:__MICROLIB
  207. EXPORT __initial_sp
  208. EXPORT __heap_base
  209. EXPORT __heap_limit
  210. ELSE
  211. IMPORT __use_two_region_memory
  212. EXPORT __user_initial_stackheap
  213. __user_initial_stackheap
  214. LDR R0, = Heap_Mem
  215. LDR R1, =(Stack_Mem + Stack_Size)
  216. LDR R2, = (Heap_Mem + Heap_Size)
  217. LDR R3, = Stack_Mem
  218. BX LR
  219. ALIGN
  220. ENDIF
  221. END
  222. ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****