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  1. ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
  2. ;* File Name : startup_stm32f051x8.s
  3. ;* Author : MCD Application Team
  4. ;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table
  5. ;* for EWARM toolchain.
  6. ;* This module performs:
  7. ;* - Set the initial SP
  8. ;* - Set the initial PC == __iar_program_start,
  9. ;* - Set the vector table entries with the exceptions ISR
  10. ;* address,
  11. ;* - Branches to main in the C library (which eventually
  12. ;* calls main()).
  13. ;* After Reset the Cortex-M0 processor is in Thread mode,
  14. ;* priority is Privileged, and the Stack is set to Main.
  15. ;*******************************************************************************
  16. ;*
  17. ;* Redistribution and use in source and binary forms, with or without modification,
  18. ;* are permitted provided that the following conditions are met:
  19. ;* 1. Redistributions of source code must retain the above copyright notice,
  20. ;* this list of conditions and the following disclaimer.
  21. ;* 2. Redistributions in binary form must reproduce the above copyright notice,
  22. ;* this list of conditions and the following disclaimer in the documentation
  23. ;* and/or other materials provided with the distribution.
  24. ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
  25. ;* may be used to endorse or promote products derived from this software
  26. ;* without specific prior written permission.
  27. ;*
  28. ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32. ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34. ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36. ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37. ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. ;*
  39. ;*******************************************************************************
  40. ;
  41. ;
  42. ; The modules in this file are included in the libraries, and may be replaced
  43. ; by any user-defined modules that define the PUBLIC symbol _program_start or
  44. ; a user defined start symbol.
  45. ; To override the cstartup defined in the library, simply add your modified
  46. ; version to the workbench project.
  47. ;
  48. ; The vector table is normally located at address 0.
  49. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
  50. ; The name "__vector_table" has special meaning for C-SPY:
  51. ; it is where the SP start value is found, and the NVIC vector
  52. ; table register (VTOR) is initialized to this address if != 0.
  53. ;
  54. ; Cortex-M version
  55. ;
  56. MODULE ?cstartup
  57. ;; Forward declaration of sections.
  58. SECTION CSTACK:DATA:NOROOT(3)
  59. SECTION .intvec:CODE:NOROOT(2)
  60. EXTERN __iar_program_start
  61. EXTERN SystemInit
  62. PUBLIC __vector_table
  63. DATA
  64. __vector_table
  65. DCD sfe(CSTACK)
  66. DCD Reset_Handler ; Reset Handler
  67. DCD NMI_Handler ; NMI Handler
  68. DCD HardFault_Handler ; Hard Fault Handler
  69. DCD 0 ; Reserved
  70. DCD 0 ; Reserved
  71. DCD 0 ; Reserved
  72. DCD 0 ; Reserved
  73. DCD 0 ; Reserved
  74. DCD 0 ; Reserved
  75. DCD 0 ; Reserved
  76. DCD SVC_Handler ; SVCall Handler
  77. DCD 0 ; Reserved
  78. DCD 0 ; Reserved
  79. DCD PendSV_Handler ; PendSV Handler
  80. DCD SysTick_Handler ; SysTick Handler
  81. ; External Interrupts
  82. DCD WWDG_IRQHandler ; Window Watchdog
  83. DCD PVD_IRQHandler ; PVD through EXTI Line detect
  84. DCD RTC_IRQHandler ; RTC through EXTI Line
  85. DCD FLASH_IRQHandler ; FLASH
  86. DCD RCC_CRS_IRQHandler ; RCC and CRS
  87. DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
  88. DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
  89. DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
  90. DCD TSC_IRQHandler ; TSC
  91. DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
  92. DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
  93. DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
  94. DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
  95. DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
  96. DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
  97. DCD TIM2_IRQHandler ; TIM2
  98. DCD TIM3_IRQHandler ; TIM3
  99. DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
  100. DCD 0 ; Reserved
  101. DCD TIM14_IRQHandler ; TIM14
  102. DCD TIM15_IRQHandler ; TIM15
  103. DCD TIM16_IRQHandler ; TIM16
  104. DCD TIM17_IRQHandler ; TIM17
  105. DCD I2C1_IRQHandler ; I2C1
  106. DCD I2C2_IRQHandler ; I2C2
  107. DCD SPI1_IRQHandler ; SPI1
  108. DCD SPI2_IRQHandler ; SPI2
  109. DCD USART1_IRQHandler ; USART1
  110. DCD USART2_IRQHandler ; USART2
  111. DCD 0 ; Reserved
  112. DCD CEC_CAN_IRQHandler ; CEC and CAN
  113. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  114. ;;
  115. ;; Default interrupt handlers.
  116. ;;
  117. THUMB
  118. PUBWEAK Reset_Handler
  119. SECTION .text:CODE:NOROOT:REORDER(2)
  120. Reset_Handler
  121. LDR R0, =SystemInit
  122. BLX R0
  123. LDR R0, =__iar_program_start
  124. BX R0
  125. PUBWEAK NMI_Handler
  126. SECTION .text:CODE:NOROOT:REORDER(1)
  127. NMI_Handler
  128. B NMI_Handler
  129. PUBWEAK HardFault_Handler
  130. SECTION .text:CODE:NOROOT:REORDER(1)
  131. HardFault_Handler
  132. B HardFault_Handler
  133. PUBWEAK SVC_Handler
  134. SECTION .text:CODE:NOROOT:REORDER(1)
  135. SVC_Handler
  136. B SVC_Handler
  137. PUBWEAK PendSV_Handler
  138. SECTION .text:CODE:NOROOT:REORDER(1)
  139. PendSV_Handler
  140. B PendSV_Handler
  141. PUBWEAK SysTick_Handler
  142. SECTION .text:CODE:NOROOT:REORDER(1)
  143. SysTick_Handler
  144. B SysTick_Handler
  145. PUBWEAK WWDG_IRQHandler
  146. SECTION .text:CODE:NOROOT:REORDER(1)
  147. WWDG_IRQHandler
  148. B WWDG_IRQHandler
  149. PUBWEAK PVD_IRQHandler
  150. SECTION .text:CODE:NOROOT:REORDER(1)
  151. PVD_IRQHandler
  152. B PVD_IRQHandler
  153. PUBWEAK RTC_IRQHandler
  154. SECTION .text:CODE:NOROOT:REORDER(1)
  155. RTC_IRQHandler
  156. B RTC_IRQHandler
  157. PUBWEAK FLASH_IRQHandler
  158. SECTION .text:CODE:NOROOT:REORDER(1)
  159. FLASH_IRQHandler
  160. B FLASH_IRQHandler
  161. PUBWEAK RCC_CRS_IRQHandler
  162. SECTION .text:CODE:NOROOT:REORDER(1)
  163. RCC_CRS_IRQHandler
  164. B RCC_CRS_IRQHandler
  165. PUBWEAK EXTI0_1_IRQHandler
  166. SECTION .text:CODE:NOROOT:REORDER(1)
  167. EXTI0_1_IRQHandler
  168. B EXTI0_1_IRQHandler
  169. PUBWEAK EXTI2_3_IRQHandler
  170. SECTION .text:CODE:NOROOT:REORDER(1)
  171. EXTI2_3_IRQHandler
  172. B EXTI2_3_IRQHandler
  173. PUBWEAK EXTI4_15_IRQHandler
  174. SECTION .text:CODE:NOROOT:REORDER(1)
  175. EXTI4_15_IRQHandler
  176. B EXTI4_15_IRQHandler
  177. PUBWEAK TSC_IRQHandler
  178. SECTION .text:CODE:NOROOT:REORDER(1)
  179. TSC_IRQHandler
  180. B TSC_IRQHandler
  181. PUBWEAK DMA1_Channel1_IRQHandler
  182. SECTION .text:CODE:NOROOT:REORDER(1)
  183. DMA1_Channel1_IRQHandler
  184. B DMA1_Channel1_IRQHandler
  185. PUBWEAK DMA1_Channel2_3_IRQHandler
  186. SECTION .text:CODE:NOROOT:REORDER(1)
  187. DMA1_Channel2_3_IRQHandler
  188. B DMA1_Channel2_3_IRQHandler
  189. PUBWEAK DMA1_Channel4_5_IRQHandler
  190. SECTION .text:CODE:NOROOT:REORDER(1)
  191. DMA1_Channel4_5_IRQHandler
  192. B DMA1_Channel4_5_IRQHandler
  193. PUBWEAK ADC1_COMP_IRQHandler
  194. SECTION .text:CODE:NOROOT:REORDER(1)
  195. ADC1_COMP_IRQHandler
  196. B ADC1_COMP_IRQHandler
  197. PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
  198. SECTION .text:CODE:NOROOT:REORDER(1)
  199. TIM1_BRK_UP_TRG_COM_IRQHandler
  200. B TIM1_BRK_UP_TRG_COM_IRQHandler
  201. PUBWEAK TIM1_CC_IRQHandler
  202. SECTION .text:CODE:NOROOT:REORDER(1)
  203. TIM1_CC_IRQHandler
  204. B TIM1_CC_IRQHandler
  205. PUBWEAK TIM2_IRQHandler
  206. SECTION .text:CODE:NOROOT:REORDER(1)
  207. TIM2_IRQHandler
  208. B TIM2_IRQHandler
  209. PUBWEAK TIM3_IRQHandler
  210. SECTION .text:CODE:NOROOT:REORDER(1)
  211. TIM3_IRQHandler
  212. B TIM3_IRQHandler
  213. PUBWEAK TIM6_DAC_IRQHandler
  214. SECTION .text:CODE:NOROOT:REORDER(1)
  215. TIM6_DAC_IRQHandler
  216. B TIM6_DAC_IRQHandler
  217. PUBWEAK TIM14_IRQHandler
  218. SECTION .text:CODE:NOROOT:REORDER(1)
  219. TIM14_IRQHandler
  220. B TIM14_IRQHandler
  221. PUBWEAK TIM15_IRQHandler
  222. SECTION .text:CODE:NOROOT:REORDER(1)
  223. TIM15_IRQHandler
  224. B TIM15_IRQHandler
  225. PUBWEAK TIM16_IRQHandler
  226. SECTION .text:CODE:NOROOT:REORDER(1)
  227. TIM16_IRQHandler
  228. B TIM16_IRQHandler
  229. PUBWEAK TIM17_IRQHandler
  230. SECTION .text:CODE:NOROOT:REORDER(1)
  231. TIM17_IRQHandler
  232. B TIM17_IRQHandler
  233. PUBWEAK I2C1_IRQHandler
  234. SECTION .text:CODE:NOROOT:REORDER(1)
  235. I2C1_IRQHandler
  236. B I2C1_IRQHandler
  237. PUBWEAK I2C2_IRQHandler
  238. SECTION .text:CODE:NOROOT:REORDER(1)
  239. I2C2_IRQHandler
  240. B I2C2_IRQHandler
  241. PUBWEAK SPI1_IRQHandler
  242. SECTION .text:CODE:NOROOT:REORDER(1)
  243. SPI1_IRQHandler
  244. B SPI1_IRQHandler
  245. PUBWEAK SPI2_IRQHandler
  246. SECTION .text:CODE:NOROOT:REORDER(1)
  247. SPI2_IRQHandler
  248. B SPI2_IRQHandler
  249. PUBWEAK USART1_IRQHandler
  250. SECTION .text:CODE:NOROOT:REORDER(1)
  251. USART1_IRQHandler
  252. B USART1_IRQHandler
  253. PUBWEAK USART2_IRQHandler
  254. SECTION .text:CODE:NOROOT:REORDER(1)
  255. USART2_IRQHandler
  256. B USART2_IRQHandler
  257. PUBWEAK CEC_CAN_IRQHandler
  258. SECTION .text:CODE:NOROOT:REORDER(1)
  259. CEC_CAN_IRQHandler
  260. B CEC_CAN_IRQHandler
  261. END
  262. ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****