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stm32lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32h7xx_hal_rcc.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of RCC HAL module.

  6.   ******************************************************************************

  7.   * @attention

  8.   *

  9.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

  10.   * All rights reserved.</center></h2>

  11.   *

  12.   * This software component is licensed by ST under BSD 3-Clause license,

  13.   * the "License"; You may not use this file except in compliance with the

  14.   * License. You may obtain a copy of the License at:

  15.   *                        opensource.org/licenses/BSD-3-Clause

  16.   *

  17.   ******************************************************************************

  18.   */

  19. 

  20. /* Define to prevent recursive inclusion -------------------------------------*/

  21. #ifndef STM32H7xx_HAL_RCC_H

  22. #define STM32H7xx_HAL_RCC_H

  23. 

  24. #ifdef __cplusplus

  25.  extern "C" {

  26. #endif

  27. 

  28. /* Includes ------------------------------------------------------------------*/

  29. #include "stm32h7xx_hal_def.h"

  30. 

  31. /** @addtogroup STM32H7xx_HAL_Driver

  32.   * @{

  33.   */

  34. 

  35. /** @addtogroup RCC

  36.   * @{

  37.   */

  38. 

  39. /* Exported types ------------------------------------------------------------*/

  40. 

  41. /** @defgroup RCC_Exported_Types RCC Exported Types

  42.   * @{

  43.   */

  44. 

  45. /**

  46.   * @brief  RCC PLL configuration structure definition

  47.   */

  48. typedef struct

  49. {

  50.   uint32_t PLLState;   /*!< The new state of the PLL.

  51.                             This parameter can be a value of @ref RCC_PLL_Config                      */

  52. 

  53.   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.

  54.                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */

  55. 

  56.   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.

  57.                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */

  58. 

  59.   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.

  60.                             This parameter must be a number between Min_Data = 4 and Max_Data = 512

  61.                             or between Min_Data = 8 and Max_Data = 420(*)

  62.                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */

  63. 

  64.   uint32_t PLLP;       /*!< PLLP: Division factor for system clock.

  65.                             This parameter must be a number between Min_Data = 2 and Max_Data = 128

  66.                           odd division factors are not allowed                                        */

  67. 

  68.   uint32_t PLLQ;       /*!< PLLQ: Division factor for peripheral clocks.

  69.                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

  70. 

  71.   uint32_t PLLR;       /*!< PLLR: Division factor for peripheral clocks.

  72.                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

  73.   uint32_t PLLRGE;     /*!<PLLRGE: PLL1 clock Input range

  74.                          This parameter must be a value of @ref RCC_PLL1_VCI_Range                    */

  75.   uint32_t PLLVCOSEL;  /*!<PLLVCOSEL: PLL1 clock Output range

  76.                          This parameter must be a value of @ref RCC_PLL1_VCO_Range                    */

  77. 

  78.   uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for

  79.                         PLL1 VCO It should be a value between 0 and 8191                              */

  80. 

  81. }RCC_PLLInitTypeDef;

  82. 

  83. /**

  84.   * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition

  85.   */

  86. typedef struct

  87. {

  88.   uint32_t OscillatorType;       /*!< The oscillators to be configured.

  89.                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */

  90. 

  91.   uint32_t HSEState;             /*!< The new state of the HSE.

  92.                                       This parameter can be a value of @ref RCC_HSE_Config                        */

  93. 

  94.   uint32_t LSEState;             /*!< The new state of the LSE.

  95.                                       This parameter can be a value of @ref RCC_LSE_Config                        */

  96. 

  97.   uint32_t HSIState;             /*!< The new state of the HSI.

  98.                                       This parameter can be a value of @ref RCC_HSI_Config                        */

  99. 

  100.   uint32_t HSICalibrationValue;  /*!< The calibration trimming value.

  101.                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y

  102.                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */

  103. 

  104.   uint32_t LSIState;             /*!< The new state of the LSI.

  105.                                       This parameter can be a value of @ref RCC_LSI_Config                        */

  106. 

  107.  uint32_t HSI48State;            /*!< The new state of the HSI48.

  108.                                       This parameter can be a value of @ref RCC_HSI48_Config                      */

  109. 

  110.   uint32_t CSIState;             /*!< The new state of the CSI.

  111.                                       This parameter can be a value of @ref RCC_CSI_Config */

  112. 

  113.   uint32_t CSICalibrationValue;  /*!< The calibration trimming value.

  114.                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y

  115.                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */

  116. 

  117.   RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */

  118. 

  119. }RCC_OscInitTypeDef;

  120. 

  121. /**

  122.   * @brief  RCC System, AHB and APB busses clock configuration structure definition

  123.   */

  124. typedef struct

  125. {

  126.   uint32_t ClockType;             /*!< The clock to be configured.

  127.                                        This parameter can be a value of @ref RCC_System_Clock_Type                          */

  128. 

  129.   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.

  130.                                        This parameter can be a value of @ref RCC_System_Clock_Source                        */

  131. 

  132.   uint32_t SYSCLKDivider;         /*!< The system clock  divider. This parameter can be

  133.                                        a value of @ref RCC_SYS_Clock_Source                                                 */

  134. 

  135.   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).

  136.                                        This parameter can be a value of @ref RCC_HCLK_Clock_Source                          */

  137. 

  138.   uint32_t APB3CLKDivider;        /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).

  139.                                        This parameter can be a value of @ref RCC_APB3_Clock_Source                        */

  140. 

  141.   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).

  142.                                        This parameter can be a value of @ref RCC_APB1_Clock_Source                        */

  143.   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).

  144.                                        This parameter can be a value of @ref RCC_APB2_Clock_Source                        */

  145.   uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).

  146.                                        This parameter can be a value of @ref RCC_APB4_Clock_Source                        */

  147. }RCC_ClkInitTypeDef;

  148. 

  149. /**

  150.   * @}

  151.   */

  152. 

  153. /* Exported constants --------------------------------------------------------*/

  154. 

  155. /** @defgroup RCC_Exported_Constants RCC Exported Constants

  156.   * @{

  157.   */

  158. 

  159. /** @defgroup RCC_Oscillator_Type  RCC Oscillator Type

  160.   * @{

  161.   */

  162. #define RCC_OSCILLATORTYPE_NONE        (0x00000000U)

  163. #define RCC_OSCILLATORTYPE_HSE         (0x00000001U)

  164. #define RCC_OSCILLATORTYPE_HSI         (0x00000002U)

  165. #define RCC_OSCILLATORTYPE_LSE         (0x00000004U)

  166. #define RCC_OSCILLATORTYPE_LSI         (0x00000008U)

  167. #define RCC_OSCILLATORTYPE_CSI         (0x00000010U)

  168. #define RCC_OSCILLATORTYPE_HSI48       (0x00000020U)

  169. 

  170. /**

  171.   * @}

  172.   */

  173. 

  174. /** @defgroup RCC_HSE_Config  RCC HSE Config

  175.   * @{

  176.   */

  177. #define RCC_HSE_OFF                    (0x00000000U)

  178. #define RCC_HSE_ON                     RCC_CR_HSEON

  179. #define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

  180. #if defined(RCC_CR_HSEEXT)

  181. #define RCC_HSE_BYPASS_DIGITAL         ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))

  182. #endif /* RCC_CR_HSEEXT */

  183. 

  184. /**

  185.   * @}

  186.   */

  187. 

  188. /** @defgroup RCC_LSE_Config  RCC LSE Config

  189.   * @{

  190.   */

  191. #define RCC_LSE_OFF                    (0x00000000U)

  192. #define RCC_LSE_ON                     RCC_BDCR_LSEON

  193. #define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

  194. #if defined(RCC_BDCR_LSEEXT)

  195. #define RCC_LSE_BYPASS_DIGITAL         ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

  196. #endif /* RCC_BDCR_LSEEXT */

  197. 

  198. /**

  199.   * @}

  200.   */

  201. 

  202. /** @defgroup RCC_HSI_Config  RCC HSI Config

  203.   * @{

  204.   */

  205. #define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */

  206. #define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */

  207. 

  208. #define RCC_HSI_DIV1                     (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */

  209. #define RCC_HSI_DIV2                     (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */

  210. #define RCC_HSI_DIV4                     (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */

  211. #define RCC_HSI_DIV8                     (RCC_CR_HSIDIV | RCC_CR_HSION)   /*!< HSI_DIV8 clock activation */

  212. 

  213. 

  214. #if defined(RCC_HSICFGR_HSITRIM_6)

  215. #define RCC_HSICALIBRATION_DEFAULT     (0x40U)         /* Default HSI calibration trimming value, for STM32H7 rev.V and above  */

  216. #else

  217. #define RCC_HSICALIBRATION_DEFAULT     (0x20U)         /* Default HSI calibration trimming value, for STM32H7 rev.Y */

  218. #endif

  219. /**

  220.   * @}

  221.   */

  222. 

  223. /** @defgroup RCC_HSI48_Config  RCC HSI48 Config

  224.   * @{

  225.   */

  226. #define RCC_HSI48_OFF                      ((uint8_t)0x00)

  227. #define RCC_HSI48_ON                       ((uint8_t)0x01)

  228. 

  229. /**

  230.   * @}

  231.   */

  232. 

  233. /** @defgroup RCC_LSI_Config  RCC LSI Config

  234.   * @{

  235.   */

  236. #define RCC_LSI_OFF                    (0x00000000U)

  237. #define RCC_LSI_ON                     RCC_CSR_LSION

  238. 

  239. /**

  240.   * @}

  241.   */

  242. 

  243. /** @defgroup RCC_CSI_Config  RCC CSI Config

  244.   * @{

  245.   */

  246. #define RCC_CSI_OFF                    (0x00000000U)

  247. #define RCC_CSI_ON                     RCC_CR_CSION

  248. 

  249. #if defined(RCC_CSICFGR_CSITRIM_5)

  250. #define RCC_CSICALIBRATION_DEFAULT     (0x20U)         /* Default CSI calibration trimming value */

  251. #else

  252. #define RCC_CSICALIBRATION_DEFAULT     (0x10U)         /* Default CSI calibration trimming value */

  253. #endif /* RCC_CSICFGR_CSITRIM_5 */

  254. /**

  255.   * @}

  256.   */

  257. 

  258. /** @defgroup RCC_PLL_Config  RCC PLL Config

  259.   * @{

  260.   */

  261. #define RCC_PLL_NONE                   (0x00000000U)

  262. #define RCC_PLL_OFF                    (0x00000001U)

  263. #define RCC_PLL_ON                     (0x00000002U)

  264. 

  265. /**

  266.   * @}

  267.   */

  268. 

  269. 

  270. /** @defgroup RCC_PLL_Clock_Source  RCC PLL Clock Source

  271.   * @{

  272.   */

  273. #define RCC_PLLSOURCE_HSI              (0x00000000U)

  274. #define RCC_PLLSOURCE_CSI              (0x00000001U)

  275. #define RCC_PLLSOURCE_HSE              (0x00000002U)

  276. #define RCC_PLLSOURCE_NONE             (0x00000003U)

  277. /**

  278.   * @}

  279.   */

  280. 

  281. /** @defgroup RCC_PLL_Clock_Output  RCC PLL Clock Output

  282.   * @{

  283.   */

  284. #define RCC_PLL1_DIVP                RCC_PLLCFGR_DIVP1EN

  285. #define RCC_PLL1_DIVQ                RCC_PLLCFGR_DIVQ1EN

  286. #define RCC_PLL1_DIVR                RCC_PLLCFGR_DIVR1EN

  287. 

  288. /**

  289.   * @}

  290.   */

  291. 

  292. 

  293. 

  294. /** @defgroup RCC_PLL1_VCI_Range  RCC PLL1 VCI Range

  295.   * @{

  296.   */

  297. #define RCC_PLL1VCIRANGE_0                RCC_PLLCFGR_PLL1RGE_0

  298. #define RCC_PLL1VCIRANGE_1                RCC_PLLCFGR_PLL1RGE_1

  299. #define RCC_PLL1VCIRANGE_2                RCC_PLLCFGR_PLL1RGE_2

  300. #define RCC_PLL1VCIRANGE_3                RCC_PLLCFGR_PLL1RGE_3

  301. 

  302. 

  303. /**

  304.   * @}

  305.   */

  306. 

  307. 

  308. /** @defgroup RCC_PLL1_VCO_Range  RCC PLL1 VCO Range

  309.   * @{

  310.   */

  311. #define RCC_PLL1VCOWIDE                 (0x00000000U)

  312. #define RCC_PLL1VCOMEDIUM               RCC_PLLCFGR_PLL1VCOSEL

  313. 

  314. /**

  315.   * @}

  316.   */

  317. 

  318. 

  319. /** @defgroup RCC_System_Clock_Type  RCC System Clock Type

  320.   * @{

  321.   */

  322. #define RCC_CLOCKTYPE_SYSCLK           (0x00000001U)

  323. #define RCC_CLOCKTYPE_HCLK             (0x00000002U)

  324. #define RCC_CLOCKTYPE_D1PCLK1          (0x00000004U)

  325. #define RCC_CLOCKTYPE_PCLK1            (0x00000008U)

  326. #define RCC_CLOCKTYPE_PCLK2            (0x00000010U)

  327. #define RCC_CLOCKTYPE_D3PCLK1          (0x00000020U)

  328. 

  329. /**

  330.   * @}

  331.   */

  332. 

  333. /** @defgroup RCC_System_Clock_Source  RCC System Clock Source

  334.   * @{

  335.   */

  336. #define RCC_SYSCLKSOURCE_CSI           RCC_CFGR_SW_CSI

  337. #define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI

  338. #define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE

  339. #define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL1

  340. 

  341. /**

  342.   * @}

  343.   */

  344. 

  345. /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status

  346.   * @{

  347.   */

  348. #define RCC_SYSCLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */

  349. #define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */

  350. #define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */

  351. #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */

  352. /**

  353.   * @}

  354.   */

  355. 

  356. /** @defgroup RCC_SYS_Clock_Source  RCC SYS Clock Source

  357.   * @{

  358.   */

  359. #if defined(RCC_D1CFGR_D1CPRE_DIV1)

  360. #define RCC_SYSCLK_DIV1                RCC_D1CFGR_D1CPRE_DIV1

  361. #define RCC_SYSCLK_DIV2                RCC_D1CFGR_D1CPRE_DIV2

  362. #define RCC_SYSCLK_DIV4                RCC_D1CFGR_D1CPRE_DIV4

  363. #define RCC_SYSCLK_DIV8                RCC_D1CFGR_D1CPRE_DIV8

  364. #define RCC_SYSCLK_DIV16               RCC_D1CFGR_D1CPRE_DIV16

  365. #define RCC_SYSCLK_DIV64               RCC_D1CFGR_D1CPRE_DIV64

  366. #define RCC_SYSCLK_DIV128              RCC_D1CFGR_D1CPRE_DIV128

  367. #define RCC_SYSCLK_DIV256              RCC_D1CFGR_D1CPRE_DIV256

  368. #define RCC_SYSCLK_DIV512              RCC_D1CFGR_D1CPRE_DIV512

  369. #else

  370. #define RCC_SYSCLK_DIV1                RCC_CDCFGR1_CDCPRE_DIV1

  371. #define RCC_SYSCLK_DIV2                RCC_CDCFGR1_CDCPRE_DIV2

  372. #define RCC_SYSCLK_DIV4                RCC_CDCFGR1_CDCPRE_DIV4

  373. #define RCC_SYSCLK_DIV8                RCC_CDCFGR1_CDCPRE_DIV8

  374. #define RCC_SYSCLK_DIV16               RCC_CDCFGR1_CDCPRE_DIV16

  375. #define RCC_SYSCLK_DIV64               RCC_CDCFGR1_CDCPRE_DIV64

  376. #define RCC_SYSCLK_DIV128              RCC_CDCFGR1_CDCPRE_DIV128

  377. #define RCC_SYSCLK_DIV256              RCC_CDCFGR1_CDCPRE_DIV256

  378. #define RCC_SYSCLK_DIV512              RCC_CDCFGR1_CDCPRE_DIV512

  379. #endif

  380. /**

  381.   * @}

  382.   */

  383. 

  384. 

  385. /** @defgroup RCC_HCLK_Clock_Source  RCC HCLK Clock Source

  386.   * @{

  387.   */

  388. #if defined(RCC_D1CFGR_HPRE_DIV1)

  389. #define RCC_HCLK_DIV1                RCC_D1CFGR_HPRE_DIV1

  390. #define RCC_HCLK_DIV2                RCC_D1CFGR_HPRE_DIV2

  391. #define RCC_HCLK_DIV4                RCC_D1CFGR_HPRE_DIV4

  392. #define RCC_HCLK_DIV8                RCC_D1CFGR_HPRE_DIV8

  393. #define RCC_HCLK_DIV16               RCC_D1CFGR_HPRE_DIV16

  394. #define RCC_HCLK_DIV64               RCC_D1CFGR_HPRE_DIV64

  395. #define RCC_HCLK_DIV128              RCC_D1CFGR_HPRE_DIV128

  396. #define RCC_HCLK_DIV256              RCC_D1CFGR_HPRE_DIV256

  397. #define RCC_HCLK_DIV512              RCC_D1CFGR_HPRE_DIV512

  398. #else

  399. #define RCC_HCLK_DIV1                RCC_CDCFGR1_HPRE_DIV1

  400. #define RCC_HCLK_DIV2                RCC_CDCFGR1_HPRE_DIV2

  401. #define RCC_HCLK_DIV4                RCC_CDCFGR1_HPRE_DIV4

  402. #define RCC_HCLK_DIV8                RCC_CDCFGR1_HPRE_DIV8

  403. #define RCC_HCLK_DIV16               RCC_CDCFGR1_HPRE_DIV16

  404. #define RCC_HCLK_DIV64               RCC_CDCFGR1_HPRE_DIV64

  405. #define RCC_HCLK_DIV128              RCC_CDCFGR1_HPRE_DIV128

  406. #define RCC_HCLK_DIV256              RCC_CDCFGR1_HPRE_DIV256

  407. #define RCC_HCLK_DIV512              RCC_CDCFGR1_HPRE_DIV512

  408. #endif

  409. /**

  410.   * @}

  411.   */

  412. 

  413. /** @defgroup RCC_APB3_Clock_Source  RCC APB3 Clock Source

  414.   * @{

  415.   */

  416. #if defined (RCC_D1CFGR_D1PPRE_DIV1)

  417. #define RCC_APB3_DIV1                  RCC_D1CFGR_D1PPRE_DIV1

  418. #define RCC_APB3_DIV2                  RCC_D1CFGR_D1PPRE_DIV2

  419. #define RCC_APB3_DIV4                  RCC_D1CFGR_D1PPRE_DIV4

  420. #define RCC_APB3_DIV8                  RCC_D1CFGR_D1PPRE_DIV8

  421. #define RCC_APB3_DIV16                 RCC_D1CFGR_D1PPRE_DIV16

  422. #else

  423. #define RCC_APB3_DIV1                  RCC_CDCFGR1_CDPPRE_DIV1

  424. #define RCC_APB3_DIV2                  RCC_CDCFGR1_CDPPRE_DIV2

  425. #define RCC_APB3_DIV4                  RCC_CDCFGR1_CDPPRE_DIV4

  426. #define RCC_APB3_DIV8                  RCC_CDCFGR1_CDPPRE_DIV8

  427. #define RCC_APB3_DIV16                 RCC_CDCFGR1_CDPPRE_DIV16

  428. #endif

  429. /**

  430.   * @}

  431.   */

  432. 

  433. /** @defgroup RCC_APB1_Clock_Source  RCC APB1 Clock Source

  434.   * @{

  435.   */

  436. #if defined (RCC_D2CFGR_D2PPRE1_DIV1)

  437. #define RCC_APB1_DIV1                  RCC_D2CFGR_D2PPRE1_DIV1

  438. #define RCC_APB1_DIV2                  RCC_D2CFGR_D2PPRE1_DIV2

  439. #define RCC_APB1_DIV4                  RCC_D2CFGR_D2PPRE1_DIV4

  440. #define RCC_APB1_DIV8                  RCC_D2CFGR_D2PPRE1_DIV8

  441. #define RCC_APB1_DIV16                 RCC_D2CFGR_D2PPRE1_DIV16

  442. #else

  443. #define RCC_APB1_DIV1                  RCC_CDCFGR2_CDPPRE1_DIV1

  444. #define RCC_APB1_DIV2                  RCC_CDCFGR2_CDPPRE1_DIV2

  445. #define RCC_APB1_DIV4                  RCC_CDCFGR2_CDPPRE1_DIV4

  446. #define RCC_APB1_DIV8                  RCC_CDCFGR2_CDPPRE1_DIV8

  447. #define RCC_APB1_DIV16                 RCC_CDCFGR2_CDPPRE1_DIV16

  448. #endif

  449. 

  450. /**

  451.   * @}

  452.   */

  453. 

  454. /** @defgroup RCC_APB2_Clock_Source  RCC APB2 Clock Source

  455.   * @{

  456.   */

  457. #if defined (RCC_D2CFGR_D2PPRE2_DIV1)

  458. #define RCC_APB2_DIV1                  RCC_D2CFGR_D2PPRE2_DIV1

  459. #define RCC_APB2_DIV2                  RCC_D2CFGR_D2PPRE2_DIV2

  460. #define RCC_APB2_DIV4                  RCC_D2CFGR_D2PPRE2_DIV4

  461. #define RCC_APB2_DIV8                  RCC_D2CFGR_D2PPRE2_DIV8

  462. #define RCC_APB2_DIV16                 RCC_D2CFGR_D2PPRE2_DIV16

  463. #else

  464. #define RCC_APB2_DIV1                  RCC_CDCFGR2_CDPPRE2_DIV1

  465. #define RCC_APB2_DIV2                  RCC_CDCFGR2_CDPPRE2_DIV2

  466. #define RCC_APB2_DIV4                  RCC_CDCFGR2_CDPPRE2_DIV4

  467. #define RCC_APB2_DIV8                  RCC_CDCFGR2_CDPPRE2_DIV8

  468. #define RCC_APB2_DIV16                 RCC_CDCFGR2_CDPPRE2_DIV16

  469. #endif

  470. /**

  471.   * @}

  472.   */

  473. 

  474. /** @defgroup RCC_APB4_Clock_Source  RCC APB4 Clock Source

  475.   * @{

  476.   */

  477. #if defined(RCC_D3CFGR_D3PPRE_DIV1)

  478. #define RCC_APB4_DIV1                  RCC_D3CFGR_D3PPRE_DIV1

  479. #define RCC_APB4_DIV2                  RCC_D3CFGR_D3PPRE_DIV2

  480. #define RCC_APB4_DIV4                  RCC_D3CFGR_D3PPRE_DIV4

  481. #define RCC_APB4_DIV8                  RCC_D3CFGR_D3PPRE_DIV8

  482. #define RCC_APB4_DIV16                 RCC_D3CFGR_D3PPRE_DIV16

  483. #else

  484. #define RCC_APB4_DIV1                  RCC_SRDCFGR_SRDPPRE_DIV1

  485. #define RCC_APB4_DIV2                  RCC_SRDCFGR_SRDPPRE_DIV2

  486. #define RCC_APB4_DIV4                  RCC_SRDCFGR_SRDPPRE_DIV4

  487. #define RCC_APB4_DIV8                  RCC_SRDCFGR_SRDPPRE_DIV8

  488. #define RCC_APB4_DIV16                 RCC_SRDCFGR_SRDPPRE_DIV16

  489. #endif

  490. /**

  491.   * @}

  492.   */

  493. 

  494. /** @defgroup RCC_RTC_Clock_Source  RCC RTC Clock Source

  495.   * @{

  496.   */

  497. #define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)

  498. #define RCC_RTCCLKSOURCE_LSE             (0x00000100U)

  499. #define RCC_RTCCLKSOURCE_LSI             (0x00000200U)

  500. #define RCC_RTCCLKSOURCE_HSE_DIV2        (0x00002300U)

  501. #define RCC_RTCCLKSOURCE_HSE_DIV3        (0x00003300U)

  502. #define RCC_RTCCLKSOURCE_HSE_DIV4        (0x00004300U)

  503. #define RCC_RTCCLKSOURCE_HSE_DIV5        (0x00005300U)

  504. #define RCC_RTCCLKSOURCE_HSE_DIV6        (0x00006300U)

  505. #define RCC_RTCCLKSOURCE_HSE_DIV7        (0x00007300U)

  506. #define RCC_RTCCLKSOURCE_HSE_DIV8        (0x00008300U)

  507. #define RCC_RTCCLKSOURCE_HSE_DIV9        (0x00009300U)

  508. #define RCC_RTCCLKSOURCE_HSE_DIV10       (0x0000A300U)

  509. #define RCC_RTCCLKSOURCE_HSE_DIV11       (0x0000B300U)

  510. #define RCC_RTCCLKSOURCE_HSE_DIV12       (0x0000C300U)

  511. #define RCC_RTCCLKSOURCE_HSE_DIV13       (0x0000D300U)

  512. #define RCC_RTCCLKSOURCE_HSE_DIV14       (0x0000E300U)

  513. #define RCC_RTCCLKSOURCE_HSE_DIV15       (0x0000F300U)

  514. #define RCC_RTCCLKSOURCE_HSE_DIV16       (0x00010300U)

  515. #define RCC_RTCCLKSOURCE_HSE_DIV17       (0x00011300U)

  516. #define RCC_RTCCLKSOURCE_HSE_DIV18       (0x00012300U)

  517. #define RCC_RTCCLKSOURCE_HSE_DIV19       (0x00013300U)

  518. #define RCC_RTCCLKSOURCE_HSE_DIV20       (0x00014300U)

  519. #define RCC_RTCCLKSOURCE_HSE_DIV21       (0x00015300U)

  520. #define RCC_RTCCLKSOURCE_HSE_DIV22       (0x00016300U)

  521. #define RCC_RTCCLKSOURCE_HSE_DIV23       (0x00017300U)

  522. #define RCC_RTCCLKSOURCE_HSE_DIV24       (0x00018300U)

  523. #define RCC_RTCCLKSOURCE_HSE_DIV25       (0x00019300U)

  524. #define RCC_RTCCLKSOURCE_HSE_DIV26       (0x0001A300U)

  525. #define RCC_RTCCLKSOURCE_HSE_DIV27       (0x0001B300U)

  526. #define RCC_RTCCLKSOURCE_HSE_DIV28       (0x0001C300U)

  527. #define RCC_RTCCLKSOURCE_HSE_DIV29       (0x0001D300U)

  528. #define RCC_RTCCLKSOURCE_HSE_DIV30       (0x0001E300U)

  529. #define RCC_RTCCLKSOURCE_HSE_DIV31       (0x0001F300U)

  530. #define RCC_RTCCLKSOURCE_HSE_DIV32       (0x00020300U)

  531. #define RCC_RTCCLKSOURCE_HSE_DIV33       (0x00021300U)

  532. #define RCC_RTCCLKSOURCE_HSE_DIV34       (0x00022300U)

  533. #define RCC_RTCCLKSOURCE_HSE_DIV35       (0x00023300U)

  534. #define RCC_RTCCLKSOURCE_HSE_DIV36       (0x00024300U)

  535. #define RCC_RTCCLKSOURCE_HSE_DIV37       (0x00025300U)

  536. #define RCC_RTCCLKSOURCE_HSE_DIV38       (0x00026300U)

  537. #define RCC_RTCCLKSOURCE_HSE_DIV39       (0x00027300U)

  538. #define RCC_RTCCLKSOURCE_HSE_DIV40       (0x00028300U)

  539. #define RCC_RTCCLKSOURCE_HSE_DIV41       (0x00029300U)

  540. #define RCC_RTCCLKSOURCE_HSE_DIV42       (0x0002A300U)

  541. #define RCC_RTCCLKSOURCE_HSE_DIV43       (0x0002B300U)

  542. #define RCC_RTCCLKSOURCE_HSE_DIV44       (0x0002C300U)

  543. #define RCC_RTCCLKSOURCE_HSE_DIV45       (0x0002D300U)

  544. #define RCC_RTCCLKSOURCE_HSE_DIV46       (0x0002E300U)

  545. #define RCC_RTCCLKSOURCE_HSE_DIV47       (0x0002F300U)

  546. #define RCC_RTCCLKSOURCE_HSE_DIV48       (0x00030300U)

  547. #define RCC_RTCCLKSOURCE_HSE_DIV49       (0x00031300U)

  548. #define RCC_RTCCLKSOURCE_HSE_DIV50       (0x00032300U)

  549. #define RCC_RTCCLKSOURCE_HSE_DIV51       (0x00033300U)

  550. #define RCC_RTCCLKSOURCE_HSE_DIV52       (0x00034300U)

  551. #define RCC_RTCCLKSOURCE_HSE_DIV53       (0x00035300U)

  552. #define RCC_RTCCLKSOURCE_HSE_DIV54       (0x00036300U)

  553. #define RCC_RTCCLKSOURCE_HSE_DIV55       (0x00037300U)

  554. #define RCC_RTCCLKSOURCE_HSE_DIV56       (0x00038300U)

  555. #define RCC_RTCCLKSOURCE_HSE_DIV57       (0x00039300U)

  556. #define RCC_RTCCLKSOURCE_HSE_DIV58       (0x0003A300U)

  557. #define RCC_RTCCLKSOURCE_HSE_DIV59       (0x0003B300U)

  558. #define RCC_RTCCLKSOURCE_HSE_DIV60       (0x0003C300U)

  559. #define RCC_RTCCLKSOURCE_HSE_DIV61       (0x0003D300U)

  560. #define RCC_RTCCLKSOURCE_HSE_DIV62       (0x0003E300U)

  561. #define RCC_RTCCLKSOURCE_HSE_DIV63       (0x0003F300U)

  562. 

  563. 

  564. /**

  565.   * @}

  566.   */

  567. 

  568. 

  569. /** @defgroup RCC_MCO_Index  RCC MCO Index

  570.   * @{

  571.   */

  572. #define RCC_MCO1                         (0x00000000U)

  573. #define RCC_MCO2                         (0x00000001U)

  574. 

  575. /**

  576.   * @}

  577.   */

  578. 

  579. /** @defgroup RCC_MCO1_Clock_Source  RCC MCO1 Clock Source

  580.   * @{

  581.   */

  582. #define RCC_MCO1SOURCE_HSI               (0x00000000U)

  583. #define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0

  584. #define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1

  585. #define RCC_MCO1SOURCE_PLL1QCLK          ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)

  586. #define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO1_2

  587. 

  588. /**

  589.   * @}

  590.   */

  591. 

  592. /** @defgroup RCC_MCO2_Clock_Source  RCC MCO2 Clock Source

  593.   * @{

  594.   */

  595. #define RCC_MCO2SOURCE_SYSCLK            (0x00000000U)

  596. #define RCC_MCO2SOURCE_PLL2PCLK          RCC_CFGR_MCO2_0

  597. #define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1

  598. #define RCC_MCO2SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)

  599. #define RCC_MCO2SOURCE_CSICLK            RCC_CFGR_MCO2_2

  600. #define RCC_MCO2SOURCE_LSICLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)

  601. 

  602. /**

  603.   * @}

  604.   */

  605. 

  606. /** @defgroup RCC_MCOx_Clock_Prescaler  RCC MCOx Clock Prescaler

  607.   * @{

  608.   */

  609. #define RCC_MCODIV_1                    RCC_CFGR_MCO1PRE_0

  610. #define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_1

  611. #define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)

  612. #define RCC_MCODIV_4                    RCC_CFGR_MCO1PRE_2

  613. #define RCC_MCODIV_5                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

  614. #define RCC_MCODIV_6                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

  615. #define RCC_MCODIV_7                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

  616. #define RCC_MCODIV_8                    RCC_CFGR_MCO1PRE_3

  617. #define RCC_MCODIV_9                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)

  618. #define RCC_MCODIV_10                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

  619. #define RCC_MCODIV_11                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

  620. #define RCC_MCODIV_12                   ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

  621. #define RCC_MCODIV_13                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

  622. #define RCC_MCODIV_14                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

  623. #define RCC_MCODIV_15                   RCC_CFGR_MCO1PRE

  624. 

  625. 

  626. /**

  627.   * @}

  628.   */

  629. 

  630. /** @defgroup RCC_Interrupt  RCC Interrupt

  631.   * @{

  632.   */

  633. #define RCC_IT_LSIRDY                  (0x00000001U)

  634. #define RCC_IT_LSERDY                  (0x00000002U)

  635. #define RCC_IT_HSIRDY                  (0x00000004U)

  636. #define RCC_IT_HSERDY                  (0x00000008U)

  637. #define RCC_IT_CSIRDY                  (0x00000010U)

  638. #define RCC_IT_HSI48RDY                (0x00000020U)

  639. #define RCC_IT_PLLRDY                  (0x00000040U)

  640. #define RCC_IT_PLL2RDY                 (0x00000080U)

  641. #define RCC_IT_PLL3RDY                 (0x00000100U)

  642. #define RCC_IT_LSECSS                  (0x00000200U)

  643. #define RCC_IT_CSS                     (0x00000400U)

  644. /**

  645.   * @}

  646.   */

  647. 

  648. /** @defgroup RCC_Flag  RCC Flag

  649.   *        Elements values convention: XXXYYYYYb

  650.   *           - YYYYY  : Flag position in the register

  651.   *           - XXX  : Register index

  652.   *                 - 001: CR register

  653.   *                 - 010: BDCR register

  654.   *                 - 011: CSR register

  655.   *                 - 100: RSR register

  656.   * @{

  657.   */

  658. /* Flags in the CR register */

  659. #define RCC_FLAG_HSIRDY                ((uint8_t)0x22)

  660. #define RCC_FLAG_HSIDIV                ((uint8_t)0x25)

  661. #define RCC_FLAG_CSIRDY                ((uint8_t)0x28)

  662. #define RCC_FLAG_HSI48RDY              ((uint8_t)0x2D)

  663. #if defined(RCC_CR_D1CKRDY)

  664. #define RCC_FLAG_D1CKRDY               ((uint8_t)0x2E)

  665. #else

  666. #define RCC_FLAG_CPUCKRDY              ((uint8_t)0x2E)

  667. #define RCC_FLAG_D1CKRDY               RCC_FLAG_CPUCKRDY   /* alias */

  668. #endif /* RCC_CR_D1CKRDY */

  669. #if defined(RCC_CR_D2CKRDY)

  670. #define RCC_FLAG_D2CKRDY               ((uint8_t)0x2F)

  671. #else

  672. #define RCC_FLAG_CDCKRDY               ((uint8_t)0x2F)

  673. #define RCC_FLAG_D2CKRDY               RCC_FLAG_CDCKRDY    /* alias */

  674. #endif /* RCC_CR_D2CKRDY */

  675. #define RCC_FLAG_HSERDY                ((uint8_t)0x31)

  676. #define RCC_FLAG_PLLRDY                ((uint8_t)0x39)

  677. #define RCC_FLAG_PLL2RDY               ((uint8_t)0x3B)

  678. #define RCC_FLAG_PLL3RDY               ((uint8_t)0x3D)

  679. /* Flags in the BDCR register */

  680. #define RCC_FLAG_LSERDY                ((uint8_t)0x41)

  681. 

  682. /* Flags in the CSR register */

  683. #define RCC_FLAG_LSIRDY                ((uint8_t)0x61)

  684. 

  685. /* Flags in the RSR register */

  686. #if defined(RCC_RSR_CPURSTF)

  687. #define RCC_FLAG_CPURST                ((uint8_t)0x91)

  688. #endif /* RCC_RSR_CPURSTF */

  689. 

  690. #if defined(RCC_RSR_D1RSTF)

  691. #define RCC_FLAG_D1RST                 ((uint8_t)0x93)

  692. #else

  693. #define RCC_FLAG_CDRST                 ((uint8_t)0x93)

  694. #endif /* RCC_RSR_D1RSTF */

  695. #if defined(RCC_RSR_D2RSTF)

  696. #define RCC_FLAG_D2RST                 ((uint8_t)0x94)

  697. #endif /* RCC_RSR_D2RSTF */

  698. #define RCC_FLAG_BORRST                ((uint8_t)0x95)

  699. #define RCC_FLAG_PINRST                ((uint8_t)0x96)

  700. #define RCC_FLAG_PORRST                ((uint8_t)0x97)

  701. #define RCC_FLAG_SFTRST                ((uint8_t)0x98)

  702. #define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)

  703. #define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)

  704. #define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)

  705. #define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)

  706. 

  707. #if defined(DUAL_CORE)

  708. #define RCC_FLAG_C1RST                 (RCC_FLAG_CPURST)

  709. #define RCC_FLAG_C2RST                 ((uint8_t)0x92)

  710. #define RCC_FLAG_SFTR1ST               (RCC_FLAG_SFTRST)

  711. #define RCC_FLAG_SFTR2ST               ((uint8_t)0x99)

  712. #define RCC_FLAG_WWDG2RST              ((uint8_t)0x9D)

  713. #define RCC_FLAG_IWDG2RST              ((uint8_t)0x9B)

  714. #endif /*DUAL_CORE*/

  715. 

  716. 

  717. /**

  718.   * @}

  719.   */

  720. 

  721. /** @defgroup RCC_LSEDrive_Config LSE Drive Config

  722.   * @{

  723.   */

  724. #define RCC_LSEDRIVE_LOW                 (0x00000000U) /*!< LSE low drive capability */

  725. #define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */

  726. #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */

  727. #define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */

  728. /**

  729.   * @}

  730.   */

  731. 

  732. /** @defgroup RCC_Stop_WakeUpClock  RCC Stop WakeUpClock

  733.   * @{

  734.   */

  735. #define RCC_STOP_WAKEUPCLOCK_HSI       (0x00000000U)

  736. #define RCC_STOP_WAKEUPCLOCK_CSI       RCC_CFGR_STOPWUCK

  737. 

  738. /**

  739.   * @}

  740.   */

  741. 

  742. /** @defgroup RCC_Stop_KernelWakeUpClock  RCC Stop KernelWakeUpClock

  743.   * @{

  744.   */

  745. #define RCC_STOP_KERWAKEUPCLOCK_HSI       (0x00000000U)

  746. #define RCC_STOP_KERWAKEUPCLOCK_CSI        RCC_CFGR_STOPKERWUCK

  747. 

  748. 

  749. /**

  750.   * @}

  751.   */

  752. 

  753. #if defined(RCC_VER_X)

  754. #define HAL_RCC_REV_Y_HSITRIM_Pos  (12U)

  755. #define HAL_RCC_REV_Y_HSITRIM_Msk  (0x3F000U)

  756. #define HAL_RCC_REV_Y_CSITRIM_Pos  (26U)

  757. #define HAL_RCC_REV_Y_CSITRIM_Msk  (0x7C000000U)

  758. #endif /* RCC_VER_X */

  759. 

  760. /**

  761.   * @}

  762.   */

  763. 

  764. /* Exported macros -----------------------------------------------------------*/

  765. 

  766. /** @defgroup RCC_Exported_Macros RCC Exported Macros

  767.   * @{

  768.   */

  769. 

  770. /** @brief  Enable or disable the AHB3 peripheral clock.

  771.   * @note   After reset, the peripheral clock (used for registers read/write access)

  772.   *         is disabled and the application software has to enable this clock before

  773.   *         using it.

  774.   */

  775. #define __HAL_RCC_MDMA_CLK_ENABLE()   do { \

  776.                                         __IO uint32_t tmpreg; \

  777.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

  778.                                         /* Delay after an RCC peripheral clock enabling */ \

  779.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

  780.                                         UNUSED(tmpreg); \

  781.                                        } while(0)

  782. 

  783. #define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \

  784.                                         __IO uint32_t tmpreg; \

  785.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

  786.                                         /* Delay after an RCC peripheral clock enabling */ \

  787.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

  788.                                         UNUSED(tmpreg); \

  789.                                        } while(0)

  790. 

  791. #if defined(JPEG)

  792. #define __HAL_RCC_JPGDECEN_CLK_ENABLE()   do { \

  793.                                         __IO uint32_t tmpreg; \

  794.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

  795.                                         /* Delay after an RCC peripheral clock enabling */ \

  796.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

  797.                                         UNUSED(tmpreg); \

  798.                                        } while(0)

  799. #endif /* JPEG */

  800. 

  801. #define __HAL_RCC_FMC_CLK_ENABLE()   do { \

  802.                                         __IO uint32_t tmpreg; \

  803.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\

  804.                                         /* Delay after an RCC peripheral clock enabling */ \

  805.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\

  806.                                         UNUSED(tmpreg); \

  807.                                        } while(0)

  808. 

  809. #if defined(QUADSPI)

  810. #define __HAL_RCC_QSPI_CLK_ENABLE()   do { \

  811.                                         __IO uint32_t tmpreg; \

  812.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

  813.                                         /* Delay after an RCC peripheral clock enabling */ \

  814.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

  815.                                         UNUSED(tmpreg); \

  816.                                        } while(0)

  817. #endif /* QUADSPI */

  818. #if defined(OCTOSPI1)

  819. #define __HAL_RCC_OSPI1_CLK_ENABLE()   do { \

  820.                                         __IO uint32_t tmpreg; \

  821.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\

  822.                                         /* Delay after an RCC peripheral clock enabling */ \

  823.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\

  824.                                         UNUSED(tmpreg); \

  825.                                        } while(0)

  826. #endif /* OCTOSPI1 */

  827. #if defined(OCTOSPI2)

  828. #define __HAL_RCC_OSPI2_CLK_ENABLE()   do { \

  829.                                         __IO uint32_t tmpreg; \

  830.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\

  831.                                         /* Delay after an RCC peripheral clock enabling */ \

  832.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\

  833.                                         UNUSED(tmpreg); \

  834.                                        } while(0)

  835. #endif /* OCTOSPI2 */

  836. #if defined(OCTOSPIM)

  837. #define __HAL_RCC_OCTOSPIM_CLK_ENABLE()   do { \

  838.                                         __IO uint32_t tmpreg; \

  839.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\

  840.                                         /* Delay after an RCC peripheral clock enabling */ \

  841.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\

  842.                                         UNUSED(tmpreg); \

  843.                                        } while(0)

  844. #endif /* OCTOSPIM */

  845. #if defined(OTFDEC1)

  846. #define __HAL_RCC_OTFDEC1_CLK_ENABLE()   do { \

  847.                                         __IO uint32_t tmpreg; \

  848.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\

  849.                                         /* Delay after an RCC peripheral clock enabling */ \

  850.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\

  851.                                         UNUSED(tmpreg); \

  852.                                        } while(0)

  853. #endif /* OTFDEC1 */

  854. #if defined(OTFDEC2)

  855. #define __HAL_RCC_OTFDEC2_CLK_ENABLE()   do { \

  856.                                         __IO uint32_t tmpreg; \

  857.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\

  858.                                         /* Delay after an RCC peripheral clock enabling */ \

  859.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\

  860.                                         UNUSED(tmpreg); \

  861.                                        } while(0)

  862. #endif /* OTFDEC2 */

  863. #if defined(GFXMMU)

  864. #define __HAL_RCC_GFXMMU_CLK_ENABLE()   do { \

  865.                                         __IO uint32_t tmpreg; \

  866.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\

  867.                                         /* Delay after an RCC peripheral clock enabling */ \

  868.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\

  869.                                         UNUSED(tmpreg); \

  870.                                        } while(0)

  871. #endif /* GFXMMU */

  872. #define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \

  873.                                         __IO uint32_t tmpreg; \

  874.                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

  875.                                         /* Delay after an RCC peripheral clock enabling */ \

  876.                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

  877.                                         UNUSED(tmpreg); \

  878.                                        } while(0)

  879. 

  880. 

  881. #define __HAL_RCC_MDMA_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

  882. #define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

  883. #if defined(JPEG)

  884. #define __HAL_RCC_JPGDECEN_CLK_DISABLE()        (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))

  885. #endif /* JPEG */

  886. #define __HAL_RCC_FMC_CLK_DISABLE()             (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

  887. 

  888. #if defined(QUADSPI)

  889. #define __HAL_RCC_QSPI_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))

  890. #endif /* QUADSPI */

  891. #if defined(OCTOSPI1)

  892. #define __HAL_RCC_OSPI1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))

  893. #endif /* OCTOSPII */

  894. #if defined(OCTOSPI2)

  895. #define __HAL_RCC_OSPI2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))

  896. #endif /* OCTOSPI2 */

  897. #define __HAL_RCC_SDMMC1_CLK_DISABLE()          (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

  898. #if defined(OCTOSPIM)

  899. #define __HAL_RCC_OCTOSPIM_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))

  900. #endif /* OCTOSPIM */

  901. #if defined(OTFDEC1)

  902. #define __HAL_RCC_OTFDEC1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))

  903. #endif /* OTOFDEC1 */

  904. #if defined(OTFDEC2)

  905. #define __HAL_RCC_OTFDEC2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))

  906. #endif /* OTOFDEC2 */

  907. #if defined(GFXMMU)

  908. #define __HAL_RCC_GFXMMU_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))

  909. #endif /* GFXMMU */

  910. 

  911. /** @brief  Get the enable or disable status of the AHB3 peripheral clock

  912.   * @note   After reset, the peripheral clock (used for registers read/write access)

  913.   *         is disabled and the application software has to enable this clock before

  914.   *         using it.

  915.   */

  916. 

  917. #define __HAL_RCC_MDMA_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   != 0U)

  918. #define __HAL_RCC_DMA2D_IS_CLK_ENABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  != 0U)

  919. #if defined(JPEG)

  920. #define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)

  921. #endif /* JPEG */

  922. #define __HAL_RCC_FMC_IS_CLK_ENABLED()           ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    != 0U)

  923. #if defined (QUADSPI)

  924. #define __HAL_RCC_QSPI_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   != 0U)

  925. #endif /* QUADSPI */

  926. #if defined(OCTOSPI1)

  927. #define __HAL_RCC_OSPI1_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN)   != 0U)

  928. #endif /* OCTOSPII */

  929. #if defined(OCTOSPI2)

  930. #define __HAL_RCC_OSPI2_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN)   != 0U)

  931. #endif /* OCTOSPI2 */

  932. #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)

  933. #if defined(OCTOSPIM)

  934. #define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)

  935. #endif /* OCTOSPIM */

  936. #if defined(OTFDEC1)

  937. #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)

  938. #endif /* OTOFDEC1 */

  939. #if defined(OTFDEC2)

  940. #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)

  941. #endif /* OTOFDEC2 */

  942. #if defined(GFXMMU)

  943. #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)

  944. #endif /* GFXMMU */

  945. 

  946. #define __HAL_RCC_MDMA_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   == 0U)

  947. #define __HAL_RCC_DMA2D_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  == 0U)

  948. #if defined(JPEG)

  949. #define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)

  950. #endif /* JPEG */

  951. #define __HAL_RCC_FMC_IS_CLK_DISABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    == 0U)

  952. #if defined (QUADSPI)

  953. #define __HAL_RCC_QSPI_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   == 0U)

  954. #endif /* QUADSPI */

  955. #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)

  956. #if defined(OCTOSPI1)

  957. #define __HAL_RCC_OSPI1_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)

  958. #endif

  959. #if defined(OCTOSPI2)

  960. #define __HAL_RCC_OSPI2_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)

  961. #endif

  962. #if defined(OCTOSPIM)

  963. #define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)

  964. #endif

  965. #if defined(OTFDEC1)

  966. #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)

  967. #endif

  968. #if defined(OTFDEC2)

  969. #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)

  970. #endif

  971. #if defined(GFXMMU)

  972. #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)

  973. #endif

  974. /** @brief  Enable or disable the AHB1 peripheral clock.

  975.   * @note   After reset, the peripheral clock (used for registers read/write access)

  976.   *         is disabled and the application software has to enable this clock before

  977.   *         using it.

  978.   */

  979. 

  980. #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \

  981.                                         __IO uint32_t tmpreg; \

  982.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

  983.                                         /* Delay after an RCC peripheral clock enabling */ \

  984.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

  985.                                         UNUSED(tmpreg); \

  986.                                        } while(0)

  987. 

  988. #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \

  989.                                         __IO uint32_t tmpreg; \

  990.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

  991.                                         /* Delay after an RCC peripheral clock enabling */ \

  992.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

  993.                                         UNUSED(tmpreg); \

  994.                                        } while(0)

  995. 

  996. #define __HAL_RCC_ADC12_CLK_ENABLE()   do { \

  997.                                         __IO uint32_t tmpreg; \

  998.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

  999.                                         /* Delay after an RCC peripheral clock enabling */ \

  1000.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

  1001.                                         UNUSED(tmpreg); \

  1002.                                        } while(0)

  1003. 

  1004. #if defined(DUAL_CORE)

  1005. #define __HAL_RCC_ART_CLK_ENABLE()   do { \

  1006.                                         __IO uint32_t tmpreg; \

  1007.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\

  1008.                                         /* Delay after an RCC peripheral clock enabling */ \

  1009.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\

  1010.                                         UNUSED(tmpreg); \

  1011.                                        } while(0)

  1012. #endif /*DUAL_CORE*/

  1013. 

  1014. #if defined(RCC_AHB1ENR_CRCEN)

  1015. #define __HAL_RCC_CRC_CLK_ENABLE()   do { \

  1016.                                         __IO uint32_t tmpreg; \

  1017.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\

  1018.                                         /* Delay after an RCC peripheral clock enabling */ \

  1019.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\

  1020.                                         UNUSED(tmpreg); \

  1021.                                        } while(0)

  1022. #endif

  1023. 

  1024. #if defined(ETH)

  1025. #define __HAL_RCC_ETH1MAC_CLK_ENABLE()   do { \

  1026.                                         __IO uint32_t tmpreg; \

  1027.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

  1028.                                         /* Delay after an RCC peripheral clock enabling */ \

  1029.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

  1030.                                         UNUSED(tmpreg); \

  1031.                                        } while(0)

  1032. 

  1033. #define __HAL_RCC_ETH1TX_CLK_ENABLE()   do { \

  1034.                                         __IO uint32_t tmpreg; \

  1035.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

  1036.                                         /* Delay after an RCC peripheral clock enabling */ \

  1037.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

  1038.                                         UNUSED(tmpreg); \

  1039.                                        } while(0)

  1040. 

  1041. #define __HAL_RCC_ETH1RX_CLK_ENABLE()   do { \

  1042.                                         __IO uint32_t tmpreg; \

  1043.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

  1044.                                         /* Delay after an RCC peripheral clock enabling */ \

  1045.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

  1046.                                         UNUSED(tmpreg); \

  1047.                                        } while(0)

  1048. #endif

  1049. 

  1050. #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()   do { \

  1051.                                         __IO uint32_t tmpreg; \

  1052.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

  1053.                                         /* Delay after an RCC peripheral clock enabling */ \

  1054.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

  1055.                                         UNUSED(tmpreg); \

  1056.                                        } while(0)

  1057. 

  1058. #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \

  1059.                                         __IO uint32_t tmpreg; \

  1060.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

  1061.                                         /* Delay after an RCC peripheral clock enabling */ \

  1062.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

  1063.                                         UNUSED(tmpreg); \

  1064.                                        } while(0)

  1065. 

  1066. #if defined(USB2_OTG_FS)

  1067. #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()   do { \

  1068.                                         __IO uint32_t tmpreg; \

  1069.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

  1070.                                         /* Delay after an RCC peripheral clock enabling */ \

  1071.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

  1072.                                         UNUSED(tmpreg); \

  1073.                                        } while(0)

  1074. 

  1075. #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \

  1076.                                         __IO uint32_t tmpreg; \

  1077.                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

  1078.                                         /* Delay after an RCC peripheral clock enabling */ \

  1079.                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

  1080.                                         UNUSED(tmpreg); \

  1081.                                        } while(0)

  1082. #endif

  1083. 

  1084. #define __HAL_RCC_DMA1_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

  1085. #define __HAL_RCC_DMA2_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

  1086. #define __HAL_RCC_ADC12_CLK_DISABLE()            (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

  1087. #if defined(DUAL_CORE)

  1088. #define __HAL_RCC_ART_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))

  1089. #endif /*DUAL_CORE*/

  1090. #if defined(RCC_AHB1ENR_CRCEN)

  1091. #define __HAL_RCC_CRC_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))

  1092. #endif

  1093. #if defined(ETH)

  1094. #define __HAL_RCC_ETH1MAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))

  1095. #define __HAL_RCC_ETH1TX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))

  1096. #define __HAL_RCC_ETH1RX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))

  1097. #endif

  1098. #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

  1099. #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

  1100. #if defined(USB2_OTG_FS)

  1101. #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))

  1102. #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))

  1103. #endif /* USB2_OTG_FS */

  1104. 

  1105. /** @brief  Get the enable or disable status of the AHB1 peripheral clock

  1106.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1107.   *         is disabled and the application software has to enable this clock before

  1108.   *         using it.

  1109.   */

  1110. 

  1111. #define __HAL_RCC_DMA1_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          != 0U)

  1112. #define __HAL_RCC_DMA2_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          != 0U)

  1113. #define __HAL_RCC_ADC12_IS_CLK_ENABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         != 0U)

  1114. #if defined(DUAL_CORE)

  1115. #define __HAL_RCC_ART_IS_CLK_ENABLED()               ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           != 0U)

  1116. #endif /*DUAL_CORE*/

  1117. #if defined(RCC_AHB1ENR_CRCEN)

  1118. #define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)       != 0U)

  1119. #endif

  1120. #if defined(ETH)

  1121. #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       != 0U)

  1122. #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        != 0U)

  1123. #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        != 0U)

  1124. #endif

  1125. #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     != 0U)

  1126. #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)

  1127. #if defined(USB2_OTG_FS)

  1128. #define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     != 0U)

  1129. #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)

  1130. #endif /* USB2_OTG_FS */

  1131. 

  1132. #define __HAL_RCC_DMA1_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          == 0U)

  1133. #define __HAL_RCC_DMA2_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          == 0U)

  1134. #define __HAL_RCC_ADC12_IS_CLK_DISABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         == 0U)

  1135. #if defined(DUAL_CORE)

  1136. #define __HAL_RCC_ART_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           == 0U)

  1137. #endif /*DUAL_CORE*/

  1138. #if defined(RCC_AHB1ENR_CRCEN)

  1139. #define __HAL_RCC_CRC_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)           == 0U)

  1140. #endif

  1141. #if defined(ETH)

  1142. #define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       == 0U)

  1143. #define __HAL_RCC_ETH1TX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        == 0U)

  1144. #define __HAL_RCC_ETH1RX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        == 0U)

  1145. #endif

  1146. #define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     == 0U)

  1147. #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)

  1148. #if defined(USB2_OTG_FS)

  1149. #define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     == 0U)

  1150. #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)

  1151. #endif /* USB2_OTG_FS */

  1152. 

  1153. /** @brief  Enable or disable the AHB2 peripheral clock.

  1154.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1155.   *         is disabled and the application software has to enable this clock before

  1156.   *         using it.

  1157.   */

  1158. 

  1159. #if defined(DCMI) && defined(PSSI)

  1160. #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE()   do { \

  1161.                                         __IO uint32_t tmpreg; \

  1162.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\

  1163.                                         /* Delay after an RCC peripheral clock enabling */ \

  1164.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\

  1165.                                         UNUSED(tmpreg); \

  1166.                                        } while(0)

  1167. 

  1168. #define __HAL_RCC_DCMI_CLK_ENABLE()  __HAL_RCC_DCMI_PSSI_CLK_ENABLE()  /* for API backward compatibility*/

  1169. #else

  1170. #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \

  1171.                                         __IO uint32_t tmpreg; \

  1172.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

  1173.                                         /* Delay after an RCC peripheral clock enabling */ \

  1174.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

  1175.                                         UNUSED(tmpreg); \

  1176.                                        } while(0)

  1177. #endif /* DCMI && PSSI */

  1178. 

  1179. #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \

  1180.                                         __IO uint32_t tmpreg; \

  1181.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

  1182.                                         /* Delay after an RCC peripheral clock enabling */ \

  1183.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

  1184.                                         UNUSED(tmpreg); \

  1185.                                        } while(0)

  1186. 

  1187. #define __HAL_RCC_HASH_CLK_ENABLE()   do { \

  1188.                                         __IO uint32_t tmpreg; \

  1189.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\

  1190.                                         /* Delay after an RCC peripheral clock enabling */ \

  1191.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\

  1192.                                         UNUSED(tmpreg); \

  1193.                                        } while(0)

  1194. 

  1195. #define __HAL_RCC_RNG_CLK_ENABLE()   do { \

  1196.                                         __IO uint32_t tmpreg; \

  1197.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\

  1198.                                         /* Delay after an RCC peripheral clock enabling */ \

  1199.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\

  1200.                                         UNUSED(tmpreg); \

  1201.                                        } while(0)

  1202. 

  1203. #define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \

  1204.                                         __IO uint32_t tmpreg; \

  1205.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

  1206.                                         /* Delay after an RCC peripheral clock enabling */ \

  1207.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

  1208.                                         UNUSED(tmpreg); \

  1209.                                        } while(0)

  1210. 

  1211. #if defined(RCC_AHB2ENR_D2SRAM1EN)

  1212. #define __HAL_RCC_D2SRAM1_CLK_ENABLE()   do { \

  1213.                                         __IO uint32_t tmpreg; \

  1214.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

  1215.                                         /* Delay after an RCC peripheral clock enabling */ \

  1216.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

  1217.                                         UNUSED(tmpreg); \

  1218.                                        } while(0)

  1219. #else

  1220. #define __HAL_RCC_AHBSRAM1_CLK_ENABLE()   do { \

  1221.                                         __IO uint32_t tmpreg; \

  1222.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\

  1223.                                         /* Delay after an RCC peripheral clock enabling */ \

  1224.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\

  1225.                                         UNUSED(tmpreg); \

  1226.                                        } while(0)

  1227. #endif /* RCC_AHB2ENR_D2SRAM1EN */

  1228. 

  1229. #if defined(RCC_AHB2ENR_D2SRAM2EN)

  1230. #define __HAL_RCC_D2SRAM2_CLK_ENABLE()   do { \

  1231.                                         __IO uint32_t tmpreg; \

  1232.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

  1233.                                         /* Delay after an RCC peripheral clock enabling */ \

  1234.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

  1235.                                         UNUSED(tmpreg); \

  1236.                                        } while(0)

  1237. #else

  1238. #define __HAL_RCC_AHBSRAM2_CLK_ENABLE()   do { \

  1239.                                         __IO uint32_t tmpreg; \

  1240.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\

  1241.                                         /* Delay after an RCC peripheral clock enabling */ \

  1242.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\

  1243.                                         UNUSED(tmpreg); \

  1244.                                        } while(0)

  1245. #endif /* RCC_AHB2ENR_D2SRAM2EN */

  1246. 

  1247. #if defined(RCC_AHB2ENR_D2SRAM3EN)

  1248. #define __HAL_RCC_D2SRAM3_CLK_ENABLE()   do { \

  1249.                                         __IO uint32_t tmpreg; \

  1250.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

  1251.                                         /* Delay after an RCC peripheral clock enabling */ \

  1252.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

  1253.                                         UNUSED(tmpreg); \

  1254.                                        } while(0)

  1255. #endif

  1256. 

  1257. #if defined(RCC_AHB2ENR_HSEMEN)

  1258. #define __HAL_RCC_HSEM_CLK_ENABLE()   do { \

  1259.                                         __IO uint32_t tmpreg; \

  1260.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\

  1261.                                         /* Delay after an RCC peripheral clock enabling */ \

  1262.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\

  1263.                                         UNUSED(tmpreg); \

  1264.                                        } while(0)

  1265. #endif /* RCC_AHB2ENR_HSEMEN */

  1266. 

  1267. #if defined(BDMA1)

  1268. #define __HAL_RCC_BDMA1_CLK_ENABLE()   do { \

  1269.                                         __IO uint32_t tmpreg; \

  1270.                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\

  1271.                                         /* Delay after an RCC peripheral clock enabling */ \

  1272.                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\

  1273.                                         UNUSED(tmpreg); \

  1274.                                        } while(0)

  1275. #endif /* BDMA1 */

  1276. 

  1277. #if defined(DCMI) && defined(PSSI)

  1278. #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))

  1279. #define __HAL_RCC_DCMI_CLK_DISABLE()              __HAL_RCC_DCMI_PSSI_CLK_DISABLE()  /* for API backward compatibility*/

  1280. #else

  1281. #define __HAL_RCC_DCMI_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

  1282. #endif /* DCMI && PSSI */

  1283. #define __HAL_RCC_CRYP_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))

  1284. #define __HAL_RCC_HASH_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))

  1285. #define __HAL_RCC_RNG_CLK_DISABLE()              (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

  1286. #define __HAL_RCC_SDMMC2_CLK_DISABLE()           (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

  1287. #if defined(RCC_AHB2ENR_D2SRAM1EN)

  1288. #define __HAL_RCC_D2SRAM1_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))

  1289. #else

  1290. #define __HAL_RCC_AHBSRAM1_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))

  1291. #endif /* RCC_AHB2ENR_D2SRAM1EN */

  1292. #if defined(RCC_AHB2ENR_D2SRAM2EN)

  1293. #define __HAL_RCC_D2SRAM2_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))

  1294. #else

  1295. #define __HAL_RCC_AHBSRAM2_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))

  1296. #endif /* RCC_AHB2ENR_D2SRAM2EN */

  1297. #if defined(RCC_AHB2ENR_D2SRAM3EN)

  1298. #define __HAL_RCC_D2SRAM3_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))

  1299. #endif

  1300. #if defined(RCC_AHB2ENR_HSEMEN)

  1301. #define __HAL_RCC_HSEM_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))

  1302. #endif

  1303. #if defined(BDMA1)

  1304. #define __HAL_RCC_BDMA1_CLK_DISABLE()            (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))

  1305. #endif

  1306. 

  1307. /** @brief  Get the enable or disable status of the AHB2 peripheral clock

  1308.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1309.   *         is disabled and the application software has to enable this clock before

  1310.   *         using it.

  1311.   */

  1312. 

  1313. #if defined(DCMI) && defined(PSSI)

  1314. #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    != 0U)

  1315. #define __HAL_RCC_DCMI_IS_CLK_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()  /* for API backward compatibility*/

  1316. #else

  1317. #define __HAL_RCC_DCMI_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    != 0U)

  1318. #endif /* DCMI && PSSI */

  1319. #define __HAL_RCC_CRYP_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    != 0U)

  1320. #define __HAL_RCC_HASH_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    != 0U)

  1321. #define __HAL_RCC_RNG_IS_CLK_ENABLED()               ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     != 0U)

  1322. #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  != 0U)

  1323. #if defined(RCC_AHB2ENR_D2SRAM1EN)

  1324. #define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)

  1325. #else

  1326. #define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)

  1327. #endif /* RCC_AHB2ENR_D2SRAM1EN */

  1328. #if defined(RCC_AHB2ENR_D2SRAM2EN)

  1329. #define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)

  1330. #else

  1331. #define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)

  1332. #endif /* RCC_AHB2ENR_D2SRAM2EN */

  1333. #if defined(RCC_AHB2ENR_D2SRAM3EN)

  1334. #define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)

  1335. #endif

  1336. #if defined(RCC_AHB2ENR_HSEMEN)

  1337. #define __HAL_RCC_HSEM_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    != 0U)

  1338. #endif

  1339. #if defined(BDMA1)

  1340. #define __HAL_RCC_BDMA1_IS_CLK_ENABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)  != 0U)

  1341. #endif

  1342. 

  1343. #if defined(DCMI) && defined(PSSI)

  1344. #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()        ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    == 0U)

  1345. #define __HAL_RCC_DCMI_IS_CLK_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()  /* for API backward compatibility*/

  1346. #else

  1347. #define __HAL_RCC_DCMI_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    == 0U)

  1348. #endif /* DCMI && PSSI */

  1349. #define __HAL_RCC_CRYP_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    == 0U)

  1350. #define __HAL_RCC_HASH_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    == 0U)

  1351. #define __HAL_RCC_RNG_IS_CLK_DISABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     == 0U)

  1352. #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  == 0U)

  1353. #if defined(RCC_AHB2ENR_D2SRAM1EN)

  1354. #define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)

  1355. #else

  1356. #define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)

  1357. #endif /* RCC_AHB2ENR_D2SRAM1EN */

  1358. #if defined(RCC_AHB2ENR_D2SRAM2EN)

  1359. #define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)

  1360. #else

  1361. #define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)

  1362. #endif /* RCC_AHB2ENR_D2SRAM2EN */

  1363. #if defined(RCC_AHB2ENR_D2SRAM3EN)

  1364. #define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)

  1365. #endif

  1366. #if defined(RCC_AHB2ENR_HSEMEN)

  1367. #define __HAL_RCC_HSEM_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    == 0U)

  1368. #endif

  1369. #if defined(BDMA1)

  1370. #define __HAL_RCC_BDMA1_IS_CLK_DISABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)   == 0U)

  1371. #endif

  1372. 

  1373. /** @brief  Enable or disable the AHB4 peripheral clock.

  1374.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1375.   *         is disabled and the application software has to enable this clock before

  1376.   *         using it.

  1377.   */

  1378. 

  1379. #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \

  1380.                                         __IO uint32_t tmpreg; \

  1381.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

  1382.                                         /* Delay after an RCC peripheral clock enabling */ \

  1383.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

  1384.                                         UNUSED(tmpreg); \

  1385.                                        } while(0)

  1386. 

  1387. #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \

  1388.                                         __IO uint32_t tmpreg; \

  1389.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

  1390.                                         /* Delay after an RCC peripheral clock enabling */ \

  1391.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

  1392.                                         UNUSED(tmpreg); \

  1393.                                        } while(0)

  1394. 

  1395. #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \

  1396.                                         __IO uint32_t tmpreg; \

  1397.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

  1398.                                         /* Delay after an RCC peripheral clock enabling */ \

  1399.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

  1400.                                         UNUSED(tmpreg); \

  1401.                                        } while(0)

  1402. 

  1403. #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \

  1404.                                         __IO uint32_t tmpreg; \

  1405.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

  1406.                                         /* Delay after an RCC peripheral clock enabling */ \

  1407.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

  1408.                                         UNUSED(tmpreg); \

  1409.                                        } while(0)

  1410. 

  1411. #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \

  1412.                                         __IO uint32_t tmpreg; \

  1413.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

  1414.                                         /* Delay after an RCC peripheral clock enabling */ \

  1415.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

  1416.                                         UNUSED(tmpreg); \

  1417.                                        } while(0)

  1418. 

  1419. #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \

  1420.                                         __IO uint32_t tmpreg; \

  1421.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

  1422.                                         /* Delay after an RCC peripheral clock enabling */ \

  1423.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

  1424.                                         UNUSED(tmpreg); \

  1425.                                        } while(0)

  1426. 

  1427. #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \

  1428.                                         __IO uint32_t tmpreg; \

  1429.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

  1430.                                         /* Delay after an RCC peripheral clock enabling */ \

  1431.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

  1432.                                         UNUSED(tmpreg); \

  1433.                                        } while(0)

  1434. 

  1435. #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \

  1436.                                         __IO uint32_t tmpreg; \

  1437.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

  1438.                                         /* Delay after an RCC peripheral clock enabling */ \

  1439.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

  1440.                                         UNUSED(tmpreg); \

  1441.                                        } while(0)

  1442. 

  1443. #define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \

  1444.                                         __IO uint32_t tmpreg; \

  1445.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

  1446.                                         /* Delay after an RCC peripheral clock enabling */ \

  1447.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

  1448.                                         UNUSED(tmpreg); \

  1449.                                        } while(0)

  1450. 

  1451. #define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \

  1452.                                         __IO uint32_t tmpreg; \

  1453.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

  1454.                                         /* Delay after an RCC peripheral clock enabling */ \

  1455.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

  1456.                                         UNUSED(tmpreg); \

  1457.                                        } while(0)

  1458. 

  1459. #define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \

  1460.                                         __IO uint32_t tmpreg; \

  1461.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

  1462.                                         /* Delay after an RCC peripheral clock enabling */ \

  1463.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

  1464.                                         UNUSED(tmpreg); \

  1465.                                        } while(0)

  1466. 

  1467. #if defined(RCC_AHB4ENR_CRCEN)

  1468. #define __HAL_RCC_CRC_CLK_ENABLE()   do { \

  1469.                                         __IO uint32_t tmpreg; \

  1470.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\

  1471.                                         /* Delay after an RCC peripheral clock enabling */ \

  1472.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\

  1473.                                         UNUSED(tmpreg); \

  1474.                                        } while(0)

  1475. #endif

  1476. 

  1477. #if defined(BDMA2)

  1478. #define __HAL_RCC_BDMA2_CLK_ENABLE()   do { \

  1479.                                         __IO uint32_t tmpreg; \

  1480.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\

  1481.                                         /* Delay after an RCC peripheral clock enabling */ \

  1482.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\

  1483.                                         UNUSED(tmpreg); \

  1484.                                        } while(0)

  1485. 

  1486. #define __HAL_RCC_BDMA_CLK_ENABLE()  __HAL_RCC_BDMA2_CLK_ENABLE()  /* for API backward compatibility*/

  1487. #else

  1488. #define __HAL_RCC_BDMA_CLK_ENABLE()   do { \

  1489.                                         __IO uint32_t tmpreg; \

  1490.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

  1491.                                         /* Delay after an RCC peripheral clock enabling */ \

  1492.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

  1493.                                         UNUSED(tmpreg); \

  1494.                                        } while(0)

  1495. #endif

  1496. 

  1497. #if defined(ADC3)

  1498. #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \

  1499.                                         __IO uint32_t tmpreg; \

  1500.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

  1501.                                         /* Delay after an RCC peripheral clock enabling */ \

  1502.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

  1503.                                         UNUSED(tmpreg); \

  1504.                                        } while(0)

  1505. #endif

  1506. 

  1507. #if defined(RCC_AHB4ENR_HSEMEN)

  1508. #define __HAL_RCC_HSEM_CLK_ENABLE()   do { \

  1509.                                         __IO uint32_t tmpreg; \

  1510.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

  1511.                                         /* Delay after an RCC peripheral clock enabling */ \

  1512.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

  1513.                                         UNUSED(tmpreg); \

  1514.                                        } while(0)

  1515. #endif

  1516. 

  1517. #if defined(RCC_AHB4ENR_SRDSRAMEN)

  1518. #define __HAL_RCC_SRDSRAM_CLK_ENABLE()   do { \

  1519.                                         __IO uint32_t tmpreg; \

  1520.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\

  1521.                                         /* Delay after an RCC peripheral clock enabling */ \

  1522.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\

  1523.                                         UNUSED(tmpreg); \

  1524.                                        } while(0)

  1525. #endif

  1526. 

  1527. #define __HAL_RCC_BKPRAM_CLK_ENABLE()   do { \

  1528.                                         __IO uint32_t tmpreg; \

  1529.                                         SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

  1530.                                         /* Delay after an RCC peripheral clock enabling */ \

  1531.                                         tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

  1532.                                         UNUSED(tmpreg); \

  1533.                                        } while(0)

  1534. 

  1535. 

  1536. #define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

  1537. #define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

  1538. #define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

  1539. #define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

  1540. #define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

  1541. #define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

  1542. #define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

  1543. #define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

  1544. #define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)

  1545. #define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

  1546. #define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

  1547. #if defined(RCC_AHB4ENR_CRCEN)

  1548. #define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)

  1549. #endif

  1550. #if defined(BDMA2)

  1551. #define __HAL_RCC_BDMA2_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)

  1552. #define __HAL_RCC_BDMA_CLK_DISABLE()            __HAL_RCC_BDMA2_CLK_DISABLE()  /* for API backward compatibility*/

  1553. #else

  1554. #define __HAL_RCC_BDMA_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

  1555. #endif

  1556. #if defined(ADC3)

  1557. #define __HAL_RCC_ADC3_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)

  1558. #endif

  1559. #if defined(RCC_AHB4ENR_HSEMEN)

  1560. #define __HAL_RCC_HSEM_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)

  1561. #endif

  1562. #if defined(RCC_AHB4ENR_SRDSRAMEN)

  1563. #define __HAL_RCC_SRDSRAM_CLK_DISABLE()         (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)

  1564. #endif

  1565. #define __HAL_RCC_BKPRAM_CLK_DISABLE()          (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

  1566. 

  1567. 

  1568. /** @brief  Get the enable or disable status of the AHB4 peripheral clock

  1569.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1570.   *         is disabled and the application software has to enable this clock before

  1571.   *         using it.

  1572.   */

  1573. 

  1574. #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  != 0U)

  1575. #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  != 0U)

  1576. #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  != 0U)

  1577. #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  != 0U)

  1578. #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  != 0U)

  1579. #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  != 0U)

  1580. #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  != 0U)

  1581. #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  != 0U)

  1582. #define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  != 0U)

  1583. #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  != 0U)

  1584. #define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  != 0U)

  1585. #if defined(RCC_AHB4ENR_CRCEN)

  1586. #define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    != 0U)

  1587. #endif

  1588. #if defined(BDMA2)

  1589. #define __HAL_RCC_BDMA2_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   != 0U)

  1590. #define __HAL_RCC_BDMA_IS_CLK_ENABLED()  __HAL_RCC_BDMA2_IS_CLK_ENABLED()            /* for API backward compatibility*/

  1591. #else

  1592. #define __HAL_RCC_BDMA_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   != 0U)

  1593. #endif

  1594. #if defined(ADC3)

  1595. #define __HAL_RCC_ADC3_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   != 0U)

  1596. #endif

  1597. #if defined(RCC_AHB4ENR_HSEMEN)

  1598. #define __HAL_RCC_HSEM_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   != 0U)

  1599. #endif

  1600. #if defined(RCC_AHB4ENR_SRDSRAMEN)

  1601. #define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)

  1602. #endif

  1603. #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)

  1604. 

  1605. #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  == 0U)

  1606. #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  == 0U)

  1607. #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  == 0U)

  1608. #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  == 0U)

  1609. #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  == 0U)

  1610. #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  == 0U)

  1611. #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  == 0U)

  1612. #define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  == 0U)

  1613. #define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  == 0U)

  1614. #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  == 0U)

  1615. #define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  == 0U)

  1616. 

  1617. #if defined(RCC_AHB4ENR_CRCEN)

  1618. #define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    == 0U)

  1619. #endif

  1620. #if defined(BDMA2)

  1621. #define __HAL_RCC_BDMA2_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   == 0U)

  1622. #define __HAL_RCC_BDMA_IS_CLK_DISABLED()  __HAL_RCC_BDMA2_IS_CLK_DISABLED()           /* for API backward compatibility*/

  1623. #else

  1624. #define __HAL_RCC_BDMA_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   == 0U)

  1625. #endif

  1626. #if defined(ADC3)

  1627. #define __HAL_RCC_ADC3_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   == 0U)

  1628. #endif

  1629. #if defined(RCC_AHB4ENR_HSEMEN)

  1630. #define __HAL_RCC_HSEM_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   == 0U)

  1631. #endif

  1632. #if defined(RCC_AHB4ENR_SRDSRAMEN)

  1633. #define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED()         ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN)   == 0U)

  1634. #endif

  1635. #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)

  1636. 

  1637. 

  1638. /** @brief  Enable or disable the APB3 peripheral clock.

  1639.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1640.   *         is disabled and the application software has to enable this clock before

  1641.   *         using it.

  1642.   */

  1643. 

  1644. #if defined(LTDC)

  1645. #define __HAL_RCC_LTDC_CLK_ENABLE()   do { \

  1646.                                         __IO uint32_t tmpreg; \

  1647.                                         SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\

  1648.                                         /* Delay after an RCC peripheral clock enabling */ \

  1649.                                         tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\

  1650.                                         UNUSED(tmpreg); \

  1651.                                        } while(0)

  1652. #endif /* LTDC */

  1653. 

  1654. #if defined(DSI)

  1655. #define __HAL_RCC_DSI_CLK_ENABLE()   do { \

  1656.                                         __IO uint32_t tmpreg; \

  1657.                                         SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\

  1658.                                         /* Delay after an RCC peripheral clock enabling */ \

  1659.                                         tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\

  1660.                                         UNUSED(tmpreg); \

  1661.                                        } while(0)

  1662. #endif /*DSI*/

  1663. 

  1664. #define __HAL_RCC_WWDG1_CLK_ENABLE()   do { \

  1665.                                         __IO uint32_t tmpreg; \

  1666.                                         SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\

  1667.                                         /* Delay after an RCC peripheral clock enabling */ \

  1668.                                         tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\

  1669.                                         UNUSED(tmpreg); \

  1670.                                        } while(0)

  1671. 

  1672. #if defined(LTDC)

  1673. #define __HAL_RCC_LTDC_CLK_DISABLE()           (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)

  1674. #endif /* LTDC */

  1675. #if defined(DSI)

  1676. #define __HAL_RCC_DSI_CLK_DISABLE()            (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)

  1677. #endif /*DSI*/

  1678. #define __HAL_RCC_WWDG1_CLK_DISABLE()          (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

  1679. 

  1680. /** @brief  Get the enable or disable status of the APB3 peripheral clock

  1681.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1682.   *         is disabled and the application software has to enable this clock before

  1683.   *         using it.

  1684.   */

  1685. 

  1686. #if defined(LTDC)

  1687. #define __HAL_RCC_LTDC_IS_CLK_ENABLED()            ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  != 0U)

  1688. #endif /* LTDC */

  1689. #if defined(DSI)

  1690. #define __HAL_RCC_DSI_IS_CLK_ENABLED()             ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   != 0U)

  1691. #endif /*DSI*/

  1692. #define __HAL_RCC_WWDG1_IS_CLK_ENABLED()           ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)

  1693. #if defined(LTDC)

  1694. #define __HAL_RCC_LTDC_IS_CLK_DISABLED()           ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  == 0U)

  1695. #endif /* LTDC */

  1696. #if defined(DSI)

  1697. #define __HAL_RCC_DSI_IS_CLK_DISABLED()            ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   == 0U)

  1698. #endif /*DSI*/

  1699. #define __HAL_RCC_WWDG1_IS_CLK_DISABLED()          ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)

  1700. 

  1701. 

  1702. /** @brief  Enable or disable the APB1 peripheral clock.

  1703.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1704.   *         is disabled and the application software has to enable this clock before

  1705.   *         using it.

  1706.   */

  1707. 

  1708. #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \

  1709.                                         __IO uint32_t tmpreg; \

  1710.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\

  1711.                                         /* Delay after an RCC peripheral clock enabling */ \

  1712.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\

  1713.                                         UNUSED(tmpreg); \

  1714.                                        } while(0)

  1715. 

  1716. #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \

  1717.                                         __IO uint32_t tmpreg; \

  1718.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\

  1719.                                         /* Delay after an RCC peripheral clock enabling */ \

  1720.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\

  1721.                                         UNUSED(tmpreg); \

  1722.                                        } while(0)

  1723. 

  1724. #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \

  1725.                                         __IO uint32_t tmpreg; \

  1726.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\

  1727.                                         /* Delay after an RCC peripheral clock enabling */ \

  1728.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\

  1729.                                         UNUSED(tmpreg); \

  1730.                                        } while(0)

  1731. 

  1732. #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \

  1733.                                         __IO uint32_t tmpreg; \

  1734.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\

  1735.                                         /* Delay after an RCC peripheral clock enabling */ \

  1736.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\

  1737.                                         UNUSED(tmpreg); \

  1738.                                        } while(0)

  1739. 

  1740. #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \

  1741.                                         __IO uint32_t tmpreg; \

  1742.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\

  1743.                                         /* Delay after an RCC peripheral clock enabling */ \

  1744.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\

  1745.                                         UNUSED(tmpreg); \

  1746.                                        } while(0)

  1747. 

  1748. #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \

  1749.                                         __IO uint32_t tmpreg; \

  1750.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\

  1751.                                         /* Delay after an RCC peripheral clock enabling */ \

  1752.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\

  1753.                                         UNUSED(tmpreg); \

  1754.                                        } while(0)

  1755. 

  1756. #define __HAL_RCC_TIM12_CLK_ENABLE()   do { \

  1757.                                         __IO uint32_t tmpreg; \

  1758.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\

  1759.                                         /* Delay after an RCC peripheral clock enabling */ \

  1760.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\

  1761.                                         UNUSED(tmpreg); \

  1762.                                        } while(0)

  1763. 

  1764. #define __HAL_RCC_TIM13_CLK_ENABLE()   do { \

  1765.                                         __IO uint32_t tmpreg; \

  1766.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\

  1767.                                         /* Delay after an RCC peripheral clock enabling */ \

  1768.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\

  1769.                                         UNUSED(tmpreg); \

  1770.                                        } while(0)

  1771. 

  1772. #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \

  1773.                                         __IO uint32_t tmpreg; \

  1774.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\

  1775.                                         /* Delay after an RCC peripheral clock enabling */ \

  1776.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\

  1777.                                         UNUSED(tmpreg); \

  1778.                                        } while(0)

  1779. 

  1780. #define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \

  1781.                                         __IO uint32_t tmpreg; \

  1782.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

  1783.                                         /* Delay after an RCC peripheral clock enabling */ \

  1784.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

  1785.                                         UNUSED(tmpreg); \

  1786.                                        } while(0)

  1787. 

  1788. #if defined(DUAL_CORE)

  1789. #define __HAL_RCC_WWDG2_CLK_ENABLE()   do { \

  1790.                                         __IO uint32_t tmpreg; \

  1791.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\

  1792.                                         /* Delay after an RCC peripheral clock enabling */ \

  1793.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\

  1794.                                         UNUSED(tmpreg); \

  1795.                                        } while(0)

  1796. #endif /*DUAL_CORE*/

  1797. 

  1798. #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \

  1799.                                         __IO uint32_t tmpreg; \

  1800.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\

  1801.                                         /* Delay after an RCC peripheral clock enabling */ \

  1802.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\

  1803.                                         UNUSED(tmpreg); \

  1804.                                        } while(0)

  1805. 

  1806. #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \

  1807.                                         __IO uint32_t tmpreg; \

  1808.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\

  1809.                                         /* Delay after an RCC peripheral clock enabling */ \

  1810.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\

  1811.                                         UNUSED(tmpreg); \

  1812.                                        } while(0)

  1813. 

  1814. #define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \

  1815.                                         __IO uint32_t tmpreg; \

  1816.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

  1817.                                         /* Delay after an RCC peripheral clock enabling */ \

  1818.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

  1819.                                         UNUSED(tmpreg); \

  1820.                                        } while(0)

  1821. 

  1822. #define __HAL_RCC_USART2_CLK_ENABLE()   do { \

  1823.                                         __IO uint32_t tmpreg; \

  1824.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\

  1825.                                         /* Delay after an RCC peripheral clock enabling */ \

  1826.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\

  1827.                                         UNUSED(tmpreg); \

  1828.                                        } while(0)

  1829. 

  1830. #define __HAL_RCC_USART3_CLK_ENABLE()   do { \

  1831.                                         __IO uint32_t tmpreg; \

  1832.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\

  1833.                                         /* Delay after an RCC peripheral clock enabling */ \

  1834.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\

  1835.                                         UNUSED(tmpreg); \

  1836.                                        } while(0)

  1837. 

  1838. #define __HAL_RCC_UART4_CLK_ENABLE()   do { \

  1839.                                         __IO uint32_t tmpreg; \

  1840.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\

  1841.                                         /* Delay after an RCC peripheral clock enabling */ \

  1842.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\

  1843.                                         UNUSED(tmpreg); \

  1844.                                        } while(0)

  1845. 

  1846. #define __HAL_RCC_UART5_CLK_ENABLE()   do { \

  1847.                                         __IO uint32_t tmpreg; \

  1848.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\

  1849.                                         /* Delay after an RCC peripheral clock enabling */ \

  1850.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\

  1851.                                         UNUSED(tmpreg); \

  1852.                                        } while(0)

  1853. 

  1854. #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \

  1855.                                         __IO uint32_t tmpreg; \

  1856.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\

  1857.                                         /* Delay after an RCC peripheral clock enabling */ \

  1858.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\

  1859.                                         UNUSED(tmpreg); \

  1860.                                        } while(0)

  1861. 

  1862. #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \

  1863.                                         __IO uint32_t tmpreg; \

  1864.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\

  1865.                                         /* Delay after an RCC peripheral clock enabling */ \

  1866.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\

  1867.                                         UNUSED(tmpreg); \

  1868.                                        } while(0)

  1869. 

  1870. #define __HAL_RCC_I2C3_CLK_ENABLE()   do { \

  1871.                                         __IO uint32_t tmpreg; \

  1872.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\

  1873.                                         /* Delay after an RCC peripheral clock enabling */ \

  1874.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\

  1875.                                         UNUSED(tmpreg); \

  1876.                                        } while(0)

  1877. 

  1878. #define __HAL_RCC_CEC_CLK_ENABLE()   do { \

  1879.                                         __IO uint32_t tmpreg; \

  1880.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\

  1881.                                         /* Delay after an RCC peripheral clock enabling */ \

  1882.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\

  1883.                                         UNUSED(tmpreg); \

  1884.                                        } while(0)

  1885. 

  1886. #define __HAL_RCC_DAC12_CLK_ENABLE()   do { \

  1887.                                         __IO uint32_t tmpreg; \

  1888.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\

  1889.                                         /* Delay after an RCC peripheral clock enabling */ \

  1890.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\

  1891.                                         UNUSED(tmpreg); \

  1892.                                        } while(0)

  1893. 

  1894. #define __HAL_RCC_UART7_CLK_ENABLE()   do { \

  1895.                                         __IO uint32_t tmpreg; \

  1896.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\

  1897.                                         /* Delay after an RCC peripheral clock enabling */ \

  1898.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\

  1899.                                         UNUSED(tmpreg); \

  1900.                                        } while(0)

  1901. 

  1902. #define __HAL_RCC_UART8_CLK_ENABLE()   do { \

  1903.                                         __IO uint32_t tmpreg; \

  1904.                                         SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\

  1905.                                         /* Delay after an RCC peripheral clock enabling */ \

  1906.                                         tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\

  1907.                                         UNUSED(tmpreg); \

  1908.                                        } while(0)

  1909. 

  1910. #define __HAL_RCC_CRS_CLK_ENABLE()   do { \

  1911.                                         __IO uint32_t tmpreg; \

  1912.                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\

  1913.                                         /* Delay after an RCC peripheral clock enabling */ \

  1914.                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\

  1915.                                         UNUSED(tmpreg); \

  1916.                                        } while(0)

  1917. 

  1918. #define __HAL_RCC_SWPMI1_CLK_ENABLE()   do { \

  1919.                                         __IO uint32_t tmpreg; \

  1920.                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\

  1921.                                         /* Delay after an RCC peripheral clock enabling */ \

  1922.                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\

  1923.                                         UNUSED(tmpreg); \

  1924.                                        } while(0)

  1925. 

  1926. #define __HAL_RCC_OPAMP_CLK_ENABLE()   do { \

  1927.                                         __IO uint32_t tmpreg; \

  1928.                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\

  1929.                                         /* Delay after an RCC peripheral clock enabling */ \

  1930.                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\

  1931.                                         UNUSED(tmpreg); \

  1932.                                        } while(0)

  1933. 

  1934. #define __HAL_RCC_MDIOS_CLK_ENABLE()   do { \

  1935.                                         __IO uint32_t tmpreg; \

  1936.                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\

  1937.                                         /* Delay after an RCC peripheral clock enabling */ \

  1938.                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\

  1939.                                         UNUSED(tmpreg); \

  1940.                                        } while(0)

  1941. 

  1942. #define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \

  1943.                                         __IO uint32_t tmpreg; \

  1944.                                         SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\

  1945.                                         /* Delay after an RCC peripheral clock enabling */ \

  1946.                                         tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\

  1947.                                         UNUSED(tmpreg); \

  1948.                                        } while(0)

  1949. 

  1950. 

  1951. #define __HAL_RCC_TIM2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

  1952. #define __HAL_RCC_TIM3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

  1953. #define __HAL_RCC_TIM4_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

  1954. #define __HAL_RCC_TIM5_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

  1955. #define __HAL_RCC_TIM6_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

  1956. #define __HAL_RCC_TIM7_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

  1957. #define __HAL_RCC_TIM12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

  1958. #define __HAL_RCC_TIM13_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

  1959. #define __HAL_RCC_TIM14_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

  1960. #define __HAL_RCC_LPTIM1_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

  1961. 

  1962. #if defined(DUAL_CORE)

  1963. #define __HAL_RCC_WWDG2_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)

  1964. #endif /*DUAL_CORE*/

  1965. 

  1966. #define __HAL_RCC_SPI2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

  1967. #define __HAL_RCC_SPI3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

  1968. #define __HAL_RCC_SPDIFRX_CLK_DISABLE()        (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

  1969. #define __HAL_RCC_USART2_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

  1970. #define __HAL_RCC_USART3_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

  1971. #define __HAL_RCC_UART4_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

  1972. #define __HAL_RCC_UART5_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

  1973. #define __HAL_RCC_I2C1_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

  1974. #define __HAL_RCC_I2C2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

  1975. #define __HAL_RCC_I2C3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

  1976. #define __HAL_RCC_CEC_CLK_DISABLE()            (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

  1977. #define __HAL_RCC_DAC12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

  1978. #define __HAL_RCC_UART7_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

  1979. #define __HAL_RCC_UART8_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

  1980. #define __HAL_RCC_CRS_CLK_DISABLE()            (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

  1981. #define __HAL_RCC_SWPMI1_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

  1982. #define __HAL_RCC_OPAMP_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

  1983. #define __HAL_RCC_MDIOS_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

  1984. #define __HAL_RCC_FDCAN_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

  1985. 

  1986. 

  1987. /** @brief  Get the enable or disable status of the APB1 peripheral clock

  1988.   * @note   After reset, the peripheral clock (used for registers read/write access)

  1989.   *         is disabled and the application software has to enable this clock before

  1990.   *         using it.

  1991.   */

  1992. 

  1993. #define __HAL_RCC_TIM2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    != 0U)

  1994. #define __HAL_RCC_TIM3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    != 0U)

  1995. #define __HAL_RCC_TIM4_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    != 0U)

  1996. #define __HAL_RCC_TIM5_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    != 0U)

  1997. #define __HAL_RCC_TIM6_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    != 0U)

  1998. #define __HAL_RCC_TIM7_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    != 0U)

  1999. #define __HAL_RCC_TIM12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   != 0U)

  2000. #define __HAL_RCC_TIM13_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   != 0U)

  2001. #define __HAL_RCC_TIM14_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   != 0U)

  2002. #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  != 0U)

  2003. #if defined(DUAL_CORE)

  2004. #define __HAL_RCC_WWDG2_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   != 0U)

  2005. #endif /*DUAL_CORE*/

  2006. #define __HAL_RCC_SPI2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    != 0U)

  2007. #define __HAL_RCC_SPI3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    != 0U)

  2008. #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED()         ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)

  2009. #define __HAL_RCC_USART2_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  != 0U)

  2010. #define __HAL_RCC_USART3_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  != 0U)

  2011. #define __HAL_RCC_UART4_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   != 0U)

  2012. #define __HAL_RCC_UART5_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   != 0U)

  2013. #define __HAL_RCC_I2C1_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    != 0U)

  2014. #define __HAL_RCC_I2C2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    != 0U)

  2015. #define __HAL_RCC_I2C3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    != 0U)

  2016. #define __HAL_RCC_CEC_IS_CLK_ENABLED()             ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     != 0U)

  2017. #define __HAL_RCC_DAC12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   != 0U)

  2018. #define __HAL_RCC_UART7_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   != 0U)

  2019. #define __HAL_RCC_UART8_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   != 0U)

  2020. #define __HAL_RCC_CRS_IS_CLK_ENABLED()             ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     != 0U)

  2021. #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()          ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   != 0U)

  2022. #define __HAL_RCC_OPAMP_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   != 0U)

  2023. #define __HAL_RCC_MDIOS_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   != 0U)

  2024. #define __HAL_RCC_FDCAN_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   != 0U)

  2025. 

  2026. #define __HAL_RCC_TIM2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    == 0U)

  2027. #define __HAL_RCC_TIM3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    == 0U)

  2028. #define __HAL_RCC_TIM4_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    == 0U)

  2029. #define __HAL_RCC_TIM5_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    == 0U)

  2030. #define __HAL_RCC_TIM6_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    == 0U)

  2031. #define __HAL_RCC_TIM7_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    == 0U)

  2032. #define __HAL_RCC_TIM12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   == 0U)

  2033. #define __HAL_RCC_TIM13_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   == 0U)

  2034. #define __HAL_RCC_TIM14_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   == 0U)

  2035. #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  == 0U)

  2036. #if defined(DUAL_CORE)

  2037. #define __HAL_RCC_WWDG2_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   == 0U)

  2038. #endif /*DUAL_CORE*/

  2039. #define __HAL_RCC_SPI2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    == 0U)

  2040. #define __HAL_RCC_SPI3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    == 0U)

  2041. #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()        ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)

  2042. #define __HAL_RCC_USART2_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  == 0U)

  2043. #define __HAL_RCC_USART3_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  == 0U)

  2044. #define __HAL_RCC_UART4_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   == 0U)

  2045. #define __HAL_RCC_UART5_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   == 0U)

  2046. #define __HAL_RCC_I2C1_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    == 0U)

  2047. #define __HAL_RCC_I2C2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    == 0U)

  2048. #define __HAL_RCC_I2C3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    == 0U)

  2049. #define __HAL_RCC_CEC_IS_CLK_DISABLED()            ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     == 0U)

  2050. #define __HAL_RCC_DAC12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   == 0U)

  2051. #define __HAL_RCC_UART7_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   == 0U)

  2052. #define __HAL_RCC_UART8_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   == 0U)

  2053. #define __HAL_RCC_CRS_IS_CLK_DISABLED()            ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     == 0U)

  2054. #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()         ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   == 0U)

  2055. #define __HAL_RCC_OPAMP_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   == 0U)

  2056. #define __HAL_RCC_MDIOS_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   == 0U)

  2057. #define __HAL_RCC_FDCAN_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   == 0U)

  2058. 

  2059. 

  2060. /** @brief  Enable or disable the APB2 peripheral clock.

  2061.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2062.   *         is disabled and the application software has to enable this clock before

  2063.   *         using it.

  2064.   */

  2065. 

  2066. #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \

  2067.                                         __IO uint32_t tmpreg; \

  2068.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\

  2069.                                         /* Delay after an RCC peripheral clock enabling */ \

  2070.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\

  2071.                                         UNUSED(tmpreg); \

  2072.                                        } while(0)

  2073. 

  2074. #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \

  2075.                                         __IO uint32_t tmpreg; \

  2076.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\

  2077.                                         /* Delay after an RCC peripheral clock enabling */ \

  2078.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\

  2079.                                         UNUSED(tmpreg); \

  2080.                                        } while(0)

  2081. 

  2082. #define __HAL_RCC_USART1_CLK_ENABLE()   do { \

  2083.                                         __IO uint32_t tmpreg; \

  2084.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\

  2085.                                         /* Delay after an RCC peripheral clock enabling */ \

  2086.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\

  2087.                                         UNUSED(tmpreg); \

  2088.                                        } while(0)

  2089. 

  2090. #define __HAL_RCC_USART6_CLK_ENABLE()   do { \

  2091.                                         __IO uint32_t tmpreg; \

  2092.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\

  2093.                                         /* Delay after an RCC peripheral clock enabling */ \

  2094.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\

  2095.                                         UNUSED(tmpreg); \

  2096.                                        } while(0)

  2097. 

  2098. #if defined(UART9)

  2099. #define __HAL_RCC_UART9_CLK_ENABLE()   do { \

  2100.                                         __IO uint32_t tmpreg; \

  2101.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\

  2102.                                         /* Delay after an RCC peripheral clock enabling */ \

  2103.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\

  2104.                                         UNUSED(tmpreg); \

  2105.                                        } while(0)

  2106. #endif /*UART9*/

  2107. 

  2108. #if defined(USART10)

  2109. #define __HAL_RCC_USART10_CLK_ENABLE()   do { \

  2110.                                         __IO uint32_t tmpreg; \

  2111.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\

  2112.                                         /* Delay after an RCC peripheral clock enabling */ \

  2113.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\

  2114.                                         UNUSED(tmpreg); \

  2115.                                        } while(0)

  2116. #endif /*USART10*/

  2117. 

  2118. #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \

  2119.                                         __IO uint32_t tmpreg; \

  2120.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\

  2121.                                         /* Delay after an RCC peripheral clock enabling */ \

  2122.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\

  2123.                                         UNUSED(tmpreg); \

  2124.                                        } while(0)

  2125. 

  2126. #define __HAL_RCC_SPI4_CLK_ENABLE()   do { \

  2127.                                         __IO uint32_t tmpreg; \

  2128.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\

  2129.                                         /* Delay after an RCC peripheral clock enabling */ \

  2130.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\

  2131.                                         UNUSED(tmpreg); \

  2132.                                        } while(0)

  2133. 

  2134. #define __HAL_RCC_TIM15_CLK_ENABLE()   do { \

  2135.                                         __IO uint32_t tmpreg; \

  2136.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\

  2137.                                         /* Delay after an RCC peripheral clock enabling */ \

  2138.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\

  2139.                                         UNUSED(tmpreg); \

  2140.                                        } while(0)

  2141. 

  2142. #define __HAL_RCC_TIM16_CLK_ENABLE()   do { \

  2143.                                         __IO uint32_t tmpreg; \

  2144.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\

  2145.                                         /* Delay after an RCC peripheral clock enabling */ \

  2146.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\

  2147.                                         UNUSED(tmpreg); \

  2148.                                        } while(0)

  2149. 

  2150. #define __HAL_RCC_TIM17_CLK_ENABLE()   do { \

  2151.                                         __IO uint32_t tmpreg; \

  2152.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\

  2153.                                         /* Delay after an RCC peripheral clock enabling */ \

  2154.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\

  2155.                                         UNUSED(tmpreg); \

  2156.                                        } while(0)

  2157. 

  2158. #define __HAL_RCC_SPI5_CLK_ENABLE()   do { \

  2159.                                         __IO uint32_t tmpreg; \

  2160.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\

  2161.                                         /* Delay after an RCC peripheral clock enabling */ \

  2162.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\

  2163.                                         UNUSED(tmpreg); \

  2164.                                        } while(0)

  2165. 

  2166. #define __HAL_RCC_SAI1_CLK_ENABLE()   do { \

  2167.                                         __IO uint32_t tmpreg; \

  2168.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\

  2169.                                         /* Delay after an RCC peripheral clock enabling */ \

  2170.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\

  2171.                                         UNUSED(tmpreg); \

  2172.                                        } while(0)

  2173. 

  2174. #define __HAL_RCC_SAI2_CLK_ENABLE()   do { \

  2175.                                         __IO uint32_t tmpreg; \

  2176.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\

  2177.                                         /* Delay after an RCC peripheral clock enabling */ \

  2178.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\

  2179.                                         UNUSED(tmpreg); \

  2180.                                        } while(0)

  2181. 

  2182. #if defined(SAI3)

  2183. #define __HAL_RCC_SAI3_CLK_ENABLE()   do { \

  2184.                                         __IO uint32_t tmpreg; \

  2185.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\

  2186.                                         /* Delay after an RCC peripheral clock enabling */ \

  2187.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\

  2188.                                         UNUSED(tmpreg); \

  2189.                                        } while(0)

  2190. #endif /*SAI3*/

  2191. 

  2192. #define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \

  2193.                                         __IO uint32_t tmpreg; \

  2194.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

  2195.                                         /* Delay after an RCC peripheral clock enabling */ \

  2196.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

  2197.                                         UNUSED(tmpreg); \

  2198.                                        } while(0)

  2199. 

  2200. #if defined(HRTIM1)

  2201. #define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \

  2202.                                         __IO uint32_t tmpreg; \

  2203.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\

  2204.                                         /* Delay after an RCC peripheral clock enabling */ \

  2205.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\

  2206.                                         UNUSED(tmpreg); \

  2207.                                        } while(0)

  2208. #endif /*HRTIM1*/

  2209. 

  2210. #define __HAL_RCC_TIM1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

  2211. #define __HAL_RCC_TIM8_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

  2212. #define __HAL_RCC_USART1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

  2213. #define __HAL_RCC_USART6_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

  2214. #if defined(UART9)

  2215. #define __HAL_RCC_UART9_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)

  2216. #endif /*UART9*/

  2217. #if defined(USART10)

  2218. #define __HAL_RCC_USART10_CLK_DISABLE()        (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)

  2219. #endif /*USART10*/

  2220. #define __HAL_RCC_SPI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

  2221. #define __HAL_RCC_SPI4_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

  2222. #define __HAL_RCC_TIM15_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

  2223. #define __HAL_RCC_TIM16_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

  2224. #define __HAL_RCC_TIM17_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

  2225. #define __HAL_RCC_SPI5_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

  2226. #define __HAL_RCC_SAI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

  2227. #define __HAL_RCC_SAI2_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)

  2228. #if defined(SAI3)

  2229. #define __HAL_RCC_SAI3_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)

  2230. #endif /*SAI3*/

  2231. #define __HAL_RCC_DFSDM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

  2232. #if defined(HRTIM1)

  2233. #define __HAL_RCC_HRTIM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)

  2234. #endif /*HRTIM*/

  2235. 

  2236. /** @brief  Get the enable or disable status of the APB2 peripheral clock

  2237.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2238.   *         is disabled and the application software has to enable this clock before

  2239.   *         using it.

  2240.   */

  2241. 

  2242. #define __HAL_RCC_TIM1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   != 0U)

  2243. #define __HAL_RCC_TIM8_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   != 0U)

  2244. #define __HAL_RCC_USART1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)

  2245. #define __HAL_RCC_USART6_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)

  2246. #if defined(UART9)

  2247. #define __HAL_RCC_UART9_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)

  2248. #endif /*UART9*/

  2249. #if defined(USART10)

  2250. #define __HAL_RCC_USART10_IS_CLK_ENABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)

  2251. #endif /*USART10*/

  2252. #define __HAL_RCC_SPI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   != 0U)

  2253. #define __HAL_RCC_SPI4_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   != 0U)

  2254. #define __HAL_RCC_TIM15_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  != 0U)

  2255. #define __HAL_RCC_TIM16_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  != 0U)

  2256. #define __HAL_RCC_TIM17_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  != 0U)

  2257. #define __HAL_RCC_SPI5_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   != 0U)

  2258. #define __HAL_RCC_SAI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   != 0U)

  2259. #define __HAL_RCC_SAI2_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   != 0U)

  2260. #if defined(SAI3)

  2261. #define __HAL_RCC_SAI3_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   != 0U)

  2262. #endif /* SAI3 */

  2263. #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)

  2264. #if defined(HRTIM1)

  2265. #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  != 0U)

  2266. #endif /*HRTIM1*/

  2267. 

  2268. #define __HAL_RCC_TIM1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   == 0U)

  2269. #define __HAL_RCC_TIM8_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   == 0U)

  2270. #define __HAL_RCC_USART1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)

  2271. #define __HAL_RCC_USART6_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)

  2272. #if defined(UART9)

  2273. #define __HAL_RCC_UART9_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)

  2274. #endif /*UART9*/

  2275. #if defined(USART10)

  2276. #define __HAL_RCC_USART10_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)

  2277. #endif /*USART10*/

  2278. #define __HAL_RCC_SPI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   == 0U)

  2279. #define __HAL_RCC_SPI4_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   == 0U)

  2280. #define __HAL_RCC_TIM15_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  == 0U)

  2281. #define __HAL_RCC_TIM16_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  == 0U)

  2282. #define __HAL_RCC_TIM17_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  == 0U)

  2283. #define __HAL_RCC_SPI5_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   == 0U)

  2284. #define __HAL_RCC_SAI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   == 0U)

  2285. #define __HAL_RCC_SAI2_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   == 0U)

  2286. #if defined(SAI3)

  2287. #define __HAL_RCC_SAI3_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   == 0U)

  2288. #endif /*SAI3*/

  2289. #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)

  2290. #if defined(HRTIM1)

  2291. #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  == 0U)

  2292. #endif /*HRTIM1*/

  2293. 

  2294. /** @brief  Enable or disable the APB4 peripheral clock.

  2295.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2296.   *         is disabled and the application software has to enable this clock before

  2297.   *         using it.

  2298.   */

  2299. 

  2300. #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \

  2301.                                         __IO uint32_t tmpreg; \

  2302.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

  2303.                                         /* Delay after an RCC peripheral clock enabling */ \

  2304.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

  2305.                                         UNUSED(tmpreg); \

  2306.                                        } while(0)

  2307. 

  2308. #define __HAL_RCC_LPUART1_CLK_ENABLE()   do { \

  2309.                                         __IO uint32_t tmpreg; \

  2310.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\

  2311.                                         /* Delay after an RCC peripheral clock enabling */ \

  2312.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\

  2313.                                         UNUSED(tmpreg); \

  2314.                                        } while(0)

  2315. 

  2316. #define __HAL_RCC_SPI6_CLK_ENABLE()   do { \

  2317.                                         __IO uint32_t tmpreg; \

  2318.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\

  2319.                                         /* Delay after an RCC peripheral clock enabling */ \

  2320.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\

  2321.                                         UNUSED(tmpreg); \

  2322.                                        } while(0)

  2323. 

  2324. #define __HAL_RCC_I2C4_CLK_ENABLE()   do { \

  2325.                                         __IO uint32_t tmpreg; \

  2326.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\

  2327.                                         /* Delay after an RCC peripheral clock enabling */ \

  2328.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\

  2329.                                         UNUSED(tmpreg); \

  2330.                                        } while(0)

  2331. 

  2332. #define __HAL_RCC_LPTIM2_CLK_ENABLE()   do { \

  2333.                                         __IO uint32_t tmpreg; \

  2334.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

  2335.                                         /* Delay after an RCC peripheral clock enabling */ \

  2336.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

  2337.                                         UNUSED(tmpreg); \

  2338.                                        } while(0)

  2339. 

  2340. #define __HAL_RCC_LPTIM3_CLK_ENABLE()   do { \

  2341.                                         __IO uint32_t tmpreg; \

  2342.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

  2343.                                         /* Delay after an RCC peripheral clock enabling */ \

  2344.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

  2345.                                         UNUSED(tmpreg); \

  2346.                                        } while(0)

  2347. 

  2348. #if defined(LPTIM4)

  2349. #define __HAL_RCC_LPTIM4_CLK_ENABLE()   do { \

  2350.                                         __IO uint32_t tmpreg; \

  2351.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

  2352.                                         /* Delay after an RCC peripheral clock enabling */ \

  2353.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

  2354.                                         UNUSED(tmpreg); \

  2355.                                        } while(0)

  2356. #endif /* LPTIM4 */

  2357. 

  2358. #if defined(LPTIM5)

  2359. #define __HAL_RCC_LPTIM5_CLK_ENABLE()   do { \

  2360.                                         __IO uint32_t tmpreg; \

  2361.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

  2362.                                         /* Delay after an RCC peripheral clock enabling */ \

  2363.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

  2364.                                         UNUSED(tmpreg); \

  2365.                                        } while(0)

  2366. #endif /* LPTIM5 */

  2367. 

  2368. #if defined(DAC2)

  2369. #define __HAL_RCC_DAC2_CLK_ENABLE()   do { \

  2370.                                         __IO uint32_t tmpreg; \

  2371.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\

  2372.                                         /* Delay after an RCC peripheral clock enabling */ \

  2373.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\

  2374.                                         UNUSED(tmpreg); \

  2375.                                        } while(0)

  2376. #endif /*  DAC2 */

  2377. 

  2378. #define __HAL_RCC_COMP12_CLK_ENABLE()   do { \

  2379.                                         __IO uint32_t tmpreg; \

  2380.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\

  2381.                                         /* Delay after an RCC peripheral clock enabling */ \

  2382.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\

  2383.                                         UNUSED(tmpreg); \

  2384.                                        } while(0)

  2385. 

  2386. #define __HAL_RCC_VREF_CLK_ENABLE()   do { \

  2387.                                         __IO uint32_t tmpreg; \

  2388.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\

  2389.                                         /* Delay after an RCC peripheral clock enabling */ \

  2390.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\

  2391.                                         UNUSED(tmpreg); \

  2392.                                        } while(0)

  2393. 

  2394. #if defined(SAI4)

  2395. #define __HAL_RCC_SAI4_CLK_ENABLE()   do { \

  2396.                                         __IO uint32_t tmpreg; \

  2397.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\

  2398.                                         /* Delay after an RCC peripheral clock enabling */ \

  2399.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\

  2400.                                         UNUSED(tmpreg); \

  2401.                                        } while(0)

  2402. #endif /* SAI4 */

  2403. 

  2404. #define __HAL_RCC_RTC_CLK_ENABLE()   do { \

  2405.                                         __IO uint32_t tmpreg; \

  2406.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

  2407.                                         /* Delay after an RCC peripheral clock enabling */ \

  2408.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

  2409.                                         UNUSED(tmpreg); \

  2410.                                        } while(0)

  2411. 

  2412. #if defined(DTS)

  2413. #define __HAL_RCC_DTS_CLK_ENABLE()   do { \

  2414.                                         __IO uint32_t tmpreg; \

  2415.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\

  2416.                                         /* Delay after an RCC peripheral clock enabling */ \

  2417.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\

  2418.                                         UNUSED(tmpreg); \

  2419.                                        } while(0)

  2420. #endif /*DTS*/

  2421. 

  2422. #if defined(DFSDM2_BASE)

  2423. #define __HAL_RCC_DFSDM2_CLK_ENABLE()   do { \

  2424.                                         __IO uint32_t tmpreg; \

  2425.                                         SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\

  2426.                                         /* Delay after an RCC peripheral clock enabling */ \

  2427.                                         tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\

  2428.                                         UNUSED(tmpreg); \

  2429.                                        } while(0)

  2430. #endif /*DFSDM2*/

  2431. 

  2432. #define __HAL_RCC_SYSCFG_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

  2433. #define __HAL_RCC_LPUART1_CLK_DISABLE()          (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

  2434. #define __HAL_RCC_SPI6_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

  2435. #define __HAL_RCC_I2C4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

  2436. #define __HAL_RCC_LPTIM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

  2437. #define __HAL_RCC_LPTIM3_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

  2438. #if defined(LPTIM4)

  2439. #define __HAL_RCC_LPTIM4_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)

  2440. #endif /*LPTIM4*/

  2441. #if defined(LPTIM5)

  2442. #define __HAL_RCC_LPTIM5_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)

  2443. #endif /*LPTIM5*/

  2444. #if defined(DAC2)

  2445. #define __HAL_RCC_DAC2_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)

  2446. #endif /*DAC2*/

  2447. #define __HAL_RCC_COMP12_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

  2448. #define __HAL_RCC_VREF_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

  2449. #define __HAL_RCC_RTC_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

  2450. #if defined(SAI4)

  2451. #define __HAL_RCC_SAI4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)

  2452. #endif /*SAI4*/

  2453. #if defined(DTS)

  2454. #define __HAL_RCC_DTS_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)

  2455. #endif /*DTS*/

  2456. #if defined(DFSDM2_BASE)

  2457. #define __HAL_RCC_DFSDM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)

  2458. #endif /*DFSDM2*/

  2459. 

  2460. /** @brief  Get the enable or disable status of the APB4 peripheral clock

  2461.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2462.   *         is disabled and the application software has to enable this clock before

  2463.   *         using it.

  2464.   */

  2465. 

  2466. #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  != 0U)

  2467. #define __HAL_RCC_LPUART1_IS_CLK_ENABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)

  2468. #define __HAL_RCC_SPI6_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    != 0U)

  2469. #define __HAL_RCC_I2C4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    != 0U)

  2470. #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  != 0U)

  2471. #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  != 0U)

  2472. #if defined(LPTIM4)

  2473. #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  != 0U)

  2474. #endif /*LPTIM4*/

  2475. #if defined(LPTIM5)

  2476. #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  != 0U)

  2477. #endif /*LPTIM5*/

  2478. #if defined(DAC2)

  2479. #define __HAL_RCC_DAC2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  != 0U)

  2480. #endif /*DAC2*/

  2481. #define __HAL_RCC_COMP12_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  != 0U)

  2482. #define __HAL_RCC_VREF_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    != 0U)

  2483. #define __HAL_RCC_RTC_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  != 0U)

  2484. #if defined(SAI4)

  2485. #define __HAL_RCC_SAI4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    != 0U)

  2486. #endif /*SAI4*/

  2487. #if defined(DTS)

  2488. #define __HAL_RCC_DTS_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    != 0U)

  2489. #endif /*DTS*/

  2490. #if defined(DFSDM2_BASE)

  2491. #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    != 0U)

  2492. #endif /*DFSDM2*/

  2493. 

  2494. #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  == 0U)

  2495. #define __HAL_RCC_LPUART1_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)

  2496. #define __HAL_RCC_SPI6_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    == 0U)

  2497. #define __HAL_RCC_I2C4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    == 0U)

  2498. #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  == 0U)

  2499. #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  == 0U)

  2500. #if defined(LPTIM4)

  2501. #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  == 0U)

  2502. #endif /*LPTIM4*/

  2503. #if defined(LPTIM5)

  2504. #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  == 0U)

  2505. #endif /*LPTIM5*/

  2506. #if defined(DAC2)

  2507. #define __HAL_RCC_DAC2_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  == 0U)

  2508. #endif /*DAC2*/

  2509. #define __HAL_RCC_COMP12_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  == 0U)

  2510. #define __HAL_RCC_VREF_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    == 0U)

  2511. #define __HAL_RCC_RTC_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  == 0U)

  2512. #if defined(SAI4)

  2513. #define __HAL_RCC_SAI4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    == 0U)

  2514. #endif /*SAI4*/

  2515. #if defined(DTS)

  2516. #define __HAL_RCC_DTS_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    == 0U)

  2517. #endif /*DTS*/

  2518. #if defined(DFSDM2_BASE)

  2519. #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    == 0U)

  2520. #endif /*DFSDM2*/

  2521. 

  2522. #if defined(DUAL_CORE)

  2523. 

  2524. /* Exported macros for RCC_C1 -------------------------------------------------*/

  2525. 

  2526. /** @brief  Enable or disable the AHB3 peripheral clock.

  2527.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2528.   *         is disabled and the application software has to enable this clock before

  2529.   *         using it.

  2530.   */

  2531. 

  2532. #define __HAL_RCC_C1_MDMA_CLK_ENABLE()   do { \

  2533.                                         __IO uint32_t tmpreg; \

  2534.                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

  2535.                                         /* Delay after an RCC peripheral clock enabling */ \

  2536.                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

  2537.                                         UNUSED(tmpreg); \

  2538.                                        } while(0)

  2539. 

  2540. #define __HAL_RCC_C1_DMA2D_CLK_ENABLE()   do { \

  2541.                                         __IO uint32_t tmpreg; \

  2542.                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

  2543.                                         /* Delay after an RCC peripheral clock enabling */ \

  2544.                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

  2545.                                         UNUSED(tmpreg); \

  2546.                                        } while(0)

  2547. 

  2548. #define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE()   do { \

  2549.                                         __IO uint32_t tmpreg; \

  2550.                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

  2551.                                         /* Delay after an RCC peripheral clock enabling */ \

  2552.                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

  2553.                                         UNUSED(tmpreg); \

  2554.                                        } while(0)

  2555. 

  2556. 

  2557. #define __HAL_RCC_C1_FMC_CLK_ENABLE()   do { \

  2558.                                         __IO uint32_t tmpreg; \

  2559.                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\

  2560.                                         /* Delay after an RCC peripheral clock enabling */ \

  2561.                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\

  2562.                                         UNUSED(tmpreg); \

  2563.                                        } while(0)

  2564. 

  2565. #define __HAL_RCC_C1_QSPI_CLK_ENABLE()   do { \

  2566.                                         __IO uint32_t tmpreg; \

  2567.                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

  2568.                                         /* Delay after an RCC peripheral clock enabling */ \

  2569.                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

  2570.                                         UNUSED(tmpreg); \

  2571.                                        } while(0)

  2572. 

  2573. #define __HAL_RCC_C1_SDMMC1_CLK_ENABLE()   do { \

  2574.                                         __IO uint32_t tmpreg; \

  2575.                                         SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

  2576.                                         /* Delay after an RCC peripheral clock enabling */ \

  2577.                                         tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

  2578.                                         UNUSED(tmpreg); \

  2579.                                        } while(0)

  2580. 

  2581. 

  2582. 

  2583. 

  2584. #define __HAL_RCC_C1_MDMA_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

  2585. #define __HAL_RCC_C1_DMA2D_CLK_DISABLE()           (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

  2586. #define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE()        (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))

  2587. #define __HAL_RCC_C1_FMC_CLK_DISABLE()             (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

  2588. #define __HAL_RCC_C1_QSPI_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))

  2589. #define __HAL_RCC_C1_SDMMC1_CLK_DISABLE()          (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

  2590. 

  2591. 

  2592. 

  2593. 

  2594. /** @brief  Enable or disable the AHB1 peripheral clock.

  2595.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2596.   *         is disabled and the application software has to enable this clock before

  2597.   *         using it.

  2598.   */

  2599. 

  2600. #define __HAL_RCC_C1_DMA1_CLK_ENABLE()   do { \

  2601.                                         __IO uint32_t tmpreg; \

  2602.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

  2603.                                         /* Delay after an RCC peripheral clock enabling */ \

  2604.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

  2605.                                         UNUSED(tmpreg); \

  2606.                                        } while(0)

  2607. 

  2608. #define __HAL_RCC_C1_DMA2_CLK_ENABLE()   do { \

  2609.                                         __IO uint32_t tmpreg; \

  2610.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

  2611.                                         /* Delay after an RCC peripheral clock enabling */ \

  2612.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

  2613.                                         UNUSED(tmpreg); \

  2614.                                        } while(0)

  2615. 

  2616. #define __HAL_RCC_C1_ADC12_CLK_ENABLE()   do { \

  2617.                                         __IO uint32_t tmpreg; \

  2618.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

  2619.                                         /* Delay after an RCC peripheral clock enabling */ \

  2620.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

  2621.                                         UNUSED(tmpreg); \

  2622.                                        } while(0)

  2623. 

  2624. #define __HAL_RCC_C1_ART_CLK_ENABLE()   do { \

  2625.                                         __IO uint32_t tmpreg; \

  2626.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\

  2627.                                         /* Delay after an RCC peripheral clock enabling */ \

  2628.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\

  2629.                                         UNUSED(tmpreg); \

  2630.                                        } while(0)

  2631. 

  2632. #define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE()   do { \

  2633.                                         __IO uint32_t tmpreg; \

  2634.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

  2635.                                         /* Delay after an RCC peripheral clock enabling */ \

  2636.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

  2637.                                         UNUSED(tmpreg); \

  2638.                                        } while(0)

  2639. 

  2640. #define __HAL_RCC_C1_ETH1TX_CLK_ENABLE()   do { \

  2641.                                         __IO uint32_t tmpreg; \

  2642.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

  2643.                                         /* Delay after an RCC peripheral clock enabling */ \

  2644.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

  2645.                                         UNUSED(tmpreg); \

  2646.                                        } while(0)

  2647. 

  2648. #define __HAL_RCC_C1_ETH1RX_CLK_ENABLE()   do { \

  2649.                                         __IO uint32_t tmpreg; \

  2650.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

  2651.                                         /* Delay after an RCC peripheral clock enabling */ \

  2652.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

  2653.                                         UNUSED(tmpreg); \

  2654.                                        } while(0)

  2655. 

  2656. 

  2657. #define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE()   do { \

  2658.                                         __IO uint32_t tmpreg; \

  2659.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

  2660.                                         /* Delay after an RCC peripheral clock enabling */ \

  2661.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

  2662.                                         UNUSED(tmpreg); \

  2663.                                        } while(0)

  2664. 

  2665. #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \

  2666.                                         __IO uint32_t tmpreg; \

  2667.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

  2668.                                         /* Delay after an RCC peripheral clock enabling */ \

  2669.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

  2670.                                         UNUSED(tmpreg); \

  2671.                                        } while(0)

  2672. 

  2673. #define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE()   do { \

  2674.                                         __IO uint32_t tmpreg; \

  2675.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

  2676.                                         /* Delay after an RCC peripheral clock enabling */ \

  2677.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

  2678.                                         UNUSED(tmpreg); \

  2679.                                        } while(0)

  2680. 

  2681. #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \

  2682.                                         __IO uint32_t tmpreg; \

  2683.                                         SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

  2684.                                         /* Delay after an RCC peripheral clock enabling */ \

  2685.                                         tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

  2686.                                         UNUSED(tmpreg); \

  2687.                                        } while(0)

  2688. 

  2689. #define __HAL_RCC_C1_DMA1_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

  2690. #define __HAL_RCC_C1_DMA2_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

  2691. #define __HAL_RCC_C1_ADC12_CLK_DISABLE()            (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

  2692. #define __HAL_RCC_C1_ART_CLK_DISABLE()              (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))

  2693. #define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE()          (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))

  2694. #define __HAL_RCC_C1_ETH1TX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))

  2695. #define __HAL_RCC_C1_ETH1RX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))

  2696. #define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

  2697. #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

  2698. #define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))

  2699. #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))

  2700. 

  2701. /** @brief  Enable or disable the AHB2 peripheral clock.

  2702.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2703.   *         is disabled and the application software has to enable this clock before

  2704.   *         using it.

  2705.   */

  2706. 

  2707. #define __HAL_RCC_C1_DCMI_CLK_ENABLE()   do { \

  2708.                                         __IO uint32_t tmpreg; \

  2709.                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

  2710.                                         /* Delay after an RCC peripheral clock enabling */ \

  2711.                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

  2712.                                         UNUSED(tmpreg); \

  2713.                                        } while(0)

  2714. 

  2715. #define __HAL_RCC_C1_CRYP_CLK_ENABLE()   do { \

  2716.                                         __IO uint32_t tmpreg; \

  2717.                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

  2718.                                         /* Delay after an RCC peripheral clock enabling */ \

  2719.                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

  2720.                                         UNUSED(tmpreg); \

  2721.                                        } while(0)

  2722. 

  2723. #define __HAL_RCC_C1_HASH_CLK_ENABLE()   do { \

  2724.                                         __IO uint32_t tmpreg; \

  2725.                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\

  2726.                                         /* Delay after an RCC peripheral clock enabling */ \

  2727.                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\

  2728.                                         UNUSED(tmpreg); \

  2729.                                        } while(0)

  2730. 

  2731. #define __HAL_RCC_C1_RNG_CLK_ENABLE()   do { \

  2732.                                         __IO uint32_t tmpreg; \

  2733.                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\

  2734.                                         /* Delay after an RCC peripheral clock enabling */ \

  2735.                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\

  2736.                                         UNUSED(tmpreg); \

  2737.                                        } while(0)

  2738. 

  2739. #define __HAL_RCC_C1_SDMMC2_CLK_ENABLE()   do { \

  2740.                                         __IO uint32_t tmpreg; \

  2741.                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

  2742.                                         /* Delay after an RCC peripheral clock enabling */ \

  2743.                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

  2744.                                         UNUSED(tmpreg); \

  2745.                                        } while(0)

  2746. 

  2747. #define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE()   do { \

  2748.                                         __IO uint32_t tmpreg; \

  2749.                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

  2750.                                         /* Delay after an RCC peripheral clock enabling */ \

  2751.                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

  2752.                                         UNUSED(tmpreg); \

  2753.                                        } while(0)

  2754. 

  2755. #define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE()   do { \

  2756.                                         __IO uint32_t tmpreg; \

  2757.                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

  2758.                                         /* Delay after an RCC peripheral clock enabling */ \

  2759.                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

  2760.                                         UNUSED(tmpreg); \

  2761.                                        } while(0)

  2762. 

  2763. #define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE()   do { \

  2764.                                         __IO uint32_t tmpreg; \

  2765.                                         SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

  2766.                                         /* Delay after an RCC peripheral clock enabling */ \

  2767.                                         tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

  2768.                                         UNUSED(tmpreg); \

  2769.                                        } while(0)

  2770. 

  2771. #define __HAL_RCC_C1_DCMI_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

  2772. #define __HAL_RCC_C1_CRYP_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))

  2773. #define __HAL_RCC_C1_HASH_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))

  2774. #define __HAL_RCC_C1_RNG_CLK_DISABLE()              (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

  2775. #define __HAL_RCC_C1_SDMMC2_CLK_DISABLE()           (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

  2776. #define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))

  2777. #define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))

  2778. #define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))

  2779. 

  2780. /** @brief  Enable or disable the AHB4 peripheral clock.

  2781.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2782.   *         is disabled and the application software has to enable this clock before

  2783.   *         using it.

  2784.   */

  2785. 

  2786. #define __HAL_RCC_C1_GPIOA_CLK_ENABLE()   do { \

  2787.                                         __IO uint32_t tmpreg; \

  2788.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

  2789.                                         /* Delay after an RCC peripheral clock enabling */ \

  2790.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

  2791.                                         UNUSED(tmpreg); \

  2792.                                        } while(0)

  2793. 

  2794. #define __HAL_RCC_C1_GPIOB_CLK_ENABLE()   do { \

  2795.                                         __IO uint32_t tmpreg; \

  2796.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

  2797.                                         /* Delay after an RCC peripheral clock enabling */ \

  2798.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

  2799.                                         UNUSED(tmpreg); \

  2800.                                        } while(0)

  2801. 

  2802. #define __HAL_RCC_C1_GPIOC_CLK_ENABLE()   do { \

  2803.                                         __IO uint32_t tmpreg; \

  2804.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

  2805.                                         /* Delay after an RCC peripheral clock enabling */ \

  2806.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

  2807.                                         UNUSED(tmpreg); \

  2808.                                        } while(0)

  2809. 

  2810. #define __HAL_RCC_C1_GPIOD_CLK_ENABLE()   do { \

  2811.                                         __IO uint32_t tmpreg; \

  2812.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

  2813.                                         /* Delay after an RCC peripheral clock enabling */ \

  2814.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

  2815.                                         UNUSED(tmpreg); \

  2816.                                        } while(0)

  2817. 

  2818. #define __HAL_RCC_C1_GPIOE_CLK_ENABLE()   do { \

  2819.                                         __IO uint32_t tmpreg; \

  2820.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

  2821.                                         /* Delay after an RCC peripheral clock enabling */ \

  2822.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

  2823.                                         UNUSED(tmpreg); \

  2824.                                        } while(0)

  2825. 

  2826. #define __HAL_RCC_C1_GPIOF_CLK_ENABLE()   do { \

  2827.                                         __IO uint32_t tmpreg; \

  2828.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

  2829.                                         /* Delay after an RCC peripheral clock enabling */ \

  2830.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

  2831.                                         UNUSED(tmpreg); \

  2832.                                        } while(0)

  2833. 

  2834. #define __HAL_RCC_C1_GPIOG_CLK_ENABLE()   do { \

  2835.                                         __IO uint32_t tmpreg; \

  2836.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

  2837.                                         /* Delay after an RCC peripheral clock enabling */ \

  2838.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

  2839.                                         UNUSED(tmpreg); \

  2840.                                        } while(0)

  2841. 

  2842. #define __HAL_RCC_C1_GPIOH_CLK_ENABLE()   do { \

  2843.                                         __IO uint32_t tmpreg; \

  2844.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

  2845.                                         /* Delay after an RCC peripheral clock enabling */ \

  2846.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

  2847.                                         UNUSED(tmpreg); \

  2848.                                        } while(0)

  2849. 

  2850. #define __HAL_RCC_C1_GPIOI_CLK_ENABLE()   do { \

  2851.                                         __IO uint32_t tmpreg; \

  2852.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

  2853.                                         /* Delay after an RCC peripheral clock enabling */ \

  2854.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

  2855.                                         UNUSED(tmpreg); \

  2856.                                        } while(0)

  2857. 

  2858. #define __HAL_RCC_C1_GPIOJ_CLK_ENABLE()   do { \

  2859.                                         __IO uint32_t tmpreg; \

  2860.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

  2861.                                         /* Delay after an RCC peripheral clock enabling */ \

  2862.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

  2863.                                         UNUSED(tmpreg); \

  2864.                                        } while(0)

  2865. 

  2866. #define __HAL_RCC_C1_GPIOK_CLK_ENABLE()   do { \

  2867.                                         __IO uint32_t tmpreg; \

  2868.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

  2869.                                         /* Delay after an RCC peripheral clock enabling */ \

  2870.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

  2871.                                         UNUSED(tmpreg); \

  2872.                                        } while(0)

  2873. 

  2874. #define __HAL_RCC_C1_CRC_CLK_ENABLE()   do { \

  2875.                                         __IO uint32_t tmpreg; \

  2876.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\

  2877.                                         /* Delay after an RCC peripheral clock enabling */ \

  2878.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\

  2879.                                         UNUSED(tmpreg); \

  2880.                                        } while(0)

  2881. 

  2882. #define __HAL_RCC_C1_BDMA_CLK_ENABLE()   do { \

  2883.                                         __IO uint32_t tmpreg; \

  2884.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

  2885.                                         /* Delay after an RCC peripheral clock enabling */ \

  2886.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

  2887.                                         UNUSED(tmpreg); \

  2888.                                        } while(0)

  2889. 

  2890. #define __HAL_RCC_C1_ADC3_CLK_ENABLE()   do { \

  2891.                                         __IO uint32_t tmpreg; \

  2892.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

  2893.                                         /* Delay after an RCC peripheral clock enabling */ \

  2894.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

  2895.                                         UNUSED(tmpreg); \

  2896.                                        } while(0)

  2897. 

  2898. #define __HAL_RCC_C1_HSEM_CLK_ENABLE()   do { \

  2899.                                         __IO uint32_t tmpreg; \

  2900.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

  2901.                                         /* Delay after an RCC peripheral clock enabling */ \

  2902.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

  2903.                                         UNUSED(tmpreg); \

  2904.                                        } while(0)

  2905. 

  2906. #define __HAL_RCC_C1_BKPRAM_CLK_ENABLE()   do { \

  2907.                                         __IO uint32_t tmpreg; \

  2908.                                         SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

  2909.                                         /* Delay after an RCC peripheral clock enabling */ \

  2910.                                         tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

  2911.                                         UNUSED(tmpreg); \

  2912.                                        } while(0)

  2913. 

  2914. 

  2915. #define __HAL_RCC_C1_GPIOA_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

  2916. #define __HAL_RCC_C1_GPIOB_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

  2917. #define __HAL_RCC_C1_GPIOC_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

  2918. #define __HAL_RCC_C1_GPIOD_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

  2919. #define __HAL_RCC_C1_GPIOE_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

  2920. #define __HAL_RCC_C1_GPIOF_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

  2921. #define __HAL_RCC_C1_GPIOG_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

  2922. #define __HAL_RCC_C1_GPIOH_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

  2923. #define __HAL_RCC_C1_GPIOI_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)

  2924. #define __HAL_RCC_C1_GPIOJ_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

  2925. #define __HAL_RCC_C1_GPIOK_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

  2926. #define __HAL_RCC_C1_CRC_CLK_DISABLE()             (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)

  2927. #define __HAL_RCC_C1_BDMA_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

  2928. #define __HAL_RCC_C1_ADC3_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)

  2929. #define __HAL_RCC_C1_HSEM_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)

  2930. #define __HAL_RCC_C1_BKPRAM_CLK_DISABLE()          (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

  2931. 

  2932. 

  2933. /** @brief  Enable or disable the APB3 peripheral clock.

  2934.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2935.   *         is disabled and the application software has to enable this clock before

  2936.   *         using it.

  2937.   */

  2938. 

  2939. #define __HAL_RCC_C1_LTDC_CLK_ENABLE()   do { \

  2940.                                         __IO uint32_t tmpreg; \

  2941.                                         SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\

  2942.                                         /* Delay after an RCC peripheral clock enabling */ \

  2943.                                         tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\

  2944.                                         UNUSED(tmpreg); \

  2945.                                        } while(0)

  2946. 

  2947. #define __HAL_RCC_C1_DSI_CLK_ENABLE()   do { \

  2948.                                         __IO uint32_t tmpreg; \

  2949.                                         SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\

  2950.                                         /* Delay after an RCC peripheral clock enabling */ \

  2951.                                         tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\

  2952.                                         UNUSED(tmpreg); \

  2953.                                        } while(0)

  2954. 

  2955. #define __HAL_RCC_C1_WWDG1_CLK_ENABLE()   do { \

  2956.                                         __IO uint32_t tmpreg; \

  2957.                                         SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\

  2958.                                         /* Delay after an RCC peripheral clock enabling */ \

  2959.                                         tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\

  2960.                                         UNUSED(tmpreg); \

  2961.                                        } while(0)

  2962. 

  2963. #define __HAL_RCC_C1_LTDC_CLK_DISABLE()           (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)

  2964. #define __HAL_RCC_C1_DSI_CLK_DISABLE()            (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)

  2965. #define __HAL_RCC_C1_WWDG1_CLK_DISABLE()          (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

  2966. 

  2967. /** @brief  Enable or disable the APB1 peripheral clock.

  2968.   * @note   After reset, the peripheral clock (used for registers read/write access)

  2969.   *         is disabled and the application software has to enable this clock before

  2970.   *         using it.

  2971.   */

  2972. 

  2973. #define __HAL_RCC_C1_TIM2_CLK_ENABLE()   do { \

  2974.                                         __IO uint32_t tmpreg; \

  2975.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\

  2976.                                         /* Delay after an RCC peripheral clock enabling */ \

  2977.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\

  2978.                                         UNUSED(tmpreg); \

  2979.                                        } while(0)

  2980. 

  2981. #define __HAL_RCC_C1_TIM3_CLK_ENABLE()   do { \

  2982.                                         __IO uint32_t tmpreg; \

  2983.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\

  2984.                                         /* Delay after an RCC peripheral clock enabling */ \

  2985.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\

  2986.                                         UNUSED(tmpreg); \

  2987.                                        } while(0)

  2988. 

  2989. #define __HAL_RCC_C1_TIM4_CLK_ENABLE()   do { \

  2990.                                         __IO uint32_t tmpreg; \

  2991.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\

  2992.                                         /* Delay after an RCC peripheral clock enabling */ \

  2993.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\

  2994.                                         UNUSED(tmpreg); \

  2995.                                        } while(0)

  2996. 

  2997. #define __HAL_RCC_C1_TIM5_CLK_ENABLE()   do { \

  2998.                                         __IO uint32_t tmpreg; \

  2999.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\

  3000.                                         /* Delay after an RCC peripheral clock enabling */ \

  3001.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\

  3002.                                         UNUSED(tmpreg); \

  3003.                                        } while(0)

  3004. 

  3005. #define __HAL_RCC_C1_TIM6_CLK_ENABLE()   do { \

  3006.                                         __IO uint32_t tmpreg; \

  3007.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\

  3008.                                         /* Delay after an RCC peripheral clock enabling */ \

  3009.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\

  3010.                                         UNUSED(tmpreg); \

  3011.                                        } while(0)

  3012. 

  3013. #define __HAL_RCC_C1_TIM7_CLK_ENABLE()   do { \

  3014.                                         __IO uint32_t tmpreg; \

  3015.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\

  3016.                                         /* Delay after an RCC peripheral clock enabling */ \

  3017.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\

  3018.                                         UNUSED(tmpreg); \

  3019.                                        } while(0)

  3020. 

  3021. #define __HAL_RCC_C1_TIM12_CLK_ENABLE()   do { \

  3022.                                         __IO uint32_t tmpreg; \

  3023.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\

  3024.                                         /* Delay after an RCC peripheral clock enabling */ \

  3025.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\

  3026.                                         UNUSED(tmpreg); \

  3027.                                        } while(0)

  3028. 

  3029. #define __HAL_RCC_C1_TIM13_CLK_ENABLE()   do { \

  3030.                                         __IO uint32_t tmpreg; \

  3031.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\

  3032.                                         /* Delay after an RCC peripheral clock enabling */ \

  3033.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\

  3034.                                         UNUSED(tmpreg); \

  3035.                                        } while(0)

  3036. 

  3037. #define __HAL_RCC_C1_TIM14_CLK_ENABLE()   do { \

  3038.                                         __IO uint32_t tmpreg; \

  3039.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\

  3040.                                         /* Delay after an RCC peripheral clock enabling */ \

  3041.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\

  3042.                                         UNUSED(tmpreg); \

  3043.                                        } while(0)

  3044. 

  3045. #define __HAL_RCC_C1_LPTIM1_CLK_ENABLE()   do { \

  3046.                                         __IO uint32_t tmpreg; \

  3047.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

  3048.                                         /* Delay after an RCC peripheral clock enabling */ \

  3049.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

  3050.                                         UNUSED(tmpreg); \

  3051.                                        } while(0)

  3052. 

  3053. #define __HAL_RCC_C1_WWDG2_CLK_ENABLE()   do { \

  3054.                                         __IO uint32_t tmpreg; \

  3055.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\

  3056.                                         /* Delay after an RCC peripheral clock enabling */ \

  3057.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\

  3058.                                         UNUSED(tmpreg); \

  3059.                                        } while(0)

  3060. 

  3061. #define __HAL_RCC_C1_SPI2_CLK_ENABLE()   do { \

  3062.                                         __IO uint32_t tmpreg; \

  3063.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\

  3064.                                         /* Delay after an RCC peripheral clock enabling */ \

  3065.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\

  3066.                                         UNUSED(tmpreg); \

  3067.                                        } while(0)

  3068. 

  3069. #define __HAL_RCC_C1_SPI3_CLK_ENABLE()   do { \

  3070.                                         __IO uint32_t tmpreg; \

  3071.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\

  3072.                                         /* Delay after an RCC peripheral clock enabling */ \

  3073.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\

  3074.                                         UNUSED(tmpreg); \

  3075.                                        } while(0)

  3076. 

  3077. #define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE()   do { \

  3078.                                         __IO uint32_t tmpreg; \

  3079.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

  3080.                                         /* Delay after an RCC peripheral clock enabling */ \

  3081.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

  3082.                                         UNUSED(tmpreg); \

  3083.                                        } while(0)

  3084. 

  3085. #define __HAL_RCC_C1_USART2_CLK_ENABLE()   do { \

  3086.                                         __IO uint32_t tmpreg; \

  3087.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\

  3088.                                         /* Delay after an RCC peripheral clock enabling */ \

  3089.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\

  3090.                                         UNUSED(tmpreg); \

  3091.                                        } while(0)

  3092. 

  3093. #define __HAL_RCC_C1_USART3_CLK_ENABLE()   do { \

  3094.                                         __IO uint32_t tmpreg; \

  3095.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\

  3096.                                         /* Delay after an RCC peripheral clock enabling */ \

  3097.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\

  3098.                                         UNUSED(tmpreg); \

  3099.                                        } while(0)

  3100. 

  3101. #define __HAL_RCC_C1_UART4_CLK_ENABLE()   do { \

  3102.                                         __IO uint32_t tmpreg; \

  3103.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\

  3104.                                         /* Delay after an RCC peripheral clock enabling */ \

  3105.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\

  3106.                                         UNUSED(tmpreg); \

  3107.                                        } while(0)

  3108. 

  3109. #define __HAL_RCC_C1_UART5_CLK_ENABLE()   do { \

  3110.                                         __IO uint32_t tmpreg; \

  3111.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\

  3112.                                         /* Delay after an RCC peripheral clock enabling */ \

  3113.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\

  3114.                                         UNUSED(tmpreg); \

  3115.                                        } while(0)

  3116. 

  3117. #define __HAL_RCC_C1_I2C1_CLK_ENABLE()   do { \

  3118.                                         __IO uint32_t tmpreg; \

  3119.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\

  3120.                                         /* Delay after an RCC peripheral clock enabling */ \

  3121.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\

  3122.                                         UNUSED(tmpreg); \

  3123.                                        } while(0)

  3124. 

  3125. #define __HAL_RCC_C1_I2C2_CLK_ENABLE()   do { \

  3126.                                         __IO uint32_t tmpreg; \

  3127.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\

  3128.                                         /* Delay after an RCC peripheral clock enabling */ \

  3129.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\

  3130.                                         UNUSED(tmpreg); \

  3131.                                        } while(0)

  3132. 

  3133. #define __HAL_RCC_C1_I2C3_CLK_ENABLE()   do { \

  3134.                                         __IO uint32_t tmpreg; \

  3135.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\

  3136.                                         /* Delay after an RCC peripheral clock enabling */ \

  3137.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\

  3138.                                         UNUSED(tmpreg); \

  3139.                                        } while(0)

  3140. 

  3141. #define __HAL_RCC_C1_CEC_CLK_ENABLE()   do { \

  3142.                                         __IO uint32_t tmpreg; \

  3143.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\

  3144.                                         /* Delay after an RCC peripheral clock enabling */ \

  3145.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\

  3146.                                         UNUSED(tmpreg); \

  3147.                                        } while(0)

  3148. 

  3149. #define __HAL_RCC_C1_DAC12_CLK_ENABLE()   do { \

  3150.                                         __IO uint32_t tmpreg; \

  3151.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\

  3152.                                         /* Delay after an RCC peripheral clock enabling */ \

  3153.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\

  3154.                                         UNUSED(tmpreg); \

  3155.                                        } while(0)

  3156. 

  3157. #define __HAL_RCC_C1_UART7_CLK_ENABLE()   do { \

  3158.                                         __IO uint32_t tmpreg; \

  3159.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\

  3160.                                         /* Delay after an RCC peripheral clock enabling */ \

  3161.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\

  3162.                                         UNUSED(tmpreg); \

  3163.                                        } while(0)

  3164. 

  3165. #define __HAL_RCC_C1_UART8_CLK_ENABLE()   do { \

  3166.                                         __IO uint32_t tmpreg; \

  3167.                                         SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\

  3168.                                         /* Delay after an RCC peripheral clock enabling */ \

  3169.                                         tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\

  3170.                                         UNUSED(tmpreg); \

  3171.                                        } while(0)

  3172. 

  3173. #define __HAL_RCC_C1_CRS_CLK_ENABLE()   do { \

  3174.                                         __IO uint32_t tmpreg; \

  3175.                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\

  3176.                                         /* Delay after an RCC peripheral clock enabling */ \

  3177.                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\

  3178.                                         UNUSED(tmpreg); \

  3179.                                        } while(0)

  3180. 

  3181. #define __HAL_RCC_C1_SWPMI_CLK_ENABLE()   do { \

  3182.                                         __IO uint32_t tmpreg; \

  3183.                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\

  3184.                                         /* Delay after an RCC peripheral clock enabling */ \

  3185.                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\

  3186.                                         UNUSED(tmpreg); \

  3187.                                        } while(0)

  3188. 

  3189. #define __HAL_RCC_C1_OPAMP_CLK_ENABLE()   do { \

  3190.                                         __IO uint32_t tmpreg; \

  3191.                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\

  3192.                                         /* Delay after an RCC peripheral clock enabling */ \

  3193.                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\

  3194.                                         UNUSED(tmpreg); \

  3195.                                        } while(0)

  3196. 

  3197. #define __HAL_RCC_C1_MDIOS_CLK_ENABLE()   do { \

  3198.                                         __IO uint32_t tmpreg; \

  3199.                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\

  3200.                                         /* Delay after an RCC peripheral clock enabling */ \

  3201.                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\

  3202.                                         UNUSED(tmpreg); \

  3203.                                        } while(0)

  3204. 

  3205. #define __HAL_RCC_C1_FDCAN_CLK_ENABLE()   do { \

  3206.                                         __IO uint32_t tmpreg; \

  3207.                                         SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\

  3208.                                         /* Delay after an RCC peripheral clock enabling */ \

  3209.                                         tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\

  3210.                                         UNUSED(tmpreg); \

  3211.                                        } while(0)

  3212. 

  3213. 

  3214. #define __HAL_RCC_C1_TIM2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

  3215. #define __HAL_RCC_C1_TIM3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

  3216. #define __HAL_RCC_C1_TIM4_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

  3217. #define __HAL_RCC_C1_TIM5_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

  3218. #define __HAL_RCC_C1_TIM6_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

  3219. #define __HAL_RCC_C1_TIM7_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

  3220. #define __HAL_RCC_C1_TIM12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

  3221. #define __HAL_RCC_C1_TIM13_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

  3222. #define __HAL_RCC_C1_TIM14_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

  3223. #define __HAL_RCC_C1_LPTIM1_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

  3224. #define __HAL_RCC_C1_WWDG2_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)

  3225. #define __HAL_RCC_C1_SPI2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

  3226. #define __HAL_RCC_C1_SPI3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

  3227. #define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE()        (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

  3228. #define __HAL_RCC_C1_USART2_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

  3229. #define __HAL_RCC_C1_USART3_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

  3230. #define __HAL_RCC_C1_UART4_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

  3231. #define __HAL_RCC_C1_UART5_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

  3232. #define __HAL_RCC_C1_I2C1_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

  3233. #define __HAL_RCC_C1_I2C2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

  3234. #define __HAL_RCC_C1_I2C3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

  3235. #define __HAL_RCC_C1_CEC_CLK_DISABLE()            (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

  3236. #define __HAL_RCC_C1_DAC12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

  3237. #define __HAL_RCC_C1_UART7_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

  3238. #define __HAL_RCC_C1_UART8_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

  3239. #define __HAL_RCC_C1_CRS_CLK_DISABLE()            (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

  3240. #define __HAL_RCC_C1_SWPMI_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

  3241. #define __HAL_RCC_C1_OPAMP_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

  3242. #define __HAL_RCC_C1_MDIOS_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

  3243. #define __HAL_RCC_C1_FDCAN_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

  3244. 

  3245. /** @brief  Enable or disable the APB2 peripheral clock.

  3246.   * @note   After reset, the peripheral clock (used for registers read/write access)

  3247.   *         is disabled and the application software has to enable this clock before

  3248.   *         using it.

  3249.   */

  3250. 

  3251. #define __HAL_RCC_C1_TIM1_CLK_ENABLE()   do { \

  3252.                                         __IO uint32_t tmpreg; \

  3253.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\

  3254.                                         /* Delay after an RCC peripheral clock enabling */ \

  3255.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\

  3256.                                         UNUSED(tmpreg); \

  3257.                                        } while(0)

  3258. 

  3259. #define __HAL_RCC_C1_TIM8_CLK_ENABLE()   do { \

  3260.                                         __IO uint32_t tmpreg; \

  3261.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\

  3262.                                         /* Delay after an RCC peripheral clock enabling */ \

  3263.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\

  3264.                                         UNUSED(tmpreg); \

  3265.                                        } while(0)

  3266. 

  3267. #define __HAL_RCC_C1_USART1_CLK_ENABLE()   do { \

  3268.                                         __IO uint32_t tmpreg; \

  3269.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\

  3270.                                         /* Delay after an RCC peripheral clock enabling */ \

  3271.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\

  3272.                                         UNUSED(tmpreg); \

  3273.                                        } while(0)

  3274. 

  3275. #define __HAL_RCC_C1_USART6_CLK_ENABLE()   do { \

  3276.                                         __IO uint32_t tmpreg; \

  3277.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\

  3278.                                         /* Delay after an RCC peripheral clock enabling */ \

  3279.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\

  3280.                                         UNUSED(tmpreg); \

  3281.                                        } while(0)

  3282. 

  3283. #define __HAL_RCC_C1_SPI1_CLK_ENABLE()   do { \

  3284.                                         __IO uint32_t tmpreg; \

  3285.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\

  3286.                                         /* Delay after an RCC peripheral clock enabling */ \

  3287.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\

  3288.                                         UNUSED(tmpreg); \

  3289.                                        } while(0)

  3290. 

  3291. #define __HAL_RCC_C1_SPI4_CLK_ENABLE()   do { \

  3292.                                         __IO uint32_t tmpreg; \

  3293.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\

  3294.                                         /* Delay after an RCC peripheral clock enabling */ \

  3295.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\

  3296.                                         UNUSED(tmpreg); \

  3297.                                        } while(0)

  3298. 

  3299. #define __HAL_RCC_C1_TIM15_CLK_ENABLE()   do { \

  3300.                                         __IO uint32_t tmpreg; \

  3301.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\

  3302.                                         /* Delay after an RCC peripheral clock enabling */ \

  3303.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\

  3304.                                         UNUSED(tmpreg); \

  3305.                                        } while(0)

  3306. 

  3307. #define __HAL_RCC_C1_TIM16_CLK_ENABLE()   do { \

  3308.                                         __IO uint32_t tmpreg; \

  3309.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\

  3310.                                         /* Delay after an RCC peripheral clock enabling */ \

  3311.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\

  3312.                                         UNUSED(tmpreg); \

  3313.                                        } while(0)

  3314. 

  3315. #define __HAL_RCC_C1_TIM17_CLK_ENABLE()   do { \

  3316.                                         __IO uint32_t tmpreg; \

  3317.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\

  3318.                                         /* Delay after an RCC peripheral clock enabling */ \

  3319.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\

  3320.                                         UNUSED(tmpreg); \

  3321.                                        } while(0)

  3322. 

  3323. #define __HAL_RCC_C1_SPI5_CLK_ENABLE()   do { \

  3324.                                         __IO uint32_t tmpreg; \

  3325.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\

  3326.                                         /* Delay after an RCC peripheral clock enabling */ \

  3327.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\

  3328.                                         UNUSED(tmpreg); \

  3329.                                        } while(0)

  3330. 

  3331. #define __HAL_RCC_C1_SAI1_CLK_ENABLE()   do { \

  3332.                                         __IO uint32_t tmpreg; \

  3333.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\

  3334.                                         /* Delay after an RCC peripheral clock enabling */ \

  3335.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\

  3336.                                         UNUSED(tmpreg); \

  3337.                                        } while(0)

  3338. 

  3339. #define __HAL_RCC_C1_SAI2_CLK_ENABLE()   do { \

  3340.                                         __IO uint32_t tmpreg; \

  3341.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\

  3342.                                         /* Delay after an RCC peripheral clock enabling */ \

  3343.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\

  3344.                                         UNUSED(tmpreg); \

  3345.                                        } while(0)

  3346. 

  3347. #define __HAL_RCC_C1_SAI3_CLK_ENABLE()   do { \

  3348.                                         __IO uint32_t tmpreg; \

  3349.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\

  3350.                                         /* Delay after an RCC peripheral clock enabling */ \

  3351.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\

  3352.                                         UNUSED(tmpreg); \

  3353.                                        } while(0)

  3354. 

  3355. #define __HAL_RCC_C1_DFSDM1_CLK_ENABLE()   do { \

  3356.                                         __IO uint32_t tmpreg; \

  3357.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

  3358.                                         /* Delay after an RCC peripheral clock enabling */ \

  3359.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

  3360.                                         UNUSED(tmpreg); \

  3361.                                        } while(0)

  3362. 

  3363. #define __HAL_RCC_C1_HRTIM1_CLK_ENABLE()   do { \

  3364.                                         __IO uint32_t tmpreg; \

  3365.                                         SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\

  3366.                                         /* Delay after an RCC peripheral clock enabling */ \

  3367.                                         tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\

  3368.                                         UNUSED(tmpreg); \

  3369.                                        } while(0)

  3370. 

  3371. #define __HAL_RCC_C1_TIM1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

  3372. #define __HAL_RCC_C1_TIM8_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

  3373. #define __HAL_RCC_C1_USART1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

  3374. #define __HAL_RCC_C1_USART6_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

  3375. #define __HAL_RCC_C1_SPI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

  3376. #define __HAL_RCC_C1_SPI4_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

  3377. #define __HAL_RCC_C1_TIM15_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

  3378. #define __HAL_RCC_C1_TIM16_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

  3379. #define __HAL_RCC_C1_TIM17_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

  3380. #define __HAL_RCC_C1_SPI5_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

  3381. #define __HAL_RCC_C1_SAI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

  3382. #define __HAL_RCC_C1_SAI2_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)

  3383. #define __HAL_RCC_C1_SAI3_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)

  3384. #define __HAL_RCC_C1_DFSDM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

  3385. #define __HAL_RCC_C1_HRTIM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)

  3386. 

  3387. /** @brief  Enable or disable the APB4 peripheral clock.

  3388.   * @note   After reset, the peripheral clock (used for registers read/write access)

  3389.   *         is disabled and the application software has to enable this clock before

  3390.   *         using it.

  3391.   */

  3392. 

  3393. #define __HAL_RCC_C1_SYSCFG_CLK_ENABLE()   do { \

  3394.                                         __IO uint32_t tmpreg; \

  3395.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

  3396.                                         /* Delay after an RCC peripheral clock enabling */ \

  3397.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

  3398.                                         UNUSED(tmpreg); \

  3399.                                        } while(0)

  3400. 

  3401. #define __HAL_RCC_C1_LPUART1_CLK_ENABLE()   do { \

  3402.                                         __IO uint32_t tmpreg; \

  3403.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\

  3404.                                         /* Delay after an RCC peripheral clock enabling */ \

  3405.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\

  3406.                                         UNUSED(tmpreg); \

  3407.                                        } while(0)

  3408. 

  3409. #define __HAL_RCC_C1_SPI6_CLK_ENABLE()   do { \

  3410.                                         __IO uint32_t tmpreg; \

  3411.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\

  3412.                                         /* Delay after an RCC peripheral clock enabling */ \

  3413.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\

  3414.                                         UNUSED(tmpreg); \

  3415.                                        } while(0)

  3416. 

  3417. #define __HAL_RCC_C1_I2C4_CLK_ENABLE()   do { \

  3418.                                         __IO uint32_t tmpreg; \

  3419.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\

  3420.                                         /* Delay after an RCC peripheral clock enabling */ \

  3421.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\

  3422.                                         UNUSED(tmpreg); \

  3423.                                        } while(0)

  3424. 

  3425. #define __HAL_RCC_C1_LPTIM2_CLK_ENABLE()   do { \

  3426.                                         __IO uint32_t tmpreg; \

  3427.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

  3428.                                         /* Delay after an RCC peripheral clock enabling */ \

  3429.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

  3430.                                         UNUSED(tmpreg); \

  3431.                                        } while(0)

  3432. 

  3433. #define __HAL_RCC_C1_LPTIM3_CLK_ENABLE()   do { \

  3434.                                         __IO uint32_t tmpreg; \

  3435.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

  3436.                                         /* Delay after an RCC peripheral clock enabling */ \

  3437.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

  3438.                                         UNUSED(tmpreg); \

  3439.                                        } while(0)

  3440. 

  3441. #define __HAL_RCC_C1_LPTIM4_CLK_ENABLE()   do { \

  3442.                                         __IO uint32_t tmpreg; \

  3443.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

  3444.                                         /* Delay after an RCC peripheral clock enabling */ \

  3445.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

  3446.                                         UNUSED(tmpreg); \

  3447.                                        } while(0)

  3448. 

  3449. #define __HAL_RCC_C1_LPTIM5_CLK_ENABLE()   do { \

  3450.                                         __IO uint32_t tmpreg; \

  3451.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

  3452.                                         /* Delay after an RCC peripheral clock enabling */ \

  3453.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

  3454.                                         UNUSED(tmpreg); \

  3455.                                        } while(0)

  3456. 

  3457. #define __HAL_RCC_C1_COMP12_CLK_ENABLE()   do { \

  3458.                                         __IO uint32_t tmpreg; \

  3459.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\

  3460.                                         /* Delay after an RCC peripheral clock enabling */ \

  3461.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\

  3462.                                         UNUSED(tmpreg); \

  3463.                                        } while(0)

  3464. 

  3465. 

  3466. #define __HAL_RCC_C1_VREF_CLK_ENABLE()   do { \

  3467.                                         __IO uint32_t tmpreg; \

  3468.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\

  3469.                                         /* Delay after an RCC peripheral clock enabling */ \

  3470.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\

  3471.                                         UNUSED(tmpreg); \

  3472.                                        } while(0)

  3473. 

  3474. #define __HAL_RCC_C1_RTC_CLK_ENABLE()   do { \

  3475.                                         __IO uint32_t tmpreg; \

  3476.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

  3477.                                         /* Delay after an RCC peripheral clock enabling */ \

  3478.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

  3479.                                         UNUSED(tmpreg); \

  3480.                                        } while(0)

  3481. 

  3482. #define __HAL_RCC_C1_SAI4_CLK_ENABLE()   do { \

  3483.                                         __IO uint32_t tmpreg; \

  3484.                                         SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\

  3485.                                         /* Delay after an RCC peripheral clock enabling */ \

  3486.                                         tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\

  3487.                                         UNUSED(tmpreg); \

  3488.                                        } while(0)

  3489. 

  3490. 

  3491. #define __HAL_RCC_C1_SYSCFG_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

  3492. #define __HAL_RCC_C1_LPUART1_CLK_DISABLE()          (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

  3493. #define __HAL_RCC_C1_SPI6_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

  3494. #define __HAL_RCC_C1_I2C4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

  3495. #define __HAL_RCC_C1_LPTIM2_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

  3496. #define __HAL_RCC_C1_LPTIM3_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

  3497. #define __HAL_RCC_C1_LPTIM4_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)

  3498. #define __HAL_RCC_C1_LPTIM5_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)

  3499. #define __HAL_RCC_C1_COMP12_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

  3500. #define __HAL_RCC_C1_VREF_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

  3501. #define __HAL_RCC_C1_RTC_CLK_DISABLE()              (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

  3502. #define __HAL_RCC_C1_SAI4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)

  3503. 

  3504. /* Exported macros for RCC_C2 -------------------------------------------------*/

  3505. 

  3506. /** @brief  Enable or disable the AHB3 peripheral clock.

  3507.   * @note   After reset, the peripheral clock (used for registers read/write access)

  3508.   *         is disabled and the application software has to enable this clock before

  3509.   *         using it.

  3510.   */

  3511. 

  3512. 

  3513. #define __HAL_RCC_C2_MDMA_CLK_ENABLE()   do { \

  3514.                                         __IO uint32_t tmpreg; \

  3515.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

  3516.                                         /* Delay after an RCC peripheral clock enabling */ \

  3517.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

  3518.                                         UNUSED(tmpreg); \

  3519.                                        } while(0)

  3520. 

  3521. #define __HAL_RCC_C2_DMA2D_CLK_ENABLE()   do { \

  3522.                                         __IO uint32_t tmpreg; \

  3523.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

  3524.                                         /* Delay after an RCC peripheral clock enabling */ \

  3525.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

  3526.                                         UNUSED(tmpreg); \

  3527.                                        } while(0)

  3528. 

  3529. #define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE()   do { \

  3530.                                         __IO uint32_t tmpreg; \

  3531.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

  3532.                                         /* Delay after an RCC peripheral clock enabling */ \

  3533.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

  3534.                                         UNUSED(tmpreg); \

  3535.                                        } while(0)

  3536. 

  3537. #define __HAL_RCC_FLASH_C2_ALLOCATE()   do { \

  3538.                                         __IO uint32_t tmpreg; \

  3539.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\

  3540.                                         /* Delay after an RCC peripheral clock enabling */ \

  3541.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\

  3542.                                         UNUSED(tmpreg); \

  3543.                                        } while(0)

  3544. 

  3545. #define __HAL_RCC_DTCM1_C2_ALLOCATE()   do { \

  3546.                                         __IO uint32_t tmpreg; \

  3547.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\

  3548.                                         /* Delay after an RCC peripheral clock enabling */ \

  3549.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\

  3550.                                         UNUSED(tmpreg); \

  3551.                                        } while(0)

  3552. 

  3553. #define __HAL_RCC_DTCM2_C2_ALLOCATE()   do { \

  3554.                                         __IO uint32_t tmpreg; \

  3555.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\

  3556.                                         /* Delay after an RCC peripheral clock enabling */ \

  3557.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\

  3558.                                         UNUSED(tmpreg); \

  3559.                                        } while(0)

  3560. 

  3561. #define __HAL_RCC_ITCM_C2_ALLOCATE()   do { \

  3562.                                         __IO uint32_t tmpreg; \

  3563.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\

  3564.                                         /* Delay after an RCC peripheral clock enabling */ \

  3565.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\

  3566.                                         UNUSED(tmpreg); \

  3567.                                        } while(0)

  3568. 

  3569. #define __HAL_RCC_D1SRAM1_C2_ALLOCATE()   do { \

  3570.                                         __IO uint32_t tmpreg; \

  3571.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\

  3572.                                         /* Delay after an RCC peripheral clock enabling */ \

  3573.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\

  3574.                                         UNUSED(tmpreg); \

  3575.                                        } while(0)

  3576. 

  3577. #define __HAL_RCC_C2_FMC_CLK_ENABLE()   do { \

  3578.                                         __IO uint32_t tmpreg; \

  3579.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\

  3580.                                         /* Delay after an RCC peripheral clock enabling */ \

  3581.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\

  3582.                                         UNUSED(tmpreg); \

  3583.                                        } while(0)

  3584. 

  3585. #define __HAL_RCC_C2_QSPI_CLK_ENABLE()   do { \

  3586.                                         __IO uint32_t tmpreg; \

  3587.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

  3588.                                         /* Delay after an RCC peripheral clock enabling */ \

  3589.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

  3590.                                         UNUSED(tmpreg); \

  3591.                                        } while(0)

  3592. 

  3593. #define __HAL_RCC_C2_SDMMC1_CLK_ENABLE()   do { \

  3594.                                         __IO uint32_t tmpreg; \

  3595.                                         SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

  3596.                                         /* Delay after an RCC peripheral clock enabling */ \

  3597.                                         tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

  3598.                                         UNUSED(tmpreg); \

  3599.                                        } while(0)

  3600. 

  3601. 

  3602. 

  3603. 

  3604. #define __HAL_RCC_C2_MDMA_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

  3605. #define __HAL_RCC_C2_DMA2D_CLK_DISABLE()           (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

  3606. #define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE()        (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))

  3607. #define __HAL_RCC_C2_FMC_CLK_DISABLE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

  3608. #define __HAL_RCC_C2_QSPI_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))

  3609. #define __HAL_RCC_C2_SDMMC1_CLK_DISABLE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

  3610. #define __HAL_RCC_FLASH_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))

  3611. #define __HAL_RCC_DTCM1_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))

  3612. #define __HAL_RCC_DTCM2_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))

  3613. #define __HAL_RCC_ITCM_C2_DEALLOCATE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))

  3614. #define __HAL_RCC_D1SRAM1_C2_DEALLOCATE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))

  3615. 

  3616. /** @brief  Enable or disable the AHB1 peripheral clock.

  3617.   * @note   After reset, the peripheral clock (used for registers read/write access)

  3618.   *         is disabled and the application software has to enable this clock before

  3619.   *         using it.

  3620.   */

  3621. 

  3622. #define __HAL_RCC_C2_DMA1_CLK_ENABLE()   do { \

  3623.                                         __IO uint32_t tmpreg; \

  3624.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

  3625.                                         /* Delay after an RCC peripheral clock enabling */ \

  3626.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

  3627.                                         UNUSED(tmpreg); \

  3628.                                        } while(0)

  3629. 

  3630. #define __HAL_RCC_C2_DMA2_CLK_ENABLE()   do { \

  3631.                                         __IO uint32_t tmpreg; \

  3632.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

  3633.                                         /* Delay after an RCC peripheral clock enabling */ \

  3634.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

  3635.                                         UNUSED(tmpreg); \

  3636.                                        } while(0)

  3637. 

  3638. #define __HAL_RCC_C2_ADC12_CLK_ENABLE()   do { \

  3639.                                         __IO uint32_t tmpreg; \

  3640.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

  3641.                                         /* Delay after an RCC peripheral clock enabling */ \

  3642.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

  3643.                                         UNUSED(tmpreg); \

  3644.                                        } while(0)

  3645. 

  3646. #define __HAL_RCC_C2_ART_CLK_ENABLE()   do { \

  3647.                                         __IO uint32_t tmpreg; \

  3648.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\

  3649.                                         /* Delay after an RCC peripheral clock enabling */ \

  3650.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\

  3651.                                         UNUSED(tmpreg); \

  3652.                                        } while(0)

  3653. 

  3654. #define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE()   do { \

  3655.                                         __IO uint32_t tmpreg; \

  3656.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

  3657.                                         /* Delay after an RCC peripheral clock enabling */ \

  3658.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

  3659.                                         UNUSED(tmpreg); \

  3660.                                        } while(0)

  3661. 

  3662. #define __HAL_RCC_C2_ETH1TX_CLK_ENABLE()   do { \

  3663.                                         __IO uint32_t tmpreg; \

  3664.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

  3665.                                         /* Delay after an RCC peripheral clock enabling */ \

  3666.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

  3667.                                         UNUSED(tmpreg); \

  3668.                                        } while(0)

  3669. 

  3670. #define __HAL_RCC_C2_ETH1RX_CLK_ENABLE()   do { \

  3671.                                         __IO uint32_t tmpreg; \

  3672.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

  3673.                                         /* Delay after an RCC peripheral clock enabling */ \

  3674.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

  3675.                                         UNUSED(tmpreg); \

  3676.                                        } while(0)

  3677. 

  3678. #define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE()   do { \

  3679.                                         __IO uint32_t tmpreg; \

  3680.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

  3681.                                         /* Delay after an RCC peripheral clock enabling */ \

  3682.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

  3683.                                         UNUSED(tmpreg); \

  3684.                                        } while(0)

  3685. 

  3686. #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \

  3687.                                         __IO uint32_t tmpreg; \

  3688.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

  3689.                                         /* Delay after an RCC peripheral clock enabling */ \

  3690.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

  3691.                                         UNUSED(tmpreg); \

  3692.                                        } while(0)

  3693. 

  3694. #define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE()   do { \

  3695.                                         __IO uint32_t tmpreg; \

  3696.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

  3697.                                         /* Delay after an RCC peripheral clock enabling */ \

  3698.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

  3699.                                         UNUSED(tmpreg); \

  3700.                                        } while(0)

  3701. 

  3702. #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \

  3703.                                         __IO uint32_t tmpreg; \

  3704.                                         SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

  3705.                                         /* Delay after an RCC peripheral clock enabling */ \

  3706.                                         tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

  3707.                                         UNUSED(tmpreg); \

  3708.                                        } while(0)

  3709. 

  3710. 

  3711. #define __HAL_RCC_C2_DMA1_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

  3712. #define __HAL_RCC_C2_DMA2_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

  3713. #define __HAL_RCC_C2_ADC12_CLK_DISABLE()            (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

  3714. #define __HAL_RCC_C2_ART_CLK_DISABLE()              (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))

  3715. #define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE()          (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))

  3716. #define __HAL_RCC_C2_ETH1TX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))

  3717. #define __HAL_RCC_C2_ETH1RX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))

  3718. #define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

  3719. #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

  3720. #define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))

  3721. #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))

  3722. 

  3723. /** @brief  Enable or disable the AHB2 peripheral clock.

  3724.   * @note   After reset, the peripheral clock (used for registers read/write access)

  3725.   *         is disabled and the application software has to enable this clock before

  3726.   *         using it.

  3727.   */

  3728. 

  3729. #define __HAL_RCC_C2_DCMI_CLK_ENABLE()   do { \

  3730.                                         __IO uint32_t tmpreg; \

  3731.                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

  3732.                                         /* Delay after an RCC peripheral clock enabling */ \

  3733.                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

  3734.                                         UNUSED(tmpreg); \

  3735.                                        } while(0)

  3736. 

  3737. #define __HAL_RCC_C2_CRYP_CLK_ENABLE()   do { \

  3738.                                         __IO uint32_t tmpreg; \

  3739.                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

  3740.                                         /* Delay after an RCC peripheral clock enabling */ \

  3741.                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

  3742.                                         UNUSED(tmpreg); \

  3743.                                        } while(0)

  3744. 

  3745. #define __HAL_RCC_C2_HASH_CLK_ENABLE()   do { \

  3746.                                         __IO uint32_t tmpreg; \

  3747.                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\

  3748.                                         /* Delay after an RCC peripheral clock enabling */ \

  3749.                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\

  3750.                                         UNUSED(tmpreg); \

  3751.                                        } while(0)

  3752. 

  3753. #define __HAL_RCC_C2_RNG_CLK_ENABLE()   do { \

  3754.                                         __IO uint32_t tmpreg; \

  3755.                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\

  3756.                                         /* Delay after an RCC peripheral clock enabling */ \

  3757.                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\

  3758.                                         UNUSED(tmpreg); \

  3759.                                        } while(0)

  3760. 

  3761. #define __HAL_RCC_C2_SDMMC2_CLK_ENABLE()   do { \

  3762.                                         __IO uint32_t tmpreg; \

  3763.                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

  3764.                                         /* Delay after an RCC peripheral clock enabling */ \

  3765.                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

  3766.                                         UNUSED(tmpreg); \

  3767.                                        } while(0)

  3768. 

  3769. #define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE()   do { \

  3770.                                         __IO uint32_t tmpreg; \

  3771.                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

  3772.                                         /* Delay after an RCC peripheral clock enabling */ \

  3773.                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

  3774.                                         UNUSED(tmpreg); \

  3775.                                        } while(0)

  3776. 

  3777. #define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE()   do { \

  3778.                                         __IO uint32_t tmpreg; \

  3779.                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

  3780.                                         /* Delay after an RCC peripheral clock enabling */ \

  3781.                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

  3782.                                         UNUSED(tmpreg); \

  3783.                                        } while(0)

  3784. 

  3785. #define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE()   do { \

  3786.                                         __IO uint32_t tmpreg; \

  3787.                                         SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

  3788.                                         /* Delay after an RCC peripheral clock enabling */ \

  3789.                                         tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

  3790.                                         UNUSED(tmpreg); \

  3791.                                        } while(0)

  3792. 

  3793. #define __HAL_RCC_C2_DCMI_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

  3794. #define __HAL_RCC_C2_CRYP_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))

  3795. #define __HAL_RCC_C2_HASH_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))

  3796. #define __HAL_RCC_C2_RNG_CLK_DISABLE()              (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

  3797. #define __HAL_RCC_C2_SDMMC2_CLK_DISABLE()           (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

  3798. #define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))

  3799. #define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))

  3800. #define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))

  3801. 

  3802. /** @brief  Enable or disable the AHB4 peripheral clock.

  3803.   * @note   After reset, the peripheral clock (used for registers read/write access)

  3804.   *         is disabled and the application software has to enable this clock before

  3805.   *         using it.

  3806.   */

  3807. 

  3808. #define __HAL_RCC_C2_GPIOA_CLK_ENABLE()   do { \

  3809.                                         __IO uint32_t tmpreg; \

  3810.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

  3811.                                         /* Delay after an RCC peripheral clock enabling */ \

  3812.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

  3813.                                         UNUSED(tmpreg); \

  3814.                                        } while(0)

  3815. 

  3816. #define __HAL_RCC_C2_GPIOB_CLK_ENABLE()   do { \

  3817.                                         __IO uint32_t tmpreg; \

  3818.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

  3819.                                         /* Delay after an RCC peripheral clock enabling */ \

  3820.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

  3821.                                         UNUSED(tmpreg); \

  3822.                                        } while(0)

  3823. 

  3824. #define __HAL_RCC_C2_GPIOC_CLK_ENABLE()   do { \

  3825.                                         __IO uint32_t tmpreg; \

  3826.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

  3827.                                         /* Delay after an RCC peripheral clock enabling */ \

  3828.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

  3829.                                         UNUSED(tmpreg); \

  3830.                                        } while(0)

  3831. 

  3832. #define __HAL_RCC_C2_GPIOD_CLK_ENABLE()   do { \

  3833.                                         __IO uint32_t tmpreg; \

  3834.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

  3835.                                         /* Delay after an RCC peripheral clock enabling */ \

  3836.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

  3837.                                         UNUSED(tmpreg); \

  3838.                                        } while(0)

  3839. 

  3840. #define __HAL_RCC_C2_GPIOE_CLK_ENABLE()   do { \

  3841.                                         __IO uint32_t tmpreg; \

  3842.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

  3843.                                         /* Delay after an RCC peripheral clock enabling */ \

  3844.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

  3845.                                         UNUSED(tmpreg); \

  3846.                                        } while(0)

  3847. 

  3848. #define __HAL_RCC_C2_GPIOF_CLK_ENABLE()   do { \

  3849.                                         __IO uint32_t tmpreg; \

  3850.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

  3851.                                         /* Delay after an RCC peripheral clock enabling */ \

  3852.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

  3853.                                         UNUSED(tmpreg); \

  3854.                                        } while(0)

  3855. 

  3856. #define __HAL_RCC_C2_GPIOG_CLK_ENABLE()   do { \

  3857.                                         __IO uint32_t tmpreg; \

  3858.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

  3859.                                         /* Delay after an RCC peripheral clock enabling */ \

  3860.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

  3861.                                         UNUSED(tmpreg); \

  3862.                                        } while(0)

  3863. 

  3864. #define __HAL_RCC_C2_GPIOH_CLK_ENABLE()   do { \

  3865.                                         __IO uint32_t tmpreg; \

  3866.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

  3867.                                         /* Delay after an RCC peripheral clock enabling */ \

  3868.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

  3869.                                         UNUSED(tmpreg); \

  3870.                                        } while(0)

  3871. 

  3872. #define __HAL_RCC_C2_GPIOI_CLK_ENABLE()   do { \

  3873.                                         __IO uint32_t tmpreg; \

  3874.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

  3875.                                         /* Delay after an RCC peripheral clock enabling */ \

  3876.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

  3877.                                         UNUSED(tmpreg); \

  3878.                                        } while(0)

  3879. 

  3880. #define __HAL_RCC_C2_GPIOJ_CLK_ENABLE()   do { \

  3881.                                         __IO uint32_t tmpreg; \

  3882.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

  3883.                                         /* Delay after an RCC peripheral clock enabling */ \

  3884.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

  3885.                                         UNUSED(tmpreg); \

  3886.                                        } while(0)

  3887. 

  3888. #define __HAL_RCC_C2_GPIOK_CLK_ENABLE()   do { \

  3889.                                         __IO uint32_t tmpreg; \

  3890.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

  3891.                                         /* Delay after an RCC peripheral clock enabling */ \

  3892.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

  3893.                                         UNUSED(tmpreg); \

  3894.                                        } while(0)

  3895. 

  3896. #define __HAL_RCC_C2_CRC_CLK_ENABLE()   do { \

  3897.                                         __IO uint32_t tmpreg; \

  3898.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\

  3899.                                         /* Delay after an RCC peripheral clock enabling */ \

  3900.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\

  3901.                                         UNUSED(tmpreg); \

  3902.                                        } while(0)

  3903. 

  3904. #define __HAL_RCC_C2_BDMA_CLK_ENABLE()   do { \

  3905.                                         __IO uint32_t tmpreg; \

  3906.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

  3907.                                         /* Delay after an RCC peripheral clock enabling */ \

  3908.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

  3909.                                         UNUSED(tmpreg); \

  3910.                                        } while(0)

  3911. 

  3912. #define __HAL_RCC_C2_ADC3_CLK_ENABLE()   do { \

  3913.                                         __IO uint32_t tmpreg; \

  3914.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

  3915.                                         /* Delay after an RCC peripheral clock enabling */ \

  3916.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

  3917.                                         UNUSED(tmpreg); \

  3918.                                        } while(0)

  3919. 

  3920. #define __HAL_RCC_C2_HSEM_CLK_ENABLE()   do { \

  3921.                                         __IO uint32_t tmpreg; \

  3922.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

  3923.                                         /* Delay after an RCC peripheral clock enabling */ \

  3924.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

  3925.                                         UNUSED(tmpreg); \

  3926.                                        } while(0)

  3927. 

  3928. #define __HAL_RCC_C2_BKPRAM_CLK_ENABLE()   do { \

  3929.                                         __IO uint32_t tmpreg; \

  3930.                                         SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

  3931.                                         /* Delay after an RCC peripheral clock enabling */ \

  3932.                                         tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

  3933.                                         UNUSED(tmpreg); \

  3934.                                        } while(0)

  3935. 

  3936. 

  3937. #define __HAL_RCC_C2_GPIOA_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

  3938. #define __HAL_RCC_C2_GPIOB_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

  3939. #define __HAL_RCC_C2_GPIOC_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

  3940. #define __HAL_RCC_C2_GPIOD_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

  3941. #define __HAL_RCC_C2_GPIOE_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

  3942. #define __HAL_RCC_C2_GPIOF_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

  3943. #define __HAL_RCC_C2_GPIOG_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

  3944. #define __HAL_RCC_C2_GPIOH_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

  3945. #define __HAL_RCC_C2_GPIOI_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)

  3946. #define __HAL_RCC_C2_GPIOJ_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

  3947. #define __HAL_RCC_C2_GPIOK_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

  3948. #define __HAL_RCC_C2_CRC_CLK_DISABLE()             (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)

  3949. #define __HAL_RCC_C2_BDMA_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

  3950. #define __HAL_RCC_C2_ADC3_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)

  3951. #define __HAL_RCC_C2_HSEM_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)

  3952. #define __HAL_RCC_C2_BKPRAM_CLK_DISABLE()          (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

  3953. 

  3954. 

  3955. /** @brief  Enable or disable the APB3 peripheral clock.

  3956.   * @note   After reset, the peripheral clock (used for registers read/write access)

  3957.   *         is disabled and the application software has to enable this clock before

  3958.   *         using it.

  3959.   */

  3960. 

  3961. #define __HAL_RCC_C2_LTDC_CLK_ENABLE()   do { \

  3962.                                         __IO uint32_t tmpreg; \

  3963.                                         SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\

  3964.                                         /* Delay after an RCC peripheral clock enabling */ \

  3965.                                         tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\

  3966.                                         UNUSED(tmpreg); \

  3967.                                        } while(0)

  3968. 

  3969. #define __HAL_RCC_C2_DSI_CLK_ENABLE()   do { \

  3970.                                         __IO uint32_t tmpreg; \

  3971.                                         SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\

  3972.                                         /* Delay after an RCC peripheral clock enabling */ \

  3973.                                         tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\

  3974.                                         UNUSED(tmpreg); \

  3975.                                        } while(0)

  3976. 

  3977. #define __HAL_RCC_C2_WWDG1_CLK_ENABLE()   do { \

  3978.                                         __IO uint32_t tmpreg; \

  3979.                                         SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\

  3980.                                         /* Delay after an RCC peripheral clock enabling */ \

  3981.                                         tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\

  3982.                                         UNUSED(tmpreg); \

  3983.                                        } while(0)

  3984. 

  3985. #define __HAL_RCC_C2_LTDC_CLK_DISABLE()           (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)

  3986. #define __HAL_RCC_C2_DSI_CLK_DISABLE()            (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)

  3987. #define __HAL_RCC_C2_WWDG1_CLK_DISABLE()          (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

  3988. 

  3989. /** @brief  Enable or disable the APB1 peripheral clock.

  3990.   * @note   After reset, the peripheral clock (used for registers read/write access)

  3991.   *         is disabled and the application software has to enable this clock before

  3992.   *         using it.

  3993.   */

  3994. 

  3995. #define __HAL_RCC_C2_TIM2_CLK_ENABLE()   do { \

  3996.                                         __IO uint32_t tmpreg; \

  3997.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\

  3998.                                         /* Delay after an RCC peripheral clock enabling */ \

  3999.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\

  4000.                                         UNUSED(tmpreg); \

  4001.                                        } while(0)

  4002. 

  4003. #define __HAL_RCC_C2_TIM3_CLK_ENABLE()   do { \

  4004.                                         __IO uint32_t tmpreg; \

  4005.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\

  4006.                                         /* Delay after an RCC peripheral clock enabling */ \

  4007.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\

  4008.                                         UNUSED(tmpreg); \

  4009.                                        } while(0)

  4010. 

  4011. #define __HAL_RCC_C2_TIM4_CLK_ENABLE()   do { \

  4012.                                         __IO uint32_t tmpreg; \

  4013.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\

  4014.                                         /* Delay after an RCC peripheral clock enabling */ \

  4015.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\

  4016.                                         UNUSED(tmpreg); \

  4017.                                        } while(0)

  4018. 

  4019. #define __HAL_RCC_C2_TIM5_CLK_ENABLE()   do { \

  4020.                                         __IO uint32_t tmpreg; \

  4021.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\

  4022.                                         /* Delay after an RCC peripheral clock enabling */ \

  4023.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\

  4024.                                         UNUSED(tmpreg); \

  4025.                                        } while(0)

  4026. 

  4027. #define __HAL_RCC_C2_TIM6_CLK_ENABLE()   do { \

  4028.                                         __IO uint32_t tmpreg; \

  4029.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\

  4030.                                         /* Delay after an RCC peripheral clock enabling */ \

  4031.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\

  4032.                                         UNUSED(tmpreg); \

  4033.                                        } while(0)

  4034. 

  4035. #define __HAL_RCC_C2_TIM7_CLK_ENABLE()   do { \

  4036.                                         __IO uint32_t tmpreg; \

  4037.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\

  4038.                                         /* Delay after an RCC peripheral clock enabling */ \

  4039.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\

  4040.                                         UNUSED(tmpreg); \

  4041.                                        } while(0)

  4042. 

  4043. #define __HAL_RCC_C2_TIM12_CLK_ENABLE()   do { \

  4044.                                         __IO uint32_t tmpreg; \

  4045.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\

  4046.                                         /* Delay after an RCC peripheral clock enabling */ \

  4047.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\

  4048.                                         UNUSED(tmpreg); \

  4049.                                        } while(0)

  4050. 

  4051. #define __HAL_RCC_C2_TIM13_CLK_ENABLE()   do { \

  4052.                                         __IO uint32_t tmpreg; \

  4053.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\

  4054.                                         /* Delay after an RCC peripheral clock enabling */ \

  4055.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\

  4056.                                         UNUSED(tmpreg); \

  4057.                                        } while(0)

  4058. 

  4059. #define __HAL_RCC_C2_TIM14_CLK_ENABLE()   do { \

  4060.                                         __IO uint32_t tmpreg; \

  4061.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\

  4062.                                         /* Delay after an RCC peripheral clock enabling */ \

  4063.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\

  4064.                                         UNUSED(tmpreg); \

  4065.                                        } while(0)

  4066. 

  4067. #define __HAL_RCC_C2_LPTIM1_CLK_ENABLE()   do { \

  4068.                                         __IO uint32_t tmpreg; \

  4069.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

  4070.                                         /* Delay after an RCC peripheral clock enabling */ \

  4071.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

  4072.                                         UNUSED(tmpreg); \

  4073.                                        } while(0)

  4074. 

  4075. #define __HAL_RCC_C2_WWDG2_CLK_ENABLE()   do { \

  4076.                                         __IO uint32_t tmpreg; \

  4077.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\

  4078.                                         /* Delay after an RCC peripheral clock enabling */ \

  4079.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\

  4080.                                         UNUSED(tmpreg); \

  4081.                                        } while(0)

  4082. 

  4083. #define __HAL_RCC_C2_SPI2_CLK_ENABLE()   do { \

  4084.                                         __IO uint32_t tmpreg; \

  4085.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\

  4086.                                         /* Delay after an RCC peripheral clock enabling */ \

  4087.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\

  4088.                                         UNUSED(tmpreg); \

  4089.                                        } while(0)

  4090. 

  4091. #define __HAL_RCC_C2_SPI3_CLK_ENABLE()   do { \

  4092.                                         __IO uint32_t tmpreg; \

  4093.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\

  4094.                                         /* Delay after an RCC peripheral clock enabling */ \

  4095.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\

  4096.                                         UNUSED(tmpreg); \

  4097.                                        } while(0)

  4098. 

  4099. #define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE()   do { \

  4100.                                         __IO uint32_t tmpreg; \

  4101.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

  4102.                                         /* Delay after an RCC peripheral clock enabling */ \

  4103.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

  4104.                                         UNUSED(tmpreg); \

  4105.                                        } while(0)

  4106. 

  4107. #define __HAL_RCC_C2_USART2_CLK_ENABLE()   do { \

  4108.                                         __IO uint32_t tmpreg; \

  4109.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\

  4110.                                         /* Delay after an RCC peripheral clock enabling */ \

  4111.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\

  4112.                                         UNUSED(tmpreg); \

  4113.                                        } while(0)

  4114. 

  4115. #define __HAL_RCC_C2_USART3_CLK_ENABLE()   do { \

  4116.                                         __IO uint32_t tmpreg; \

  4117.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\

  4118.                                         /* Delay after an RCC peripheral clock enabling */ \

  4119.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\

  4120.                                         UNUSED(tmpreg); \

  4121.                                        } while(0)

  4122. 

  4123. #define __HAL_RCC_C2_UART4_CLK_ENABLE()   do { \

  4124.                                         __IO uint32_t tmpreg; \

  4125.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\

  4126.                                         /* Delay after an RCC peripheral clock enabling */ \

  4127.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\

  4128.                                         UNUSED(tmpreg); \

  4129.                                        } while(0)

  4130. 

  4131. #define __HAL_RCC_C2_UART5_CLK_ENABLE()   do { \

  4132.                                         __IO uint32_t tmpreg; \

  4133.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\

  4134.                                         /* Delay after an RCC peripheral clock enabling */ \

  4135.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\

  4136.                                         UNUSED(tmpreg); \

  4137.                                        } while(0)

  4138. 

  4139. #define __HAL_RCC_C2_I2C1_CLK_ENABLE()   do { \

  4140.                                         __IO uint32_t tmpreg; \

  4141.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\

  4142.                                         /* Delay after an RCC peripheral clock enabling */ \

  4143.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\

  4144.                                         UNUSED(tmpreg); \

  4145.                                        } while(0)

  4146. 

  4147. #define __HAL_RCC_C2_I2C2_CLK_ENABLE()   do { \

  4148.                                         __IO uint32_t tmpreg; \

  4149.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\

  4150.                                         /* Delay after an RCC peripheral clock enabling */ \

  4151.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\

  4152.                                         UNUSED(tmpreg); \

  4153.                                        } while(0)

  4154. 

  4155. #define __HAL_RCC_C2_I2C3_CLK_ENABLE()   do { \

  4156.                                         __IO uint32_t tmpreg; \

  4157.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\

  4158.                                         /* Delay after an RCC peripheral clock enabling */ \

  4159.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\

  4160.                                         UNUSED(tmpreg); \

  4161.                                        } while(0)

  4162. 

  4163. #define __HAL_RCC_C2_CEC_CLK_ENABLE()   do { \

  4164.                                         __IO uint32_t tmpreg; \

  4165.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\

  4166.                                         /* Delay after an RCC peripheral clock enabling */ \

  4167.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\

  4168.                                         UNUSED(tmpreg); \

  4169.                                        } while(0)

  4170. 

  4171. #define __HAL_RCC_C2_DAC12_CLK_ENABLE()   do { \

  4172.                                         __IO uint32_t tmpreg; \

  4173.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\

  4174.                                         /* Delay after an RCC peripheral clock enabling */ \

  4175.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\

  4176.                                         UNUSED(tmpreg); \

  4177.                                        } while(0)

  4178. 

  4179. #define __HAL_RCC_C2_UART7_CLK_ENABLE()   do { \

  4180.                                         __IO uint32_t tmpreg; \

  4181.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\

  4182.                                         /* Delay after an RCC peripheral clock enabling */ \

  4183.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\

  4184.                                         UNUSED(tmpreg); \

  4185.                                        } while(0)

  4186. 

  4187. #define __HAL_RCC_C2_UART8_CLK_ENABLE()   do { \

  4188.                                         __IO uint32_t tmpreg; \

  4189.                                         SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\

  4190.                                         /* Delay after an RCC peripheral clock enabling */ \

  4191.                                         tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\

  4192.                                         UNUSED(tmpreg); \

  4193.                                        } while(0)

  4194. 

  4195. #define __HAL_RCC_C2_CRS_CLK_ENABLE()   do { \

  4196.                                         __IO uint32_t tmpreg; \

  4197.                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\

  4198.                                         /* Delay after an RCC peripheral clock enabling */ \

  4199.                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\

  4200.                                         UNUSED(tmpreg); \

  4201.                                        } while(0)

  4202. 

  4203. #define __HAL_RCC_C2_SWPMI_CLK_ENABLE()   do { \

  4204.                                         __IO uint32_t tmpreg; \

  4205.                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\

  4206.                                         /* Delay after an RCC peripheral clock enabling */ \

  4207.                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\

  4208.                                         UNUSED(tmpreg); \

  4209.                                        } while(0)

  4210. 

  4211. #define __HAL_RCC_C2_OPAMP_CLK_ENABLE()   do { \

  4212.                                         __IO uint32_t tmpreg; \

  4213.                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\

  4214.                                         /* Delay after an RCC peripheral clock enabling */ \

  4215.                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\

  4216.                                         UNUSED(tmpreg); \

  4217.                                        } while(0)

  4218. 

  4219. #define __HAL_RCC_C2_MDIOS_CLK_ENABLE()   do { \

  4220.                                         __IO uint32_t tmpreg; \

  4221.                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\

  4222.                                         /* Delay after an RCC peripheral clock enabling */ \

  4223.                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\

  4224.                                         UNUSED(tmpreg); \

  4225.                                        } while(0)

  4226. 

  4227. #define __HAL_RCC_C2_FDCAN_CLK_ENABLE()   do { \

  4228.                                         __IO uint32_t tmpreg; \

  4229.                                         SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\

  4230.                                         /* Delay after an RCC peripheral clock enabling */ \

  4231.                                         tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\

  4232.                                         UNUSED(tmpreg); \

  4233.                                        } while(0)

  4234. 

  4235. 

  4236. #define __HAL_RCC_C2_TIM2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

  4237. #define __HAL_RCC_C2_TIM3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

  4238. #define __HAL_RCC_C2_TIM4_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

  4239. #define __HAL_RCC_C2_TIM5_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

  4240. #define __HAL_RCC_C2_TIM6_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

  4241. #define __HAL_RCC_C2_TIM7_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

  4242. #define __HAL_RCC_C2_TIM12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

  4243. #define __HAL_RCC_C2_TIM13_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

  4244. #define __HAL_RCC_C2_TIM14_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

  4245. #define __HAL_RCC_C2_LPTIM1_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

  4246. #define __HAL_RCC_C2_WWDG2_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)

  4247. #define __HAL_RCC_C2_SPI2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

  4248. #define __HAL_RCC_C2_SPI3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

  4249. #define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE()        (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

  4250. #define __HAL_RCC_C2_USART2_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

  4251. #define __HAL_RCC_C2_USART3_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

  4252. #define __HAL_RCC_C2_UART4_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

  4253. #define __HAL_RCC_C2_UART5_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

  4254. #define __HAL_RCC_C2_I2C1_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

  4255. #define __HAL_RCC_C2_I2C2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

  4256. #define __HAL_RCC_C2_I2C3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

  4257. #define __HAL_RCC_C2_CEC_CLK_DISABLE()            (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

  4258. #define __HAL_RCC_C2_DAC12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

  4259. #define __HAL_RCC_C2_UART7_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

  4260. #define __HAL_RCC_C2_UART8_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

  4261. #define __HAL_RCC_C2_CRS_CLK_DISABLE()            (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

  4262. #define __HAL_RCC_C2_SWPMI_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

  4263. #define __HAL_RCC_C2_OPAMP_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

  4264. #define __HAL_RCC_C2_MDIOS_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

  4265. #define __HAL_RCC_C2_FDCAN_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

  4266. 

  4267. /** @brief  Enable or disable the APB2 peripheral clock.

  4268.   * @note   After reset, the peripheral clock (used for registers read/write access)

  4269.   *         is disabled and the application software has to enable this clock before

  4270.   *         using it.

  4271.   */

  4272. 

  4273. #define __HAL_RCC_C2_TIM1_CLK_ENABLE()   do { \

  4274.                                         __IO uint32_t tmpreg; \

  4275.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\

  4276.                                         /* Delay after an RCC peripheral clock enabling */ \

  4277.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\

  4278.                                         UNUSED(tmpreg); \

  4279.                                        } while(0)

  4280. 

  4281. #define __HAL_RCC_C2_TIM8_CLK_ENABLE()   do { \

  4282.                                         __IO uint32_t tmpreg; \

  4283.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\

  4284.                                         /* Delay after an RCC peripheral clock enabling */ \

  4285.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\

  4286.                                         UNUSED(tmpreg); \

  4287.                                        } while(0)

  4288. 

  4289. #define __HAL_RCC_C2_USART1_CLK_ENABLE()   do { \

  4290.                                         __IO uint32_t tmpreg; \

  4291.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\

  4292.                                         /* Delay after an RCC peripheral clock enabling */ \

  4293.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\

  4294.                                         UNUSED(tmpreg); \

  4295.                                        } while(0)

  4296. 

  4297. #define __HAL_RCC_C2_USART6_CLK_ENABLE()   do { \

  4298.                                         __IO uint32_t tmpreg; \

  4299.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\

  4300.                                         /* Delay after an RCC peripheral clock enabling */ \

  4301.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\

  4302.                                         UNUSED(tmpreg); \

  4303.                                        } while(0)

  4304. 

  4305. #define __HAL_RCC_C2_SPI1_CLK_ENABLE()   do { \

  4306.                                         __IO uint32_t tmpreg; \

  4307.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\

  4308.                                         /* Delay after an RCC peripheral clock enabling */ \

  4309.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\

  4310.                                         UNUSED(tmpreg); \

  4311.                                        } while(0)

  4312. 

  4313. #define __HAL_RCC_C2_SPI4_CLK_ENABLE()   do { \

  4314.                                         __IO uint32_t tmpreg; \

  4315.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\

  4316.                                         /* Delay after an RCC peripheral clock enabling */ \

  4317.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\

  4318.                                         UNUSED(tmpreg); \

  4319.                                        } while(0)

  4320. 

  4321. #define __HAL_RCC_C2_TIM15_CLK_ENABLE()   do { \

  4322.                                         __IO uint32_t tmpreg; \

  4323.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\

  4324.                                         /* Delay after an RCC peripheral clock enabling */ \

  4325.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\

  4326.                                         UNUSED(tmpreg); \

  4327.                                        } while(0)

  4328. 

  4329. #define __HAL_RCC_C2_TIM16_CLK_ENABLE()   do { \

  4330.                                         __IO uint32_t tmpreg; \

  4331.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\

  4332.                                         /* Delay after an RCC peripheral clock enabling */ \

  4333.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\

  4334.                                         UNUSED(tmpreg); \

  4335.                                        } while(0)

  4336. 

  4337. #define __HAL_RCC_C2_TIM17_CLK_ENABLE()   do { \

  4338.                                         __IO uint32_t tmpreg; \

  4339.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\

  4340.                                         /* Delay after an RCC peripheral clock enabling */ \

  4341.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\

  4342.                                         UNUSED(tmpreg); \

  4343.                                        } while(0)

  4344. 

  4345. #define __HAL_RCC_C2_SPI5_CLK_ENABLE()   do { \

  4346.                                         __IO uint32_t tmpreg; \

  4347.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\

  4348.                                         /* Delay after an RCC peripheral clock enabling */ \

  4349.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\

  4350.                                         UNUSED(tmpreg); \

  4351.                                        } while(0)

  4352. 

  4353. #define __HAL_RCC_C2_SAI1_CLK_ENABLE()   do { \

  4354.                                         __IO uint32_t tmpreg; \

  4355.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\

  4356.                                         /* Delay after an RCC peripheral clock enabling */ \

  4357.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\

  4358.                                         UNUSED(tmpreg); \

  4359.                                        } while(0)

  4360. 

  4361. #define __HAL_RCC_C2_SAI2_CLK_ENABLE()   do { \

  4362.                                         __IO uint32_t tmpreg; \

  4363.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\

  4364.                                         /* Delay after an RCC peripheral clock enabling */ \

  4365.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\

  4366.                                         UNUSED(tmpreg); \

  4367.                                        } while(0)

  4368. 

  4369. #define __HAL_RCC_C2_SAI3_CLK_ENABLE()   do { \

  4370.                                         __IO uint32_t tmpreg; \

  4371.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\

  4372.                                         /* Delay after an RCC peripheral clock enabling */ \

  4373.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\

  4374.                                         UNUSED(tmpreg); \

  4375.                                        } while(0)

  4376. 

  4377. #define __HAL_RCC_C2_DFSDM1_CLK_ENABLE()   do { \

  4378.                                         __IO uint32_t tmpreg; \

  4379.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

  4380.                                         /* Delay after an RCC peripheral clock enabling */ \

  4381.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

  4382.                                         UNUSED(tmpreg); \

  4383.                                        } while(0)

  4384. 

  4385. #define __HAL_RCC_C2_HRTIM1_CLK_ENABLE()   do { \

  4386.                                         __IO uint32_t tmpreg; \

  4387.                                         SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\

  4388.                                         /* Delay after an RCC peripheral clock enabling */ \

  4389.                                         tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\

  4390.                                         UNUSED(tmpreg); \

  4391.                                        } while(0)

  4392. 

  4393. #define __HAL_RCC_C2_TIM1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

  4394. #define __HAL_RCC_C2_TIM8_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

  4395. #define __HAL_RCC_C2_USART1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

  4396. #define __HAL_RCC_C2_USART6_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

  4397. #define __HAL_RCC_C2_SPI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

  4398. #define __HAL_RCC_C2_SPI4_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

  4399. #define __HAL_RCC_C2_TIM15_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

  4400. #define __HAL_RCC_C2_TIM16_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

  4401. #define __HAL_RCC_C2_TIM17_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

  4402. #define __HAL_RCC_C2_SPI5_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

  4403. #define __HAL_RCC_C2_SAI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

  4404. #define __HAL_RCC_C2_SAI2_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)

  4405. #define __HAL_RCC_C2_SAI3_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)

  4406. #define __HAL_RCC_C2_DFSDM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

  4407. #define __HAL_RCC_C2_HRTIM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)

  4408. 

  4409. /** @brief  Enable or disable the APB4 peripheral clock.

  4410.   * @note   After reset, the peripheral clock (used for registers read/write access)

  4411.   *         is disabled and the application software has to enable this clock before

  4412.   *         using it.

  4413.   */

  4414. 

  4415. #define __HAL_RCC_C2_SYSCFG_CLK_ENABLE()   do { \

  4416.                                         __IO uint32_t tmpreg; \

  4417.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

  4418.                                         /* Delay after an RCC peripheral clock enabling */ \

  4419.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

  4420.                                         UNUSED(tmpreg); \

  4421.                                        } while(0)

  4422. 

  4423. #define __HAL_RCC_C2_LPUART1_CLK_ENABLE()   do { \

  4424.                                         __IO uint32_t tmpreg; \

  4425.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\

  4426.                                         /* Delay after an RCC peripheral clock enabling */ \

  4427.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\

  4428.                                         UNUSED(tmpreg); \

  4429.                                        } while(0)

  4430. 

  4431. #define __HAL_RCC_C2_SPI6_CLK_ENABLE()   do { \

  4432.                                         __IO uint32_t tmpreg; \

  4433.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\

  4434.                                         /* Delay after an RCC peripheral clock enabling */ \

  4435.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\

  4436.                                         UNUSED(tmpreg); \

  4437.                                        } while(0)

  4438. 

  4439. #define __HAL_RCC_C2_I2C4_CLK_ENABLE()   do { \

  4440.                                         __IO uint32_t tmpreg; \

  4441.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\

  4442.                                         /* Delay after an RCC peripheral clock enabling */ \

  4443.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\

  4444.                                         UNUSED(tmpreg); \

  4445.                                        } while(0)

  4446. 

  4447. #define __HAL_RCC_C2_LPTIM2_CLK_ENABLE()   do { \

  4448.                                         __IO uint32_t tmpreg; \

  4449.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

  4450.                                         /* Delay after an RCC peripheral clock enabling */ \

  4451.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

  4452.                                         UNUSED(tmpreg); \

  4453.                                        } while(0)

  4454. 

  4455. #define __HAL_RCC_C2_LPTIM3_CLK_ENABLE()   do { \

  4456.                                         __IO uint32_t tmpreg; \

  4457.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

  4458.                                         /* Delay after an RCC peripheral clock enabling */ \

  4459.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

  4460.                                         UNUSED(tmpreg); \

  4461.                                        } while(0)

  4462. 

  4463. #define __HAL_RCC_C2_LPTIM4_CLK_ENABLE()   do { \

  4464.                                         __IO uint32_t tmpreg; \

  4465.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

  4466.                                         /* Delay after an RCC peripheral clock enabling */ \

  4467.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

  4468.                                         UNUSED(tmpreg); \

  4469.                                        } while(0)

  4470. 

  4471. #define __HAL_RCC_C2_LPTIM5_CLK_ENABLE()   do { \

  4472.                                         __IO uint32_t tmpreg; \

  4473.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

  4474.                                         /* Delay after an RCC peripheral clock enabling */ \

  4475.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

  4476.                                         UNUSED(tmpreg); \

  4477.                                        } while(0)

  4478. 

  4479. #define __HAL_RCC_C2_COMP12_CLK_ENABLE()   do { \

  4480.                                         __IO uint32_t tmpreg; \

  4481.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\

  4482.                                         /* Delay after an RCC peripheral clock enabling */ \

  4483.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\

  4484.                                         UNUSED(tmpreg); \

  4485.                                        } while(0)

  4486. 

  4487. #define __HAL_RCC_C2_VREF_CLK_ENABLE()   do { \

  4488.                                         __IO uint32_t tmpreg; \

  4489.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\

  4490.                                         /* Delay after an RCC peripheral clock enabling */ \

  4491.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\

  4492.                                         UNUSED(tmpreg); \

  4493.                                        } while(0)

  4494. 

  4495. #define __HAL_RCC_C2_RTC_CLK_ENABLE()   do { \

  4496.                                         __IO uint32_t tmpreg; \

  4497.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

  4498.                                         /* Delay after an RCC peripheral clock enabling */ \

  4499.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

  4500.                                         UNUSED(tmpreg); \

  4501.                                        } while(0)

  4502. 

  4503. #define __HAL_RCC_C2_SAI4_CLK_ENABLE()   do { \

  4504.                                         __IO uint32_t tmpreg; \

  4505.                                         SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\

  4506.                                         /* Delay after an RCC peripheral clock enabling */ \

  4507.                                         tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\

  4508.                                         UNUSED(tmpreg); \

  4509.                                        } while(0)

  4510. 

  4511. 

  4512. 

  4513. #define __HAL_RCC_C2_SYSCFG_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

  4514. #define __HAL_RCC_C2_LPUART1_CLK_DISABLE()          (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

  4515. #define __HAL_RCC_C2_SPI6_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

  4516. #define __HAL_RCC_C2_I2C4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

  4517. #define __HAL_RCC_C2_LPTIM2_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

  4518. #define __HAL_RCC_C2_LPTIM3_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

  4519. #define __HAL_RCC_C2_LPTIM4_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)

  4520. #define __HAL_RCC_C2_LPTIM5_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)

  4521. #define __HAL_RCC_C2_COMP12_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

  4522. #define __HAL_RCC_C2_VREF_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

  4523. #define __HAL_RCC_C2_RTC_CLK_DISABLE()              (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

  4524. #define __HAL_RCC_C2_SAI4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)

  4525. 

  4526. #endif /*DUAL_CORE*/

  4527. 

  4528. /** @brief  Enable or disable the AHB3 peripheral reset.

  4529.   */

  4530. 

  4531. #define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0xFFFFFFFFU)

  4532. #define __HAL_RCC_MDMA_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))

  4533. #define __HAL_RCC_DMA2D_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))

  4534. #if defined(JPEG)

  4535. #define __HAL_RCC_JPGDECRST_FORCE_RESET()     (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))

  4536. #endif /* JPEG */

  4537. #define __HAL_RCC_FMC_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))

  4538. #if defined(QUADSPI)

  4539. #define __HAL_RCC_QSPI_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))

  4540. #endif /*QUADSPI*/

  4541. #if defined(OCTOSPI1)

  4542. #define __HAL_RCC_OSPI1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))

  4543. #endif /*OCTOSPI1*/

  4544. #define __HAL_RCC_SDMMC1_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))

  4545. #if defined(OCTOSPI2)

  4546. #define __HAL_RCC_OSPI2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))

  4547. #endif /*OCTOSPI2*/

  4548. #if defined(OCTOSPIM)

  4549. #define __HAL_RCC_IOMNGR_FORCE_RESET()      (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))

  4550. #endif /*OCTOSPIM*/

  4551. #if defined(OTFDEC1)

  4552. #define __HAL_RCC_OTFDEC1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))

  4553. #endif /*OTFDEC1*/

  4554. #if defined(OTFDEC2)

  4555. #define __HAL_RCC_OTFDEC2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))

  4556. #endif /*OTFDEC2*/

  4557. #if defined(GFXMMU)

  4558. #define __HAL_RCC_GFXMMU_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))

  4559. #endif /*GFXMMU*/

  4560. 

  4561. #define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)

  4562. #define __HAL_RCC_MDMA_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))

  4563. #define __HAL_RCC_DMA2D_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))

  4564. #if defined(JPEG)

  4565. #define __HAL_RCC_JPGDECRST_RELEASE_RESET()   (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))

  4566. #endif /* JPEG */

  4567. #define __HAL_RCC_FMC_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))

  4568. #if defined(QUADSPI)

  4569. #define __HAL_RCC_QSPI_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))

  4570. #endif /*QUADSPI*/

  4571. #if defined(OCTOSPI1)

  4572. #define __HAL_RCC_OSPI1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))

  4573. #endif /*OCTOSPI1*/

  4574. #define __HAL_RCC_SDMMC1_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))

  4575. #if defined(OCTOSPI2)

  4576. #define __HAL_RCC_OSPI2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))

  4577. #endif /*OCTOSPI2*/

  4578. #if defined(OCTOSPIM)

  4579. #define __HAL_RCC_IOMNGR_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))

  4580. #endif /*OCTOSPIM*/

  4581. #if defined(OTFDEC1)

  4582. #define __HAL_RCC_OTFDEC1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))

  4583. #endif /*OTFDEC1*/

  4584. #if defined(OTFDEC2)

  4585. #define __HAL_RCC_OTFDEC2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))

  4586. #endif /*OTFDEC2*/

  4587. #if defined(GFXMMU)

  4588. #define __HAL_RCC_GFXMMU_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))

  4589. #endif /*GFXMMU*/

  4590. 

  4591. 

  4592. 

  4593. /** @brief  Force or release the AHB1 peripheral reset.

  4594.   */

  4595. #define __HAL_RCC_AHB1_FORCE_RESET()             (RCC->AHB1RSTR = 0xFFFFFFFFU)

  4596. #define __HAL_RCC_DMA1_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))

  4597. #define __HAL_RCC_DMA2_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))

  4598. #define __HAL_RCC_ADC12_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))

  4599. #if defined(DUAL_CORE)

  4600. #define __HAL_RCC_ART_FORCE_RESET()              (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))

  4601. #endif /*DUAL_CORE*/

  4602. #if defined(RCC_AHB1RSTR_CRCRST)

  4603. #define __HAL_RCC_CRC_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))

  4604. #endif

  4605. #if defined(ETH)

  4606. #define __HAL_RCC_ETH1MAC_FORCE_RESET()          (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))

  4607. #endif /*ETH*/

  4608. #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))

  4609. #if defined(USB2_OTG_FS)

  4610. #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))

  4611. #endif /*USB2_OTG_FS*/

  4612. 

  4613. #define __HAL_RCC_AHB1_RELEASE_RESET()           (RCC->AHB1RSTR = 0x00U)

  4614. #define __HAL_RCC_DMA1_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))

  4615. #define __HAL_RCC_DMA2_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))

  4616. #define __HAL_RCC_ADC12_RELEASE_RESET()            (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))

  4617. #if defined(DUAL_CORE)

  4618. #define __HAL_RCC_ART_RELEASE_RESET()              (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))

  4619. #endif /*DUAL_CORE*/

  4620. #if defined(RCC_AHB1RSTR_CRCRST)

  4621. #define __HAL_RCC_CRC_RELEASE_RESET()                (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))

  4622. #endif

  4623. #if defined(ETH)

  4624. #define __HAL_RCC_ETH1MAC_RELEASE_RESET()          (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))

  4625. #endif /*ETH*/

  4626. #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))

  4627. #if defined(USB2_OTG_FS)

  4628. #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))

  4629. #endif /*USB2_OTG_FS*/

  4630. 

  4631. /** @brief  Force or release the AHB2 peripheral reset.

  4632.   */

  4633. #define __HAL_RCC_AHB2_FORCE_RESET()           (RCC->AHB2RSTR = 0xFFFFFFFFU)

  4634. #if defined(DCMI) && defined(PSSI)

  4635. #define __HAL_RCC_DCMI_PSSI_FORCE_RESET()        (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))

  4636. #define __HAL_RCC_DCMI_FORCE_RESET()             __HAL_RCC_DCMI_PSSI_FORCE_RESET()  /* for API backward compatibility*/

  4637. #else

  4638. #define __HAL_RCC_DCMI_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))

  4639. #endif /* DCMI && PSSI */

  4640. #define __HAL_RCC_CRYP_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))

  4641. #define __HAL_RCC_HASH_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))

  4642. #define __HAL_RCC_RNG_FORCE_RESET()              (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))

  4643. #define __HAL_RCC_SDMMC2_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))

  4644. #if defined(RCC_AHB2RSTR_HSEMRST)

  4645. #define __HAL_RCC_HSEM_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))

  4646. #endif

  4647. #if defined(BDMA1)

  4648. #define __HAL_RCC_BDMA1_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))

  4649. #endif /*BDMA1*/

  4650. 

  4651. #define __HAL_RCC_AHB2_RELEASE_RESET()           (RCC->AHB2RSTR = 0x00U)

  4652. #if defined(DCMI) && defined(PSSI)

  4653. #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET()        (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))

  4654. #define __HAL_RCC_DCMI_RELEASE_RESET()             __HAL_RCC_DCMI_PSSI_RELEASE_RESET()  /* for API backward compatibility*/

  4655. #else

  4656. #define __HAL_RCC_DCMI_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))

  4657. #endif /* DCMI && PSSI */

  4658. #define __HAL_RCC_CRYP_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))

  4659. #define __HAL_RCC_HASH_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))

  4660. #define __HAL_RCC_RNG_RELEASE_RESET()              (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))

  4661. #define __HAL_RCC_SDMMC2_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))

  4662. #if defined(RCC_AHB2RSTR_HSEMRST)

  4663. #define __HAL_RCC_HSEM_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))

  4664. #endif

  4665. #if defined(BDMA1)

  4666. #define __HAL_RCC_BDMA1_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))

  4667. #endif /*BDMA1*/

  4668. 

  4669. 

  4670. /** @brief  Force or release the AHB4 peripheral reset.

  4671.   */

  4672. 

  4673. #define __HAL_RCC_AHB4_FORCE_RESET()            (RCC->AHB4RSTR = 0xFFFFFFFFU)

  4674. #define __HAL_RCC_GPIOA_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)

  4675. #define __HAL_RCC_GPIOB_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)

  4676. #define __HAL_RCC_GPIOC_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)

  4677. #define __HAL_RCC_GPIOD_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)

  4678. #define __HAL_RCC_GPIOE_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)

  4679. #define __HAL_RCC_GPIOF_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)

  4680. #define __HAL_RCC_GPIOG_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)

  4681. #define __HAL_RCC_GPIOH_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)

  4682. #define __HAL_RCC_GPIOI_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)

  4683. #define __HAL_RCC_GPIOJ_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)

  4684. #define __HAL_RCC_GPIOK_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)

  4685. #if defined(RCC_AHB4RSTR_CRCRST)

  4686. #define __HAL_RCC_CRC_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)

  4687. #endif

  4688. #if defined(BDMA2)

  4689. #define __HAL_RCC_BDMA2_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)

  4690. #define __HAL_RCC_BDMA_FORCE_RESET()            __HAL_RCC_BDMA2_FORCE_RESET()         /* for API backward compatibility*/

  4691. #else

  4692. #define __HAL_RCC_BDMA_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)

  4693. #endif /*BDMA2*/

  4694. #if defined(ADC3)

  4695. #define __HAL_RCC_ADC3_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)

  4696. #endif /*ADC3*/

  4697. #if defined(RCC_AHB4RSTR_HSEMRST)

  4698. #define __HAL_RCC_HSEM_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)

  4699. #endif

  4700. 

  4701. #define __HAL_RCC_AHB4_RELEASE_RESET()          (RCC->AHB4RSTR = 0x00U)

  4702. #define __HAL_RCC_GPIOA_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)

  4703. #define __HAL_RCC_GPIOB_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)

  4704. #define __HAL_RCC_GPIOC_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)

  4705. #define __HAL_RCC_GPIOD_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)

  4706. #define __HAL_RCC_GPIOE_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)

  4707. #define __HAL_RCC_GPIOF_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)

  4708. #define __HAL_RCC_GPIOG_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)

  4709. #define __HAL_RCC_GPIOH_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)

  4710. #define __HAL_RCC_GPIOI_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)

  4711. #define __HAL_RCC_GPIOJ_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)

  4712. #define __HAL_RCC_GPIOK_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)

  4713. #if defined(RCC_AHB4RSTR_CRCRST)

  4714. #define __HAL_RCC_CRC_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)

  4715. #endif

  4716. #if defined(BDMA2)

  4717. #define __HAL_RCC_BDMA2_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)

  4718. #define __HAL_RCC_BDMA_RELEASE_RESET()   __HAL_RCC_BDMA2_RELEASE_RESET()      /* for API backward compatibility*/

  4719. #else

  4720. #define __HAL_RCC_BDMA_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)

  4721. #endif /*BDMA2*/

  4722. #if defined(ADC3)

  4723. #define __HAL_RCC_ADC3_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)

  4724. #endif /*ADC3*/

  4725. #if defined(RCC_AHB4RSTR_HSEMRST)

  4726. #define __HAL_RCC_HSEM_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)

  4727. #endif

  4728. 

  4729. /** @brief  Force or release the APB3 peripheral reset.

  4730.   */

  4731. #define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APB3RSTR = 0xFFFFFFFFU)

  4732. #if defined(LTDC)

  4733. #define __HAL_RCC_LTDC_FORCE_RESET()           (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)

  4734. #endif /* LTDC */

  4735. #if defined(DSI)

  4736. #define __HAL_RCC_DSI_FORCE_RESET()            (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)

  4737. #endif /*DSI*/

  4738. 

  4739. #define __HAL_RCC_APB3_RELEASE_RESET()         (RCC->APB3RSTR = 0x00U)

  4740. #if defined(LTDC)

  4741. #define __HAL_RCC_LTDC_RELEASE_RESET()           (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)

  4742. #endif /* LTDC */

  4743. #if defined(DSI)

  4744. #define __HAL_RCC_DSI_RELEASE_RESET()            (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)

  4745. #endif /*DSI*/

  4746. 

  4747. /** @brief  Force or release the APB1 peripheral reset.

  4748.   */

  4749. #define __HAL_RCC_APB1L_FORCE_RESET()        (RCC->APB1LRSTR = 0xFFFFFFFFU)

  4750. #define __HAL_RCC_APB1H_FORCE_RESET()        (RCC->APB1HRSTR = 0xFFFFFFFFU)

  4751. #define __HAL_RCC_TIM2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)

  4752. #define __HAL_RCC_TIM3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)

  4753. #define __HAL_RCC_TIM4_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)

  4754. #define __HAL_RCC_TIM5_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)

  4755. #define __HAL_RCC_TIM6_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)

  4756. #define __HAL_RCC_TIM7_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)

  4757. #define __HAL_RCC_TIM12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)

  4758. #define __HAL_RCC_TIM13_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)

  4759. #define __HAL_RCC_TIM14_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)

  4760. #define __HAL_RCC_LPTIM1_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)

  4761. #define __HAL_RCC_SPI2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)

  4762. #define __HAL_RCC_SPI3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)

  4763. #define __HAL_RCC_SPDIFRX_FORCE_RESET()        (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)

  4764. #define __HAL_RCC_USART2_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)

  4765. #define __HAL_RCC_USART3_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)

  4766. #define __HAL_RCC_UART4_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)

  4767. #define __HAL_RCC_UART5_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)

  4768. #define __HAL_RCC_I2C1_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)

  4769. #define __HAL_RCC_I2C2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)

  4770. #define __HAL_RCC_I2C3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)

  4771. #define __HAL_RCC_CEC_FORCE_RESET()            (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)

  4772. #define __HAL_RCC_DAC12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)

  4773. #define __HAL_RCC_UART7_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)

  4774. #define __HAL_RCC_UART8_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)

  4775. #define __HAL_RCC_CRS_FORCE_RESET()            (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)

  4776. #define __HAL_RCC_SWPMI1_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)

  4777. #define __HAL_RCC_OPAMP_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)

  4778. #define __HAL_RCC_MDIOS_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)

  4779. #define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)

  4780. 

  4781. #define __HAL_RCC_APB1L_RELEASE_RESET()       (RCC->APB1LRSTR = 0x00U)

  4782. #define __HAL_RCC_APB1H_RELEASE_RESET()       (RCC->APB1HRSTR = 0x00U)

  4783. #define __HAL_RCC_TIM2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)

  4784. #define __HAL_RCC_TIM3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)

  4785. #define __HAL_RCC_TIM4_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)

  4786. #define __HAL_RCC_TIM5_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)

  4787. #define __HAL_RCC_TIM6_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)

  4788. #define __HAL_RCC_TIM7_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)

  4789. #define __HAL_RCC_TIM12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)

  4790. #define __HAL_RCC_TIM13_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)

  4791. #define __HAL_RCC_TIM14_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)

  4792. #define __HAL_RCC_LPTIM1_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)

  4793. #define __HAL_RCC_SPI2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)

  4794. #define __HAL_RCC_SPI3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)

  4795. #define __HAL_RCC_SPDIFRX_RELEASE_RESET()        (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)

  4796. #define __HAL_RCC_USART2_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)

  4797. #define __HAL_RCC_USART3_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)

  4798. #define __HAL_RCC_UART4_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)

  4799. #define __HAL_RCC_UART5_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)

  4800. #define __HAL_RCC_I2C1_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)

  4801. #define __HAL_RCC_I2C2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)

  4802. #define __HAL_RCC_I2C3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)

  4803. #define __HAL_RCC_CEC_RELEASE_RESET()            (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)

  4804. #define __HAL_RCC_DAC12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)

  4805. #define __HAL_RCC_UART7_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)

  4806. #define __HAL_RCC_UART8_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)

  4807. #define __HAL_RCC_CRS_RELEASE_RESET()            (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)

  4808. #define __HAL_RCC_SWPMI1_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)

  4809. #define __HAL_RCC_OPAMP_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)

  4810. #define __HAL_RCC_MDIOS_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)

  4811. #define __HAL_RCC_FDCAN_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)

  4812. 

  4813. /** @brief  Force or release the APB2 peripheral reset.

  4814.   */

  4815. #define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APB2RSTR = 0xFFFFFFFFU)

  4816. #define __HAL_RCC_TIM1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)

  4817. #define __HAL_RCC_TIM8_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)

  4818. #define __HAL_RCC_USART1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)

  4819. #define __HAL_RCC_USART6_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)

  4820. #if defined(UART9)

  4821. #define __HAL_RCC_UART9_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)

  4822. #endif /*UART9*/

  4823. #if defined(USART10)

  4824. #define __HAL_RCC_USART10_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)

  4825. #endif /*USART10*/

  4826. #define __HAL_RCC_SPI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)

  4827. #define __HAL_RCC_SPI4_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)

  4828. #define __HAL_RCC_TIM15_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)

  4829. #define __HAL_RCC_TIM16_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)

  4830. #define __HAL_RCC_TIM17_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)

  4831. #define __HAL_RCC_SPI5_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)

  4832. #define __HAL_RCC_SAI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)

  4833. #define __HAL_RCC_SAI2_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)

  4834. #if defined(SAI3)

  4835. #define __HAL_RCC_SAI3_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)

  4836. #endif /*SAI3*/

  4837. #define __HAL_RCC_DFSDM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)

  4838. #if defined(HRTIM1)

  4839. #define __HAL_RCC_HRTIM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)

  4840. #endif /*HRTIM1*/

  4841. 

  4842. #define __HAL_RCC_APB2_RELEASE_RESET()         (RCC->APB2RSTR = 0x00U)

  4843. #define __HAL_RCC_TIM1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)

  4844. #define __HAL_RCC_TIM8_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)

  4845. #define __HAL_RCC_USART1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)

  4846. #define __HAL_RCC_USART6_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)

  4847. #if defined(UART9)

  4848. #define __HAL_RCC_UART9_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)

  4849. #endif /*UART9*/

  4850. #if defined(USART10)

  4851. #define __HAL_RCC_USART10_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)

  4852. #endif /*USART10*/

  4853. #define __HAL_RCC_SPI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)

  4854. #define __HAL_RCC_SPI4_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)

  4855. #define __HAL_RCC_TIM15_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)

  4856. #define __HAL_RCC_TIM16_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)

  4857. #define __HAL_RCC_TIM17_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)

  4858. #define __HAL_RCC_SPI5_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)

  4859. #define __HAL_RCC_SAI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)

  4860. #define __HAL_RCC_SAI2_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)

  4861. #if defined(SAI3)

  4862. #define __HAL_RCC_SAI3_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)

  4863. #endif /*SAI3*/

  4864. #define __HAL_RCC_DFSDM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)

  4865. #if defined(HRTIM1)

  4866. #define __HAL_RCC_HRTIM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)

  4867. #endif /*HRTIM1*/

  4868. 

  4869. /** @brief  Force or release the APB4 peripheral reset.

  4870.   */

  4871. 

  4872. #define __HAL_RCC_APB4_FORCE_RESET()           (RCC->APB4RSTR = 0xFFFFFFFFU)

  4873. #define __HAL_RCC_SYSCFG_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)

  4874. #define __HAL_RCC_LPUART1_FORCE_RESET()          (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)

  4875. #define __HAL_RCC_SPI6_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)

  4876. #define __HAL_RCC_I2C4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)

  4877. #define __HAL_RCC_LPTIM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)

  4878. #define __HAL_RCC_LPTIM3_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)

  4879. #if defined(LPTIM4)

  4880. #define __HAL_RCC_LPTIM4_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)

  4881. #endif /*LPTIM4*/

  4882. #if defined(LPTIM5)

  4883. #define __HAL_RCC_LPTIM5_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)

  4884. #endif /*LPTIM5*/

  4885. #if defined(DAC2)

  4886. #define __HAL_RCC_DAC2_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)

  4887. #endif /*DAC2*/

  4888. #define __HAL_RCC_COMP12_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)

  4889. #define __HAL_RCC_VREF_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)

  4890. #if defined(SAI4)

  4891. #define __HAL_RCC_SAI4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)

  4892. #endif /*SAI4*/

  4893. #if defined(DTS)

  4894. #define __HAL_RCC_DTS_FORCE_RESET()              (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)

  4895. #endif /*DTS*/

  4896. #if defined(DFSDM2_BASE)

  4897. #define __HAL_RCC_DFSDM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)

  4898. #endif /*DFSDM2*/

  4899. 

  4900. #define __HAL_RCC_APB4_RELEASE_RESET()           (RCC->APB4RSTR = 0x00U)

  4901. #define __HAL_RCC_SYSCFG_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)

  4902. #define __HAL_RCC_LPUART1_RELEASE_RESET()          (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)

  4903. #define __HAL_RCC_SPI6_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)

  4904. #define __HAL_RCC_I2C4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)

  4905. #define __HAL_RCC_LPTIM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)

  4906. #define __HAL_RCC_LPTIM3_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)

  4907. #if defined(LPTIM4)

  4908. #define __HAL_RCC_LPTIM4_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)

  4909. #endif /*LPTIM4*/

  4910. #if defined(LPTIM5)

  4911. #define __HAL_RCC_LPTIM5_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)

  4912. #endif /*LPTIM5*/

  4913. #if defined(RCC_APB4RSTR_DAC2RST)

  4914. #define __HAL_RCC_DAC2_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)

  4915. #endif

  4916. #define __HAL_RCC_COMP12_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)

  4917. #define __HAL_RCC_VREF_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)

  4918. #if defined(SAI4)

  4919. #define __HAL_RCC_SAI4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)

  4920. #endif /*SAI4*/

  4921. #if defined(DTS)

  4922. #define __HAL_RCC_DTS_RELEASE_RESET()              (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)

  4923. #endif /*DTS*/

  4924. #if defined(DFSDM2_BASE)

  4925. #define __HAL_RCC_DFSDM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)

  4926. #endif /*DFSDM2*/

  4927. 

  4928. /** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

  4929.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  4930.   *         power consumption.

  4931.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  4932.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  4933.   */

  4934. 

  4935. 

  4936. #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

  4937. #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))

  4938. #if defined(JPEG)

  4939. #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))

  4940. #endif /* JPEG */

  4941. #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))

  4942. #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()             (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

  4943. #if defined(QUADSPI)

  4944. #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))

  4945. #endif /*QUADSPI*/

  4946. #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))

  4947. #if defined(OCTOSPI1)

  4948. #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))

  4949. #endif /*OCTOSPI1*/

  4950. #if defined(OCTOSPI2)

  4951. #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))

  4952. #endif /*OCTOSPI2*/

  4953. #if defined(OCTOSPIM)

  4954. #define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))

  4955. #endif /*OCTOSPIM*/

  4956. #if defined(OTFDEC1)

  4957. #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))

  4958. #endif /*OTFDEC1*/

  4959. #if defined(OTFDEC2)

  4960. #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))

  4961. #endif /*OTFDEC2*/

  4962. #if defined(GFXMMU)

  4963. #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))

  4964. #endif /*GFXMMU*/

  4965. #if defined(CD_AXISRAM2_BASE)

  4966. #define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))

  4967. #endif

  4968. #if defined(CD_AXISRAM3_BASE)

  4969. #define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))

  4970. #endif

  4971. #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))

  4972. #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))

  4973. #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))

  4974. #if defined(RCC_AHB3LPENR_AXISRAMLPEN)

  4975. #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))

  4976. #define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE

  4977. #else

  4978. #define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE()        (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))

  4979. #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE           __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE  /* For backward compatibility */

  4980. #endif /* RCC_AHB3LPENR_AXISRAMLPEN */

  4981. 

  4982. #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

  4983. #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

  4984. #if defined(JPEG)

  4985. #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))

  4986. #endif /* JPEG */

  4987. #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

  4988. #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()             (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

  4989. #if defined(QUADSPI)

  4990. #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))

  4991. #endif /*QUADSPI*/

  4992. #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

  4993. #if defined(OCTOSPI1)

  4994. #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))

  4995. #endif /*OCTOSPI1*/

  4996. #if defined(OCTOSPI2)

  4997. #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))

  4998. #endif /*OCTOSPI2*/

  4999. #if defined(OCTOSPIM)

  5000. #define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))

  5001. #endif /*OCTOSPIM*/

  5002. #if defined(OTFDEC1)

  5003. #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))

  5004. #endif /*OTFDEC1*/

  5005. #if defined(OTFDEC2)

  5006. #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))

  5007. #endif /*OTFDEC2*/

  5008. #if defined(GFXMMU)

  5009. #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))

  5010. #endif /*GFXMMU*/

  5011. #if defined(CD_AXISRAM2_BASE)

  5012. #define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))

  5013. #endif

  5014. #if defined(CD_AXISRAM3_BASE)

  5015. #define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))

  5016. #endif

  5017. #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

  5018. #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

  5019. #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

  5020. #if defined(RCC_AHB3LPENR_AXISRAMLPEN)

  5021. #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))

  5022. #define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE

  5023. #else

  5024. #define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE()        (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))

  5025. #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE          __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE      /* For backward compatibility */

  5026. #endif  /* RCC_AHB3LPENR_AXISRAMLPEN */

  5027. 

  5028. /** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.

  5029.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5030.   *         power consumption.

  5031.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5032.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5033.   */

  5034. 

  5035. #define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    != 0U)

  5036. #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   != 0U)

  5037. #if defined(JPEG)

  5038. #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  != 0U)

  5039. #endif /* JPEG */

  5040. #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   != 0U)

  5041. #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     != 0U)

  5042. #if defined(QUADSPI)

  5043. #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    != 0U)

  5044. #endif /*QUADSPI*/

  5045. #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  != 0U)

  5046. #if defined(OCTOSPI1)

  5047. #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)    != 0U)

  5048. #endif /*OCTOSPI1*/

  5049. #if defined(OCTOSPI2)

  5050. #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)    != 0U)

  5051. #endif /*OCTOSPI2*/

  5052. #if defined(OCTOSPIM)

  5053. #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN)   != 0U)

  5054. #endif /*OCTOSPIM*/

  5055. #if defined(OTFDEC1)

  5056. #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)

  5057. #endif /*OTFDEC1*/

  5058. #if defined(OTFDEC2)

  5059. #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)

  5060. #endif /*OTFDEC2*/

  5061. #if defined(GFXMMU)

  5062. #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)    != 0U)

  5063. #endif /*GFXMMU*/

  5064. #if defined(CD_AXISRAM2_BASE)

  5065. #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)   != 0U)

  5066. #endif

  5067. #if defined(CD_AXISRAM3_BASE)

  5068. #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)   != 0U)

  5069. #endif

  5070. #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   != 0U)

  5071. #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   != 0U)

  5072. #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    != 0U)

  5073. #if defined(RCC_AHB3LPENR_AXISRAMLPEN)

  5074. #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)

  5075. #else

  5076. #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)

  5077. #endif

  5078. 

  5079. #define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    == 0U)

  5080. #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   == 0U)

  5081. #if defined(JPEG)

  5082. #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  == 0U)

  5083. #endif /* JPEG */

  5084. #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   == 0U)

  5085. #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     == 0U)

  5086. #if defined(QUADSPI)

  5087. #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    == 0U)

  5088. #endif /*QUADSPI*/

  5089. #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  == 0U)

  5090. #if defined(OCTOSPI1)

  5091. #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)  == 0U)

  5092. #endif /*OCTOSPI1*/

  5093. #if defined(OCTOSPI2)

  5094. #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)  == 0U)

  5095. #endif /*OCTOSPI2*/

  5096. #if defined(OCTOSPIM)

  5097. #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)

  5098. #endif /*OCTOSPIM*/

  5099. #if defined(OTFDEC1)

  5100. #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN)  == 0U)

  5101. #endif /*OTFDEC1*/

  5102. #if defined(OTFDEC2)

  5103. #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN)  == 0U)

  5104. #endif /*OTFDEC2*/

  5105. #if defined(GFXMMU)

  5106. #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)  == 0U)

  5107. #endif /*GFXMMU*/

  5108. #if defined(CD_AXISRAM2_BASE)

  5109. #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)  == 0U)

  5110. #endif

  5111. #if defined(CD_AXISRAM3_BASE)

  5112. #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)  == 0U)

  5113. #endif

  5114. #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   == 0U)

  5115. #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   == 0U)

  5116. #define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    == 0U)

  5117. #if defined(RCC_AHB3LPENR_AXISRAMLPEN)

  5118. #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)

  5119. #else

  5120. #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)

  5121. #endif /* RCC_AHB3LPENR_AXISRAMLPEN */

  5122. 

  5123. /** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

  5124.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5125.   *         power consumption.

  5126.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  5127.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  5128.   */

  5129. 

  5130. #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

  5131. #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

  5132. #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()            (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))

  5133. #if defined(RCC_AHB1LPENR_CRCLPEN)

  5134. #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))

  5135. #endif

  5136. #if defined(ETH)

  5137. #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))

  5138. #endif /*ETH*/

  5139. #if defined(DUAL_CORE)

  5140. #define __HAL_RCC_ART_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))

  5141. #endif /*DUAL_CORE*/

  5142. #if defined(ETH)

  5143. #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))

  5144. #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))

  5145. #endif /*ETH*/

  5146. #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))

  5147. #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

  5148. #if defined(USB2_OTG_FS)

  5149. #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))

  5150. #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

  5151. #endif /* USB2_OTG_FS */

  5152. 

  5153. #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

  5154. #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

  5155. #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()            (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

  5156. #if defined(RCC_AHB1LPENR_CRCLPEN)

  5157. #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))

  5158. #endif

  5159. #if defined(ETH)

  5160. #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))

  5161. #endif  /*ETH*/

  5162. #if defined(DUAL_CORE)

  5163. #define __HAL_RCC_ART_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))

  5164. #endif /*DUAL_CORE*/

  5165. #if defined(ETH)

  5166. #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))

  5167. #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))

  5168. #endif  /*ETH*/

  5169. #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

  5170. #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

  5171. #if defined(USB2_OTG_FS)

  5172. #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))

  5173. #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

  5174. #endif /* USB2_OTG_FS */

  5175. 

  5176. /** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.

  5177.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5178.   *         power consumption.

  5179.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5180.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5181.   */

  5182. 

  5183. #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          != 0U)

  5184. #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          != 0U)

  5185. #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         != 0U)

  5186. #if defined(RCC_AHB1LPENR_CRCLPEN)

  5187. #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()                ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))         != 0U)

  5188. #endif

  5189. #if defined(ETH)

  5190. #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       != 0U)

  5191. #endif  /*ETH*/

  5192. #if defined(DUAL_CORE)

  5193. #define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))       != 0U)

  5194. #endif /*DUAL_CORE*/

  5195. #if defined(ETH)

  5196. #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        != 0U)

  5197. #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        != 0U)

  5198. #endif  /*ETH*/

  5199. #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     != 0U)

  5200. #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)

  5201. #if defined(USB2_OTG_FS)

  5202. #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     != 0U)

  5203. #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)

  5204. #endif /* USB2_OTG_FS */

  5205. 

  5206. #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          == 0U)

  5207. #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          == 0U)

  5208. #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         == 0U)

  5209. #if defined(RCC_AHB1LPENR_CRCLPEN)

  5210. #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))           == 0U)

  5211. #endif

  5212. #if defined(ETH)

  5213. #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       == 0U)

  5214. #endif /* ETH */

  5215. #if defined(DUAL_CORE)

  5216. #define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))           == 0U)

  5217. #endif /*DUAL_CORE*/

  5218. #if defined(ETH)

  5219. #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        == 0U)

  5220. #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        == 0U)

  5221. #endif /* ETH */

  5222. #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     == 0U)

  5223. #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)

  5224. #if defined(USB2_OTG_FS)

  5225. #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     == 0U)

  5226. #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)

  5227. #endif /* USB2_OTG_FS */

  5228. 

  5229. 

  5230. /** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

  5231.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5232.   *         power consumption.

  5233.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  5234.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  5235.   */

  5236. 

  5237. #if defined(DCMI) && defined(PSSI)

  5238. #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))

  5239. #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()  /* for API backward compatibility*/

  5240. #else

  5241. #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

  5242. #endif /* DCMI && PSSI */

  5243. #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))

  5244. #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))

  5245. #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()              (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

  5246. #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()           (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))

  5247. #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)

  5248. #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))

  5249. #endif

  5250. #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)

  5251. #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))

  5252. #else

  5253. #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))

  5254. #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */

  5255. #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)

  5256. #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))

  5257. #else

  5258. #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))

  5259. #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */

  5260. #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)

  5261. #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))

  5262. #endif

  5263. 

  5264. #if defined(DCMI) && defined(PSSI)

  5265. #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))

  5266. #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()  /* for API backward compatibility*/

  5267. #else

  5268. #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

  5269. #endif /* DCMI && PSSI */

  5270. #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))

  5271. #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))

  5272. #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()              (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

  5273. #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE()           (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

  5274. #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)

  5275. #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))

  5276. #endif

  5277. #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)

  5278. #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))

  5279. #else

  5280. #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))

  5281. #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */

  5282. #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)

  5283. #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))

  5284. #else

  5285. #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))

  5286. #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */

  5287. #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)

  5288. #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))

  5289. #endif

  5290. 

  5291. /** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.

  5292.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5293.   *         power consumption.

  5294.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5295.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5296.   */

  5297. 

  5298. #if defined(DCMI) && defined(PSSI)

  5299. #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    != 0U)

  5300. #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()  /* for API backward compatibility*/

  5301. #else

  5302. #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    != 0U)

  5303. #endif /* DCMI && PSSI */

  5304. #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    != 0U)

  5305. #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    != 0U)

  5306. #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     != 0U)

  5307. #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  != 0U)

  5308. #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)

  5309. #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)

  5310. #endif

  5311. #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)

  5312. #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)

  5313. #else

  5314. #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)

  5315. #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */

  5316. #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)

  5317. #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)

  5318. #else

  5319. #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)

  5320. #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */

  5321. #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)

  5322. #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)

  5323. #endif /* RCC_AHB2LPENR_D2SRAM3LPEN */

  5324. 

  5325. #if defined(DCMI) && defined(PSSI)

  5326. #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    == 0U)

  5327. #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()  /* for API backward compatibility*/

  5328. #else

  5329. #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    == 0U)

  5330. #endif /* DCMI && PSSI */

  5331. #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    == 0U)

  5332. #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    == 0U)

  5333. #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     == 0U)

  5334. #if defined(RCC_AHB2LPENR_DFSDMDMALPEN)

  5335. #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)

  5336. #endif

  5337. #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  == 0U)

  5338. #if defined(RCC_AHB2LPENR_D2SRAM1LPEN)

  5339. #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)

  5340. #else

  5341. #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)

  5342. #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */

  5343. #if defined(RCC_AHB2LPENR_D2SRAM2LPEN)

  5344. #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)

  5345. #else

  5346. #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)

  5347. #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */

  5348. #if defined(RCC_AHB2LPENR_D2SRAM3LPEN)

  5349. #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)

  5350. #endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/

  5351. 

  5352. 

  5353. /** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

  5354.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5355.   *         power consumption.

  5356.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  5357.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  5358.   */

  5359. 

  5360. #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

  5361. #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)

  5362. #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)

  5363. #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)

  5364. #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)

  5365. #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)

  5366. #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)

  5367. #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)

  5368. #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)

  5369. #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)

  5370. #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)

  5371. #if defined(RCC_AHB4LPENR_CRCLPEN)

  5372. #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)

  5373. #endif

  5374. #if defined(BDMA2)

  5375. #define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)

  5376. #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE  __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/

  5377. #else

  5378. #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)

  5379. #endif /* BDMA2 */

  5380. #if defined(ADC3)

  5381. #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)

  5382. #endif /* ADC3 */

  5383. #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()          (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)

  5384. #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)

  5385. #define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_SRDSRAMLPEN))

  5386. #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/

  5387. #else

  5388. #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))

  5389. #endif /* RCC_AHB4LPENR_SRDSRAMLPEN */

  5390. 

  5391. #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

  5392. #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

  5393. #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

  5394. #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

  5395. #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

  5396. #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

  5397. #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

  5398. #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

  5399. #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)

  5400. #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

  5401. #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

  5402. #if defined(RCC_AHB4LPENR_CRCLPEN)

  5403. #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)

  5404. #endif

  5405. #if defined(BDMA2)

  5406. #define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)

  5407. #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE  __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE  /* For API backward compatibility*/

  5408. #else

  5409. #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

  5410. #endif /*BDMA2*/

  5411. #if defined(ADC3)

  5412. #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)

  5413. #endif /*ADC3*/

  5414. #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE()          (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

  5415. #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)

  5416. #define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))

  5417. #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE

  5418. #else

  5419. #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

  5420. #endif

  5421. 

  5422. 

  5423. /** @brief  Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.

  5424.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5425.   *         power consumption.

  5426.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5427.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5428.   */

  5429. 

  5430. #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   != 0U)

  5431. #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   != 0U)

  5432. #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   != 0U)

  5433. #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   != 0U)

  5434. #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   != 0U)

  5435. #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   != 0U)

  5436. #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   != 0U)

  5437. #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   != 0U)

  5438. #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   != 0U)

  5439. #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   != 0U)

  5440. #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   != 0U)

  5441. #if defined(RCC_AHB4LPENR_CRCLPEN)

  5442. #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     != 0U)

  5443. #endif

  5444. #if defined(BDMA2)

  5445. #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))    != 0U)

  5446. #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/

  5447. #else

  5448. #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    != 0U)

  5449. #endif /*BDMA2*/

  5450. #if defined(ADC3)

  5451. #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    != 0U)

  5452. #endif /*ADC3*/

  5453. #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  != 0U)

  5454. #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)

  5455. #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)

  5456. #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/

  5457. #else

  5458. #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)

  5459. #endif

  5460. 

  5461. #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   == 0U)

  5462. #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   == 0U)

  5463. #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   == 0U)

  5464. #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   == 0U)

  5465. #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   == 0U)

  5466. #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   == 0U)

  5467. #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   == 0U)

  5468. #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   == 0U)

  5469. #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   == 0U)

  5470. #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   == 0U)

  5471. #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   == 0U)

  5472. #if defined(RCC_AHB4LPENR_CRCLPEN)

  5473. #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     == 0U)

  5474. #endif

  5475. #if defined(BDMA2)

  5476. #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))  == 0U)

  5477. #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/

  5478. #else

  5479. #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    == 0U)

  5480. #endif /*BDMA2*/

  5481. #if defined(ADC3)

  5482. #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    == 0U)

  5483. #endif /*ADC3*/

  5484. #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  == 0U)

  5485. #if defined(RCC_AHB4LPENR_SRDSRAMLPEN)

  5486. #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)

  5487. #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/

  5488. #else

  5489. #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)

  5490. #endif

  5491. 

  5492. 

  5493. /** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

  5494.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5495.   *         power consumption.

  5496.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  5497.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  5498.   */

  5499. 

  5500. #if defined(LTDC)

  5501. #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()           (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)

  5502. #endif /* LTDC */

  5503. #if defined(DSI)

  5504. #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()            (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)

  5505. #endif /*DSI*/

  5506. #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE()          (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

  5507. 

  5508. #if defined(LTDC)

  5509. #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()           (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)

  5510. #endif /* LTDC */

  5511. #if defined(DSI)

  5512. #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()            (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)

  5513. #endif /*DSI*/

  5514. #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE()          (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

  5515. 

  5516. 

  5517. /** @brief  Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.

  5518.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5519.   *         power consumption.

  5520.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5521.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5522.   */

  5523. 

  5524. #if defined(LTDC)

  5525. #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  != 0U)

  5526. #endif /* LTDC */

  5527. #if defined(DSI)

  5528. #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()             ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   != 0U)

  5529. #endif /*DSI*/

  5530. #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)

  5531. 

  5532. #if defined(LTDC)

  5533. #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  == 0U)

  5534. #endif /* LTDC */

  5535. #if defined(DSI)

  5536. #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   == 0U)

  5537. #endif /*DSI*/

  5538. #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)

  5539. 

  5540. 

  5541. /** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

  5542.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5543.   *         power consumption.

  5544.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  5545.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  5546.   */

  5547. 

  5548. #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

  5549. #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)

  5550. #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)

  5551. #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)

  5552. #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)

  5553. #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)

  5554. #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)

  5555. #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)

  5556. #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)

  5557. #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)

  5558. 

  5559. #if defined(DUAL_CORE)

  5560. #define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)

  5561. #endif /*DUAL_CORE*/

  5562. 

  5563. #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)

  5564. #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)

  5565. #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)

  5566. #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)

  5567. #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)

  5568. #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)

  5569. #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)

  5570. #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)

  5571. #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)

  5572. #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)

  5573. #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()            (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)

  5574. #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)

  5575. #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)

  5576. #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)

  5577. #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)

  5578. #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)

  5579. #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)

  5580. #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)

  5581. #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)

  5582. 

  5583. 

  5584. #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

  5585. #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

  5586. #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

  5587. #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

  5588. #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

  5589. #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

  5590. #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

  5591. #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

  5592. #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

  5593. #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

  5594. 

  5595. #if defined(DUAL_CORE)

  5596. #define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)

  5597. #endif /*DUAL_CORE*/

  5598. 

  5599. #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

  5600. #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

  5601. #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

  5602. #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

  5603. #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

  5604. #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

  5605. #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

  5606. #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

  5607. #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

  5608. #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

  5609. #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()            (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

  5610. #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

  5611. #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

  5612. #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

  5613. #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()            (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

  5614. #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

  5615. #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

  5616. #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

  5617. #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

  5618. 

  5619. 

  5620. /** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.

  5621.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5622.   *         power consumption.

  5623.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5624.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5625.   */

  5626. 

  5627. #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    != 0U)

  5628. #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    != 0U)

  5629. #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    != 0U)

  5630. #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    != 0U)

  5631. #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    != 0U)

  5632. #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    != 0U)

  5633. #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   != 0U)

  5634. #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   != 0U)

  5635. #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   != 0U)

  5636. #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  != 0U)

  5637. #if defined(DUAL_CORE)

  5638. #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   != 0U)

  5639. #endif /*DUAL_CORE*/

  5640. #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    != 0U)

  5641. #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    != 0U)

  5642. #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)

  5643. #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  != 0U)

  5644. #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  != 0U)

  5645. #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   != 0U)

  5646. #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   != 0U)

  5647. #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    != 0U)

  5648. #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    != 0U)

  5649. #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    != 0U)

  5650. #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     != 0U)

  5651. #define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   != 0U)

  5652. #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   != 0U)

  5653. #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   != 0U)

  5654. #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     != 0U)

  5655. #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   != 0U)

  5656. #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   != 0U)

  5657. #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   != 0U)

  5658. #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   != 0U)

  5659. 

  5660. #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    == 0U)

  5661. #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    == 0U)

  5662. #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    == 0U)

  5663. #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    == 0U)

  5664. #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    == 0U)

  5665. #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    == 0U)

  5666. #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   == 0U)

  5667. #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   == 0U)

  5668. #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   == 0U)

  5669. #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  == 0U)

  5670. #if defined(DUAL_CORE)

  5671. #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   == 0U)

  5672. #endif /*DUAL_CORE*/

  5673. #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    == 0U)

  5674. #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    == 0U)

  5675. #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)

  5676. #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  == 0U)

  5677. #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  == 0U)

  5678. #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   == 0U)

  5679. #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   == 0U)

  5680. #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    == 0U)

  5681. #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    == 0U)

  5682. #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    == 0U)

  5683. #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     == 0U)

  5684. #define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   == 0U)

  5685. #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   == 0U)

  5686. #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   == 0U)

  5687. #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     == 0U)

  5688. #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   == 0U)

  5689. #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   == 0U)

  5690. #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   == 0U)

  5691. #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   == 0U)

  5692. 

  5693. 

  5694. /** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

  5695.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5696.   *         power consumption.

  5697.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  5698.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  5699.   */

  5700. 

  5701. #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

  5702. #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)

  5703. #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)

  5704. #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)

  5705. #if defined(UART9)

  5706. #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)

  5707. #endif /*UART9*/

  5708. #if defined(USART10)

  5709. #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE()        (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)

  5710. #endif /*USART10*/

  5711. #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)

  5712. #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)

  5713. #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)

  5714. #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)

  5715. #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)

  5716. #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)

  5717. #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)

  5718. #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)

  5719. #if defined(SAI3)

  5720. #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)

  5721. #endif /*SAI3*/

  5722. #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)

  5723. #if defined(HRTIM1)

  5724. #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)

  5725. #endif /*HRTIM1*/

  5726. 

  5727. #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

  5728. #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

  5729. #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

  5730. #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

  5731. #if defined(UART9)

  5732. #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)

  5733. #endif /*UART9*/

  5734. #if defined(USART10)

  5735. #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)

  5736. #endif /*USART10*/

  5737. #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

  5738. #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

  5739. #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

  5740. #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

  5741. #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

  5742. #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

  5743. #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

  5744. #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)

  5745. #if defined(SAI3)

  5746. #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)

  5747. #endif /*SAI3*/

  5748. #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

  5749. #if defined(HRTIM1)

  5750. #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)

  5751. #endif /*HRTIM1*/

  5752. 

  5753. 

  5754. /** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.

  5755.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5756.   *         power consumption.

  5757.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5758.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5759.   */

  5760. 

  5761. #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   != 0U)

  5762. #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   != 0U)

  5763. #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)

  5764. #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)

  5765. #if defined(UART9)

  5766. #define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)

  5767. #endif /*UART9*/

  5768. #if defined(USART10)

  5769. #define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)

  5770. #endif /*USART10*/

  5771. #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   != 0U)

  5772. #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   != 0U)

  5773. #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  != 0U)

  5774. #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  != 0U)

  5775. #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  != 0U)

  5776. #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   != 0U)

  5777. #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   != 0U)

  5778. #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   != 0U)

  5779. #if defined(SAI3)

  5780. #define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   != 0U)

  5781. #endif /*SAI3*/

  5782. #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)

  5783. #if defined(HRTIM1)

  5784. #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  != 0U)

  5785. #endif /*HRTIM1*/

  5786. 

  5787. #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   == 0U)

  5788. #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   == 0U)

  5789. #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)

  5790. #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)

  5791. #if defined(UART9)

  5792. #define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)

  5793. #endif /*UART9*/

  5794. #if defined(USART10)

  5795. #define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)

  5796. #endif /*USART10*/

  5797. #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   == 0U)

  5798. #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   == 0U)

  5799. #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  == 0U)

  5800. #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  == 0U)

  5801. #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  == 0U)

  5802. #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   == 0U)

  5803. #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   == 0U)

  5804. #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   == 0U)

  5805. #if defined(SAI3)

  5806. #define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   == 0U)

  5807. #endif /*SAI3*/

  5808. #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)

  5809. #if defined(HRTIM1)

  5810. #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  == 0U)

  5811. #endif /*HRTIM1*/

  5812. 

  5813. /** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

  5814.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5815.   *         power consumption.

  5816.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  5817.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  5818.   */

  5819. 

  5820. #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

  5821. #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()          (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)

  5822. #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)

  5823. #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)

  5824. #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)

  5825. #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)

  5826. #if defined(LPTIM4)

  5827. #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)

  5828. #endif /*LPTIM4*/

  5829. #if defined(LPTIM5)

  5830. #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)

  5831. #endif /*LPTIM5*/

  5832. #if defined(DAC2)

  5833. #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)

  5834. #endif /*DAC2*/

  5835. #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)

  5836. #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)

  5837. #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)

  5838. #if defined(SAI4)

  5839. #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)

  5840. #endif /*SAI4*/

  5841. #if defined(DTS)

  5842. #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)

  5843. #endif /*DTS*/

  5844. #if defined(DFSDM2_BASE)

  5845. #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)

  5846. #endif /*DFSDM2*/

  5847. 

  5848. #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

  5849. #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

  5850. #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

  5851. #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

  5852. #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

  5853. #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

  5854. #if defined(LPTIM4)

  5855. #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)

  5856. #endif /*LPTIM4*/

  5857. #if defined(LPTIM5)

  5858. #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)

  5859. #endif /*LPTIM5*/

  5860. #if defined(DAC2)

  5861. #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)

  5862. #endif /*DAC2*/

  5863. #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

  5864. #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

  5865. #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

  5866. #if defined(SAI4)

  5867. #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)

  5868. #endif /*SAI4*/

  5869. #if defined(DTS)

  5870. #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)

  5871. #endif /*DTS*/

  5872. #if defined(DFSDM2_BASE)

  5873. #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)

  5874. #endif /*DFSDM2*/

  5875. 

  5876. 

  5877. /** @brief  Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.

  5878.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5879.   *         power consumption.

  5880.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5881.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5882.   */

  5883. 

  5884. #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  != 0U)

  5885. #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)

  5886. #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    != 0U)

  5887. #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    != 0U)

  5888. #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  != 0U)

  5889. #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  != 0U)

  5890. #if defined(LPTIM4)

  5891. #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  != 0U)

  5892. #endif /*LPTIM4*/

  5893. #if defined(LPTIM5)

  5894. #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  != 0U)

  5895. #endif /*LPTIM5*/

  5896. #if defined(DAC2)

  5897. #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  != 0U)

  5898. #endif /*DAC2*/

  5899. #define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  != 0U)

  5900. #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    != 0U)

  5901. #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  != 0U)

  5902. #if defined(SAI4)

  5903. #define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    != 0U)

  5904. #endif /*SAI4*/

  5905. #if defined(DTS)

  5906. #define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    != 0U)

  5907. #endif /*DTS*/

  5908. #if defined(DFSDM2_BASE)

  5909. #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)

  5910. #endif /*DFSDM2*/

  5911. 

  5912. #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  == 0U)

  5913. #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)

  5914. #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    == 0U)

  5915. #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    == 0U)

  5916. #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  == 0U)

  5917. #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  == 0U)

  5918. #if defined(LPTIM4)

  5919. #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  == 0U)

  5920. #endif /*LPTIM4*/

  5921. #if defined(LPTIM5)

  5922. #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  == 0U)

  5923. #endif /*LPTIM5*/

  5924. #if defined(DAC2)

  5925. #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  == 0U)

  5926. #endif /*DAC2*/

  5927. #define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  == 0U)

  5928. #define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    == 0U)

  5929. #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  == 0U)

  5930. #if defined(SAI4)

  5931. #define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    == 0U)

  5932. #endif /*SAI4*/

  5933. #if defined(DTS)

  5934. #define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    == 0U)

  5935. #endif /*DTS*/

  5936. #if defined(DFSDM2_BASE)

  5937. #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)

  5938. #endif /*DFSDM2*/

  5939. 

  5940. 

  5941. #if defined(DUAL_CORE)

  5942. 

  5943. /** @brief  Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.

  5944.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5945.   *         power consumption.

  5946.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  5947.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  5948.   */

  5949. #define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

  5950. #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))

  5951. #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))

  5952. #define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))

  5953. #define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

  5954. #define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))

  5955. #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))

  5956. #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))

  5957. #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))

  5958. #define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))

  5959. #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))

  5960. 

  5961. 

  5962. #define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

  5963. #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

  5964. #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))

  5965. #define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

  5966. #define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

  5967. #define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))

  5968. #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

  5969. #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

  5970. #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

  5971. #define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

  5972. #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))

  5973. 

  5974. 

  5975. 

  5976. /** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

  5977.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  5978.   *         power consumption.

  5979.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  5980.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  5981.   */

  5982. 

  5983. #define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

  5984. #define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

  5985. #define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE()            (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))

  5986. #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))

  5987. #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))

  5988. #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))

  5989. #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))

  5990. #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

  5991. #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))

  5992. #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

  5993. 

  5994. #define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

  5995. #define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

  5996. #define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE()            (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

  5997. #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))

  5998. #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))

  5999. #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))

  6000. #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

  6001. #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

  6002. #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))

  6003. #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

  6004. 

  6005. /** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

  6006.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6007.   *         power consumption.

  6008.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6009.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6010.   */

  6011. 

  6012. #define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

  6013. #define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))

  6014. #define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))

  6015. #define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE()              (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

  6016. #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))

  6017. #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))

  6018. #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))

  6019. #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))

  6020. 

  6021. #define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

  6022. #define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))

  6023. #define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))

  6024. #define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE()              (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

  6025. #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

  6026. #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))

  6027. #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))

  6028. #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))

  6029. 

  6030. /** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

  6031.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6032.   *         power consumption.

  6033.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6034.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6035.   */

  6036. 

  6037. #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

  6038. #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)

  6039. #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)

  6040. #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)

  6041. #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)

  6042. #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)

  6043. #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)

  6044. #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)

  6045. #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)

  6046. #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)

  6047. #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)

  6048. #define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)

  6049. #define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)

  6050. #define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)

  6051. #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)

  6052. #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))

  6053. 

  6054. #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

  6055. #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

  6056. #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

  6057. #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

  6058. #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

  6059. #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

  6060. #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

  6061. #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

  6062. #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)

  6063. #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

  6064. #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

  6065. #define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)

  6066. #define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

  6067. #define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)

  6068. #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

  6069. #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

  6070. 

  6071. /** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

  6072.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6073.   *         power consumption.

  6074.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6075.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6076.   */

  6077. 

  6078. #define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE()           (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)

  6079. #define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE()            (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)

  6080. #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

  6081. 

  6082. #define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE()           (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)

  6083. #define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE()            (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)

  6084. #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

  6085. 

  6086. /** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

  6087.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6088.   *         power consumption.

  6089.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6090.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6091.   */

  6092. 

  6093. #define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

  6094. #define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)

  6095. #define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)

  6096. #define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)

  6097. #define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)

  6098. #define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)

  6099. #define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)

  6100. #define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)

  6101. #define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)

  6102. #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)

  6103. #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)

  6104. #define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)

  6105. #define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)

  6106. #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)

  6107. #define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)

  6108. #define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)

  6109. #define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)

  6110. #define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)

  6111. #define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)

  6112. #define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)

  6113. #define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)

  6114. #define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE()            (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)

  6115. #define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)

  6116. #define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)

  6117. #define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)

  6118. #define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE()            (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)

  6119. #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)

  6120. #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)

  6121. #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)

  6122. #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)

  6123. 

  6124. 

  6125. #define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

  6126. #define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

  6127. #define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

  6128. #define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

  6129. #define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

  6130. #define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

  6131. #define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

  6132. #define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

  6133. #define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

  6134. #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

  6135. #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)

  6136. #define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

  6137. #define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

  6138. #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

  6139. #define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

  6140. #define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

  6141. #define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

  6142. #define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

  6143. #define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

  6144. #define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

  6145. #define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

  6146. #define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE()            (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

  6147. #define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

  6148. #define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

  6149. #define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

  6150. #define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE()            (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

  6151. #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

  6152. #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

  6153. #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

  6154. #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

  6155. 

  6156. /** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

  6157.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6158.   *         power consumption.

  6159.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6160.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6161.   */

  6162. 

  6163. #define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

  6164. #define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)

  6165. #define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)

  6166. #define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)

  6167. #define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)

  6168. #define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)

  6169. #define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)

  6170. #define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)

  6171. #define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)

  6172. #define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)

  6173. #define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)

  6174. #define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)

  6175. #define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)

  6176. #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)

  6177. #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)

  6178. 

  6179. #define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

  6180. #define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

  6181. #define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

  6182. #define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

  6183. #define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

  6184. #define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

  6185. #define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

  6186. #define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

  6187. #define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

  6188. #define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

  6189. #define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

  6190. #define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)

  6191. #define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)

  6192. #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

  6193. #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)

  6194. 

  6195. /** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

  6196.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6197.   *         power consumption.

  6198.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6199.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6200.   */

  6201. 

  6202. #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

  6203. #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)

  6204. #define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)

  6205. #define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)

  6206. #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)

  6207. #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)

  6208. #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)

  6209. #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)

  6210. #define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)

  6211. #define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)

  6212. #define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)

  6213. #define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE()              (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)

  6214. 

  6215. 

  6216. #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

  6217. #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

  6218. #define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

  6219. #define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

  6220. #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

  6221. #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

  6222. #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)

  6223. #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)

  6224. #define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

  6225. #define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

  6226. #define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)

  6227. #define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE()              (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

  6228. 

  6229. /** @brief  Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.

  6230.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6231.   *         power consumption.

  6232.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  6233.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  6234.   */

  6235. 

  6236. 

  6237. #define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

  6238. #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))

  6239. #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))

  6240. #define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))

  6241. #define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

  6242. #define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))

  6243. #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))

  6244. #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))

  6245. #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))

  6246. #define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))

  6247. #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))

  6248. 

  6249. 

  6250. #define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

  6251. #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

  6252. #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))

  6253. #define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

  6254. #define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

  6255. #define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))

  6256. #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

  6257. #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

  6258. #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

  6259. #define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

  6260. #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))

  6261. 

  6262. 

  6263. 

  6264. /** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

  6265.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6266.   *         power consumption.

  6267.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6268.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6269.   */

  6270. 

  6271. #define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

  6272. #define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

  6273. #define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE()            (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))

  6274. #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))

  6275. #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))

  6276. #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))

  6277. #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))

  6278. #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

  6279. #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))

  6280. #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

  6281. 

  6282. #define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

  6283. #define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

  6284. #define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE()            (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

  6285. #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))

  6286. #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))

  6287. #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))

  6288. #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

  6289. #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

  6290. #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))

  6291. #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

  6292. 

  6293. /** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

  6294.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6295.   *         power consumption.

  6296.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6297.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6298.   */

  6299. 

  6300. #define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

  6301. #define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))

  6302. #define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))

  6303. #define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE()              (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

  6304. #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))

  6305. #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))

  6306. #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))

  6307. #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))

  6308. 

  6309. #define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

  6310. #define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))

  6311. #define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))

  6312. #define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE()              (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

  6313. #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

  6314. #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))

  6315. #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))

  6316. #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))

  6317. 

  6318. /** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

  6319.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6320.   *         power consumption.

  6321.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6322.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6323.   */

  6324. 

  6325. #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

  6326. #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)

  6327. #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)

  6328. #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)

  6329. #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)

  6330. #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)

  6331. #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)

  6332. #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)

  6333. #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)

  6334. #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)

  6335. #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)

  6336. #define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)

  6337. #define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)

  6338. #define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)

  6339. #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)

  6340. #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))

  6341. 

  6342. #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

  6343. #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

  6344. #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

  6345. #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

  6346. #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

  6347. #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

  6348. #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

  6349. #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

  6350. #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)

  6351. #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

  6352. #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

  6353. #define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)

  6354. #define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

  6355. #define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)

  6356. #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

  6357. #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

  6358. 

  6359. /** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

  6360.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6361.   *         power consumption.

  6362.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6363.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6364.   */

  6365. 

  6366. #define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE()           (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)

  6367. #define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE()            (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)

  6368. #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

  6369. 

  6370. #define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE()           (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)

  6371. #define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE()            (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)

  6372. #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

  6373. 

  6374. /** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

  6375.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6376.   *         power consumption.

  6377.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6378.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6379.   */

  6380. 

  6381. #define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

  6382. #define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)

  6383. #define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)

  6384. #define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)

  6385. #define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)

  6386. #define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)

  6387. #define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)

  6388. #define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)

  6389. #define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)

  6390. #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)

  6391. #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)

  6392. #define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)

  6393. #define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)

  6394. #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)

  6395. #define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)

  6396. #define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)

  6397. #define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)

  6398. #define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)

  6399. #define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)

  6400. #define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)

  6401. #define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)

  6402. #define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE()            (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)

  6403. #define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)

  6404. #define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)

  6405. #define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)

  6406. #define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE()            (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)

  6407. #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)

  6408. #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)

  6409. #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)

  6410. #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)

  6411. 

  6412. 

  6413. #define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

  6414. #define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

  6415. #define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

  6416. #define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

  6417. #define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

  6418. #define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

  6419. #define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

  6420. #define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

  6421. #define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

  6422. #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

  6423. #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)

  6424. #define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

  6425. #define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

  6426. #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

  6427. #define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

  6428. #define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

  6429. #define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

  6430. #define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

  6431. #define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

  6432. #define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

  6433. #define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

  6434. #define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE()            (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

  6435. #define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

  6436. #define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

  6437. #define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

  6438. #define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE()            (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

  6439. #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

  6440. #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

  6441. #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

  6442. #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

  6443. 

  6444. /** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

  6445.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6446.   *         power consumption.

  6447.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6448.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6449.   */

  6450. 

  6451. #define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

  6452. #define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)

  6453. #define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)

  6454. #define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)

  6455. #define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)

  6456. #define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)

  6457. #define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)

  6458. #define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)

  6459. #define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)

  6460. #define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)

  6461. #define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)

  6462. #define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)

  6463. #define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)

  6464. #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)

  6465. #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)

  6466. 

  6467. #define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

  6468. #define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

  6469. #define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

  6470. #define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

  6471. #define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

  6472. #define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

  6473. #define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

  6474. #define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

  6475. #define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

  6476. #define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

  6477. #define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

  6478. #define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)

  6479. #define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)

  6480. #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

  6481. #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)

  6482. 

  6483. /** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

  6484.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  6485.   *         power consumption.

  6486.   * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

  6487.   * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

  6488.   */

  6489. 

  6490. #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

  6491. #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)

  6492. #define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)

  6493. #define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)

  6494. #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)

  6495. #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)

  6496. #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)

  6497. #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)

  6498. #define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)

  6499. #define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)

  6500. #define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)

  6501. #define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE()              (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)

  6502. 

  6503. #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

  6504. #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

  6505. #define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

  6506. #define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

  6507. #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

  6508. #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

  6509. #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)

  6510. #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)

  6511. #define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

  6512. #define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

  6513. #define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)

  6514. #define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE()              (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

  6515. 

  6516. #endif /*DUAL_CORE*/

  6517. 

  6518. #if defined(DUAL_CORE)

  6519. /** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN

  6520.   * @note   After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP

  6521.   */

  6522. #else

  6523. /** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN

  6524.   * @note   After reset (default config), peripheral clock is disabled when CPU is in CSTOP

  6525.   */

  6526. #endif /*DUAL_CORE*/

  6527. 

  6528. #if defined(RCC_D3AMR_BDMAAMEN)

  6529. #define __HAL_RCC_BDMA_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)

  6530. #endif

  6531. #if defined(RCC_D3AMR_LPUART1AMEN)

  6532. #define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)

  6533. #endif

  6534. #if defined(RCC_D3AMR_SPI6AMEN)

  6535. #define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)

  6536. #endif

  6537. #if defined(RCC_D3AMR_I2C4AMEN)

  6538. #define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)

  6539. #endif

  6540. #if defined(RCC_D3AMR_LPTIM2AMEN)

  6541. #define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)

  6542. #endif

  6543. #if defined(RCC_D3AMR_LPTIM3AMEN)

  6544. #define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)

  6545. #endif

  6546. #if defined(LPTIM4)

  6547. #define __HAL_RCC_LPTIM4_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)

  6548. #endif

  6549. #if defined(LPTIM5)

  6550. #define __HAL_RCC_LPTIM5_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)

  6551. #endif

  6552. #if defined(RCC_D3AMR_COMP12AMEN)

  6553. #define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)

  6554. #endif

  6555. #if defined(RCC_D3AMR_VREFAMEN)

  6556. #define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)

  6557. #endif

  6558. #if defined(RCC_D3AMR_RTCAMEN)

  6559. #define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)

  6560. #endif

  6561. #if defined(RCC_D3AMR_CRCAMEN)

  6562. #define __HAL_RCC_CRC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)

  6563. #endif

  6564. #if defined(SAI4)

  6565. #define __HAL_RCC_SAI4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)

  6566. #endif

  6567. #if defined(ADC3)

  6568. #define __HAL_RCC_ADC3_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)

  6569. #endif

  6570. #if defined(RCC_D3AMR_BKPRAMAMEN)

  6571. #define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)

  6572. #endif

  6573. #if defined(RCC_D3AMR_SRAM4AMEN)

  6574. #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)

  6575. #endif

  6576. 

  6577. #if defined(BDMA2)

  6578. #define __HAL_RCC_BDMA2_CLKAM_ENABLE()            (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)

  6579. #endif

  6580. #if defined(RCC_SRDAMR_GPIOAMEN)

  6581. #define __HAL_RCC_GPIO_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)

  6582. #endif

  6583. #if defined(RCC_SRDAMR_LPUART1AMEN)

  6584. #define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)

  6585. #endif

  6586. #if defined(RCC_SRDAMR_SPI6AMEN)

  6587. #define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)

  6588. #endif

  6589. #if defined(RCC_SRDAMR_I2C4AMEN)

  6590. #define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)

  6591. #endif

  6592. #if defined(RCC_SRDAMR_LPTIM2AMEN)

  6593. #define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)

  6594. #endif

  6595. #if defined(RCC_SRDAMR_LPTIM3AMEN)

  6596. #define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)

  6597. #endif

  6598. #if defined(DAC2)

  6599. #define __HAL_RCC_DAC2_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)

  6600. #endif

  6601. #if defined(RCC_SRDAMR_COMP12AMEN)

  6602. #define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)

  6603. #endif

  6604. #if defined(RCC_SRDAMR_VREFAMEN)

  6605. #define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)

  6606. #endif

  6607. #if defined(RCC_SRDAMR_RTCAMEN)

  6608. #define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)

  6609. #endif

  6610. #if defined(RCC_SRDAMR_DTSAMEN)

  6611. #define __HAL_RCC_DTS_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)

  6612. #endif

  6613. #if defined(DFSDM2_BASE)

  6614. #define __HAL_RCC_DFSDM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)

  6615. #endif

  6616. #if defined(RCC_SRDAMR_BKPRAMAMEN)

  6617. #define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)

  6618. #endif

  6619. #if defined(RCC_SRDAMR_SRDSRAMAMEN)

  6620. #define __HAL_RCC_SRDSRAM_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)

  6621. #endif

  6622. 

  6623. #if defined(RCC_D3AMR_BDMAAMEN)

  6624. #define __HAL_RCC_BDMA_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)

  6625. #endif

  6626. #if defined(RCC_D3AMR_LPUART1AMEN)

  6627. #define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)

  6628. #endif

  6629. #if defined(RCC_D3AMR_SPI6AMEN)

  6630. #define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)

  6631. #endif

  6632. #if defined(RCC_D3AMR_I2C4AMEN)

  6633. #define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)

  6634. #endif

  6635. #if defined(RCC_D3AMR_LPTIM2AMEN)

  6636. #define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)

  6637. #endif

  6638. #if defined(RCC_D3AMR_LPTIM3AMEN)

  6639. #define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)

  6640. #endif

  6641. #if defined(LPTIM4)

  6642. #define __HAL_RCC_LPTIM4_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)

  6643. #endif

  6644. #if defined(LPTIM5)

  6645. #define __HAL_RCC_LPTIM5_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)

  6646. #endif

  6647. #if defined(RCC_D3AMR_COMP12AMEN)

  6648. #define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)

  6649. #endif

  6650. #if defined(RCC_D3AMR_VREFAMEN)

  6651. #define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)

  6652. #endif

  6653. #if defined(RCC_D3AMR_RTCAMEN)

  6654. #define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)

  6655. #endif

  6656. #if defined(RCC_D3AMR_CRCAMEN)

  6657. #define __HAL_RCC_CRC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)

  6658. #endif

  6659. #if defined(SAI4)

  6660. #define __HAL_RCC_SAI4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)

  6661. #endif

  6662. #if defined(ADC3)

  6663. #define __HAL_RCC_ADC3_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)

  6664. #endif

  6665. #if defined(RCC_D3AMR_BKPRAMAMEN)

  6666. #define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)

  6667. #endif

  6668. #if defined(RCC_D3AMR_SRAM4AMEN)

  6669. #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE()          (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)

  6670. #endif

  6671. 

  6672. #if defined(BDMA2)

  6673. #define __HAL_RCC_BDMA2_CLKAM_DISABLE()            (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)

  6674. #endif

  6675. #if defined(RCC_SRDAMR_GPIOAMEN)

  6676. #define __HAL_RCC_GPIO_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)

  6677. #endif

  6678. #if defined(RCC_SRDAMR_LPUART1AMEN)

  6679. #define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)

  6680. #endif

  6681. #if defined(RCC_SRDAMR_SPI6AMEN)

  6682. #define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)

  6683. #endif

  6684. #if defined(RCC_SRDAMR_I2C4AMEN)

  6685. #define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)

  6686. #endif

  6687. #if defined(RCC_SRDAMR_LPTIM2AMEN)

  6688. #define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)

  6689. #endif

  6690. #if defined(RCC_SRDAMR_LPTIM3AMEN)

  6691. #define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)

  6692. #endif

  6693. #if defined(RCC_SRDAMR_DAC2AMEN)

  6694. #define __HAL_RCC_DAC2_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)

  6695. #endif

  6696. #if defined(RCC_SRDAMR_COMP12AMEN)

  6697. #define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)

  6698. #endif

  6699. #if defined(RCC_SRDAMR_VREFAMEN)

  6700. #define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)

  6701. #endif

  6702. #if defined(RCC_SRDAMR_RTCAMEN)

  6703. #define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)

  6704. #endif

  6705. #if defined(RCC_SRDAMR_DTSAMEN)

  6706. #define __HAL_RCC_DTS_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)

  6707. #endif

  6708. #if defined(DFSDM2_BASE)

  6709. #define __HAL_RCC_DFSDM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)

  6710. #endif

  6711. #if defined(RCC_SRDAMR_BKPRAMAMEN)

  6712. #define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)

  6713. #endif

  6714. #if defined(RCC_SRDAMR_SRDSRAMAMEN)

  6715. #define __HAL_RCC_SRDSRAM_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)

  6716. #endif

  6717. 

  6718. 

  6719. #if defined(RCC_CKGAENR_AXICKG)

  6720.     /** @brief  Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).

  6721.   * @note

  6722.   * @note

  6723.   * @note

  6724.   * @param

  6725.   * @note

  6726.   */

  6727. 

  6728. #define __HAL_RCC_AXI_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)

  6729. #define __HAL_RCC_AHB_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)

  6730. #define __HAL_RCC_CPU_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)

  6731. #define __HAL_RCC_SDMMC_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)

  6732. #define __HAL_RCC_MDMA_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)

  6733. #define __HAL_RCC_DMA2D_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)

  6734. #define __HAL_RCC_LTDC_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)

  6735. #define __HAL_RCC_GFXMMUM_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)

  6736. #define __HAL_RCC_AHB12_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)

  6737. #define __HAL_RCC_AHB34_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)

  6738. #define __HAL_RCC_FLIFT_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)

  6739. #define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)

  6740. #define __HAL_RCC_FMC_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)

  6741. #define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)

  6742. #define __HAL_RCC_AXIRAM1_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)

  6743. #define __HAL_RCC_AXIRAM2_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)

  6744. #define __HAL_RCC_AXIRAM3_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)

  6745. #define __HAL_RCC_GFXMMUS_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)

  6746. #define __HAL_RCC_ECCRAM_CLKGA_ENABLE()          (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)

  6747. #define __HAL_RCC_EXTI_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)

  6748. #define __HAL_RCC_JTAG_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)

  6749. 

  6750. 

  6751. #define __HAL_RCC_AXI_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)

  6752. #define __HAL_RCC_AHB_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)

  6753. #define __HAL_RCC_CPU_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)

  6754. #define __HAL_RCC_SDMMC_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)

  6755. #define __HAL_RCC_MDMA_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)

  6756. #define __HAL_RCC_DMA2D_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)

  6757. #define __HAL_RCC_LTDC_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)

  6758. #define __HAL_RCC_GFXMMUM_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)

  6759. #define __HAL_RCC_AHB12_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)

  6760. #define __HAL_RCC_AHB34_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)

  6761. #define __HAL_RCC_FLIFT_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)

  6762. #define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)

  6763. #define __HAL_RCC_FMC_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)

  6764. #define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)

  6765. #define __HAL_RCC_AXIRAM1_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)

  6766. #define __HAL_RCC_AXIRAM2_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)

  6767. #define __HAL_RCC_AXIRAM3_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)

  6768. #define __HAL_RCC_GFXMMUS_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)

  6769. #define __HAL_RCC_ECCRAM_CLKGA_DISABLE()          (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)

  6770. #define __HAL_RCC_EXTI_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)

  6771. #define __HAL_RCC_JTAG_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)

  6772. 

  6773. #endif /* RCC_CKGAENR_AXICKG */

  6774. 

  6775. 

  6776. 

  6777. 

  6778. /** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).

  6779.   * @note     After enabling the HSI, the application software should wait on

  6780.   *           HSIRDY flag to be set indicating that HSI clock is stable and can

  6781.   *           be used to clock the PLL and/or system clock.

  6782.   * @note     HSI can not be stopped if it is used directly or through the PLL

  6783.   *           as system clock. In this case, you have to select another source

  6784.   *           of the system clock then stop the HSI.

  6785.   * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.

  6786.   * @param    __STATE__ specifies the new state of the HSI.

  6787.   *           This parameter can be one of the following values:

  6788.   *            @arg RCC_HSI_OFF turn OFF the HSI oscillator

  6789.   *            @arg RCC_HSI_ON turn ON the HSI oscillator

  6790.   *            @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)

  6791.   *            @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2

  6792.   *            @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4

  6793.   *            @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8

  6794.   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator

  6795.   *         clock cycles.

  6796.   */

  6797. #define __HAL_RCC_HSI_CONFIG(__STATE__) \

  6798.                   MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))

  6799. 

  6800. 

  6801. /** @brief  Macro to get the HSI divider.

  6802.   * @retval The HSI divider. The returned value can be one

  6803.   *         of the following:

  6804.   *            - RCC_CR_HSIDIV_1  HSI oscillator divided by 1 (default after reset)

  6805.   *            - RCC_CR_HSIDIV_2  HSI oscillator divided by 2

  6806.   *            - RCC_CR_HSIDIV_4  HSI oscillator divided by 4

  6807.   *            - RCC_CR_HSIDIV_8  HSI oscillator divided by 8

  6808.   */

  6809. #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))

  6810. 

  6811. /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).

  6812.   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.

  6813.   *         It is used (enabled by hardware) as system clock source after start-up

  6814.   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure

  6815.   *         of the HSE used directly or indirectly as system clock (if the Clock

  6816.   *         Security System CSS is enabled).

  6817.   * @note   HSI can not be stopped if it is used as system clock source. In this case,

  6818.   *         you have to select another source of the system clock then stop the HSI.

  6819.   * @note   After enabling the HSI, the application software should wait on HSIRDY

  6820.   *         flag to be set indicating that HSI clock is stable and can be used as

  6821.   *         system clock source.

  6822.   *         This parameter can be: ENABLE or DISABLE.

  6823.   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator

  6824.   *         clock cycles.

  6825.   */

  6826. #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)

  6827. #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)

  6828. 

  6829. 

  6830. /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

  6831.   * @note   The calibration is used to compensate for the variations in voltage

  6832.   *         and temperature that influence the frequency of the internal HSI RC.

  6833.   * @param  __HSICalibrationValue__: specifies the calibration trimming value.

  6834.   *         This parameter must be a number between 0 and 0x7F (3F for Rev Y device).

  6835.   */

  6836. #if defined(RCC_VER_X)

  6837. #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \

  6838.            do {                                                                                                                          \

  6839.               if(HAL_GetREVID() <= REV_ID_Y)                                                                                             \

  6840.              {                                                                                                                           \

  6841.                MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);    \

  6842.              }                                                                                                                           \

  6843.              else                                                                                                                        \

  6844.              {                                                                                                                           \

  6845.                MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);            \

  6846.              }                                                                                                                           \

  6847.            } while(0)

  6848. 

  6849. #else

  6850. #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \

  6851.                MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);

  6852. #endif /*RCC_VER_X*/

  6853. /**

  6854.   * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)

  6855.   *           in STOP mode to be quickly available as kernel clock for some peripherals.

  6856.   * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication

  6857.   *           speed because of the HSI start-up time.

  6858.   * @note     The enable of this function has not effect on the HSION bit.

  6859.   *           This parameter can be: ENABLE or DISABLE.

  6860.   * @retval None

  6861.   */

  6862. #define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)

  6863. #define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

  6864. 

  6865. 

  6866. /**

  6867.   * @brief  Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).

  6868.   * @note   After enabling the HSI48, the application software should wait on

  6869.   *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can

  6870.   *         be used to clock the USB.

  6871.   * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.

  6872.   */

  6873. #define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);

  6874. 

  6875. #define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);

  6876. 

  6877. /**

  6878.   * @brief  Macros to enable or disable the Internal  oscillator (CSI).

  6879.   * @note     The CSI is stopped by hardware when entering STOP and STANDBY modes.

  6880.   *           It is used (enabled by hardware) as system clock source after

  6881.   *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case

  6882.   *           of failure of the HSE used directly or indirectly as system clock

  6883.   *           (if the Clock Security System CSS is enabled).

  6884.   * @note     CSI can not be stopped if it is used as system clock source.

  6885.   *           In this case, you have to select another source of the system

  6886.   *           clock then stop the CSI.

  6887.   * @note     After enabling the CSI, the application software should wait on

  6888.   *           CSIRDY flag to be set indicating that CSI clock is stable and can

  6889.   *           be used as system clock source.

  6890.   * @note     When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator

  6891.   *           clock cycles.

  6892.   */

  6893. #define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)

  6894. #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)

  6895. 

  6896. /** @brief  Macro Adjusts the Internal  oscillator (CSI) calibration value.

  6897.   * @note   The calibration is used to compensate for the variations in voltage

  6898.   *         and temperature that influence the frequency of the internal CSI RC.

  6899.   * @param  __CSICalibrationValue__: specifies the calibration trimming value.

  6900.   *         This parameter must be a number between 0 and 0x1F.

  6901.   */

  6902. #if defined(RCC_VER_X)

  6903. #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \

  6904.            do {                                                                                                                          \

  6905.              if(HAL_GetREVID() <= REV_ID_Y)                                                                                              \

  6906.              {                                                                                                                           \

  6907.                MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos);    \

  6908.              }                                                                                                                           \

  6909.              else                                                                                                                        \

  6910.              {                                                                                                                           \

  6911.                MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \

  6912.              }                                                                                                                           \

  6913.            } while(0)

  6914. 

  6915. #else

  6916. #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \

  6917.            do {                                                                                                                          \

  6918.                MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \

  6919.                } while(0)

  6920. 

  6921. #endif /*RCC_VER_X*/

  6922. /**

  6923.   * @brief    Macros to enable or disable the force of the Low-power Internal oscillator (CSI)

  6924.   *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

  6925.   * @note     Keeping the CSI ON in STOP mode allows to avoid slowing down the communication

  6926.   *           speed because of the CSI start-up time.

  6927.   * @note     The enable of this function has not effect on the CSION bit.

  6928.   *           This parameter can be: ENABLE or DISABLE.

  6929.   * @retval None

  6930.   */

  6931. #define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)

  6932. #define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)

  6933. 

  6934. 

  6935. /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).

  6936.   * @note   After enabling the LSI, the application software should wait on

  6937.   *         LSIRDY flag to be set indicating that LSI clock is stable and can

  6938.   *         be used to clock the IWDG and/or the RTC.

  6939.   * @note   LSI can not be disabled if the IWDG is running.

  6940.   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator

  6941.   *         clock cycles.

  6942.   */

  6943. #define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)

  6944. #define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

  6945. 

  6946. /**

  6947.   * @brief  Macro to configure the External High Speed oscillator (__HSE__).

  6948.   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application

  6949.   *         software should wait on HSERDY flag to be set indicating that HSE clock

  6950.   *         is stable and can be used to clock the PLL and/or system clock.

  6951.   * @note   HSE state can not be changed if it is used directly or through the

  6952.   *         PLL as system clock. In this case, you have to select another source

  6953.   *         of the system clock then change the HSE state (ex. disable it).

  6954.   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.

  6955.   * @note   This function reset the CSSON bit, so if the clock security system(CSS)

  6956.   *         was previously enabled you have to enable it again after calling this

  6957.   *         function.

  6958.   * @param  __STATE__: specifies the new state of the HSE.

  6959.   *         This parameter can be one of the following values:

  6960.   *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after

  6961.   *                              6 HSE oscillator clock cycles.

  6962.   *            @arg RCC_HSE_ON: turn ON the HSE oscillator.

  6963.   *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.

  6964.   */

  6965. #if defined(RCC_CR_HSEEXT)

  6966. #define __HAL_RCC_HSE_CONFIG(__STATE__)                                \

  6967.                     do {                                               \

  6968.                       if ((__STATE__) == RCC_HSE_ON)                   \

  6969.                       {                                                \

  6970.                         SET_BIT(RCC->CR, RCC_CR_HSEON);                \

  6971.                       }                                                \

  6972.                       else if ((__STATE__) == RCC_HSE_OFF)             \

  6973.                       {                                                \

  6974.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \

  6975.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \

  6976.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \

  6977.                       }                                                \

  6978.                       else if ((__STATE__) == RCC_HSE_BYPASS)          \

  6979.                       {                                                \

  6980.                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \

  6981.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \

  6982.                         SET_BIT(RCC->CR, RCC_CR_HSEON);                \

  6983.                       }                                                \

  6984.                       else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL)   \

  6985.                       {                                                \

  6986.                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \

  6987.                         SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \

  6988.                         SET_BIT(RCC->CR, RCC_CR_HSEON);                \

  6989.                       }                                                \

  6990.                       else                                             \

  6991.                       {                                                \

  6992.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \

  6993.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \

  6994.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \

  6995.                       }                                                \

  6996.                     } while(0)

  6997. #else

  6998. #define __HAL_RCC_HSE_CONFIG(__STATE__)                         \

  6999.                     do {                                        \

  7000.                       if ((__STATE__) == RCC_HSE_ON)            \

  7001.                       {                                         \

  7002.                         SET_BIT(RCC->CR, RCC_CR_HSEON);         \

  7003.                       }                                         \

  7004.                       else if ((__STATE__) == RCC_HSE_OFF)      \

  7005.                       {                                         \

  7006.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \

  7007.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \

  7008.                       }                                         \

  7009.                       else if ((__STATE__) == RCC_HSE_BYPASS)   \

  7010.                       {                                         \

  7011.                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \

  7012.                         SET_BIT(RCC->CR, RCC_CR_HSEON);         \

  7013.                       }                                         \

  7014.                       else                                      \

  7015.                       {                                         \

  7016.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \

  7017.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \

  7018.                       }                                         \

  7019.                     } while(0)

  7020. #endif /* RCC_CR_HSEEXT */

  7021. 

  7022. /** @defgroup RCC_LSE_Configuration LSE Configuration

  7023.   * @{

  7024.   */

  7025. 

  7026. /**

  7027.   * @brief  Macro to configure the External Low Speed oscillator (LSE).

  7028.   * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.

  7029.   *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.

  7030.   * @note   The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*).

  7031.             A duty cycle close to 50% is recommended.

  7032.   * @note   As the LSE is in the Backup domain and write access is denied to

  7033.   *         this domain after reset, you have to enable write access using

  7034.   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE

  7035.   *         (to be done once after reset).

  7036.   * @note   After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application

  7037.   *         software should wait on LSERDY flag to be set indicating that LSE clock

  7038.   *         is stable and can be used to clock the RTC.

  7039.   * @note   If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)

  7040.   * @param  __STATE__: specifies the new state of the LSE.

  7041.   *         This parameter can be one of the following values:

  7042.   *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after

  7043.   *                              6 LSE oscillator clock cycles.

  7044.   *            @arg RCC_LSE_ON: turn ON the LSE oscillator.

  7045.   *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.

  7046.   *            @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)

  7047.   *

  7048.   *         (*) Available on some STM32H7 lines only.

  7049.   */

  7050. #if defined(RCC_BDCR_LSEEXT)

  7051. #define __HAL_RCC_LSE_CONFIG(__STATE__) \

  7052.                     do {                                               \

  7053.                       if((__STATE__) == RCC_LSE_ON)                    \

  7054.                       {                                                \

  7055.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \

  7056.                       }                                                \

  7057.                       else if((__STATE__) == RCC_LSE_OFF)              \

  7058.                       {                                                \

  7059.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \

  7060.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \

  7061.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \

  7062.                       }                                                \

  7063.                       else if((__STATE__) == RCC_LSE_BYPASS)           \

  7064.                       {                                                \

  7065.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \

  7066.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \

  7067.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \

  7068.                       }                                                \

  7069.                       else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \

  7070.                       {                                                \

  7071.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \

  7072.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \

  7073.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \

  7074.                       }                                                \

  7075.                       else                                             \

  7076.                       {                                                \

  7077.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \

  7078.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \

  7079.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \

  7080.                       }                                                \

  7081.                     } while(0)

  7082. #else

  7083. 

  7084. #define __HAL_RCC_LSE_CONFIG(__STATE__) \

  7085.                     do {                                       \

  7086.                       if((__STATE__) == RCC_LSE_ON)            \

  7087.                       {                                        \

  7088.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \

  7089.                       }                                        \

  7090.                       else if((__STATE__) == RCC_LSE_OFF)      \

  7091.                       {                                        \

  7092.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \

  7093.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \

  7094.                       }                                        \

  7095.                       else if((__STATE__) == RCC_LSE_BYPASS)   \

  7096.                       {                                        \

  7097.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \

  7098.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \

  7099.                       }                                        \

  7100.                       else                                     \

  7101.                       {                                        \

  7102.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \

  7103.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \

  7104.                       }                                        \

  7105.                     } while(0)

  7106. 

  7107. #endif /* RCC_BDCR_LSEEXT */

  7108. /**

  7109.   * @}

  7110.   */

  7111. 

  7112. /** @brief  Macros to enable or disable the the RTC clock.

  7113.   * @note   These macros must be used only after the RTC clock source was selected.

  7114.   */

  7115. #define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

  7116. #define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

  7117. 

  7118. /** @brief  Macros to configure the RTC clock (RTCCLK).

  7119.   * @note   As the RTC clock configuration bits are in the Backup domain and write

  7120.   *         access is denied to this domain after reset, you have to enable write

  7121.   *         access using the Power Backup Access macro before to configure

  7122.   *         the RTC clock source (to be done once after reset).

  7123.   * @note   Once the RTC clock is configured it can't be changed unless the

  7124.   *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by

  7125.   *         a Power On Reset (POR).

  7126.   * @param  __RTCCLKSource__: specifies the RTC clock source.

  7127.   *         This parameter can be one of the following values:

  7128.   *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.

  7129.   *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.

  7130.   *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected

  7131.   *                                            as RTC clock, where x:[2,31]

  7132.   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to

  7133.   *         work in STOP and STANDBY modes, and can be used as wakeup source.

  7134.   *         However, when the HSE clock is used as RTC clock source, the RTC

  7135.   *         cannot be used in STOP and STANDBY modes.

  7136.   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as

  7137.   *         RTC clock source).

  7138.   */

  7139. #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \

  7140.                                                  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)

  7141. 

  7142. #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \

  7143.                                                     RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \

  7144.                                                    } while (0)

  7145. 

  7146. #define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))

  7147. 

  7148. 

  7149. /** @brief  Macros to force or release the Backup domain reset.

  7150.   * @note   This function resets the RTC peripheral (including the backup registers)

  7151.   *         and the RTC clock source selection in RCC_BDCR register.

  7152.   * @note   The BKPSRAM is not affected by this reset.

  7153.   */

  7154. #define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

  7155. #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

  7156. 

  7157. /** @brief  Macros to enable or disable the main PLL.

  7158.   * @note   After enabling the main PLL, the application software should wait on

  7159.   *         PLLRDY flag to be set indicating that PLL clock is stable and can

  7160.   *         be used as system clock source.

  7161.   * @note   The main PLL can not be disabled if it is used as system clock source

  7162.   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.

  7163.   */

  7164. #define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)

  7165. #define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)

  7166. 

  7167. /**

  7168.   * @brief  Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)

  7169.   * @note   Enabling/disabling  those Clocks can be done only when the PLL is disabled.

  7170.   *         This is mainly used to save Power.

  7171.   *        (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).

  7172.   * @param  __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted

  7173.   *          This parameter can be one of the following values:

  7174.   *            @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)

  7175.   *            @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

  7176.   *            @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

  7177.   *

  7178.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  7179.   *

  7180.   * @retval None

  7181.   */

  7182. #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

  7183. 

  7184. #define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

  7185. 

  7186. 

  7187. /**

  7188.   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO

  7189.   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL1

  7190.   * @retval None

  7191.   */

  7192. #define __HAL_RCC_PLLFRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

  7193. 

  7194. #define __HAL_RCC_PLLFRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

  7195. 

  7196. 

  7197. /**

  7198.   * @brief  Macro to configures the main PLL clock source, multiplication and division factors.

  7199.   * @note   This function must be used only when the main PLL is disabled.

  7200.   *

  7201.   * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.

  7202.   *          This parameter can be one of the following values:

  7203.   *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry

  7204.   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry

  7205.   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

  7206.   * @note   This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .

  7207.   *

  7208.   * @param  __PLLM1__: specifies the division factor for PLL VCO input clock

  7209.   *          This parameter must be a number between 1 and 63.

  7210.   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input

  7211.   *         frequency ranges from 1 to 16 MHz.

  7212.   *

  7213.   * @param  __PLLN1__: specifies the multiplication factor for PLL VCO output clock

  7214.   *          This parameter must be a number between 4 and 512 or between 8 and 420(*).

  7215.   * @note   You have to set the PLLN parameter correctly to ensure that the VCO

  7216.   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or

  7217.   *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

  7218.   *

  7219.   * @param  __PLLP1__: specifies the division factor for system  clock.

  7220.   *          This parameter must be a number between 2 and 128 (where odd numbers are not allowed)

  7221.   *

  7222.   * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks

  7223.   *          This parameter must be a number between 1 and 128

  7224.   *

  7225.   * @param  __PLLR1__: specifies the division factor for peripheral kernel clocks

  7226.   *          This parameter must be a number between 1 and 128

  7227.   *

  7228.   * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)

  7229.   *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible

  7230.   *         value to  __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.

  7231.   * @retval None

  7232.   *

  7233.   *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  7234.   */

  7235. 

  7236. 

  7237. #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \

  7238.                   do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \

  7239.                       WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \

  7240.                                 ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \

  7241.                     } while(0)

  7242. 

  7243. 

  7244. /** @brief  Macro to configure the PLLs clock source.

  7245.   * @note   This function must be used only when all PLLs are disabled.

  7246.   * @param  __PLLSOURCE__: specifies the PLLs entry clock source.

  7247.   *         This parameter can be one of the following values:

  7248.   *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry

  7249.   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry

  7250.   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

  7251.   *

  7252.   */

  7253. #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))

  7254. 

  7255. 

  7256. /**

  7257.   * @brief  Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor

  7258.   *

  7259.   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO

  7260.   *

  7261.   * @param  __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO

  7262.   *                            It should be a value between 0 and 8191

  7263.   * @note   Warning: The software has to set correctly these bits to insure that the VCO

  7264.   *                  output frequency is between its valid frequency range, which is:

  7265.   *                   192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0

  7266.   *                   150 to 420 MHz if PLL1VCOSEL = 1.

  7267.   *

  7268.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  7269.   *

  7270.   * @retval None

  7271.   */

  7272.  #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)

  7273. 

  7274. 

  7275. /** @brief  Macro to select  the PLL1  reference frequency range.

  7276.   * @param  __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range

  7277.   *         This parameter can be one of the following values:

  7278.   *            @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz

  7279.   *            @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz

  7280.   *            @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz

  7281.   *            @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz

  7282.   * @retval None

  7283.   */

  7284. #define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \

  7285.                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))

  7286. 

  7287. 

  7288. /** @brief  Macro to select  the PLL1  reference frequency range.

  7289.   * @param  __RCC_PLL1VCORange__: specifies the PLL1 input frequency range

  7290.   *         This parameter can be one of the following values:

  7291.   *            @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)

  7292.   *            @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz

  7293.   *

  7294.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  7295.   *

  7296.   * @retval None

  7297.   */

  7298. #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \

  7299.                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))

  7300. 

  7301. 

  7302. 

  7303. /** @brief  Macro to get the clock source used as system clock.

  7304.   * @retval The clock source used as system clock. The returned value can be one

  7305.   *         of the following:

  7306.   *              - RCC_CFGR_SWS_CSI: CSI used as system clock.

  7307.   *              - RCC_CFGR_SWS_HSI: HSI used as system clock.

  7308.   *              - RCC_CFGR_SWS_HSE: HSE used as system clock.

  7309.   *              - RCC_CFGR_SWS_PLL: PLL used as system clock.

  7310.   */

  7311. #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))

  7312. 

  7313. 

  7314. /**

  7315.   * @brief Macro to configure the system clock source.

  7316.   * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.

  7317.   * This parameter can be one of the following values:

  7318.   *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.

  7319.   *              - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.

  7320.   *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.

  7321.   *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.

  7322.   */

  7323. #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))

  7324. 

  7325. /** @brief  Macro to get the oscillator used as PLL clock source.

  7326.   * @retval The oscillator used as PLL clock source. The returned value can be one

  7327.   *         of the following:

  7328.   *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.

  7329.   *              - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.

  7330.   *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.

  7331.   *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

  7332.   */

  7333. #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))

  7334. 

  7335. /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config

  7336.   * @{

  7337.   */

  7338. 

  7339. /** @brief  Macro to configure the MCO1 clock.

  7340.   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.

  7341.   *          This parameter can be one of the following values:

  7342.   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source

  7343.   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source

  7344.   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source

  7345.   *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source

  7346.   *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source

  7347.   * @param  __MCODIV__ specifies the MCO clock prescaler.

  7348.   *          This parameter can be one of the following values:

  7349.   *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO1 clock

  7350.   */

  7351. #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \

  7352.                  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

  7353. 

  7354. /** @brief  Macro to configure the MCO2 clock.

  7355.   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.

  7356.   *          This parameter can be one of the following values:

  7357.   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source

  7358.   *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source

  7359.   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source

  7360.   *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source

  7361.   *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source

  7362.   *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source

  7363.   * @param  __MCODIV__ specifies the MCO clock prescaler.

  7364.   *          This parameter can be one of the following values:

  7365.   *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO2 clock

  7366.   */

  7367. #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \

  7368.     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));

  7369. 

  7370. /**

  7371.   * @}

  7372.   */

  7373. 

  7374. /**

  7375.   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.

  7376.   * @note   As the LSE is in the Backup domain and write access is denied to

  7377.   *         this domain after reset, you have to enable write access using

  7378.   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE

  7379.   *         (to be done once after reset).

  7380.   * @note   On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.

  7381.   * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.

  7382.   *          This parameter can be one of the following values:

  7383.   *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.

  7384.   *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.

  7385.   *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.

  7386.   *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.

  7387.   * @retval None

  7388.   */

  7389. #if defined(RCC_VER_X)

  7390. #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \

  7391.            do{                                                                                                                                \

  7392.              if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH)))  \

  7393.              {                                                                                                                                \

  7394.               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk);                                      \

  7395.              }                                                                                                                                \

  7396.              else                                                                                                                             \

  7397.              {                                                                                                                                \

  7398.                MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));                                                              \

  7399.              }                                                                                                                                \

  7400.            } while(0)

  7401. #else

  7402. #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \

  7403.                MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));

  7404. #endif /*RCC_VER_X*/

  7405. /**

  7406.   * @brief  Macro to configure the wake up from stop clock.

  7407.   * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop

  7408.   *         This parameter can be one of the following values:

  7409.   *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source

  7410.   *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source

  7411.   * @retval None

  7412.   */

  7413. #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \

  7414.                   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))

  7415. 

  7416. /**

  7417.   * @brief  Macro to configure the Kernel wake up from stop clock.

  7418.   * @param  __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop

  7419.   *         This parameter can be one of the following values:

  7420.   *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source

  7421.   *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source

  7422.   * @retval None

  7423.   */

  7424. #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \

  7425.                   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))

  7426. 

  7427. /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management

  7428.   * @brief macros to manage the specified RCC Flags and interrupts.

  7429.   * @{

  7430.   */

  7431. /** @brief  Enable RCC interrupt.

  7432.   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.

  7433.   *         This parameter can be any combination of the following values:

  7434.   *            @arg RCC_IT_LSIRDY: LSI ready interrupt

  7435.   *            @arg RCC_IT_LSERDY: LSE ready interrupt

  7436.   *            @arg RCC_IT_CSIRDY: HSI ready interrupt

  7437.   *            @arg RCC_IT_HSIRDY: HSI ready interrupt

  7438.   *            @arg RCC_IT_HSERDY: HSE ready interrupt

  7439.   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt

  7440.   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt

  7441.   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt

  7442.   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt

  7443.   *            @arg RCC_IT_LSECSS: Clock security system interrupt

  7444.   */

  7445. #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))

  7446. 

  7447. /** @brief Disable RCC interrupt

  7448.   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.

  7449.   *         This parameter can be any combination of the following values:

  7450.   *            @arg RCC_IT_LSIRDY: LSI ready interrupt

  7451.   *            @arg RCC_IT_LSERDY: LSE ready interrupt

  7452.   *            @arg RCC_IT_CSIRDY: HSI ready interrupt

  7453.   *            @arg RCC_IT_HSIRDY: HSI ready interrupt

  7454.   *            @arg RCC_IT_HSERDY: HSE ready interrupt

  7455.   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt

  7456.   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt

  7457.   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt

  7458.   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt

  7459.   *            @arg RCC_IT_LSECSS: Clock security system interrupt

  7460.   */

  7461. #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))

  7462. 

  7463. /** @brief  Clear the RCC's interrupt pending bits

  7464.   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.

  7465.   *         This parameter can be any combination of the following values:

  7466.   *            @arg RCC_IT_LSIRDY: LSI ready interrupt

  7467.   *            @arg RCC_IT_LSERDY: LSE ready interrupt

  7468.   *            @arg RCC_IT_CSIRDY: CSI ready interrupt

  7469.   *            @arg RCC_IT_HSIRDY: HSI ready interrupt

  7470.   *            @arg RCC_IT_HSERDY: HSE ready interrupt

  7471.   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt

  7472.   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt

  7473.   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt

  7474.   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt

  7475.   *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt

  7476.   *            @arg RCC_IT_LSECSS: Clock security system interrupt

  7477.   */

  7478. #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))

  7479. 

  7480. /** @brief  Check the RCC's interrupt has occurred or not.

  7481.   * @param  __INTERRUPT__: specifies the RCC interrupt source to check.

  7482.   *         This parameter can be any combination of the following values:

  7483.   *            @arg RCC_IT_LSIRDY: LSI ready interrupt

  7484.   *            @arg RCC_IT_LSERDY: LSE ready interrupt

  7485.   *            @arg RCC_IT_CSIRDY: CSI ready interrupt

  7486.   *            @arg RCC_IT_HSIRDY: HSI ready interrupt

  7487.   *            @arg RCC_IT_HSERDY: HSE ready interrupt

  7488.   *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt

  7489.   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt

  7490.   *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt

  7491.   *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt

  7492.   *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt

  7493.   *            @arg RCC_IT_LSECSS: Clock security system interrupt

  7494.   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

  7495.   */

  7496. #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

  7497. 

  7498. /** @brief Set RMVF bit to clear the reset flags.

  7499.   */

  7500. #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)

  7501. 

  7502. #if defined(DUAL_CORE)

  7503. #define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)

  7504. 

  7505. #define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)

  7506. #endif /*DUAL_CORE*/

  7507. 

  7508. #if defined(DUAL_CORE)

  7509. /** @brief  Check RCC flag is set or not.

  7510.   * @param  __FLAG__: specifies the flag to check.

  7511.   *         This parameter can be one of the following values:

  7512.   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready

  7513.   *            @arg RCC_FLAG_HSIDIV: HSI divider flag

  7514.   *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready

  7515.   *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready

  7516.   *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready

  7517.   *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready

  7518.   *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready

  7519.   *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready

  7520.   *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready

  7521.   *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready

  7522.   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready

  7523.   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready

  7524.   *            @arg RCC_FLAG_C1RST:  CPU reset flag

  7525.   *            @arg RCC_FLAG_C2RST:  CPU2 reset flag

  7526.   *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag

  7527.   *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag

  7528.   *            @arg RCC_FLAG_BORRST: BOR reset flag

  7529.   *            @arg RCC_FLAG_PINRST: Pin reset

  7530.   *            @arg RCC_FLAG_PORRST: POR/PDR  reset

  7531.   *            @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag

  7532.   *            @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag

  7533.   *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag

  7534.   *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset

  7535.   *            @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset

  7536.   *            @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset

  7537.   *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset

  7538.   *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag

  7539.   *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag

  7540.   * @retval The new state of __FLAG__ (TRUE or FALSE).

  7541.   */

  7542. #define RCC_FLAG_MASK  ((uint8_t)0x1F)

  7543. #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \

  7544. ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

  7545. 

  7546. #define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \

  7547. ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

  7548. 

  7549. #define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \

  7550. ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

  7551. 

  7552. #else

  7553. 

  7554. /** @brief  Check RCC flag is set or not.

  7555.   * @param  __FLAG__: specifies the flag to check.

  7556.   *         This parameter can be one of the following values:

  7557.   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready

  7558.   *            @arg RCC_FLAG_HSIDIV: HSI divider flag

  7559.   *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready

  7560.   *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready

  7561.   *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready

  7562.   *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready (*)

  7563.   *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready (*)

  7564.   *            @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*)

  7565.   *            @arg RCC_FLAG_CDCKRDY:  CPU Domain clock ready (*)

  7566.   *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready

  7567.   *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready

  7568.   *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready

  7569.   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready

  7570.   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready

  7571.   *            @arg RCC_FLAG_CPURST: CPU reset flag

  7572.   *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag (*)

  7573.   *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag (*)

  7574.   *            @arg RCC_FLAG_CDRST:  CD domain power switch reset flag (*)

  7575.   *            @arg RCC_FLAG_BORRST: BOR reset flag

  7576.   *            @arg RCC_FLAG_PINRST: Pin reset

  7577.   *            @arg RCC_FLAG_PORRST: POR/PDR  reset

  7578.   *            @arg RCC_FLAG_SFTRST: System reset from CPU reset flag

  7579.   *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag

  7580.   *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset

  7581.   *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset

  7582.   *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag

  7583.   *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag

  7584.   * @retval The new state of __FLAG__ (TRUE or FALSE).

  7585.   *

  7586.   *  (*) Available on some STM32H7 lines only.

  7587.   */

  7588. #define RCC_FLAG_MASK  ((uint8_t)0x1F)

  7589. #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \

  7590. ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

  7591. #endif /*DUAL_CORE*/

  7592. 

  7593. /**

  7594.   * @}

  7595.   */

  7596. 

  7597. #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)

  7598. 

  7599. /**

  7600.   * @}

  7601.   */

  7602. 

  7603. /* Include RCC HAL Extension module */

  7604. #include "stm32h7xx_hal_rcc_ex.h"

  7605. 

  7606. /* Exported functions --------------------------------------------------------*/

  7607.  /** @addtogroup RCC_Exported_Functions

  7608.   * @{

  7609.   */

  7610. 

  7611. /** @addtogroup RCC_Exported_Functions_Group1

  7612.   * @{

  7613.   */

  7614. /* Initialization and de-initialization functions  ******************************/

  7615. HAL_StatusTypeDef HAL_RCC_DeInit(void);

  7616. HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);

  7617. HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);

  7618. 

  7619. /**

  7620.   * @}

  7621.   */

  7622. 

  7623. /** @addtogroup RCC_Exported_Functions_Group2

  7624.   * @{

  7625.   */

  7626. /* Peripheral Control functions  ************************************************/

  7627. void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);

  7628. void     HAL_RCC_EnableCSS(void);

  7629. void     HAL_RCC_DisableCSS(void);

  7630. uint32_t HAL_RCC_GetSysClockFreq(void);

  7631. uint32_t HAL_RCC_GetHCLKFreq(void);

  7632. uint32_t HAL_RCC_GetPCLK1Freq(void);

  7633. uint32_t HAL_RCC_GetPCLK2Freq(void);

  7634. void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);

  7635. void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);

  7636. /* CSS NMI IRQ handler */

  7637. void     HAL_RCC_NMI_IRQHandler(void);

  7638. /* User Callbacks in non blocking mode (IT mode) */

  7639. void     HAL_RCC_CCSCallback(void);

  7640. 

  7641. /**

  7642.   * @}

  7643.   */

  7644. 

  7645. /**

  7646.   * @}

  7647.   */

  7648. 

  7649. /* Private types -------------------------------------------------------------*/

  7650. /* Private variables ---------------------------------------------------------*/

  7651. /* Private constants ---------------------------------------------------------*/

  7652. /** @defgroup RCC_Private_Constants RCC Private Constants

  7653.   * @{

  7654.   */

  7655. 

  7656. #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT

  7657. #define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms */

  7658. #define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms */

  7659. #define CSI_TIMEOUT_VALUE          (2U)    /* 2 ms */

  7660. #define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms */

  7661. #define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms */

  7662. #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s  */

  7663. #define RCC_DBP_TIMEOUT_VALUE      (100U)

  7664. #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT

  7665. 

  7666. /**

  7667.   * @}

  7668.   */

  7669. 

  7670. /* Private macros ------------------------------------------------------------*/

  7671. /** @addtogroup RCC_Private_Macros RCC Private Macros

  7672.   * @{

  7673.   */

  7674. 

  7675. /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters

  7676.   * @{

  7677.   */

  7678. 

  7679. #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \

  7680.                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \

  7681.                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \

  7682.                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \

  7683.                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \

  7684.                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \

  7685.                                            (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))

  7686. 

  7687. #if defined(RCC_CR_HSEEXT)

  7688. #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \

  7689.                          ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))

  7690. #else

  7691. #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \

  7692.                          ((HSE) == RCC_HSE_BYPASS))

  7693. #endif /* RCC_CR_HSEEXT */

  7694. 

  7695. #if defined(RCC_BDCR_LSEEXT)

  7696. #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \

  7697.                          ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))

  7698. #else

  7699. #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \

  7700.                          ((LSE) == RCC_LSE_BYPASS))

  7701. #endif /* RCC_BDCR_LSEEXT */

  7702. 

  7703. #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \

  7704.                          ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \

  7705.                          ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))

  7706. 

  7707. #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))

  7708. 

  7709. #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))

  7710. 

  7711. #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))

  7712. 

  7713. #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \

  7714.                          ((PLL) == RCC_PLL_ON))

  7715. 

  7716. #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI)  || \

  7717.                                   ((SOURCE) == RCC_PLLSOURCE_HSI)  || \

  7718.                                   ((SOURCE) == RCC_PLLSOURCE_NONE) || \

  7719.                                   ((SOURCE) == RCC_PLLSOURCE_HSE))

  7720. #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

  7721. #if !defined(RCC_VER_2_0)

  7722. #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

  7723. #else

  7724. #define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))

  7725. #endif /* !RCC_VER_2_0 */

  7726. #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  7727. #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  7728. #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  7729. 

  7730. #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \

  7731.                                          ((VALUE) == RCC_PLL1_DIVQ) || \

  7732.                                          ((VALUE) == RCC_PLL1_DIVR))

  7733. 

  7734. #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))

  7735. 

  7736. #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \

  7737.                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \

  7738.                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \

  7739.                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))

  7740. 

  7741. #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \

  7742.                                ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \

  7743.                                ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \

  7744.                                ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \

  7745.                                ((SYSCLK) == RCC_SYSCLK_DIV512))

  7746. 

  7747. 

  7748. #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \

  7749.                            ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \

  7750.                            ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \

  7751.                            ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \

  7752.                            ((HCLK) == RCC_HCLK_DIV512))

  7753. 

  7754. #define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \

  7755.                                  ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \

  7756.                                  ((CDPCLK1) == RCC_APB3_DIV16))

  7757. 

  7758. #define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1  /* for legacy compatibility between H7 lines */

  7759. 

  7760. #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \

  7761.                              ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \

  7762.                             ((PCLK1) == RCC_APB1_DIV16))

  7763. 

  7764. #define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \

  7765.                              ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \

  7766.                              ((PCLK2) == RCC_APB2_DIV16))

  7767. 

  7768. #define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \

  7769.                                   ((SRDPCLK1) == RCC_APB4_DIV4)  || ((SRDPCLK1) == RCC_APB4_DIV8) || \

  7770.                                   ((SRDPCLK1) == RCC_APB4_DIV16))

  7771. 

  7772. #define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/

  7773. 

  7774. #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE)       || ((SOURCE) == RCC_RTCCLKSOURCE_LSI)       || \

  7775.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3)  || \

  7776.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5)  || \

  7777.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7)  || \

  7778.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9)  || \

  7779.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \

  7780.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \

  7781.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \

  7782.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \

  7783.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \

  7784.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \

  7785.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \

  7786.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \

  7787.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \

  7788.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \

  7789.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \

  7790.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \

  7791.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \

  7792.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \

  7793.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \

  7794.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \

  7795.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \

  7796.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \

  7797.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \

  7798.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \

  7799.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \

  7800.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \

  7801.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \

  7802.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \

  7803.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \

  7804.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \

  7805.                                      ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))

  7806. 

  7807. #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))

  7808. 

  7809. #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \

  7810.                                    ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \

  7811.                                    ((SOURCE) == RCC_MCO1SOURCE_HSI48))

  7812. 

  7813. #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \

  7814.                                    ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \

  7815.                                    ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))

  7816. 

  7817. #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \

  7818.                             ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \

  7819.                             ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \

  7820.                             ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \

  7821.                             ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \

  7822.                             ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \

  7823.                             ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \

  7824.                             ((DIV) == RCC_MCODIV_15))

  7825. 

  7826. #if defined(DUAL_CORE)

  7827. #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \

  7828.                            ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \

  7829.                            ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \

  7830.                            ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \

  7831.                            ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \

  7832.                            ((FLAG) == RCC_FLAG_LSIRDY)    || \

  7833.                            ((FLAG) == RCC_FLAG_C1RST)     || ((FLAG) == RCC_FLAG_C2RST)   || \

  7834.                            ((FLAG) == RCC_FLAG_SFTR2ST)   || ((FLAG) == RCC_FLAG_WWDG2RST)|| \

  7835.                            ((FLAG) == RCC_FLAG_IWDG2RST)  || ((FLAG) == RCC_FLAG_D1RST)   || \

  7836.                            ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \

  7837.                            ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \

  7838.                            ((FLAG) == RCC_FLAG_SFTR1ST)   || ((FLAG) == RCC_FLAG_IWDG1RST)|| \

  7839.                            ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \

  7840.                            ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV))

  7841. 

  7842. #else

  7843. 

  7844. #if defined(RCC_CR_D2CKRDY)

  7845. #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \

  7846.                            ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \

  7847.                            ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \

  7848.                            ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \

  7849.                            ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \

  7850.                            ((FLAG) == RCC_FLAG_LSIRDY)    || \

  7851.                            ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \

  7852.                            ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \

  7853.                            ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \

  7854.                            ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \

  7855.                            ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \

  7856.                            ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))

  7857. #else

  7858. #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \

  7859.                            ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \

  7860.                            ((FLAG) == RCC_FLAG_CPUCKRDY)  || ((FLAG) == RCC_FLAG_CDCKRDY) || \

  7861.                            ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \

  7862.                            ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \

  7863.                            ((FLAG) == RCC_FLAG_LSIRDY)    || \

  7864.                            ((FLAG) == RCC_FLAG_CDRST)     || ((FLAG) == RCC_FLAG_BORRST)  || \

  7865.                            ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \

  7866.                            ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \

  7867.                            ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \

  7868.                            ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))

  7869. #endif /* RCC_CR_D2CKRDY */

  7870. 

  7871. #endif /*DUAL_CORE*/

  7872. 

  7873. #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)

  7874. #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)

  7875. 

  7876. #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \

  7877.                                          ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))

  7878. 

  7879. #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \

  7880.                                           ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))

  7881. /**

  7882.   * @}

  7883.   */

  7884. 

  7885. /**

  7886.   * @}

  7887.   */

  7888. 

  7889. /**

  7890.   * @}

  7891.   */

  7892. 

  7893. /**

  7894.   * @}

  7895.   */

  7896. #ifdef __cplusplus

  7897. }

  7898. #endif

  7899. 

  7900. #endif /* STM32H7xx_HAL_RCC_H */

  7901. 

  7902. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/