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stm32lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32h7xx_hal_rcc_ex.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of RCC HAL Extension module.

  6.   ******************************************************************************

  7.   * @attention

  8.   *

  9.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

  10.   * All rights reserved.</center></h2>

  11.   *

  12.   * This software component is licensed by ST under BSD 3-Clause license,

  13.   * the "License"; You may not use this file except in compliance with the

  14.   * License. You may obtain a copy of the License at:

  15.   *                        opensource.org/licenses/BSD-3-Clause

  16.   *

  17.   ******************************************************************************

  18.   */

  19. 

  20. /* Define to prevent recursive inclusion -------------------------------------*/

  21. #ifndef STM32H7xx_HAL_RCC_EX_H

  22. #define STM32H7xx_HAL_RCC_EX_H

  23. 

  24. #ifdef __cplusplus

  25.  extern "C" {

  26. #endif

  27. 

  28. /* Includes ------------------------------------------------------------------*/

  29. #include "stm32h7xx_hal_def.h"

  30. 

  31. /** @addtogroup STM32H7xx_HAL_Driver

  32.   * @{

  33.   */

  34. 

  35. /** @addtogroup RCCEx

  36.   * @{

  37.   */

  38. 

  39. /* Exported types ------------------------------------------------------------*/

  40. /** @defgroup RCCEx_Exported_Types RCCEx Exported Types

  41.   * @{

  42.   */

  43. 

  44. /**

  45.   * @brief  PLL2 Clock structure definition

  46.   */

  47. typedef struct

  48. {

  49. 

  50.   uint32_t PLL2M;       /*!< PLL2M: Division factor for PLL2 VCO input clock.

  51.                              This parameter must be a number between Min_Data = 1 and Max_Data = 63    */

  52. 

  53.   uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.

  54.                              This parameter must be a number between Min_Data = 4 and Max_Data = 512

  55.                              or between Min_Data = 8 and Max_Data = 420(*)

  56.                              (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */

  57. 

  58.   uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.

  59.                              This parameter must be a number between Min_Data = 2 and Max_Data = 128

  60.                              odd division factors are not allowed                                      */

  61. 

  62.   uint32_t PLL2Q;        /*!< PLL2Q: Division factor for peripheral clocks.

  63.                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

  64. 

  65.   uint32_t PLL2R;        /*!< PLL2R: Division factor for peripheral clocks.

  66.                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

  67.   uint32_t PLL2RGE;      /*!<PLL2RGE: PLL2 clock Input range

  68.                           This parameter must be a value of @ref RCC_PLL2_VCI_Range                    */

  69.   uint32_t PLL2VCOSEL;   /*!<PLL2VCOSEL: PLL2 clock Output range

  70.                           This parameter must be a value of @ref RCC_PLL2_VCO_Range                    */

  71. 

  72.   uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for

  73.                             PLL2 VCO It should be a value between 0 and 8191                           */

  74. }RCC_PLL2InitTypeDef;

  75. 

  76. /**

  77.   * @brief  PLL3 Clock structure definition

  78.   */

  79. typedef struct

  80. {

  81. 

  82.   uint32_t PLL3M;       /*!< PLL3M: Division factor for PLL3 VCO input clock.

  83.                              This parameter must be a number between Min_Data = 1 and Max_Data = 63    */

  84. 

  85.   uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.

  86.                              This parameter must be a number between Min_Data = 4 and Max_Data = 512

  87.                              or between Min_Data = 8 and Max_Data = 420(*)

  88.                              (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */

  89. 

  90.   uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.

  91.                              This parameter must be a number between Min_Data = 2 and Max_Data = 128

  92.                              odd division factors are not allowed                                      */

  93. 

  94.   uint32_t PLL3Q;        /*!< PLL3Q: Division factor for peripheral clocks.

  95.                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

  96. 

  97.   uint32_t PLL3R;        /*!< PLL3R: Division factor for peripheral clocks.

  98.                              This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

  99.   uint32_t PLL3RGE;      /*!<PLL3RGE: PLL3 clock Input range

  100.                           This parameter must be a value of @ref RCC_PLL3_VCI_Range                    */

  101.   uint32_t PLL3VCOSEL;   /*!<PLL3VCOSEL: PLL3 clock Output range

  102.                           This parameter must be a value of @ref RCC_PLL3_VCO_Range                    */

  103. 

  104.   uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for

  105.                             PLL3 VCO It should be a value between 0 and 8191                           */

  106. }RCC_PLL3InitTypeDef;

  107. 

  108. /**

  109.   * @brief  RCC PLL1 Clocks structure definition

  110.   */

  111. typedef struct

  112. {

  113.   uint32_t PLL1_P_Frequency;

  114.   uint32_t PLL1_Q_Frequency;

  115.   uint32_t PLL1_R_Frequency;

  116. }PLL1_ClocksTypeDef;

  117. 

  118. /**

  119.   * @brief  RCC PLL2 Clocks structure definition

  120.   */

  121. typedef struct

  122. {

  123.   uint32_t PLL2_P_Frequency;

  124.   uint32_t PLL2_Q_Frequency;

  125.   uint32_t PLL2_R_Frequency;

  126. }PLL2_ClocksTypeDef;

  127. 

  128. /**

  129.   * @brief  RCC PLL3 Clocks structure definition

  130.   */

  131. typedef struct

  132. {

  133.   uint32_t PLL3_P_Frequency;

  134.   uint32_t PLL3_Q_Frequency;

  135.   uint32_t PLL3_R_Frequency;

  136. }PLL3_ClocksTypeDef;

  137. 

  138. 

  139. /**

  140.   * @brief  RCC extended clocks structure definition

  141.   */

  142. typedef struct

  143. {

  144.   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.

  145.                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */

  146. 

  147.   RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.

  148.                                         This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */

  149. 

  150.   RCC_PLL3InitTypeDef PLL3;        /*!< PLL3 structure parameters.

  151.                                         This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */

  152. 

  153.   uint32_t FmcClockSelection;     /*!< Specifies FMC clock source

  154.                                         This parameter can be a value of @ref RCCEx_FMC_Clock_Source     */

  155. 

  156. #if defined(QUADSPI)

  157.   uint32_t QspiClockSelection;    /*!< Specifies QSPI clock source

  158.                                         This parameter can be a value of @ref RCCEx_QSPI_Clock_Source    */

  159. #endif /* QUADSPI */

  160. 

  161. #if defined(OCTOSPI1) || defined(OCTOSPI2)

  162.   uint32_t OspiClockSelection;    /*!< Specifies OSPI clock source

  163.                                         This parameter can be a value of @ref RCCEx_OSPI_Clock_Source    */

  164. #endif /*(OCTOSPI1) || (OCTOSPI2)*/

  165. 

  166. 

  167. #if defined(DSI)

  168.   uint32_t DsiClockSelection;     /*!< Specifies DSI clock source

  169.                                      This parameter can be a value of @ref RCCEx_DSI_Clock_Source        */

  170. #endif /* DSI */

  171. 

  172.   uint32_t SdmmcClockSelection;    /*!< Specifies SDMMC clock source

  173.                                         This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source   */

  174. 

  175.   uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source

  176.                                         This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */

  177. 

  178.   uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source

  179.                                         This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */

  180. 

  181. #if defined(SAI3)

  182.   uint32_t Sai23ClockSelection;     /*!< Specifies SAI2/3 clock source

  183.                                          This parameter can be a value of @ref RCCEx_SAI23_Clock_Source  */

  184. #endif /* SAI3 */

  185. 

  186. #if defined(RCC_CDCCIP1R_SAI2ASEL)

  187.   uint32_t Sai2AClockSelection;     /*!< Specifies SAI2A clock source

  188.                                         This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source  */

  189. #endif /* RCC_CDCCIP1R_SAI2ASEL */

  190. 

  191. #if defined(RCC_CDCCIP1R_SAI2BSEL)

  192.   uint32_t Sai2BClockSelection;     /*!< Specifies SAI2B clock source

  193.                                          This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source    */

  194. #endif /* RCC_CDCCIP1R_SAI2BSEL */

  195. 

  196.   uint32_t Spi123ClockSelection;     /*!< Specifies SPI1/2/3 clock source

  197.                                           This parameter can be a value of @ref RCCEx_SPI123_Clock_Source    */

  198. 

  199.   uint32_t Spi45ClockSelection;     /*!< Specifies SPI4/5 clock source

  200.                                          This parameter can be a value of @ref RCCEx_SPI45_Clock_Source    */

  201. 

  202.   uint32_t SpdifrxClockSelection;   /*!< Specifies SPDIFRX Clock clock source

  203.                                         This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */

  204. 

  205.   uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock clock source

  206.                                         This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source  */

  207. 

  208. #if defined(DFSDM2_BASE)

  209.   uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock clock source

  210.                                         This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source  */

  211. #endif /* DFSDM2_BASE */

  212. 

  213. #if defined(FDCAN1) || defined(FDCAN2)

  214.   uint32_t FdcanClockSelection;   /*!< Specifies FDCAN Clock clock source

  215.                                         This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */

  216. #endif /*FDCAN1 || FDCAN2*/

  217. 

  218.   uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 Clock clock source

  219.                                         This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source  */

  220. 

  221.   uint32_t Usart234578ClockSelection;   /*!< Specifies USART2/3/4/5/7/8 clock source

  222.                                              This parameter can be a value of @ref RCCEx_USART234578_Clock_Source  */

  223. 

  224.   uint32_t Usart16ClockSelection;  /*!< Specifies USART1/6 clock source

  225.                                         This parameter can be a value of @ref RCCEx_USART16_Clock_Source  */

  226. 

  227.    uint32_t RngClockSelection;      /*!< Specifies RNG clock source

  228.                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */

  229. 

  230.    uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source

  231.                                         This parameter can be a value of @ref RCCEx_I2C123_Clock_Source    */

  232. 

  233.   uint32_t UsbClockSelection;      /*!< Specifies USB clock source

  234.                                         This parameter can be a value of @ref RCCEx_USB_Clock_Source     */

  235. 

  236.   uint32_t CecClockSelection;     /*!< Specifies CEC clock source

  237.                                         This parameter can be a value of @ref RCCEx_CEC_Clock_Source     */

  238. 

  239.   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source

  240.                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */

  241. 

  242.   uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source

  243.                                         This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */

  244. 

  245.   uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source

  246.                                         This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */

  247. 

  248.   uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source

  249.                                         This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */

  250. 

  251.   uint32_t Lptim345ClockSelection;   /*!< Specifies LPTIM3/4/5 clock source

  252.                                           This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source  */

  253. 

  254.   uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source

  255.                                         This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */

  256. #if defined(SAI4)

  257.   uint32_t Sai4AClockSelection;     /*!< Specifies SAI4A clock source

  258.                                         This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source   */

  259. 

  260.   uint32_t Sai4BClockSelection;     /*!< Specifies SAI4B clock source

  261.                                         This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source   */

  262. #endif /* SAI4 */

  263. 

  264.   uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source

  265.                                         This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */

  266. 

  267.   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source

  268.                                         This parameter can be a value of @ref RCC_RTC_Clock_Source       */

  269. 

  270. #if defined(HRTIM1)

  271.   uint32_t Hrtim1ClockSelection;      /*!< Specifies HRTIM1 Clock clock source

  272.                                         This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source   */

  273. #endif /* HRTIM1 */

  274. 

  275.   uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.

  276.                                        This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */

  277. }RCC_PeriphCLKInitTypeDef;

  278. 

  279. 

  280. /**

  281.   * @brief RCC_CRS Init structure definition

  282.   */

  283. typedef struct

  284. {

  285.   uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.

  286.                                      This parameter can be a value of @ref RCCEx_CRS_SynchroDivider  */

  287. 

  288.   uint32_t Source;                /*!< Specifies the SYNC signal source.

  289.                                      This parameter can be a value of @ref RCCEx_CRS_SynchroSource   */

  290. 

  291.   uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.

  292.                                      This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */

  293. 

  294.   uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.

  295.                                       It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)

  296.                                      This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/

  297. 

  298.   uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.

  299.                                      This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */

  300. 

  301.   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.

  302.                                      This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */

  303. 

  304. }RCC_CRSInitTypeDef;

  305. 

  306. /**

  307.   * @brief RCC_CRS Synchronization structure definition

  308.   */

  309. typedef struct

  310. {

  311.   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.

  312.                                      This parameter must be a number between 0 and 0xFFFF */

  313. 

  314.   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.

  315.                                      This parameter must be a number between 0 and 0x3F */

  316. 

  317.   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter

  318.                                                                     value latched in the time of the last SYNC event.

  319.                                     This parameter must be a number between 0 and 0xFFFF */

  320. 

  321.   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the

  322.                                                                     frequency error counter latched in the time of the last SYNC event.

  323.                                                                     It shows whether the actual frequency is below or above the target.

  324.                                     This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/

  325. 

  326. }RCC_CRSSynchroInfoTypeDef;

  327. 

  328. /**

  329.   * @}

  330.   */

  331. 

  332. 

  333. /* Exported constants --------------------------------------------------------*/

  334. /** @defgroup RCCEx_Exported_Constants  RCCEx Exported Constants

  335.   * @{

  336.   */

  337. 

  338. /** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection

  339.   * @{

  340.   */

  341. 

  342. #if defined(UART9) && defined(USART10)

  343. #define RCC_PERIPHCLK_USART16910       (0x00000001U)

  344. #define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910

  345. #define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910

  346. #define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910

  347. #define RCC_PERIPHCLK_USART10          RCC_PERIPHCLK_USART16910

  348. /*alias*/

  349. #define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910

  350. #else

  351. #define RCC_PERIPHCLK_USART16          (0x00000001U)

  352. #define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16

  353. #define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16

  354. /* alias */

  355. #define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16

  356. #endif /* UART9 && USART10*/

  357. #define RCC_PERIPHCLK_USART234578      (0x00000002U)

  358. #define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578

  359. #define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578

  360. #define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578

  361. #define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578

  362. #define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578

  363. #define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578

  364. #define RCC_PERIPHCLK_LPUART1          (0x00000004U)

  365. #define RCC_PERIPHCLK_I2C123           (0x00000008U)

  366. #define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123

  367. #define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123

  368. #define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123

  369. #define RCC_PERIPHCLK_I2C4             (0x00000010U)

  370. #define RCC_PERIPHCLK_LPTIM1           (0x00000020U)

  371. #define RCC_PERIPHCLK_LPTIM2           (0x00000040U)

  372. #define RCC_PERIPHCLK_LPTIM345         (0x00000080U)

  373. #define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345

  374. #if defined(LPTIM4)

  375. #define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345

  376. #endif /*LPTIM4*/

  377. #if defined(LPTIM5)

  378. #define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345

  379. #endif /*LPTIM5*/

  380. #define RCC_PERIPHCLK_SAI1             (0x00000100U)

  381. #if defined(SAI3)

  382. #define RCC_PERIPHCLK_SAI23            (0x00000200U)

  383. #define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23

  384. #define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23

  385. #endif /* SAI3 */

  386. #if defined(RCC_CDCCIP1R_SAI2ASEL_0)

  387. #define RCC_PERIPHCLK_SAI2A            (0x00000200U)

  388. #endif /* RCC_CDCCIP1R_SAI2ASEL_0 */

  389. #if defined(RCC_CDCCIP1R_SAI2BSEL_0)

  390. #define RCC_PERIPHCLK_SAI2B            (0x00000400U)

  391. #endif /* RCC_CDCCIP1R_SAI2BSEL_0 */

  392. #if defined(SAI4)

  393. #define RCC_PERIPHCLK_SAI4A            (0x00000400U)

  394. #define RCC_PERIPHCLK_SAI4B            (0x00000800U)

  395. #endif /* SAI4 */

  396. #define RCC_PERIPHCLK_SPI123           (0x00001000U)

  397. #define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123

  398. #define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123

  399. #define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123

  400. #define RCC_PERIPHCLK_SPI45            (0x00002000U)

  401. #define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45

  402. #define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45

  403. #define RCC_PERIPHCLK_SPI6             (0x00004000U)

  404. #define RCC_PERIPHCLK_FDCAN            (0x00008000U)

  405. #define RCC_PERIPHCLK_SDMMC            (0x00010000U)

  406. #define RCC_PERIPHCLK_RNG              (0x00020000U)

  407. #define RCC_PERIPHCLK_USB              (0x00040000U)

  408. #define RCC_PERIPHCLK_ADC              (0x00080000U)

  409. #define RCC_PERIPHCLK_SWPMI1           (0x00100000U)

  410. #define RCC_PERIPHCLK_DFSDM1           (0x00200000U)

  411. #if defined(DFSDM2_BASE)

  412. #define RCC_PERIPHCLK_DFSDM2           (0x00000800U)

  413. #endif /* DFSDM2 */

  414. #define RCC_PERIPHCLK_RTC              (0x00400000U)

  415. #define RCC_PERIPHCLK_CEC              (0x00800000U)

  416. #define RCC_PERIPHCLK_FMC              (0x01000000U)

  417. #if defined(QUADSPI)

  418. #define RCC_PERIPHCLK_QSPI             (0x02000000U)

  419. #endif /* QUADSPI */

  420. #if defined(OCTOSPI1) || defined(OCTOSPI2)

  421. #define RCC_PERIPHCLK_OSPI             (0x02000000U)

  422. #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

  423. #define RCC_PERIPHCLK_DSI              (0x04000000U)

  424. #define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)

  425. #if defined(HRTIM1)

  426. #define RCC_PERIPHCLK_HRTIM1           (0x10000000U)

  427. #endif /* HRTIM1 */

  428. #if defined(LTDC)

  429. #define RCC_PERIPHCLK_LTDC             (0x20000000U)

  430. #endif /* LTDC */

  431. #define RCC_PERIPHCLK_TIM              (0x40000000U)

  432. #define RCC_PERIPHCLK_CKPER            (0x80000000U)

  433. 

  434. /**

  435.   * @}

  436.   */

  437. 

  438. 

  439. /** @defgroup RCC_PLL2_Clock_Output  RCC PLL2 Clock Output

  440.   * @{

  441.   */

  442. #define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN

  443. #define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN

  444. #define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN

  445. 

  446. /**

  447.   * @}

  448.   */

  449. 

  450. /** @defgroup RCC_PLL3_Clock_Output  RCC PLL3 Clock Output

  451.   * @{

  452.   */

  453. #define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN

  454. #define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN

  455. #define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN

  456. 

  457. /**

  458.   * @}

  459.   */

  460. 

  461. /** @defgroup RCC_PLL2_VCI_Range  RCC PLL2 VCI Range

  462.   * @{

  463.   */

  464. #define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0

  465. #define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1

  466. #define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2

  467. #define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3

  468. 

  469. /**

  470.   * @}

  471.   */

  472. 

  473. 

  474. /** @defgroup RCC_PLL2_VCO_Range  RCC PLL2 VCO Range

  475.   * @{

  476.   */

  477. #define RCC_PLL2VCOWIDE                 (0x00000000U)

  478. #define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL

  479. 

  480. /**

  481.   * @}

  482.   */

  483. 

  484. /** @defgroup RCC_PLL3_VCI_Range  RCC PLL3 VCI Range

  485.   * @{

  486.   */

  487. #define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0

  488. #define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1

  489. #define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2

  490. #define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3

  491. 

  492. /**

  493.   * @}

  494.   */

  495. 

  496. 

  497. /** @defgroup RCC_PLL3_VCO_Range  RCC PLL3 VCO Range

  498.   * @{

  499.   */

  500. #define RCC_PLL3VCOWIDE                 (0x00000000U)

  501. #define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL

  502. 

  503. /**

  504.   * @}

  505.   */

  506. 

  507. /** @defgroup RCCEx_USART16_Clock_Source  RCCEx USART1/6 Clock Source

  508.   * @{

  509.   */

  510. #if defined(RCC_D2CCIP2R_USART16SEL)

  511. #define RCC_USART16CLKSOURCE_D2PCLK2    (0x00000000U)

  512. /* alias */

  513. #define RCC_USART16CLKSOURCE_PCLK2        RCC_USART16CLKSOURCE_D2PCLK2

  514. #define RCC_USART16CLKSOURCE_PLL2         RCC_D2CCIP2R_USART16SEL_0

  515. #define RCC_USART16CLKSOURCE_PLL3         RCC_D2CCIP2R_USART16SEL_1

  516. #define RCC_USART16CLKSOURCE_HSI         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)

  517. #define RCC_USART16CLKSOURCE_CSI          RCC_D2CCIP2R_USART16SEL_2

  518. #define RCC_USART16CLKSOURCE_LSE         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)

  519. 

  520. #else

  521. #define RCC_USART16910CLKSOURCE_CDPCLK2   (0x00000000U)

  522. /* alias */

  523. #define RCC_USART16910CLKSOURCE_D2PCLK2   RCC_USART16910CLKSOURCE_CDPCLK2

  524. #define RCC_USART16910CLKSOURCE_PLL2      RCC_CDCCIP2R_USART16910SEL_0

  525. #define RCC_USART16910CLKSOURCE_PLL3      RCC_CDCCIP2R_USART16910SEL_1

  526. #define RCC_USART16910CLKSOURCE_HSI      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)

  527. #define RCC_USART16910CLKSOURCE_CSI       RCC_CDCCIP2R_USART16910SEL_2

  528. #define RCC_USART16910CLKSOURCE_LSE      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)

  529. 

  530. /*  Aliases */

  531. #define RCC_USART16CLKSOURCE_CDPCLK2     RCC_USART16910CLKSOURCE_CDPCLK2

  532. #define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16CLKSOURCE_CDPCLK2

  533. #define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16CLKSOURCE_CDPCLK2

  534. #define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2

  535. #define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3

  536. #define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI

  537. #define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI

  538. #define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE

  539. #endif /* RCC_D2CCIP2R_USART16SEL */

  540. /**

  541.   * @}

  542.   */

  543. 

  544. /** @defgroup RCCEx_USART1_Clock_Source  RCCEx USART1 Clock Source

  545.   * @{

  546.   */

  547. #define RCC_USART1CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

  548. #define RCC_USART1CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

  549. #define RCC_USART1CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

  550. #define RCC_USART1CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

  551. #define RCC_USART1CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

  552. #define RCC_USART1CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

  553. /**

  554.   * @}

  555.   */

  556. 

  557. /** @defgroup RCCEx_USART6_Clock_Source  RCCEx USART6 Clock Source

  558.   * @{

  559.   */

  560. #define RCC_USART6CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

  561. #define RCC_USART6CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

  562. #define RCC_USART6CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

  563. #define RCC_USART6CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

  564. #define RCC_USART6CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

  565. #define RCC_USART6CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

  566. 

  567. /**

  568.   * @}

  569.   */

  570. 

  571. #if defined(UART9)

  572. /** @defgroup RCCEx_UART9_Clock_Source  RCCEx UART9 Clock Source

  573.   * @{

  574.   */

  575. #define RCC_UART9CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

  576. #define RCC_UART9CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

  577. #define RCC_UART9CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

  578. #define RCC_UART9CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

  579. #define RCC_UART9CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

  580. #define RCC_UART9CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

  581. /**

  582.   * @}

  583.   */

  584. #endif /* UART9 */

  585. 

  586. #if defined(USART10)

  587. /** @defgroup RCCEx_USART10_Clock_Source  RCCEx USART10 Clock Source

  588.   * @{

  589.   */

  590. #define RCC_USART10CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

  591. #define RCC_USART10CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

  592. #define RCC_USART10CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

  593. #define RCC_USART10CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

  594. #define RCC_USART10CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

  595. #define RCC_USART10CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

  596. /**

  597.   * @}

  598.   */

  599. #endif /* USART10 */

  600. 

  601. /** @defgroup RCCEx_USART234578_Clock_Source  RCCEx USART2/3/4/5/7/8 Clock Source

  602.   * @{

  603.   */

  604. #if defined(RCC_D2CCIP2R_USART28SEL)

  605. #define RCC_USART234578CLKSOURCE_D2PCLK1    (0x00000000U)

  606. /* alias */

  607. #define RCC_USART234578CLKSOURCE_PCLK1      RCC_USART234578CLKSOURCE_D2PCLK1

  608. #define RCC_USART234578CLKSOURCE_PLL2       RCC_D2CCIP2R_USART28SEL_0

  609. #define RCC_USART234578CLKSOURCE_PLL3       RCC_D2CCIP2R_USART28SEL_1

  610. #define RCC_USART234578CLKSOURCE_HSI        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

  611. #define RCC_USART234578CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2

  612. #define RCC_USART234578CLKSOURCE_LSE        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

  613. #else

  614. #define RCC_USART234578CLKSOURCE_CDPCLK1   (0x00000000U)

  615. /* alias */

  616. #define RCC_USART234578CLKSOURCE_PCLK1     RCC_USART234578CLKSOURCE_CDPCLK1

  617. #define RCC_USART234578CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_CDPCLK1

  618. #define RCC_USART234578CLKSOURCE_PLL2      RCC_CDCCIP2R_USART234578SEL_0

  619. #define RCC_USART234578CLKSOURCE_PLL3      RCC_CDCCIP2R_USART234578SEL_1

  620. #define RCC_USART234578CLKSOURCE_HSI      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)

  621. #define RCC_USART234578CLKSOURCE_CSI       RCC_CDCCIP2R_USART234578SEL_2

  622. #define RCC_USART234578CLKSOURCE_LSE      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)

  623. #endif /* RCC_D2CCIP2R_USART28SEL */

  624. /**

  625.   * @}

  626.   */

  627. 

  628. /** @defgroup RCCEx_USART2_Clock_Source  RCCEx USART2 Clock Source

  629.   * @{

  630.   */

  631. #define RCC_USART2CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

  632. #define RCC_USART2CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

  633. #define RCC_USART2CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

  634. #define RCC_USART2CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

  635. #define RCC_USART2CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

  636. #define RCC_USART2CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

  637. 

  638. /**

  639.   * @}

  640.   */

  641. 

  642. /** @defgroup RCCEx_USART3_Clock_Source  RCCEx USART3 Clock Source

  643.   * @{

  644.   */

  645. #define RCC_USART3CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

  646. #define RCC_USART3CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

  647. #define RCC_USART3CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

  648. #define RCC_USART3CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

  649. #define RCC_USART3CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

  650. #define RCC_USART3CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

  651. 

  652. /**

  653.   * @}

  654.   */

  655. 

  656. /** @defgroup RCCEx_UART4_Clock_Source  RCCEx UART4 Clock Source

  657.   * @{

  658.   */

  659. #define RCC_UART4CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

  660. #define RCC_UART4CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

  661. #define RCC_UART4CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

  662. #define RCC_UART4CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

  663. #define RCC_UART4CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

  664. #define RCC_UART4CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

  665. 

  666. /**

  667.   * @}

  668.   */

  669. 

  670. /** @defgroup RCCEx_UART5_Clock_Source  RCCEx UART5 Clock Source

  671.   * @{

  672.   */

  673. #define RCC_UART5CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

  674. #define RCC_UART5CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

  675. #define RCC_UART5CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

  676. #define RCC_UART5CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

  677. #define RCC_UART5CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

  678. #define RCC_UART5CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

  679. 

  680. /**

  681.   * @}

  682.   */

  683. 

  684. /** @defgroup RCCEx_UART7_Clock_Source  RCCEx UART7 Clock Source

  685.   * @{

  686.   */

  687. #define RCC_UART7CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

  688. #define RCC_UART7CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

  689. #define RCC_UART7CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

  690. #define RCC_UART7CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

  691. #define RCC_UART7CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

  692. #define RCC_UART7CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

  693. 

  694. /**

  695.   * @}

  696.   */

  697. 

  698. /** @defgroup RCCEx_UART8_Clock_Source  RCCEx UART8 Clock Source

  699.   * @{

  700.   */

  701. #define RCC_UART8CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

  702. #define RCC_UART8CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

  703. #define RCC_UART8CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

  704. #define RCC_UART8CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

  705. #define RCC_UART8CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

  706. #define RCC_UART8CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

  707. 

  708. /**

  709.   * @}

  710.   */

  711. 

  712. /** @defgroup RCCEx_LPUART1_Clock_Source  RCCEx LPUART1 Clock Source

  713.   * @{

  714.   */

  715. #if defined(RCC_D3CCIPR_LPUART1SEL)

  716. #define RCC_LPUART1CLKSOURCE_D3PCLK1    (0x00000000U)

  717. /* alias */

  718. #define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_D3PCLK1

  719. #define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0

  720. #define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1

  721. #define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)

  722. #define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2

  723. #define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)

  724. #else

  725. #define RCC_LPUART1CLKSOURCE_SRDPCLK4   (0x00000000U)

  726. /* alias*/

  727. #define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_SRDPCLK4

  728. #define RCC_LPUART1CLKSOURCE_D3PCLK1   RCC_LPUART1CLKSOURCE_SRDPCLK4

  729. #define RCC_LPUART1CLKSOURCE_PLL2      RCC_SRDCCIPR_LPUART1SEL_0

  730. #define RCC_LPUART1CLKSOURCE_PLL3      RCC_SRDCCIPR_LPUART1SEL_1

  731. #define RCC_LPUART1CLKSOURCE_HSI       (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)

  732. #define RCC_LPUART1CLKSOURCE_CSI        RCC_SRDCCIPR_LPUART1SEL_2

  733. #define RCC_LPUART1CLKSOURCE_LSE       (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)

  734. #endif /* RCC_D3CCIPR_LPUART1SEL */

  735. /**

  736.   * @}

  737.   */

  738. 

  739. /** @defgroup RCCEx_I2C123_Clock_Source  RCCEx I2C1/2/3 Clock Source

  740.   * @{

  741.   */

  742. #if defined (RCC_D2CCIP2R_I2C123SEL)

  743. #define RCC_I2C123CLKSOURCE_D2PCLK1      (0x00000000U)

  744. #define RCC_I2C123CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0

  745. #define RCC_I2C123CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1

  746. #define RCC_I2C123CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

  747. #else

  748. #define RCC_I2C123CLKSOURCE_CDPCLK1      (0x00000000U)

  749. /* alias */

  750. #define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C123CLKSOURCE_CDPCLK1

  751. #define RCC_I2C123CLKSOURCE_PLL3         RCC_CDCCIP2R_I2C123SEL_0

  752. #define RCC_I2C123CLKSOURCE_HSI          RCC_CDCCIP2R_I2C123SEL_1

  753. #define RCC_I2C123CLKSOURCE_CSI         (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)

  754. #endif /* RCC_D2CCIP2R_I2C123SEL */

  755. /**

  756.   * @}

  757.   */

  758. 

  759. /** @defgroup RCCEx_I2C1_Clock_Source  RCCEx I2C1 Clock Source

  760.   * @{

  761.   */

  762. #define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

  763. #define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

  764. #define RCC_I2C1CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

  765. #define RCC_I2C1CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

  766. 

  767. /**

  768.   * @}

  769.   */

  770. 

  771. /** @defgroup RCCEx_I2C2_Clock_Source  RCCEx I2C2 Clock Source

  772.   * @{

  773.   */

  774. #define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

  775. #define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

  776. #define RCC_I2C2CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

  777. #define RCC_I2C2CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

  778. 

  779. /**

  780.   * @}

  781.   */

  782. 

  783. /** @defgroup RCCEx_I2C3_Clock_Source  RCCEx I2C3 Clock Source

  784.   * @{

  785.   */

  786. #define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

  787. #define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

  788. #define RCC_I2C3CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

  789. #define RCC_I2C3CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

  790. 

  791. /**

  792.   * @}

  793.   */

  794. 

  795. /** @defgroup RCCEx_I2C4_Clock_Source  RCCEx I2C4 Clock Source

  796.   * @{

  797.   */

  798. #if defined(RCC_D3CCIPR_I2C4SEL)

  799. #define RCC_I2C4CLKSOURCE_D3PCLK1      (0x00000000U)

  800. #define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0

  801. #define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1

  802. #define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)

  803. #else

  804. #define RCC_I2C4CLKSOURCE_SRDPCLK4     (0x00000000U)

  805. /* alias */

  806. #define RCC_I2C4CLKSOURCE_D3PCLK1     RCC_I2C4CLKSOURCE_SRDPCLK4

  807. #define RCC_I2C4CLKSOURCE_PLL3         RCC_SRDCCIPR_I2C4SEL_0

  808. #define RCC_I2C4CLKSOURCE_HSI          RCC_SRDCCIPR_I2C4SEL_1

  809. #define RCC_I2C4CLKSOURCE_CSI         (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)

  810. #endif /* RCC_D3CCIPR_I2C4SEL */

  811. 

  812. /**

  813.   * @}

  814.   */

  815. 

  816. /** @defgroup RCCEx_RNG_Clock_Source  RCCEx RNG Clock Source

  817.   * @{

  818.   */

  819. #if defined(RCC_D2CCIP2R_RNGSEL)

  820. #define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)

  821. #define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0

  822. #define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1

  823. #define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL

  824. #else

  825. #define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)

  826. #define RCC_RNGCLKSOURCE_PLL           RCC_CDCCIP2R_RNGSEL_0

  827. #define RCC_RNGCLKSOURCE_LSE           RCC_CDCCIP2R_RNGSEL_1

  828. #define RCC_RNGCLKSOURCE_LSI           RCC_CDCCIP2R_RNGSEL

  829. #endif /* RCC_D2CCIP2R_RNGSEL */

  830. 

  831. /**

  832.   * @}

  833.   */

  834. #if defined(HRTIM1)

  835. 

  836. /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source

  837.   * @{

  838.   */

  839. #define RCC_HRTIM1CLK_TIMCLK                (0x00000000U)

  840. #define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL

  841. 

  842. /**

  843.   * @}

  844.   */

  845. #endif /*HRTIM1*/

  846. 

  847. /** @defgroup RCCEx_USB_Clock_Source  RCCEx USB Clock Source

  848.   * @{

  849.   */

  850. #if defined(RCC_D2CCIP2R_USBSEL)

  851. #define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0

  852. #define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1

  853. #define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL

  854. #else

  855. #define RCC_USBCLKSOURCE_PLL                  RCC_CDCCIP2R_USBSEL_0

  856. #define RCC_USBCLKSOURCE_PLL3                 RCC_CDCCIP2R_USBSEL_1

  857. #define RCC_USBCLKSOURCE_HSI48                RCC_CDCCIP2R_USBSEL

  858. #endif /* RCC_D2CCIP2R_USBSEL */

  859. 

  860. /**

  861.   * @}

  862.   */

  863. 

  864. /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source

  865.   * @{

  866.   */

  867. #if defined(RCC_D2CCIP1R_SAI1SEL)

  868. #define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)

  869. #define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0

  870. #define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1

  871. #define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)

  872. #define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2

  873. #else

  874. #define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)

  875. #define RCC_SAI1CLKSOURCE_PLL2         RCC_CDCCIP1R_SAI1SEL_0

  876. #define RCC_SAI1CLKSOURCE_PLL3         RCC_CDCCIP1R_SAI1SEL_1

  877. #define RCC_SAI1CLKSOURCE_PIN         (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)

  878. #define RCC_SAI1CLKSOURCE_CLKP         RCC_CDCCIP1R_SAI1SEL_2

  879. #endif /* RCC_D2CCIP1R_SAI1SEL */

  880. /**

  881.   * @}

  882.   */

  883. 

  884. #if defined(SAI3)

  885. /** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source

  886.   * @{

  887.   */

  888. #define RCC_SAI23CLKSOURCE_PLL         (0x00000000U)

  889. #define RCC_SAI23CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0

  890. #define RCC_SAI23CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1

  891. #define RCC_SAI23CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)

  892. #define RCC_SAI23CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2

  893. /**

  894.   * @}

  895.   */

  896. 

  897. /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source

  898.   * @{

  899.   */

  900. #define RCC_SAI2CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL

  901. #define RCC_SAI2CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2

  902. #define RCC_SAI2CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3

  903. #define RCC_SAI2CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN

  904. #define RCC_SAI2CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP

  905. 

  906. /**

  907.   * @}

  908.   */

  909. 

  910. /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source

  911.   * @{

  912.   */

  913. #define RCC_SAI3CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL

  914. #define RCC_SAI3CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2

  915. #define RCC_SAI3CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3

  916. #define RCC_SAI3CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN

  917. #define RCC_SAI3CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP

  918. /**

  919.   * @}

  920.   */

  921. #endif /* SAI3 */

  922. 

  923. #if defined(RCC_CDCCIP1R_SAI2ASEL)

  924. /** @defgroup RCCEx_SAI2_Clock_A Source SAI2A Clock Source

  925.   * @{

  926.   */

  927. #define RCC_SAI2ACLKSOURCE_PLL         (0x00000000U)

  928. #define RCC_SAI2ACLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2ASEL_0

  929. #define RCC_SAI2ACLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2ASEL_1

  930. #define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)

  931. #define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2

  932. #define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)

  933.  /**

  934.   * @}

  935.   */

  936. #endif /* RCC_CDCCIP1R_SAI2ASEL */

  937. 

  938. #if defined(RCC_CDCCIP1R_SAI2BSEL)

  939. /** @defgroup RCCEx_SAI2_Block_B Clock_Source SAI2B Clock Source

  940.   * @{

  941.   */

  942. #define RCC_SAI2BCLKSOURCE_PLL         (0x00000000U)

  943. #define RCC_SAI2BCLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2BSEL_0

  944. #define RCC_SAI2BCLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2BSEL_1

  945. #define RCC_SAI2BCLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)

  946. #define RCC_SAI2BCLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2BSEL_2

  947. #define RCC_SAI2BCLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)

  948. /**

  949.   * @}

  950.   */

  951. #endif /* RCC_CDCCIP1R_SAI2BSEL */

  952. 

  953. 

  954. /** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source

  955.   * @{

  956.   */

  957. #if defined(RCC_D2CCIP1R_SPI123SEL)

  958. #define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)

  959. #define RCC_SPI123CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0

  960. #define RCC_SPI123CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1

  961. #define RCC_SPI123CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)

  962. #define RCC_SPI123CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2

  963. #else

  964. #define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)

  965. #define RCC_SPI123CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI123SEL_0

  966. #define RCC_SPI123CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI123SEL_1

  967. #define RCC_SPI123CLKSOURCE_PIN         (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)

  968. #define RCC_SPI123CLKSOURCE_CLKP         RCC_CDCCIP1R_SPI123SEL_2

  969. #endif /* RCC_D2CCIP1R_SPI123SEL */

  970. /**

  971.   * @}

  972.   */

  973. 

  974. /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source

  975.   * @{

  976.   */

  977. #define RCC_SPI1CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

  978. #define RCC_SPI1CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

  979. #define RCC_SPI1CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

  980. #define RCC_SPI1CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

  981. #define RCC_SPI1CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP

  982. 

  983. /**

  984.   * @}

  985.   */

  986. 

  987. /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source

  988.   * @{

  989.   */

  990. #define RCC_SPI2CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

  991. #define RCC_SPI2CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

  992. #define RCC_SPI2CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

  993. #define RCC_SPI2CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

  994. #define RCC_SPI2CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP

  995. 

  996. /**

  997.   * @}

  998.   */

  999. 

  1000. /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source

  1001.   * @{

  1002.   */

  1003. #define RCC_SPI3CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

  1004. #define RCC_SPI3CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

  1005. #define RCC_SPI3CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

  1006. #define RCC_SPI3CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

  1007. #define RCC_SPI3CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP

  1008. 

  1009. /**

  1010.   * @}

  1011.   */

  1012. 

  1013. /** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source

  1014.   * @{

  1015.   */

  1016. #if defined(RCC_D2CCIP1R_SPI45SEL)

  1017. #define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)

  1018. #define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1

  1019. #define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0

  1020. #define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1

  1021. #define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)

  1022. #define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2

  1023. #define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

  1024. #else

  1025. #define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)

  1026. /* aliases */

  1027. #define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

  1028. #define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1

  1029. #define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0

  1030. #define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1

  1031. #define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)

  1032. #define RCC_SPI45CLKSOURCE_CSI          RCC_CDCCIP1R_SPI45SEL_2

  1033. #define RCC_SPI45CLKSOURCE_HSE         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)

  1034. #endif /* RCC_D2CCIP1R_SPI45SEL */

  1035. /**

  1036.   * @}

  1037.   */

  1038. 

  1039. /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source

  1040.   * @{

  1041.   */

  1042. #define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1

  1043. #define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2

  1044. #define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3

  1045. #define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI

  1046. #define RCC_SPI4CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI

  1047. #define RCC_SPI4CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE

  1048. 

  1049. /**

  1050.   * @}

  1051.   */

  1052. 

  1053. /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source

  1054.   * @{

  1055.   */

  1056. #define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1

  1057. #define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2

  1058. #define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3

  1059. #define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI

  1060. #define RCC_SPI5CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI

  1061. #define RCC_SPI5CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE

  1062. 

  1063. /**

  1064.   * @}

  1065.   */

  1066. 

  1067. /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source

  1068.   * @{

  1069.   */

  1070. #if defined(RCC_D3CCIPR_SPI6SEL)

  1071. #define RCC_SPI6CLKSOURCE_D3PCLK1     (0x00000000U)

  1072. #define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_D3PCLK1

  1073. #define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0

  1074. #define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1

  1075. #define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)

  1076. #define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2

  1077. #define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)

  1078. #else

  1079. #define RCC_SPI6CLKSOURCE_SRDPCLK4    (0x00000000U)

  1080. /* alias */

  1081. #define RCC_SPI6CLKSOURCE_D3PCLK1      RCC_SPI6CLKSOURCE_SRDPCLK4  /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

  1082. #define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_SRDPCLK4

  1083. #define RCC_SPI6CLKSOURCE_PLL2         RCC_SRDCCIPR_SPI6SEL_0

  1084. #define RCC_SPI6CLKSOURCE_PLL3         RCC_SRDCCIPR_SPI6SEL_1

  1085. #define RCC_SPI6CLKSOURCE_HSI         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

  1086. #define RCC_SPI6CLKSOURCE_CSI          RCC_SRDCCIPR_SPI6SEL_2

  1087. #define RCC_SPI6CLKSOURCE_HSE         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

  1088. #define RCC_SPI6CLKSOURCE_PIN         (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

  1089. #endif /* RCC_D3CCIPR_SPI6SEL */

  1090. 

  1091. /**

  1092.   * @}

  1093.   */

  1094. 

  1095. 

  1096. #if defined(SAI4_Block_A)

  1097. /** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source

  1098.   * @{

  1099.   */

  1100. #define RCC_SAI4ACLKSOURCE_PLL         (0x00000000U)

  1101. #define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0

  1102. #define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1

  1103. #define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)

  1104. #define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2

  1105. 

  1106. /**

  1107.   * @}

  1108.   */

  1109. #endif /* SAI4_Block_A */

  1110. 

  1111. 

  1112. 

  1113. #if defined(SAI4_Block_B)

  1114. /** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source

  1115.   * @{

  1116.   */

  1117. #define RCC_SAI4BCLKSOURCE_PLL         (0x00000000U)

  1118. #define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0

  1119. #define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1

  1120. #define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)

  1121. #define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2

  1122. 

  1123. /**

  1124.   * @}

  1125.   */

  1126. #endif /* SAI4_Block_B */

  1127. 

  1128. 

  1129. /** @defgroup RCCEx_LPTIM1_Clock_Source  RCCEx LPTIM1 Clock Source

  1130.   * @{

  1131.   */

  1132. #if defined(RCC_D2CCIP2R_LPTIM1SEL)

  1133. #define RCC_LPTIM1CLKSOURCE_D2PCLK1        (0x00000000U)

  1134. /* alias */

  1135. #define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_D2PCLK1

  1136. #define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0

  1137. #define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1

  1138. #define RCC_LPTIM1CLKSOURCE_LSE          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)

  1139. #define RCC_LPTIM1CLKSOURCE_LSI           RCC_D2CCIP2R_LPTIM1SEL_2

  1140. #define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)

  1141. #else

  1142. #define RCC_LPTIM1CLKSOURCE_CDPCLK1        (0x00000000U)

  1143. /* alias */

  1144. #define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_CDPCLK1

  1145. #define RCC_LPTIM1CLKSOURCE_D2PCLK1       RCC_LPTIM1CLKSOURCE_CDPCLK1

  1146. #define RCC_LPTIM1CLKSOURCE_PLL2          RCC_CDCCIP2R_LPTIM1SEL_0

  1147. #define RCC_LPTIM1CLKSOURCE_PLL3          RCC_CDCCIP2R_LPTIM1SEL_1

  1148. #define RCC_LPTIM1CLKSOURCE_LSE          (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)

  1149. #define RCC_LPTIM1CLKSOURCE_LSI           RCC_CDCCIP2R_LPTIM1SEL_2

  1150. #define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)

  1151. #endif /* RCC_D2CCIP2R_LPTIM1SEL */

  1152. 

  1153. /**

  1154.   * @}

  1155.   */

  1156. 

  1157. /** @defgroup RCCEx_LPTIM2_Clock_Source  RCCEx LPTIM2 Clock Source

  1158.   * @{

  1159.   */

  1160. #if defined(RCC_D3CCIPR_LPTIM2SEL)

  1161. #define RCC_LPTIM2CLKSOURCE_D3PCLK1       (0x00000000U)

  1162. /* alias */

  1163. #define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_D3PCLK1

  1164. #define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0

  1165. #define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1

  1166. #define RCC_LPTIM2CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)

  1167. #define RCC_LPTIM2CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM2SEL_2

  1168. #define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)

  1169. #else

  1170. #define RCC_LPTIM2CLKSOURCE_SRDPCLK4       (0x00000000U)

  1171. /*alias*/

  1172. #define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_SRDPCLK4

  1173. #define RCC_LPTIM2CLKSOURCE_D3PCLK1       RCC_LPTIM2CLKSOURCE_SRDPCLK4

  1174. #define RCC_LPTIM2CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM2SEL_0

  1175. #define RCC_LPTIM2CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM2SEL_1

  1176. #define RCC_LPTIM2CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)

  1177. #define RCC_LPTIM2CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM2SEL_2

  1178. #define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)

  1179. #endif /* RCC_D3CCIPR_LPTIM2SEL */

  1180. /**

  1181.   * @}

  1182.   */

  1183. 

  1184. /** @defgroup RCCEx_LPTIM345_Clock_Source  RCCEx LPTIM3/4/5 Clock Source

  1185.   * @{

  1186.   */

  1187. #if defined(RCC_D3CCIPR_LPTIM345SEL)

  1188. #define RCC_LPTIM345CLKSOURCE_D3PCLK1        (0x00000000U)

  1189. /* alias*/

  1190. #define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_D3PCLK1

  1191. #define RCC_LPTIM345CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0

  1192. #define RCC_LPTIM345CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1

  1193. #define RCC_LPTIM345CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)

  1194. #define RCC_LPTIM345CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2

  1195. #define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

  1196. #else

  1197. #define RCC_LPTIM345CLKSOURCE_SRDPCLK4      (0x00000000U)

  1198. /* alias */

  1199. #define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_SRDPCLK4

  1200. #define RCC_LPTIM345CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_SRDPCLK4

  1201. #define RCC_LPTIM345CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM3SEL_0

  1202. #define RCC_LPTIM345CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM3SEL_1

  1203. #define RCC_LPTIM345CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)

  1204. #define RCC_LPTIM345CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM3SEL_2

  1205. #define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

  1206. #endif /* RCC_D3CCIPR_LPTIM345SEL */

  1207. /**

  1208.   * @}

  1209.   */

  1210. 

  1211. /** @defgroup RCCEx_LPTIM3_Clock_Source  RCCEx LPTIM3 Clock Source

  1212.   * @{

  1213.   */

  1214. #define RCC_LPTIM3CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

  1215. #define RCC_LPTIM3CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

  1216. #define RCC_LPTIM3CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

  1217. #define RCC_LPTIM3CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

  1218. #define RCC_LPTIM3CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

  1219. #define RCC_LPTIM3CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP

  1220. 

  1221. /**

  1222.   * @}

  1223.   */

  1224. #if defined(LPTIM4)

  1225. /** @defgroup RCCEx_LPTIM4_Clock_Source  RCCEx LPTIM4 Clock Source

  1226.   * @{

  1227.   */

  1228. #define RCC_LPTIM4CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

  1229. #define RCC_LPTIM4CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

  1230. #define RCC_LPTIM4CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

  1231. #define RCC_LPTIM4CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

  1232. #define RCC_LPTIM4CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

  1233. #define RCC_LPTIM4CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP

  1234. /**

  1235.   * @}

  1236.   */

  1237. #endif /* LPTIM4 */

  1238. 

  1239. #if defined(LPTIM5)

  1240. /** @defgroup RCCEx_LPTIM5_Clock_Source  RCCEx LPTIM5 Clock Source

  1241.   * @{

  1242.   */

  1243. #define RCC_LPTIM5CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

  1244. #define RCC_LPTIM5CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

  1245. #define RCC_LPTIM5CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

  1246. #define RCC_LPTIM5CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

  1247. #define RCC_LPTIM5CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

  1248. #define RCC_LPTIM5CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP

  1249. 

  1250. /**

  1251.   * @}

  1252.   */

  1253. #endif /* LPTIM5 */

  1254. 

  1255. #if defined(QUADSPI)

  1256. /** @defgroup RCCEx_QSPI_Clock_Source  RCCEx QSPI Clock Source

  1257.   * @{

  1258.   */

  1259. #define RCC_QSPICLKSOURCE_D1HCLK       (0x00000000U)

  1260. #define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0

  1261. #define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1

  1262. #define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL

  1263. 

  1264. /**

  1265.   * @}

  1266.   */

  1267. #endif /* QUADSPI */

  1268. 

  1269. 

  1270. #if defined(OCTOSPI1) || defined(OCTOSPI2)

  1271. /** @defgroup RCCEx_OSPI_Clock_Source  RCCEx OSPI Clock Source

  1272.   * @{

  1273.   */

  1274. #define RCC_OSPICLKSOURCE_CDHCLK       (0x00000000U)

  1275. /*aliases*/

  1276. #define RCC_OSPICLKSOURCE_D1HCLK       RCC_OSPICLKSOURCE_CDHCLK

  1277. #define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_CDHCLK

  1278. #define RCC_OSPICLKSOURCE_PLL          RCC_CDCCIPR_OCTOSPISEL_0

  1279. #define RCC_OSPICLKSOURCE_PLL2         RCC_CDCCIPR_OCTOSPISEL_1

  1280. #define RCC_OSPICLKSOURCE_CLKP         RCC_CDCCIPR_OCTOSPISEL

  1281. 

  1282. /**

  1283.   * @}

  1284.   */

  1285. #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

  1286. 

  1287. #if defined(DSI)

  1288. /** @defgroup RCCEx_DSI_Clock_Source  RCCEx DSI Clock Source

  1289.   * @{

  1290.   */

  1291. #define RCC_DSICLKSOURCE_PHY       (0x00000000U)

  1292. #define RCC_DSICLKSOURCE_PLL2       RCC_D1CCIPR_DSISEL

  1293. 

  1294. /**

  1295.   * @}

  1296.   */

  1297. #endif /* DSI */

  1298. 

  1299. /** @defgroup RCCEx_FMC_Clock_Source  RCCEx FMC Clock Source

  1300.   * @{

  1301.   */

  1302. #if defined(RCC_D1CCIPR_FMCSEL)

  1303. #define RCC_FMCCLKSOURCE_D1HCLK       (0x00000000U)

  1304. #define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_D1HCLK

  1305. #define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0

  1306. #define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1

  1307. #define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL

  1308. #else

  1309. #define RCC_FMCCLKSOURCE_CDHCLK       (0x00000000U)

  1310. #define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_CDHCLK

  1311. /*alias*/

  1312. #define RCC_FMCCLKSOURCE_D1HCLK       RCC_FMCCLKSOURCE_CDHCLK

  1313. #define RCC_FMCCLKSOURCE_PLL          RCC_CDCCIPR_FMCSEL_0

  1314. #define RCC_FMCCLKSOURCE_PLL2         RCC_CDCCIPR_FMCSEL_1

  1315. #define RCC_FMCCLKSOURCE_CLKP         RCC_CDCCIPR_FMCSEL

  1316. #endif /* RCC_D1CCIPR_FMCSEL */

  1317. /**

  1318.   * @}

  1319.   */

  1320. 

  1321. #if defined(FDCAN1) || defined(FDCAN2)

  1322. /** @defgroup RCCEx_FDCAN_Clock_Source  RCCEx FDCAN Clock Source

  1323.   * @{

  1324.   */

  1325. #if defined(RCC_D2CCIP1R_FDCANSEL)

  1326. #define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)

  1327. #define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0

  1328. #define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1

  1329. #else

  1330. #define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)

  1331. #define RCC_FDCANCLKSOURCE_PLL          RCC_CDCCIP1R_FDCANSEL_0

  1332. #define RCC_FDCANCLKSOURCE_PLL2         RCC_CDCCIP1R_FDCANSEL_1

  1333. #endif /* D3_SRAM_BASE */

  1334. /**

  1335.   * @}

  1336.   */

  1337. #endif /*FDCAN1 || FDCAN2*/

  1338. 

  1339. 

  1340. /** @defgroup RCCEx_SDMMC_Clock_Source  RCCEx SDMMC Clock Source

  1341.   * @{

  1342.   */

  1343. #if defined(RCC_D1CCIPR_SDMMCSEL)

  1344. #define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)

  1345. #define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL

  1346. #else

  1347. #define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)

  1348. #define RCC_SDMMCCLKSOURCE_PLL2           RCC_CDCCIPR_SDMMCSEL

  1349. #endif /* RCC_D1CCIPR_SDMMCSEL */

  1350. /**

  1351.   * @}

  1352.   */

  1353. 

  1354. 

  1355. /** @defgroup RCCEx_ADC_Clock_Source  RCCEx ADC Clock Source

  1356.   * @{

  1357.   */

  1358. #if defined(RCC_D3CCIPR_ADCSEL_0)

  1359. #define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)

  1360. #define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0

  1361. #define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1

  1362. #else

  1363. #define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)

  1364. #define RCC_ADCCLKSOURCE_PLL3       RCC_SRDCCIPR_ADCSEL_0

  1365. #define RCC_ADCCLKSOURCE_CLKP       RCC_SRDCCIPR_ADCSEL_1

  1366. #endif /* RCC_D3CCIPR_ADCSEL_0  */

  1367. /**

  1368.   * @}

  1369.   */

  1370. 

  1371. /** @defgroup RCCEx_SWPMI1_Clock_Source  RCCEx SWPMI1 Clock Source

  1372.   * @{

  1373.   */

  1374. #if defined(RCC_D2CCIP1R_SWPSEL)

  1375. #define RCC_SWPMI1CLKSOURCE_D2PCLK1       (0x00000000U)

  1376. #define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL

  1377. #else

  1378. #define RCC_SWPMI1CLKSOURCE_CDPCLK1       (0x00000000U)

  1379. /* alias */

  1380. #define RCC_SWPMI1CLKSOURCE_D2PCLK1        RCC_SWPMI1CLKSOURCE_CDPCLK1

  1381. #define RCC_SWPMI1CLKSOURCE_HSI            RCC_CDCCIP1R_SWPSEL

  1382. #endif /* RCC_D2CCIP1R_SWPSEL */

  1383. /**

  1384.   * @}

  1385.   */

  1386. 

  1387. /** @defgroup RCCEx_DFSDM1_Clock_Source  RCCEx DFSDM1 Clock Source

  1388.   * @{

  1389.   */

  1390. #if defined(RCC_D2CCIP1R_DFSDM1SEL)

  1391. #define RCC_DFSDM1CLKSOURCE_D2PCLK1        (0x00000000U)

  1392. #define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL

  1393. #else

  1394. #define RCC_DFSDM1CLKSOURCE_CDPCLK1        (0x00000000U)

  1395. /* alias */

  1396. #define RCC_DFSDM1CLKSOURCE_D2PCLK1        RCC_DFSDM1CLKSOURCE_CDPCLK1

  1397. #define RCC_DFSDM1CLKSOURCE_SYS            RCC_CDCCIP1R_DFSDM1SEL

  1398. #endif /* RCC_D2CCIP1R_DFSDM1SEL */

  1399. /**

  1400.   * @}

  1401.   */

  1402. 

  1403. #if defined(DFSDM2_BASE)

  1404. /** @defgroup RCCEx_DFSDM2_Clock_Source  RCCEx DFSDM2 Clock Source

  1405.   * @{

  1406.   */

  1407. #define RCC_DFSDM2CLKSOURCE_SRDPCLK4       (0x00000000U)

  1408. /* alias */

  1409. #define RCC_DFSDM2CLKSOURCE_SRDPCLK1       RCC_DFSDM2CLKSOURCE_SRDPCLK4

  1410. #define RCC_DFSDM2CLKSOURCE_SYS            RCC_SRDCCIPR_DFSDM2SEL

  1411. /**

  1412.   * @}

  1413.   */

  1414. #endif /* DFSDM2 */

  1415. 

  1416. /** @defgroup RCCEx_SPDIFRX_Clock_Source  RCCEx SPDIFRX Clock Source

  1417.   * @{

  1418.   */

  1419. #if defined(RCC_D2CCIP1R_SPDIFSEL_0)

  1420. #define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)

  1421. #define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0

  1422. #define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1

  1423. #define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL

  1424. #else

  1425. #define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)

  1426. #define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_CDCCIP1R_SPDIFSEL_0

  1427. #define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_CDCCIP1R_SPDIFSEL_1

  1428. #define RCC_SPDIFRXCLKSOURCE_HSI        RCC_CDCCIP1R_SPDIFSEL

  1429. #endif /* RCC_D2CCIP1R_SPDIFSEL_0 */

  1430. /**

  1431.   * @}

  1432.   */

  1433. 

  1434. /** @defgroup RCCEx_CEC_Clock_Source  RCCEx CEC Clock Source

  1435.   * @{

  1436.   */

  1437. #if defined(RCC_D2CCIP2R_CECSEL_0)

  1438. #define RCC_CECCLKSOURCE_LSE        (0x00000000U)

  1439. #define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0

  1440. #define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1

  1441. #else

  1442. #define RCC_CECCLKSOURCE_LSE        (0x00000000U)

  1443. #define RCC_CECCLKSOURCE_LSI         RCC_CDCCIP2R_CECSEL_0

  1444. #define RCC_CECCLKSOURCE_CSI         RCC_CDCCIP2R_CECSEL_1

  1445. #endif /* RCC_D2CCIP2R_CECSEL_0 */

  1446. /**

  1447.   * @}

  1448.   */

  1449. 

  1450. 

  1451. /** @defgroup RCCEx_CLKP_Clock_Source  RCCEx CLKP Clock Source

  1452.   * @{

  1453.   */

  1454. #if defined(RCC_D1CCIPR_CKPERSEL_0)

  1455. #define RCC_CLKPSOURCE_HSI        (0x00000000U)

  1456. #define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0

  1457. #define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1

  1458. #else

  1459. #define RCC_CLKPSOURCE_HSI        (0x00000000U)

  1460. #define RCC_CLKPSOURCE_CSI         RCC_CDCCIPR_CKPERSEL_0

  1461. #define RCC_CLKPSOURCE_HSE         RCC_CDCCIPR_CKPERSEL_1

  1462. #endif /* RCC_D1CCIPR_CKPERSEL_0 */

  1463. /**

  1464.   * @}

  1465.   */

  1466. 

  1467. /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection

  1468.   * @{

  1469.   */

  1470. #define RCC_TIMPRES_DESACTIVATED        (0x00000000U)

  1471. #define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE

  1472. 

  1473. /**

  1474.   * @}

  1475.   */

  1476. 

  1477. #if defined(DUAL_CORE)

  1478. 

  1479. /** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx

  1480.   * @{

  1481.   */

  1482. #define RCC_BOOT_C1        RCC_GCR_BOOT_C1

  1483. #define RCC_BOOT_C2        RCC_GCR_BOOT_C2

  1484. 

  1485. /**

  1486.   * @}

  1487.   */

  1488. #endif /*DUAL_CORE*/

  1489. 

  1490. #if defined(DUAL_CORE)

  1491. /** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx

  1492.   * @{

  1493.   */

  1494. #define RCC_WWDG1        RCC_GCR_WW1RSC

  1495. #define RCC_WWDG2        RCC_GCR_WW2RSC

  1496. 

  1497. /**

  1498.   * @}

  1499.   */

  1500. 

  1501. #else

  1502. 

  1503. /** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx

  1504.   * @{

  1505.   */

  1506. #define RCC_WWDG1        RCC_GCR_WW1RSC

  1507. 

  1508. /**

  1509.   * @}

  1510.   */

  1511. 

  1512. #endif /*DUAL_CORE*/

  1513. 

  1514. /** @defgroup RCCEx_CRS_Status RCCEx CRS Status

  1515.   * @{

  1516.   */

  1517. #define RCC_CRS_NONE                   (0x00000000U)

  1518. #define RCC_CRS_TIMEOUT                (0x00000001U)

  1519. #define RCC_CRS_SYNCOK                 (0x00000002U)

  1520. #define RCC_CRS_SYNCWARN               (0x00000004U)

  1521. #define RCC_CRS_SYNCERR                (0x00000008U)

  1522. #define RCC_CRS_SYNCMISS               (0x00000010U)

  1523. #define RCC_CRS_TRIMOVF                (0x00000020U)

  1524. /**

  1525.   * @}

  1526.   */

  1527. 

  1528. /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource

  1529.   * @{

  1530.   */

  1531. #define RCC_CRS_SYNC_SOURCE_PIN       (0x00000000U)                            /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */

  1532. #define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0                      /*!< Synchro Signal source LSE */

  1533. #define RCC_CRS_SYNC_SOURCE_USB1       CRS_CFGR_SYNCSRC_1                      /*!< Synchro Signal source USB1 SOF (default) */

  1534. #define RCC_CRS_SYNC_SOURCE_USB2      (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)  /*!< Synchro Signal source USB2 SOF */

  1535. 

  1536. 

  1537. /**

  1538.   * @}

  1539.   */

  1540. 

  1541. /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider

  1542.   * @{

  1543.   */

  1544. #define RCC_CRS_SYNC_DIV1        (0x00000000U)           /*!< Synchro Signal not divided (default) */

  1545. #define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                         /*!< Synchro Signal divided by 2 */

  1546. #define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                         /*!< Synchro Signal divided by 4 */

  1547. #define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)  /*!< Synchro Signal divided by 8 */

  1548. #define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */

  1549. #define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */

  1550. #define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */

  1551. #define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                         /*!< Synchro Signal divided by 128 */

  1552. /**

  1553.   * @}

  1554.   */

  1555. 

  1556. /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity

  1557.   * @{

  1558.   */

  1559. #define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */

  1560. #define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */

  1561. /**

  1562.   * @}

  1563.   */

  1564. 

  1565. /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault

  1566.   * @{

  1567.   */

  1568. #define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds

  1569.                                                                     to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */

  1570. /**

  1571.   * @}

  1572.   */

  1573. 

  1574. /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault

  1575.   * @{

  1576.   */

  1577. #define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */

  1578. /**

  1579.   * @}

  1580.   */

  1581. 

  1582. /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault

  1583.   * @{

  1584.   */

  1585. #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.

  1586.                                                                       The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value

  1587.                                                                       corresponds to a higher output frequency */

  1588. /**

  1589.   * @}

  1590.   */

  1591. 

  1592. /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection

  1593.   * @{

  1594.   */

  1595. #define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */

  1596. #define RCC_CRS_FREQERRORDIR_DOWN      (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */

  1597. /**

  1598.   * @}

  1599.   */

  1600. 

  1601. /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources

  1602.   * @{

  1603.   */

  1604. #define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */

  1605. #define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */

  1606. #define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */

  1607. #define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */

  1608. #define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */

  1609. #define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */

  1610. #define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE          /*!< Trimming overflow or underflow */

  1611. 

  1612. /**

  1613.   * @}

  1614.   */

  1615. 

  1616. /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags

  1617.   * @{

  1618.   */

  1619. #define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */

  1620. #define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */

  1621. #define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */

  1622. #define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */

  1623. #define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */

  1624. #define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/

  1625. #define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */

  1626. 

  1627. /**

  1628.   * @}

  1629.   */

  1630. 

  1631. /**

  1632.   * @}

  1633.   */

  1634. 

  1635. 

  1636. 

  1637. /* Exported macro ------------------------------------------------------------*/

  1638. /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros

  1639.   * @{

  1640.   */

  1641. 

  1642. /** @brief  Macros to enable or disable PLL2.

  1643.   * @note   After enabling PLL2, the application software should wait on

  1644.   *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can

  1645.   *         be used as kernel clock source.

  1646.   * @note   PLL2 is disabled by hardware when entering STOP and STANDBY modes.

  1647.   */

  1648. #define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)

  1649. #define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)

  1650. 

  1651. /**

  1652.   * @brief  Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)

  1653.   * @note   Enabling/disabling  those Clocks can be done only when the PLL2 is disabled,

  1654.   *         This is mainly used to save Power.

  1655.   * @param  __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted

  1656.   *          This parameter can be one of the following values:

  1657.   *            @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

  1658.   *            @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

  1659.   *            @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

  1660.   *

  1661.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  1662.   *

  1663.   * @retval None

  1664.   */

  1665. #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

  1666. 

  1667. #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

  1668. 

  1669. /**

  1670.   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO

  1671.   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL2

  1672.   * @retval None

  1673.   */

  1674. #define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

  1675. 

  1676. #define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

  1677. 

  1678. /**

  1679.   * @brief  Macro to configures the PLL2  multiplication and division factors.

  1680.   * @note   This function must be used only when PLL2 is disabled.

  1681.   *

  1682.   * @param  __PLL2M__ specifies the division factor for PLL2 VCO input clock

  1683.   *          This parameter must be a number between 1 and 63.

  1684.   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input

  1685.   *         frequency ranges from 1 to 16 MHz.

  1686.   *

  1687.   * @param  __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock

  1688.   *          This parameter must be a number between 4 and 512 or between 8 and 420(*).

  1689.   * @note   You have to set the PLL2N parameter correctly to ensure that the VCO

  1690.   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or

  1691.   *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

  1692.   *

  1693.   * @param  __PLL2P__ specifies the division factor for peripheral kernel clocks

  1694.   *          This parameter must be a number between 1 and 128.

  1695.   *

  1696.   * @param  __PLL2Q__ specifies the division factor for peripheral kernel clocks

  1697.   *          This parameter must be a number between 1 and 128.

  1698.   *

  1699.   * @param  __PLL2R__ specifies the division factor for peripheral kernel clocks

  1700.   *          This parameter must be a number between 1 and 128.

  1701.   *

  1702.   * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)

  1703.   *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible

  1704.   *         value to  __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.

  1705.   * @retval None

  1706.   *

  1707.   *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  1708.   */

  1709. 

  1710. #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \

  1711.                   do{ \

  1712.                        MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \

  1713.                        WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \

  1714.                        ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \

  1715.                     } while(0)

  1716. 

  1717. /**

  1718.   * @brief  Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor

  1719.   *

  1720.   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO

  1721.   *

  1722.   * @param  __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO

  1723.   *                           It should be a value between 0 and 8191

  1724.   * @note   Warning: the software has to set correctly these bits to insure that the VCO

  1725.   *                  output frequency is between its valid frequency range, which is:

  1726.   *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0

  1727.   *                  150 to 420 MHz if PLL2VCOSEL = 1.

  1728.   *

  1729.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  1730.   *

  1731.   * @retval None

  1732.   */

  1733. #define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \

  1734.                  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))

  1735. 

  1736. /** @brief  Macro to select  the PLL2  reference frequency range.

  1737.   * @param  __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range

  1738.   *         This parameter can be one of the following values:

  1739.   *            @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz

  1740.   *            @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz

  1741.   *            @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz

  1742.   *            @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz

  1743.   * @retval None

  1744.   */

  1745. #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \

  1746.                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))

  1747. 

  1748. 

  1749. /** @brief  Macro to select  the PLL2  reference frequency range.

  1750.   * @param  __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range

  1751.   *         This parameter can be one of the following values:

  1752.   *            @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)

  1753.   *            @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz

  1754.   *

  1755.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  1756.   *

  1757.   * @retval None

  1758.   */

  1759. #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \

  1760.                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))

  1761. 

  1762. /** @brief  Macros to enable or disable the main PLL3.

  1763.   * @note   After enabling  PLL3, the application software should wait on

  1764.   *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can

  1765.   *         be used as kernel clock source.

  1766.   * @note   PLL3 is disabled by hardware when entering STOP and STANDBY modes.

  1767.   */

  1768. #define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)

  1769. #define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)

  1770. 

  1771. /**

  1772.   * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO

  1773.   * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL3

  1774.   * @retval None

  1775.   */

  1776. #define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

  1777. 

  1778. #define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

  1779. 

  1780. /**

  1781.   * @brief  Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)

  1782.   * @note   Enabling/disabling  those Clocks can be done only when the PLL3 is disabled,

  1783.   *         This is mainly used to save Power.

  1784.   * @param  __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted

  1785.   *          This parameter can be one of the following values:

  1786.   *            @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

  1787.   *            @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock  up to 400MHZ or 280MHZ(*)

  1788.   *            @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

  1789.   *

  1790.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  1791.   *

  1792.   * @retval None

  1793.   */

  1794. #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

  1795. 

  1796. #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

  1797. 

  1798. /**

  1799.   * @brief  Macro to configures the PLL3  multiplication and division factors.

  1800.   * @note   This function must be used only when PLL3 is disabled.

  1801.   *

  1802.   * @param  __PLL3M__ specifies the division factor for PLL3 VCO input clock

  1803.   *          This parameter must be a number between 1 and 63.

  1804.   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input

  1805.   *         frequency ranges from 1 to 16 MHz.

  1806.   *

  1807.   * @param  __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock

  1808.   *          This parameter must be a number between 4 and 512.

  1809.   * @note   You have to set the PLL3N parameter correctly to ensure that the VCO

  1810.   *         output frequency is between 150 and 420 MHz (when in medium VCO range) or

  1811.   *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

  1812.   *

  1813.   * @param  __PLL3P__ specifies the division factor for peripheral kernel clocks

  1814.   *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)

  1815.   *

  1816.   * @param  __PLL3Q__ specifies the division factor for peripheral kernel clocks

  1817.   *          This parameter must be a number between 1 and 128

  1818.   *

  1819.   * @param  __PLL3R__ specifies the division factor for peripheral kernel clocks

  1820.   *          This parameter must be a number between 1 and 128

  1821.   *

  1822.   * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)

  1823.   *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible

  1824.   *         value to  __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.

  1825.   * @retval None

  1826.   *

  1827.   *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  1828.   */

  1829. 

  1830. #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \

  1831.                   do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \

  1832.                          WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \

  1833.                                    ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \

  1834.                        } while(0)

  1835. 

  1836. 

  1837. 

  1838. /**

  1839.   * @brief  Macro to configures  PLL3 clock Fractional Part of The Multiplication Factor

  1840.   *

  1841.   * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO

  1842.   *

  1843.   * @param  __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO

  1844.   *                            It should be a value between 0 and 8191

  1845.   * @note   Warning: the software has to set correctly these bits to insure that the VCO

  1846.   *                  output frequency is between its valid frequency range, which is:

  1847.   *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0

  1848.   *                  150 to 420 MHz if PLL3VCOSEL = 1.

  1849.   *

  1850.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  1851.   *

  1852.   * @retval None

  1853.   */

  1854.  #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)

  1855. 

  1856. /** @brief  Macro to select  the PLL3  reference frequency range.

  1857.   * @param  __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range

  1858.   *         This parameter can be one of the following values:

  1859.   *            @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz

  1860.   *            @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz

  1861.   *            @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz

  1862.   *            @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz

  1863.   * @retval None

  1864.   */

  1865. #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \

  1866.                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))

  1867. 

  1868. 

  1869. /** @brief  Macro to select  the PLL3  reference frequency range.

  1870.   * @param  __RCC_PLL3VCORange__ specifies the PLL1 input frequency range

  1871.   *         This parameter can be one of the following values:

  1872.   *            @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz  or between 128 to 560 MHz(*)

  1873.   *            @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz

  1874.   *

  1875.   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

  1876.   *

  1877.   * @retval None

  1878.   */

  1879. #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \

  1880.                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))

  1881. /**

  1882.   * @brief  Macro to Configure the SAI1 clock source.

  1883.   * @param  __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived

  1884.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  1885.   *          This parameter can be one of the following values:

  1886.   *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL

  1887.   *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2

  1888.   *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3

  1889.   *             @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock  = OSC

  1890.   *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock

  1891.   * @retval None

  1892.   */

  1893. #if defined(RCC_D2CCIP1R_SAI1SEL)

  1894. #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\

  1895.                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

  1896. #else

  1897. #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\

  1898.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

  1899. #endif /* RCC_D2CCIP1R_SAI1SEL */

  1900. 

  1901. /** @brief  Macro to get the SAI1 clock source.

  1902.   * @retval The clock source can be one of the following values:

  1903.   *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL

  1904.   *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2

  1905.   *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3

  1906.   *             @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock  = CLKP

  1907.   *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock

  1908.   */

  1909. #if defined(RCC_D2CCIP1R_SAI1SEL)

  1910. #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))

  1911. #else

  1912. #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))

  1913. #endif /* RCC_D2CCIP1R_SAI1SEL */

  1914. 

  1915. /**

  1916.   * @brief  Macro to Configure the SPDIFRX clock source.

  1917.   * @param  __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived

  1918.   *         from system PLL, PLL2, PLL3,  or internal OSC clock

  1919.   *          This parameter can be one of the following values:

  1920.   *             @arg RCC_SPDIFRXCLKSOURCE_PLL:  SPDIFRX clock = PLL

  1921.   *             @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2

  1922.   *             @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3

  1923.   *             @arg RCC_SPDIFRXCLKSOURCE_HSI:  SPDIFRX clock  = HSI

  1924.   * @retval None

  1925.   */

  1926. #if defined(RCC_D2CCIP1R_SPDIFSEL)

  1927. #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\

  1928.                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

  1929. #else

  1930. #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\

  1931.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

  1932. #endif /* RCC_D2CCIP1R_SPDIFSEL */

  1933. 

  1934. /**

  1935.   * @brief  Macro to get the SPDIFRX clock source.

  1936.   * @retval None

  1937.   */

  1938. #if defined(RCC_D2CCIP1R_SPDIFSEL)

  1939. #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))

  1940. #else

  1941. #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))

  1942. #endif /* RCC_D2CCIP1R_SPDIFSEL */

  1943. 

  1944. #if defined(SAI3)

  1945. /**

  1946.   * @brief  Macro to Configure the SAI2/3 clock source.

  1947.   * @param  __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived

  1948.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  1949.   *          This parameter can be one of the following values:

  1950.   *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL

  1951.   *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2

  1952.   *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3

  1953.   *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP

  1954.   *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock

  1955.   * @retval None

  1956.   */

  1957. #define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\

  1958.                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))

  1959. 

  1960. /** @brief  Macro to get the SAI2/3 clock source.

  1961.   * @retval The clock source can be one of the following values:

  1962.   *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL

  1963.   *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2

  1964.   *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3

  1965.   *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP

  1966.   *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock

  1967.   */

  1968. #define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))

  1969. 

  1970. /**

  1971.   * @brief  Macro to Configure the SAI2 clock source.

  1972.   * @param  __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived

  1973.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  1974.   *          This parameter can be one of the following values:

  1975.   *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL

  1976.   *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2

  1977.   *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3

  1978.   *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP

  1979.   *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock

  1980.   * @retval None

  1981.   */

  1982. #define __HAL_RCC_SAI2_CONFIG  __HAL_RCC_SAI23_CONFIG

  1983. 

  1984. /** @brief  Macro to get the SAI2 clock source.

  1985.   * @retval The clock source can be one of the following values:

  1986.   *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL

  1987.   *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2

  1988.   *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3

  1989.   *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP

  1990.   *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock

  1991.   */

  1992. #define __HAL_RCC_GET_SAI2_SOURCE  __HAL_RCC_GET_SAI23_SOURCE

  1993. 

  1994. /**

  1995.   * @brief  Macro to Configure the SAI3 clock source.

  1996.   * @param  __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived

  1997.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  1998.   *          This parameter can be one of the following values:

  1999.   *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL

  2000.   *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2

  2001.   *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3

  2002.   *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP

  2003.   *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock

  2004.   * @retval None

  2005.   */

  2006. #define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG

  2007. 

  2008. /** @brief  Macro to get the SAI3 clock source.

  2009.   * @retval The clock source can be one of the following values:

  2010.   *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL

  2011.   *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2

  2012.   *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3

  2013.   *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP

  2014.   *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock

  2015.   */

  2016. #define __HAL_RCC_GET_SAI3_SOURCE  __HAL_RCC_GET_SAI23_SOURCE

  2017. #endif /* SAI3 */

  2018. 

  2019. #if defined(RCC_CDCCIP1R_SAI2ASEL)

  2020. /**

  2021.   * @brief  Macro to Configure the SAI2A clock source.

  2022.   * @param  __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived

  2023.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  2024.   *          This parameter can be one of the following values:

  2025.   *             @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL

  2026.   *             @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2

  2027.   *             @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3

  2028.   *             @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock  = CLKP

  2029.   *             @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock

  2030.   *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock

  2031.   * @retval None

  2032.   */

  2033. #define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\

  2034.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))

  2035. 

  2036. /** @brief  Macro to get the SAI2A clock source.

  2037.   * @retval The clock source can be one of the following values:

  2038.   *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL

  2039.   *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2

  2040.   *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3

  2041.   *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock  = CLKP

  2042.   *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock

  2043.   *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock

  2044.   */

  2045. #define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))

  2046. #endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */

  2047. 

  2048. #if defined(RCC_CDCCIP1R_SAI2BSEL)

  2049. /**

  2050.   * @brief  Macro to Configure the SAI2B clock source.

  2051.   * @param  __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived

  2052.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  2053.   *          This parameter can be one of the following values:

  2054.   *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL

  2055.   *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2

  2056.   *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3

  2057.   *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP

  2058.   *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock

  2059.   *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock

  2060.   * @retval None

  2061.   */

  2062. #define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\

  2063.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))

  2064. 

  2065. /** @brief  Macro to get the SAI2B clock source.

  2066.   * @retval The clock source can be one of the following values:

  2067.   *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL

  2068.   *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2

  2069.   *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3

  2070.   *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP

  2071.   *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock

  2072.   *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock

  2073.   */

  2074. #define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))

  2075. #endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */

  2076. 

  2077. 

  2078. #if defined(SAI4_Block_A)

  2079. /**

  2080.   * @brief  Macro to Configure the SAI4A clock source.

  2081.   * @param  __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived

  2082.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  2083.   *          This parameter can be one of the following values:

  2084.   *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL

  2085.   *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2

  2086.   *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3

  2087.   *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock  = CLKP

  2088.   *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock

  2089.   * @retval None

  2090.   */

  2091. #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\

  2092.                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))

  2093. 

  2094. /** @brief  Macro to get the SAI4A clock source.

  2095.   * @retval The clock source can be one of the following values:

  2096.   *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL

  2097.   *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2

  2098.   *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3

  2099.   *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock  = CLKP

  2100.   *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock

  2101.   */

  2102. #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))

  2103. #endif /* SAI4_Block_A */

  2104. 

  2105. #if defined(SAI4_Block_B)

  2106. /**

  2107.   * @brief  Macro to Configure the SAI4B clock source.

  2108.   * @param  __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived

  2109.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  2110.   *          This parameter can be one of the following values:

  2111.   *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL

  2112.   *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2

  2113.   *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3

  2114.   *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP

  2115.   *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock

  2116.   * @retval None

  2117.   */

  2118. #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\

  2119.                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))

  2120. 

  2121. /** @brief  Macro to get the SAI4B clock source.

  2122.   * @retval The clock source can be one of the following values:

  2123.   *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL

  2124.   *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2

  2125.   *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3

  2126.   *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP

  2127.   *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock

  2128.   */

  2129. #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))

  2130. #endif /* SAI4_Block_B */

  2131. 

  2132. /** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).

  2133.   *

  2134.   * @param  __I2C123CLKSource__ specifies the I2C1/2/3 clock source.

  2135.   *          This parameter can be one of the following values:

  2136.   *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock

  2137.   *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock

  2138.   *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock

  2139.   *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock

  2140.   */

  2141. #if defined(RCC_D2CCIP2R_I2C123SEL)

  2142. #define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \

  2143.                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))

  2144. #else

  2145. #define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \

  2146.                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))

  2147. #endif /* RCC_D2CCIP2R_I2C123SEL */

  2148. 

  2149. /** @brief  macro to get the I2C1/2/3 clock source.

  2150.   * @retval The clock source can be one of the following values:

  2151.   *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock

  2152.   *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock

  2153.   *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock

  2154.   *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock

  2155.   */

  2156. #if defined(RCC_D2CCIP2R_I2C123SEL)

  2157. #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))

  2158. #else

  2159. #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))

  2160. #endif /* RCC_D2CCIP2R_I2C123SEL */

  2161. 

  2162. /** @brief macro to configure the I2C1 clock (I2C1CLK).

  2163.   *

  2164.   * @param  __I2C1CLKSource__ specifies the I2C1 clock source.

  2165.   *          This parameter can be one of the following values:

  2166.   *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock

  2167.   *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock

  2168.   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock

  2169.   *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

  2170.   */

  2171. #define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C123_CONFIG

  2172. 

  2173. /** @brief  macro to get the I2C1 clock source.

  2174.   * @retval The clock source can be one of the following values:

  2175.   *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock

  2176.   *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock

  2177.   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock

  2178.   *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

  2179.   */

  2180. #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE

  2181. 

  2182. /** @brief macro to configure the I2C2 clock (I2C2CLK).

  2183.   *

  2184.   * @param  __I2C2CLKSource__ specifies the I2C2 clock source.

  2185.   *          This parameter can be one of the following values:

  2186.   *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock

  2187.   *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock

  2188.   *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock

  2189.   *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

  2190.   */

  2191. #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG

  2192. 

  2193. /** @brief  macro to get the I2C2 clock source.

  2194.   * @retval The clock source can be one of the following values:

  2195.   *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock

  2196.   *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock

  2197.   *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock

  2198.   *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

  2199.   */

  2200. #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE

  2201. 

  2202. /** @brief macro to configure the I2C3 clock (I2C3CLK).

  2203.   *

  2204.   * @param  __I2C3CLKSource__ specifies the I2C3 clock source.

  2205.   *          This parameter can be one of the following values:

  2206.   *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock

  2207.   *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock

  2208.   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock

  2209.   *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

  2210.   */

  2211. #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG

  2212. 

  2213. /** @brief  macro to get the I2C3 clock source.

  2214.   * @retval The clock source can be one of the following values:

  2215.   *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock

  2216.   *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock

  2217.   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock

  2218.   *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

  2219.   */

  2220. #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE

  2221. 

  2222. /** @brief macro to configure the I2C4 clock (I2C4CLK).

  2223.   *

  2224.   * @param  __I2C4CLKSource__ specifies the I2C4 clock source.

  2225.   *          This parameter can be one of the following values:

  2226.   *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock

  2227.   *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock

  2228.   *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock

  2229.   *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

  2230.   */

  2231. #if defined(RCC_D3CCIPR_I2C4SEL)

  2232. #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \

  2233.                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

  2234. #else

  2235. #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \

  2236.                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

  2237. #endif /* RCC_D3CCIPR_I2C4SEL */

  2238. 

  2239. /** @brief  macro to get the I2C4 clock source.

  2240.   * @retval The clock source can be one of the following values:

  2241.   *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock

  2242.   *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock

  2243.   *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock

  2244.   *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

  2245.   */

  2246. #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))

  2247. 

  2248. /** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK).

  2249.   *

  2250.   * @param  __USART16CLKSource__ specifies the USART1/6/9* /10* clock source.

  2251.   *          This parameter can be one of the following values:

  2252.   *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock

  2253.   *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock

  2254.   *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock

  2255.   *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock

  2256.   *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock

  2257.   *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock

  2258.   *

  2259.   * (*) : Available on some STM32H7 lines only.

  2260.   */

  2261. #if defined(RCC_D2CCIP2R_USART16SEL)

  2262. #define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \

  2263.                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))

  2264. #else

  2265. #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \

  2266.                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))

  2267. /* alias */

  2268. #define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG

  2269. #endif /* RCC_D2CCIP2R_USART16SEL */

  2270. 

  2271. /** @brief  macro to get the USART1/6/9* /10* clock source.

  2272.   * @retval The clock source can be one of the following values:

  2273.   *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock

  2274.   *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock

  2275.   *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock

  2276.   *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock

  2277.   *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock

  2278.   *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock

  2279.   *

  2280.   * (*) : Available on some STM32H7 lines only.

  2281.   */

  2282. #if defined(RCC_D2CCIP2R_USART16SEL)

  2283. #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))

  2284. #else

  2285. #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))

  2286. /* alias*/

  2287. #define  __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE

  2288. #endif /* RCC_D2CCIP2R_USART16SEL */

  2289. 

  2290. /** @brief macro to configure the USART234578 clock (USART234578CLK).

  2291.   *

  2292.   * @param  __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.

  2293.   *          This parameter can be one of the following values:

  2294.   *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock

  2295.   *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock

  2296.   *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock

  2297.   *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock

  2298.   *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock

  2299.   *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

  2300.   */

  2301. #if defined(RCC_D2CCIP2R_USART28SEL)

  2302. #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \

  2303.                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))

  2304. #else

  2305. #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \

  2306.                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))

  2307. #endif /* RCC_D2CCIP2R_USART28SEL */

  2308. 

  2309. /** @brief  macro to get the USART2/3/4/5/7/8 clock source.

  2310.   * @retval The clock source can be one of the following values:

  2311.   *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock

  2312.   *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock

  2313.   *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock

  2314.   *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock

  2315.   *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock

  2316.   *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

  2317.   */

  2318. #if defined(RCC_D2CCIP2R_USART28SEL)

  2319. #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

  2320. #else

  2321. #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))

  2322. #endif /* RCC_D2CCIP2R_USART28SEL */

  2323. 

  2324. /** @brief macro to configure the USART1 clock (USART1CLK).

  2325.   *

  2326.   * @param  __USART1CLKSource__ specifies the USART1 clock source.

  2327.   *          This parameter can be one of the following values:

  2328.   *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock

  2329.   *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock

  2330.   *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock

  2331.   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock

  2332.   *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock

  2333.   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

  2334.   */

  2335. #define __HAL_RCC_USART1_CONFIG  __HAL_RCC_USART16_CONFIG

  2336. 

  2337. /** @brief  macro to get the USART1 clock source.

  2338.   * @retval The clock source can be one of the following values:

  2339.   *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock

  2340.   *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock

  2341.   *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock

  2342.   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock

  2343.   *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock

  2344.   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

  2345.   */

  2346. #define __HAL_RCC_GET_USART1_SOURCE  __HAL_RCC_GET_USART16_SOURCE

  2347. 

  2348. /** @brief macro to configure the USART2 clock (USART2CLK).

  2349.   *

  2350.   * @param  __USART2CLKSource__ specifies the USART2 clock source.

  2351.   *          This parameter can be one of the following values:

  2352.   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock

  2353.   *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock

  2354.   *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock

  2355.   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock

  2356.   *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock

  2357.   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

  2358.   */

  2359. #define __HAL_RCC_USART2_CONFIG  __HAL_RCC_USART234578_CONFIG

  2360. 

  2361. /** @brief  macro to get the USART2 clock source.

  2362.   * @retval The clock source can be one of the following values:

  2363.   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock

  2364.   *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock

  2365.   *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock

  2366.   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock

  2367.   *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock

  2368.   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

  2369.   */

  2370. #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE

  2371. 

  2372. /** @brief macro to configure the USART3 clock (USART3CLK).

  2373.   *

  2374.   * @param  __USART3CLKSource__ specifies the USART3 clock source.

  2375.   *          This parameter can be one of the following values:

  2376.   *            @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock

  2377.   *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock

  2378.   *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock

  2379.   *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock

  2380.   *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock

  2381.   *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

  2382.   */

  2383. #define __HAL_RCC_USART3_CONFIG  __HAL_RCC_USART234578_CONFIG

  2384. 

  2385. /** @brief  macro to get the USART3 clock source.

  2386.   * @retval The clock source can be one of the following values:

  2387.   *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock

  2388.   *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock

  2389.   *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock

  2390.   *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock

  2391.   *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock

  2392.   *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

  2393.   */

  2394. #define __HAL_RCC_GET_USART3_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

  2395. 

  2396. /** @brief macro to configure the UART4 clock (UART4CLK).

  2397.   *

  2398.   * @param  __UART4CLKSource__ specifies the UART4 clock source.

  2399.   *          This parameter can be one of the following values:

  2400.   *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock

  2401.   *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock

  2402.   *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock

  2403.   *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock

  2404.   *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock

  2405.   *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

  2406.   */

  2407. #define __HAL_RCC_UART4_CONFIG  __HAL_RCC_USART234578_CONFIG

  2408. 

  2409. /** @brief  macro to get the UART4 clock source.

  2410.   * @retval The clock source can be one of the following values:

  2411.   *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock

  2412.   *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock

  2413.   *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock

  2414.   *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock

  2415.   *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock

  2416.   *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

  2417.   */

  2418. #define __HAL_RCC_GET_UART4_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

  2419. 

  2420. /** @brief macro to configure the UART5 clock (UART5CLK).

  2421.   *

  2422.   * @param  __UART5CLKSource__ specifies the UART5 clock source.

  2423.   *          This parameter can be one of the following values:

  2424.   *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock

  2425.   *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock

  2426.   *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock

  2427.   *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock

  2428.   *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock

  2429.   *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

  2430.   */

  2431. #define __HAL_RCC_UART5_CONFIG  __HAL_RCC_USART234578_CONFIG

  2432. 

  2433. /** @brief  macro to get the UART5 clock source.

  2434.   * @retval The clock source can be one of the following values:

  2435.   *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock

  2436.   *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock

  2437.   *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock

  2438.   *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock

  2439.   *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock

  2440.   *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

  2441.   */

  2442. #define __HAL_RCC_GET_UART5_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

  2443. 

  2444. /** @brief macro to configure the USART6 clock (USART6CLK).

  2445.   *

  2446.   * @param  __USART6CLKSource__ specifies the USART6 clock source.

  2447.   *          This parameter can be one of the following values:

  2448.   *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock

  2449.   *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock

  2450.   *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock

  2451.   *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock

  2452.   *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock

  2453.   *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

  2454.   */

  2455. #define __HAL_RCC_USART6_CONFIG  __HAL_RCC_USART16_CONFIG

  2456. 

  2457. /** @brief  macro to get the USART6 clock source.

  2458.   * @retval The clock source can be one of the following values:

  2459.   *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock

  2460.   *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock

  2461.   *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock

  2462.   *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock

  2463.   *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock

  2464.   *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

  2465.   */

  2466. #define __HAL_RCC_GET_USART6_SOURCE  __HAL_RCC_GET_USART16_SOURCE

  2467. 

  2468. /** @brief macro to configure the UART5 clock (UART7CLK).

  2469.   *

  2470.   * @param  __UART7CLKSource__ specifies the UART7 clock source.

  2471.   *          This parameter can be one of the following values:

  2472.   *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock

  2473.   *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock

  2474.   *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock

  2475.   *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock

  2476.   *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock

  2477.   *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

  2478.   */

  2479. #define __HAL_RCC_UART7_CONFIG  __HAL_RCC_USART234578_CONFIG

  2480. 

  2481. /** @brief  macro to get the UART7 clock source.

  2482.   * @retval The clock source can be one of the following values:

  2483.   *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock

  2484.   *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock

  2485.   *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock

  2486.   *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock

  2487.   *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock

  2488.   *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

  2489.   */

  2490. #define __HAL_RCC_GET_UART7_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

  2491. 

  2492. /** @brief macro to configure the UART8 clock (UART8CLK).

  2493.   *

  2494.   * @param  __UART8CLKSource__ specifies the UART8 clock source.

  2495.   *          This parameter can be one of the following values:

  2496.   *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock

  2497.   *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock

  2498.   *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock

  2499.   *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock

  2500.   *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock

  2501.   *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

  2502.   */

  2503. #define __HAL_RCC_UART8_CONFIG  __HAL_RCC_USART234578_CONFIG

  2504. 

  2505. /** @brief  macro to get the UART8 clock source.

  2506.   * @retval The clock source can be one of the following values:

  2507.   *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock

  2508.   *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock

  2509.   *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock

  2510.   *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock

  2511.   *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock

  2512.   *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

  2513.   */

  2514. #define __HAL_RCC_GET_UART8_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

  2515. 

  2516. #if defined(UART9)

  2517. /** @brief macro to configure the UART9 clock (UART9CLK).

  2518.   *

  2519.   * @param  __UART8CLKSource__ specifies the UART8 clock source.

  2520.   *          This parameter can be one of the following values:

  2521.   *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock

  2522.   *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock

  2523.   *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock

  2524.   *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock

  2525.   *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock

  2526.   *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock

  2527.   */

  2528. #define __HAL_RCC_UART9_CONFIG  __HAL_RCC_USART16_CONFIG

  2529. 

  2530. /** @brief  macro to get the UART9 clock source.

  2531.   * @retval The clock source can be one of the following values:

  2532.   *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock

  2533.   *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock

  2534.   *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock

  2535.   *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock

  2536.   *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock

  2537.   *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock

  2538.   */

  2539. #define __HAL_RCC_GET_UART9_SOURCE  __HAL_RCC_GET_USART16_SOURCE

  2540. #endif /* UART9 */

  2541. 

  2542. #if defined(USART10)

  2543. /** @brief macro to configure the USART10 clock (USART10CLK).

  2544.   *

  2545.   * @param  __UART8CLKSource__ specifies the UART8 clock source.

  2546.   *          This parameter can be one of the following values:

  2547.   *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock

  2548.   *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock

  2549.   *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock

  2550.   *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock

  2551.   *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock

  2552.   *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock

  2553.   */

  2554. #define __HAL_RCC_USART10_CONFIG  __HAL_RCC_USART16_CONFIG

  2555. 

  2556. /** @brief  macro to get the USART10 clock source.

  2557.   * @retval The clock source can be one of the following values:

  2558.   *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock

  2559.   *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock

  2560.   *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock

  2561.   *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock

  2562.   *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock

  2563.   *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock

  2564.   */

  2565. #define __HAL_RCC_GET_USART10_SOURCE  __HAL_RCC_GET_USART16_SOURCE

  2566. #endif /* USART10 */

  2567. 

  2568. /** @brief macro to configure the LPUART1 clock (LPUART1CLK).

  2569.   *

  2570.   * @param  __LPUART1CLKSource__ specifies the LPUART1 clock source.

  2571.   *          This parameter can be one of the following values:

  2572.   *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock

  2573.   *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock

  2574.   *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock

  2575.   *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock

  2576.   *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock

  2577.   *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

  2578.   */

  2579. #if defined (RCC_D3CCIPR_LPUART1SEL)

  2580. #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \

  2581.                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

  2582. #else

  2583. #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \

  2584.                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

  2585. #endif /* RCC_D3CCIPR_LPUART1SEL */

  2586. 

  2587. /** @brief  macro to get the LPUART1 clock source.

  2588.   * @retval The clock source can be one of the following values:

  2589.   *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock

  2590.   *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock

  2591.   *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock

  2592.   *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock

  2593.   *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock

  2594.   *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

  2595.   */

  2596. #if defined (RCC_D3CCIPR_LPUART1SEL)

  2597. #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))

  2598. #else

  2599. #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))

  2600. #endif /* RCC_D3CCIPR_LPUART1SEL */

  2601. 

  2602. /** @brief  macro to configure the LPTIM1 clock source.

  2603.   *

  2604.   * @param  __LPTIM1CLKSource__ specifies the LPTIM1 clock source.

  2605.   *          This parameter can be one of the following values:

  2606.   *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock

  2607.   *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock

  2608.   *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock

  2609.   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

  2610.   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock

  2611.   *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

  2612.   */

  2613. #if defined(RCC_D2CCIP2R_LPTIM1SEL)

  2614. #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \

  2615.                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

  2616. #else

  2617. #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \

  2618.                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

  2619. #endif /* RCC_D2CCIP2R_LPTIM1SEL */

  2620. 

  2621. /** @brief  macro to get the LPTIM1 clock source.

  2622.   * @retval The clock source can be one of the following values:

  2623.   *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock

  2624.   *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock

  2625.   *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock

  2626.   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

  2627.   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock

  2628.   *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

  2629.   */

  2630. #if defined(RCC_D2CCIP2R_LPTIM1SEL)

  2631. #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))

  2632. #else

  2633. #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))

  2634. #endif /* RCC_D2CCIP2R_LPTIM1SEL */

  2635. 

  2636. /** @brief  macro to configure the LPTIM2 clock source.

  2637.   *

  2638.   * @param  __LPTIM2CLKSource__ specifies the LPTIM2 clock source.

  2639.   *          This parameter can be one of the following values:

  2640.   *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock

  2641.   *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock

  2642.   *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock

  2643.   *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock

  2644.   *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock

  2645.   *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

  2646.   */

  2647. #if defined(RCC_D3CCIPR_LPTIM2SEL)

  2648. #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \

  2649.                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

  2650. #else

  2651. #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \

  2652.                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

  2653. #endif /* RCC_D3CCIPR_LPTIM2SEL */

  2654. 

  2655. /** @brief  macro to get the LPTIM2 clock source.

  2656.   * @retval The clock source can be one of the following values:

  2657.   *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock

  2658.   *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock

  2659.   *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock

  2660.   *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock

  2661.   *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock

  2662.   *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

  2663.   */

  2664. #if defined(RCC_D3CCIPR_LPTIM2SEL)

  2665. #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))

  2666. #else

  2667. #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))

  2668. #endif /* RCC_D3CCIPR_LPTIM2SEL */

  2669. 

  2670. /** @brief  macro to configure the LPTIM3/4/5 clock source.

  2671.   *

  2672.   * @param  __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.

  2673.   *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock

  2674.   *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock

  2675.   *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock

  2676.   *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock

  2677.   *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock

  2678.   *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

  2679.   */

  2680. #if defined(RCC_D3CCIPR_LPTIM345SEL)

  2681. #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \

  2682.                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))

  2683. #else

  2684. #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) \

  2685.                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))

  2686. #endif /* RCC_D3CCIPR_LPTIM345SEL */

  2687. 

  2688. /** @brief  macro to get the LPTIM3/4/5 clock source.

  2689.   * @retval The clock source can be one of the following values:

  2690.   *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock

  2691.   *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock

  2692.   *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock

  2693.   *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock

  2694.   *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock

  2695.   *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

  2696.   */

  2697. #if defined(RCC_D3CCIPR_LPTIM345SEL)

  2698. #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))

  2699. #else

  2700. #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))

  2701. #endif /* RCC_D3CCIPR_LPTIM345SEL */

  2702. 

  2703. /** @brief  macro to configure the LPTIM3 clock source.

  2704.   *

  2705.   * @param  __LPTIM3CLKSource__ specifies the LPTIM3 clock source.

  2706.   *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock

  2707.   *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock

  2708.   *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock

  2709.   *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock

  2710.   *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock

  2711.   *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

  2712.   */

  2713. #define __HAL_RCC_LPTIM3_CONFIG  __HAL_RCC_LPTIM345_CONFIG

  2714. 

  2715. /** @brief  macro to get the LPTIM3 clock source.

  2716.   * @retval The clock source can be one of the following values:

  2717.   *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock

  2718.   *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock

  2719.   *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock

  2720.   *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock

  2721.   *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock

  2722.   *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

  2723.   */

  2724. #define __HAL_RCC_GET_LPTIM3_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE

  2725. 

  2726. #if defined(LPTIM4)

  2727. /** @brief  macro to configure the LPTIM4 clock source.

  2728.   *

  2729.   * @param  __LPTIM4CLKSource__ specifies the LPTIM4 clock source.

  2730.   *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock

  2731.   *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock

  2732.   *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock

  2733.   *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock

  2734.   *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock

  2735.   *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock

  2736.   */

  2737. #define __HAL_RCC_LPTIM4_CONFIG  __HAL_RCC_LPTIM345_CONFIG

  2738. 

  2739. 

  2740. /** @brief  macro to get the LPTIM4 clock source.

  2741.   * @retval The clock source can be one of the following values:

  2742.   *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock

  2743.   *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock

  2744.   *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock

  2745.   *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock

  2746.   *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock

  2747.   *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock

  2748.   */

  2749. #define __HAL_RCC_GET_LPTIM4_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE

  2750. #endif /* LPTIM4 */

  2751. 

  2752. #if defined(LPTIM5)

  2753. /** @brief  macro to configure the LPTIM5 clock source.

  2754.   *

  2755.   * @param  __LPTIM5CLKSource__ specifies the LPTIM5 clock source.

  2756.   *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock

  2757.   *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock

  2758.   *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock

  2759.   *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock

  2760.   *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock

  2761.   *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock

  2762.   */

  2763. #define __HAL_RCC_LPTIM5_CONFIG  __HAL_RCC_LPTIM345_CONFIG

  2764. 

  2765. 

  2766. /** @brief  macro to get the LPTIM5 clock source.

  2767.   * @retval The clock source can be one of the following values:

  2768.   *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock

  2769.   *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock

  2770.   *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock

  2771.   *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock

  2772.   *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock

  2773.   *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock

  2774.   */

  2775. #define __HAL_RCC_GET_LPTIM5_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE

  2776. #endif /* LPTIM5 */

  2777. 

  2778. #if defined(QUADSPI)

  2779. /** @brief  macro to configure the QSPI clock source.

  2780.   *

  2781.   * @param  __QSPICLKSource__ specifies the QSPI clock source.

  2782.   *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock

  2783.   *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock

  2784.   *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock

  2785.   *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock

  2786.   */

  2787. #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \

  2788.                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))

  2789. 

  2790. 

  2791. /** @brief  macro to get the QSPI clock source.

  2792.   * @retval The clock source can be one of the following values:

  2793.   *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock

  2794.   *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock

  2795.   *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock

  2796.   *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock

  2797.   */

  2798. #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))

  2799. #endif /* QUADSPI */

  2800. 

  2801. #if defined(OCTOSPI1) || defined(OCTOSPI2)

  2802. /** @brief  macro to configure the OSPI clock source.

  2803.   *

  2804.   * @param  __OSPICLKSource__ specifies the OSPI clock source.

  2805.   *            @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock

  2806.   *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock

  2807.   *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock

  2808.   *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock

  2809.   */

  2810. #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \

  2811.                   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))

  2812. 

  2813. 

  2814. /** @brief  macro to get the OSPI clock source.

  2815.   * @retval The clock source can be one of the following values:

  2816.   *            @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock

  2817.   *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock

  2818.   *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock

  2819.   *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock

  2820.   */

  2821. #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))

  2822. #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

  2823. 

  2824. 

  2825. #if defined(DSI)

  2826. /** @brief  macro to configure the DSI clock source.

  2827.   *

  2828.   * @param  __DSICLKSource__ specifies the DSI clock source.

  2829.   *            @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock

  2830.   *            @arg RCC_RCC_DSICLKSOURCE_PLL2   : PLL2_Q Clock clock is selected as DSI byte lane clock

  2831.   */

  2832. #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \

  2833.                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))

  2834. 

  2835. 

  2836. /** @brief  macro to get the DSI clock source.

  2837.   * @retval The clock source can be one of the following values:

  2838.   *            @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock

  2839.   *            @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock

  2840.   */

  2841. #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))

  2842. #endif /*DSI*/

  2843. 

  2844. /** @brief  macro to configure the FMC clock source.

  2845.   *

  2846.   * @param  __FMCCLKSource__ specifies the FMC clock source.

  2847.   *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock

  2848.   *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock

  2849.   *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock

  2850.   *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock

  2851.   */

  2852. #if defined(RCC_D1CCIPR_FMCSEL)

  2853. #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \

  2854.                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

  2855. #else

  2856. #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \

  2857.                   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

  2858. #endif /* RCC_D1CCIPR_FMCSEL */

  2859. 

  2860. /** @brief  macro to get the FMC clock source.

  2861.   * @retval The clock source can be one of the following values:

  2862.   *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock

  2863.   *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock

  2864.   *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock

  2865.   *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock

  2866.   */

  2867. #if defined(RCC_D1CCIPR_FMCSEL)

  2868. #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))

  2869. #else

  2870. #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))

  2871. #endif /* RCC_D1CCIPR_FMCSEL */

  2872. 

  2873. /** @brief  Macro to configure the USB clock (USBCLK).

  2874.   * @param  __USBCLKSource__ specifies the USB clock source.

  2875.   *         This parameter can be one of the following values:

  2876.   *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock

  2877.   *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock

  2878.   *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

  2879.   */

  2880. #if defined(RCC_D2CCIP2R_USBSEL)

  2881. #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \

  2882.                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))

  2883. #else

  2884. #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \

  2885.                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))

  2886. #endif /* RCC_D2CCIP2R_USBSEL */

  2887. 

  2888. /** @brief  Macro to get the USB clock source.

  2889.   * @retval The clock source can be one of the following values:

  2890.   *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock

  2891.   *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock

  2892.   *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

  2893.   */

  2894. #if defined(RCC_D2CCIP2R_USBSEL)

  2895. #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))

  2896. #else

  2897. #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))

  2898. #endif /* RCC_D2CCIP2R_USBSEL */

  2899. 

  2900. /** @brief  Macro to configure the ADC clock

  2901.   * @param  __ADCCLKSource__ specifies the ADC digital interface clock source.

  2902.   *         This parameter can be one of the following values:

  2903.   *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock

  2904.   *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock

  2905.   *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

  2906.   */

  2907. #if defined(RCC_D3CCIPR_ADCSEL)

  2908. #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \

  2909.                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

  2910. #else

  2911. #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \

  2912.                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

  2913. #endif /* RCC_D3CCIPR_ADCSEL */

  2914. 

  2915. /** @brief  Macro to get the ADC clock source.

  2916.   * @retval The clock source can be one of the following values:

  2917.   *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock

  2918.   *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock

  2919.   *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

  2920.   */

  2921. #if defined(RCC_D3CCIPR_ADCSEL)

  2922. #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))

  2923. #else

  2924. #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))

  2925. #endif /* RCC_D3CCIPR_ADCSEL */

  2926. 

  2927.  /** @brief  Macro to configure the SWPMI1 clock

  2928.   * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.

  2929.   *         This parameter can be one of the following values:

  2930.   *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock

  2931.   *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

  2932.   */

  2933. #if defined(RCC_D2CCIP1R_SWPSEL)

  2934. #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \

  2935.                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

  2936. #else

  2937. #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \

  2938.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

  2939. #endif /* RCC_D2CCIP1R_SWPSEL */

  2940. 

  2941. /** @brief  Macro to get the SWPMI1 clock source.

  2942.   * @retval The clock source can be one of the following values:

  2943.   *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock

  2944.   *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

  2945.   */

  2946. #if defined(RCC_D2CCIP1R_SWPSEL)

  2947. #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))

  2948. #else

  2949. #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))

  2950. #endif /* RCC_D2CCIP1R_SWPSEL */

  2951. 

  2952.  /** @brief  Macro to configure the DFSDM1 clock

  2953.   * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.

  2954.   *         This parameter can be one of the following values:

  2955.   *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock

  2956.   *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock

  2957.   */

  2958. #if defined(RCC_D2CCIP1R_DFSDM1SEL)

  2959. #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \

  2960.                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

  2961. #else

  2962. #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \

  2963.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

  2964. #endif /* RCC_D2CCIP1R_DFSDM1SEL */

  2965. 

  2966. /** @brief  Macro to get the DFSDM1 clock source.

  2967.   * @retval The clock source can be one of the following values:

  2968.   *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock

  2969.   *            @arg RCC_DFSDM1CLKSOURCE_SYS:   System Clock selected as DFSDM1 clock

  2970.   */

  2971. #if defined (RCC_D2CCIP1R_DFSDM1SEL)

  2972. #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))

  2973. #else

  2974. #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))

  2975. #endif /* RCC_D2CCIP1R_DFSDM1SEL */

  2976. 

  2977. #if defined(DFSDM2_BASE)

  2978.  /** @brief  Macro to configure the DFSDM2 clock

  2979.   * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.

  2980.   *         This parameter can be one of the following values:

  2981.   *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock

  2982.   *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock

  2983.   */

  2984. #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \

  2985.                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))

  2986. 

  2987. /** @brief  Macro to get the DFSDM2 clock source.

  2988.   * @retval The clock source can be one of the following values:

  2989.   *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) Clock selected as DFSDM2 clock

  2990.   *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock

  2991.   */

  2992. #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))

  2993. #endif /* DFSDM2 */

  2994. 

  2995. /** @brief macro to configure the CEC clock (CECCLK).

  2996.   *

  2997.   * @param  __CECCLKSource__ specifies the CEC clock source.

  2998.   *          This parameter can be one of the following values:

  2999.   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock

  3000.   *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock

  3001.   *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

  3002.   */

  3003. #if defined(RCC_D2CCIP2R_CECSEL)

  3004. #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \

  3005.                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

  3006. #else

  3007. #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \

  3008.                   MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

  3009. #endif /* RCC_D2CCIP2R_CECSEL */

  3010. 

  3011. /** @brief  macro to get the CEC clock source.

  3012.   * @retval The clock source can be one of the following values:

  3013.   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock

  3014.   *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock

  3015.   *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

  3016.   */

  3017. #if defined(RCC_D2CCIP2R_CECSEL)

  3018. #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))

  3019. #else

  3020. #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))

  3021. #endif /* RCC_D2CCIP2R_CECSEL */

  3022. 

  3023. /** @brief  Macro to configure the CLKP : Oscillator clock for peripheral

  3024.   * @param  __CLKPSource__ specifies Oscillator clock for peripheral

  3025.   *         This parameter can be one of the following values:

  3026.   *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral

  3027.   *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral

  3028.   *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

  3029.   */

  3030. #if defined(RCC_D1CCIPR_CKPERSEL)

  3031. #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \

  3032.                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

  3033. #else

  3034. #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \

  3035.                   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

  3036. #endif /* RCC_D1CCIPR_CKPERSEL */

  3037. 

  3038. /** @brief  Macro to get the Oscillator clock for peripheral  source.

  3039.   * @retval The clock source can be one of the following values:

  3040.   *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral

  3041.   *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral

  3042.   *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

  3043.   */

  3044. #if defined(RCC_D1CCIPR_CKPERSEL)

  3045. #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))

  3046. #else

  3047. #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))

  3048. #endif /* RCC_D1CCIPR_CKPERSEL */

  3049. 

  3050. #if defined(FDCAN1) || defined(FDCAN2)

  3051. /** @brief  Macro to configure the FDCAN clock

  3052.   * @param  __FDCANCLKSource__ specifies  clock source  for FDCAN

  3053.   *         This parameter can be one of the following values:

  3054.   *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock

  3055.   *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock

  3056.   *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

  3057.   */

  3058. #if defined(RCC_D2CCIP1R_FDCANSEL)

  3059. #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \

  3060.                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

  3061. #else

  3062. #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \

  3063.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

  3064. #endif /* RCC_D2CCIP1R_FDCANSEL */

  3065. 

  3066. /** @brief  Macro to get the FDCAN clock

  3067.   * @retval The clock source can be one of the following values:

  3068.   *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock

  3069.   *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock

  3070.   *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

  3071.   */

  3072. #if defined(RCC_D2CCIP1R_FDCANSEL)

  3073. #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))

  3074. #else

  3075. #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))

  3076. #endif /* RCC_D2CCIP1R_FDCANSEL */

  3077. 

  3078. #endif /*FDCAN1 || FDCAN2*/

  3079. 

  3080. /**

  3081.   * @brief  Macro to Configure the SPI1/2/3 clock source.

  3082.   * @param  __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived

  3083.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  3084.   *          This parameter can be one of the following values:

  3085.   *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL

  3086.   *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2

  3087.   *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3

  3088.   *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP

  3089.   *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock

  3090.   * @retval None

  3091.   */

  3092. #if defined(RCC_D2CCIP1R_SPI123SEL)

  3093. #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\

  3094.                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))

  3095. #else

  3096. #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\

  3097.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))

  3098. #endif /* RCC_D2CCIP1R_SPI123SEL */

  3099. 

  3100. /** @brief  Macro to get the SPI1/2/3 clock source.

  3101.   * @retval The clock source can be one of the following values:

  3102.   *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL

  3103.   *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2

  3104.   *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3

  3105.   *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP

  3106.   *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock

  3107.   */

  3108. #if defined(RCC_D2CCIP1R_SPI123SEL)

  3109. #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))

  3110. #else

  3111. #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))

  3112. #endif /* RCC_D2CCIP1R_SPI123SEL */

  3113. 

  3114. /**

  3115.   * @brief  Macro to Configure the SPI1 clock source.

  3116.   * @param  __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived

  3117.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  3118.   *          This parameter can be one of the following values:

  3119.   *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL

  3120.   *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2

  3121.   *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3

  3122.   *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP

  3123.   *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock

  3124.   * @retval None

  3125.   */

  3126. #define __HAL_RCC_SPI1_CONFIG  __HAL_RCC_SPI123_CONFIG

  3127. 

  3128. /** @brief  Macro to get the SPI1 clock source.

  3129.   * @retval The clock source can be one of the following values:

  3130.   *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL

  3131.   *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2

  3132.   *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3

  3133.   *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP

  3134.   *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock

  3135.   */

  3136. #define __HAL_RCC_GET_SPI1_SOURCE  __HAL_RCC_GET_SPI123_SOURCE

  3137. 

  3138. /**

  3139.   * @brief  Macro to Configure the SPI2 clock source.

  3140.   * @param  __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived

  3141.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  3142.   *          This parameter can be one of the following values:

  3143.   *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL

  3144.   *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2

  3145.   *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3

  3146.   *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP

  3147.   *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock

  3148.   * @retval None

  3149.   */

  3150. #define __HAL_RCC_SPI2_CONFIG  __HAL_RCC_SPI123_CONFIG

  3151. 

  3152. /** @brief  Macro to get the SPI2 clock source.

  3153.   * @retval The clock source can be one of the following values:

  3154.   *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL

  3155.   *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2

  3156.   *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3

  3157.   *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP

  3158.   *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock

  3159.   */

  3160. #define __HAL_RCC_GET_SPI2_SOURCE  __HAL_RCC_GET_SPI123_SOURCE

  3161. 

  3162. /**

  3163.   * @brief  Macro to Configure the SPI3 clock source.

  3164.   * @param  __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived

  3165.   *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

  3166.   *          This parameter can be one of the following values:

  3167.   *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL

  3168.   *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2

  3169.   *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3

  3170.   *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP

  3171.   *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock

  3172.   * @retval None

  3173.   */

  3174. #define __HAL_RCC_SPI3_CONFIG  __HAL_RCC_SPI123_CONFIG

  3175. 

  3176. /** @brief  Macro to get the SPI3 clock source.

  3177.   * @retval The clock source can be one of the following values:

  3178.   *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL

  3179.   *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2

  3180.   *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3

  3181.   *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP

  3182.   *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock

  3183.   */

  3184. #define __HAL_RCC_GET_SPI3_SOURCE  __HAL_RCC_GET_SPI123_SOURCE

  3185. 

  3186. /**

  3187.   * @brief  Macro to Configure the SPI4/5 clock source.

  3188.   * @param  __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived

  3189.   *         from system PCLK, PLL2, PLL3, OSC

  3190.   *          This parameter can be one of the following values:

  3191.   *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1

  3192.   *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2

  3193.   *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3

  3194.   *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI

  3195.   *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI

  3196.   *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE

  3197.   * @retval None

  3198.   */

  3199. #if defined(RCC_D2CCIP1R_SPI45SEL)

  3200. #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\

  3201.                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))

  3202. #else

  3203. #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\

  3204.                   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))

  3205. #endif /* RCC_D2CCIP1R_SPI45SEL */

  3206. 

  3207. /** @brief  Macro to get the SPI4/5 clock source.

  3208.   * @retval The clock source can be one of the following values:

  3209.   *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1

  3210.   *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2

  3211.   *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3

  3212.   *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI

  3213.   *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI

  3214.   *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE

  3215. */

  3216. #if defined(RCC_D2CCIP1R_SPI45SEL)

  3217. #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))

  3218. #else

  3219. #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))

  3220. #endif /* RCC_D2CCIP1R_SPI45SEL */

  3221. 

  3222. /**

  3223.   * @brief  Macro to Configure the SPI4 clock source.

  3224.   * @param  __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived

  3225.   *         from system PCLK, PLL2, PLL3, OSC

  3226.   *          This parameter can be one of the following values:

  3227.   *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1

  3228.   *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2

  3229.   *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3

  3230.   *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI

  3231.   *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI

  3232.   *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE

  3233.   * @retval None

  3234.   */

  3235. #define __HAL_RCC_SPI4_CONFIG  __HAL_RCC_SPI45_CONFIG

  3236. 

  3237. /** @brief  Macro to get the SPI4 clock source.

  3238.   * @retval The clock source can be one of the following values:

  3239.   *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1

  3240.   *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2

  3241.   *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3

  3242.   *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI

  3243.   *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI

  3244.   *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE

  3245. */

  3246. #define __HAL_RCC_GET_SPI4_SOURCE  __HAL_RCC_GET_SPI45_SOURCE

  3247. 

  3248. /**

  3249.   * @brief  Macro to Configure the SPI5 clock source.

  3250.   * @param  __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived

  3251.   *         from system PCLK, PLL2, PLL3, OSC

  3252.   *          This parameter can be one of the following values:

  3253.   *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1

  3254.   *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2

  3255.   *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3

  3256.   *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI

  3257.   *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI

  3258.   *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE

  3259.   * @retval None

  3260.   */

  3261. #define __HAL_RCC_SPI5_CONFIG  __HAL_RCC_SPI45_CONFIG

  3262. 

  3263. /** @brief  Macro to get the SPI5 clock source.

  3264.   * @retval The clock source can be one of the following values:

  3265.   *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1

  3266.   *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2

  3267.   *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3

  3268.   *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI

  3269.   *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI

  3270.   *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE

  3271. */

  3272. #define __HAL_RCC_GET_SPI5_SOURCE  __HAL_RCC_GET_SPI45_SOURCE

  3273. 

  3274. /**

  3275.   * @brief  Macro to Configure the SPI6 clock source.

  3276.   * @param  __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived

  3277.   *         from system PCLK, PLL2, PLL3, OSC

  3278.   *          This parameter can be one of the following values:

  3279.   *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1

  3280.   *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2

  3281.   *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3

  3282.   *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI

  3283.   *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI

  3284.   *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE

  3285.   *             @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN (*)

  3286.   *

  3287.   * @retval None

  3288.   *

  3289.   * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.

  3290.   *

  3291.   */

  3292. #if defined(RCC_D3CCIPR_SPI6SEL)

  3293. #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\

  3294.                   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

  3295. #else

  3296. #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\

  3297.                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

  3298. #endif /* RCC_D3CCIPR_SPI6SEL */

  3299. 

  3300. /** @brief  Macro to get the SPI6 clock source.

  3301.   * @retval The clock source can be one of the following values:

  3302.   *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1

  3303.   *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2

  3304.   *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3

  3305.   *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI

  3306.   *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI

  3307.   *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE

  3308.   *                @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN

  3309. */

  3310. #if defined(RCC_D3CCIPR_SPI6SEL)

  3311. #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))

  3312. #else

  3313. #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))

  3314. #endif /* RCC_D3CCIPR_SPI6SEL */

  3315. 

  3316. /** @brief  Macro to configure the SDMMC clock

  3317.   * @param  __SDMMCCLKSource__ specifies  clock source  for SDMMC

  3318.   *         This parameter can be one of the following values:

  3319.   *            @arg RCC_SDMMCCLKSOURCE_PLL:  PLLQ selected as SDMMC clock

  3320.   *            @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock

  3321.   */

  3322. #if defined(RCC_D1CCIPR_SDMMCSEL)

  3323. #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \

  3324.                   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

  3325. #else

  3326. #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \

  3327.                   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

  3328. #endif /* RCC_D1CCIPR_SDMMCSEL */

  3329. 

  3330. /** @brief  Macro to get the SDMMC clock

  3331.   */

  3332. #if defined(RCC_D1CCIPR_SDMMCSEL)

  3333. #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))

  3334. #else

  3335. #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))

  3336. #endif /* RCC_D1CCIPR_SDMMCSEL */

  3337. 

  3338. /** @brief macro to configure the RNG clock (RNGCLK).

  3339.   *

  3340.   * @param  __RNGCLKSource__ specifies the RNG clock source.

  3341.   *          This parameter can be one of the following values:

  3342.   *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock

  3343.   *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock

  3344.   *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock

  3345.   *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

  3346.   */

  3347. #if defined(RCC_D2CCIP2R_RNGSEL)

  3348. #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \

  3349.                   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

  3350. #else

  3351. #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \

  3352.                   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

  3353. #endif /* RCC_D2CCIP2R_RNGSEL */

  3354. 

  3355. /** @brief  macro to get the RNG clock source.

  3356.   * @retval The clock source can be one of the following values:

  3357.   *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock

  3358.   *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock

  3359.   *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock

  3360.   *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

  3361.   */

  3362. #if defined(RCC_D2CCIP2R_RNGSEL)

  3363. #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))

  3364. #else

  3365. #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))

  3366. #endif /* RCC_D2CCIP2R_RNGSEL */

  3367. 

  3368. #if defined(HRTIM1)

  3369. /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config

  3370.   * @{

  3371.   */

  3372. /** @brief  Macro to configure the HRTIM1 prescaler clock source.

  3373.   * @param  __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.

  3374.   *         This parameter can be one of the following values:

  3375.   *            @arg @ref RCC_HRTIM1CLK_TIMCLK    Timers  clock  selected as HRTIM1 prescaler clock

  3376.   *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock

  3377.   */

  3378. #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \

  3379.                   MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))

  3380. 

  3381. /** @brief  Macro to get the HRTIM1 clock source.

  3382.   * @retval The clock source can be one of the following values:

  3383.   *            @arg @ref RCC_HRTIM1CLK_TIMCLK   Timers  clock  selected as HRTIM1 prescaler clock

  3384.   *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock

  3385.   */

  3386. #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))

  3387. #endif /* HRTIM1 */

  3388. 

  3389. /** @brief  Macro to configure the Timers clocks prescalers

  3390.   * @param  __PRESC__  specifies the Timers clocks prescalers selection

  3391.   *         This parameter can be one of the following values:

  3392.   *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is

  3393.   *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,

  3394.   *                 else it is equal to 2 x Frcc_pclkx_d2 (default after reset)

  3395.   *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is

  3396.   *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,

  3397.   *                 else it is equal to 4 x Frcc_pclkx_d2

  3398.   */

  3399. #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\

  3400.                                                  RCC->CFGR |= (__PRESC__);       \

  3401.                                                 }while(0)

  3402. 

  3403. /**

  3404.   * @}

  3405.   */

  3406. /**

  3407.   * @brief  Enable the specified CRS interrupts.

  3408.   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.

  3409.   *          This parameter can be any combination of the following values:

  3410.   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt

  3411.   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt

  3412.   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt

  3413.   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt

  3414.   * @retval None

  3415.   */

  3416. #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))

  3417. 

  3418. /**

  3419.   * @brief  Disable the specified CRS interrupts.

  3420.   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.

  3421.   *          This parameter can be any combination of the following values:

  3422.   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt

  3423.   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt

  3424.   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt

  3425.   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt

  3426.   * @retval None

  3427.   */

  3428. #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))

  3429. 

  3430. /** @brief  Check whether the CRS interrupt has occurred or not.

  3431.   * @param  __INTERRUPT__ specifies the CRS interrupt source to check.

  3432.   *         This parameter can be one of the following values:

  3433.   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt

  3434.   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt

  3435.   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt

  3436.   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt

  3437.   * @retval The new state of __INTERRUPT__ (SET or RESET).

  3438.   */

  3439. #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)

  3440. 

  3441. /** @brief  Clear the CRS interrupt pending bits

  3442.   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

  3443.   *         This parameter can be any combination of the following values:

  3444.   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt

  3445.   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt

  3446.   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt

  3447.   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt

  3448.   *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt

  3449.   *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt

  3450.   *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt

  3451.   */

  3452. /* CRS IT Error Mask */

  3453. #define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))

  3454. 

  3455. #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \

  3456.                                                  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \

  3457.                                                  { \

  3458.                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \

  3459.                                                  } \

  3460.                                                  else \

  3461.                                                  { \

  3462.                                                    WRITE_REG(CRS->ICR, (__INTERRUPT__)); \

  3463.                                                  } \

  3464.                                                } while(0)

  3465. 

  3466. /**

  3467.   * @brief  Check whether the specified CRS flag is set or not.

  3468.   * @param  __FLAG__ specifies the flag to check.

  3469.   *          This parameter can be one of the following values:

  3470.   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK

  3471.   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning

  3472.   *              @arg @ref RCC_CRS_FLAG_ERR  Error

  3473.   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC

  3474.   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow

  3475.   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error

  3476.   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed

  3477.   * @retval The new state of _FLAG_ (TRUE or FALSE).

  3478.   */

  3479. #define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

  3480. 

  3481. /**

  3482.   * @brief  Clear the CRS specified FLAG.

  3483.   * @param __FLAG__ specifies the flag to clear.

  3484.   *          This parameter can be one of the following values:

  3485.   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK

  3486.   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning

  3487.   *              @arg @ref RCC_CRS_FLAG_ERR  Error

  3488.   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC

  3489.   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow

  3490.   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error

  3491.   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed

  3492.   * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR

  3493.   * @retval None

  3494.   */

  3495. 

  3496. /* CRS Flag Error Mask */

  3497. #define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))

  3498. 

  3499. #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \

  3500.                                                  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \

  3501.                                                  { \

  3502.                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \

  3503.                                                  } \

  3504.                                                  else \

  3505.                                                  { \

  3506.                                                    WRITE_REG(CRS->ICR, (__FLAG__)); \

  3507.                                                  } \

  3508.                                                } while(0)

  3509. 

  3510.  /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features

  3511.   * @{

  3512.   */

  3513. /**

  3514.   * @brief  Enable the oscillator clock for frequency error counter.

  3515.   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.

  3516.   * @retval None

  3517.   */

  3518. #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)

  3519. 

  3520. /**

  3521.   * @brief  Disable the oscillator clock for frequency error counter.

  3522.   * @retval None

  3523.   */

  3524. #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)

  3525. 

  3526. /**

  3527.   * @brief  Enable the automatic hardware adjustment of TRIM bits.

  3528.   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.

  3529.   * @retval None

  3530.   */

  3531. #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

  3532. 

  3533. /**

  3534.   * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.

  3535.   * @retval None

  3536.   */

  3537. #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

  3538. 

  3539. /**

  3540.   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies

  3541.   * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency

  3542.   *             of the synchronization source after pre-scaling. It is then decreased by one in order to

  3543.   *             reach the expected synchronization on the zero value. The formula is the following:

  3544.   *             RELOAD = (fTARGET / fSYNC) -1

  3545.   * @param  __FTARGET__ Target frequency (value in Hz)

  3546.   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)

  3547.   * @retval None

  3548.   */

  3549. #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)

  3550. 

  3551. 

  3552. /**

  3553.   * @}

  3554.   */

  3555. 

  3556. 

  3557. /**

  3558.   * @}

  3559.   */

  3560. 

  3561. 

  3562. /* Exported functions --------------------------------------------------------*/

  3563. /** @addtogroup RCCEx_Exported_Functions_Group1

  3564.   * @{

  3565.   */

  3566. HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);

  3567. void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);

  3568. uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);

  3569. uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);

  3570. uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);

  3571. uint32_t HAL_RCCEx_GetD1SysClockFreq(void);

  3572. void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);

  3573. void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);

  3574. void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);

  3575. /**

  3576.   * @}

  3577.   */

  3578. 

  3579. /** @addtogroup RCCEx_Exported_Functions_Group2

  3580.   * @{

  3581.   */

  3582. void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);

  3583. void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);

  3584. void HAL_RCCEx_EnableLSECSS(void);

  3585. void HAL_RCCEx_DisableLSECSS(void);

  3586. #if defined(DUAL_CORE)

  3587. void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);

  3588. #endif /*DUAL_CORE*/

  3589. #if defined(RCC_GCR_WW1RSC)

  3590. void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);

  3591. #endif /*RCC_GCR_WW1RSC*/

  3592. /**

  3593.   * @}

  3594.   */

  3595. 

  3596. 

  3597. /** @addtogroup RCCEx_Exported_Functions_Group3

  3598.   * @{

  3599.   */

  3600. 

  3601. void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);

  3602. void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);

  3603. void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);

  3604. uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);

  3605. void     HAL_RCCEx_CRS_IRQHandler(void);

  3606. void     HAL_RCCEx_CRS_SyncOkCallback(void);

  3607. void     HAL_RCCEx_CRS_SyncWarnCallback(void);

  3608. void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);

  3609. void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);

  3610. 

  3611. /**

  3612.   * @}

  3613.   */

  3614. 

  3615.  /* Private macros ------------------------------------------------------------*/

  3616. /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros

  3617.   * @{

  3618.   */

  3619. /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters

  3620.   * @{

  3621.   */

  3622. 

  3623. #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \

  3624.                                          ((VALUE) == RCC_PLL2_DIVQ)  || \

  3625.                                          ((VALUE) == RCC_PLL2_DIVR))

  3626. 

  3627. #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \

  3628.                                           ((VALUE) == RCC_PLL3_DIVQ) || \

  3629.                                           ((VALUE) == RCC_PLL3_DIVR))

  3630. 

  3631. #if defined(RCC_D2CCIP2R_USART16SEL)

  3632. #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \

  3633.                                          ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \

  3634.                                          ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \

  3635.                                          ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \

  3636.                                          ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \

  3637.                                          ((SOURCE) == RCC_USART16CLKSOURCE_HSI))

  3638. #else

  3639. #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \

  3640.                                          ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \

  3641.                                          ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \

  3642.                                          ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \

  3643.                                          ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \

  3644.                                          ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \

  3645.                                          ((SOURCE) == RCC_USART16CLKSOURCE_HSI))

  3646. /* alias*/

  3647. #define IS_RCC_USART16910CLKSOURCE    IS_RCC_USART16CLKSOURCE

  3648. #endif /* RCC_D2CCIP2R_USART16SEL */

  3649. 

  3650. #if defined(RCC_D2CCIP2R_USART28SEL)

  3651. #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \

  3652.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \

  3653.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \

  3654.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \

  3655.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \

  3656.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))

  3657. #else

  3658. #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \

  3659.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \

  3660.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \

  3661.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \

  3662.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \

  3663.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \

  3664.                                              ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))

  3665. #endif /* RCC_D2CCIP2R_USART28SEL */

  3666. 

  3667. #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \

  3668.                                         ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \

  3669.                                         ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \

  3670.                                         ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \

  3671.                                         ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \

  3672.                                         ((SOURCE) == RCC_USART1CLKSOURCE_HSI))

  3673. 

  3674. #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \

  3675.                                         ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \

  3676.                                         ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \

  3677.                                         ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \

  3678.                                         ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \

  3679.                                         ((SOURCE) == RCC_USART2CLKSOURCE_HSI))

  3680. 

  3681. #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \

  3682.                                         ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \

  3683.                                         ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \

  3684.                                         ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \

  3685.                                         ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \

  3686.                                         ((SOURCE) == RCC_USART3CLKSOURCE_HSI))

  3687. 

  3688. #define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \

  3689.                                         ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \

  3690.                                         ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \

  3691.                                         ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \

  3692.                                         ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \

  3693.                                         ((SOURCE) == RCC_UART4CLKSOURCE_HSI))

  3694. 

  3695. #define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \

  3696.                                         ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \

  3697.                                         ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \

  3698.                                         ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \

  3699.                                         ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \

  3700.                                         ((SOURCE) == RCC_UART5CLKSOURCE_HSI))

  3701. 

  3702. #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \

  3703.                                         ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \

  3704.                                         ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \

  3705.                                         ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \

  3706.                                         ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \

  3707.                                         ((SOURCE) == RCC_USART6CLKSOURCE_HSI))

  3708. 

  3709. #define IS_RCC_UART7CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \

  3710.                                         ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \

  3711.                                         ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \

  3712.                                         ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \

  3713.                                         ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \

  3714.                                         ((SOURCE) == RCC_UART7CLKSOURCE_HSI))

  3715. 

  3716. #define IS_RCC_UART8CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \

  3717.                                         ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \

  3718.                                         ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \

  3719.                                         ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \

  3720.                                         ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \

  3721.                                         ((SOURCE) == RCC_UART8CLKSOURCE_HSI))

  3722. 

  3723. #if defined(UART9)

  3724. #define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \

  3725.                                         ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \

  3726.                                         ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \

  3727.                                         ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \

  3728.                                         ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \

  3729.                                         ((SOURCE) == RCC_UART9CLKSOURCE_HSI))

  3730. #endif

  3731. 

  3732. #if defined(USART10)

  3733. #define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \

  3734.                                         ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \

  3735.                                         ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \

  3736.                                         ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \

  3737.                                         ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \

  3738.                                         ((SOURCE) == RCC_USART10CLKSOURCE_HSI))

  3739. #endif

  3740. 

  3741. #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \

  3742.                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \

  3743.                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \

  3744.                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \

  3745.                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \

  3746.                                          ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))

  3747. 

  3748. #define IS_RCC_I2C123CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \

  3749.                                           ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \

  3750.                                           ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \

  3751.                                           ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))

  3752. 

  3753. #define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \

  3754.                                         ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \

  3755.                                         ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \

  3756.                                         ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))

  3757. 

  3758. #define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \

  3759.                                         ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \

  3760.                                         ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \

  3761.                                         ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))

  3762. 

  3763. #define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \

  3764.                                         ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \

  3765.                                         ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \

  3766.                                         ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

  3767. 

  3768. #define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \

  3769.                                         ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \

  3770.                                         ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \

  3771.                                         ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

  3772. 

  3773. #define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \

  3774.                                         ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \

  3775.                                         ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \

  3776.                                         ((SOURCE) == RCC_RNGCLKSOURCE_LSI))

  3777. 

  3778. #if defined(HRTIM1)

  3779. #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \

  3780.                                         ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))

  3781. #endif

  3782. 

  3783. #define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \

  3784.                                         ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \

  3785.                                         ((SOURCE) == RCC_USBCLKSOURCE_HSI48))

  3786. 

  3787. #define IS_RCC_SAI1CLK(__SOURCE__)   \

  3788.                (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \

  3789.                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \

  3790.                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \

  3791.                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \

  3792.                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))

  3793. 

  3794. #if defined(SAI3)

  3795. #define IS_RCC_SAI23CLK(__SOURCE__)   \

  3796.                (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL)  || \

  3797.                 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \

  3798.                 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \

  3799.                 ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \

  3800.                 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))

  3801. 

  3802. #define IS_RCC_SAI2CLK(__SOURCE__)   \

  3803.                (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \

  3804.                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \

  3805.                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \

  3806.                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \

  3807.                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))

  3808. 

  3809. 

  3810. #define IS_RCC_SAI3CLK(__SOURCE__)   \

  3811.                (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \

  3812.                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \

  3813.                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \

  3814.                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \

  3815.                 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))

  3816. #endif

  3817. 

  3818. #if defined(RCC_CDCCIP1R_SAI2ASEL)

  3819. #define IS_RCC_SAI2ACLK(__SOURCE__)   \

  3820.                (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \

  3821.                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \

  3822.                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \

  3823.                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \

  3824.                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \

  3825.                 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))

  3826. #endif

  3827. 

  3828. #if defined(RCC_CDCCIP1R_SAI2BSEL)

  3829. #define IS_RCC_SAI2BCLK(__SOURCE__)   \

  3830.                (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \

  3831.                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \

  3832.                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \

  3833.                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \

  3834.                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \

  3835.                 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))

  3836. #endif

  3837. 

  3838. #define IS_RCC_SPI123CLK(__SOURCE__)   \

  3839.                (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \

  3840.                 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \

  3841.                 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \

  3842.                 ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \

  3843.                 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))

  3844. 

  3845. #define IS_RCC_SPI1CLK(__SOURCE__)   \

  3846.                (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \

  3847.                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \

  3848.                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \

  3849.                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \

  3850.                 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))

  3851. 

  3852. #define IS_RCC_SPI2CLK(__SOURCE__)   \

  3853.                (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \

  3854.                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \

  3855.                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \

  3856.                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \

  3857.                 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))

  3858. 

  3859. #define IS_RCC_SPI3CLK(__SOURCE__)   \

  3860.                (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \

  3861.                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \

  3862.                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \

  3863.                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \

  3864.                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))

  3865. 

  3866. #define IS_RCC_SPI45CLK(__SOURCE__)   \

  3867.                (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \

  3868.                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \

  3869.                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \

  3870.                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \

  3871.                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \

  3872.                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))

  3873. 

  3874. #define IS_RCC_SPI4CLK(__SOURCE__)   \

  3875.                (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \

  3876.                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \

  3877.                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \

  3878.                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \

  3879.                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \

  3880.                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))

  3881. 

  3882. #define IS_RCC_SPI5CLK(__SOURCE__)   \

  3883.                (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \

  3884.                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \

  3885.                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \

  3886.                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \

  3887.                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \

  3888.                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))

  3889. 

  3890. #if defined(RCC_D3CCIPR_SPI6SEL)

  3891. #define IS_RCC_SPI6CLK(__SOURCE__)   \

  3892.                (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \

  3893.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \

  3894.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \

  3895.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \

  3896.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \

  3897.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))

  3898. #else

  3899. #define IS_RCC_SPI6CLK(__SOURCE__)   \

  3900.                (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \

  3901.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \

  3902.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \

  3903.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \

  3904.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \

  3905.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \

  3906.                 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))

  3907. #endif /* RCC_D3CCIPR_SPI6SEL */

  3908. 

  3909. #if defined(SAI4)

  3910. #define IS_RCC_SAI4ACLK(__SOURCE__)   \

  3911.                (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \

  3912.                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \

  3913.                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \

  3914.                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \

  3915.                 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))

  3916. 

  3917. #define IS_RCC_SAI4BCLK(__SOURCE__)   \

  3918.                (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \

  3919.                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \

  3920.                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \

  3921.                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \

  3922.                 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))

  3923. #endif /*SAI4*/

  3924. 

  3925. #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

  3926. #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

  3927. #define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  3928. #define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  3929. #define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  3930. 

  3931. #define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

  3932. #define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

  3933. #define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  3934. #define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  3935. #define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

  3936. 

  3937. #define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0)  || \

  3938.                                     ((VALUE) == RCC_PLL2VCIRANGE_1)   || \

  3939.                                     ((VALUE) == RCC_PLL2VCIRANGE_2)   || \

  3940.                                     ((VALUE) == RCC_PLL2VCIRANGE_3))

  3941. 

  3942. #define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0)  || \

  3943.                                     ((VALUE) == RCC_PLL3VCIRANGE_1)   || \

  3944.                                     ((VALUE) == RCC_PLL3VCIRANGE_2)   || \

  3945.                                     ((VALUE) == RCC_PLL3VCIRANGE_3))

  3946. 

  3947. #define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE)  || \

  3948.                                     ((VALUE) == RCC_PLL2VCOMEDIUM))

  3949. 

  3950. #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE)  || \

  3951.                                     ((VALUE) == RCC_PLL3VCOMEDIUM))

  3952. 

  3953. #define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)

  3954. 

  3955. #define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \

  3956.                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \

  3957.                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \

  3958.                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \

  3959.                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \

  3960.                                         ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))

  3961. 

  3962. #define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \

  3963.                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \

  3964.                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \

  3965.                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \

  3966.                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \

  3967.                                         ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))

  3968. 

  3969. #define IS_RCC_LPTIM345CLK(SOURCE)     (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \

  3970.                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \

  3971.                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \

  3972.                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \

  3973.                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \

  3974.                                         ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))

  3975. 

  3976. #define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \

  3977.                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \

  3978.                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \

  3979.                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \

  3980.                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \

  3981.                                         ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))

  3982. 

  3983. #if defined(LPTIM4)

  3984. #define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \

  3985.                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \

  3986.                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \

  3987.                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \

  3988.                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \

  3989.                                         ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))

  3990. #endif /* LPTIM4*/

  3991. 

  3992. #if defined(LPTIM5)

  3993. #define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \

  3994.                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \

  3995.                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \

  3996.                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \

  3997.                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \

  3998.                                         ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))

  3999. #endif /*LPTIM5*/

  4000. 

  4001. #if defined(QUADSPI)

  4002. #define IS_RCC_QSPICLK(__SOURCE__)   \

  4003.                (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \

  4004.                 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \

  4005.                 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \

  4006.                 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))

  4007. #endif /*QUADSPI*/

  4008. 

  4009. #if defined(OCTOSPI1) || defined(OCTOSPI1)

  4010. #define IS_RCC_OSPICLK(__SOURCE__)   \

  4011.                (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \

  4012.                 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \

  4013.                 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \

  4014.                 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))

  4015. #endif /*OCTOSPI1 || OCTOSPI1*/

  4016. 

  4017. #if defined(DSI)

  4018. #define IS_RCC_DSICLK(__SOURCE__)   \

  4019.                (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \

  4020.                 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))

  4021. #endif /*DSI*/

  4022. 

  4023. #define IS_RCC_FMCCLK(__SOURCE__)   \

  4024.                (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \

  4025.                 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \

  4026.                 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \

  4027.                 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))

  4028. 

  4029. #if defined(FDCAN1) || defined(FDCAN2)

  4030. #define IS_RCC_FDCANCLK(__SOURCE__)   \

  4031.                (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \

  4032.                 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \

  4033.                 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))

  4034. #endif /*FDCAN1 || FDCAN2*/

  4035. 

  4036. #define IS_RCC_SDMMC(__SOURCE__)   \

  4037.                 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \

  4038.                 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))

  4039. 

  4040. #define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \

  4041.                                         ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \

  4042.                                         ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))

  4043. 

  4044. #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \

  4045.                                         ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))

  4046. 

  4047. #define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \

  4048.                                          ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))

  4049. 

  4050. #if defined(DFSDM2_BASE)

  4051. #define IS_RCC_DFSDM2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \

  4052.                                         ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))

  4053. #endif /*DFSDM2*/

  4054. 

  4055. #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \

  4056.                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \

  4057.                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \

  4058.                                         ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))

  4059. 

  4060. #define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \

  4061.                                       ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \

  4062.                                       ((SOURCE) == RCC_CECCLKSOURCE_CSI))

  4063. 

  4064. #define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \

  4065.                                       ((SOURCE) == RCC_CLKPSOURCE_CSI) || \

  4066.                                       ((SOURCE) == RCC_CLKPSOURCE_HSE))

  4067. #define IS_RCC_TIMPRES(VALUE)  \

  4068.                (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \

  4069.                 ((VALUE) == RCC_TIMPRES_ACTIVATED))

  4070. 

  4071. #if defined(DUAL_CORE)

  4072. #define IS_RCC_BOOT_CORE(CORE)   (((CORE) == RCC_BOOT_C1)  || \

  4073.                                   ((CORE) == RCC_BOOT_C2))

  4074. #endif /*DUAL_CORE*/

  4075. 

  4076. #if defined(DUAL_CORE)

  4077. #define IS_RCC_SCOPE_WWDG(WWDG)   (((WWDG) == RCC_WWDG1)  || \

  4078.                                   ((WWDG) == RCC_WWDG2))

  4079. #else

  4080. #define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)

  4081. 

  4082. #endif /*DUAL_CORE*/

  4083. 

  4084. #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \

  4085.                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \

  4086.                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \

  4087.                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))

  4088. 

  4089. #define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \

  4090.                                             ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \

  4091.                                             ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \

  4092.                                             ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))

  4093. 

  4094. #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \

  4095.                                                 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))

  4096. 

  4097. #define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))

  4098. 

  4099. #define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))

  4100. 

  4101. #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))

  4102. 

  4103. #define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \

  4104.                                             ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

  4105. /**

  4106.   * @}

  4107.   */

  4108. 

  4109. /**

  4110.   * @}

  4111.   */

  4112. 

  4113. /**

  4114.   * @}

  4115.   */

  4116. 

  4117. #ifdef __cplusplus

  4118. }

  4119. #endif

  4120. 

  4121. #endif /* STM32H7xx_HAL_RCC_EX_H */

  4122. 

  4123. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/