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stm32lib/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32wbxx_hal.h

  4.   * @author  MCD Application Team

  5.   * @brief   This file contains all the functions prototypes for the HAL

  6.   *          module driver.

  7.   ******************************************************************************

  8.   * @attention

  9.   *

  10.   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

  11.   * All rights reserved.</center></h2>

  12.   *

  13.   * This software component is licensed by ST under BSD 3-Clause license,

  14.   * the "License"; You may not use this file except in compliance with the

  15.   * License. You may obtain a copy of the License at:

  16.   *                        opensource.org/licenses/BSD-3-Clause

  17.   *

  18.   ******************************************************************************

  19.   */

  20. 

  21. /* Define to prevent recursive inclusion -------------------------------------*/

  22. #ifndef STM32WBxx_HAL_H

  23. #define STM32WBxx_HAL_H

  24. 

  25. #ifdef __cplusplus

  26.  extern "C" {

  27. #endif

  28. 

  29. /* Includes ------------------------------------------------------------------*/

  30. #include "stm32wbxx_hal_conf.h"

  31. #include "stm32wbxx_ll_system.h"

  32. 

  33. /** @addtogroup STM32WBxx_HAL_Driver

  34.   * @{

  35.   */

  36. 

  37. /** @defgroup HAL HAL

  38.   * @{

  39.   */

  40. 

  41. /** @defgroup HAL_TICK_FREQ Tick Frequency

  42.   * @{

  43.   */

  44. typedef enum

  45. {

  46.   HAL_TICK_FREQ_10HZ         = 100U,

  47.   HAL_TICK_FREQ_100HZ        = 10U,

  48.   HAL_TICK_FREQ_1KHZ         = 1U,

  49.   HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ

  50. } HAL_TickFreqTypeDef;

  51. 

  52. /**

  53.   * @}

  54.   */

  55. 

  56. /* Exported constants --------------------------------------------------------*/

  57. /** @defgroup HAL_Exported_Constants HAL Exported Constants

  58.   * @{

  59.   */

  60. 

  61. /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants

  62.   * @{

  63.   */

  64. 

  65. /** @defgroup SYSCFG_BootMode BOOT Mode

  66.   * @{

  67.   */

  68. #define SYSCFG_BOOT_MAINFLASH           LL_SYSCFG_REMAP_FLASH           /*!< Main Flash memory mapped at 0x00000000   */

  69. #define SYSCFG_BOOT_SYSTEMFLASH         LL_SYSCFG_REMAP_SYSTEMFLASH     /*!< System Flash memory mapped at 0x00000000 */

  70. #define SYSCFG_BOOT_SRAM                LL_SYSCFG_REMAP_SRAM            /*!< SRAM1 mapped at 0x00000000               */

  71. #if defined(LL_SYSCFG_REMAP_QUADSPI)

  72. #define SYSCFG_BOOT_QUADSPI             LL_SYSCFG_REMAP_QUADSPI         /*!< QUADSPI memory mapped at 0x00000000      */

  73. #endif

  74. /**

  75.   * @}

  76.   */

  77. 

  78. /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts

  79.   * @{

  80.   */

  81. #define SYSCFG_IT_FPU_IOC               SYSCFG_CFGR1_FPU_IE_0           /*!< Floating Point Unit Invalid operation Interrupt */

  82. #define SYSCFG_IT_FPU_DZC               SYSCFG_CFGR1_FPU_IE_1           /*!< Floating Point Unit Divide-by-zero Interrupt    */

  83. #define SYSCFG_IT_FPU_UFC               SYSCFG_CFGR1_FPU_IE_2           /*!< Floating Point Unit Underflow Interrupt         */

  84. #define SYSCFG_IT_FPU_OFC               SYSCFG_CFGR1_FPU_IE_3           /*!< Floating Point Unit Overflow Interrupt          */

  85. #define SYSCFG_IT_FPU_IDC               SYSCFG_CFGR1_FPU_IE_4           /*!< Floating Point Unit Input denormal Interrupt    */

  86. #define SYSCFG_IT_FPU_IXC               SYSCFG_CFGR1_FPU_IE_5           /*!< Floating Point Unit Inexact Interrupt           */

  87. 

  88. /**

  89.   * @}

  90.   */

  91. 

  92. /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)

  93.   * @{

  94.   */

  95. #define SYSCFG_SRAM2WRP_PAGE0           LL_SYSCFG_SRAM2WRP_PAGE0        /*!< SRAM2A Write protection page 0  */

  96. #define SYSCFG_SRAM2WRP_PAGE1           LL_SYSCFG_SRAM2WRP_PAGE1        /*!< SRAM2A Write protection page 1  */

  97. #define SYSCFG_SRAM2WRP_PAGE2           LL_SYSCFG_SRAM2WRP_PAGE2        /*!< SRAM2A Write protection page 2  */

  98. #define SYSCFG_SRAM2WRP_PAGE3           LL_SYSCFG_SRAM2WRP_PAGE3        /*!< SRAM2A Write protection page 3  */

  99. #define SYSCFG_SRAM2WRP_PAGE4           LL_SYSCFG_SRAM2WRP_PAGE4        /*!< SRAM2A Write protection page 4  */

  100. #define SYSCFG_SRAM2WRP_PAGE5           LL_SYSCFG_SRAM2WRP_PAGE5        /*!< SRAM2A Write protection page 5  */

  101. #define SYSCFG_SRAM2WRP_PAGE6           LL_SYSCFG_SRAM2WRP_PAGE6        /*!< SRAM2A Write protection page 6  */

  102. #define SYSCFG_SRAM2WRP_PAGE7           LL_SYSCFG_SRAM2WRP_PAGE7        /*!< SRAM2A Write protection page 7  */

  103. #define SYSCFG_SRAM2WRP_PAGE8           LL_SYSCFG_SRAM2WRP_PAGE8        /*!< SRAM2A Write protection page 8  */

  104. #define SYSCFG_SRAM2WRP_PAGE9           LL_SYSCFG_SRAM2WRP_PAGE9        /*!< SRAM2A Write protection page 9  */

  105. #define SYSCFG_SRAM2WRP_PAGE10          LL_SYSCFG_SRAM2WRP_PAGE10       /*!< SRAM2A Write protection page 10 */

  106. #define SYSCFG_SRAM2WRP_PAGE11          LL_SYSCFG_SRAM2WRP_PAGE11       /*!< SRAM2A Write protection page 11 */

  107. #define SYSCFG_SRAM2WRP_PAGE12          LL_SYSCFG_SRAM2WRP_PAGE12       /*!< SRAM2A Write protection page 12 */

  108. #define SYSCFG_SRAM2WRP_PAGE13          LL_SYSCFG_SRAM2WRP_PAGE13       /*!< SRAM2A Write protection page 13 */

  109. #define SYSCFG_SRAM2WRP_PAGE14          LL_SYSCFG_SRAM2WRP_PAGE14       /*!< SRAM2A Write protection page 14 */

  110. #define SYSCFG_SRAM2WRP_PAGE15          LL_SYSCFG_SRAM2WRP_PAGE15       /*!< SRAM2A Write protection page 15 */

  111. #define SYSCFG_SRAM2WRP_PAGE16          LL_SYSCFG_SRAM2WRP_PAGE16       /*!< SRAM2A Write protection page 16 */

  112. #define SYSCFG_SRAM2WRP_PAGE17          LL_SYSCFG_SRAM2WRP_PAGE17       /*!< SRAM2A Write protection page 17 */

  113. #define SYSCFG_SRAM2WRP_PAGE18          LL_SYSCFG_SRAM2WRP_PAGE18       /*!< SRAM2A Write protection page 18 */

  114. #define SYSCFG_SRAM2WRP_PAGE19          LL_SYSCFG_SRAM2WRP_PAGE19       /*!< SRAM2A Write protection page 19 */

  115. #define SYSCFG_SRAM2WRP_PAGE20          LL_SYSCFG_SRAM2WRP_PAGE20       /*!< SRAM2A Write protection page 20 */

  116. #define SYSCFG_SRAM2WRP_PAGE21          LL_SYSCFG_SRAM2WRP_PAGE21       /*!< SRAM2A Write protection page 21 */

  117. #define SYSCFG_SRAM2WRP_PAGE22          LL_SYSCFG_SRAM2WRP_PAGE22       /*!< SRAM2A Write protection page 22 */

  118. #define SYSCFG_SRAM2WRP_PAGE23          LL_SYSCFG_SRAM2WRP_PAGE23       /*!< SRAM2A Write protection page 23 */

  119. #define SYSCFG_SRAM2WRP_PAGE24          LL_SYSCFG_SRAM2WRP_PAGE24       /*!< SRAM2A Write protection page 24 */

  120. #define SYSCFG_SRAM2WRP_PAGE25          LL_SYSCFG_SRAM2WRP_PAGE25       /*!< SRAM2A Write protection page 25 */

  121. #define SYSCFG_SRAM2WRP_PAGE26          LL_SYSCFG_SRAM2WRP_PAGE26       /*!< SRAM2A Write protection page 26 */

  122. #define SYSCFG_SRAM2WRP_PAGE27          LL_SYSCFG_SRAM2WRP_PAGE27       /*!< SRAM2A Write protection page 27 */

  123. #define SYSCFG_SRAM2WRP_PAGE28          LL_SYSCFG_SRAM2WRP_PAGE28       /*!< SRAM2A Write protection page 28 */

  124. #define SYSCFG_SRAM2WRP_PAGE29          LL_SYSCFG_SRAM2WRP_PAGE29       /*!< SRAM2A Write protection page 29 */

  125. #define SYSCFG_SRAM2WRP_PAGE30          LL_SYSCFG_SRAM2WRP_PAGE30       /*!< SRAM2A Write protection page 30 */

  126. #define SYSCFG_SRAM2WRP_PAGE31          LL_SYSCFG_SRAM2WRP_PAGE31       /*!< SRAM2A Write protection page 31 */

  127. 

  128. /**

  129.   * @}

  130.   */

  131. 

  132. /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)

  133.   * @{

  134.   */

  135. #define SYSCFG_SRAM2WRP_PAGE32          LL_SYSCFG_SRAM2WRP_PAGE32       /*!< SRAM2B Write protection page 32 */

  136. #define SYSCFG_SRAM2WRP_PAGE33          LL_SYSCFG_SRAM2WRP_PAGE33       /*!< SRAM2B Write protection page 33 */

  137. #define SYSCFG_SRAM2WRP_PAGE34          LL_SYSCFG_SRAM2WRP_PAGE34       /*!< SRAM2B Write protection page 34 */

  138. #define SYSCFG_SRAM2WRP_PAGE35          LL_SYSCFG_SRAM2WRP_PAGE35       /*!< SRAM2B Write protection page 35 */

  139. #define SYSCFG_SRAM2WRP_PAGE36          LL_SYSCFG_SRAM2WRP_PAGE36       /*!< SRAM2B Write protection page 36 */

  140. #define SYSCFG_SRAM2WRP_PAGE37          LL_SYSCFG_SRAM2WRP_PAGE37       /*!< SRAM2B Write protection page 37 */

  141. #define SYSCFG_SRAM2WRP_PAGE38          LL_SYSCFG_SRAM2WRP_PAGE38       /*!< SRAM2B Write protection page 38 */

  142. #define SYSCFG_SRAM2WRP_PAGE39          LL_SYSCFG_SRAM2WRP_PAGE39       /*!< SRAM2B Write protection page 39 */

  143. #define SYSCFG_SRAM2WRP_PAGE40          LL_SYSCFG_SRAM2WRP_PAGE40       /*!< SRAM2B Write protection page 40 */

  144. #define SYSCFG_SRAM2WRP_PAGE41          LL_SYSCFG_SRAM2WRP_PAGE41       /*!< SRAM2B Write protection page 41 */

  145. #define SYSCFG_SRAM2WRP_PAGE42          LL_SYSCFG_SRAM2WRP_PAGE42       /*!< SRAM2B Write protection page 42 */

  146. #define SYSCFG_SRAM2WRP_PAGE43          LL_SYSCFG_SRAM2WRP_PAGE43       /*!< SRAM2B Write protection page 43 */

  147. #define SYSCFG_SRAM2WRP_PAGE44          LL_SYSCFG_SRAM2WRP_PAGE44       /*!< SRAM2B Write protection page 44 */

  148. #define SYSCFG_SRAM2WRP_PAGE45          LL_SYSCFG_SRAM2WRP_PAGE45       /*!< SRAM2B Write protection page 45 */

  149. #define SYSCFG_SRAM2WRP_PAGE46          LL_SYSCFG_SRAM2WRP_PAGE46       /*!< SRAM2B Write protection page 46 */

  150. #define SYSCFG_SRAM2WRP_PAGE47          LL_SYSCFG_SRAM2WRP_PAGE47       /*!< SRAM2B Write protection page 47 */

  151. #define SYSCFG_SRAM2WRP_PAGE48          LL_SYSCFG_SRAM2WRP_PAGE48       /*!< SRAM2B Write protection page 48 */

  152. #define SYSCFG_SRAM2WRP_PAGE49          LL_SYSCFG_SRAM2WRP_PAGE49       /*!< SRAM2B Write protection page 49 */

  153. #define SYSCFG_SRAM2WRP_PAGE50          LL_SYSCFG_SRAM2WRP_PAGE50       /*!< SRAM2B Write protection page 50 */

  154. #define SYSCFG_SRAM2WRP_PAGE51          LL_SYSCFG_SRAM2WRP_PAGE51       /*!< SRAM2B Write protection page 51 */

  155. #define SYSCFG_SRAM2WRP_PAGE52          LL_SYSCFG_SRAM2WRP_PAGE52       /*!< SRAM2B Write protection page 52 */

  156. #define SYSCFG_SRAM2WRP_PAGE53          LL_SYSCFG_SRAM2WRP_PAGE53       /*!< SRAM2B Write protection page 53 */

  157. #define SYSCFG_SRAM2WRP_PAGE54          LL_SYSCFG_SRAM2WRP_PAGE54       /*!< SRAM2B Write protection page 54 */

  158. #define SYSCFG_SRAM2WRP_PAGE55          LL_SYSCFG_SRAM2WRP_PAGE55       /*!< SRAM2B Write protection page 55 */

  159. #define SYSCFG_SRAM2WRP_PAGE56          LL_SYSCFG_SRAM2WRP_PAGE56       /*!< SRAM2B Write protection page 56 */

  160. #define SYSCFG_SRAM2WRP_PAGE57          LL_SYSCFG_SRAM2WRP_PAGE57       /*!< SRAM2B Write protection page 57 */

  161. #define SYSCFG_SRAM2WRP_PAGE58          LL_SYSCFG_SRAM2WRP_PAGE58       /*!< SRAM2B Write protection page 58 */

  162. #define SYSCFG_SRAM2WRP_PAGE59          LL_SYSCFG_SRAM2WRP_PAGE59       /*!< SRAM2B Write protection page 59 */

  163. #define SYSCFG_SRAM2WRP_PAGE60          LL_SYSCFG_SRAM2WRP_PAGE60       /*!< SRAM2B Write protection page 60 */

  164. #define SYSCFG_SRAM2WRP_PAGE61          LL_SYSCFG_SRAM2WRP_PAGE61       /*!< SRAM2B Write protection page 61 */

  165. #define SYSCFG_SRAM2WRP_PAGE62          LL_SYSCFG_SRAM2WRP_PAGE62       /*!< SRAM2B Write protection page 62 */

  166. #define SYSCFG_SRAM2WRP_PAGE63          LL_SYSCFG_SRAM2WRP_PAGE63       /*!< SRAM2B Write protection page 63 */

  167. 

  168. /**

  169.   * @}

  170.   */

  171. 

  172. #if defined(VREFBUF)

  173. /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale

  174.   * @{

  175.   */

  176. #define SYSCFG_VREFBUF_VOLTAGE_SCALE0   LL_VREFBUF_VOLTAGE_SCALE0       /*!< Voltage reference scale 0 (VREF_OUT1) */

  177. #define SYSCFG_VREFBUF_VOLTAGE_SCALE1   LL_VREFBUF_VOLTAGE_SCALE1       /*!< Voltage reference scale 1 (VREF_OUT2) */

  178. 

  179. /**

  180.   * @}

  181.   */

  182. 

  183. /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance

  184.   * @{

  185.   */

  186. #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   0x00000000U             /*!< VREF_plus pin is internally connected to Voltage reference buffer output */

  187. #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_CSR_HIZ         /*!< VREF_plus pin is high impedance */

  188. 

  189. /**

  190.   * @}

  191.   */

  192. #endif /* VREFBUF */

  193. 

  194. /** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags

  195.   * @{

  196.   */

  197. 

  198. #define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF                /*!< SRAM2 parity error */

  199. #define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY            /*!< SRAM2 busy by erase operation */

  200. 

  201. /**

  202.   * @}

  203.   */

  204. 

  205. /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO

  206.   * @{

  207.   */

  208. 

  209. /** @brief  Fast-mode Plus driving capability on a specific GPIO

  210.   */

  211. #define SYSCFG_FASTMODEPLUS_PB6         SYSCFG_CFGR1_I2C_PB6_FMP        /*!< Enable Fast-mode Plus on PB6 */

  212. #define SYSCFG_FASTMODEPLUS_PB7         SYSCFG_CFGR1_I2C_PB7_FMP        /*!< Enable Fast-mode Plus on PB7 */

  213. #define SYSCFG_FASTMODEPLUS_PB8         SYSCFG_CFGR1_I2C_PB8_FMP        /*!< Enable Fast-mode Plus on PB8 */

  214. #define SYSCFG_FASTMODEPLUS_PB9         SYSCFG_CFGR1_I2C_PB9_FMP        /*!< Enable Fast-mode Plus on PB9 */

  215. 

  216. /**

  217.  * @}

  218.  */

  219. 

  220. /** @defgroup Secure_IP_Write_Access Secure IP Write Access

  221.   * @{

  222.   */

  223. #if defined(LL_SYSCFG_SECURE_ACCESS_AES1)

  224. #define HAL_SYSCFG_SECURE_ACCESS_AES1   LL_SYSCFG_SECURE_ACCESS_AES1    /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */

  225. #endif

  226. #define HAL_SYSCFG_SECURE_ACCESS_AES2   LL_SYSCFG_SECURE_ACCESS_AES2    /*!< Enabling the security access of Advanced Encryption Standard 2          */

  227. #define HAL_SYSCFG_SECURE_ACCESS_PKA    LL_SYSCFG_SECURE_ACCESS_PKA     /*!< Enabling the security access of Public Key Accelerator                  */

  228. #define HAL_SYSCFG_SECURE_ACCESS_RNG    LL_SYSCFG_SECURE_ACCESS_RNG     /*!< Enabling the security access of Random Number Generator                 */

  229. /**

  230.   * @}

  231.   */

  232. 

  233. /**

  234.   * @}

  235.   */

  236. 

  237. /**

  238.   * @}

  239.   */

  240. 

  241. /* Exported macros -----------------------------------------------------------*/

  242. /** @defgroup HAL_Exported_Macros HAL Exported Macros

  243.   * @{

  244.   */

  245. 

  246. /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros

  247.   * @{

  248.   */

  249. 

  250. /** @brief  Freeze and Unfreeze Peripherals in Debug mode

  251.   */

  252. 

  253. /** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP

  254.   * @{

  255.   */

  256. #if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

  257. #define __HAL_DBGMCU_FREEZE_TIM2()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

  258. #define __HAL_DBGMCU_UNFREEZE_TIM2()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

  259. #endif

  260. 

  261. #if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)

  262. #define __HAL_DBGMCU_FREEZE_RTC()               LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)

  263. #define __HAL_DBGMCU_UNFREEZE_RTC()             LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)

  264. #endif

  265. 

  266. #if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

  267. #define __HAL_DBGMCU_FREEZE_WWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

  268. #define __HAL_DBGMCU_UNFREEZE_WWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

  269. #endif

  270. 

  271. #if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

  272. #define __HAL_DBGMCU_FREEZE_IWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

  273. #define __HAL_DBGMCU_UNFREEZE_IWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

  274. #endif

  275. 

  276. #if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

  277. #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

  278. #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

  279. #endif

  280. 

  281. #if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

  282. #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

  283. #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

  284. #endif

  285. 

  286. #if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  287. #define __HAL_DBGMCU_FREEZE_LPTIM1()            LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  288. #define __HAL_DBGMCU_UNFREEZE_LPTIM1()          LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  289. #endif

  290. 

  291. #if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  292. #define __HAL_DBGMCU_FREEZE_LPTIM2()            LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  293. #define __HAL_DBGMCU_UNFREEZE_LPTIM2()          LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  294. #endif

  295. 

  296. #if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

  297. #define __HAL_DBGMCU_FREEZE_TIM1()              LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

  298. #define __HAL_DBGMCU_UNFREEZE_TIM1()            LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

  299. #endif

  300. 

  301. #if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

  302. #define __HAL_DBGMCU_FREEZE_TIM16()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

  303. #define __HAL_DBGMCU_UNFREEZE_TIM16()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

  304. #endif

  305. 

  306. #if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

  307. #define __HAL_DBGMCU_FREEZE_TIM17()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

  308. #define __HAL_DBGMCU_UNFREEZE_TIM17()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

  309. #endif

  310. 

  311. /**

  312.   * @}

  313.   */

  314. 

  315. /** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP

  316.   * @{

  317.   */

  318. #if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

  319. #define __HAL_C2_DBGMCU_FREEZE_TIM2()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

  320. #define __HAL_C2_DBGMCU_UNFREEZE_TIM2()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

  321. #endif

  322. 

  323. #if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

  324. #define __HAL_C2_DBGMCU_FREEZE_RTC()            LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

  325. #define __HAL_C2_DBGMCU_UNFREEZE_RTC()          LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

  326. #endif

  327. 

  328. #if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

  329. #define __HAL_C2_DBGMCU_FREEZE_IWDG()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

  330. #define __HAL_C2_DBGMCU_UNFREEZE_IWDG()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

  331. #endif

  332. 

  333. #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

  334. #define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

  335. #define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

  336. #endif

  337. 

  338. #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

  339. #define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

  340. #define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

  341. #endif

  342. 

  343. #if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  344. #define __HAL_C2_DBGMCU_FREEZE_LPTIM1()         LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  345. #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1()       LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

  346. #endif

  347. 

  348. #if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  349. #define __HAL_C2_DBGMCU_FREEZE_LPTIM2()         LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  350. #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2()       LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

  351. #endif

  352. 

  353. #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

  354. #define __HAL_C2_DBGMCU_FREEZE_TIM1()           LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

  355. #define __HAL_C2_DBGMCU_UNFREEZE_TIM1()         LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

  356. #endif

  357. 

  358. #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

  359. #define __HAL_C2_DBGMCU_FREEZE_TIM16()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

  360. #define __HAL_C2_DBGMCU_UNFREEZE_TIM16()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

  361. #endif

  362. 

  363. #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

  364. #define __HAL_C2_DBGMCU_FREEZE_TIM17()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

  365. #define __HAL_C2_DBGMCU_UNFREEZE_TIM17()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

  366. #endif

  367. 

  368. /**

  369.   * @}

  370.   */

  371. 

  372. /**

  373.   * @}

  374.   */

  375. 

  376. /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros

  377.   * @{

  378.   */

  379. 

  380. /** @brief  Main Flash memory mapped at 0x00000000

  381.   */

  382. #define __HAL_SYSCFG_REMAPMEMORY_FLASH()        LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)

  383. 

  384. /** @brief  System Flash memory mapped at 0x00000000

  385.   */

  386. #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()  LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)

  387. 

  388. /** @brief  Embedded SRAM mapped at 0x00000000

  389.   */

  390. #define __HAL_SYSCFG_REMAPMEMORY_SRAM()         LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)

  391. 

  392. #if defined(LL_SYSCFG_REMAP_QUADSPI)

  393. /** @brief  QUADSPI mapped at 0x00000000.

  394.   */

  395. #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()      LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)

  396. #endif

  397. 

  398. /**

  399.   * @brief  Return the boot mode as configured by user.

  400.   * @retval The boot mode as configured by user. The returned value can be one

  401.   *         of the following values:

  402.   *           @arg @ref SYSCFG_BOOT_MAINFLASH

  403.   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH

  404.   *           @arg @ref SYSCFG_BOOT_SRAM

  405. #if defined(LL_SYSCFG_REMAP_QUADSPI)

  406.   *           @arg @ref SYSCFG_BOOT_QUADSPI

  407. #endif

  408.   */

  409. #define __HAL_SYSCFG_GET_BOOT_MODE()            LL_SYSCFG_GetRemapMemory()

  410. 

  411. /** @brief  SRAM2 page 0 to 31 write protection enable macro

  412.   * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP

  413.   * @note   Write protection can only be disabled by a system reset

  414.   */

  415. /* Legacy define */

  416. #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE      __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE

  417. #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\

  418.                                                                 LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\

  419.                                                             }while(0)

  420. 

  421. /** @brief  SRAM2 page 32 to 63 write protection enable macro

  422.   * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63

  423.   * @note   Write protection can only be disabled by a system reset

  424.   */

  425. #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\

  426.                                                                 LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\

  427.                                                             }while(0)

  428. 

  429. /** @brief  SRAM2 page write protection unlock prior to erase

  430.   * @note   Writing a wrong key reactivates the write protection

  431.   */

  432. #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()         LL_SYSCFG_UnlockSRAM2WRP()

  433. 

  434. /** @brief  SRAM2 erase

  435.   * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase

  436.   */

  437. #define __HAL_SYSCFG_SRAM2_ERASE()              LL_SYSCFG_EnableSRAM2Erase()

  438. 

  439. /** @brief  Floating Point Unit interrupt enable/disable macros

  440.   * @param __INTERRUPT__  This parameter can be a value of @ref SYSCFG_FPU_Interrupts

  441.   */

  442. #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\

  443.                                                                 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\

  444.                                                             }while(0)

  445. 

  446. #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\

  447.                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\

  448.                                                             }while(0)

  449. 

  450. /** @brief  SYSCFG Break ECC lock.

  451.   *         Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.

  452.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  453.   */

  454. #define __HAL_SYSCFG_BREAK_ECC_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)

  455. 

  456. /** @brief  SYSCFG Break Cortex-M4 Lockup lock.

  457.   *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input.

  458.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  459.   */

  460. #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()        LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)

  461. 

  462. /** @brief  SYSCFG Break PVD lock.

  463.   *         Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

  464.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  465.   */

  466. #define __HAL_SYSCFG_BREAK_PVD_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)

  467. 

  468. /** @brief  SYSCFG Break SRAM2 parity lock.

  469.   *         Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input.

  470.   * @note   The selected configuration is locked and can be unlocked by system reset.

  471.   */

  472. #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()   LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)

  473. 

  474. /** @brief  Check SYSCFG flag is set or not.

  475.   * @param  __FLAG__  specifies the flag to check.

  476.   *         This parameter can be one of the following values:

  477.   *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag

  478.   *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing

  479.   * @retval The new state of __FLAG__ (TRUE or FALSE).

  480.   */

  481. #define __HAL_SYSCFG_GET_FLAG(__FLAG__)         ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)

  482. 

  483. /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.

  484.   */

  485. #define __HAL_SYSCFG_CLEAR_FLAG()               LL_SYSCFG_ClearFlag_SP()

  486. 

  487. /** @brief  Fast mode Plus driving capability enable/disable macros

  488.   * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO

  489.   */

  490. #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \

  491.                                                                 LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__);           \

  492.                                                                }while(0)

  493. 

  494. #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \

  495.                                                                 LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__);          \

  496.                                                                }while(0)

  497. 

  498. /**

  499.   * @}

  500.   */

  501. 

  502. /**

  503.   * @}

  504.   */

  505. 

  506. /* Private macros ------------------------------------------------------------*/

  507. /** @defgroup HAL_Private_Macros HAL Private Macros

  508.   * @{

  509.   */

  510. 

  511. /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros

  512.   * @{

  513.   */

  514. 

  515. #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)          ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \

  516.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \

  517.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \

  518.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \

  519.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \

  520.                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))

  521. 

  522. #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)               (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))

  523. 

  524. #if defined(VREFBUF)

  525. #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)      (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \

  526.                                                          ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))

  527. 

  528. #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)     (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \

  529.                                                          ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

  530. 

  531. #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)           (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

  532. #endif

  533. 

  534. #define IS_SYSCFG_FASTMODEPLUS(__PIN__)                 ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \

  535.                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \

  536.                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \

  537.                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))

  538. 

  539. #if defined(LL_SYSCFG_SECURE_ACCESS_AES1)

  540. #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__)            ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1)  == HAL_SYSCFG_SECURE_ACCESS_AES1)  || \

  541.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2)  == HAL_SYSCFG_SECURE_ACCESS_AES2)  || \

  542.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA)   == HAL_SYSCFG_SECURE_ACCESS_PKA)   || \

  543.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG)   == HAL_SYSCFG_SECURE_ACCESS_RNG))

  544. #else

  545. #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__)            ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2)  == HAL_SYSCFG_SECURE_ACCESS_AES2)  || \

  546.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA)   == HAL_SYSCFG_SECURE_ACCESS_PKA)   || \

  547.                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG)   == HAL_SYSCFG_SECURE_ACCESS_RNG))

  548. #endif

  549. 

  550. /**

  551.   * @}

  552.   */

  553. 

  554. /**

  555.   * @}

  556.   */

  557. 

  558. /** @defgroup HAL_Private_Macros HAL Private Macros

  559.   * @{

  560.   */

  561. #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \

  562.                            ((FREQ) == HAL_TICK_FREQ_100HZ) || \

  563.                            ((FREQ) == HAL_TICK_FREQ_1KHZ))

  564. /**

  565.   * @}

  566.   */

  567. 

  568. 

  569. /* Exported functions --------------------------------------------------------*/

  570. 

  571. /** @defgroup HAL_Exported_Functions HAL Exported Functions

  572.   * @{

  573.   */

  574. 

  575. /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions

  576.   * @{

  577.   */

  578. 

  579. /* Initialization and Configuration functions  ******************************/

  580. HAL_StatusTypeDef HAL_Init(void);

  581. HAL_StatusTypeDef HAL_DeInit(void);

  582. void HAL_MspInit(void);

  583. void HAL_MspDeInit(void);

  584. 

  585. HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);

  586. 

  587. /**

  588.   * @}

  589.   */

  590. 

  591. /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions

  592.   * @{

  593.   */

  594. 

  595. /* Peripheral Control functions  ************************************************/

  596. void HAL_IncTick(void);

  597. void HAL_Delay(uint32_t Delay);

  598. uint32_t HAL_GetTick(void);

  599. uint32_t HAL_GetTickPrio(void);

  600. HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);

  601. HAL_TickFreqTypeDef HAL_GetTickFreq(void);

  602. void HAL_SuspendTick(void);

  603. void HAL_ResumeTick(void);

  604. uint32_t HAL_GetHalVersion(void);

  605. uint32_t HAL_GetREVID(void);

  606. uint32_t HAL_GetDEVID(void);

  607. uint32_t HAL_GetUIDw0(void);

  608. uint32_t HAL_GetUIDw1(void);

  609. uint32_t HAL_GetUIDw2(void);

  610. 

  611. /**

  612.   * @}

  613.   */

  614. 

  615. /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions

  616.   * @{

  617.   */

  618. 

  619. /* DBGMCU Peripheral Control functions  *****************************************/

  620. void HAL_DBGMCU_EnableDBGSleepMode(void);

  621. void HAL_DBGMCU_DisableDBGSleepMode(void);

  622. void HAL_DBGMCU_EnableDBGStopMode(void);

  623. void HAL_DBGMCU_DisableDBGStopMode(void);

  624. void HAL_DBGMCU_EnableDBGStandbyMode(void);

  625. void HAL_DBGMCU_DisableDBGStandbyMode(void);

  626. /**

  627.   * @}

  628.   */

  629. 

  630. /* Exported variables ---------------------------------------------------------*/

  631. /** @addtogroup HAL_Exported_Variables

  632.   * @{

  633.   */

  634. extern __IO uint32_t uwTick;

  635. extern uint32_t uwTickPrio;

  636. extern HAL_TickFreqTypeDef uwTickFreq;

  637. /**

  638.   * @}

  639.   */

  640. 

  641. /** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions

  642.   * @{

  643.   */

  644. 

  645. /* SYSCFG Control functions  ****************************************************/

  646. void HAL_SYSCFG_SRAM2Erase(void);

  647. void HAL_SYSCFG_DisableSRAMFetch(void);

  648. uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void);

  649. 

  650. #if defined(VREFBUF)

  651. void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);

  652. void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);

  653. void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);

  654. HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);

  655. void HAL_SYSCFG_DisableVREFBUF(void);

  656. #endif

  657. 

  658. void HAL_SYSCFG_EnableIOBooster(void);

  659. void HAL_SYSCFG_DisableIOBooster(void);

  660. void HAL_SYSCFG_EnableIOVdd(void);

  661. void HAL_SYSCFG_DisableIOVdd(void);

  662. 

  663. void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess);

  664. void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess);

  665. uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess);

  666. 

  667. /**

  668.   * @}

  669.   */

  670. 

  671. /**

  672.   * @}

  673.   */

  674. 

  675. /**

  676.   * @}

  677.   */

  678. 

  679. /**

  680.   * @}

  681.   */

  682. 

  683. #ifdef __cplusplus

  684. }

  685. #endif

  686. 

  687. #endif /* STM32WBxx_HAL_H */

  688. 

  689. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/