---<<BOOT>>---
KDB: debugger backends: ddb
KDB: current backend: ddb
Copyright (c) 1992-2020 The FreeBSD Project.
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        The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 13.0-CURRENT #0 r361019: Thu May 14 04:50:42 UTC 2020
    root@releng1.nyi.freebsd.org:/usr/obj/usr/src/arm.armv7/sys/GENERIC arm
FreeBSD clang version 10.0.0 (git@github.com:llvm/llvm-project.git llvmorg-10.0.0-0-gd32170dbd5b)
WARNING: WITNESS option enabled, expect reduced performance.
VT: init without driver.
No PSCI/SMCCC call function found
CPU: ARM Cortex-A9 r3p0 (ECO: 0x00000000)
CPU Features: 
  Multiprocessing, Thumb2, Security, VMSAv7, Coherent Walk
Optional instructions: 
  UMULL, SMULL, SIMD(ext)
LoUU:2 LoC:2 LoUIS:2 
Cache level 1:
 32KB/32B 4-way data cache WB Read-Alloc Write-Alloc
 32KB/32B 4-way instruction cache Read-Alloc
real memory  = 536526848 (511 MB)
avail memory = 506220544 (482 MB)
arc4random: WARNING: initial seeding bypassed the cryptographic random device because it was not yet seeded and the knob 'bypass_before_seeding' was enabled.
random: entropy device external interface
WARNING: Device "openfirm" is Giant locked and may be deleted before FreeBSD 13.0.
WARNING: Device "kbd" is Giant locked and may be deleted before FreeBSD 13.0.
kbd0 at kbdmux0
ofwbus0: <Open Firmware Device Tree>
simplebus0: <Flattened device tree simple bus> on ofwbus0
simplebus1: <Flattened device tree simple bus> on ofwbus0
l2cache0: <PL310 L2 cache controller> mem 0xf02000-0xf02fff irq 0 on simplebus0
l2cache0: cannot allocate IRQ, not using interrupt
l2cache0: Part number: 0x3, release: 0x8
l2cache0: L2 Cache enabled: 512KB/32B 8 ways
gic0: <ARM Generic Interrupt Controller> mem 0xf01000-0xf01fff,0xf00100-0xf001ff on simplebus0
gic0: pn 0x39, arch 0x1, rev 0x2, implementer 0x43b irqs 96
mp_tmr0: <ARM MPCore Timers> mem 0xf00200-0xf002ff,0xf00600-0xf0061f irq 2,3 on simplebus0
Timecounter "MPCore" frequency 50000000 Hz quality 800
Event timer "MPCore" frequency 50000000 Hz quality 1000
zy7_slcr0: <Zynq-7000 slcr block> mem 0-0xfff on simplebus0
zy7_devcfg0: <Zynq devcfg block> mem 0x7000-0x7fff irq 1 on simplebus0
uart0: <Cadence UART> mem 0-0xfff irq 6 on simplebus1
uart0: console (-1,n,8,1)
ehci0: <Zynq-7000 EHCI USB 2.0 controller> mem 0x2000-0x2fff irq 8 on simplebus1
usbus0: EHCI version 1.0
usbus0: stop timeout
usbus0 on ehci0
gpio0: <Zynq-7000 GPIO driver> mem 0xa000-0xafff irq 10 on simplebus1
gpiobus0: <GPIO bus> on gpio0
gpioc0: <GPIO controller> on gpio0
cgem0: <Cadence CGEM Gigabit Ethernet Interface> mem 0xb000-0xbfff irq 11 on simplebus1
miibus0: <MII bus> on cgem0
rgephy0: <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 0 on miibus0
rgephy0:  none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, 1000baseT-FDX-master, auto
rgephy1: <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 1 on miibus0
rgephy1:  none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, 1000baseT-FDX-master, auto
cgem0: Ethernet address: 00:18:3e:03:42:45
sdhci_fdt0: <Zynq-7000 generic fdt SDHCI controller> mem 0x100000-0x100fff irq 16 on simplebus1
sdhci_fdt0: 1 slot(s) allocated
mmc0: <MMC/SD bus> on sdhci_fdt0
cryptosoft0: <software crypto>
Timecounters tick every 1.000 msec
usbus0: 480Mbps High Speed USB v2.0
Obsolete code will be removed soon: random(9) is the obsolete Park-Miller LCG from 1988
ugen0.1: <Xilinx EHCI root HUB> at usbus0
uhub0 on usbus0
uhub0: <Xilinx EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus0
mmcsd0: 16GB <SDHC SC16G 8.0 SN 7C723DFC MFG 04/2018 by 3 SD> at mmc0 50.0MHz/4bit/65535-block
WARNING: WITNESS option enabled, expect reduced performance.
Trying to mount root from ufs:/dev/ufs/rootfs [rw]...
uhub0: 1 port with 1 removable, self powered
Warning: no time-of-day clock registered, system time will not be set accurately
random: unblocking device.
lo0: link state changed to UP
cgem0: link state changed to DOWN
cgem0: cgem_mediachange: could not set ref clk0 to 125000000.
cgem0: link state changed to UP