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add first test getting techmap working.. workings fine w/ yosys 0.9

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John-Mark Gurney 7 months ago
commit
92905c647f
8 changed files with 182 additions and 0 deletions
  1. +2
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      .gitignore
  2. +11
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      NOTES.md
  3. +3
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      cmds.txt
  4. +99
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      factorsynio.lib
  5. +29
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      factorsyniomap.v
  6. +0
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      requirements.txt
  7. +33
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      script.ys
  8. +5
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      testmod.v

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.gitignore View File

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p
synth.*

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NOTES.md View File

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has half and full adder:
yosys/tests/liberty/normal.lib

https://people.eecs.berkeley.edu/~alanmi/publications/other/liberty13_03.pdf

use techmap to use the functions

blueprint with max pack combiners around small poll (maybe do other ones for substation and medium poll?)

has three other max spaced polls for reference, and a large one off to the side also for reference also has a few functions programed for reference.
0eNrFmFGPlDAQx7/LPBo427KAx9vp6aMmJuqpMRvYrXdNgJJSNm42/e627OZWWfDsROFpA+38++9vmZnCAYqy440StYbsAGIj6xayrwdoxX2dl+6e3jccMhCaVxBAnVfuKldCP1Rci024kVUh6lxLBSYAUW/5D8io+RYAr7XQgh8F+4v9uu6qgis74VGqrfKyDHnJN1pZuUaW3K7TyNbGyto5sHokgD1kYWJMcCHF/KTSP0hFT2zwQixkV/FRj9rNb4WyS/ej1pRlqZUs1wV/yHfCRtuQs+zaDm97qdYNfBeq1esL6juhdGfvnLfYzwiJY91yp/H3QV9ckGy4yo8e4ZmdIjvddB4r34AxY+hW3ujoCdxV/Du6lSe6Ewb36OrcPcdkuMtRw7Gv4YX9Jr5+ybJ+U1+/bFm/L9C5T2ZNfYpJ/c/D1H+OSP2XE6l/jSY3b9FkGHJ3Q3IhgtyrCXKUIKsm6ZPkf8KKMbA+DGHdvXuPwPVmChfF1eylSgpl3jX735QUrN8Icyqjo1Le5wG27NZjrF+6jN8Ec+od/6tSdP2OZq3fK0xJ+jgsSaiK9HqqIuFPDWxWdhGG3achu5u3twh4t1Pw/A8OZBxeMk/SMWy7jvzbNdYiskXO6JDhXmRmdBhhewFbpBewFe5Va0ai5+5aiPunelUYn3DaX+M+JPXfnrJfPlUFsOOq7SPSiNDrhNEoTYz5Ca/3hLU=

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cmds.txt View File

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ls * | ~/src/eradman-entr-c15b0be493fc/entr sh -c '~/github/yosys/yosys -s script.ys'

python -c 'import sys; import pprint; import json; import zlib; pprint.pprint(json.loads(zlib.decompress(sys.stdin.read()[1:].decode("base64"))))'

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factorsynio.lib View File

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// test comment
/* test comment */
library(demo) {
type (bus4) {
base_type : array;
data_type : bit;
bit_width : 4;
bit_from : 0;
bit_to : 3;
}
cell(BUF) {
area: 2;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: "A"; }
}
cell(NOT) {
area: 2;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: "A'"; }
}
cell(XOR) {
area: 100;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A^B)"; }
}
// not used, see -g option of abc http://www.clifford.at/yosys/cmd_abc.html
cell(XORDUAL) {
area: 2;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(C) { direction: input; }
pin(D) { direction: input; }
pin(Y) { direction: output;
function: "(A^B)"; }
pin(Z) { direction: output;
function: "(C^D)"; }
}
cell(XOR2) {
area: 2;
bus(I1) {
bus_type : bus4;
direction : input;
}
bus(I2) {
bus_type : bus4;
direction : input;
}
bus(Y) {
bus_type : bus4;
direction : output;
pin (Y[0:3]) {
function: "(I1^I2)";
}
}
}
cell(NAND) {
area: 2;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A*B)'"; }
}
cell(NOR) {
area: 2;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A+B)'"; }
}
cell(DFF) {
area: 2;
ff(IQ, IQN) { clocked_on: C;
next_state: D; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
}
cell(DFFSR) {
area: 2;
ff("IQ", "IQN") { clocked_on: C;
next_state: D;
preset: S;
clear: R; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(S) { direction: input; }
pin(R) { direction: input; }
; // empty statement
}
}

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factorsyniomap.v View File

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(* techmap_cellteype = "$mul" *)
module $mul(A, B, Y);

parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 4;
parameter B_WIDTH = 4;
parameter Y_WIDTH = 4;

input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;


foobar #(
.A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED),
.A_WIDTH(B_WIDTH),
.B_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_.baz (
.A(B),
.B(A),
.Y(Y)
);
wire [1023:0] _TECHMAP_DO_00 = "log fklj;;";
wire _TECHMAP_FAIL_ = 0;

endmodule

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requirements.txt View File


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script.ys View File

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# read design
read_verilog testmod.v

# from pdf docs, page 26
proc
opt
memory
opt
#techmap
techmap -map factorsyniomap.v
opt
dfflibmap -liberty factorsynio.lib
abc -liberty factorsynio.lib

opt

##### from sample some where
# generic synthesis
#synth -top top #-noalumacc

#techmap -map factorsyniomap.v

# mapping to mycells.lib
#dfflibmap -liberty ../../git/factorsynio/factorsynio.lib
#abc -liberty ../../git/factorsynio/factorsynio.lib
#abc

#clean

# write synthesized design
write_verilog synth.v
write_ilang synth.ilang
write_json synth.json

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testmod.v View File

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module top (output reg [3:0] out, input clk, input [3:0] a, input [3:0] b, input [3:0] c);
always @(posedge clk) begin
out <= (a * b) + c + (10 + 12);
end
endmodule

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